target/linux/sunxi/patches-4.4/130-pinctrl-sunxi-add-h3-pio.patch

   1 From 03b83828e452418c18ba506e3e02b5deadbb53fa Mon Sep 17 00:00:00 2001
   2 From: Jens Kuske <jenskuske@gmail.com>
   3 Date: Tue, 27 Oct 2015 17:50:23 +0100
   4 Subject: [PATCH] pinctrl: sunxi: Add H3 PIO controller support
   5
   6 The H3 uses the same pin controller as previous SoC's from Allwinner.
   7 Add support for the pins controlled by the main PIO controller.
   8
   9 Signed-off-by: Jens Kuske <jenskuske@gmail.com>
  10 Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt   |   1 +
  13  drivers/pinctrl/sunxi/Kconfig                      |   4 +
  14  drivers/pinctrl/sunxi/Makefile                     |   1 +
  15  drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c           | 516 +++++++++++++++++++++
  16  4 files changed, 522 insertions(+)
  17  create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
  18
  19 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
  20 +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
  21 @@ -18,6 +18,7 @@ Required properties:
  22    "allwinner,sun8i-a23-r-pinctrl"
  23    "allwinner,sun8i-a33-pinctrl"
  24    "allwinner,sun8i-a83t-pinctrl"
  25 +  "allwinner,sun8i-h3-pinctrl"
  26
  27  - reg: Should contain the register physical address and length for the
  28    pin controller.
  29 --- a/drivers/pinctrl/sunxi/Kconfig
  30 +++ b/drivers/pinctrl/sunxi/Kconfig
  31 @@ -51,6 +51,10 @@ config PINCTRL_SUN8I_A23_R
  32         depends on RESET_CONTROLLER
  33         select PINCTRL_SUNXI_COMMON
  34
  35 +config PINCTRL_SUN8I_H3
  36 +       def_bool MACH_SUN8I
  37 +       select PINCTRL_SUNXI_COMMON
  38 +
  39  config PINCTRL_SUN9I_A80
  40         def_bool MACH_SUN9I
  41         select PINCTRL_SUNXI_COMMON
  42 --- a/drivers/pinctrl/sunxi/Makefile
  43 +++ b/drivers/pinctrl/sunxi/Makefile
  44 @@ -13,4 +13,5 @@ obj-$(CONFIG_PINCTRL_SUN8I_A23)               += pinc
  45  obj-$(CONFIG_PINCTRL_SUN8I_A23_R)      += pinctrl-sun8i-a23-r.o
  46  obj-$(CONFIG_PINCTRL_SUN8I_A33)                += pinctrl-sun8i-a33.o
  47  obj-$(CONFIG_PINCTRL_SUN8I_A83T)       += pinctrl-sun8i-a83t.o
  48 +obj-$(CONFIG_PINCTRL_SUN8I_H3)         += pinctrl-sun8i-h3.o
  49  obj-$(CONFIG_PINCTRL_SUN9I_A80)                += pinctrl-sun9i-a80.o
  50 --- /dev/null
  51 +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-h3.c
  52 @@ -0,0 +1,516 @@
  53 +/*
  54 + * Allwinner H3 SoCs pinctrl driver.
  55 + *
  56 + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  57 + *
  58 + * Based on pinctrl-sun8i-a23.c, which is:
  59 + * Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
  60 + * Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
  61 + *
  62 + * This file is licensed under the terms of the GNU General Public
  63 + * License version 2.  This program is licensed "as is" without any
  64 + * warranty of any kind, whether express or implied.
  65 + */
  66 +
  67 +#include <linux/module.h>
  68 +#include <linux/platform_device.h>
  69 +#include <linux/of.h>
  70 +#include <linux/of_device.h>
  71 +#include <linux/pinctrl/pinctrl.h>
  72 +
  73 +#include "pinctrl-sunxi.h"
  74 +
  75 +static const struct sunxi_desc_pin sun8i_h3_pins[] = {
  76 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
  77 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
  78 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
  79 +                 SUNXI_FUNCTION(0x2, "uart2"),         /* TX */
  80 +                 SUNXI_FUNCTION(0x3, "jtag"),          /* MS */
  81 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)),  /* PA_EINT0 */
  82 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
  83 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
  84 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
  85 +                 SUNXI_FUNCTION(0x2, "uart2"),         /* RX */
  86 +                 SUNXI_FUNCTION(0x3, "jtag"),          /* CK */
  87 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)),  /* PA_EINT1 */
  88 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
  89 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
  90 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
  91 +                 SUNXI_FUNCTION(0x2, "uart2"),         /* RTS */
  92 +                 SUNXI_FUNCTION(0x3, "jtag"),          /* DO */
  93 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)),  /* PA_EINT2 */
  94 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
  95 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
  96 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
  97 +                 SUNXI_FUNCTION(0x2, "uart2"),         /* CTS */
  98 +                 SUNXI_FUNCTION(0x3, "jtag"),          /* DI */
  99 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)),  /* PA_EINT3 */
 100 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
 101 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 102 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 103 +                 SUNXI_FUNCTION(0x2, "uart0"),         /* TX */
 104 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)),  /* PA_EINT4 */
 105 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
 106 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 107 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 108 +                 SUNXI_FUNCTION(0x2, "uart0"),         /* RX */
 109 +                 SUNXI_FUNCTION(0x3, "pwm0"),
 110 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)),  /* PA_EINT5 */
 111 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
 112 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 113 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 114 +                 SUNXI_FUNCTION(0x2, "sim"),           /* PWREN */
 115 +                 SUNXI_FUNCTION(0x3, "pwm1"),
 116 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)),  /* PA_EINT6 */
 117 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
 118 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 119 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 120 +                 SUNXI_FUNCTION(0x2, "sim"),           /* CLK */
 121 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)),  /* PA_EINT7 */
 122 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
 123 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 124 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 125 +                 SUNXI_FUNCTION(0x2, "sim"),           /* DATA */
 126 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)),  /* PA_EINT8 */
 127 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
 128 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 129 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 130 +                 SUNXI_FUNCTION(0x2, "sim"),           /* RST */
 131 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)),  /* PA_EINT9 */
 132 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
 133 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 134 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 135 +                 SUNXI_FUNCTION(0x2, "sim"),           /* DET */
 136 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
 137 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
 138 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 139 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 140 +                 SUNXI_FUNCTION(0x2, "i2c0"),          /* SCK */
 141 +                 SUNXI_FUNCTION(0x3, "di"),            /* TX */
 142 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
 143 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
 144 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 145 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 146 +                 SUNXI_FUNCTION(0x2, "i2c0"),          /* SDA */
 147 +                 SUNXI_FUNCTION(0x3, "di"),            /* RX */
 148 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
 149 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
 150 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 151 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 152 +                 SUNXI_FUNCTION(0x2, "spi1"),          /* CS */
 153 +                 SUNXI_FUNCTION(0x3, "uart3"),         /* TX */
 154 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
 155 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
 156 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 157 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 158 +                 SUNXI_FUNCTION(0x2, "spi1"),          /* CLK */
 159 +                 SUNXI_FUNCTION(0x3, "uart3"),         /* RX */
 160 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
 161 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
 162 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 163 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 164 +                 SUNXI_FUNCTION(0x2, "spi1"),          /* MOSI */
 165 +                 SUNXI_FUNCTION(0x3, "uart3"),         /* RTS */
 166 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
 167 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
 168 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 169 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 170 +                 SUNXI_FUNCTION(0x2, "spi1"),          /* MISO */
 171 +                 SUNXI_FUNCTION(0x3, "uart3"),         /* CTS */
 172 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
 173 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
 174 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 175 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 176 +                 SUNXI_FUNCTION(0x2, "spdif"),         /* OUT */
 177 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
 178 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
 179 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 180 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 181 +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* SYNC */
 182 +                 SUNXI_FUNCTION(0x3, "i2c1"),          /* SCK */
 183 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
 184 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
 185 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 186 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 187 +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* CLK */
 188 +                 SUNXI_FUNCTION(0x3, "i2c1"),          /* SDA */
 189 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
 190 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
 191 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 192 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 193 +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* DOUT */
 194 +                 SUNXI_FUNCTION(0x3, "sim"),           /* VPPEN */
 195 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
 196 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
 197 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 198 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 199 +                 SUNXI_FUNCTION(0x2, "i2s0"),          /* DIN */
 200 +                 SUNXI_FUNCTION(0x3, "sim"),           /* VPPPP */
 201 +                 SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
 202 +       /* Hole */
 203 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
 204 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 205 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 206 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* WE */
 207 +                 SUNXI_FUNCTION(0x3, "spi0")),         /* MOSI */
 208 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
 209 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 210 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 211 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* ALE */
 212 +                 SUNXI_FUNCTION(0x3, "spi0")),         /* MISO */
 213 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
 214 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 215 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 216 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* CLE */
 217 +                 SUNXI_FUNCTION(0x3, "spi0")),         /* CLK */
 218 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
 219 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 220 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 221 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* CE1 */
 222 +                 SUNXI_FUNCTION(0x3, "spi0")),         /* CS */
 223 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
 224 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 225 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 226 +                 SUNXI_FUNCTION(0x2, "nand0")),        /* CE0 */
 227 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
 228 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 229 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 230 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* RE */
 231 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* CLK */
 232 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
 233 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 234 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 235 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* RB0 */
 236 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* CMD */
 237 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
 238 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 239 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 240 +                 SUNXI_FUNCTION(0x2, "nand0")),        /* RB1 */
 241 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
 242 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 243 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 244 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ0 */
 245 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D0 */
 246 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
 247 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 248 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 249 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ1 */
 250 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D1 */
 251 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
 252 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 253 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 254 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ2 */
 255 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D2 */
 256 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
 257 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 258 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 259 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ3 */
 260 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D3 */
 261 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
 262 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 263 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 264 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ4 */
 265 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D4 */
 266 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
 267 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 268 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 269 +                 SUNXI_FUNCTION(0x2, "nand0"),         /* DQ5 */
 270 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D5 */
 271 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
 272 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 273 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 274 +                 SUNXI_FUNCTION(0x2, "nand"),          /* DQ6 */
 275 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D6 */
 276 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
 277 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 278 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 279 +                 SUNXI_FUNCTION(0x2, "nand"),          /* DQ7 */
 280 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* D7 */
 281 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
 282 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 283 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 284 +                 SUNXI_FUNCTION(0x2, "nand"),          /* DQS */
 285 +                 SUNXI_FUNCTION(0x3, "mmc2")),         /* RST */
 286 +       /* Hole */
 287 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
 288 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 289 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 290 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXD3 */
 291 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
 292 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 293 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 294 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXD2 */
 295 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
 296 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 297 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 298 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXD1 */
 299 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
 300 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 301 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 302 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXD0 */
 303 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
 304 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 305 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 306 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXCK */
 307 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
 308 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 309 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 310 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXCTL/RCDV */
 311 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
 312 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 313 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 314 +                 SUNXI_FUNCTION(0x2, "emac")),         /* RXERR */
 315 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
 316 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 317 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 318 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXD3 */
 319 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
 320 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 321 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 322 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXD2L */
 323 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
 324 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 325 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 326 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXD1 */
 327 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
 328 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 329 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 330 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXD0 */
 331 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
 332 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 333 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 334 +                 SUNXI_FUNCTION(0x2, "emac")),         /* CRS */
 335 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
 336 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 337 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 338 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXCK */
 339 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
 340 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 341 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 342 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXCTL/TXEN */
 343 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
 344 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 345 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 346 +                 SUNXI_FUNCTION(0x2, "emac")),         /* TXERR */
 347 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
 348 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 349 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 350 +                 SUNXI_FUNCTION(0x2, "emac")),         /* CLKIN/COL */
 351 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
 352 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 353 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 354 +                 SUNXI_FUNCTION(0x2, "emac")),         /* MDC */
 355 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
 356 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 357 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 358 +                 SUNXI_FUNCTION(0x2, "emac")),         /* MDIO */
 359 +       /* Hole */
 360 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
 361 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 362 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 363 +                 SUNXI_FUNCTION(0x2, "csi"),           /* PCLK */
 364 +                 SUNXI_FUNCTION(0x3, "ts")),           /* CLK */
 365 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
 366 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 367 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 368 +                 SUNXI_FUNCTION(0x2, "csi"),           /* MCLK */
 369 +                 SUNXI_FUNCTION(0x3, "ts")),           /* ERR */
 370 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
 371 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 372 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 373 +                 SUNXI_FUNCTION(0x2, "csi"),           /* HSYNC */
 374 +                 SUNXI_FUNCTION(0x3, "ts")),           /* SYNC */
 375 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
 376 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 377 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 378 +                 SUNXI_FUNCTION(0x2, "csi"),           /* VSYNC */
 379 +                 SUNXI_FUNCTION(0x3, "ts")),           /* DVLD */
 380 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
 381 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 382 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 383 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D0 */
 384 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D0 */
 385 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
 386 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 387 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 388 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D1 */
 389 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D1 */
 390 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
 391 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 392 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 393 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D2 */
 394 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D2 */
 395 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
 396 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 397 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 398 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D3 */
 399 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D3 */
 400 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
 401 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 402 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 403 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D4 */
 404 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D4 */
 405 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
 406 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 407 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 408 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D5 */
 409 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D5 */
 410 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
 411 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 412 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 413 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D6 */
 414 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D6 */
 415 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
 416 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 417 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 418 +                 SUNXI_FUNCTION(0x2, "csi"),           /* D7 */
 419 +                 SUNXI_FUNCTION(0x3, "ts")),           /* D7 */
 420 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
 421 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 422 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 423 +                 SUNXI_FUNCTION(0x2, "csi"),           /* SCK */
 424 +                 SUNXI_FUNCTION(0x3, "i2c2")),         /* SCK */
 425 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
 426 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 427 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 428 +                 SUNXI_FUNCTION(0x2, "csi"),           /* SDA */
 429 +                 SUNXI_FUNCTION(0x3, "i2c2")),         /* SDA */
 430 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
 431 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 432 +                 SUNXI_FUNCTION(0x1, "gpio_out")),
 433 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
 434 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 435 +                 SUNXI_FUNCTION(0x1, "gpio_out")),
 436 +       /* Hole */
 437 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
 438 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 439 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 440 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D1 */
 441 +                 SUNXI_FUNCTION(0x3, "jtag")),         /* MS */
 442 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
 443 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 444 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 445 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D0 */
 446 +                 SUNXI_FUNCTION(0x3, "jtag")),         /* DI */
 447 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
 448 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 449 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 450 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* CLK */
 451 +                 SUNXI_FUNCTION(0x3, "uart0")),        /* TX */
 452 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
 453 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 454 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 455 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* CMD */
 456 +                 SUNXI_FUNCTION(0x3, "jtag")),         /* DO */
 457 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
 458 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 459 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 460 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D3 */
 461 +                 SUNXI_FUNCTION(0x3, "uart0")),        /* RX */
 462 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
 463 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 464 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 465 +                 SUNXI_FUNCTION(0x2, "mmc0"),          /* D2 */
 466 +                 SUNXI_FUNCTION(0x3, "jtag")),         /* CK */
 467 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
 468 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 469 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 470 +                 SUNXI_FUNCTION(0x2, "mmc0")),         /* DET */
 471 +       /* Hole */
 472 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
 473 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 474 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 475 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* CLK */
 476 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 0)),  /* PG_EINT0 */
 477 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
 478 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 479 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 480 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* CMD */
 481 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 1)),  /* PG_EINT1 */
 482 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
 483 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 484 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 485 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D0 */
 486 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 2)),  /* PG_EINT2 */
 487 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
 488 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 489 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 490 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D1 */
 491 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 3)),  /* PG_EINT3 */
 492 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
 493 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 494 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 495 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D2 */
 496 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 4)),  /* PG_EINT4 */
 497 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
 498 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 499 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 500 +                 SUNXI_FUNCTION(0x2, "mmc1"),          /* D3 */
 501 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 5)),  /* PG_EINT5 */
 502 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
 503 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 504 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 505 +                 SUNXI_FUNCTION(0x2, "uart1"),         /* TX */
 506 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 6)),  /* PG_EINT6 */
 507 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
 508 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 509 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 510 +                 SUNXI_FUNCTION(0x2, "uart1"),         /* RX */
 511 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 7)),  /* PG_EINT7 */
 512 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
 513 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 514 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 515 +                 SUNXI_FUNCTION(0x2, "uart1"),         /* RTS */
 516 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 8)),  /* PG_EINT8 */
 517 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
 518 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 519 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 520 +                 SUNXI_FUNCTION(0x2, "uart1"),         /* CTS */
 521 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 9)),  /* PG_EINT9 */
 522 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
 523 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 524 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 525 +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* SYNC */
 526 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 10)), /* PG_EINT10 */
 527 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
 528 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 529 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 530 +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* CLK */
 531 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 11)), /* PG_EINT11 */
 532 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
 533 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 534 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 535 +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* DOUT */
 536 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 12)), /* PG_EINT12 */
 537 +       SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
 538 +                 SUNXI_FUNCTION(0x0, "gpio_in"),
 539 +                 SUNXI_FUNCTION(0x1, "gpio_out"),
 540 +                 SUNXI_FUNCTION(0x2, "i2s1"),          /* DIN */
 541 +                 SUNXI_FUNCTION_IRQ_BANK(0x4, 1, 13)), /* PG_EINT13 */
 542 +};
 543 +
 544 +static const struct sunxi_pinctrl_desc sun8i_h3_pinctrl_data = {
 545 +       .pins = sun8i_h3_pins,
 546 +       .npins = ARRAY_SIZE(sun8i_h3_pins),
 547 +       .irq_banks = 2,
 548 +};
 549 +
 550 +static int sun8i_h3_pinctrl_probe(struct platform_device *pdev)
 551 +{
 552 +       return sunxi_pinctrl_init(pdev,
 553 +                                 &sun8i_h3_pinctrl_data);
 554 +}
 555 +
 556 +static const struct of_device_id sun8i_h3_pinctrl_match[] = {
 557 +       { .compatible = "allwinner,sun8i-h3-pinctrl", },
 558 +       {}
 559 +};
 560 +
 561 +static struct platform_driver sun8i_h3_pinctrl_driver = {
 562 +       .probe  = sun8i_h3_pinctrl_probe,
 563 +       .driver = {
 564 +               .name           = "sun8i-h3-pinctrl",
 565 +               .of_match_table = sun8i_h3_pinctrl_match,
 566 +       },
 567 +};
 568 +builtin_platform_driver(sun8i_h3_pinctrl_driver);