target/linux/sunxi/patches-4.4/104-1-dt-sunxi-add-h3-dtsi.patch

   1 From 318d93bc41823e86967c8251eef0444a72e4d687 Mon Sep 17 00:00:00 2001
   2 From: Jens Kuske <jenskuske@gmail.com>
   3 Date: Fri, 4 Dec 2015 22:24:42 +0100
   4 Subject: [PATCH] ARM: dts: sunxi: Add Allwinner H3 DTSI
   5
   6 The Allwinner H3 is a home entertainment system oriented SoC with
   7 four Cortex-A7 cores and a Mali-400MP2 GPU.
   8
   9 Signed-off-by: Jens Kuske <jenskuske@gmail.com>
  10 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  11 ---
  12  arch/arm/boot/dts/sun8i-h3.dtsi | 497 ++++++++++++++++++++++++++++++++++++++++
  13  1 file changed, 497 insertions(+)
  14  create mode 100644 arch/arm/boot/dts/sun8i-h3.dtsi
  15
  16 diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
  17 new file mode 100644
  18 index 0000000..1524130e
  19 --- /dev/null
  20 +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
  21 @@ -0,0 +1,497 @@
  22 +/*
  23 + * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
  24 + *
  25 + * This file is dual-licensed: you can use it either under the terms
  26 + * of the GPL or the X11 license, at your option. Note that this dual
  27 + * licensing only applies to this file, and not this project as a
  28 + * whole.
  29 + *
  30 + *  a) This file is free software; you can redistribute it and/or
  31 + *     modify it under the terms of the GNU General Public License as
  32 + *     published by the Free Software Foundation; either version 2 of the
  33 + *     License, or (at your option) any later version.
  34 + *
  35 + *     This file is distributed in the hope that it will be useful,
  36 + *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  37 + *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  38 + *     GNU General Public License for more details.
  39 + *
  40 + * Or, alternatively,
  41 + *
  42 + *  b) Permission is hereby granted, free of charge, to any person
  43 + *     obtaining a copy of this software and associated documentation
  44 + *     files (the "Software"), to deal in the Software without
  45 + *     restriction, including without limitation the rights to use,
  46 + *     copy, modify, merge, publish, distribute, sublicense, and/or
  47 + *     sell copies of the Software, and to permit persons to whom the
  48 + *     Software is furnished to do so, subject to the following
  49 + *     conditions:
  50 + *
  51 + *     The above copyright notice and this permission notice shall be
  52 + *     included in all copies or substantial portions of the Software.
  53 + *
  54 + *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  55 + *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  56 + *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  57 + *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  58 + *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  59 + *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  60 + *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  61 + *     OTHER DEALINGS IN THE SOFTWARE.
  62 + */
  63 +
  64 +#include "skeleton.dtsi"
  65 +
  66 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  67 +#include <dt-bindings/pinctrl/sun4i-a10.h>
  68 +
  69 +/ {
  70 +       interrupt-parent = <&gic>;
  71 +
  72 +       cpus {
  73 +               #address-cells = <1>;
  74 +               #size-cells = <0>;
  75 +
  76 +               cpu@0 {
  77 +                       compatible = "arm,cortex-a7";
  78 +                       device_type = "cpu";
  79 +                       reg = <0>;
  80 +               };
  81 +
  82 +               cpu@1 {
  83 +                       compatible = "arm,cortex-a7";
  84 +                       device_type = "cpu";
  85 +                       reg = <1>;
  86 +               };
  87 +
  88 +               cpu@2 {
  89 +                       compatible = "arm,cortex-a7";
  90 +                       device_type = "cpu";
  91 +                       reg = <2>;
  92 +               };
  93 +
  94 +               cpu@3 {
  95 +                       compatible = "arm,cortex-a7";
  96 +                       device_type = "cpu";
  97 +                       reg = <3>;
  98 +               };
  99 +       };
 100 +
 101 +       timer {
 102 +               compatible = "arm,armv7-timer";
 103 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 104 +                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 105 +                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 106 +                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 107 +       };
 108 +
 109 +       clocks {
 110 +               #address-cells = <1>;
 111 +               #size-cells = <1>;
 112 +               ranges;
 113 +
 114 +               osc24M: osc24M_clk {
 115 +                       #clock-cells = <0>;
 116 +                       compatible = "fixed-clock";
 117 +                       clock-frequency = <24000000>;
 118 +                       clock-output-names = "osc24M";
 119 +               };
 120 +
 121 +               osc32k: osc32k_clk {
 122 +                       #clock-cells = <0>;
 123 +                       compatible = "fixed-clock";
 124 +                       clock-frequency = <32768>;
 125 +                       clock-output-names = "osc32k";
 126 +               };
 127 +
 128 +               pll1: clk@01c20000 {
 129 +                       #clock-cells = <0>;
 130 +                       compatible = "allwinner,sun8i-a23-pll1-clk";
 131 +                       reg = <0x01c20000 0x4>;
 132 +                       clocks = <&osc24M>;
 133 +                       clock-output-names = "pll1";
 134 +               };
 135 +
 136 +               /* dummy clock until actually implemented */
 137 +               pll5: pll5_clk {
 138 +                       #clock-cells = <0>;
 139 +                       compatible = "fixed-clock";
 140 +                       clock-frequency = <0>;
 141 +                       clock-output-names = "pll5";
 142 +               };
 143 +
 144 +               pll6: clk@01c20028 {
 145 +                       #clock-cells = <1>;
 146 +                       compatible = "allwinner,sun6i-a31-pll6-clk";
 147 +                       reg = <0x01c20028 0x4>;
 148 +                       clocks = <&osc24M>;
 149 +                       clock-output-names = "pll6", "pll6x2";
 150 +               };
 151 +
 152 +               pll6d2: pll6d2_clk {
 153 +                       #clock-cells = <0>;
 154 +                       compatible = "fixed-factor-clock";
 155 +                       clock-div = <2>;
 156 +                       clock-mult = <1>;
 157 +                       clocks = <&pll6 0>;
 158 +                       clock-output-names = "pll6d2";
 159 +               };
 160 +
 161 +               /* dummy clock until pll6 can be reused */
 162 +               pll8: pll8_clk {
 163 +                       #clock-cells = <0>;
 164 +                       compatible = "fixed-clock";
 165 +                       clock-frequency = <1>;
 166 +                       clock-output-names = "pll8";
 167 +               };
 168 +
 169 +               cpu: cpu_clk@01c20050 {
 170 +                       #clock-cells = <0>;
 171 +                       compatible = "allwinner,sun4i-a10-cpu-clk";
 172 +                       reg = <0x01c20050 0x4>;
 173 +                       clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 174 +                       clock-output-names = "cpu";
 175 +               };
 176 +
 177 +               axi: axi_clk@01c20050 {
 178 +                       #clock-cells = <0>;
 179 +                       compatible = "allwinner,sun4i-a10-axi-clk";
 180 +                       reg = <0x01c20050 0x4>;
 181 +                       clocks = <&cpu>;
 182 +                       clock-output-names = "axi";
 183 +               };
 184 +
 185 +               ahb1: ahb1_clk@01c20054 {
 186 +                       #clock-cells = <0>;
 187 +                       compatible = "allwinner,sun6i-a31-ahb1-clk";
 188 +                       reg = <0x01c20054 0x4>;
 189 +                       clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 190 +                       clock-output-names = "ahb1";
 191 +               };
 192 +
 193 +               ahb2: ahb2_clk@01c2005c {
 194 +                       #clock-cells = <0>;
 195 +                       compatible = "allwinner,sun8i-h3-ahb2-clk";
 196 +                       reg = <0x01c2005c 0x4>;
 197 +                       clocks = <&ahb1>, <&pll6d2>;
 198 +                       clock-output-names = "ahb2";
 199 +               };
 200 +
 201 +               apb1: apb1_clk@01c20054 {
 202 +                       #clock-cells = <0>;
 203 +                       compatible = "allwinner,sun4i-a10-apb0-clk";
 204 +                       reg = <0x01c20054 0x4>;
 205 +                       clocks = <&ahb1>;
 206 +                       clock-output-names = "apb1";
 207 +               };
 208 +
 209 +               apb2: apb2_clk@01c20058 {
 210 +                       #clock-cells = <0>;
 211 +                       compatible = "allwinner,sun4i-a10-apb1-clk";
 212 +                       reg = <0x01c20058 0x4>;
 213 +                       clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 214 +                       clock-output-names = "apb2";
 215 +               };
 216 +
 217 +               bus_gates: clk@01c20060 {
 218 +                       #clock-cells = <1>;
 219 +                       compatible = "allwinner,sun8i-h3-bus-gates-clk";
 220 +                       reg = <0x01c20060 0x14>;
 221 +                       clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
 222 +                       clock-names = "ahb1", "ahb2", "apb1", "apb2";
 223 +                       clock-indices = <5>, <6>, <8>,
 224 +                                       <9>, <10>, <13>,
 225 +                                       <14>, <17>, <18>,
 226 +                                       <19>, <20>,
 227 +                                       <21>, <23>,
 228 +                                       <24>, <25>,
 229 +                                       <26>, <27>,
 230 +                                       <28>, <29>,
 231 +                                       <30>, <31>, <32>,
 232 +                                       <35>, <36>, <37>,
 233 +                                       <40>, <41>, <43>,
 234 +                                       <44>, <52>, <53>,
 235 +                                       <54>, <64>,
 236 +                                       <65>, <69>, <72>,
 237 +                                       <76>, <77>, <78>,
 238 +                                       <96>, <97>, <98>,
 239 +                                       <112>, <113>,
 240 +                                       <114>, <115>,
 241 +                                       <116>, <128>, <135>;
 242 +                       clock-output-names = "bus_ce", "bus_dma", "bus_mmc0",
 243 +                                            "bus_mmc1", "bus_mmc2", "bus_nand",
 244 +                                            "bus_sdram", "bus_gmac", "bus_ts",
 245 +                                            "bus_hstimer", "bus_spi0",
 246 +                                            "bus_spi1", "bus_otg",
 247 +                                            "bus_otg_ehci0", "bus_ehci1",
 248 +                                            "bus_ehci2", "bus_ehci3",
 249 +                                            "bus_otg_ohci0", "bus_ohci1",
 250 +                                            "bus_ohci2", "bus_ohci3", "bus_ve",
 251 +                                            "bus_lcd0", "bus_lcd1", "bus_deint",
 252 +                                            "bus_csi", "bus_tve", "bus_hdmi",
 253 +                                            "bus_de", "bus_gpu", "bus_msgbox",
 254 +                                            "bus_spinlock", "bus_codec",
 255 +                                            "bus_spdif", "bus_pio", "bus_ths",
 256 +                                            "bus_i2s0", "bus_i2s1", "bus_i2s2",
 257 +                                            "bus_i2c0", "bus_i2c1", "bus_i2c2",
 258 +                                            "bus_uart0", "bus_uart1",
 259 +                                            "bus_uart2", "bus_uart3",
 260 +                                            "bus_scr", "bus_ephy", "bus_dbg";
 261 +               };
 262 +
 263 +               mmc0_clk: clk@01c20088 {
 264 +                       #clock-cells = <1>;
 265 +                       compatible = "allwinner,sun4i-a10-mmc-clk";
 266 +                       reg = <0x01c20088 0x4>;
 267 +                       clocks = <&osc24M>, <&pll6 0>, <&pll8>;
 268 +                       clock-output-names = "mmc0",
 269 +                                            "mmc0_output",
 270 +                                            "mmc0_sample";
 271 +               };
 272 +
 273 +               mmc1_clk: clk@01c2008c {
 274 +                       #clock-cells = <1>;
 275 +                       compatible = "allwinner,sun4i-a10-mmc-clk";
 276 +                       reg = <0x01c2008c 0x4>;
 277 +                       clocks = <&osc24M>, <&pll6 0>, <&pll8>;
 278 +                       clock-output-names = "mmc1",
 279 +                                            "mmc1_output",
 280 +                                            "mmc1_sample";
 281 +               };
 282 +
 283 +               mmc2_clk: clk@01c20090 {
 284 +                       #clock-cells = <1>;
 285 +                       compatible = "allwinner,sun4i-a10-mmc-clk";
 286 +                       reg = <0x01c20090 0x4>;
 287 +                       clocks = <&osc24M>, <&pll6 0>, <&pll8>;
 288 +                       clock-output-names = "mmc2",
 289 +                                            "mmc2_output",
 290 +                                            "mmc2_sample";
 291 +               };
 292 +
 293 +               mbus_clk: clk@01c2015c {
 294 +                       #clock-cells = <0>;
 295 +                       compatible = "allwinner,sun8i-a23-mbus-clk";
 296 +                       reg = <0x01c2015c 0x4>;
 297 +                       clocks = <&osc24M>, <&pll6 1>, <&pll5>;
 298 +                       clock-output-names = "mbus";
 299 +               };
 300 +       };
 301 +
 302 +       soc {
 303 +               compatible = "simple-bus";
 304 +               #address-cells = <1>;
 305 +               #size-cells = <1>;
 306 +               ranges;
 307 +
 308 +               dma: dma-controller@01c02000 {
 309 +                       compatible = "allwinner,sun8i-h3-dma";
 310 +                       reg = <0x01c02000 0x1000>;
 311 +                       interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 312 +                       clocks = <&bus_gates 6>;
 313 +                       resets = <&ahb_rst 6>;
 314 +                       #dma-cells = <1>;
 315 +               };
 316 +
 317 +               mmc0: mmc@01c0f000 {
 318 +                       compatible = "allwinner,sun5i-a13-mmc";
 319 +                       reg = <0x01c0f000 0x1000>;
 320 +                       clocks = <&bus_gates 8>,
 321 +                                <&mmc0_clk 0>,
 322 +                                <&mmc0_clk 1>,
 323 +                                <&mmc0_clk 2>;
 324 +                       clock-names = "ahb",
 325 +                                     "mmc",
 326 +                                     "output",
 327 +                                     "sample";
 328 +                       resets = <&ahb_rst 8>;
 329 +                       reset-names = "ahb";
 330 +                       interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 331 +                       status = "disabled";
 332 +                       #address-cells = <1>;
 333 +                       #size-cells = <0>;
 334 +               };
 335 +
 336 +               mmc1: mmc@01c10000 {
 337 +                       compatible = "allwinner,sun5i-a13-mmc";
 338 +                       reg = <0x01c10000 0x1000>;
 339 +                       clocks = <&bus_gates 9>,
 340 +                                <&mmc1_clk 0>,
 341 +                                <&mmc1_clk 1>,
 342 +                                <&mmc1_clk 2>;
 343 +                       clock-names = "ahb",
 344 +                                     "mmc",
 345 +                                     "output",
 346 +                                     "sample";
 347 +                       resets = <&ahb_rst 9>;
 348 +                       reset-names = "ahb";
 349 +                       interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 350 +                       status = "disabled";
 351 +                       #address-cells = <1>;
 352 +                       #size-cells = <0>;
 353 +               };
 354 +
 355 +               mmc2: mmc@01c11000 {
 356 +                       compatible = "allwinner,sun5i-a13-mmc";
 357 +                       reg = <0x01c11000 0x1000>;
 358 +                       clocks = <&bus_gates 10>,
 359 +                                <&mmc2_clk 0>,
 360 +                                <&mmc2_clk 1>,
 361 +                                <&mmc2_clk 2>;
 362 +                       clock-names = "ahb",
 363 +                                     "mmc",
 364 +                                     "output",
 365 +                                     "sample";
 366 +                       resets = <&ahb_rst 10>;
 367 +                       reset-names = "ahb";
 368 +                       interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 369 +                       status = "disabled";
 370 +                       #address-cells = <1>;
 371 +                       #size-cells = <0>;
 372 +               };
 373 +
 374 +               pio: pinctrl@01c20800 {
 375 +                       compatible = "allwinner,sun8i-h3-pinctrl";
 376 +                       reg = <0x01c20800 0x400>;
 377 +                       interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 378 +                                    <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 379 +                       clocks = <&bus_gates 69>;
 380 +                       gpio-controller;
 381 +                       #gpio-cells = <3>;
 382 +                       interrupt-controller;
 383 +                       #interrupt-cells = <2>;
 384 +
 385 +                       uart0_pins_a: uart0@0 {
 386 +                               allwinner,pins = "PA4", "PA5";
 387 +                               allwinner,function = "uart0";
 388 +                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 389 +                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 390 +                       };
 391 +
 392 +                       mmc0_pins_a: mmc0@0 {
 393 +                               allwinner,pins = "PF0", "PF1", "PF2", "PF3",
 394 +                                                "PF4", "PF5";
 395 +                               allwinner,function = "mmc0";
 396 +                               allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 397 +                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 398 +                       };
 399 +
 400 +                       mmc0_cd_pin: mmc0_cd_pin@0 {
 401 +                               allwinner,pins = "PF6";
 402 +                               allwinner,function = "gpio_in";
 403 +                               allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 404 +                               allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 405 +                       };
 406 +
 407 +                       mmc1_pins_a: mmc1@0 {
 408 +                               allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 409 +                                                "PG4", "PG5";
 410 +                               allwinner,function = "mmc1";
 411 +                               allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 412 +                               allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 413 +                       };
 414 +               };
 415 +
 416 +               ahb_rst: reset@01c202c0 {
 417 +                       #reset-cells = <1>;
 418 +                       compatible = "allwinner,sun6i-a31-ahb1-reset";
 419 +                       reg = <0x01c202c0 0xc>;
 420 +               };
 421 +
 422 +               apb1_rst: reset@01c202d0 {
 423 +                       #reset-cells = <1>;
 424 +                       compatible = "allwinner,sun6i-a31-clock-reset";
 425 +                       reg = <0x01c202d0 0x4>;
 426 +               };
 427 +
 428 +               apb2_rst: reset@01c202d8 {
 429 +                       #reset-cells = <1>;
 430 +                       compatible = "allwinner,sun6i-a31-clock-reset";
 431 +                       reg = <0x01c202d8 0x4>;
 432 +               };
 433 +
 434 +               timer@01c20c00 {
 435 +                       compatible = "allwinner,sun4i-a10-timer";
 436 +                       reg = <0x01c20c00 0xa0>;
 437 +                       interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 438 +                                    <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 439 +                       clocks = <&osc24M>;
 440 +               };
 441 +
 442 +               wdt0: watchdog@01c20ca0 {
 443 +                       compatible = "allwinner,sun6i-a31-wdt";
 444 +                       reg = <0x01c20ca0 0x20>;
 445 +                       interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 446 +               };
 447 +
 448 +               uart0: serial@01c28000 {
 449 +                       compatible = "snps,dw-apb-uart";
 450 +                       reg = <0x01c28000 0x400>;
 451 +                       interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 452 +                       reg-shift = <2>;
 453 +                       reg-io-width = <4>;
 454 +                       clocks = <&bus_gates 112>;
 455 +                       resets = <&apb2_rst 16>;
 456 +                       dmas = <&dma 6>, <&dma 6>;
 457 +                       dma-names = "rx", "tx";
 458 +                       status = "disabled";
 459 +               };
 460 +
 461 +               uart1: serial@01c28400 {
 462 +                       compatible = "snps,dw-apb-uart";
 463 +                       reg = <0x01c28400 0x400>;
 464 +                       interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 465 +                       reg-shift = <2>;
 466 +                       reg-io-width = <4>;
 467 +                       clocks = <&bus_gates 113>;
 468 +                       resets = <&apb2_rst 17>;
 469 +                       dmas = <&dma 7>, <&dma 7>;
 470 +                       dma-names = "rx", "tx";
 471 +                       status = "disabled";
 472 +               };
 473 +
 474 +               uart2: serial@01c28800 {
 475 +                       compatible = "snps,dw-apb-uart";
 476 +                       reg = <0x01c28800 0x400>;
 477 +                       interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 478 +                       reg-shift = <2>;
 479 +                       reg-io-width = <4>;
 480 +                       clocks = <&bus_gates 114>;
 481 +                       resets = <&apb2_rst 18>;
 482 +                       dmas = <&dma 8>, <&dma 8>;
 483 +                       dma-names = "rx", "tx";
 484 +                       status = "disabled";
 485 +               };
 486 +
 487 +               uart3: serial@01c28c00 {
 488 +                       compatible = "snps,dw-apb-uart";
 489 +                       reg = <0x01c28c00 0x400>;
 490 +                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 491 +                       reg-shift = <2>;
 492 +                       reg-io-width = <4>;
 493 +                       clocks = <&bus_gates 115>;
 494 +                       resets = <&apb2_rst 19>;
 495 +                       dmas = <&dma 9>, <&dma 9>;
 496 +                       dma-names = "rx", "tx";
 497 +                       status = "disabled";
 498 +               };
 499 +
 500 +               gic: interrupt-controller@01c81000 {
 501 +                       compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 502 +                       reg = <0x01c81000 0x1000>,
 503 +                             <0x01c82000 0x1000>,
 504 +                             <0x01c84000 0x2000>,
 505 +                             <0x01c86000 0x2000>;
 506 +                       interrupt-controller;
 507 +                       #interrupt-cells = <3>;
 508 +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 509 +               };
 510 +
 511 +               rtc: rtc@01f00000 {
 512 +                       compatible = "allwinner,sun6i-a31-rtc";
 513 +                       reg = <0x01f00000 0x54>;
 514 +                       interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 515 +                                    <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 516 +               };
 517 +       };
 518 +};