target/linux/sunxi/patches-4.4/101-dt-sun4i-add-dram-gates.patch

   1 From 82f8582feef4c048ee7ef0155a71c23614a7856d Mon Sep 17 00:00:00 2001
   2 From: Chen-Yu Tsai <wens@csie.org>
   3 Date: Sat, 5 Dec 2015 21:16:44 +0800
   4 Subject: [PATCH] ARM: dts: sun4i: Add DRAM gates
   5
   6 The DRAM gates controls direct memory access for some peripherals.
   7 These peripherals include the display pipeline, so add the required
   8 gates to the simplefb nodes as well.
   9
  10 Signed-off-by: Chen-Yu Tsai <wens@csie.org>
  11 Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
  12 ---
  13  arch/arm/boot/dts/sun4i-a10.dtsi | 36 ++++++++++++++++++++++++++++++++----
  14  1 file changed, 32 insertions(+), 4 deletions(-)
  15
  16 --- a/arch/arm/boot/dts/sun4i-a10.dtsi
  17 +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
  18 @@ -66,7 +66,7 @@
  19                                      "simple-framebuffer";
  20                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  21                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  22 -                                <&ahb_gates 44>;
  23 +                                <&ahb_gates 44>, <&dram_gates 26>;
  24                         status = "disabled";
  25                 };
  26
  27 @@ -75,7 +75,8 @@
  28                                      "simple-framebuffer";
  29                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  30                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  31 -                                <&ahb_gates 44>, <&ahb_gates 46>;
  32 +                                <&ahb_gates 44>, <&ahb_gates 46>,
  33 +                                <&dram_gates 25>, <&dram_gates 26>;
  34                         status = "disabled";
  35                 };
  36
  37 @@ -84,7 +85,8 @@
  38                                      "simple-framebuffer";
  39                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
  40                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
  41 -                                <&ahb_gates 46>;
  42 +                                <&ahb_gates 46>, <&dram_gates 25>,
  43 +                                <&dram_gates 26>;
  44                         status = "disabled";
  45                 };
  46
  47 @@ -93,7 +95,8 @@
  48                                      "simple-framebuffer";
  49                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
  50                         clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
  51 -                                <&ahb_gates 44>, <&ahb_gates 46>;
  52 +                                <&ahb_gates 44>, <&ahb_gates 46>,
  53 +                                <&dram_gates 25>, <&dram_gates 26>;
  54                         status = "disabled";
  55                 };
  56         };
  57 @@ -492,6 +495,31 @@
  58                         clock-output-names = "spi3";
  59                 };
  60
  61 +               dram_gates: clk@01c20100 {
  62 +                       #clock-cells = <1>;
  63 +                       compatible = "allwinner,sun4i-a10-dram-gates-clk";
  64 +                       reg = <0x01c20100 0x4>;
  65 +                       clocks = <&pll5 0>;
  66 +                       clock-indices = <0>,
  67 +                                       <1>, <2>,
  68 +                                       <3>,
  69 +                                       <4>,
  70 +                                       <5>, <6>,
  71 +                                       <15>,
  72 +                                       <24>, <25>,
  73 +                                       <26>, <27>,
  74 +                                       <28>, <29>;
  75 +                       clock-output-names = "dram_ve",
  76 +                                            "dram_csi0", "dram_csi1",
  77 +                                            "dram_ts",
  78 +                                            "dram_tvd",
  79 +                                            "dram_tve0", "dram_tve1",
  80 +                                            "dram_output",
  81 +                                            "dram_de_fe1", "dram_de_fe0",
  82 +                                            "dram_de_be0", "dram_de_be1",
  83 +                                            "dram_de_mp", "dram_ace";
  84 +               };
  85 +
  86                 codec_clk: clk@01c20140 {
  87                         #clock-cells = <0>;
  88                         compatible = "allwinner,sun4i-a10-codec-clk";