1 From d1bcc34ce6cb7601ce27f3090aee0e8a3e8076e3 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
3 Date: Sat, 14 Sep 2013 20:54:42 -0300
4 Subject: [PATCH] clk: sunxi: protect core clocks from accidental shutdown
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
9 Some important clocks may get disabled as a side effect of another clock
10 being disabled, because they have no consumers. This patch implements a
11 mechanism so those clocks can be claimed by the driver and therefore
12 remain enabled at all times.
14 Signed-off-by: Emilio López <emilio@elopez.com.ar>
16 drivers/clk/sunxi/clk-sunxi.c | 28 ++++++++++++++++++++++++++++
17 1 file changed, 28 insertions(+)
19 diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
20 index 9bbd035..8fc1375 100644
21 --- a/drivers/clk/sunxi/clk-sunxi.c
22 +++ b/drivers/clk/sunxi/clk-sunxi.c
23 @@ -616,6 +616,31 @@ static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_mat
28 + * System clock protection
30 + * By enabling these critical clocks, we prevent their accidental gating
33 +static void __init sunxi_clock_protect(void)
37 + /* memory bus clock - sun5i+ */
38 + clk = clk_get(NULL, "mbus");
40 + clk_prepare_enable(clk);
44 + /* DDR clock - sun4i+ */
45 + clk = clk_get(NULL, "pll5_ddr");
47 + clk_prepare_enable(clk);
52 static void __init sunxi_init_clocks(struct device_node *np)
54 /* Register factor clocks */
55 @@ -629,6 +654,9 @@ static void __init sunxi_init_clocks(struct device_node *np)
57 /* Register gate clocks */
58 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
60 + /* Enable core system clocks */
61 + sunxi_clock_protect();
63 CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sunxi_init_clocks);
64 CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sunxi_init_clocks);