target/linux/storm/patches/1006-gmac-napi-tx.patch

   1 Index: linux-2.6.23.17/drivers/net/sl351x_gmac.c
   2 ===================================================================
   3 --- linux-2.6.23.17.orig/drivers/net/sl351x_gmac.c
   4 +++ linux-2.6.23.17/drivers/net/sl351x_gmac.c
   5 @@ -43,9 +43,13 @@
   6
   7  #include <linux/mtd/kvctl.h>
   8
   9 +#define GET_RPTR(x) ((x) & 0xFFFF)
  10 +#define GET_WPTR(x) ((x) >> 16)
  11 +
  12  #define         MIDWAY
  13  #define         SL_LEPUS
  14 -#define VITESSE_G5SWITCH       1
  15 +// #define VITESSE_G5SWITCH    1
  16 +#undef VITESSE_G5SWITCH
  17
  18  #ifndef CONFIG_SL351x_RXTOE
  19  //#define CONFIG_SL351x_RXTOE  1
  20 @@ -126,7 +130,6 @@ static      char _debug_prefetch_buf[_DEBUG_P
  21   *************************************************************/
  22  static int     gmac_initialized = 0;
  23  TOE_INFO_T toe_private_data;
  24 -static int             do_again = 0;
  25  static int rx_poll_enabled;
  26  spinlock_t gmac_fq_lock;
  27  unsigned int FLAG_SWITCH;
  28 @@ -190,7 +193,7 @@ void mac_get_sw_tx_weight(struct net_dev
  29  void mac_set_sw_tx_weight(struct net_device *dev, char *weight);
  30  void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
  31  void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
  32 -static inline void toe_gmac_fill_free_q(void);
  33 +static inline void toe_gmac_fill_free_q(int count);
  34
  35  #ifdef VITESSE_G5SWITCH
  36  extern int Get_Set_port_status(void);
  37 @@ -295,12 +298,14 @@ static int __init gmac_init_module(void)
  38         for(j = 0; i<CONFIG_MAC_NUM; j++)
  39         {
  40                 i=j;
  41 +#ifdef VITESSE_G5SWITCH
  42                 if(Giga_switch){                // if gswitch present, swap eth0/1
  43                         if(j==0)
  44                                 i=1;
  45                         else if(j==1)
  46                                 i=0;
  47                 }
  48 +#endif
  49
  50                 tp = (GMAC_INFO_T *)&toe_private_data.gmac[i];
  51                 tp->dev = NULL;
  52 @@ -459,7 +464,7 @@ void mac_init_drv(void)
  53                 toe->gmac[1].dma_base_addr = TOE_GMAC1_DMA_BASE;
  54          toe->gmac[0].auto_nego_cfg = 1;
  55          toe->gmac[1].auto_nego_cfg = 1;
  56 -#ifdef CONFIG_SL3516_ASIC
  57 +#ifndef CONFIG_SL3516_ASIC
  58          toe->gmac[0].speed_cfg = GMAC_SPEED_1000;
  59          toe->gmac[1].speed_cfg = GMAC_SPEED_1000;
  60  #else
  61 @@ -508,7 +513,7 @@ void mac_init_drv(void)
  62                 // Write GLOBAL_QUEUE_THRESHOLD_REG
  63                 threshold.bits32 = 0;
  64                 threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
  65 -                                                       TOE_SW_FREEQ_DESC_NUM/2;
  66 +                                                       TOE_SW_FREEQ_DESC_NUM/16;
  67                 threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256/4 :
  68                                                         TOE_HW_FREEQ_DESC_NUM/4;
  69                 threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256/4 :
  70 @@ -613,18 +618,25 @@ static void toe_init_free_queue(void)
  71         rwptr_reg.bits.rptr = 0;
  72         toe->fq_rx_rwptr.bits32 = rwptr_reg.bits32;
  73         writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
  74 +       printk("SWFQ: %08X\n", readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG));
  75
  76         // SW Free Queue Descriptors
  77         for (i=0; i<TOE_SW_FREEQ_DESC_NUM; i++)
  78         {
  79 +               void *data = NULL;
  80                 sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
  81 -               sw_desc_ptr->word1.bits.sw_id = i;      // used to locate skb
  82 +               sw_desc_ptr->word1.bits.sw_id = 0;      // used to locate skb
  83                 if ( (skb = dev_alloc_skb(SW_RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
  84                 {
  85                         printk("%s::skb buffer allocation fail !\n",__func__); while(1);
  86                 }
  87 -               REG32(skb->data) = (unsigned int)skb;
  88 +
  89 +               data = skb->data;
  90                 skb_reserve(skb, SKB_RESERVE_BYTES);
  91 +
  92 +               REG32(data + 0) = (unsigned int)skb;
  93 +               REG32(data + 4) = (unsigned short)i;
  94 +
  95                 // toe->rx_skb[i] = skb;
  96                 sw_desc_ptr->word2.buf_adr = (unsigned int)__pa(skb->data);
  97  //             consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
  98 @@ -851,14 +863,14 @@ static void toe_init_hwtx_queue(void)
  99  *----------------------------------------------------------------------*/
 100  static void toe_init_default_queue(void)
 101  {
 102 -       TOE_INFO_T                              *toe;
 103 +       TOE_INFO_T              *toe;
 104         volatile NONTOE_QHDR_T  *qhdr;
 105 -       GMAC_RXDESC_T                   *desc_ptr;
 106 -       DMA_SKB_SIZE_T                  skb_size;
 107 +       GMAC_RXDESC_T           *desc_ptr;
 108 +       DMA_SKB_SIZE_T          skb_size;
 109
 110         toe = (TOE_INFO_T *)&toe_private_data;
 111         desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T)),
 112 -                                                                                       (dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
 113 +                                              (dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
 114         if (!desc_ptr)
 115         {
 116                 printk("%s::DMA_MALLOC fail !\n",__func__);
 117 @@ -866,14 +878,17 @@ static void toe_init_default_queue(void)
 118         }
 119         memset((void *)desc_ptr, 0, TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T));
 120         toe->gmac[0].default_desc_base = (unsigned int)desc_ptr;
 121 +       printk("toe->gmac[0].default_desc_base_dma: %08X\n", toe->gmac[0].default_desc_base_dma);
 122 +
 123         toe->gmac[0].default_desc_num = TOE_DEFAULT_Q0_DESC_NUM;
 124         qhdr = (volatile NONTOE_QHDR_T *)TOE_DEFAULT_Q0_HDR_BASE;
 125         qhdr->word0.base_size = ((unsigned int)toe->gmac[0].default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q0_DESC_POWER;
 126         qhdr->word1.bits32 = 0;
 127         toe->gmac[0].rx_rwptr.bits32 = 0;
 128         toe->gmac[0].default_qhdr = (NONTOE_QHDR_T *)qhdr;
 129 +
 130         desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q1_DESC_NUM * sizeof(GMAC_RXDESC_T)),
 131 -                                                                                       (dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
 132 +                                              (dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
 133         if (!desc_ptr)
 134         {
 135                 printk("%s::DMA_MALLOC fail !\n",__func__);
 136 @@ -1071,12 +1086,16 @@ static void toe_init_gmac(struct net_dev
 137
 138             data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
 139             writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
 140 +
 141             data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG) & ~tp->intr1_selected;
 142             writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
 143 +
 144             data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG) & ~tp->intr2_selected;
 145             writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
 146 +
 147             data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG) & ~tp->intr3_selected;
 148             writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
 149 +
 150             data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) & ~tp->intr4_selected;
 151             writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
 152         }
 153 @@ -1176,11 +1195,11 @@ static int toe_gmac_init_chip(struct net
 154         GMAC_CONFIG2_T  config2_val;
 155         GMAC_CONFIG0_T  config0,config0_mask;
 156         GMAC_CONFIG1_T  config1;
 157 -       #ifdef CONFIG_SL351x_NAT
 158         GMAC_CONFIG3_T  config3_val;
 159 -       #endif
 160         GMAC_TX_WCR0_T  hw_weigh;
 161         GMAC_TX_WCR1_T  sw_weigh;
 162 +
 163 +       uint32_t weight = 0;
 164  //     GMAC_HASH_ENABLE_REG0_T hash_ctrl;
 165  //
 166  #if 0 /* mac address will be set in late_initcall */
 167 @@ -1202,24 +1221,23 @@ static int toe_gmac_init_chip(struct net
 168         //      config1.bits32 = 0x002004;      //next version
 169         /* set flow control threshold */
 170         config1.bits32 = 0;
 171 -       config1.bits.set_threshold = 32 / 2;
 172 -       config1.bits.rel_threshold = 32 / 4 * 3;
 173 +       config1.bits.set_threshold = (32 / 2);
 174 +       config1.bits.rel_threshold = (32 / 4) * 3;
 175         gmac_write_reg(tp->base_addr, GMAC_CONFIG1, config1.bits32, 0xffffffff);
 176
 177 -       /* set flow control threshold */
 178 +       /* TODO: set flow control threshold */
 179         config2_val.bits32 = 0;
 180 -       config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM/2;
 181 -       config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM*3/4;
 182 +       config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM/4;
 183 +       config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM/2;
 184         gmac_write_reg(tp->base_addr, GMAC_CONFIG2, config2_val.bits32,0xffffffff);
 185
 186 -       #ifdef CONFIG_SL351x_NAT
 187 -       /* set HW free queue flow control threshold */
 188 +       /* TODO: set HW free queue flow control threshold */
 189         config3_val.bits32 = 0;
 190         config3_val.bits.set_threshold = PAUSE_SET_HW_FREEQ;
 191         config3_val.bits.rel_threshold = PAUSE_REL_HW_FREEQ;
 192         gmac_write_reg(tp->base_addr, GMAC_CONFIG3, config3_val.bits32,0xffffffff);
 193 -       #endif
 194 -       /* set_mcast_filter mask*/
 195 +
 196 +       /* TODO: set_mcast_filter mask*/
 197         //      gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,0x0,0xffffffff);
 198         //  gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,0x0,0xffffffff);
 199
 200 @@ -1249,7 +1267,7 @@ static int toe_gmac_init_chip(struct net
 201         config0.bits.dis_rx = 1;  /* disable rx */
 202         config0.bits.dis_tx = 1;  /* disable tx */
 203         config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
 204 -       config0.bits.rx_err_detect = 1;
 205 +       config0.bits.rx_err_detect = 1; /* TODO: was 1, means disabled, 0 enabled ! */
 206         config0.bits.rgmii_en = 0;
 207         config0.bits.rgmm_edge = 1;
 208         config0.bits.rxc_inv = 0;
 209 @@ -1342,6 +1360,9 @@ static int toe_gmac_init_chip(struct net
 210         gmac_write_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG, ahb_weight.bits32, ahb_weight_mask.bits32);
 211         #endif
 212
 213 +       weight = gmac_read_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG);
 214 +       printk("====> %08X\n", weight);
 215 +
 216         #if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
 217         gmac_write_reg(tp->dma_base_addr, GMAC_SPR0, IPPROTO_TCP, 0xffffffff);
 218         #endif
 219 @@ -1552,7 +1573,7 @@ static  void toe_gmac_tx_complete(GMAC_I
 220                 rwptr.bits32 = readl(swtxq->rwptr_reg);
 221                 if (rwptr.bits.rptr == swtxq->finished_idx)
 222                         break;
 223 -       curr_desc = (volatile GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
 224 +               curr_desc = (volatile GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
 225  //             consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
 226                 word0.bits32 = curr_desc->word0.bits32;
 227                 word1.bits32 = curr_desc->word1.bits32;
 228 @@ -1573,6 +1594,7 @@ static  void toe_gmac_tx_complete(GMAC_I
 229                                 swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
 230                                 curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
 231                                 word0.bits32 = curr_desc->word0.bits32;
 232 +
 233  #ifdef _DUMP_TX_TCP_CONTENT
 234                                 if (curr_desc->word0.bits.buffer_size < 16)
 235                                 {
 236 @@ -1592,12 +1614,12 @@ static  void toe_gmac_tx_complete(GMAC_I
 237                         word0.bits.status_tx_ok = 0;
 238                         if (swtxq->tx_skb[swtxq->finished_idx])
 239                         {
 240 -                               if (interrupt)
 241 -                                       dev_kfree_skb_irq(swtxq->tx_skb[swtxq->finished_idx]);
 242 -                               else
 243 -                                       dev_kfree_skb(swtxq->tx_skb[swtxq->finished_idx]);
 244 +                               dev_kfree_skb(swtxq->tx_skb[swtxq->finished_idx]);
 245                                 swtxq->tx_skb[swtxq->finished_idx] = NULL;
 246 +                       } else {
 247 +                               BUG();
 248                         }
 249 +
 250                         curr_desc->word0.bits32 = word0.bits32;
 251                         swtxq->curr_finished_desc = (GMAC_TXDESC_T *)curr_desc;
 252                         swtxq->total_finished++;
 253 @@ -1624,31 +1646,29 @@ static  void toe_gmac_tx_complete(GMAC_I
 254  *----------------------------------------------------------------------*/
 255  static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 256  {
 257 -       GMAC_INFO_T                     *tp= dev->priv;
 258 -//     static unsigned int     pcount = 0;
 259 -//     unsigned int                    tx_qid;
 260 -    DMA_RWPTR_T                                rwptr;
 261 -       volatile GMAC_TXDESC_T  *curr_desc;
 262 -       int                                     snd_pages = skb_shinfo(skb)->nr_frags + 1;  /* get number of descriptor */
 263 -       int                                     frag_id = 0;
 264 -       int                                     len, total_len = skb->len;
 265 +       GMAC_INFO_T *tp= dev->priv;
 266 +       DMA_RWPTR_T rwptr;
 267 +       GMAC_TXDESC_T *curr_desc;
 268 +       int snd_pages = skb_shinfo(skb)->nr_frags + 1;  /* get number of descriptor */
 269 +       int frag_id = 0;
 270 +       int len, total_len = skb->len;
 271         struct net_device_stats *isPtr;
 272 -       unsigned int                    free_desc;
 273 -       GMAC_SWTXQ_T                    *swtxq;
 274 +       unsigned int free_desc;
 275 +       GMAC_SWTXQ_T *swtxq;
 276         register unsigned long  word0, word1, word2, word3;
 277         unsigned short                  wptr, rptr;
 278  #ifdef L2_jumbo_frame
 279         int header_len = skb->len;
 280         struct iphdr    *ip_hdr;
 281 -    struct tcphdr      *tcp_hdr;
 282 -    int             tcp_hdr_len;
 283 -    unsigned char      *ptr;
 284 -    int             data_len,a;
 285 -    unsigned int    val;
 286 +       struct tcphdr   *tcp_hdr;
 287 +       int             tcp_hdr_len;
 288 +       unsigned char   *ptr;
 289 +       int             data_len,a;
 290 +       unsigned int    val;
 291  #endif
 292
 293  #ifdef GMAC_LEN_1_2_ISSUE
 294 -       int                                             total_pages;
 295 +       int total_pages;
 296         total_pages = snd_pages;
 297  #endif
 298
 299 @@ -1664,13 +1684,6 @@ static int gmac_start_xmit(struct sk_buf
 300      }
 301  #endif
 302
 303 -#if 0
 304 -       if (storlink_ctl.recvfile==2)
 305 -       {
 306 -           printk("snd_pages=%d skb->len=%d\n",snd_pages,skb->len);
 307 -       }
 308 -#endif
 309 -
 310  #ifdef GMAC_USE_TXQ0
 311         #define tx_qid  0
 312  #endif
 313 @@ -1703,9 +1716,9 @@ static int gmac_start_xmit(struct sk_buf
 314         toe_gmac_tx_complete(tp, tx_qid, dev, 0);
 315
 316         if (wptr >= swtxq->finished_idx)
 317 -               free_desc = swtxq->total_desc_num - wptr - 1 + swtxq->finished_idx;
 318 +               free_desc = swtxq->total_desc_num - wptr + swtxq->finished_idx;
 319         else
 320 -               free_desc = swtxq->finished_idx - wptr - 1;
 321 +               free_desc = swtxq->finished_idx - wptr;
 322         if (free_desc < snd_pages)
 323         {
 324  //             spin_unlock(&tp->tx_mutex);
 325 @@ -2063,9 +2076,10 @@ void mac_start_txdma(struct net_device *
 326  struct net_device_stats * gmac_get_stats(struct net_device *dev)
 327  {
 328      GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
 329 +#if 0  /* don't read stats from hardware, scary numbers. */
 330      // unsigned int        flags;
 331 -    unsigned int        pkt_drop;
 332 -    unsigned int        pkt_error;
 333 +    unsigned int        pkt_drop = 0;
 334 +    unsigned int        pkt_error = 0;
 335
 336      if (netif_running(dev))
 337      {
 338 @@ -2073,10 +2087,14 @@ struct net_device_stats * gmac_get_stats
 339          // spin_lock_irqsave(&tp->lock,flags);
 340          pkt_drop = gmac_read_reg(tp->base_addr,GMAC_IN_DISCARDS);
 341          pkt_error = gmac_read_reg(tp->base_addr,GMAC_IN_ERRORS);
 342 +       printk("**** stack: %lu, hw: %lu\n", tp->ifStatics.rx_dropped, pkt_drop);
 343 +
 344          tp->ifStatics.rx_dropped = tp->ifStatics.rx_dropped + pkt_drop;
 345          tp->ifStatics.rx_errors = tp->ifStatics.rx_errors + pkt_error;
 346          // spin_unlock_irqrestore(&tp->lock,flags);
 347      }
 348 +#endif
 349 +
 350      return &tp->ifStatics;
 351  }
 352
 353 @@ -2401,36 +2419,63 @@ static int gmac_close(struct net_device
 354  * toe_gmac_fill_free_q
 355  * allocate buffers for free queue.
 356  *----------------------------------------------------------------------*/
 357 -static inline void toe_gmac_fill_free_q(void)
 358 +static inline void toe_gmac_fill_free_q(int count)
 359  {
 360         struct sk_buff  *skb;
 361         volatile DMA_RWPTR_T    fq_rwptr;
 362         volatile GMAC_RXDESC_T  *fq_desc;
 363 -       unsigned long   flags;
 364 +       unsigned long flags;
 365 +       unsigned short index;
 366 +       int filled = 0;
 367 +       static int entered;
 368         // unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
 369
 370 +       BUG_ON(entered == 1);
 371 +
 372 +       entered = 1;
 373 +
 374 +
 375         fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
 376         // spin_lock_irqsave(&gmac_fq_lock, flags);
 377         //while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
 378         //                              TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
 379 -       while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
 380 -                                       TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
 381 +       index = fq_rwptr.bits.wptr;
 382 +#if 0
 383 +       printk("wptr: %hu, rptr: %hu, refill idx: %hu\n",
 384 +              GET_RPTR(fq_rwptr.bits32),
 385 +              GET_WPTR(fq_rwptr.bits32),
 386 +              index);
 387 +#endif
 388 +
 389 +       index = RWPTR_ADVANCE_ONE(index, TOE_SW_FREEQ_DESC_NUM);
 390 +       fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base + index;
 391 +       while (fq_desc->word2.buf_adr == 0) {
 392 +               void *data = NULL;
 393 +
 394                 if ((skb = dev_alloc_skb(SW_RX_BUF_SIZE)) == NULL) {
 395                         printk("%s::skb allocation fail!\n", __func__);
 396 -                       //while(1);
 397 -                       break;
 398 +                       goto out;
 399                 }
 400 -               REG32(skb->data) = (unsigned int)skb;
 401 +               ++ filled;
 402 +               data = skb->data;
 403                 skb_reserve(skb, SKB_RESERVE_BYTES);
 404 -               // fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
 405 -               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
 406 -                       TOE_SW_FREEQ_DESC_NUM);
 407 -               fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base+fq_rwptr.bits.wptr;
 408 +
 409 +               REG32(data + 0) = (unsigned int)skb;
 410 +               REG32(data + 4) = (unsigned short)index;
 411 +
 412 +               // printk("refill skb: %p, idx: %hu\n", skb, index);
 413                 fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
 414 -               SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
 415 -               toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
 416 +       writel(0x07960202, TOE_GMAC0_BASE+GMAC_CONFIG0);
 417 +               SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, index);
 418 +       writel(0x07960200, TOE_GMAC0_BASE+GMAC_CONFIG0);
 419 +
 420 +               index = RWPTR_ADVANCE_ONE(index, TOE_SW_FREEQ_DESC_NUM);
 421 +               fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base+index;
 422         }
 423 +out:
 424         // spin_unlock_irqrestore(&gmac_fq_lock, flags);
 425 +
 426 +       entered = 0;
 427  }
 428  // EXPORT_SYMBOL(toe_gmac_fill_free_q);
 429
 430 @@ -2442,14 +2487,14 @@ static void gmac_registers(const char *m
 431         unsigned int            status3;
 432         unsigned int            status4;
 433
 434 -       printk("%s\n", message);
 435 -
 436         status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
 437         status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
 438         status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
 439         status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
 440         status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
 441
 442 +       printk("%s\n", message);
 443 +
 444         printk("status: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
 445                    status0, status1, status2, status3, status4);
 446
 447 @@ -2468,8 +2513,9 @@ static void gmac_registers(const char *m
 448         status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
 449         status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
 450
 451 -       printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
 452 -                  status0, status1, status2, status3, status4);
 453 +       if (status0 || status1 || status2 || status3 || status4)
 454 +                       printk("select: s0:%08X, s1:%08X, s2:%08X, s3:%08X, s4:%08X\n",
 455 +                                  status0, status1, status2, status3, status4);
 456  }
 457  /*----------------------------------------------------------------------
 458  * toe_gmac_interrupt
 459 @@ -2485,75 +2531,44 @@ static irqreturn_t toe_gmac_interrupt (i
 460         unsigned int            status3;
 461         unsigned int            status4;
 462
 463 -//     struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
 464         toe = (TOE_INFO_T *)&toe_private_data;
 465 -//     handle NAPI
 466 -#ifdef CONFIG_SL_NAPI
 467 -       /* XXX: check this, changed from 'storlink_ctl.pauseoff == 1' to if (1) */
 468 -if (1)
 469 -{
 470 -/* disable GMAC interrupt */
 471 -    //toe_gmac_disable_interrupt(tp->irq);
 472
 473 -//     isPtr->interrupts++;
 474 +       if (0 && rx_poll_enabled) {
 475 +               gmac_registers("interrupt handler");
 476 +       }
 477 +
 478         /* read Interrupt status */
 479         status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
 480         status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
 481         status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
 482         status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
 483         status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
 484 -       // prompt warning if status bit ON but not enabled
 485 +
 486  #if 0
 487 -       if (status0 & ~tp->intr0_enabled)
 488 -               printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
 489 -                               status0, tp->intr0_enabled);
 490 -       if (status1 & ~tp->intr1_enabled)
 491 -               printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
 492 -                               status1, tp->intr1_enabled);
 493 -       if (status2 & ~tp->intr2_enabled)
 494 -               printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
 495 -                               status2, tp->intr2_enabled);
 496 -       if (status3 & ~tp->intr3_enabled)
 497 -               printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
 498 -                               status3, tp->intr3_enabled);
 499 -       if (status4 & ~tp->intr4_enabled)
 500 -               printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
 501 -                               status4, tp->intr4_enabled);
 502 +       /* handle freeq interrupt first */
 503 +       if (status4 & SWFQ_EMPTY_INT_BIT)
 504 +       {
 505 +               toe_gmac_fill_free_q();
 506 +               writel(status4 & SWFQ_EMPTY_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
 507 +               tp->sw_fq_empty_cnt++;
 508 +       }
 509  #endif
 510
 511 +       if (status4 & GMAC0_MIB_INT_BIT)
 512 +               writel(GMAC0_MIB_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
 513 +
 514 +       if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
 515 +               writel(GMAC0_RX_OVERRUN_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
 516 +
 517         if (status0)
 518                 writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
 519 -       if (status1)
 520 -               writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
 521         if (status2)
 522                 writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
 523         if (status3)
 524                 writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
 525 -       if (status4)
 526 -               writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
 527 -
 528 -#if 0
 529 -       /* handle freeq interrupt first */
 530 -       if (status4 & tp->intr4_enabled) {
 531 -               if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
 532 -               {
 533 -                       // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
 534 -                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
 535 -                       //      tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
 536 -
 537 -                       if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
 538 -                               toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
 539 -                       if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
 540 -                               toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
 541 -                       printk("\nfreeq int\n");
 542 -                       toe_gmac_fill_free_q();
 543 -                       tp->sw_fq_empty_cnt++;
 544
 545 -               }
 546 -       }
 547 -#endif
 548         // Interrupt Status 1
 549 -       if (status1 & tp->intr1_enabled)
 550 +       if ((status1 & 3) || (status4 & 1))
 551         {
 552                 #define G1_INTR0_BITS   (GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
 553                 #define G0_INTR0_BITS   (GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
 554 @@ -2563,7 +2578,7 @@ if (1)
 555                 // because they should pass packets to upper layer
 556                 if (tp->port_id == 0)
 557                 {
 558 -                       if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
 559 +                       if (((status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS)) || (status4 & 1))
 560                         {
 561                                 if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
 562                                         tp->hwtxq[3].eof_cnt++;
 563 @@ -2574,50 +2589,51 @@ if (1)
 564                                 if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
 565                                         tp->hwtxq[0].eof_cnt++;
 566                         }
 567 -                               if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
 568 +                       if (status1 & DEFAULT_Q0_INT_BIT || status4 & 1)
 569 +                       {
 570 +                               if (likely(netif_rx_schedule_prep(dev)))
 571                                 {
 572 -                                       if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
 573 -                               {
 574 -                                       unsigned int data32;
 575 +                                       unsigned int data32;
 576 +
 577 +                                       BUG_ON(rx_poll_enabled == 1);
 578
 579 -                                               if (rx_poll_enabled)
 580 -                                                               gmac_registers("check #1");
 581 +                                       /* Masks GMAC-0 rx interrupt */
 582 +                                       data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 583 +                                       data32 &= ~(DEFAULT_Q0_INT_BIT);
 584 +                                       writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 585
 586 -                                               BUG_ON(rx_poll_enabled == 1);
 587 +                                       /* Masks GMAC-0 queue empty interrupt */
 588 +                                       data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
 589 +                                       data32 &= ~DEFAULT_Q0_INT_BIT;
 590 +                                       writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
 591
 592 +                                       __netif_rx_schedule(dev);
 593 +                                       rx_poll_enabled = 1;
 594 +                               } else {
 595  #if 0
 596 -                                       /* Masks GMAC-0 rx interrupt */
 597 -                                               data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 598 -                                               data32 &= ~(DEFAULT_Q0_INT_BIT);
 599 -                                               writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 600 -
 601 -                                       /* Masks GMAC-0 queue empty interrupt */
 602 -                                               data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
 603 -                                               data32 &= ~DEFAULT_Q0_INT_BIT;
 604 -                                               writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
 605 -
 606 -                                               data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
 607 -                                               data32 &= ~DEFAULT_Q0_INT_BIT;
 608 -                                               writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
 609 -#endif
 610 -
 611 -                                       // class-Q & TOE-Q are implemented in future
 612 -                                       //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 613 -                                       //data32 &= ~DEFAULT_Q0_INT_BIT;
 614 -                                               //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 615 -                                               //printk("\%s: DEFAULT_Q0_INT_BIT===================>>>>>>>>>>>>\n",__func__);
 616 -                                               writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
 617 -                                               //tp->total_q_cnt_napi=0;
 618 -                                               //rx_time = jiffies;
 619 -                                               //rx_old_bytes = isPtr->rx_bytes;
 620 -                                               __netif_rx_schedule(dev);
 621 -                                               rx_poll_enabled = 1;
 622 -                               }
 623 +                                       unsigned int data32;
 624 +
 625 +                                       if (rx_poll_enabled)
 626 +                                               gmac_registers("->poll() running.");
 627 +                                       /* Masks GMAC-0 rx interrupt */
 628 +                                       data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 629 +                                       data32 &= ~(DEFAULT_Q0_INT_BIT);
 630 +                                       writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 631 +
 632 +                                       /* Masks GMAC-0 queue empty interrupt */
 633 +                                       data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
 634 +                                       data32 &= ~DEFAULT_Q0_INT_BIT;
 635 +                                       writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
 636 +#endif
 637 +                               }
 638 +                       } else {
 639 +                               if (0)
 640 +                                       gmac_registers("status1 & DEFAULT_Q0_INT_BIT || status4 & 1");
 641                         }
 642                 }
 643 -               else if (tp->port_id == 1)
 644 +               else if (tp->port_id == 1 && netif_running(dev))
 645                 {
 646 -                       if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
 647 +                       if ((status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
 648                         {
 649                                 if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
 650                                         tp->hwtxq[3].eof_cnt++;
 651 @@ -2629,14 +2645,14 @@ if (1)
 652                                         tp->hwtxq[0].eof_cnt++;
 653                         }
 654
 655 -                       if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
 656 +                       if ((status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
 657                         {
 658                                 if (!rx_poll_enabled && likely(netif_rx_schedule_prep(dev)))
 659 -                       {
 660 -                               unsigned int data32;
 661 +                               {
 662 +                                       unsigned int data32;
 663
 664                                         if (rx_poll_enabled)
 665 -                                                       gmac_registers("check #2");
 666 +                                               gmac_registers("check #2");
 667
 668                                         BUG_ON(rx_poll_enabled == 1);
 669
 670 @@ -2646,7 +2662,7 @@ if (1)
 671                                         data32 &= ~(DEFAULT_Q1_INT_BIT);
 672                                         writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 673
 674 -                               /* Masks GMAC-1 queue empty interrupt */
 675 +                                       /* Masks GMAC-1 queue empty interrupt */
 676                                         data32  = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
 677                                         data32 &= ~DEFAULT_Q1_INT_BIT;
 678                                         writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
 679 @@ -2656,24 +2672,21 @@ if (1)
 680                                         writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
 681  #endif
 682
 683 -                               // disable GMAC-0 rx interrupt
 684 -                               // class-Q & TOE-Q are implemented in future
 685 -                               //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 686 -                               //data32 &= ~DEFAULT_Q1_INT_BIT;
 687 +                                       // disable GMAC-0 rx interrupt
 688 +                                       // class-Q & TOE-Q are implemented in future
 689 +                                       //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 690 +                                       //data32 &= ~DEFAULT_Q1_INT_BIT;
 691                                         //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
 692                                         //printk("\%s: 1111111111--->DEFAULT_Q1_INT_BIT===================>>>>>>>>>>>>\n",__func__);
 693                                         writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
 694                                         //tp->total_q_cnt_napi=0;
 695                                         //rx_time = jiffies;
 696                                         //rx_old_bytes = isPtr->rx_bytes;
 697 -                               __netif_rx_schedule(dev);
 698 -                               rx_poll_enabled = 1;
 699 -                       }
 700 +                                       __netif_rx_schedule(dev);
 701 +                                       rx_poll_enabled = 1;
 702 +                               }
 703                         }
 704                 }
 705 -       } else {
 706 -
 707 -               gmac_registers("check #3");
 708         }
 709
 710         // Interrupt Status 0
 711 @@ -2814,676 +2827,93 @@ if (1)
 712                 }
 713         }
 714
 715 -       //toe_gmac_enable_interrupt(tp->irq);
 716 -#ifdef IxscriptMate_1518
 717 -       if (storlink_ctl.pauseoff == 1)
 718 -       {
 719 -               GMAC_CONFIG0_T config0;
 720 -               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
 721 -               config0.bits.dis_rx = 0;
 722 -               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
 723 -               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
 724 -               config0.bits.dis_rx = 0;
 725 -               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
 726 -       }
 727 -#endif
 728 -//      enable_irq(gmac_irq[dev_index]);
 729 -       //printk("gmac_interrupt complete!\n\n");
 730 -//     return IRQ_RETVAL(handled);
 731         return  IRQ_RETVAL(1);
 732  }
 733 -else
 734 -{
 735 -#endif //endif NAPI
 736
 737 +/*----------------------------------------------------------------------
 738 +* gmac_get_phy_vendor
 739 +*----------------------------------------------------------------------*/
 740 +static unsigned int gmac_get_phy_vendor(int phy_addr)
 741 +{
 742 +    unsigned int       reg_val;
 743 +    reg_val=(mii_read(phy_addr,0x02) << 16) + mii_read(phy_addr,0x03);
 744 +    return reg_val;
 745 +}
 746
 747 -       /* disable GMAC interrupt */
 748 -    toe_gmac_disable_interrupt(tp->irq);
 749 +/*----------------------------------------------------------------------
 750 +* gmac_set_phy_status
 751 +*----------------------------------------------------------------------*/
 752 +void gmac_set_phy_status(struct net_device *dev)
 753 +{
 754 +       GMAC_INFO_T *tp = dev->priv;
 755 +       GMAC_STATUS_T   status;
 756 +       unsigned int    reg_val, ability,wan_port_id;
 757 +       unsigned int    i = 0;
 758
 759 -//     isPtr->interrupts++;
 760 -       /* read Interrupt status */
 761 -       status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
 762 -       status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
 763 -       status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
 764 -       status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
 765 -       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
 766 -       // prompt warning if status bit ON but not enabled
 767 +#ifdef VITESSE_G5SWITCH
 768 +       if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1)){
 769  #if 0
 770 -       if (status0 & ~tp->intr0_enabled)
 771 -               printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
 772 -                               status0, tp->intr0_enabled);
 773 -       if (status1 & ~tp->intr1_enabled)
 774 -               printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
 775 -                               status1, tp->intr1_enabled);
 776 -       if (status2 & ~tp->intr2_enabled)
 777 -               printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
 778 -                               status2, tp->intr2_enabled);
 779 -       if (status3 & ~tp->intr3_enabled)
 780 -               printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
 781 -                               status3, tp->intr3_enabled);
 782 -       if (status4 & ~tp->intr4_enabled)
 783 -               printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
 784 -                               status4, tp->intr4_enabled);
 785 -#endif
 786 -#define        INTERRUPT_SELECT                        1
 787 -       if (status0)
 788 -               writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
 789 -       if (status1)
 790 -               writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
 791 -       if (status2)
 792 -               writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
 793 -       if (status3)
 794 -               writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
 795 -       if (status4)
 796 -               writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
 797 -
 798 -       /* handle freeq interrupt first */
 799 -       if (status4 & tp->intr4_enabled) {
 800 -               if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
 801 -               {
 802 -                       // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
 803 -                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
 804 -                       //      tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
 805 -
 806 -                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
 807 -                       //      SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
 808 -                       if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
 809 -                               toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
 810 -                       if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
 811 -                               toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
 812 -                       printk("\nfreeq int\n");
 813 -                       toe_gmac_fill_free_q();
 814 -                       tp->sw_fq_empty_cnt++;
 815 -
 816 -                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
 817 -                               SWFQ_EMPTY_INT_BIT);
 818 -               }
 819 -       }
 820 -
 821 -       // Interrupt Status 1
 822 -       if (status1 & tp->intr1_enabled)
 823 -       {
 824 -               #define G1_INTR0_BITS   (GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
 825 -               #define G0_INTR0_BITS   (GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
 826 -               // Handle GMAC 0/1 HW Tx queue 0-3 EOF events
 827 -               // Only count
 828 -               // TOE, Classification, and default queues interrupts are handled by ISR
 829 -               // because they should pass packets to upper layer
 830 -               if (tp->port_id == 0)
 831 -               {
 832 -#ifndef        INTERRUPT_SELECT
 833 -                       if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
 834 -                       {
 835 -                               if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
 836 -                                       tp->hwtxq[3].eof_cnt++;
 837 -                               if (status1 & GMAC0_HWTQ02_EOF_INT_BIT)
 838 -                                       tp->hwtxq[2].eof_cnt++;
 839 -                               if (status1 & GMAC0_HWTQ01_EOF_INT_BIT)
 840 -                                       tp->hwtxq[1].eof_cnt++;
 841 -                               if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
 842 -                                       tp->hwtxq[0].eof_cnt++;
 843 -#endif //INTERRUPT_SELECT
 844 -#ifndef        INTERRUPT_SELECT
 845 -                       }
 846 -#endif //INTERRUPT_SELECT
 847 -                       if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
 848 -                       {
 849 -                               tp->default_q_intr_cnt++;
 850 -                               toe_gmac_handle_default_rxq(dev, tp);
 851 +               rcv_mask = SPI_read(2,0,0x10);                  // Receive mask
 852 +               rcv_mask |= 0x4F;
 853 +               for(i=0;i<4;i++){
 854 +                       reg_val = BIT(26)|(i<<21)|(10<<16);
 855 +                       SPI_write(3,0,1,reg_val);
 856 +                       msleep(10);
 857 +                       reg_val = SPI_read(3,0,2);
 858 +                       if(reg_val & 0x0c00){
 859 +                               printk("Port%d:Giga mode\n",i);
 860 +                               SPI_write(1,i,0x00,0x300701B1);
 861 +                               SPI_write(1,i,0x00,0x10070181);
 862 +                               switch_pre_link[i]=LINK_UP;
 863 +                               switch_pre_speed[i]=GMAC_SPEED_1000;
 864                         }
 865 -#ifdef CONFIG_SL351x_RXTOE
 866 -                       if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
 867 -                           (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
 868 -                               //printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
 869 -                               toe_gmac_handle_toeq(dev, tp, status1);
 870 -                               //toe_gmac_handle_toeq(dev, toe, tp, status1);
 871 +                       else{
 872 +                               reg_val = BIT(26)|(i<<21)|(5<<16);
 873 +                               SPI_write(3,0,1,reg_val);
 874 +                               msleep(10);
 875 +                               ability = (reg_val = SPI_read(3,0,2)&0x5e0) >>5;
 876 +                               if ((ability & 0x0C)) /* 100M full duplex */
 877 +                               {
 878 +                                       SPI_write(1,i,0x00,0x30050472);
 879 +                                       SPI_write(1,i,0x00,0x10050442);
 880 +                                       printk("Port%d:100M\n",i);
 881 +                                       switch_pre_link[i]=LINK_UP;
 882 +                               switch_pre_speed[i]=GMAC_SPEED_100;
 883 +                               }
 884 +                               else if((ability & 0x03)) /* 10M full duplex */
 885 +                               {
 886 +                                       SPI_write(1,i,0x00,0x30050473);
 887 +                                       SPI_write(1,i,0x00,0x10050443);
 888 +                                       printk("Port%d:10M\n",i);
 889 +                                       switch_pre_link[i]=LINK_UP;
 890 +                                       switch_pre_speed[i]=GMAC_SPEED_10;
 891 +                               }
 892 +                               else{
 893 +                                       SPI_write(1,i,0x00,BIT(16));                    // disable RX
 894 +                                       SPI_write(5,0,0x0E,BIT(i));                     // dicard packet
 895 +                                       while((SPI_read(5,0,0x0C)&BIT(i))==0)           // wait to be empty
 896 +                                               msleep(1);
 897 +
 898 +                                       SPI_write(1,i,0x00,0x20000030);                 // PORT_RST
 899 +                                       switch_pre_link[i]=LINK_DOWN;
 900 +                                       switch_pre_speed[i]=GMAC_SPEED_10;
 901 +                                       rcv_mask &= ~BIT(i);
 902 +                                       SPI_write(2,0,0x10,rcv_mask);                   // Disable Receive
 903 +                               }
 904                         }
 905 -#endif
 906                 }
 907 -               else if (tp->port_id == 1)
 908 -               {
 909 -#ifndef        INTERRUPT_SELECT
 910 -                       if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
 911 -                       {
 912 -                               if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
 913 -                                       tp->hwtxq[3].eof_cnt++;
 914 -                               if (status1 & GMAC1_HWTQ12_EOF_INT_BIT)
 915 -                                       tp->hwtxq[2].eof_cnt++;
 916 -                               if (status1 & GMAC1_HWTQ11_EOF_INT_BIT)
 917 -                                       tp->hwtxq[1].eof_cnt++;
 918 -                               if (status1 & GMAC1_HWTQ10_EOF_INT_BIT)
 919 -                                       tp->hwtxq[0].eof_cnt++;
 920 -#endif //INTERRUPT_SELECT
 921 -#ifndef        INTERRUPT_SELECT
 922 -                       }
 923 -#endif //INTERRUPT_SELECT
 924 -                       if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
 925 -                       {
 926 -                               tp->default_q_intr_cnt++;
 927 -                               toe_gmac_handle_default_rxq(dev, tp);
 928 -                       }
 929 -#ifdef CONFIG_SL351x_RXTOE
 930 -                       if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
 931 -                           (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
 932 -                               //printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
 933 -                               toe_gmac_handle_toeq(dev, tp, status1);
 934 -                               //toe_gmac_handle_toeq(dev, toe, tp, status1);
 935 -                       }
 936  #endif
 937 -               }
 938 +               gmac_get_switch_status(dev);
 939 +               gmac_write_reg(tp->base_addr, GMAC_STATUS, 0x7d, 0x0000007f);
 940 +//             SPI_write(2,0,0x10,rcv_mask);                   // Enable Receive
 941 +               return ;
 942         }
 943 +#endif
 944
 945 +       reg_val = gmac_get_phy_vendor(tp->phy_addr);
 946 +       printk("GMAC-%d Addr %d Vendor ID: 0x%08x\n", tp->port_id, tp->phy_addr, reg_val);
 947
 948 -       // Interrupt Status 0
 949 -       if (status0 & tp->intr0_enabled)
 950 -       {
 951 -
 952 -               #define ERR_INTR_BITS   (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |  \
 953 -                                                                GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |  \
 954 -                                                                GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |  \
 955 -                                                                GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT)
 956 -#ifndef        INTERRUPT_SELECT
 957 -               if (status0 &  ERR_INTR_BITS)
 958 -               {
 959 -                       if ((status0 & GMAC0_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXDERR_INT_BIT))
 960 -                       {
 961 -                               tp->txDerr_cnt[0]++;
 962 -                               printk("GMAC0 TX AHB Bus Error!\n");
 963 -                       }
 964 -                       if ((status0 & GMAC0_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXPERR_INT_BIT))
 965 -                       {
 966 -                               tp->txPerr_cnt[0]++;
 967 -                               printk("GMAC0 Tx Descriptor Protocol Error!\n");
 968 -                       }
 969 -                       if ((status0 & GMAC1_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXDERR_INT_BIT))
 970 -                       {
 971 -                               tp->txDerr_cnt[1]++;
 972 -                               printk("GMAC1 Tx AHB Bus Error!\n");
 973 -                       }
 974 -                       if ((status0 & GMAC1_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXPERR_INT_BIT))
 975 -                       {
 976 -                               tp->txPerr_cnt[1]++;
 977 -                               printk("GMAC1 Tx Descriptor Protocol Error!\n");
 978 -                       }
 979 -
 980 -                       if ((status0 & GMAC0_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXDERR_INT_BIT))
 981 -                       {
 982 -                               tp->RxDerr_cnt[0]++;
 983 -                               printk("GMAC0 Rx AHB Bus Error!\n");
 984 -                       }
 985 -                       if ((status0 & GMAC0_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXPERR_INT_BIT))
 986 -                       {
 987 -                               tp->RxPerr_cnt[0]++;
 988 -                               printk("GMAC0 Rx Descriptor Protocol Error!\n");
 989 -                       }
 990 -                       if ((status0 & GMAC1_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXDERR_INT_BIT))
 991 -                       {
 992 -                               tp->RxDerr_cnt[1]++;
 993 -                               printk("GMAC1 Rx AHB Bus Error!\n");
 994 -                       }
 995 -                       if ((status0 & GMAC1_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXPERR_INT_BIT))
 996 -                       {
 997 -                               tp->RxPerr_cnt[1]++;
 998 -                               printk("GMAC1 Rx Descriptor Protocol Error!\n");
 999 -                       }
1000 -               }
1001 -#endif //INTERRUPT_SELECT
1002 -#ifndef        GMAX_TX_INTR_DISABLED
1003 -               if (tp->port_id == 1 && netif_running(dev) &&
1004 -                       (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
1005 -                       ||
1006 -                       ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT))))
1007 -               {
1008 -                       toe_gmac_tx_complete(&toe_private_data.gmac[1], 0, dev, 1);
1009 -               }
1010 -
1011 -               if (tp->port_id == 0 && netif_running(dev) &&
1012 -                       (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
1013 -                       ||
1014 -                       ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT))))
1015 -               {
1016 -                       toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
1017 -               }
1018 -#endif
1019 -               // clear enabled status bits
1020 -       }
1021 -       // Interrupt Status 4
1022 -#ifndef        INTERRUPT_SELECT
1023 -       if (status4 & tp->intr4_enabled)
1024 -       {
1025 -               #define G1_INTR4_BITS           (0xff000000)
1026 -               #define G0_INTR4_BITS           (0x00ff0000)
1027 -
1028 -               if (tp->port_id == 0)
1029 -               {
1030 -                       if ((status4 & G0_INTR4_BITS) && (tp->intr4_enabled & G0_INTR4_BITS))
1031 -                       {
1032 -                               if (status4 & GMAC0_RESERVED_INT_BIT)
1033 -                                       printk("GMAC0_RESERVED_INT_BIT is ON\n");
1034 -                               if (status4 & GMAC0_MIB_INT_BIT)
1035 -                                       tp->mib_full_cnt++;
1036 -                               if (status4 & GMAC0_RX_PAUSE_ON_INT_BIT)
1037 -                                       tp->rx_pause_on_cnt++;
1038 -                               if (status4 & GMAC0_TX_PAUSE_ON_INT_BIT)
1039 -                                       tp->tx_pause_on_cnt++;
1040 -                               if (status4 & GMAC0_RX_PAUSE_OFF_INT_BIT)
1041 -                                       tp->rx_pause_off_cnt++;
1042 -                               if (status4 & GMAC0_TX_PAUSE_OFF_INT_BIT)
1043 -                                       tp->rx_pause_off_cnt++;
1044 -                               if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
1045 -                                       tp->rx_overrun_cnt++;
1046 -                               if (status4 & GMAC0_STATUS_CHANGE_INT_BIT)
1047 -                                       tp->status_changed_cnt++;
1048 -                       }
1049 -               }
1050 -               else if (tp->port_id == 1)
1051 -               {
1052 -                       if ((status4 & G1_INTR4_BITS) && (tp->intr4_enabled & G1_INTR4_BITS))
1053 -                       {
1054 -                               if (status4 & GMAC1_RESERVED_INT_BIT)
1055 -                                       printk("GMAC1_RESERVED_INT_BIT is ON\n");
1056 -                               if (status4 & GMAC1_MIB_INT_BIT)
1057 -                                       tp->mib_full_cnt++;
1058 -                               if (status4 & GMAC1_RX_PAUSE_ON_INT_BIT)
1059 -                               {
1060 -                                       //printk("Gmac pause on\n");
1061 -                                       tp->rx_pause_on_cnt++;
1062 -                               }
1063 -                               if (status4 & GMAC1_TX_PAUSE_ON_INT_BIT)
1064 -                               {
1065 -                                       //printk("Gmac pause on\n");
1066 -                                       tp->tx_pause_on_cnt++;
1067 -                               }
1068 -                               if (status4 & GMAC1_RX_PAUSE_OFF_INT_BIT)
1069 -                               {
1070 -                                       //printk("Gmac pause off\n");
1071 -                                       tp->rx_pause_off_cnt++;
1072 -                               }
1073 -                               if (status4 & GMAC1_TX_PAUSE_OFF_INT_BIT)
1074 -                               {
1075 -                                       //printk("Gmac pause off\n");
1076 -                                       tp->rx_pause_off_cnt++;
1077 -                               }
1078 -                               if (status4 & GMAC1_RX_OVERRUN_INT_BIT)
1079 -                               {
1080 -                                       //printk("Gmac Rx Overrun \n");
1081 -                                       tp->rx_overrun_cnt++;
1082 -                               }
1083 -                               if (status4 & GMAC1_STATUS_CHANGE_INT_BIT)
1084 -                                       tp->status_changed_cnt++;
1085 -                       }
1086 -               }
1087 -#if 0
1088 -               if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
1089 -               {
1090 -                       // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1091 -//                     mac_stop_rxdma(tp->sc);
1092 -                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
1093 -                               tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
1094 -
1095 -                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
1096 -                               SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
1097 -                       toe_gmac_fill_free_q();
1098 -                       tp->sw_fq_empty_cnt++;
1099 -
1100 -                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
1101 -                               SWFQ_EMPTY_INT_BIT);
1102 -//#if 0
1103 -/*                     if (netif_running(dev))
1104 -                               toe_gmac_handle_default_rxq(dev, tp);
1105 -                       printk("SWFQ_EMPTY_INT_BIT is ON!\n");  // should not be happened */
1106 -//#endif
1107 -               }
1108 -#endif
1109 -       }
1110 -#endif //INTERRUPT_SELECT
1111 -       toe_gmac_enable_interrupt(tp->irq);
1112 -//enable gmac rx function when do RFC 2544
1113 -#ifdef IxscriptMate_1518
1114 -       if (storlink_ctl.pauseoff == 1)
1115 -       {
1116 -               GMAC_CONFIG0_T config0;
1117 -               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1118 -               config0.bits.dis_rx = 0;
1119 -               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1120 -               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1121 -               config0.bits.dis_rx = 0;
1122 -               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1123 -       }
1124 -#endif
1125 -       //printk("gmac_interrupt complete!\n\n");
1126 -//     return IRQ_RETVAL(handled);
1127 -       return  IRQ_RETVAL(1);
1128 -#ifdef CONFIG_SL_NAPI
1129 -}
1130 -#endif
1131 -}
1132 -
1133 -/*----------------------------------------------------------------------
1134 -*      toe_gmac_handle_default_rxq
1135 -*      (1) Get rx Buffer for default Rx queue
1136 -*      (2) notify or call upper-routine to handle it
1137 -*      (3) get a new buffer and insert it into SW free queue
1138 -*      (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
1139 -*----------------------------------------------------------------------*/
1140 -//static inline void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
1141 -static void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
1142 -{
1143 -       TOE_INFO_T                      *toe;
1144 -    GMAC_RXDESC_T      *curr_desc;
1145 -       struct sk_buff          *skb;
1146 -    DMA_RWPTR_T                        rwptr;
1147 -       unsigned int            pkt_size;
1148 -       int                                     max_cnt;
1149 -       unsigned int        desc_count;
1150 -       unsigned int        good_frame, chksum_status, rx_status;
1151 -       struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
1152 -
1153 -//when do ixia RFC 2544 test and packet size is select 1518 bytes,disable gmace rx function immediately after one interrupt come in.
1154 -#ifdef IxscriptMate_1518
1155 -       if (storlink_ctl.pauseoff == 1)
1156 -       {
1157 -               GMAC_CONFIG0_T config0;
1158 -               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1159 -               config0.bits.dis_rx = 1;
1160 -               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1161 -               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1162 -               config0.bits.dis_rx = 1;
1163 -               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1164 -       }
1165 -#endif
1166 -       rwptr.bits32 = readl(&tp->default_qhdr->word1);
1167 -#if 0
1168 -       if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
1169 -       {
1170 -               mac_stop_txdma((struct net_device *)tp->dev);
1171 -               printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
1172 -                               rwptr.bits32, tp->rx_rwptr.bits.rptr);
1173 -               while(1);
1174 -       }
1175 -#endif
1176 -       toe = (TOE_INFO_T *)&toe_private_data;
1177 -       max_cnt = DEFAULT_RXQ_MAX_CNT;
1178 -       while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr)
1179 -//     while (rwptr.bits.rptr != rwptr.bits.wptr)
1180 -       {
1181 -//if packet size is not 1518 for RFC 2544,enable gmac rx function.The other packet size have RX workaround.
1182 -#ifdef IxscriptMate_1518
1183 -       if (storlink_ctl.pauseoff == 1)
1184 -               {
1185 -                       if (pkt_size != 1514)
1186 -                       {
1187 -                                               GMAC_CONFIG0_T config0;
1188 -                                               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1189 -                                               config0.bits.dis_rx = 0;
1190 -                                               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1191 -                                               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1192 -                                               config0.bits.dis_rx = 0;
1193 -                                               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1194 -                       }
1195 -               }
1196 -#endif
1197 -       curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
1198 -//             consistent_sync(curr_desc, sizeof(GMAC_RXDESC_T), PCI_DMA_FROMDEVICE);
1199 -               tp->default_q_cnt++;
1200 -       tp->rx_curr_desc = (unsigned int)curr_desc;
1201 -       rx_status = curr_desc->word0.bits.status;
1202 -       chksum_status = curr_desc->word0.bits.chksum_status;
1203 -       tp->rx_status_cnt[rx_status]++;
1204 -       tp->rx_chksum_cnt[chksum_status]++;
1205 -        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
1206 -               desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
1207 -               good_frame=1;
1208 -               if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
1209 -                       || (pkt_size < 60)
1210 -                   || (chksum_status & 0x4)
1211 -                       || rx_status)
1212 -               {
1213 -                       good_frame = 0;
1214 -                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
1215 -                               printk("%s::derr (GMAC-%d)!!!\n", __func__, tp->port_id);
1216 -                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
1217 -                               printk("%s::perr (GMAC-%d)!!!\n", __func__, tp->port_id);
1218 -                       if (rx_status)
1219 -                       {
1220 -                               if (rx_status == 4 || rx_status == 7)
1221 -                                       isPtr->rx_crc_errors++;
1222 -//                             printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
1223 -                       }
1224 -#ifdef SL351x_GMAC_WORKAROUND
1225 -                       else if (pkt_size < 60)
1226 -                       {
1227 -                               if (tp->short_frames_cnt < GMAC_SHORT_FRAME_THRESHOLD)
1228 -                                       tp->short_frames_cnt++;
1229 -                               if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
1230 -                               {
1231 -                                       GMAC_CONFIG0_T config0;
1232 -                                       config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1233 -                                       config0.bits.dis_rx = 1;
1234 -                                       writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1235 -                                       config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1236 -                                       config0.bits.dis_rx = 1;
1237 -                                       writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1238 -                               }
1239 -                       }
1240 -#endif
1241 -//                     if (chksum_status)
1242 -//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
1243 -                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
1244 -                       dev_kfree_skb_irq(skb);
1245 -               }
1246 -               if (good_frame)
1247 -               {
1248 -                       if (curr_desc->word0.bits.drop)
1249 -                               printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
1250 -//                     if (chksum_status)
1251 -//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
1252 -
1253 -               /* get frame information from the first descriptor of the frame */
1254 -#ifdef SL351x_GMAC_WORKAROUND
1255 -                       if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
1256 -                       {
1257 -                               GMAC_CONFIG0_T config0;
1258 -                               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
1259 -                               config0.bits.dis_rx = 0;
1260 -                               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
1261 -                               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
1262 -                               config0.bits.dis_rx = 0;
1263 -                               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
1264 -                       }
1265 -                       tp->short_frames_cnt = 0;
1266 -#endif
1267 -                       isPtr->rx_packets++;
1268 -                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr - SKB_RESERVE_BYTES)));
1269 -                       if (!skb)
1270 -                       {
1271 -                               printk("Fatal Error!!skb==NULL\n");
1272 -                               goto next_rx;
1273 -                       }
1274 -                       tp->curr_rx_skb = skb;
1275 -                       // consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
1276 -
1277 -       //              curr_desc->word2.buf_adr = 0;
1278 -
1279 -                       skb_reserve (skb, RX_INSERT_BYTES);     /* 16 byte align the IP fields. */
1280 -                       skb_put(skb, pkt_size);
1281 -                       skb->dev = dev;
1282 -                       if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
1283 -                       {
1284 -                               skb->ip_summed = CHECKSUM_UNNECESSARY;
1285 -#ifdef CONFIG_SL351x_NAT
1286 -                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
1287 -                               {
1288 -                                       struct iphdr    *ip_hdr;
1289 -                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
1290 -                                       sl351x_nat_input(skb,
1291 -                                                                       tp->port_id,
1292 -                                                                       (void *)curr_desc->word3.bits.l3_offset,
1293 -                                                                       (void *)curr_desc->word3.bits.l4_offset);
1294 -                               }
1295 -#endif
1296 -                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1297 -#if 0
1298 -#ifdef CONFIG_SL351x_RXTOE
1299 -                               if (storlink_ctl.rx_max_pktsize) {
1300 -                                       struct iphdr    *ip_hdr;
1301 -                                       struct tcphdr   *tcp_hdr;
1302 -                                       int ip_hdrlen;
1303 -
1304 -                                       ip_hdr = (struct iphdr*)&(skb->data[0]);
1305 -                                       if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
1306 -                                          ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
1307 -                                               ip_hdrlen = ip_hdr->ihl << 2;
1308 -                                               tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
1309 -                                               if (tcp_hdr->syn) {
1310 -                                                       struct toe_conn* connection = init_toeq(ip_hdr->version,
1311 -                                                                       ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
1312 -                                                       TCP_SKB_CB(skb)->connection = connection;
1313 -                                                       //      hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
1314 -                                                       //              printk("%s::skb data %x, conn %x, mode %x\n",
1315 -                                                       //                      __func__, skb->data, connection, connection->mode);
1316 -                                               }
1317 -                                       }
1318 -                               }
1319 -#endif
1320 -#endif
1321 -                       }
1322 -                       else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
1323 -                       {
1324 -                               skb->ip_summed = CHECKSUM_UNNECESSARY;
1325 -#ifdef CONFIG_SL351x_NAT
1326 -                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
1327 -                               {
1328 -                                       struct iphdr            *ip_hdr;
1329 -                                       //struct tcphdr         *tcp_hdr;
1330 -                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
1331 -                                       //tcp_hdr = (struct tcphdr *)&(skb->data[curr_desc->word3.bits.l4_offset]);
1332 -                                       if (ip_hdr->protocol == IPPROTO_UDP)
1333 -                                       {
1334 -                                               sl351x_nat_input(skb,
1335 -                                                                               tp->port_id,
1336 -                                                                               (void *)curr_desc->word3.bits.l3_offset,
1337 -                                                                               (void *)curr_desc->word3.bits.l4_offset);
1338 -                                       }
1339 -                                       else if (ip_hdr->protocol == IPPROTO_GRE)
1340 -                                       {
1341 -                                               sl351x_nat_input(skb,
1342 -                                                                       tp->port_id,
1343 -                                                                       (void *)curr_desc->word3.bits.l3_offset,
1344 -                                                                       (void *)curr_desc->word3.bits.l4_offset);
1345 -                                       }
1346 -                               }
1347 -#endif
1348 -                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1349 -                       }
1350 -                       else
1351 -                       {
1352 -                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1353 -                       }
1354 -
1355 -                       netif_rx(skb);  /* socket rx */
1356 -                       dev->last_rx = jiffies;
1357 -
1358 -                       isPtr->rx_bytes += pkt_size;
1359 -
1360 -        }
1361 -
1362 -next_rx:
1363 -               // advance one for Rx default Q 0/1
1364 -               rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
1365 -               SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
1366 -       tp->rx_rwptr.bits32 = rwptr.bits32;
1367 -
1368 -       }
1369 -
1370 -       /* Handles first available packets only then refill the queue. */
1371 -       toe_gmac_fill_free_q();
1372 -}
1373 -
1374 -/*----------------------------------------------------------------------
1375 -* gmac_get_phy_vendor
1376 -*----------------------------------------------------------------------*/
1377 -static unsigned int gmac_get_phy_vendor(int phy_addr)
1378 -{
1379 -    unsigned int       reg_val;
1380 -    reg_val=(mii_read(phy_addr,0x02) << 16) + mii_read(phy_addr,0x03);
1381 -    return reg_val;
1382 -}
1383 -
1384 -/*----------------------------------------------------------------------
1385 -* gmac_set_phy_status
1386 -*----------------------------------------------------------------------*/
1387 -void gmac_set_phy_status(struct net_device *dev)
1388 -{
1389 -       GMAC_INFO_T *tp = dev->priv;
1390 -       GMAC_STATUS_T   status;
1391 -       unsigned int    reg_val, ability,wan_port_id;
1392 -       unsigned int    i = 0;
1393 -
1394 -#ifdef VITESSE_G5SWITCH
1395 -       if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1)){
1396 -#if 0
1397 -               rcv_mask = SPI_read(2,0,0x10);                  // Receive mask
1398 -               rcv_mask |= 0x4F;
1399 -               for(i=0;i<4;i++){
1400 -                       reg_val = BIT(26)|(i<<21)|(10<<16);
1401 -                       SPI_write(3,0,1,reg_val);
1402 -                       msleep(10);
1403 -                       reg_val = SPI_read(3,0,2);
1404 -                       if(reg_val & 0x0c00){
1405 -                               printk("Port%d:Giga mode\n",i);
1406 -                               SPI_write(1,i,0x00,0x300701B1);
1407 -                               SPI_write(1,i,0x00,0x10070181);
1408 -                               switch_pre_link[i]=LINK_UP;
1409 -                               switch_pre_speed[i]=GMAC_SPEED_1000;
1410 -                       }
1411 -                       else{
1412 -                               reg_val = BIT(26)|(i<<21)|(5<<16);
1413 -                               SPI_write(3,0,1,reg_val);
1414 -                               msleep(10);
1415 -                               ability = (reg_val = SPI_read(3,0,2)&0x5e0) >>5;
1416 -                               if ((ability & 0x0C)) /* 100M full duplex */
1417 -                               {
1418 -                                       SPI_write(1,i,0x00,0x30050472);
1419 -                                       SPI_write(1,i,0x00,0x10050442);
1420 -                                       printk("Port%d:100M\n",i);
1421 -                                       switch_pre_link[i]=LINK_UP;
1422 -                               switch_pre_speed[i]=GMAC_SPEED_100;
1423 -                               }
1424 -                               else if((ability & 0x03)) /* 10M full duplex */
1425 -                               {
1426 -                                       SPI_write(1,i,0x00,0x30050473);
1427 -                                       SPI_write(1,i,0x00,0x10050443);
1428 -                                       printk("Port%d:10M\n",i);
1429 -                                       switch_pre_link[i]=LINK_UP;
1430 -                                       switch_pre_speed[i]=GMAC_SPEED_10;
1431 -                               }
1432 -                               else{
1433 -                                       SPI_write(1,i,0x00,BIT(16));                    // disable RX
1434 -                                       SPI_write(5,0,0x0E,BIT(i));                     // dicard packet
1435 -                                       while((SPI_read(5,0,0x0C)&BIT(i))==0)           // wait to be empty
1436 -                                               msleep(1);
1437 -
1438 -                                       SPI_write(1,i,0x00,0x20000030);                 // PORT_RST
1439 -                                       switch_pre_link[i]=LINK_DOWN;
1440 -                                       switch_pre_speed[i]=GMAC_SPEED_10;
1441 -                                       rcv_mask &= ~BIT(i);
1442 -                                       SPI_write(2,0,0x10,rcv_mask);                   // Disable Receive
1443 -                               }
1444 -                       }
1445 -               }
1446 -#endif
1447 -               gmac_get_switch_status(dev);
1448 -               gmac_write_reg(tp->base_addr, GMAC_STATUS, 0x7d, 0x0000007f);
1449 -//             SPI_write(2,0,0x10,rcv_mask);                   // Enable Receive
1450 -               return ;
1451 -       }
1452 -#endif
1453 -
1454 -       reg_val = gmac_get_phy_vendor(tp->phy_addr);
1455 -       printk("GMAC-%d Addr %d Vendor ID: 0x%08x\n", tp->port_id, tp->phy_addr, reg_val);
1456 -
1457 -       switch (tp->phy_mode)
1458 +       switch (tp->phy_mode)
1459         {
1460                 case GMAC_PHY_GMII:
1461                 mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
1462 @@ -3552,6 +2982,7 @@ void gmac_set_phy_status(struct net_devi
1463                 status.bits.link = LINK_DOWN;
1464                 //              clear_bit(__LINK_STATE_START, &dev->state);
1465                 printk("Link Down (0x%04x) ", reg_val);
1466 +#ifdef VITESSE_G5SWITCH
1467                 if(Giga_switch == 1)
1468                 {
1469                                 wan_port_id = 1;
1470 @@ -3565,6 +2996,7 @@ void gmac_set_phy_status(struct net_devi
1471                                 storlink_ctl.link[ tp->port_id] = 0;
1472  #endif
1473                 }
1474 +#endif
1475         }
1476         else
1477         {
1478 @@ -3572,6 +3004,7 @@ void gmac_set_phy_status(struct net_devi
1479                 status.bits.link = LINK_UP;
1480                 //              set_bit(__LINK_STATE_START, &dev->state);
1481                 printk("Link Up (0x%04x) ",reg_val);
1482 +#ifdef VITESSE_G5SWITCH
1483                 if(Giga_switch == 1)
1484                 {
1485                                 wan_port_id = 1;
1486 @@ -3585,6 +3018,7 @@ void gmac_set_phy_status(struct net_devi
1487                                 storlink_ctl.link[ tp->port_id] = 1;
1488  #endif
1489                 }
1490 +#endif
1491         }
1492         //    value = mii_read(PHY_ADDR,0x05);
1493
1494 @@ -3863,6 +3297,7 @@ void gmac_get_phy_status(struct net_devi
1495                         }
1496                 }
1497                 status.bits.link = LINK_UP; /* link up */
1498 +#ifdef VITESSE_G5SWITCH
1499                 if(Giga_switch==1)
1500                 {
1501                                 wan_port_id = 1;
1502 @@ -3874,6 +3309,7 @@ void gmac_get_phy_status(struct net_devi
1503                                 storlink_ctl.link[ tp->port_id] = 1;
1504  #endif
1505                 }
1506 +#endif
1507                 if ((ability & 0x20)==0x20)
1508                 {
1509                         if (tp->flow_control_enable == 0)
1510 @@ -3914,6 +3350,7 @@ void gmac_get_phy_status(struct net_devi
1511         else
1512         {
1513                 status.bits.link = LINK_DOWN; /* link down */
1514 +#ifdef VITESSE_G5SWITCH
1515                 if(Giga_switch == 1)
1516                 {
1517                                 wan_port_id = 1;
1518 @@ -3925,6 +3362,7 @@ void gmac_get_phy_status(struct net_devi
1519                                 storlink_ctl.link[ tp->port_id] = 0;
1520  #endif
1521                 }
1522 +#endif
1523                 if (tp->pre_phy_status == LINK_UP)
1524                 {
1525                         printk("GMAC-%d LINK_Down......\n",tp->port_id);
1526 @@ -4298,86 +3736,102 @@ static void gmac_set_rx_mode(struct net_
1527  }
1528
1529  #ifdef CONFIG_SL_NAPI
1530 +
1531 +static int gmax_rx(struct net_device *dev, int *budget)
1532 +{
1533 +       return 0;
1534 +}
1535 +
1536 +static int gmac_tx(struct net_device *dev, int *budget)
1537 +{
1538 +       return 0;
1539 +}
1540 +
1541  /*----------------------------------------------------------------------
1542  * gmac_rx_poll
1543  *----------------------------------------------------------------------*/
1544  static int gmac_rx_poll(struct net_device *dev, int *budget)
1545  {
1546 -       TOE_INFO_T                      *toe;
1547 -    GMAC_RXDESC_T      *curr_desc;
1548 -       struct sk_buff          *skb;
1549 -    DMA_RWPTR_T                        rwptr;
1550 -    unsigned int data32;
1551 -       unsigned int            pkt_size;
1552 -       unsigned int        desc_count;
1553 -       unsigned int        good_frame, chksum_status, rx_status;
1554 -       int                 rx_pkts_num = 0;
1555 -       int                 quota = min(dev->quota, *budget);
1556 -       GMAC_INFO_T                     *tp = (GMAC_INFO_T *)dev->priv;
1557 -       unsigned int            status4;
1558 -       volatile DMA_RWPTR_T    fq_rwptr;
1559 -       // int                                  max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
1560 -       //unsigned long         rx_old_bytes;
1561 +       TOE_INFO_T      *toe;
1562 +       GMAC_RXDESC_T   *curr_desc;
1563 +       struct sk_buff  *skb;
1564 +       DMA_RWPTR_T     rwptr;
1565 +       unsigned int    data32;
1566 +       unsigned int    pkt_size;
1567 +       unsigned int    desc_count;
1568 +       unsigned int    good_frame, chksum_status, rx_status;
1569 +       int             rx_pkts_num = 0;
1570 +       int             quota = min(dev->quota, *budget);
1571 +       GMAC_INFO_T     *tp = (GMAC_INFO_T *)dev->priv;
1572 +       unsigned int    status1;
1573 +       unsigned int    status4;
1574         struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
1575 -       //unsigned long long    rx_time;
1576 -
1577
1578         BUG_ON(rx_poll_enabled == 0);
1579 -#if 1
1580 -       if (do_again)
1581 -       {
1582 -                       toe_gmac_fill_free_q();
1583 -                       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1584 -                       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1585 -                       //printk("\n%s:: do_again toe_gmac_fill_free_q =======>status4=0x%x =====fq_rwptr =0x%8x======>JKJKJKJKJKJKJKJKJ \n", __func__,status4,fq_rwptr.bits32);
1586 -                       if (fq_rwptr.bits.wptr != fq_rwptr.bits.rptr)
1587 -                       {
1588 -                                               //status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1589 -                                               do_again =0;
1590 -                                               //netif_rx_complete(dev);
1591 -                                               gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4, 0x1);
1592 -                                               fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1593 -                                               rwptr.bits32 = readl(&tp->default_qhdr->word1);
1594 -                       }
1595 -                       else
1596 -                               return 1;
1597 -       }
1598 -#endif
1599 -       rwptr.bits32 = readl(&tp->default_qhdr->word1);
1600 -#if 0
1601 -       if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
1602 -       {
1603 -               mac_stop_txdma((struct net_device *)tp->dev);
1604 -               printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
1605 -                               rwptr.bits32, tp->rx_rwptr.bits.rptr);
1606 -               while(1);
1607 -       }
1608 -#endif
1609 +
1610         toe = (TOE_INFO_T *)&toe_private_data;
1611
1612 -       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1613 -       //printk("%s:---Before-------------->Default Queue HW RW ptr (0x%8x),   fq_rwptr =0x%8x \n",__func__,rwptr.bits32,fq_rwptr.bits32 );
1614 -       //printk("%s:---Before while   rx_pkts_num=%d------rx_finished_idx=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rx_finished_idx,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
1615 -//     while ((--max_cnt) && (rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
1616 +rx_poll_retry:
1617 +       status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
1618 +       if (status1 & 1) {
1619 +               writel(1, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
1620 +       }
1621
1622 +       rwptr.bits32 = readl(&tp->default_qhdr->word1);
1623         while ((rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
1624         {
1625 -
1626 -       curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
1627 +               curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
1628                 tp->default_q_cnt++;
1629 -       tp->rx_curr_desc = (unsigned int)curr_desc;
1630 -       rx_status = curr_desc->word0.bits.status;
1631 -       chksum_status = curr_desc->word0.bits.chksum_status;
1632 -       tp->rx_status_cnt[rx_status]++;
1633 -       tp->rx_chksum_cnt[chksum_status]++;
1634 -        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
1635 +               tp->rx_curr_desc = (unsigned int)curr_desc;
1636 +               rx_status = curr_desc->word0.bits.status;
1637 +               chksum_status = curr_desc->word0.bits.chksum_status;
1638 +               tp->rx_status_cnt[rx_status]++;
1639 +               tp->rx_chksum_cnt[chksum_status]++;
1640 +               pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
1641                 desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
1642                 good_frame=1;
1643 +
1644 +               if (0) {
1645 +
1646 +                               int free, busy;
1647 +                               uint32_t rwptr1;
1648 +                               uint32_t rwptr2;
1649 +
1650 +                               rwptr1 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1651 +                               free = (GET_WPTR(rwptr1) - GET_RPTR(rwptr1)) & 0xFF;
1652 +
1653 +                               rwptr2 = readl(&tp->default_qhdr->word1);
1654 +                               busy = (GET_RPTR(rwptr2) - GET_WPTR(rwptr2)) & 0xFF;
1655 +
1656 +                               if (GET_WPTR(rwptr1) == GET_RPTR(rwptr1)) {
1657 +                                       printk("frame  status: %d\n"
1658 +                                              "SWFQ: wptr: %hu, rptr: %hu, free: %d\n"
1659 +                                              "GMAC: wptr: %hu, rptr: %hu, free: %d\n",
1660 +                                              rx_status,
1661 +                                              GET_WPTR(rwptr1), GET_RPTR(rwptr1), free,
1662 +                                              GET_WPTR(rwptr2), GET_RPTR(rwptr2), busy);
1663 +                               }
1664 +               }
1665 +
1666 +               {
1667 +                       GMAC_RXDESC_T   *fq_desc;
1668 +                       void *data;
1669 +                       struct sk_buff *skb;
1670 +                       unsigned short idx;
1671 +
1672 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
1673 +                       idx = (unsigned short)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES + 4));
1674 +
1675 +                       BUG_ON(idx > TOE_SW_FREEQ_DESC_NUM);
1676 +                       BUG_ON(skb == NULL);
1677 +                       fq_desc = (GMAC_RXDESC_T*)toe->swfq_desc_base + idx;
1678 +                       fq_desc->word2.buf_adr = 0;
1679 +               }
1680 +
1681                 if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
1682 -                       || (pkt_size < 60)
1683 +                   || (pkt_size < 60)
1684                     || (chksum_status & 0x4)
1685                     || rx_status )
1686 -//                     || rx_status || (rwptr.bits.rptr > rwptr.bits.wptr ))
1687                 {
1688                         good_frame = 0;
1689                         if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
1690 @@ -4388,7 +3842,6 @@ static int gmac_rx_poll(struct net_devic
1691                         {
1692                                 if (rx_status == 4 || rx_status == 7)
1693                                         isPtr->rx_crc_errors++;
1694 -//                             printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
1695                         }
1696  #ifdef SL351x_GMAC_WORKAROUND
1697                         else if (pkt_size < 60)
1698 @@ -4407,17 +3860,32 @@ static int gmac_rx_poll(struct net_devic
1699                                 }
1700                         }
1701  #endif
1702 -//                     if (chksum_status)
1703 -//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
1704                         skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
1705 -                       dev_kfree_skb_irq(skb);
1706 +                       dev_kfree_skb(skb);
1707 +
1708 +                       if (0) {
1709 +                               int free, busy;
1710 +                               uint32_t rwptr1;
1711 +                               uint32_t rwptr2;
1712 +
1713 +                               rwptr1 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1714 +                               free = (GET_WPTR(rwptr1) - GET_RPTR(rwptr1)) & 0xFF;
1715 +
1716 +                               rwptr2 = readl(&tp->default_qhdr->word1);
1717 +                               busy = (GET_RPTR(rwptr2) - GET_WPTR(rwptr2)) & 0xFF;
1718 +
1719 +                               printk("frame  status: %d\n"
1720 +                                      "SWFQ: wptr: %hu, rptr: %hu, free: %d\n"
1721 +                                      "GMAC: wptr: %hu, rptr: %hu, free: %d\n",
1722 +                                      rx_status,
1723 +                                      GET_WPTR(rwptr1), GET_RPTR(rwptr1), free,
1724 +                                      GET_WPTR(rwptr2), GET_RPTR(rwptr2), busy);
1725 +                       }
1726                 }
1727                 if (good_frame)
1728                 {
1729                         if (curr_desc->word0.bits.drop)
1730                                 printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
1731 -//                     if (chksum_status)
1732 -//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
1733
1734  #ifdef SL351x_GMAC_WORKAROUND
1735                         if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
1736 @@ -4432,225 +3900,118 @@ static int gmac_rx_poll(struct net_devic
1737                         }
1738                         tp->short_frames_cnt = 0;
1739  #endif
1740 -               /* get frame information from the first descriptor of the frame */
1741 +                       /* get frame information from the first descriptor of the frame */
1742                         isPtr->rx_packets++;
1743 -                       //consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
1744 +                       consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
1745                         skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
1746                         tp->curr_rx_skb = skb;
1747 -       //              curr_desc->word2.buf_adr = 0;
1748
1749 -                   //skb_reserve (skb, SKB_RESERVE_BYTES);
1750                         skb_reserve (skb, RX_INSERT_BYTES);     /* 2 byte align the IP fields. */
1751 -                       //if ((skb->tail+pkt_size) > skb->end )
1752 -                       //printk("%s::------------->Here skb->len=%d,pkt_size= %d,skb->head=0x%x,skb->tail= 0x%x, skb->end= 0x%x\n", __func__, skb->len, pkt_size,skb->head,skb->tail,skb->end);
1753                         skb_put(skb, pkt_size);
1754
1755 -
1756                         skb->dev = dev;
1757                         if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
1758                         {
1759                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1760 -#ifdef CONFIG_SL351x_NAT
1761 -                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
1762 -                               {
1763 -                                       struct iphdr    *ip_hdr;
1764 -                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
1765 -                                       sl351x_nat_input(skb,
1766 -                                                                       tp->port_id,
1767 -                                                                       (void *)curr_desc->word3.bits.l3_offset,
1768 -                                                                       (void *)curr_desc->word3.bits.l4_offset);
1769 -                               }
1770 -#endif
1771                                 skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1772 -#if 0
1773 -#ifdef CONFIG_SL351x_RXTOE
1774 -                               if (storlink_ctl.rx_max_pktsize) {
1775 -                                       struct iphdr    *ip_hdr;
1776 -                                       struct tcphdr   *tcp_hdr;
1777 -                                       int ip_hdrlen;
1778 -
1779 -                                       ip_hdr = (struct iphdr*)&(skb->data[0]);
1780 -                                       if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
1781 -                                          ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
1782 -                                               ip_hdrlen = ip_hdr->ihl << 2;
1783 -                                               tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
1784 -                                               if (tcp_hdr->syn) {
1785 -                                                       struct toe_conn* connection = init_toeq(ip_hdr->version,
1786 -                                                                       ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
1787 -                                                       TCP_SKB_CB(skb)->connection = connection;
1788 -                                                       //      hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
1789 -                                                       //              printk("%s::skb data %x, conn %x, mode %x\n",
1790 -                                                       //                      __func__, skb->data, connection, connection->mode);
1791 -                                               }
1792 -                                       }
1793 -                               }
1794 -#endif
1795 -#endif
1796                         }
1797                         else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
1798                         {
1799                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1800 -#ifdef CONFIG_SL351x_NAT
1801 -                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
1802 -                               {
1803 -                                       struct iphdr    *ip_hdr;
1804 -                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
1805 -                                       if (ip_hdr->protocol == IPPROTO_UDP)
1806 -                                       {
1807 -                                               sl351x_nat_input(skb,
1808 -                                                                               tp->port_id,
1809 -                                                                               (void *)curr_desc->word3.bits.l3_offset,
1810 -                                                                               (void *)curr_desc->word3.bits.l4_offset);
1811 -                                       }
1812 -                                       else if (ip_hdr->protocol == IPPROTO_GRE)
1813 -                                       {
1814 -                                               sl351x_nat_input(skb,
1815 -                                                                       tp->port_id,
1816 -                                                                       (void *)curr_desc->word3.bits.l3_offset,
1817 -                                                                       (void *)curr_desc->word3.bits.l4_offset);
1818 -                                       }
1819 -                               }
1820 -#endif
1821                                 skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1822                         }
1823                         else
1824                         {
1825                                 skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
1826                         }
1827 -                       //netif_rx(skb);  /* socket rx */
1828 +
1829                         netif_receive_skb(skb); //For NAPI
1830                         dev->last_rx = jiffies;
1831
1832                         isPtr->rx_bytes += pkt_size;
1833 -                       //printk("------------------->isPtr->rx_bytes = %d\n",isPtr->rx_bytes);
1834 -
1835 +               }
1836
1837 -        }
1838                 // advance one for Rx default Q 0/1
1839                 rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
1840                 SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
1841 -       tp->rx_rwptr.bits32 = rwptr.bits32;
1842 +               tp->rx_rwptr.bits32 = rwptr.bits32;
1843                 rx_pkts_num++;
1844 -               //rwptr.bits32 = readl(&tp->default_qhdr->word1);//try read default_qhdr again
1845 -               //fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1846 -               //printk("%s:---Loop  -------->rx_pkts_num=%d------------>Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits32,fq_rwptr.bits32 );
1847 -#if 0
1848 -               if ((status4 & 0x1) == 0)
1849 -               {
1850 -                       //if (!((dev->last_rx <= (rx_time + 2)) &&  (isPtr->rx_bytes > (rx_old_bytes + 1000000 ))))
1851 -                       if (tp->total_q_cnt_napi < 1024)
1852 -                       {
1853 -                               tp->total_q_cnt_napi++;
1854 -                               toe_gmac_fill_free_q();  //for iperf test disable
1855 -                       }
1856 -                       //else
1857 -                               //printk("%s:---isPtr->rx_bytes =%u , rx_old_bytes =%u\n",__func__,isPtr->rx_bytes,rx_old_bytes );
1858 +               // rwptr.bits32 = readl(&tp->default_qhdr->word1);
1859
1860 +               status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1861 +               if (status4 & 1) {
1862 +                       writel(status4 & SWFQ_EMPTY_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
1863                 }
1864 +
1865 +               toe_gmac_fill_free_q(5);
1866 +       }
1867 +
1868 +#if 0
1869 +       /* avoid races with hard_start_xmit() */
1870 +
1871 +       spin_lock(&gmac_fq_lock);
1872 +       toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
1873 +       spin_unlock(&gmac_fq_lock);
1874  #endif
1875 -               //rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
1876 -               //printk("%s:---Loop  -------->rx_pkts_num=%d----rwptr.bits.rptr=0x%x-------->Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits32,fq_rwptr.bits32 );
1877 -               //printk("%s:---Loop  rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
1878 +
1879 +       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1880 +       if (status4 & 1)
1881 +       {
1882 +               writel(status4 & SWFQ_EMPTY_INT_BIT, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
1883 +               status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
1884 +               toe_gmac_fill_free_q(rx_pkts_num);
1885         }
1886 -       // advance one for Rx default Q 0/1
1887
1888 -               //rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
1889 -               //SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
1890 -       //tp->rx_rwptr.bits32 = rwptr.bits32;
1891 -       //rwptr.bits.rptr = rwptr.bits.rptr;
1892 +       rwptr.bits32 = readl(&tp->default_qhdr->word1);
1893 +       if (rwptr.bits.rptr != rwptr.bits.wptr &&
1894 +           quota > rx_pkts_num)
1895 +               goto rx_poll_retry;
1896
1897         dev->quota -= rx_pkts_num;
1898         *budget -= rx_pkts_num;
1899
1900 -       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);//try read SWFQ empty again
1901 -       //fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
1902 -       rwptr.bits32 = readl(&tp->default_qhdr->word1); //try read default_qhdr again
1903 -       //printk("%s:---After    rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
1904 -//     if (rwptr.bits.rptr > rwptr.bits.wptr )
1905 -//                     {
1906 -                               //toe_gmac_disable_rx(dev);
1907 -                               //wait_event_interruptible_timeout(freeq_wait,
1908 -                                       //(rx_pkts_num == 100), CMTP_INTEROP_TIMEOUT);
1909 -                               //printk("\n%s:: return 22222=======> rx_pkts_num =%d,   rwptr.bits.rptr=%d,   rwptr.bits.wptr = %d ====---------=======>JKJKJKJKJK\n",
1910 -                                       //__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
1911 -//                             return 1;
1912 -//                     }
1913 -
1914 -       if (rwptr.bits.rptr == rwptr.bits.wptr)
1915 +       /* Receive queue is empty now */
1916 +       if (quota >= rx_pkts_num)
1917         {
1918 -               // unsigned int data32;
1919 -                       //printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr]   rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
1920 -
1921 -           /* Receive descriptor is empty now */
1922 -#if 1
1923 -     if (status4 & 0x1)
1924 -                       {
1925 -                               do_again =1;
1926 -                               //writel(0x40400000, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_4_REG); //disable SWFQ empty interrupt
1927 -                               //toe_gmac_disable_interrupt(tp->irq);
1928 -                               tp->sw_fq_empty_cnt++;
1929 -                               //toe_gmac_disable_rx(dev);
1930 -                               writel(0x07960202, TOE_GMAC0_BASE+GMAC_CONFIG0);
1931 -                               writel(0x07960202, TOE_GMAC1_BASE+GMAC_CONFIG0);
1932 -                               //printk("\n%s ::  freeq int-----tp->sw_fq_empty_cnt  =%d---------====================----------------->\n",__func__,tp->sw_fq_empty_cnt);
1933 -                               //while ((fq_rwptr.bits.wptr >= (fq_rwptr.bits.rptr+256)) || (fq_rwptr.bits.wptr <= (fq_rwptr.bits.rptr+256)))
1934 -                               //{
1935 -                                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
1936 -                                       //0x1);
1937 -                               //printk("\n%s::fq_rwptr.wrptr = %x =======> ===========>here \n", __func__,fq_rwptr.bits32);
1938 -                               //if ((status4 & 0x1) == 0)
1939 -                                       //break;
1940 -                                return 1;
1941 -                               //}
1942 +               unsigned long flags;
1943
1944 +               netif_rx_complete(dev);
1945 +               rx_poll_enabled = 0;
1946 +#if 0
1947 +               status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
1948 +               if (status1 & 1) {
1949 +                       if (netif_rx_reschedule(dev, rx_pkts_num)) {
1950 +                               rx_poll_enabled = 1;
1951 +                               return 1;
1952                         }
1953 +               }
1954  #endif
1955 -        //toe_gmac_fill_free_q();
1956 -        netif_rx_complete(dev);
1957 -
1958 -               rx_poll_enabled = 0;
1959
1960 -               data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1961 -               if (tp->port_id == 0)
1962 -                               data32 |= DEFAULT_Q0_INT_BIT;
1963 -               else
1964 -                               data32 |= DEFAULT_Q1_INT_BIT;
1965 -               writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1966 +               spin_lock_irqsave(&gmac_fq_lock, flags);
1967
1968                 data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
1969                 if (tp->port_id == 0)
1970 -                               data32 |= DEFAULT_Q0_INT_BIT;
1971 +                       data32 |= DEFAULT_Q0_INT_BIT;
1972                 else
1973 -                               data32 |= DEFAULT_Q1_INT_BIT;
1974 +                       data32 |= DEFAULT_Q1_INT_BIT;
1975                 writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
1976
1977 -               data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
1978 +               data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1979                 if (tp->port_id == 0)
1980 -                               data32 |= DEFAULT_Q0_INT_BIT;
1981 +                       data32 |= DEFAULT_Q0_INT_BIT;
1982                 else
1983 -                               data32 |= DEFAULT_Q1_INT_BIT;
1984 -               writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
1985 +                       data32 |= DEFAULT_Q1_INT_BIT;
1986 +               writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1987
1988 -        // enable GMAC-0 rx interrupt
1989 -        // class-Q & TOE-Q are implemented in future
1990 -        //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1991 -        //if (tp->port_id == 0)
1992 -               //data32 |= DEFAULT_Q0_INT_BIT;
1993 -        //else
1994 -               //data32 |= DEFAULT_Q1_INT_BIT;
1995 -        //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
1996 -               writel(0x3, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
1997 -               //printk("\n%s::netif_rx_complete-->  rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x ====---------=======>JKJKJKJKJK\n",
1998 -               //__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
1999 -        writel(0x07960200, TOE_GMAC0_BASE+GMAC_CONFIG0);
2000 -               writel(0x07960200, TOE_GMAC1_BASE+GMAC_CONFIG0);
2001 -        return 0;
2002 -    }
2003 -    else
2004 -    {
2005 -        //printk("\n%s:: return 1 -->status4= 0x%x,rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x  ======> \n", __func__,status4,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
2006 -        return 1;
2007 -    }
2008 +               spin_unlock_irqrestore(&gmac_fq_lock, flags);
2009 +
2010 +               return 0;
2011 +       }
2012 +       else
2013 +       {
2014 +               /* not done, will call ->poll() later. */
2015 +               return 1;
2016 +       }
2017  }
2018  #endif
2019
2020 @@ -5114,6 +4475,7 @@ void sl351x_poll_gmac_hanged_status(u32
2021                         {
2022                                 sl351x_nat_workaround_cnt++;
2023                                 sl351x_nat_workaround_handler();
2024 +                               printk("%():%d - workaround\n", __func__, __LINE__);
2025                         }
2026  #endif
2027  #endif
2028 @@ -5124,6 +4486,7 @@ void sl351x_poll_gmac_hanged_status(u32
2029         }
2030
2031  do_workaround:
2032 +       printk("doing workaround ?!\n");
2033
2034         gmac_initialized = 0;
2035         if (hanged_state)
2036 @@ -5290,6 +4653,7 @@ static void sl351x_gmac_release_swtx_q(v
2037         GMAC_SWTXQ_T    *swtxq;
2038         DMA_RWPTR_T             rwptr;
2039
2040 +       printk("**** %s():%d\n", __func__, __LINE__);
2041         toe = (TOE_INFO_T *)&toe_private_data;
2042         tp = (GMAC_INFO_T *)&toe->gmac[0];
2043         for (i=0; i<GMAC_NUM; i++, tp++)
2044 @@ -5341,6 +4705,7 @@ static void sl351x_gmac_release_rx_q(voi
2045         volatile GMAC_RXDESC_T  *curr_desc;
2046         struct sk_buff                  *skb;
2047
2048 +       printk("**** %s():%d\n", __func__, __LINE__);
2049         toe = (TOE_INFO_T *)&toe_private_data;
2050         tp = (GMAC_INFO_T *)&toe->gmac[0];
2051         for (i=0; i<GMAC_NUM; i++, tp++)
2052 @@ -5374,6 +4739,7 @@ static void sl351x_gmac_release_class_q(
2053         volatile GMAC_RXDESC_T  *curr_desc;
2054         struct sk_buff                  *skb;
2055
2056 +       printk("**** %s():%d\n", __func__, __LINE__);
2057         toe = (TOE_INFO_T *)&toe_private_data;
2058         classq = (CLASSQ_INFO_T *)&toe->classq[0];
2059         for (i=0; i<TOE_CLASS_QUEUE_NUM; i++, classq++)
2060 @@ -5410,6 +4776,7 @@ static void sl351x_gmac_release_toe_q(vo
2061         GMAC_RXDESC_T   *toe_curr_desc;
2062         struct sk_buff                  *skb;
2063
2064 +       printk("**** %s():%d\n", __func__, __LINE__);
2065         toe = (TOE_INFO_T *)&toe_private_data;
2066         toe_qhdr = (TOE_QHDR_T *)TOE_TOE_QUE_HDR_BASE;
2067         for (i=0; i<TOE_TOE_QUEUE_NUM; i++, toe_qhdr++)
2068 Index: linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_gmac.h
2069 ===================================================================
2070 --- linux-2.6.23.17.orig/include/asm-arm/arch-sl2312/sl351x_gmac.h
2071 +++ linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_gmac.h
2072 @@ -107,7 +107,7 @@
2073   * The base address and descriptor number are configured at
2074   * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
2075   **********************************************************************/
2076 -#define TOE_SW_FREEQ_DESC_POWER                10
2077 +#define TOE_SW_FREEQ_DESC_POWER                8
2078  #define TOE_SW_FREEQ_DESC_NUM          (1<<TOE_SW_FREEQ_DESC_POWER)
2079  #define TOE_HW_FREEQ_DESC_POWER                8
2080  #define TOE_HW_FREEQ_DESC_NUM          (1<<TOE_HW_FREEQ_DESC_POWER)
2081 @@ -123,12 +123,12 @@
2082  #define TOE_DEFAULT_Q0_DESC_NUM                (1<<TOE_DEFAULT_Q0_DESC_POWER)
2083  #define TOE_DEFAULT_Q1_DESC_POWER      8
2084  #define TOE_DEFAULT_Q1_DESC_NUM                (1<<TOE_DEFAULT_Q1_DESC_POWER)
2085 -#define TOE_TOE_DESC_POWER                     8
2086 -#define TOE_TOE_DESC_NUM                       (1<<TOE_TOE_DESC_POWER)
2087 +#define TOE_TOE_DESC_POWER             8
2088 +#define TOE_TOE_DESC_NUM               (1<<TOE_TOE_DESC_POWER)
2089  #define TOE_CLASS_DESC_POWER           8
2090 -#define TOE_CLASS_DESC_NUM                     (1<<TOE_CLASS_DESC_POWER)
2091 -#define TOE_INTR_DESC_POWER                    8
2092 -#define TOE_INTR_DESC_NUM                      (1<<TOE_INTR_DESC_POWER)
2093 +#define TOE_CLASS_DESC_NUM             (1<<TOE_CLASS_DESC_POWER)
2094 +#define TOE_INTR_DESC_POWER            8
2095 +#define TOE_INTR_DESC_NUM              (1<<TOE_INTR_DESC_POWER)
2096
2097  #define TOE_TOE_QUEUE_MAX                      64
2098  #define TOE_TOE_QUEUE_NUM                      64