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* refresh storm patches * disable BX in uClibc config, add ethernet and watchdog...
[librecmc/librecmc.git] / target / linux / storm / patches / 1002-gmac.patch
1 --- /dev/null
2 +++ b/drivers/net/sl2312_emac.c
3 @@ -0,0 +1,4604 @@
4 +#include <linux/module.h>
5 +#include <linux/kernel.h>
6 +#include <linux/compiler.h>
7 +#include <linux/pci.h>
8 +#include <linux/init.h>
9 +#include <linux/ioport.h>
10 +#include <linux/netdevice.h>
11 +#include <linux/etherdevice.h>
12 +#include <linux/rtnetlink.h>
13 +#include <linux/delay.h>
14 +#include <linux/ethtool.h>
15 +#include <linux/mii.h>
16 +#include <linux/completion.h>
17 +#include <asm/hardware.h>
18 +#include <asm/io.h>
19 +#include <asm/irq.h>
20 +#include <asm/semaphore.h>
21 +#include <asm/arch-sl2312/irqs.h>
22 +#include <asm/arch/it8712.h>
23 +#include <asm/arch/sl2312.h>
24 +#include <linux/mtd/kvctl.h>
25 +#include <linux/sysctl_storlink.h>
26 +
27 +#define BIG_ENDIAN     0
28 +
29 +#define GMAC_DEBUG      0
30 +
31 +#define GMAC_PHY_IF     2
32 +
33 +/* define PHY address */
34 +#define HPHY_ADDR   0x01
35 +#define GPHY_ADDR   0x02
36 +
37 +#define CONFIG_ADM_6999 1
38 +/* define chip information */
39 +#define DRV_NAME                       "SL2312"
40 +#define DRV_VERSION                    "0.1.1"
41 +#define SL2312_DRIVER_NAME  DRV_NAME " Fast Ethernet driver " DRV_VERSION
42 +
43 +/* define TX/RX descriptor parameter */
44 +#define MAX_ETH_FRAME_SIZE     1920
45 +#define TX_BUF_SIZE                    MAX_ETH_FRAME_SIZE
46 +#define TX_DESC_NUM                    128
47 +#define TX_BUF_TOT_LEN         (TX_BUF_SIZE * TX_DESC_NUM)
48 +#define RX_BUF_SIZE                    MAX_ETH_FRAME_SIZE
49 +#define RX_DESC_NUM                    256
50 +#define RX_BUF_TOT_LEN         (RX_BUF_SIZE * RX_DESC_NUM)
51 +#define MAX_ISR_WORK        20
52 +
53 +unsigned int int_status = 0;
54 +
55 +/* define GMAC base address */
56 +#define GMAC_PHYSICAL_BASE_ADDR            (SL2312_GMAC_BASE)
57 +#define GMAC_BASE_ADDR                     (IO_ADDRESS(GMAC_PHYSICAL_BASE_ADDR))
58 +#define GMAC_GLOBAL_BASE_ADDR       (IO_ADDRESS(SL2312_GLOBAL_BASE))
59 +
60 +#define GMAC0_BASE                  (IO_ADDRESS(SL2312_GMAC0_BASE))
61 +#define GMAC1_BASE                  (IO_ADDRESS(SL2312_GMAC1_BASE))
62 +
63 +/* memory management utility */
64 +#define DMA_MALLOC(size,handle)                pci_alloc_consistent(NULL,size,handle)
65 +#define DMA_MFREE(mem,size,handle)     pci_free_consistent(NULL,size,mem,handle)
66 +
67 +//#define gmac_read_reg(offset)       (readl(GMAC_BASE_ADDR + offset))
68 +//#define gmac_write_reg(offset,data,mask)  writel( (gmac_read_reg(offset)&~mask) |(data&mask),(GMAC_BASE_ADDR+offset))
69 +
70 +/* define owner bit */
71 +#define CPU            0
72 +#define DMA            1
73 +
74 +#define ACTIVE      1
75 +#define NONACTIVE   0
76 +
77 +#define CONFIG_SL_NAPI
78 +
79 +#ifndef CONFIG_SL2312_MPAGE
80 +#define CONFIG_SL2312_MPAGE
81 +#endif
82 +
83 +#ifdef CONFIG_SL2312_MPAGE
84 +#include <linux/skbuff.h>
85 +#include <linux/ip.h>
86 +#include <linux/tcp.h>
87 +#endif
88 +
89 +#ifndef CONFIG_TXINT_DISABLE
90 +//#define CONFIG_TXINT_DISABLE
91 +#endif
92 +
93 +enum phy_state
94 +{
95 +    LINK_DOWN   = 0,
96 +    LINK_UP     = 1
97 +};
98 +
99 +
100 +/* transmit timeout value */
101 +#define TX_TIMEOUT  (6*HZ)
102 +
103 +/***************************************/
104 +/* the offset address of GMAC register */
105 +/***************************************/
106 +enum GMAC_REGISTER {
107 +       GMAC_STA_ADD0   = 0x0000,
108 +       GMAC_STA_ADD1   = 0x0004,
109 +       GMAC_STA_ADD2   = 0x0008,
110 +       GMAC_RX_FLTR    = 0x000c,
111 +       GMAC_MCAST_FIL0 = 0x0010,
112 +       GMAC_MCAST_FIL1 = 0x0014,
113 +       GMAC_CONFIG0    = 0x0018,
114 +       GMAC_CONFIG1    = 0x001c,
115 +       GMAC_CONFIG2    = 0x0020,
116 +       GMAC_BNCR               = 0x0024,
117 +       GMAC_RBNR               = 0x0028,
118 +       GMAC_STATUS             = 0x002c,
119 +       GMAC_IN_DISCARDS= 0x0030,
120 +       GMAC_IN_ERRORS  = 0x0034,
121 +       GMAC_IN_MCAST   = 0x0038,
122 +       GMAC_IN_BCAST   = 0x003c,
123 +       GMAC_IN_MAC1    = 0x0040,
124 +       GMAC_IN_MAC2    = 0x0044
125 +};
126 +
127 +/*******************************************/
128 +/* the offset address of GMAC DMA register */
129 +/*******************************************/
130 +enum GMAC_DMA_REGISTER {
131 +       GMAC_DMA_DEVICE_ID              = 0xff00,
132 +       GMAC_DMA_STATUS                 = 0xff04,
133 +       GMAC_TXDMA_CTRL                 = 0xff08,
134 +       GMAC_TXDMA_FIRST_DESC   = 0xff0c,
135 +       GMAC_TXDMA_CURR_DESC    = 0xff10,
136 +       GMAC_RXDMA_CTRL                 = 0xff14,
137 +       GMAC_RXDMA_FIRST_DESC   = 0xff18,
138 +       GMAC_RXDMA_CURR_DESC    = 0xff1c,
139 +};
140 +
141 +/*******************************************/
142 +/* the register structure of GMAC          */
143 +/*******************************************/
144 +typedef union
145 +{
146 +       unsigned int bits32;
147 +       struct bit1_0004
148 +       {
149 +#if (BIG_ENDIAN==1)
150 +               unsigned int sta_add2_l16       : 16;   /* station MAC address2 bits 15 to 0 */
151 +               unsigned int sta_add1_h16       : 16;   /* station MAC address1 bits 47 to 32 */
152 +#else
153 +               unsigned int sta_add1_h16       : 16;   /* station MAC address1 bits 47 to 32 */
154 +               unsigned int sta_add2_l16       : 16;   /* station MAC address2 bits 15 to 0 */
155 +#endif
156 +       } bits;
157 +} GMAC_STA_ADD1_T;
158 +
159 +typedef union
160 +{
161 +       unsigned int bits32;
162 +       struct bit1_000c
163 +       {
164 +#if (BIG_ENDIAN==1)
165 +               unsigned int                            : 27;
166 +               unsigned int error                      :  1;   /* enable receive of all error frames */
167 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
168 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
169 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
170 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
171 +#else
172 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
173 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
174 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
175 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
176 +               unsigned int error                      :  1;   /* enable receive of all error frames */
177 +               unsigned int                            : 27;
178 +#endif
179 +       } bits;
180 +} GMAC_RX_FLTR_T;
181 +
182 +typedef union
183 +{
184 +       unsigned int bits32;
185 +       struct bit1_0018
186 +       {
187 +#if (BIG_ENDIAN==1)
188 +               unsigned int : 10;
189 +               unsigned int inv_rx_clk     : 1;        /* Inverse RX Clock */
190 +               unsigned int rising_latch   : 1;
191 +        unsigned int rx_tag_remove  :  1;   /* Remove Rx VLAN tag */
192 +        unsigned int ipv6_tss_rx_en :  1;   /* IPv6 TSS RX enable */
193 +        unsigned int ipv4_tss_rx_en :  1;   /* IPv4 TSS RX enable */
194 +        unsigned int rgmii_en       :  1;   /* RGMII in-band status enable */
195 +               unsigned int tx_fc_en           :  1;   /* TX flow control enable */
196 +               unsigned int rx_fc_en           :  1;   /* RX flow control enable */
197 +               unsigned int sim_test           :  1;   /* speed up timers in simulation */
198 +               unsigned int dis_col            :  1;   /* disable 16 collisions abort function */
199 +               unsigned int dis_bkoff          :  1;   /* disable back-off function */
200 +               unsigned int max_len            :  3;   /* maximum receive frame length allowed */
201 +               unsigned int adj_ifg            :  4;   /* adjust IFG from 96+/-56 */
202 +        unsigned int                :  1;   /* reserved */
203 +               unsigned int loop_back          :  1;   /* transmit data loopback enable */
204 +               unsigned int dis_rx                     :  1;   /* disable receive */
205 +               unsigned int dis_tx                     :  1;   /* disable transmit */
206 +#else
207 +               unsigned int dis_tx                     :  1;   /* disable transmit */
208 +               unsigned int dis_rx                     :  1;   /* disable receive */
209 +               unsigned int loop_back          :  1;   /* transmit data loopback enable */
210 +        unsigned int                :  1;   /* reserved */
211 +               unsigned int adj_ifg            :  4;   /* adjust IFG from 96+/-56 */
212 +               unsigned int max_len            :  3;   /* maximum receive frame length allowed */
213 +               unsigned int dis_bkoff          :  1;   /* disable back-off function */
214 +               unsigned int dis_col            :  1;   /* disable 16 collisions abort function */
215 +               unsigned int sim_test           :  1;   /* speed up timers in simulation */
216 +               unsigned int rx_fc_en           :  1;   /* RX flow control enable */
217 +               unsigned int tx_fc_en           :  1;   /* TX flow control enable */
218 +        unsigned int rgmii_en       :  1;   /* RGMII in-band status enable */
219 +        unsigned int ipv4_tss_rx_en :  1;   /* IPv4 TSS RX enable */
220 +        unsigned int ipv6_tss_rx_en :  1;   /* IPv6 TSS RX enable */
221 +        unsigned int rx_tag_remove  :  1;   /* Remove Rx VLAN tag */
222 +               unsigned int rising_latch   :  1;
223 +               unsigned int inv_rx_clk : 1;    /* Inverse RX Clock */
224 +               unsigned int : 10;
225 +#endif
226 +       } bits;
227 +} GMAC_CONFIG0_T;
228 +
229 +typedef union
230 +{
231 +       unsigned int bits32;
232 +       struct bit1_001c
233 +       {
234 +#if (BIG_ENDIAN==1)
235 +               unsigned int                            : 28;
236 +               unsigned int buf_size           :  4;   /* per packet buffer size */
237 +#else
238 +               unsigned int buf_size           :  4;   /* per packet buffer size */
239 +               unsigned int                            : 28;
240 +#endif
241 +       } bits;
242 +} GMAC_CONFIG1_T;
243 +
244 +typedef union
245 +{
246 +       unsigned int bits32;
247 +       struct bit1_0020
248 +       {
249 +#if (BIG_ENDIAN==1)
250 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
251 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
252 +#else
253 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
254 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
255 +#endif
256 +       } bits;
257 +} GMAC_CONFIG2_T;
258 +
259 +typedef union
260 +{
261 +       unsigned int bits32;
262 +       struct bit1_0024
263 +       {
264 +#if (BIG_ENDIAN==1)
265 +               unsigned int                            : 16;
266 +               unsigned int buf_num            : 16;   /* return buffer number from software */
267 +#else
268 +               unsigned int buf_num            : 16;   /* return buffer number from software */
269 +               unsigned int                            : 16;
270 +#endif
271 +       } bits;
272 +} GMAC_BNCR_T;
273 +
274 +typedef union
275 +{
276 +       unsigned int bits32;
277 +       struct bit1_0028
278 +       {
279 +#if (BIG_ENDIAN==1)
280 +               unsigned int                            : 16;
281 +               unsigned int buf_remain         : 16;   /* remaining buffer number */
282 +#else
283 +               unsigned int buf_remain         : 16;   /* remaining buffer number */
284 +               unsigned int                            : 16;
285 +#endif
286 +       } bits;
287 +} GMAC_RBNR_T;
288 +
289 +typedef union
290 +{
291 +       unsigned int bits32;
292 +       struct bit1_002c
293 +       {
294 +#if (BIG_ENDIAN==1)
295 +               unsigned int                            : 25;
296 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
297 +               unsigned int phy_mode           :  1;   /* PHY interface mode in 10M-bps */
298 +               unsigned int duplex                     :  1;   /* duplex mode */
299 +               unsigned int speed                      :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
300 +               unsigned int link                       :  1;   /* link status */
301 +#else
302 +               unsigned int link                       :  1;   /* link status */
303 +               unsigned int speed                      :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
304 +               unsigned int duplex                     :  1;   /* duplex mode */
305 +               unsigned int phy_mode           :  1;   /* PHY interface mode in 10M-bps */
306 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
307 +               unsigned int                            : 25;
308 +#endif
309 +       } bits;
310 +} GMAC_STATUS_T;
311 +
312 +
313 +typedef union
314 +{
315 +       unsigned int bits32;
316 +       struct bit1_009
317 +       {
318 +#if (BIG_ENDIAN==1)
319 +               unsigned int                            : 10;
320 +               unsigned int tx_fail            :  1;   /* Tx fail interrupt */
321 +               unsigned int cnt_full           :  1;   /* MIB counters half full interrupt */
322 +               unsigned int rx_pause_on        :  1;   /* received pause on frame interrupt */
323 +               unsigned int tx_pause_on        :  1;   /* transmit pause on frame interrupt */
324 +               unsigned int rx_pause_off   :  1;       /* received pause off frame interrupt */
325 +               unsigned int tx_pause_off       :  1;   /* received pause off frame interrupt */
326 +               unsigned int rx_overrun         :  1;   /* GMAC Rx FIFO overrun interrupt */
327 +               unsigned int tx_underrun        :  1;   /* GMAC Tx FIFO underrun interrupt */
328 +               unsigned int                            :  6;
329 +               unsigned int m_tx_fail          :  1;   /* Tx fail interrupt mask */
330 +               unsigned int m_cnt_full         :  1;   /* MIB counters half full interrupt mask */
331 +               unsigned int m_rx_pause_on      :  1;   /* received pause on frame interrupt mask */
332 +               unsigned int m_tx_pause_on  :  1;       /* transmit pause on frame interrupt mask */
333 +               unsigned int m_rx_pause_off :  1;       /* received pause off frame interrupt mask */
334 +               unsigned int m_tx_pause_off     :  1;   /* received pause off frame interrupt mask */
335 +               unsigned int m_rx_overrun       :  1;   /* GMAC Rx FIFO overrun interrupt mask */
336 +               unsigned int m_tx_underrun      :  1;   /* GMAC Tx FIFO underrun interrupt mask */
337 +#else
338 +               unsigned int m_tx_underrun      :  1;   /* GMAC Tx FIFO underrun interrupt mask */
339 +               unsigned int m_rx_overrun       :  1;   /* GMAC Rx FIFO overrun interrupt mask */
340 +               unsigned int m_tx_pause_off     :  1;   /* received pause off frame interrupt mask */
341 +               unsigned int m_rx_pause_off :  1;       /* received pause off frame interrupt mask */
342 +               unsigned int m_tx_pause_on  :  1;       /* transmit pause on frame interrupt mask */
343 +               unsigned int m_rx_pause_on      :  1;   /* received pause on frame interrupt mask */
344 +               unsigned int m_cnt_full         :  1;   /* MIB counters half full interrupt mask */
345 +               unsigned int m_tx_fail          :  1;   /* Tx fail interrupt mask */
346 +               unsigned int                            :  6;
347 +               unsigned int tx_underrun        :  1;   /* GMAC Tx FIFO underrun interrupt */
348 +               unsigned int rx_overrun         :  1;   /* GMAC Rx FIFO overrun interrupt */
349 +               unsigned int tx_pause_off       :  1;   /* received pause off frame interrupt */
350 +               unsigned int rx_pause_off   :  1;       /* received pause off frame interrupt */
351 +               unsigned int tx_pause_on        :  1;   /* transmit pause on frame interrupt */
352 +               unsigned int rx_pause_on        :  1;   /* received pause on frame interrupt */
353 +               unsigned int cnt_full           :  1;   /* MIB counters half full interrupt */
354 +               unsigned int tx_fail            :  1;   /* Tx fail interrupt */
355 +               unsigned int                            : 10;
356 +#endif
357 +       } bits;
358 +} GMAC_INT_MASK_T;
359 +
360 +
361 +/*******************************************/
362 +/* the register structure of GMAC DMA      */
363 +/*******************************************/
364 +typedef union
365 +{
366 +       unsigned int bits32;
367 +       struct bit2_ff00
368 +       {
369 +#if (BIG_ENDIAN==1)
370 +               unsigned int                :  7;   /* reserved */
371 +               unsigned int s_ahb_err          :  1;   /* Slave AHB bus error */
372 +               unsigned int tx_err_code    :  4;   /* TxDMA error code */
373 +               unsigned int rx_err_code        :  4;   /* RxDMA error code */
374 +               unsigned int device_id          : 12;
375 +               unsigned int revision_id        :  4;
376 +#else
377 +               unsigned int revision_id        :  4;
378 +               unsigned int device_id          : 12;
379 +               unsigned int rx_err_code        :  4;   /* RxDMA error code */
380 +               unsigned int tx_err_code    :  4;   /* TxDMA error code */
381 +               unsigned int s_ahb_err          :  1;   /* Slave AHB bus error */
382 +               unsigned int                :  7;   /* reserved */
383 +#endif
384 +       } bits;
385 +} GMAC_DMA_DEVICE_ID_T;
386 +
387 +typedef union
388 +{
389 +       unsigned int bits32;
390 +       struct bit2_ff04
391 +       {
392 +#if (BIG_ENDIAN==1)
393 +               unsigned int ts_finish          :  1;   /* finished tx interrupt */
394 +               unsigned int ts_derr            :  1;   /* AHB Bus Error while tx */
395 +               unsigned int ts_perr            :  1;   /* Tx Descriptor protocol error */
396 +               unsigned int ts_eodi            :  1;   /* TxDMA end of descriptor interrupt */
397 +               unsigned int ts_eofi            :  1;   /* TxDMA end of frame interrupt */
398 +               unsigned int rs_finish          :  1;   /* finished rx interrupt */
399 +               unsigned int rs_derr            :  1;   /* AHB Bus Error while rx */
400 +               unsigned int rs_perr            :  1;   /* Rx Descriptor protocol error */
401 +               unsigned int rs_eodi            :  1;   /* RxDMA end of descriptor interrupt */
402 +               unsigned int rs_eofi            :  1;   /* RxDMA end of frame interrupt */
403 +               unsigned int                    :  1;   /* Tx fail interrupt */
404 +               unsigned int cnt_full           :  1;   /* MIB counters half full interrupt */
405 +               unsigned int rx_pause_on        :  1;   /* received pause on frame interrupt */
406 +               unsigned int tx_pause_on        :  1;   /* transmit pause on frame interrupt */
407 +               unsigned int rx_pause_off   :  1;       /* received pause off frame interrupt */
408 +               unsigned int tx_pause_off       :  1;   /* received pause off frame interrupt */
409 +               unsigned int rx_overrun         :  1;   /* GMAC Rx FIFO overrun interrupt */
410 +               unsigned int link_change        :  1;   /* GMAC link changed Interrupt for RGMII mode */
411 +               unsigned int                    :  1;
412 +               unsigned int                    :  1;
413 +               unsigned int                            :  3;
414 +               unsigned int loop_back          :  1;   /* loopback TxDMA to RxDMA */
415 +               unsigned int                    :  1;   /* Tx fail interrupt mask */
416 +               unsigned int m_cnt_full         :  1;   /* MIB counters half full interrupt mask */
417 +               unsigned int m_rx_pause_on      :  1;   /* received pause on frame interrupt mask */
418 +               unsigned int m_tx_pause_on  :  1;       /* transmit pause on frame interrupt mask */
419 +               unsigned int m_rx_pause_off :  1;       /* received pause off frame interrupt mask */
420 +               unsigned int m_tx_pause_off     :  1;   /* received pause off frame interrupt mask */
421 +               unsigned int m_rx_overrun       :  1;   /* GMAC Rx FIFO overrun interrupt mask */
422 +               unsigned int m_link_change      :  1;   /* GMAC link changed Interrupt mask for RGMII mode */
423 +#else
424 +               unsigned int m_link_change      :  1;   /* GMAC link changed Interrupt mask for RGMII mode */
425 +               unsigned int m_rx_overrun       :  1;   /* GMAC Rx FIFO overrun interrupt mask */
426 +               unsigned int m_tx_pause_off     :  1;   /* received pause off frame interrupt mask */
427 +               unsigned int m_rx_pause_off :  1;       /* received pause off frame interrupt mask */
428 +               unsigned int m_tx_pause_on  :  1;       /* transmit pause on frame interrupt mask */
429 +               unsigned int m_rx_pause_on      :  1;   /* received pause on frame interrupt mask */
430 +               unsigned int m_cnt_full         :  1;   /* MIB counters half full interrupt mask */
431 +               unsigned int                    :  1;   /* Tx fail interrupt mask */
432 +               unsigned int loop_back          :  1;   /* loopback TxDMA to RxDMA */
433 +               unsigned int                            :  3;
434 +               unsigned int                    :  1;
435 +               unsigned int                    :  1;
436 +               unsigned int link_change        :  1;   /* GMAC link changed Interrupt for RGMII mode */
437 +               unsigned int rx_overrun         :  1;   /* GMAC Rx FIFO overrun interrupt */
438 +               unsigned int tx_pause_off       :  1;   /* received pause off frame interrupt */
439 +               unsigned int rx_pause_off   :  1;       /* received pause off frame interrupt */
440 +               unsigned int tx_pause_on        :  1;   /* transmit pause on frame interrupt */
441 +               unsigned int rx_pause_on        :  1;   /* received pause on frame interrupt */
442 +               unsigned int cnt_full           :  1;   /* MIB counters half full interrupt */
443 +               unsigned int                    :  1;   /* Tx fail interrupt */
444 +               unsigned int rs_eofi            :  1;   /* RxDMA end of frame interrupt */
445 +               unsigned int rs_eodi            :  1;   /* RxDMA end of descriptor interrupt */
446 +               unsigned int rs_perr            :  1;   /* Rx Descriptor protocol error */
447 +               unsigned int rs_derr            :  1;   /* AHB Bus Error while rx */
448 +               unsigned int rs_finish          :  1;   /* finished rx interrupt */
449 +               unsigned int ts_eofi            :  1;   /* TxDMA end of frame interrupt */
450 +               unsigned int ts_eodi            :  1;   /* TxDMA end of descriptor interrupt */
451 +               unsigned int ts_perr            :  1;   /* Tx Descriptor protocol error */
452 +               unsigned int ts_derr            :  1;   /* AHB Bus Error while tx */
453 +               unsigned int ts_finish          :  1;   /* finished tx interrupt */
454 +#endif
455 +       } bits;
456 +} GMAC_DMA_STATUS_T;
457 +
458 +typedef union
459 +{
460 +       unsigned int bits32;
461 +       struct bit2_ff08
462 +       {
463 +#if (BIG_ENDIAN==1)
464 +               unsigned int td_start           :  1;   /* Start DMA transfer */
465 +               unsigned int td_continue        :  1;   /* Continue DMA operation */
466 +               unsigned int td_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
467 +               unsigned int                            :  1;
468 +               unsigned int td_prot            :  4;   /* TxDMA protection control */
469 +               unsigned int td_burst_size  :  2;       /* TxDMA max burst size for every AHB request */
470 +               unsigned int td_bus                 :  2;       /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */
471 +               unsigned int td_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
472 +               unsigned int td_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
473 +               unsigned int td_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
474 +               unsigned int td_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
475 +               unsigned int td_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
476 +               unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
477 +               unsigned int                            : 14;
478 +#else
479 +               unsigned int                            : 14;
480 +               unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
481 +               unsigned int td_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
482 +               unsigned int td_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
483 +               unsigned int td_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
484 +               unsigned int td_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
485 +               unsigned int td_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
486 +               unsigned int td_bus                 :  2;       /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */
487 +               unsigned int td_burst_size  :  2;       /* TxDMA max burst size for every AHB request */
488 +               unsigned int td_prot            :  4;   /* TxDMA protection control */
489 +               unsigned int                            :  1;
490 +               unsigned int td_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
491 +               unsigned int td_continue        :  1;   /* Continue DMA operation */
492 +               unsigned int td_start           :  1;   /* Start DMA transfer */
493 +#endif
494 +       } bits;
495 +} GMAC_TXDMA_CTRL_T;
496 +
497 +
498 +typedef union
499 +{
500 +       unsigned int bits32;
501 +       struct bit2_ff0c
502 +       {
503 +#if (BIG_ENDIAN==1)
504 +               unsigned int td_first_des_ptr   : 28;/* first descriptor address */
505 +               unsigned int td_busy                    :  1;/* 1-TxDMA busy; 0-TxDMA idle */
506 +               unsigned int                                    :  3;
507 +#else
508 +               unsigned int                                    :  3;
509 +               unsigned int td_busy                    :  1;/* 1-TxDMA busy; 0-TxDMA idle */
510 +               unsigned int td_first_des_ptr   : 28;/* first descriptor address */
511 +#endif
512 +       } bits;
513 +} GMAC_TXDMA_FIRST_DESC_T;
514 +
515 +typedef union
516 +{
517 +       unsigned int bits32;
518 +       struct bit2_ff10
519 +       {
520 +#if (BIG_ENDIAN==1)
521 +               unsigned int ndar                       : 28;   /* next descriptor address */
522 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
523 +               unsigned int                            :  1;
524 +               unsigned int sof_eof            :  2;
525 +#else
526 +               unsigned int sof_eof            :  2;
527 +               unsigned int                            :  1;
528 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
529 +               unsigned int ndar                       : 28;   /* next descriptor address */
530 +#endif
531 +       } bits;
532 +} GMAC_TXDMA_CURR_DESC_T;
533 +
534 +
535 +typedef union
536 +{
537 +       unsigned int bits32;
538 +       struct bit2_ff14
539 +       {
540 +#if (BIG_ENDIAN==1)
541 +               unsigned int rd_start           :  1;   /* Start DMA transfer */
542 +               unsigned int rd_continue        :  1;   /* Continue DMA operation */
543 +               unsigned int rd_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
544 +               unsigned int                            :  1;
545 +               unsigned int rd_prot            :  4;   /* DMA protection control */
546 +               unsigned int rd_burst_size  :  2;       /* DMA max burst size for every AHB request */
547 +               unsigned int rd_bus                 :  2;       /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */
548 +               unsigned int rd_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
549 +               unsigned int rd_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
550 +               unsigned int rd_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
551 +               unsigned int rd_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
552 +               unsigned int rd_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
553 +               unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
554 +               unsigned int                            : 14;
555 +#else
556 +               unsigned int                            : 14;
557 +               unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
558 +               unsigned int rd_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
559 +               unsigned int rd_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
560 +               unsigned int rd_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
561 +               unsigned int rd_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
562 +               unsigned int rd_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
563 +               unsigned int rd_bus                 :  2;       /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */
564 +               unsigned int rd_burst_size  :  2;       /* DMA max burst size for every AHB request */
565 +               unsigned int rd_prot            :  4;   /* DMA protection control */
566 +               unsigned int                            :  1;
567 +               unsigned int rd_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
568 +               unsigned int rd_continue        :  1;   /* Continue DMA operation */
569 +               unsigned int rd_start           :  1;   /* Start DMA transfer */
570 +#endif
571 +       } bits;
572 +} GMAC_RXDMA_CTRL_T;
573 +
574 +
575 +typedef union
576 +{
577 +       unsigned int bits32;
578 +       struct bit2_ff18
579 +       {
580 +#if (BIG_ENDIAN==1)
581 +               unsigned int rd_first_des_ptr   : 28;/* first descriptor address */
582 +               unsigned int rd_busy                    :  1;/* 1-RxDMA busy; 0-RxDMA idle */
583 +               unsigned int                                    :  3;
584 +#else
585 +               unsigned int                                    :  3;
586 +               unsigned int rd_busy                    :  1;/* 1-RxDMA busy; 0-RxDMA idle */
587 +               unsigned int rd_first_des_ptr   : 28;/* first descriptor address */
588 +#endif
589 +       } bits;
590 +} GMAC_RXDMA_FIRST_DESC_T;
591 +
592 +typedef union
593 +{
594 +       unsigned int bits32;
595 +       struct bit2_ff1c
596 +       {
597 +#if (BIG_ENDIAN==1)
598 +               unsigned int ndar                       : 28;   /* next descriptor address */
599 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
600 +               unsigned int                            :  1;
601 +               unsigned int sof_eof            :  2;
602 +#else
603 +               unsigned int sof_eof            :  2;
604 +               unsigned int                            :  1;
605 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
606 +               unsigned int ndar                       : 28;   /* next descriptor address */
607 +#endif
608 +       } bits;
609 +} GMAC_RXDMA_CURR_DESC_T;
610 +
611 +
612 +/********************************************/
613 +/*          Descriptor Format               */
614 +/********************************************/
615 +
616 +typedef struct descriptor_t
617 +{
618 +       union frame_control_t
619 +       {
620 +               unsigned int bits32;
621 +               struct bits_0000
622 +               {
623 +#if (BIG_ENDIAN==1)
624 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
625 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
626 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
627 +                       unsigned int csum_state : 3;    /* checksum error status */
628 +                       unsigned int vlan_tag   : 1;    /* 802.1q vlan tag packet */
629 +                       unsigned int frame_state: 3;    /* reference Rx Status1 */
630 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
631 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
632 +#else
633 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
634 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
635 +                       unsigned int frame_state: 3;    /* reference Rx Status1 */
636 +                       unsigned int vlan_tag   : 1;    /* 802.1q vlan tag packet */
637 +                       unsigned int csum_state : 3;    /* checksum error status */
638 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
639 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
640 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
641 +#endif
642 +               } bits_rx;
643 +
644 +               struct bits_0001
645 +               {
646 +#if (BIG_ENDIAN==1)
647 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
648 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
649 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
650 +                       unsigned int            : 6;
651 +                       unsigned int success_tx : 1;    /* successful transmitted */
652 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
653 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
654 +#else
655 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
656 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
657 +                       unsigned int success_tx : 1;    /* successful transmitted */
658 +                       unsigned int            : 6;
659 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
660 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
661 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
662 +#endif
663 +        } bits_tx_in;
664 +
665 +               struct bits_0002
666 +               {
667 +#if (BIG_ENDIAN==1)
668 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
669 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
670 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
671 +                       unsigned int            : 2;
672 +                       unsigned int udp_csum_en: 1;    /* TSS UDP checksum enable */
673 +                       unsigned int tcp_csum_en: 1;    /* TSS TCP checksum enable */
674 +                       unsigned int ipv6_tx_en : 1;    /* TSS IPv6 TX enable */
675 +                       unsigned int ip_csum_en : 1;    /* TSS IPv4 IP Header checksum enable */
676 +                       unsigned int vlan_enable: 1;    /* VLAN TIC insertion enable */
677 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
678 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
679 +#else
680 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
681 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
682 +                       unsigned int vlan_enable: 1;    /* VLAN TIC insertion enable */
683 +                       unsigned int ip_csum_en : 1;    /* TSS IPv4 IP Header checksum enable */
684 +                       unsigned int ipv6_tx_en : 1;    /* TSS IPv6 TX enable */
685 +                       unsigned int tcp_csum_en: 1;    /* TSS TCP checksum enable */
686 +                       unsigned int udp_csum_en: 1;    /* TSS UDP checksum enable */
687 +                       unsigned int            : 2;
688 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
689 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
690 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
691 +#endif
692 +        } bits_tx_out;
693 +
694 +       } frame_ctrl;
695 +
696 +       union flag_status_t
697 +       {
698 +               unsigned int bits32;
699 +               struct bits_0004
700 +               {
701 +#if (BIG_ENDIAN==1)
702 +            unsigned int priority   : 3;    /* user priority extracted from receiving frame*/
703 +            unsigned int cfi        : 1;       /* cfi extracted from receiving frame*/
704 +                       unsigned int vlan_id    :12;    /* VLAN ID extracted from receiving frame */
705 +                       unsigned int frame_count:16;    /* received frame byte count,include CRC,not include VLAN TIC */
706 +#else
707 +                       unsigned int frame_count:16;    /* received frame byte count,include CRC,not include VLAN TIC */
708 +                       unsigned int vlan_id    :12;    /* VLAN ID extracted from receiving frame */
709 +            unsigned int cfi        : 1;       /* cfi extracted from receiving frame*/
710 +            unsigned int priority   : 3;    /* user priority extracted from receiving frame*/
711 +#endif
712 +               } bits_rx_status;
713 +
714 +               struct bits_0005
715 +               {
716 +#if (BIG_ENDIAN==1)
717 +            unsigned int priority   : 3;    /* user priority to transmit*/
718 +            unsigned int cfi        : 1;       /* cfi to transmit*/
719 +                       unsigned int vlan_id    :12;    /* VLAN ID to transmit */
720 +                       unsigned int frame_count:16;    /* total tx frame byte count */
721 +#else
722 +                       unsigned int frame_count:16;    /* total tx frame byte count */
723 +                       unsigned int vlan_id    :12;    /* VLAN ID to transmit */
724 +            unsigned int cfi        : 1;       /* cfi to transmit*/
725 +            unsigned int priority   : 3;    /* user priority to transmit*/
726 +#endif
727 +               } bits_tx_flag;
728 +       } flag_status;
729 +
730 +       unsigned int buf_adr;   /* data buffer address */
731 +
732 +       union next_desc_t
733 +       {
734 +               unsigned int next_descriptor;
735 +               struct bits_000c
736 +               {
737 +#if (BIG_ENDIAN==1)
738 +                       unsigned int ndar               :28;    /* next descriptor address */
739 +                       unsigned int eofie              : 1;    /* end of frame interrupt enable */
740 +                       unsigned int                    : 1;
741 +                       unsigned int sof_eof    : 2;    /* 00-the linking descriptor   01-the last descriptor of a frame*/
742 +                                                       /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
743 +#else
744 +                       unsigned int sof_eof    : 2;    /* 00-the linking descriptor   01-the last descriptor of a frame*/
745 +                                                       /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
746 +                       unsigned int                    : 1;
747 +                       unsigned int eofie              : 1;    /* end of frame interrupt enable */
748 +                       unsigned int ndar               :28;    /* next descriptor address */
749 +#endif
750 +               } bits;
751 +       } next_desc;
752 +} GMAC_DESCRIPTOR_T;
753 +
754 +typedef struct gmac_conf {
755 +       struct net_device *dev;
756 +       int portmap;
757 +       int vid;
758 +       int flag;     /* 1: active  0: non-active */
759 +} sys_gmac_conf;
760 +
761 +struct gmac_private {
762 +       unsigned char       *tx_bufs;   /* Tx bounce buffer region. */
763 +       unsigned char       *rx_bufs;
764 +       GMAC_DESCRIPTOR_T       *tx_desc;       /* point to virtual TX descriptor address*/
765 +       GMAC_DESCRIPTOR_T       *rx_desc;       /* point to virtual RX descriptor address*/
766 +       GMAC_DESCRIPTOR_T       *tx_cur_desc;   /* point to current TX descriptor */
767 +       GMAC_DESCRIPTOR_T       *rx_cur_desc;   /* point to current RX descriptor */
768 +       GMAC_DESCRIPTOR_T   *tx_finished_desc;
769 +       GMAC_DESCRIPTOR_T   *rx_finished_desc;
770 +       unsigned long       cur_tx;
771 +       unsigned int        cur_rx;     /* Index into the Rx buffer of next Rx pkt. */
772 +       unsigned int        tx_flag;
773 +       unsigned long       dirty_tx;
774 +       unsigned char       *tx_buf[TX_DESC_NUM];       /* Tx bounce buffers */
775 +       dma_addr_t          tx_desc_dma; /* physical TX descriptor address */
776 +       dma_addr_t          rx_desc_dma;        /* physical RX descriptor address */
777 +       dma_addr_t          tx_bufs_dma; /* physical TX descriptor address */
778 +       dma_addr_t          rx_bufs_dma; /* physical RX descriptor address */
779 +    struct net_device_stats  stats;
780 +       pid_t               thr_pid;
781 +       wait_queue_head_t   thr_wait;
782 +       struct completion   thr_exited;
783 +    spinlock_t          lock;
784 +    int                 time_to_die;
785 +       unsigned int            tx_desc_hdr[GMAC_PHY_IF];       /* the descriptor which sw can fill */
786 +       unsigned int            tx_desc_tail[GMAC_PHY_IF];      /* the descriptor which is not cleaned yet */
787 +};
788 +
789 +
790 +struct reg_ioctl_data {
791 +    unsigned int    reg_addr;   /* the register address */
792 +    unsigned int    val_in;     /* data write to the register */
793 +    unsigned int    val_out;    /* data read from the register */
794 +};
795 +
796 +#ifdef CONFIG_SL2312_MPAGE
797 +typedef struct tx_data_t {
798 +       int     freeable; // 1 when it's skb. it can be freed in tx interrupt handler
799 +       struct sk_buff* skb; // skb
800 +       int     desc_in_use; // 1 when the desc is in use. 0 when desc is available.
801 +       long end_seq; // to find out packets are in seq.
802 +       // so this value is the seq of next packet.
803 +} tx_data;
804 +#endif
805 +
806 +/*************************************************************
807 + *         Global Variable
808 + *************************************************************/
809 +struct semaphore        sem_gmac;   /* semaphore for share pins issue */
810 +
811 +/*************************************************************
812 + *        Static Global Variable
813 + *************************************************************/
814 +// static unsigned int     MAC_BASE_ADDR = GMAC0_BASE;
815 +static unsigned int     gmac_base_addr[GMAC_PHY_IF] = {GMAC0_BASE,GMAC1_BASE};
816 +static unsigned int     gmac_irq[GMAC_PHY_IF] = {IRQ_GMAC0,IRQ_GMAC1};
817 +static struct net_device *gmac_dev[GMAC_PHY_IF];
818 +
819 +static unsigned int     FLAG_SWITCH=0; /* if 1-->switch chip presented. if 0-->switch chip unpresented */
820 +static unsigned int     flow_control_enable[GMAC_PHY_IF] = {1,1};
821 +static unsigned int     pre_phy_status[GMAC_PHY_IF] = {LINK_DOWN,LINK_DOWN};
822 +static unsigned int     tx_desc_virtual_base[GMAC_PHY_IF];
823 +static unsigned int     rx_desc_virtual_base[GMAC_PHY_IF];
824 +static unsigned int     full_duplex = 1;
825 +static unsigned int     speed = 1;
826 +#ifdef CONFIG_SL2312_MPAGE
827 +static tx_data             tx_skb[GMAC_PHY_IF][TX_DESC_NUM];
828 +#else
829 +static struct sk_buff   *tx_skb[GMAC_PHY_IF][TX_DESC_NUM];
830 +#endif
831 +static struct sk_buff   *rx_skb[GMAC_PHY_IF][RX_DESC_NUM];
832 +static unsigned int     tx_desc_start_adr[GMAC_PHY_IF];
833 +static unsigned int     rx_desc_start_adr[GMAC_PHY_IF];
834 +static unsigned char    eth0_mac[6]= {0x00,0x50,0xc2,0x2b,0xd3,0x25};
835 +static unsigned char    eth1_mac[6]= {0x00,0x50,0xc2,0x2b,0xdf,0xfe};
836 +static unsigned int     next_tick = 3 * HZ;
837 +
838 +static unsigned int     phy_addr[GMAC_PHY_IF] = {0x01,0x02};  /* define PHY address */
839 +
840 +DECLARE_WAIT_QUEUE_HEAD(gmac_queue);
841 +//static       wait_queue_t    wait;
842 +
843 +struct gmac_conf VLAN_conf[] = {
844 +#ifdef CONFIG_ADM_6999
845 +       { (struct net_device *)0,0x7F,1 },
846 +       { (struct net_device *)0,0x80,2 }
847 +#endif
848 +#ifdef CONFIG_ADM_6996
849 +       { (struct net_device *)0,0x0F,1 },
850 +       { (struct net_device *)0,0x10,2 }
851 +#endif
852 +};
853 +
854 +#define NUM_VLAN_IF    (sizeof(VLAN_conf)/sizeof(struct gmac_conf))
855 +
856 +
857 +/************************************************/
858 +/*            GMAC function declare             */
859 +/************************************************/
860 +
861 +unsigned int mii_read(unsigned char phyad,unsigned char regad);
862 +void mii_write(unsigned char phyad,unsigned char regad,unsigned int value);
863 +static void gmac_set_phy_status(struct net_device *dev);
864 +static void gmac_get_phy_status(struct net_device *dev);
865 +static int gmac_phy_thread (void *data);
866 +static int gmac_set_mac_address(struct net_device *dev, void *addr);
867 +static void gmac_tx_timeout(struct net_device *dev);
868 +static void gmac_tx_packet_complete(struct net_device *dev);
869 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev);
870 +static void gmac_set_rx_mode(struct net_device *dev);
871 +static void gmac_rx_packet(struct net_device *dev);
872 +static int gmac_open (struct net_device *dev);
873 +static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
874 +
875 +static unsigned int gmac_get_dev_index(struct net_device *dev);
876 +static unsigned int gmac_select_interface(struct net_device *dev);
877 +
878 +#ifdef CONFIG_SL2312_MPAGE
879 +int printk_all(int dev_index, struct gmac_private* tp);
880 +#endif
881 +
882 +/****************************************/
883 +/*     SPI Function Declare            */
884 +/****************************************/
885 +void SPI_write(unsigned char addr,unsigned int value);
886 +unsigned int SPI_read(unsigned char table,unsigned char addr);
887 +void SPI_write_bit(char bit_EEDO);
888 +unsigned int SPI_read_bit(void);
889 +void SPI_default(void);
890 +void SPI_reset(unsigned char rstype,unsigned char port_cnt);
891 +void SPI_pre_st(void);
892 +void SPI_CS_enable(unsigned char enable);
893 +void SPI_Set_VLAN(unsigned char LAN,unsigned int port_mask);
894 +void SPI_Set_tag(unsigned int port,unsigned tag);
895 +void SPI_Set_PVID(unsigned int PVID,unsigned int port_mask);
896 +unsigned int SPI_Get_PVID(unsigned int port);
897 +void SPI_mac_lock(unsigned int port, unsigned char lock);
898 +void SPI_get_port_state(unsigned int port);
899 +void SPI_port_enable(unsigned int port,unsigned char enable);
900 +unsigned int SPI_get_identifier(void);
901 +void SPI_get_status(unsigned int port);
902 +
903 +/****************************************/
904 +/*     VLAN Function Declare                   */
905 +/****************************************/
906 +int getVLANfromdev (struct net_device *dev );
907 +struct net_device * getdevfromVLAN( int VID);
908 +
909 +
910 +
911 +/************************************************/
912 +/*                 function body                */
913 +/************************************************/
914 +#if 0
915 +void hw_memcpy(void *to,const void *from,unsigned long n)
916 +{
917 +    writel(from,SL2312_DRAM_CTRL_BASE+0x20);  /* set source address */
918 +    writel(to,SL2312_DRAM_CTRL_BASE+0x24);    /* set destination address */
919 +    writel(n,SL2312_DRAM_CTRL_BASE+0x28);     /* set byte count */
920 +    writel(0x00000001,SL2312_DRAM_CTRL_BASE+0x2c);
921 +    while (readl(SL2312_DRAM_CTRL_BASE+0x2c));
922 +}
923 +#endif
924 +
925 +static unsigned int gmac_read_reg(unsigned int addr)
926 +{
927 +    unsigned int    reg_val;
928 +//    unsigned int    flags;
929 +//    spinlock_t     lock;
930 +
931 +//    spin_lock_irqsave(&lock, flags);
932 +    reg_val = readl(addr);     // Gary Chen
933 +//     spin_unlock_irqrestore(&lock, flags);
934 +       return (reg_val);
935 +}
936 +
937 +static void gmac_write_reg(unsigned int addr,unsigned int data,unsigned int bit_mask)
938 +{
939 +       unsigned int    reg_val;
940 +    //unsigned int    *addr;
941 +//    unsigned int    flags;
942 +//    spinlock_t     lock;
943 +
944 +//    spin_lock_irqsave(&lock, flags);
945 +       reg_val = ( gmac_read_reg(addr) & (~bit_mask) ) | (data & bit_mask);
946 +    writel(reg_val,addr);
947 +//     spin_unlock_irqrestore(&lock, flags);
948 +       return;
949 +}
950 +
951 +
952 +static void gmac_sw_reset(struct net_device *dev)
953 +{
954 +    unsigned int    index;
955 +    unsigned int    reg_val;
956 +
957 +    index = gmac_get_dev_index(dev);
958 +    if (index==0)
959 +        reg_val = readl(GMAC_GLOBAL_BASE_ADDR+0x0c) | 0x00000020;   /* GMAC0 S/W reset */
960 +    else
961 +        reg_val = readl(GMAC_GLOBAL_BASE_ADDR+0x0c) | 0x00000040;   /* GMAC1 S/W reset */
962 +
963 +    writel(reg_val,GMAC_GLOBAL_BASE_ADDR+0x0c);
964 +    return;
965 +}
966 +
967 +static void gmac_get_mac_address(void)
968 +{
969 +#ifdef CONFIG_MTD
970 +       extern int get_vlaninfo(vlaninfo* vlan);
971 +    static vlaninfo    vlan[2];
972 +
973 +    if (get_vlaninfo(&vlan[0]))
974 +    {
975 +        memcpy(eth0_mac,vlan[0].mac,6);
976 +        VLAN_conf[0].vid = vlan[0].vlanid;
977 +        VLAN_conf[0].portmap = vlan[0].vlanmap;
978 +        memcpy(eth1_mac,vlan[1].mac,6);
979 +        VLAN_conf[1].vid = vlan[1].vlanid;
980 +        VLAN_conf[1].portmap = vlan[1].vlanmap;
981 +    }
982 +#else
983 +    unsigned int reg_val;
984 +
985 +    reg_val = readl(IO_ADDRESS(SL2312_SECURITY_BASE)+0xac);
986 +    eth0_mac[4] = (reg_val & 0xff00) >> 8;
987 +    eth0_mac[5] = reg_val & 0x00ff;
988 +    reg_val = readl(IO_ADDRESS(SL2312_SECURITY_BASE)+0xac);
989 +    eth1_mac[4] = (reg_val & 0xff00) >> 8;
990 +    eth1_mac[5] = reg_val & 0x00ff;
991 +#endif
992 +    return;
993 +}
994 +
995 +static unsigned int gmac_get_dev_index(struct net_device *dev)
996 +{
997 +    unsigned int    i;
998 +
999 +    /* get device index number */
1000 +    for (i=0;i<GMAC_PHY_IF;i++)
1001 +    {
1002 +        if (gmac_dev[i]==dev)
1003 +        {
1004 +            return(i);
1005 +        }
1006 +    }
1007 +    return (0xff);
1008 +}
1009 +
1010 +static unsigned int gmac_select_interface(struct net_device *dev)
1011 +{
1012 +    unsigned int    index;
1013 +
1014 +    index = gmac_get_dev_index(dev);
1015 +    // MAC_BASE_ADDR = gmac_base_addr[index];  // Gary Chen
1016 +    return (index);
1017 +}
1018 +
1019 +
1020 +static void gmac_dump_register(struct net_device *dev)
1021 +{
1022 +#if 0
1023 +    unsigned int   i,val,index;
1024 +
1025 +    index = gmac_select_interface(dev);
1026 +
1027 +    printk("========== GMAC%d ==========\n",index);
1028 +    for (i=0;i<=0x7c;i=i+4)
1029 +    {
1030 +        val = gmac_read_reg(gmac_base_addr[index] + i);
1031 +        printk("offset = %08x   value = %08x\n",i,val);
1032 +    }
1033 +    for (i=0xff00;i<=0xff7c;i=i+4)
1034 +    {
1035 +        val = gmac_read_reg(gmac_base_addr[index] + i);
1036 +        printk("offset = %08x   value = %08x\n",i,val);
1037 +    }
1038 +#endif
1039 +}
1040 +
1041 +static int gmac_init_chip(struct net_device *dev)
1042 +{
1043 +       GMAC_RBNR_T             rbnr_val,rbnr_mask;
1044 +       GMAC_CONFIG2_T  config2_val;
1045 +       GMAC_CONFIG0_T  config0,config0_mask;
1046 +       GMAC_CONFIG1_T  config1;
1047 +       struct sockaddr sock;
1048 +       unsigned int    status;
1049 +       unsigned int    phy_mode;
1050 +       unsigned int    index;
1051 +
1052 +    index = gmac_get_dev_index(dev);
1053 +
1054 +    /* set GMAC RMII mode */
1055 +    if (index==0)
1056 +        phy_mode = 0;   /* 0->MII 1->GMII 2->RGMII(10/100) 3->RGMII(1000) */
1057 +    else
1058 +        phy_mode = 2;   /* 0->MII 1->GMII 2->RGMII(10/100) 3->RGMII(1000) */
1059 +
1060 +    /* set PHY operation mode */
1061 +    status = (phy_mode<<5) | 0x11 | (full_duplex<<3) | (speed<<1);
1062 +    gmac_write_reg(gmac_base_addr[index] + GMAC_STATUS,status ,0x0000007f);
1063 +
1064 +       /* set station MAC address1 and address2 */
1065 +       if (index==0)
1066 +           memcpy(&sock.sa_data[0],&eth0_mac[0],6);
1067 +    else
1068 +           memcpy(&sock.sa_data[0],&eth1_mac[0],6);
1069 +    gmac_set_mac_address(dev,(void *)&sock);
1070 +
1071 +    /* set RX_FLTR register to receive all multicast packet */
1072 +    gmac_write_reg(gmac_base_addr[index] + GMAC_RX_FLTR,0x0000001F,0x0000001f);
1073 +    //gmac_write_reg(gmac_base_addr[index] + GMAC_RX_FLTR,0x00000007,0x0000001f);
1074 +
1075 +       /* set per packet buffer size */
1076 +       config1.bits32 = 0;
1077 +    config1.bits.buf_size = 11; /* buffer size = 2048-byte */
1078 +    gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG1,config1.bits32,0x0000000f);
1079 +
1080 +       /* set flow control threshold */
1081 +       config2_val.bits32 = 0;
1082 +       config2_val.bits.set_threshold = RX_DESC_NUM/4;
1083 +       config2_val.bits.rel_threshold = RX_DESC_NUM*3/4;
1084 +       gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG2,config2_val.bits32,0xffffffff);
1085 +
1086 +       /* init remaining buffer number register */
1087 +       rbnr_val.bits32 = 0;
1088 +       rbnr_val.bits.buf_remain = RX_DESC_NUM;
1089 +       rbnr_mask.bits32 = 0;
1090 +       rbnr_mask.bits.buf_remain = 0xffff;
1091 +       gmac_write_reg(gmac_base_addr[index] + GMAC_RBNR,rbnr_val.bits32,rbnr_mask.bits32);
1092 +
1093 +    /* disable TX/RX and disable internal loop back */
1094 +    config0.bits32 = 0;
1095 +    config0_mask.bits32 = 0;
1096 +    config0.bits.max_len = 2;
1097 +    if (flow_control_enable[index]==1)
1098 +    {
1099 +        config0.bits.tx_fc_en = 1; /* enable tx flow control */
1100 +        config0.bits.rx_fc_en = 1; /* enable rx flow control */
1101 +        printk("Enable MAC Flow Control...\n");
1102 +    }
1103 +    else
1104 +    {
1105 +        config0.bits.tx_fc_en = 0; /* disable tx flow control */
1106 +        config0.bits.rx_fc_en = 0; /* disable rx flow control */
1107 +        printk("Disable MAC Flow Control...\n");
1108 +    }
1109 +    config0.bits.dis_rx = 1;  /* disable rx */
1110 +    config0.bits.dis_tx = 1;  /* disable tx */
1111 +    config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
1112 +       config0.bits.inv_rx_clk = 0;
1113 +       config0.bits.rising_latch = 1;
1114 +       config0.bits.ipv4_tss_rx_en = 1;  /* enable H/W to check ip checksum */
1115 +       config0.bits.ipv6_tss_rx_en = 1;  /* enable H/W to check ip checksum */
1116 +
1117 +    config0_mask.bits.max_len = 7;
1118 +    config0_mask.bits.tx_fc_en = 1;
1119 +    config0_mask.bits.rx_fc_en = 1;
1120 +    config0_mask.bits.dis_rx = 1;
1121 +    config0_mask.bits.dis_tx = 1;
1122 +    config0_mask.bits.loop_back = 1;
1123 +    config0_mask.bits.inv_rx_clk = 1;
1124 +       config0_mask.bits.rising_latch = 1;
1125 +       config0_mask.bits.ipv4_tss_rx_en = 1;
1126 +       config0_mask.bits.ipv6_tss_rx_en = 1;
1127 +    gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
1128 +
1129 +       return (0);
1130 +}
1131 +
1132 +static void gmac_enable_tx_rx(struct net_device *dev)
1133 +{
1134 +       GMAC_CONFIG0_T  config0,config0_mask;
1135 +       int                             dev_index;
1136 +
1137 +    dev_index = gmac_select_interface(dev);
1138 +
1139 +    /* enable TX/RX */
1140 +    config0.bits32 = 0;
1141 +    config0_mask.bits32 = 0;
1142 +    config0.bits.dis_rx = 0;  /* enable rx */
1143 +    config0.bits.dis_tx = 0;  /* enable tx */
1144 +    config0_mask.bits.dis_rx = 1;
1145 +    config0_mask.bits.dis_tx = 1;
1146 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
1147 +}
1148 +
1149 +static void gmac_disable_tx_rx(struct net_device *dev)
1150 +{
1151 +       GMAC_CONFIG0_T  config0,config0_mask;
1152 +       int                             dev_index;
1153 +
1154 +    dev_index = gmac_select_interface(dev);
1155 +
1156 +    /* enable TX/RX */
1157 +    config0.bits32 = 0;
1158 +    config0_mask.bits32 = 0;
1159 +    config0.bits.dis_rx = 1;  /* disable rx */
1160 +    config0.bits.dis_tx = 1;  /* disable tx */
1161 +    config0_mask.bits.dis_rx = 1;
1162 +    config0_mask.bits.dis_tx = 1;
1163 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
1164 +}
1165 +
1166 +#ifdef CONFIG_SL_NAPI
1167 +static int gmac_rx_poll_ga(struct net_device *dev, int *budget)
1168 +{
1169 +       struct gmac_private *tp = dev->priv;
1170 +       struct sk_buff          *skb;
1171 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1172 +       GMAC_RXDMA_FIRST_DESC_T rxdma_busy;
1173 +    GMAC_DESCRIPTOR_T   *rx_desc;
1174 +       unsigned int            pkt_size;
1175 +       unsigned int        desc_count;
1176 +    unsigned int        vid;
1177 +//    unsigned int        priority;
1178 +       unsigned int        own;
1179 +       unsigned int        good_frame = 0;
1180 +       unsigned int        index;
1181 +       unsigned int        dev_index;
1182 +       int                 work = 0;
1183 +       int                 work_done = 0;
1184 +       int                 quota = min(dev->quota, *budget);
1185 +
1186 +    dev_index = gmac_select_interface(dev);
1187 +
1188 +       for (;;)
1189 +       {
1190 +        own = tp->rx_cur_desc->frame_ctrl.bits32 >> 31;
1191 +        if (own == CPU) /* check owner bit */
1192 +        {
1193 +               rx_desc = tp->rx_cur_desc;
1194 +#if (GMAC_DEBUG==1)
1195 +               /* check error interrupt */
1196 +               if ( (rx_desc->frame_ctrl.bits_rx.derr==1)||(rx_desc->frame_ctrl.bits_rx.perr==1) )
1197 +               {
1198 +               printk("%s::Rx Descriptor Processing Error !!!\n",__func__);
1199 +           }
1200 +#endif
1201 +           /* get frame information from the first descriptor of the frame */
1202 +               pkt_size = rx_desc->flag_status.bits_rx_status.frame_count - 4;  /*total byte count in a frame*/
1203 +#if (GMAC_DEBUG==1)
1204 +            priority = rx_desc->flag_status.bits_rx_status.priority;    /* 802.1p priority */
1205 +#endif
1206 +            vid = rx_desc->flag_status.bits_rx_status.vlan_id;          /* 802.1q vlan id */
1207 +            if (vid == 0)
1208 +            {
1209 +                vid = 1;    /* default vlan */
1210 +            }
1211 +               desc_count = rx_desc->frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */
1212 +
1213 +               if (rx_desc->frame_ctrl.bits_rx.frame_state == 0x000) /* good frame */
1214 +               {
1215 +                       tp->stats.rx_bytes += pkt_size;
1216 +                       tp->stats.rx_packets++;
1217 +                       good_frame = 1;
1218 +               }
1219 +               else
1220 +               {
1221 +                       tp->stats.rx_errors++;
1222 +                       good_frame = 0;
1223 +                       printk("RX status: 0x%x\n",rx_desc->frame_ctrl.bits_rx.frame_state);
1224 +               }
1225 +       }
1226 +       else
1227 +       {
1228 +           work_done = 1;
1229 +           break;  /* Rx process is completed */
1230 +       }
1231 +
1232 +        if (good_frame == 1)
1233 +        {
1234 +            /* get rx skb buffer index */
1235 +            index = ((unsigned int)tp->rx_cur_desc - rx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1236 +            if (rx_skb[dev_index][index])
1237 +            {
1238 +                skb_reserve (rx_skb[dev_index][index], 2);     /* 16 byte align the IP fields. */
1239 +                rx_skb[dev_index][index]->dev = dev;
1240 +                rx_skb[dev_index][index]->ip_summed = CHECKSUM_UNNECESSARY;
1241 +                           skb_put(rx_skb[dev_index][index],pkt_size);
1242 +                           rx_skb[dev_index][index]->protocol = eth_type_trans(rx_skb[dev_index][index],dev); /* set skb protocol */
1243 +                           netif_rx(rx_skb[dev_index][index]);  /* socket rx */
1244 +                           dev->last_rx = jiffies;
1245 +
1246 +                           /* allocate rx skb buffer */
1247 +                if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
1248 +                {
1249 +                    printk("%s::skb buffer allocation fail !\n",__func__);
1250 +                }
1251 +                rx_skb[dev_index][index] = skb;
1252 +                tp->rx_cur_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
1253 +            }
1254 +            else
1255 +            {
1256 +                printk("%s::rx skb index error !\n",__func__);
1257 +            }
1258 +        }
1259 +
1260 +           tp->rx_cur_desc->frame_ctrl.bits_rx.own = DMA; /* release rx descriptor to DMA */
1261 +        /* point to next rx descriptor */
1262 +        tp->rx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->rx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+rx_desc_virtual_base[dev_index]);
1263 +
1264 +        /* release buffer to Remaining Buffer Number Register */
1265 +        if (flow_control_enable[dev_index] ==1)
1266 +        {
1267 +//            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_BNCR,desc_count,0x0000ffff);
1268 +            writel(desc_count,(unsigned int *)(gmac_base_addr[dev_index] + GMAC_BNCR));
1269 +        }
1270 +
1271 +               if (work++ >= quota )
1272 +               {
1273 +                       break;
1274 +               }
1275 +    }
1276 +
1277 +    /* if RX DMA process is stoped , restart it */
1278 +       rxdma_busy.bits.rd_first_des_ptr = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC);
1279 +       if (rxdma_busy.bits.rd_busy == 0)
1280 +       {
1281 +           rxdma_ctrl.bits32 = 0;
1282 +       rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1283 +           rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1284 +           rxdma_ctrl_mask.bits32 = 0;
1285 +       rxdma_ctrl_mask.bits.rd_start = 1;
1286 +           rxdma_ctrl_mask.bits.rd_continue = 1;
1287 +           gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1288 +    }
1289 +
1290 +       dev->quota -= work;
1291 +       *budget -= work;
1292 +       if (work_done==1)
1293 +       {
1294 +           /* Receive descriptor is empty now */
1295 +        netif_rx_complete(dev);
1296 +        /* enable receive interrupt */
1297 +        gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,0x0007c000,0x0007c000);   /* enable rx interrupt */
1298 +        return 0;
1299 +    }
1300 +    else
1301 +    {
1302 +        return -1;
1303 +    }
1304 +}
1305 +
1306 +static int gmac_rx_poll_gb(struct net_device *dev, int *budget)
1307 +{
1308 +       struct gmac_private *tp = dev->priv;
1309 +       struct sk_buff          *skb;
1310 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1311 +       GMAC_RXDMA_FIRST_DESC_T rxdma_busy;
1312 +    GMAC_DESCRIPTOR_T   *rx_desc;
1313 +       unsigned int            pkt_size;
1314 +       unsigned int        desc_count;
1315 +    unsigned int        vid;
1316 +//    unsigned int        priority;
1317 +       unsigned int        own;
1318 +       unsigned int        good_frame = 0;
1319 +       unsigned int        index;
1320 +       unsigned int        dev_index;
1321 +       int                 work = 0;
1322 +       int                 work_done = 0;
1323 +       int                 quota = min(dev->quota, *budget);
1324 +
1325 +    dev_index = gmac_select_interface(dev);
1326 +
1327 +       for (;;)
1328 +       {
1329 +        own = tp->rx_cur_desc->frame_ctrl.bits32 >> 31;
1330 +        if (own == CPU) /* check owner bit */
1331 +        {
1332 +               rx_desc = tp->rx_cur_desc;
1333 +#if (GMAC_DEBUG==1)
1334 +               /* check error interrupt */
1335 +               if ( (rx_desc->frame_ctrl.bits_rx.derr==1)||(rx_desc->frame_ctrl.bits_rx.perr==1) )
1336 +               {
1337 +               printk("%s::Rx Descriptor Processing Error !!!\n",__func__);
1338 +           }
1339 +#endif
1340 +           /* get frame information from the first descriptor of the frame */
1341 +               pkt_size = rx_desc->flag_status.bits_rx_status.frame_count - 4;  /*total byte count in a frame*/
1342 +#if (GMAC_DEBUG==1)
1343 +            priority = rx_desc->flag_status.bits_rx_status.priority;    /* 802.1p priority */
1344 +#endif
1345 +            vid = rx_desc->flag_status.bits_rx_status.vlan_id;          /* 802.1q vlan id */
1346 +            if (vid == 0)
1347 +            {
1348 +                vid = 1;    /* default vlan */
1349 +            }
1350 +               desc_count = rx_desc->frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */
1351 +
1352 +               if (rx_desc->frame_ctrl.bits_rx.frame_state == 0x000) /* good frame */
1353 +               {
1354 +                       tp->stats.rx_bytes += pkt_size;
1355 +                       tp->stats.rx_packets++;
1356 +                       good_frame = 1;
1357 +               }
1358 +               else
1359 +               {
1360 +                       tp->stats.rx_errors++;
1361 +                       good_frame = 0;
1362 +                       printk("RX status: 0x%x\n",rx_desc->frame_ctrl.bits_rx.frame_state);
1363 +               }
1364 +       }
1365 +       else
1366 +       {
1367 +           work_done = 1;
1368 +           break;  /* Rx process is completed */
1369 +       }
1370 +
1371 +        if (good_frame == 1)
1372 +        {
1373 +            /* get rx skb buffer index */
1374 +            index = ((unsigned int)tp->rx_cur_desc - rx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1375 +            if (rx_skb[dev_index][index])
1376 +            {
1377 +                skb_reserve (rx_skb[dev_index][index], 2);     /* 16 byte align the IP fields. */
1378 +                rx_skb[dev_index][index]->dev = dev;
1379 +                rx_skb[dev_index][index]->ip_summed = CHECKSUM_UNNECESSARY;
1380 +                           skb_put(rx_skb[dev_index][index],pkt_size);
1381 +                           rx_skb[dev_index][index]->protocol = eth_type_trans(rx_skb[dev_index][index],dev); /* set skb protocol */
1382 +                           netif_rx(rx_skb[dev_index][index]);  /* socket rx */
1383 +                           dev->last_rx = jiffies;
1384 +
1385 +                           /* allocate rx skb buffer */
1386 +                if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
1387 +                {
1388 +                    printk("%s::skb buffer allocation fail !\n",__func__);
1389 +                }
1390 +                rx_skb[dev_index][index] = skb;
1391 +                tp->rx_cur_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
1392 +            }
1393 +            else
1394 +            {
1395 +                printk("%s::rx skb index error !\n",__func__);
1396 +            }
1397 +        }
1398 +
1399 +           tp->rx_cur_desc->frame_ctrl.bits_rx.own = DMA; /* release rx descriptor to DMA */
1400 +        /* point to next rx descriptor */
1401 +        tp->rx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->rx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+rx_desc_virtual_base[dev_index]);
1402 +
1403 +        /* release buffer to Remaining Buffer Number Register */
1404 +        if (flow_control_enable[dev_index] ==1)
1405 +        {
1406 +//            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_BNCR,desc_count,0x0000ffff);
1407 +            writel(desc_count,(unsigned int *)(gmac_base_addr[dev_index] + GMAC_BNCR));
1408 +        }
1409 +
1410 +               if (work++ >= quota )
1411 +               {
1412 +                       break;
1413 +               }
1414 +    }
1415 +
1416 +    /* if RX DMA process is stoped , restart it */
1417 +       rxdma_busy.bits.rd_first_des_ptr = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC);
1418 +       if (rxdma_busy.bits.rd_busy == 0)
1419 +       {
1420 +           rxdma_ctrl.bits32 = 0;
1421 +       rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1422 +           rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1423 +           rxdma_ctrl_mask.bits32 = 0;
1424 +       rxdma_ctrl_mask.bits.rd_start = 1;
1425 +           rxdma_ctrl_mask.bits.rd_continue = 1;
1426 +           gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1427 +    }
1428 +
1429 +       dev->quota -= work;
1430 +       *budget -= work;
1431 +       if (work_done==1)
1432 +       {
1433 +           /* Receive descriptor is empty now */
1434 +        netif_rx_complete(dev);
1435 +        /* enable receive interrupt */
1436 +        gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,0x0007c000,0x0007c000);   /* enable rx interrupt */
1437 +        return 0;
1438 +    }
1439 +    else
1440 +    {
1441 +        return -1;
1442 +    }
1443 +}
1444 +
1445 +#endif
1446 +
1447 +static void gmac_rx_packet(struct net_device *dev)
1448 +{
1449 +       struct gmac_private *tp = dev->priv;
1450 +       struct sk_buff          *skb;
1451 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1452 +       GMAC_RXDMA_FIRST_DESC_T rxdma_busy;
1453 +    GMAC_DESCRIPTOR_T   *rx_desc;
1454 +       unsigned int            pkt_size;
1455 +       unsigned int        desc_count;
1456 +    unsigned int        vid;
1457 +//    unsigned int        priority;
1458 +       unsigned int        own;
1459 +       unsigned int        good_frame = 0;
1460 +       unsigned int        i,index;
1461 +       unsigned int        dev_index;
1462 +
1463 +    dev_index = gmac_select_interface(dev);
1464 +
1465 +       for (i=0;i<256;i++)
1466 +       {
1467 +        own = tp->rx_cur_desc->frame_ctrl.bits32 >> 31;
1468 +        if (own == CPU) /* check owner bit */
1469 +        {
1470 +               rx_desc = tp->rx_cur_desc;
1471 +#if (GMAC_DEBUG==1)
1472 +               /* check error interrupt */
1473 +               if ( (rx_desc->frame_ctrl.bits_rx.derr==1)||(rx_desc->frame_ctrl.bits_rx.perr==1) )
1474 +               {
1475 +               printk("%s::Rx Descriptor Processing Error !!!\n",__func__);
1476 +           }
1477 +#endif
1478 +           /* get frame information from the first descriptor of the frame */
1479 +               pkt_size = rx_desc->flag_status.bits_rx_status.frame_count - 4;  /*total byte count in a frame*/
1480 +#if (GMAC_DEBUG==1)
1481 +            priority = rx_desc->flag_status.bits_rx_status.priority;    /* 802.1p priority */
1482 +#endif
1483 +            vid = rx_desc->flag_status.bits_rx_status.vlan_id;          /* 802.1q vlan id */
1484 +            if (vid == 0)
1485 +            {
1486 +                vid = 1;    /* default vlan */
1487 +            }
1488 +               desc_count = rx_desc->frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */
1489 +
1490 +               if (rx_desc->frame_ctrl.bits_rx.frame_state == 0x000) /* good frame */
1491 +               {
1492 +                       tp->stats.rx_bytes += pkt_size;
1493 +                       tp->stats.rx_packets++;
1494 +                       good_frame = 1;
1495 +               }
1496 +               else
1497 +               {
1498 +                       tp->stats.rx_errors++;
1499 +                       good_frame = 0;
1500 +                       printk("RX status: 0x%x\n",rx_desc->frame_ctrl.bits_rx.frame_state);
1501 +               }
1502 +       }
1503 +       else
1504 +       {
1505 +           break;  /* Rx process is completed */
1506 +       }
1507 +
1508 +        if (good_frame == 1)
1509 +        {
1510 +            /* get rx skb buffer index */
1511 +            index = ((unsigned int)tp->rx_cur_desc - rx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1512 +            if (rx_skb[dev_index][index])
1513 +            {
1514 +                skb_reserve (rx_skb[dev_index][index], 2);     /* 16 byte align the IP fields. */
1515 +                rx_skb[dev_index][index]->dev = dev;
1516 +                rx_skb[dev_index][index]->ip_summed = CHECKSUM_UNNECESSARY;
1517 +                           skb_put(rx_skb[dev_index][index],pkt_size);
1518 +                           rx_skb[dev_index][index]->protocol = eth_type_trans(rx_skb[dev_index][index],dev); /* set skb protocol */
1519 +                           netif_rx(rx_skb[dev_index][index]);  /* socket rx */
1520 +                           dev->last_rx = jiffies;
1521 +
1522 +                           /* allocate rx skb buffer */
1523 +                if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
1524 +                {
1525 +                    printk("%s::skb buffer allocation fail !\n",__func__);
1526 +                }
1527 +                rx_skb[dev_index][index] = skb;
1528 +                tp->rx_cur_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
1529 +            }
1530 +            else
1531 +            {
1532 +                printk("%s::rx skb index error !\n",__func__);
1533 +            }
1534 +        }
1535 +
1536 +           tp->rx_cur_desc->frame_ctrl.bits_rx.own = DMA; /* release rx descriptor to DMA */
1537 +        /* point to next rx descriptor */
1538 +        tp->rx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->rx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+rx_desc_virtual_base[dev_index]);
1539 +
1540 +        /* release buffer to Remaining Buffer Number Register */
1541 +        if (flow_control_enable[dev_index] ==1)
1542 +        {
1543 +            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_BNCR,desc_count,0x0000ffff);
1544 +        }
1545 +    }
1546 +
1547 +    /* if RX DMA process is stoped , restart it */
1548 +       rxdma_busy.bits.rd_first_des_ptr = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC);
1549 +       if (rxdma_busy.bits.rd_busy == 0)
1550 +       {
1551 +           rxdma_ctrl.bits32 = 0;
1552 +       rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1553 +           rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1554 +           rxdma_ctrl_mask.bits32 = 0;
1555 +       rxdma_ctrl_mask.bits.rd_start = 1;
1556 +           rxdma_ctrl_mask.bits.rd_continue = 1;
1557 +           gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1558 +    }
1559 +}
1560 +
1561 +#ifdef CONFIG_SL2312_MPAGE
1562 +static inline void free_tx_buf(int dev_index, int desc_index)
1563 +{
1564 +       if (tx_skb[dev_index][desc_index].freeable &&
1565 +           tx_skb[dev_index][desc_index].skb) {
1566 +               struct sk_buff* skb = tx_skb[dev_index][desc_index].skb;
1567 +               //printk("free_skb %x, len %d\n", skb, skb->len);
1568 +#ifdef CONFIG_TXINT_DISABLE
1569 +               dev_kfree_skb(skb);
1570 +#else
1571 +               dev_kfree_skb_irq(skb);
1572 +#endif
1573 +               tx_skb[dev_index][desc_index].skb = 0;
1574 +       }
1575 +}
1576 +
1577 +#ifdef CONFIG_TXINT_DISABLE
1578 +static void gmac_tx_packet_complete(struct net_device *dev)
1579 +{
1580 +       struct gmac_private     *tp = dev->priv;
1581 +    GMAC_DESCRIPTOR_T      *tx_hw_complete_desc, *next_desc;
1582 +    unsigned int desc_cnt=0;
1583 +    unsigned int i,index,dev_index;
1584 +    unsigned int tx_current_descriptor = 0;
1585 +       // int own_dma = 0;
1586 +
1587 +    dev_index = gmac_select_interface(dev);
1588 +
1589 +       index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1590 +       if (tx_skb[dev_index][index].desc_in_use && tp->tx_finished_desc->frame_ctrl.bits_tx_in.own == CPU) {
1591 +               free_tx_buf(dev_index, index);
1592 +               tx_skb[dev_index][index].desc_in_use = 0;
1593 +       }
1594 +       next_desc = (GMAC_DESCRIPTOR_T*)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
1595 +
1596 +       for (;;) {
1597 +               tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0)+ tx_desc_virtual_base[dev_index]);
1598 +               if (next_desc == tx_hw_complete_desc)
1599 +                       break;
1600 +               if (next_desc->frame_ctrl.bits_tx_in.own == CPU) {
1601 +                       if (next_desc->frame_ctrl.bits_tx_in.success_tx == 1) {
1602 +                               tp->stats.tx_bytes += next_desc->flag_status.bits_tx_flag.frame_count;
1603 +                               tp->stats.tx_packets ++;
1604 +                       } else {
1605 +                               tp->stats.tx_errors++;
1606 +                       }
1607 +                       desc_cnt = next_desc->frame_ctrl.bits_tx_in.desc_count;
1608 +                       for (i=1; i<desc_cnt; i++) {
1609 +                               /* get tx skb buffer index */
1610 +                               index = ((unsigned int)next_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1611 +                               next_desc->frame_ctrl.bits_tx_in.own = CPU;
1612 +                               free_tx_buf(dev_index, index);
1613 +                               tx_skb[dev_index][index].desc_in_use = 0;
1614 +                               tp->tx_desc_tail[dev_index] = (tp->tx_desc_tail[dev_index] +1) & (TX_DESC_NUM-1);
1615 +                               /* release Tx descriptor to CPU */
1616 +                               next_desc = (GMAC_DESCRIPTOR_T *)((next_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1617 +                       }
1618 +                       /* get tx skb buffer index */
1619 +                       index = ((unsigned int)next_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1620 +                       /* free skb buffer */
1621 +                       next_desc->frame_ctrl.bits_tx_in.own = CPU;
1622 +                       free_tx_buf(dev_index, index);
1623 +                       tx_skb[dev_index][index].desc_in_use = 0;
1624 +                       tp->tx_desc_tail[dev_index] = (tp->tx_desc_tail[dev_index] +1) & (TX_DESC_NUM-1);
1625 +                       tp->tx_finished_desc = next_desc;
1626 +//                     printk("finish tx_desc index %d\n", index);
1627 +                       next_desc = (GMAC_DESCRIPTOR_T *)((next_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1628 +               }
1629 +               else
1630 +                       break;
1631 +       }
1632 +       if (netif_queue_stopped(dev))
1633 +       {
1634 +               netif_wake_queue(dev);
1635 +       }
1636 +
1637 +}
1638 +#else
1639 +static void gmac_tx_packet_complete(struct net_device *dev)
1640 +{
1641 +       struct gmac_private     *tp = dev->priv;
1642 +       GMAC_DESCRIPTOR_T           *tx_hw_complete_desc;
1643 +       unsigned int desc_cnt=0;
1644 +       unsigned int i,index,dev_index;
1645 +       unsigned int tx_current_descriptor = 0;
1646 +       // int own_dma = 0;
1647 +
1648 +       dev_index = gmac_select_interface(dev);
1649 +
1650 +       index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1651 +
1652 +       /* check tx status and accumulate tx statistics */
1653 +       for (;;)
1654 +       {
1655 +
1656 +        for (i=0;i<1000;i++)
1657 +        {
1658 +            tx_current_descriptor = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC);
1659 +            if ( ((tx_current_descriptor & 0x00000003)==0x00000003) ||  /* only one descriptor */
1660 +                 ((tx_current_descriptor & 0x00000003)==0x00000001) )   /* the last descriptor */
1661 +            {
1662 +                break;
1663 +            }
1664 +            udelay(1);
1665 +        }
1666 +        if (i==1000)
1667 +        {
1668 +//            gmac_dump_register(dev);
1669 +//            printk("%s: tx current descriptor = %x \n",__func__,tx_current_descriptor);
1670 +//            printk_all(dev_index, tp);
1671 +            continue;
1672 +        }
1673 +
1674 +           /* get tx H/W completed descriptor virtual address */
1675 +       tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((tx_current_descriptor & 0xfffffff0)+ tx_desc_virtual_base[dev_index]);
1676 +//     tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0)+ tx_desc_virtual_base[dev_index]);
1677 +           if (tp->tx_finished_desc == tx_hw_complete_desc ) // ||
1678 +                   //tx_skb[dev_index][index].desc_in_use )   /* complete tx processing */
1679 +               {
1680 +                       break;
1681 +               }
1682 +
1683 +        for (;;)
1684 +        {
1685 +               if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.own == CPU)
1686 +               {
1687 +    #if (GMAC_DEBUG==1)
1688 +                       if ( (tp->tx_finished_desc->frame_ctrl.bits_tx_in.derr) ||
1689 +                          (tp->tx_finished_desc->frame_ctrl.bits_tx_in.perr) )
1690 +                       {
1691 +                               printk("%s::Descriptor Processing Error !!!\n",__func__);
1692 +                       }
1693 +    #endif
1694 +                       if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.success_tx == 1)
1695 +                       {
1696 +                               tp->stats.tx_bytes += tp->tx_finished_desc->flag_status.bits_tx_flag.frame_count;
1697 +                               tp->stats.tx_packets ++;
1698 +                       }
1699 +                       else
1700 +                       {
1701 +                               tp->stats.tx_errors++;
1702 +                       }
1703 +                       desc_cnt = tp->tx_finished_desc->frame_ctrl.bits_tx_in.desc_count;
1704 +                       for (i=1; i<desc_cnt; i++)  /* multi-descriptor in one packet */
1705 +                       {
1706 +                               /* get tx skb buffer index */
1707 +                               index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1708 +                               tp->tx_finished_desc->frame_ctrl.bits_tx_in.own = CPU;
1709 +                               free_tx_buf(dev_index, index);
1710 +                               tx_skb[dev_index][index].desc_in_use = 0;
1711 +                               /* release Tx descriptor to CPU */
1712 +                               tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1713 +                       }
1714 +                       /* get tx skb buffer index */
1715 +                       index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1716 +                       /* free skb buffer */
1717 +                       tp->tx_finished_desc->frame_ctrl.bits_tx_in.own = CPU;
1718 +                       free_tx_buf(dev_index, index);
1719 +                       tx_skb[dev_index][index].desc_in_use = 0;
1720 +                       tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1721 +
1722 +                   if (tp->tx_finished_desc == tx_hw_complete_desc )
1723 +                       {
1724 +                               break;
1725 +                       }
1726 +            }
1727 +               else
1728 +               {
1729 +                       break;
1730 +                       }
1731 +               }
1732 +       }
1733 +
1734 +       if (netif_queue_stopped(dev))
1735 +       {
1736 +               netif_wake_queue(dev);
1737 +       }
1738 +
1739 +}
1740 +#endif
1741 +#else
1742 +
1743 +static void gmac_tx_packet_complete(struct net_device *dev)
1744 +{
1745 +       struct gmac_private     *tp = dev->priv;
1746 +    GMAC_DESCRIPTOR_T      *tx_hw_complete_desc;
1747 +    unsigned int desc_cnt=0;
1748 +    unsigned int i,index,dev_index;
1749 +
1750 +    dev_index = gmac_select_interface(dev);
1751 +
1752 +       /* get tx H/W completed descriptor virtual address */
1753 +       tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0)+ tx_desc_virtual_base[dev_index]);
1754 +       /* check tx status and accumulate tx statistics */
1755 +    for (;;)
1756 +    {
1757 +        if (tp->tx_finished_desc == tx_hw_complete_desc)   /* complete tx processing */
1758 +        {
1759 +            break;
1760 +        }
1761 +       if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.own == CPU)
1762 +       {
1763 +#if (GMAC_DEBUG==1)
1764 +           if ( (tp->tx_finished_desc->frame_ctrl.bits_tx_in.derr) ||
1765 +                (tp->tx_finished_desc->frame_ctrl.bits_tx_in.perr) )
1766 +           {
1767 +               printk("%s::Descriptor Processing Error !!!\n",__func__);
1768 +           }
1769 +#endif
1770 +            if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.success_tx == 1)
1771 +            {
1772 +                tp->stats.tx_bytes += tp->tx_finished_desc->flag_status.bits_tx_flag.frame_count;
1773 +                tp->stats.tx_packets ++;
1774 +            }
1775 +            else
1776 +            {
1777 +                tp->stats.tx_errors++;
1778 +            }
1779 +            desc_cnt = tp->tx_finished_desc->frame_ctrl.bits_tx_in.desc_count;
1780 +               for (i=1; i<desc_cnt; i++)  /* multi-descriptor in one packet */
1781 +               {
1782 +                /* get tx skb buffer index */
1783 +                index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1784 +                /* free skb buffer */
1785 +                if (tx_skb[dev_index][index])
1786 +                {
1787 +                           dev_kfree_skb_irq(tx_skb[dev_index][index]);
1788 +                       }
1789 +                   /* release Tx descriptor to CPU */
1790 +                tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1791 +                tp->tx_finished_desc->frame_ctrl.bits_tx_in.own = CPU;
1792 +               }
1793 +            /* get tx skb buffer index */
1794 +            index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1795 +            /* free skb buffer */
1796 +            if (tx_skb[dev_index][index])
1797 +            {
1798 +                   dev_kfree_skb_irq(tx_skb[dev_index][index]);
1799 +               }
1800 +            tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1801 +       }
1802 +    }
1803 +
1804 +       if (netif_queue_stopped(dev))
1805 +       {
1806 +           netif_wake_queue(dev);
1807 +       }
1808 +
1809 +}
1810 +
1811 +
1812 +#endif
1813 +
1814 +#if 0
1815 +static void gmac_weird_interrupt(struct net_device *dev)
1816 +{
1817 +    gmac_dump_register(dev);
1818 +}
1819 +#endif
1820 +
1821 +/* The interrupt handler does all of the Rx thread work and cleans up
1822 +   after the Tx thread. */
1823 +static irqreturn_t gmac_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
1824 +{
1825 +       struct net_device       *dev = (struct net_device *)dev_instance;
1826 +       GMAC_RXDMA_FIRST_DESC_T rxdma_busy;
1827 +//     GMAC_TXDMA_FIRST_DESC_T txdma_busy;
1828 +//    GMAC_TXDMA_CTRL_T       txdma_ctrl,txdma_ctrl_mask;
1829 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1830 +       GMAC_DMA_STATUS_T           status;
1831 +    unsigned int            i,dev_index;
1832 +       int                     handled = 0;
1833 +
1834 +    dev_index = gmac_select_interface(dev);
1835 +
1836 +       handled = 1;
1837 +
1838 +#ifdef CONFIG_SL_NAPI
1839 +       disable_irq(gmac_irq[dev_index]);   /* disable GMAC interrupt */
1840 +
1841 +    status.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS);         /* read DMA status */
1842 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS,status.bits32,status.bits32);    /* clear DMA status */
1843 +
1844 +    if (status.bits.rx_overrun == 1)
1845 +    {
1846 +               printk("%s::RX Overrun !!!%d\n",__func__,gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RBNR));
1847 +         gmac_dump_register(dev);
1848 +        /* if RX DMA process is stoped , restart it */
1849 +        rxdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC) ;
1850 +        if (rxdma_busy.bits.rd_busy == 0)
1851 +        {
1852 +            /* restart Rx DMA process */
1853 +               rxdma_ctrl.bits32 = 0;
1854 +               rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1855 +            rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1856 +            rxdma_ctrl_mask.bits32 = 0;
1857 +               rxdma_ctrl_mask.bits.rd_start = 1;
1858 +            rxdma_ctrl_mask.bits.rd_continue = 1;
1859 +            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1860 +        }
1861 +    }
1862 +
1863 +    /* process rx packet */
1864 +       if (netif_running(dev) && ((status.bits.rs_eofi==1)||(status.bits.rs_finish==1)))
1865 +       {
1866 +        if (likely(netif_rx_schedule_prep(dev)))
1867 +        {
1868 +            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,0,0x0007c000);   /* disable rx interrupt */
1869 +            __netif_rx_schedule(dev);
1870 +        }
1871 +    }
1872 +#ifndef CONFIG_TXINT_DISABLE
1873 +    /* process tx packet */
1874 +       if (netif_running(dev) && ((status.bits.ts_eofi==1)||(status.bits.ts_finish==1)))
1875 +       {
1876 +               gmac_tx_packet_complete(dev);
1877 +       }
1878 +#endif
1879 +
1880 +       enable_irq(gmac_irq[dev_index]);    /* enable GMAC interrupt */
1881 +    return IRQ_RETVAL(handled);
1882 +#endif
1883 +
1884 +   /* disable GMAC interrupt */
1885 +       disable_irq(gmac_irq[dev_index]);
1886 +    for (i=0;i<MAX_ISR_WORK;i++)
1887 +    {
1888 +        /* read DMA status */
1889 +           status.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS);
1890 +int_status = status.bits32;
1891 +           /* clear DMA status */
1892 +        gmac_write_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS,status.bits32,status.bits32);
1893 +
1894 +        if ((status.bits32 & 0xffffc000)==0)
1895 +        {
1896 +            break;
1897 +        }
1898 +
1899 +           if (status.bits.rx_overrun == 1)
1900 +           {
1901 +                       printk("%s::RX Overrun !!!%d\n",__func__,gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RBNR));
1902 +               gmac_dump_register(dev);
1903 +            /* if RX DMA process is stoped , restart it */
1904 +               rxdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC) ;
1905 +               if (rxdma_busy.bits.rd_busy == 0)
1906 +               {
1907 +                   /* restart Rx DMA process */
1908 +               rxdma_ctrl.bits32 = 0;
1909 +               rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1910 +                   rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1911 +                   rxdma_ctrl_mask.bits32 = 0;
1912 +               rxdma_ctrl_mask.bits.rd_start = 1;
1913 +                   rxdma_ctrl_mask.bits.rd_continue = 1;
1914 +                   gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1915 +            }
1916 +           }
1917 +
1918 +        /* receive rx interrupt */
1919 +       if (netif_running(dev) && ((status.bits.rs_eofi==1)||(status.bits.rs_finish==1)))
1920 +       {
1921 +               gmac_rx_packet(dev);
1922 +//             gmac_tx_packet_complete(dev);
1923 +        }
1924 +
1925 +        /* receive tx interrupt */
1926 +       // if (netif_running(dev) && (status.bits.ts_finish==1))
1927 +#ifndef CONFIG_TXINT_DISABLE
1928 +       if (netif_running(dev) && ((status.bits.ts_eofi==1)||
1929 +                          (status.bits.ts_finish==1)))
1930 +       {
1931 +               gmac_tx_packet_complete(dev);
1932 +       }
1933 +#endif
1934 +       /* check uncommon events */
1935 +/*        if ((status.bits32 & 0x632fc000)!=0)
1936 +        {
1937 +            printk("%s::DMA Status = %08x \n",__func__,status.bits32);
1938 +            gmac_weird_interrupt(dev);
1939 +        }
1940 +*/
1941 +       }
1942 +
1943 +    /* enable GMAC interrupt */
1944 +       enable_irq(gmac_irq[dev_index]);
1945 +       //printk("gmac_interrupt complete!\n\n");
1946 +       return IRQ_RETVAL(handled);
1947 +}
1948 +
1949 +static void gmac_hw_start(struct net_device *dev)
1950 +{
1951 +       struct gmac_private     *tp = dev->priv;
1952 +       GMAC_TXDMA_CURR_DESC_T  tx_desc;
1953 +       GMAC_RXDMA_CURR_DESC_T  rx_desc;
1954 +    GMAC_TXDMA_CTRL_T       txdma_ctrl,txdma_ctrl_mask;
1955 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1956 +       GMAC_DMA_STATUS_T       dma_status,dma_status_mask;
1957 +       int                                             dev_index;
1958 +
1959 +    dev_index = gmac_select_interface(dev);
1960 +
1961 +       /* program TxDMA Current Descriptor Address register for first descriptor */
1962 +       tx_desc.bits32 = (unsigned int)(tp->tx_desc_dma);
1963 +       tx_desc.bits.eofie = 1;
1964 +       tx_desc.bits.sof_eof = 0x03;
1965 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC,tx_desc.bits32,0xffffffff);
1966 +       gmac_write_reg(gmac_base_addr[dev_index] + 0xff2c,tx_desc.bits32,0xffffffff);   /* tx next descriptor address */
1967 +
1968 +       /* program RxDMA Current Descriptor Address register for first descriptor */
1969 +       rx_desc.bits32 = (unsigned int)(tp->rx_desc_dma);
1970 +       rx_desc.bits.eofie = 1;
1971 +       rx_desc.bits.sof_eof = 0x03;
1972 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CURR_DESC,rx_desc.bits32,0xffffffff);
1973 +       gmac_write_reg(gmac_base_addr[dev_index] + 0xff3c,rx_desc.bits32,0xffffffff);   /* rx next descriptor address */
1974 +
1975 +       /* enable GMAC interrupt & disable loopback */
1976 +       dma_status.bits32 = 0;
1977 +       dma_status.bits.loop_back = 0;  /* disable DMA loop-back mode */
1978 +//     dma_status.bits.m_tx_fail = 1;
1979 +       dma_status.bits.m_cnt_full = 1;
1980 +       dma_status.bits.m_rx_pause_on = 1;
1981 +       dma_status.bits.m_tx_pause_on = 1;
1982 +       dma_status.bits.m_rx_pause_off = 1;
1983 +       dma_status.bits.m_tx_pause_off = 1;
1984 +       dma_status.bits.m_rx_overrun = 1;
1985 +       dma_status.bits.m_link_change = 1;
1986 +       dma_status_mask.bits32 = 0;
1987 +       dma_status_mask.bits.loop_back = 1;
1988 +//     dma_status_mask.bits.m_tx_fail = 1;
1989 +       dma_status_mask.bits.m_cnt_full = 1;
1990 +       dma_status_mask.bits.m_rx_pause_on = 1;
1991 +       dma_status_mask.bits.m_tx_pause_on = 1;
1992 +       dma_status_mask.bits.m_rx_pause_off = 1;
1993 +       dma_status_mask.bits.m_tx_pause_off = 1;
1994 +       dma_status_mask.bits.m_rx_overrun = 1;
1995 +       dma_status_mask.bits.m_link_change = 1;
1996 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS,dma_status.bits32,dma_status_mask.bits32);
1997 +
1998 +    /* program tx dma control register */
1999 +       txdma_ctrl.bits32 = 0;
2000 +       txdma_ctrl.bits.td_start = 0;    /* start TX DMA transfer */
2001 +       txdma_ctrl.bits.td_continue = 0; /* continue Tx DMA operation */
2002 +       txdma_ctrl.bits.td_chain_mode = 1;  /* chain mode */
2003 +       txdma_ctrl.bits.td_prot = 0;
2004 +       txdma_ctrl.bits.td_burst_size = 2;  /* DMA burst size for every AHB request */
2005 +       txdma_ctrl.bits.td_bus = 2;         /* peripheral bus width */
2006 +       txdma_ctrl.bits.td_endian = 0;      /* little endian */
2007 +#ifdef CONFIG_TXINT_DISABLE
2008 +       txdma_ctrl.bits.td_finish_en = 0;   /* DMA finish event interrupt disable */
2009 +#else
2010 +       txdma_ctrl.bits.td_finish_en = 1;   /* DMA finish event interrupt enable */
2011 +#endif
2012 +       txdma_ctrl.bits.td_fail_en = 1;     /* DMA fail interrupt enable */
2013 +       txdma_ctrl.bits.td_perr_en = 1;     /* protocol failure interrupt enable */
2014 +       txdma_ctrl.bits.td_eod_en = 0;      /* disable Tx End of Descriptor Interrupt */
2015 +       //txdma_ctrl.bits.td_eod_en = 0;      /* disable Tx End of Descriptor Interrupt */
2016 +#ifdef CONFIG_TXINT_DISABLE
2017 +       txdma_ctrl.bits.td_eof_en = 0;      /* end of frame interrupt disable */
2018 +#else
2019 +       txdma_ctrl.bits.td_eof_en = 1;      /* end of frame interrupt enable */
2020 +#endif
2021 +       txdma_ctrl_mask.bits32 = 0;
2022 +       txdma_ctrl_mask.bits.td_start = 1;
2023 +       txdma_ctrl_mask.bits.td_continue = 1;
2024 +       txdma_ctrl_mask.bits.td_chain_mode = 1;
2025 +       txdma_ctrl_mask.bits.td_prot = 15;
2026 +       txdma_ctrl_mask.bits.td_burst_size = 3;
2027 +       txdma_ctrl_mask.bits.td_bus = 3;
2028 +       txdma_ctrl_mask.bits.td_endian = 1;
2029 +       txdma_ctrl_mask.bits.td_finish_en = 1;
2030 +       txdma_ctrl_mask.bits.td_fail_en = 1;
2031 +       txdma_ctrl_mask.bits.td_perr_en = 1;
2032 +       txdma_ctrl_mask.bits.td_eod_en = 1;
2033 +       //txdma_ctrl_mask.bits.td_eod_en = 1;
2034 +       txdma_ctrl_mask.bits.td_eof_en = 1;
2035 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,txdma_ctrl.bits32,txdma_ctrl_mask.bits32);
2036 +
2037 +    /* program rx dma control register */
2038 +       rxdma_ctrl.bits32 = 0;
2039 +       rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
2040 +       rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
2041 +       rxdma_ctrl.bits.rd_chain_mode = 1;  /* chain mode */
2042 +       rxdma_ctrl.bits.rd_prot = 0;
2043 +       rxdma_ctrl.bits.rd_burst_size = 2;  /* DMA burst size for every AHB request */
2044 +       rxdma_ctrl.bits.rd_bus = 2;         /* peripheral bus width */
2045 +       rxdma_ctrl.bits.rd_endian = 0;      /* little endian */
2046 +       rxdma_ctrl.bits.rd_finish_en = 1;   /* DMA finish event interrupt enable */
2047 +       rxdma_ctrl.bits.rd_fail_en = 1;     /* DMA fail interrupt enable */
2048 +       rxdma_ctrl.bits.rd_perr_en = 1;     /* protocol failure interrupt enable */
2049 +       rxdma_ctrl.bits.rd_eod_en = 0;      /* disable Rx End of Descriptor Interrupt */
2050 +       rxdma_ctrl.bits.rd_eof_en = 1;      /* end of frame interrupt enable */
2051 +       rxdma_ctrl_mask.bits32 = 0;
2052 +       rxdma_ctrl_mask.bits.rd_start = 1;
2053 +       rxdma_ctrl_mask.bits.rd_continue = 1;
2054 +       rxdma_ctrl_mask.bits.rd_chain_mode = 1;
2055 +       rxdma_ctrl_mask.bits.rd_prot = 15;
2056 +       rxdma_ctrl_mask.bits.rd_burst_size = 3;
2057 +       rxdma_ctrl_mask.bits.rd_bus = 3;
2058 +       rxdma_ctrl_mask.bits.rd_endian = 1;
2059 +       rxdma_ctrl_mask.bits.rd_finish_en = 1;
2060 +       rxdma_ctrl_mask.bits.rd_fail_en = 1;
2061 +       rxdma_ctrl_mask.bits.rd_perr_en = 1;
2062 +       rxdma_ctrl_mask.bits.rd_eod_en = 1;
2063 +       rxdma_ctrl_mask.bits.rd_eof_en = 1;
2064 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
2065 +    return;
2066 +}
2067 +
2068 +static void gmac_hw_stop(struct net_device *dev)
2069 +{
2070 +    GMAC_TXDMA_CTRL_T       txdma_ctrl,txdma_ctrl_mask;
2071 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
2072 +       int                                     dev_index;
2073 +
2074 +    dev_index = gmac_select_interface(dev);
2075 +
2076 +    /* program tx dma control register */
2077 +       txdma_ctrl.bits32 = 0;
2078 +       txdma_ctrl.bits.td_start = 0;
2079 +       txdma_ctrl.bits.td_continue = 0;
2080 +       txdma_ctrl_mask.bits32 = 0;
2081 +       txdma_ctrl_mask.bits.td_start = 1;
2082 +       txdma_ctrl_mask.bits.td_continue = 1;
2083 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,txdma_ctrl.bits32,txdma_ctrl_mask.bits32);
2084 +    /* program rx dma control register */
2085 +       rxdma_ctrl.bits32 = 0;
2086 +       rxdma_ctrl.bits.rd_start = 0;    /* stop RX DMA transfer */
2087 +       rxdma_ctrl.bits.rd_continue = 0; /* stop continue RX DMA operation */
2088 +       rxdma_ctrl_mask.bits32 = 0;
2089 +       rxdma_ctrl_mask.bits.rd_start = 1;
2090 +       rxdma_ctrl_mask.bits.rd_continue = 1;
2091 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
2092 +}
2093 +
2094 +static int gmac_init_desc_buf(struct net_device *dev)
2095 +{
2096 +       struct gmac_private *tp = dev->priv;
2097 +       struct sk_buff          *skb;
2098 +       dma_addr_t          tx_first_desc_dma=0;
2099 +       dma_addr_t          rx_first_desc_dma=0;
2100 +       dma_addr_t          rx_first_buf_dma=0;
2101 +       unsigned int        i,index;
2102 +
2103 +    printk("Descriptor buffer init......\n");
2104 +
2105 +    /* get device index number */
2106 +    index = gmac_get_dev_index(dev);
2107 +#ifdef CONFIG_SL2312_MPAGE
2108 +       for (i=0; i<TX_DESC_NUM; i++) {
2109 +               tx_skb[index][i].freeable = 0;
2110 +               tx_skb[index][i].skb = 0;
2111 +               tx_skb[index][i].desc_in_use = 0;
2112 +               tx_skb[index][i].end_seq = 0;
2113 +       }
2114 +#else
2115 +    for (i=0;i<TX_DESC_NUM;i++)
2116 +    {
2117 +        tx_skb[index][i] = NULL;
2118 +    }
2119 +#endif
2120 +    for (i=0;i<RX_DESC_NUM;i++)
2121 +    {
2122 +        rx_skb[index][i] = NULL;
2123 +    }
2124 +
2125 +       /* allocates TX/RX descriptors */
2126 +       tp->tx_desc = DMA_MALLOC(TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(dma_addr_t *)&tp->tx_desc_dma);
2127 +    tx_desc_virtual_base[index] = (unsigned int)tp->tx_desc - (unsigned int)tp->tx_desc_dma;
2128 +    memset(tp->tx_desc,0x00,TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T));
2129 +       tp->rx_desc = DMA_MALLOC(RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(dma_addr_t *)&tp->rx_desc_dma);
2130 +    rx_desc_virtual_base[index] = (unsigned int)tp->rx_desc - (unsigned int)tp->rx_desc_dma;
2131 +    memset(tp->rx_desc,0x00,RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T));
2132 +    tx_desc_start_adr[index] = (unsigned int)tp->tx_desc;   /* for tx skb index calculation */
2133 +    rx_desc_start_adr[index] = (unsigned int)tp->rx_desc;   /* for rx skb index calculation */
2134 +    printk("tx_desc = %08x\n",(unsigned int)tp->tx_desc);
2135 +    printk("rx_desc = %08x\n",(unsigned int)tp->rx_desc);
2136 +       printk("tx_desc_dma = %08x\n",tp->tx_desc_dma);
2137 +       printk("rx_desc_dma = %08x\n",tp->rx_desc_dma);
2138 +
2139 +       if (tp->tx_desc==0x00 || tp->rx_desc==0x00)
2140 +       {
2141 +               free_irq(dev->irq, dev);
2142 +
2143 +               if (tp->tx_desc)
2144 +                       DMA_MFREE(tp->tx_desc, TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),tp->tx_desc_dma);
2145 +               if (tp->rx_desc)
2146 +                       DMA_MFREE(tp->rx_desc, RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),tp->rx_desc_dma);
2147 +               return -ENOMEM;
2148 +       }
2149 +
2150 +       /* TX descriptors initial */
2151 +       tp->tx_cur_desc = tp->tx_desc;  /* virtual address */
2152 +       tp->tx_finished_desc = tp->tx_desc; /* virtual address */
2153 +       tx_first_desc_dma = tp->tx_desc_dma; /* physical address */
2154 +       for (i = 1; i < TX_DESC_NUM; i++)
2155 +       {
2156 +               tp->tx_desc->frame_ctrl.bits_tx_out.own = CPU; /* set owner to CPU */
2157 +               tp->tx_desc->frame_ctrl.bits_tx_out.buffer_size = TX_BUF_SIZE;  /* set tx buffer size for descriptor */
2158 +               tp->tx_desc_dma = tp->tx_desc_dma + sizeof(GMAC_DESCRIPTOR_T); /* next tx descriptor DMA address */
2159 +               tp->tx_desc->next_desc.next_descriptor = tp->tx_desc_dma | 0x0000000b;
2160 +               tp->tx_desc = &tp->tx_desc[1] ; /* next tx descriptor virtual address */
2161 +       }
2162 +       /* the last descriptor will point back to first descriptor */
2163 +       tp->tx_desc->frame_ctrl.bits_tx_out.own = CPU;
2164 +       tp->tx_desc->frame_ctrl.bits_tx_out.buffer_size = TX_BUF_SIZE;
2165 +       tp->tx_desc->next_desc.next_descriptor = tx_first_desc_dma | 0x0000000b;
2166 +       tp->tx_desc = tp->tx_cur_desc;
2167 +       tp->tx_desc_dma = tx_first_desc_dma;
2168 +
2169 +       /* RX descriptors initial */
2170 +       tp->rx_cur_desc = tp->rx_desc;  /* virtual address */
2171 +       rx_first_desc_dma = tp->rx_desc_dma; /* physical address */
2172 +       for (i = 1; i < RX_DESC_NUM; i++)
2173 +       {
2174 +        if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
2175 +        {
2176 +            printk("%s::skb buffer allocation fail !\n",__func__);
2177 +        }
2178 +        rx_skb[index][i-1] = skb;
2179 +        tp->rx_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
2180 +               tp->rx_desc->frame_ctrl.bits_rx.own = DMA;  /* set owner bit to DMA */
2181 +               tp->rx_desc->frame_ctrl.bits_rx.buffer_size = RX_BUF_SIZE; /* set rx buffer size for descriptor */
2182 +               tp->rx_bufs_dma = tp->rx_bufs_dma + RX_BUF_SIZE;    /* point to next buffer address */
2183 +               tp->rx_desc_dma = tp->rx_desc_dma + sizeof(GMAC_DESCRIPTOR_T); /* next rx descriptor DMA address */
2184 +               tp->rx_desc->next_desc.next_descriptor = tp->rx_desc_dma | 0x0000000b;
2185 +               tp->rx_desc = &tp->rx_desc[1]; /* next rx descriptor virtual address */
2186 +       }
2187 +       /* the last descriptor will point back to first descriptor */
2188 +    if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
2189 +    {
2190 +        printk("%s::skb buffer allocation fail !\n",__func__);
2191 +    }
2192 +    rx_skb[index][i-1] = skb;
2193 +    tp->rx_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
2194 +       tp->rx_desc->frame_ctrl.bits_rx.own = DMA;
2195 +       tp->rx_desc->frame_ctrl.bits_rx.buffer_size = RX_BUF_SIZE;
2196 +       tp->rx_desc->next_desc.next_descriptor = rx_first_desc_dma | 0x0000000b;
2197 +       tp->rx_desc = tp->rx_cur_desc;
2198 +       tp->rx_desc_dma = rx_first_desc_dma;
2199 +       tp->rx_bufs_dma = rx_first_buf_dma;
2200 +
2201 +       for (i=0; i<GMAC_PHY_IF; i++) {
2202 +               tp->tx_desc_hdr[i] = 0;
2203 +               tp->tx_desc_tail[i] = 0;
2204 +       }
2205 +       return (0);
2206 +}
2207 +
2208 +static int gmac_clear_counter (struct net_device *dev)
2209 +{
2210 +       struct gmac_private *tp = dev->priv;
2211 +       unsigned int    dev_index;
2212 +
2213 +    dev_index = gmac_select_interface(dev);
2214 +//     tp = gmac_dev[index]->priv;
2215 +    /* clear counter */
2216 +    gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_DISCARDS);
2217 +    gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_ERRORS);
2218 +    tp->stats.tx_bytes = 0;
2219 +    tp->stats.tx_packets = 0;
2220 +       tp->stats.tx_errors = 0;
2221 +    tp->stats.rx_bytes = 0;
2222 +       tp->stats.rx_packets = 0;
2223 +       tp->stats.rx_errors = 0;
2224 +    tp->stats.rx_dropped = 0;
2225 +       return (0);
2226 +}
2227 +
2228 +static int gmac_open (struct net_device *dev)
2229 +{
2230 +       struct gmac_private     *tp = dev->priv;
2231 +       int    retval;
2232 +
2233 +    gmac_select_interface(dev);
2234 +
2235 +       /* chip reset */
2236 +       gmac_sw_reset(dev);
2237 +
2238 +    /* allocates tx/rx descriptor and buffer memory */
2239 +    gmac_init_desc_buf(dev);
2240 +
2241 +    /* get mac address from FLASH */
2242 +    gmac_get_mac_address();
2243 +
2244 +    /* set PHY register to start autonegition process */
2245 +    gmac_set_phy_status(dev);
2246 +
2247 +       /* GMAC initialization */
2248 +       if (gmac_init_chip(dev))
2249 +       {
2250 +               printk (KERN_ERR "GMAC init fail\n");
2251 +       }
2252 +
2253 +    /* start DMA process */
2254 +       gmac_hw_start(dev);
2255 +
2256 +    /* enable tx/rx register */
2257 +    gmac_enable_tx_rx(dev);
2258 +
2259 +    /* clear statistic counter */
2260 +    gmac_clear_counter(dev);
2261 +
2262 +       netif_start_queue (dev);
2263 +
2264 +    /* hook ISR */
2265 +       retval = request_irq (dev->irq, gmac_interrupt, SA_INTERRUPT, dev->name, dev);
2266 +       if (retval)
2267 +               return retval;
2268 +
2269 +       if(!FLAG_SWITCH)
2270 +       {
2271 +       init_waitqueue_head (&tp->thr_wait);
2272 +       init_completion(&tp->thr_exited);
2273 +
2274 +       tp->time_to_die = 0;
2275 +       tp->thr_pid = kernel_thread (gmac_phy_thread, dev, CLONE_FS | CLONE_FILES);
2276 +       if (tp->thr_pid < 0)
2277 +       {
2278 +               printk (KERN_WARNING "%s: unable to start kernel thread\n",dev->name);
2279 +       }
2280 +    }
2281 +       return (0);
2282 +}
2283 +
2284 +static int gmac_close(struct net_device *dev)
2285 +{
2286 +    struct gmac_private *tp = dev->priv;
2287 +    unsigned int        i,dev_index;
2288 +    unsigned int        ret;
2289 +
2290 +    dev_index = gmac_get_dev_index(dev);
2291 +
2292 +    /* stop tx/rx packet */
2293 +    gmac_disable_tx_rx(dev);
2294 +
2295 +    /* stop the chip's Tx and Rx DMA processes */
2296 +       gmac_hw_stop(dev);
2297 +
2298 +    netif_stop_queue(dev);
2299 +
2300 +    /* disable interrupts by clearing the interrupt mask */
2301 +    synchronize_irq();
2302 +    free_irq(dev->irq,dev);
2303 +
2304 +       DMA_MFREE(tp->tx_desc, TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(unsigned int)tp->tx_desc_dma);
2305 +       DMA_MFREE(tp->rx_desc, RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(unsigned int)tp->rx_desc_dma);
2306 +
2307 +#ifdef CONFIG_SL2312_MPAGE
2308 +//     kfree(tx_skb);
2309 +#endif
2310 +
2311 +    for (i=0;i<RX_DESC_NUM;i++)
2312 +    {
2313 +        if (rx_skb[dev_index][i])
2314 +        {
2315 +            dev_kfree_skb(rx_skb[dev_index][i]);
2316 +        }
2317 +    }
2318 +       if(!FLAG_SWITCH)
2319 +       {
2320 +       if (tp->thr_pid >= 0)
2321 +       {
2322 +                   tp->time_to_die = 1;
2323 +               wmb();
2324 +               ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2325 +               if (ret)
2326 +               {
2327 +                       printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2328 +                       return ret;
2329 +               }
2330 +//             wait_for_completion (&tp->thr_exited);
2331 +       }
2332 +    }
2333 +
2334 +    return (0);
2335 +}
2336 +
2337 +#ifdef CONFIG_SL2312_MPAGE
2338 +int printk_all(int dev_index, struct gmac_private* tp)
2339 +{
2340 +       int i=0;
2341 +    unsigned int tx_current_descriptor = 0;
2342 +    int hw_index;
2343 +    int fi;
2344 +    GMAC_DESCRIPTOR_T* tmp_desc;
2345 +
2346 +       GMAC_DESCRIPTOR_T* cur_desc=tp->tx_cur_desc;
2347 +       fi = ((unsigned int)cur_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2348 +       printk("tmp_desc %x, id %d\n", (int)cur_desc, fi);
2349 +
2350 +       tmp_desc = (GMAC_DESCRIPTOR_T*)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2351 +       hw_index = ((unsigned int)tmp_desc - tx_desc_start_adr[dev_index])/ sizeof(GMAC_DESCRIPTOR_T);
2352 +       printk("hd_desc %x, ind %d, fin desc %x\n",(int)tmp_desc, hw_index, (int)tp->tx_finished_desc);
2353 +
2354 +       for (i=0; i<TX_DESC_NUM; i++) {
2355 +               printk("**id %4d, hw_index %4d ==> ", fi, hw_index);
2356 +               printk("fc %8x ", tmp_desc->frame_ctrl.bits32);
2357 +               printk("fs %8x ", tmp_desc->flag_status.bits32);
2358 +               printk("fb %8x ", tmp_desc->buf_adr);
2359 +               printk("fd %8x\n",  tmp_desc->next_desc.next_descriptor);
2360 +               tmp_desc = (GMAC_DESCRIPTOR_T*)((tmp_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2361 +               fi = ((unsigned int)tmp_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2362 +       }
2363 +    tx_current_descriptor = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC);
2364 +    printk("%s: tx current descriptor = %x \n",__func__,tx_current_descriptor);
2365 +    printk("%s: interrupt status = %x \n",__func__,int_status);
2366 +    return 0;
2367 +}
2368 +
2369 +int cleanup_desc(int dev_index, struct gmac_private* tp)
2370 +{
2371 +       int i=0;
2372 +       int index = ((unsigned int)tp->tx_cur_desc - tx_desc_start_adr[dev_index])/sizeof(GMAC_DESCRIPTOR_T);
2373 +       GMAC_DESCRIPTOR_T* fill_desc = tp->tx_cur_desc;
2374 +
2375 +       for (i=0; i< TX_DESC_NUM; i++)
2376 +       {
2377 +               fill_desc->frame_ctrl.bits_tx_out.own = CPU;
2378 +               fill_desc->frame_ctrl.bits_tx_out.buffer_size = TX_BUF_SIZE;
2379 +               tx_skb[dev_index][index].desc_in_use = 0;
2380 +               free_tx_buf(dev_index, index);
2381 +               printk("cleanup di %d\n", index);
2382 +               fill_desc = (GMAC_DESCRIPTOR_T*)((fill_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2383 +               index++;
2384 +               if (index > TX_DESC_NUM)
2385 +                       index = 0;
2386 +       }
2387 +       return 1;
2388 +}
2389 +
2390 +size_t get_available_tx_desc(struct net_device* dev, int dev_index)
2391 +{
2392 +       struct gmac_private *tp = dev->priv;
2393 +       unsigned int desc_hdr = tp->tx_desc_hdr[dev_index];
2394 +       unsigned int desc_tail = tp->tx_desc_tail[dev_index];
2395 +       int available_desc_num = (TX_DESC_NUM - desc_hdr + desc_tail) & (TX_DESC_NUM-1);
2396 +       if (!available_desc_num) {
2397 +               if (tx_skb[dev_index][desc_hdr].desc_in_use)
2398 +                       return 0;
2399 +               else
2400 +                       return TX_DESC_NUM;
2401 +       }
2402 +       return available_desc_num;
2403 +}
2404 +
2405 +int check_free_tx_desc(int dev_index, int n, GMAC_DESCRIPTOR_T* desc)
2406 +{
2407 +       int i,index;
2408 +       GMAC_DESCRIPTOR_T* tmp_desc = desc;
2409 +
2410 +       if (n > TX_DESC_NUM)
2411 +               return 0;
2412 +
2413 +       index = ((unsigned int)tmp_desc - tx_desc_start_adr[dev_index])/sizeof(GMAC_DESCRIPTOR_T);
2414 +       for (i=0; i<n; i++)
2415 +       {
2416 +               if (tx_skb[dev_index][index].desc_in_use)
2417 +               {
2418 +                       printk("sw desc %d is in use\n", index);
2419 +                       /* cleanup all the descriptors to check if DMA still running */
2420 +                       return 0;
2421 +               }
2422 +               index++;
2423 +               if (index == TX_DESC_NUM)
2424 +                       index = 0;
2425 +       }
2426 +       return 1;
2427 +}
2428 +
2429 +#define TCPHDRLEN(tcp_hdr)  ((ntohs(*((__u16 *)tcp_hdr + 6)) >> 12) & 0x000F)
2430 +
2431 +inline int fill_in_desc(int dev_index, GMAC_DESCRIPTOR_T *desc, char* data, int len, int total_len, int sof, int freeable, int ownership, struct sk_buff* skb)
2432 +{
2433 +       int index = ((unsigned int)desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2434 +
2435 +       if (desc->frame_ctrl.bits_tx_in.own == CPU)
2436 +       {
2437 +               tx_skb[dev_index][index].freeable = freeable;
2438 +               if ((sof & 0x01) && skb) {
2439 +                       tx_skb[dev_index][index].skb = skb;
2440 +               }
2441 +               else
2442 +                       tx_skb[dev_index][index].skb = 0;
2443 +
2444 +               if (sof != 2)
2445 +                       tx_skb[dev_index][index].desc_in_use = 1;
2446 +               else
2447 +                       tx_skb[dev_index][index].desc_in_use = 0;
2448 +
2449 +               consistent_sync(data, len, PCI_DMA_TODEVICE);
2450 +               desc->buf_adr = (unsigned int)__pa(data);
2451 +               desc->frame_ctrl.bits_tx_out.buffer_size = len;
2452 +               desc->flag_status.bits_tx_flag.frame_count = total_len;
2453 +               desc->next_desc.bits.eofie = 1;
2454 +               desc->next_desc.bits.sof_eof = sof;
2455 +               desc->frame_ctrl.bits_tx_out.vlan_enable = 0;
2456 +               desc->frame_ctrl.bits_tx_out.ip_csum_en = 1;     /* TSS IPv4 IP header checksum enable */
2457 +               desc->frame_ctrl.bits_tx_out.ipv6_tx_en = 1;    /* TSS IPv6 tx enable */
2458 +               desc->frame_ctrl.bits_tx_out.tcp_csum_en = 1;    /* TSS TCP checksum enable */
2459 +               desc->frame_ctrl.bits_tx_out.udp_csum_en = 1;    /* TSS UDP checksum enable */
2460 +        wmb();
2461 +               desc->frame_ctrl.bits_tx_out.own = ownership;
2462 +//             consistent_sync(desc, sizeof(GMAC_DESCRIPTOR_T), PCI_DMA_TODEVICE);
2463 +       }
2464 +       return 0;
2465 +}
2466 +#endif
2467 +
2468 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
2469 +{
2470 +       struct gmac_private     *tp = dev->priv;
2471 +       GMAC_TXDMA_CTRL_T               tx_ctrl,tx_ctrl_mask;
2472 +       GMAC_TXDMA_FIRST_DESC_T txdma_busy;
2473 +       unsigned int            len = skb->len;
2474 +       unsigned int            dev_index;
2475 +       static unsigned int     pcount = 0;
2476 +#ifdef CONFIG_SL2312_MPAGE
2477 +    GMAC_DESCRIPTOR_T *fill_desc;
2478 +       int snd_pages = skb_shinfo(skb)->nr_frags;  /* get number of descriptor */
2479 +       int desc_needed = 1; // for jumbo packet, one descriptor is enough.
2480 +       int header_len = skb->len;
2481 +    struct iphdr       *ip_hdr;
2482 +    struct tcphdr      *tcp_hdr;
2483 +    int             tcp_hdr_len;
2484 +    int             data_len;
2485 +    int             prv_index;
2486 +    long            seq_num;
2487 +    int             first_desc_index;
2488 +    int             ownership, freeable;
2489 +    int             eof;
2490 +       int             i=0;
2491 +#endif
2492 +#ifdef CONFIG_TXINT_DISABLE
2493 +       int                             available_desc_cnt = 0;
2494 +#endif
2495 +
2496 +    dev_index = gmac_select_interface(dev);
2497 +
2498 +#ifdef CONFIG_TXINT_DISABLE
2499 +       available_desc_cnt = get_available_tx_desc(dev, dev_index);
2500 +
2501 +       if (available_desc_cnt < (TX_DESC_NUM >> 2)) {
2502 +               gmac_tx_packet_complete(dev);
2503 +       }
2504 +#endif
2505 +
2506 +#ifdef CONFIG_SL2312_MPAGE
2507 +
2508 +       fill_desc = tp->tx_cur_desc;
2509 +       if(!fill_desc) {
2510 +               printk("cur_desc is NULL!\n");
2511 +               return -1;
2512 +       }
2513 +
2514 +       if (storlink_ctl.recvfile==2)
2515 +       {
2516 +           printk("snd_pages=%d skb->len=%d\n",snd_pages,skb->len);
2517 +       }
2518 +
2519 +       if (snd_pages)
2520 +               desc_needed += snd_pages;   /* decriptors needed for this large packet */
2521 +
2522 +       if (!check_free_tx_desc(dev_index, desc_needed, fill_desc)) {
2523 +               printk("no available desc!\n");
2524 +        gmac_dump_register(dev);
2525 +               printk_all(dev_index, tp);
2526 +               tp->stats.tx_dropped++;
2527 +               if (pcount++ > 10)
2528 +               {
2529 +                   for (;;);
2530 +               }
2531 +               return -1;
2532 +       }
2533 +
2534 +       first_desc_index = ((unsigned int)fill_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2535 +
2536 +       /* check if the tcp packet is in order*/
2537 +       ip_hdr = (struct iphdr*) &(skb->data[14]);
2538 +       tcp_hdr = (struct tcphdr*) &(skb->data[14+ip_hdr->ihl * 4]);
2539 +       tcp_hdr_len = TCPHDRLEN(tcp_hdr) * 4;
2540 +       data_len = skb->len - 14 - ip_hdr->ihl *4 - tcp_hdr_len;
2541 +
2542 +       prv_index = first_desc_index-1;
2543 +       if (prv_index <0)
2544 +           prv_index += TX_DESC_NUM;
2545 +       seq_num = ntohl(tcp_hdr->seq);
2546 +
2547 +       if (snd_pages)
2548 +       {
2549 +               // calculate header length
2550 +               // check fragment total length and header len = skb len - frag len
2551 +               // or parse the header.
2552 +               for (i=0; i<snd_pages; i++) {
2553 +                       skb_frag_t* frag = &skb_shinfo(skb)->frags[i];
2554 +                       header_len -= frag->size;
2555 +               }
2556 +               ownership = CPU;
2557 +               freeable = 0;
2558 +               /* fill header into first descriptor */
2559 +               fill_in_desc(dev_index, fill_desc, skb->data, header_len, len, 2, freeable, ownership, 0);
2560 +               fill_desc = (GMAC_DESCRIPTOR_T*)((fill_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2561 +               tx_skb[dev_index][first_desc_index].end_seq = seq_num + data_len;
2562 +
2563 +               eof = 0;
2564 +               ownership = DMA;
2565 +               for (i=0; i<snd_pages; i++)
2566 +               {
2567 +                       skb_frag_t* frag = &skb_shinfo(skb)->frags[i];
2568 +                       int start_pos = frag->page_offset;
2569 +                       char* data_buf = page_address(frag->page);
2570 +                       int data_size = frag->size;
2571 +                       int cur_index;
2572 +
2573 +                       if (i == snd_pages-1)
2574 +                       {
2575 +                               eof=1;
2576 +                               freeable = 1;
2577 +                       }
2578 +                       fill_in_desc(dev_index, fill_desc, data_buf+(start_pos), data_size,
2579 +                                    len, eof, freeable, ownership, skb);
2580 +                       cur_index = ((unsigned int)fill_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2581 +
2582 +                       fill_desc = (GMAC_DESCRIPTOR_T*)((fill_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2583 +               }
2584 +               /* pass the ownership of the first descriptor to hardware */
2585 +//         disable_irq(gmac_irq[dev_index]);
2586 +               tx_skb[dev_index][first_desc_index].desc_in_use = 1;
2587 +        wmb();
2588 +               tp->tx_cur_desc->frame_ctrl.bits_tx_out.own = DMA;
2589 +//             consistent_sync(tp->tx_cur_desc, sizeof(GMAC_DESCRIPTOR_T), PCI_DMA_TODEVICE);
2590 +               tp->tx_cur_desc = fill_desc;
2591 +               dev->trans_start = jiffies;
2592 +//         enable_irq(gmac_irq[dev_index]);
2593 +       }
2594 +       else if ( tp->tx_cur_desc->frame_ctrl.bits_tx_out.own == CPU )
2595 +       {
2596 +//             tx_skb[dev_index][first_desc_index].end_seq = seq_num + data_len;
2597 +//         disable_irq(gmac_irq[dev_index]);
2598 +               fill_in_desc(dev_index, tp->tx_cur_desc, skb->data, skb->len, skb->len, 3, 1, DMA, skb);
2599 +//         enable_irq(gmac_irq[dev_index]);
2600 +               //consistent_sync(tp->tx_cur_desc, sizeof(GMAC_DESCRIPTOR_T), PCI_DMA_TODEVICE);
2601 +               tp->tx_cur_desc = (GMAC_DESCRIPTOR_T*)((tp->tx_cur_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2602 +               dev->trans_start = jiffies;
2603 +       }
2604 +       else
2605 +       {
2606 +               printk("gmac tx drop!\n");
2607 +               tp->stats.tx_dropped++;
2608 +               return -1;
2609 +       }
2610 +
2611 +#ifdef CONFIG_TXINT_DISABLE
2612 +       tp->tx_desc_hdr[dev_index] = (tp->tx_desc_hdr[dev_index] + desc_needed) & (TX_DESC_NUM-1);
2613 +#endif
2614 +
2615 +#else
2616 +    if ((tp->tx_cur_desc->frame_ctrl.bits_tx_out.own == CPU) && (len < TX_BUF_SIZE))
2617 +       {
2618 +        index = ((unsigned int)tp->tx_cur_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2619 +        tx_skb[dev_index][index] = skb;
2620 +        consistent_sync(skb->data,skb->len,PCI_DMA_TODEVICE);
2621 +        tp->tx_cur_desc->buf_adr = (unsigned int)__pa(skb->data);
2622 +       tp->tx_cur_desc->flag_status.bits_tx_flag.frame_count = len;    /* total frame byte count */
2623 +       tp->tx_cur_desc->next_desc.bits.sof_eof = 0x03;                 /*only one descriptor*/
2624 +               tp->tx_cur_desc->frame_ctrl.bits_tx_out.buffer_size = len;      /* descriptor byte count */
2625 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.vlan_enable = 0;
2626 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.ip_csum_en = 0;     /* TSS IPv4 IP header checksum enable */
2627 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.ipv6_tx_en = 0 ;    /* TSS IPv6 tx enable */
2628 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.tcp_csum_en = 0;    /* TSS TCP checksum enable */
2629 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.udp_csum_en = 0;    /* TSS UDP checksum enable */
2630 +        wmb();
2631 +       tp->tx_cur_desc->frame_ctrl.bits_tx_out.own = DMA;              /* set owner bit */
2632 +       tp->tx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
2633 +       dev->trans_start = jiffies;
2634 +       }
2635 +       else
2636 +       {
2637 +               /* no free tx descriptor */
2638 +               dev_kfree_skb(skb);
2639 +           netif_stop_queue(dev);
2640 +               tp->stats.tx_dropped++;
2641 +               return (-1);
2642 +       }
2643 +#endif
2644 +       /* if TX DMA process is stoped , restart it */
2645 +       txdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_FIRST_DESC);
2646 +       if (txdma_busy.bits.td_busy == 0)
2647 +       {
2648 +               /* restart DMA process */
2649 +               tx_ctrl.bits32 = 0;
2650 +               tx_ctrl.bits.td_start = 1;
2651 +               tx_ctrl.bits.td_continue = 1;
2652 +               tx_ctrl_mask.bits32 = 0;
2653 +               tx_ctrl_mask.bits.td_start = 1;
2654 +               tx_ctrl_mask.bits.td_continue = 1;
2655 +               gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,tx_ctrl.bits32,tx_ctrl_mask.bits32);
2656 +       }
2657 +       return (0);
2658 +}
2659 +
2660 +
2661 +struct net_device_stats * gmac_get_stats(struct net_device *dev)
2662 +{
2663 +    struct gmac_private *tp = dev->priv;
2664 +    unsigned long       flags;
2665 +    unsigned int        pkt_drop;
2666 +    unsigned int        pkt_error;
2667 +    unsigned int        dev_index;
2668 +
2669 +    dev_index = gmac_select_interface(dev);
2670 +
2671 +//     if (storlink_ctl.recvfile==3)
2672 +//     {
2673 +//        printk("GMAC_GLOBAL_BASE_ADDR=%x\n", readl(GMAC_GLOBAL_BASE_ADDR+0x30));
2674 +//        gmac_dump_register(dev);
2675 +//        printk_all(0, dev);
2676 +//    }
2677 +
2678 +    if (netif_running(dev))
2679 +    {
2680 +        /* read H/W counter */
2681 +        spin_lock_irqsave(&tp->lock,flags);
2682 +        pkt_drop = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_DISCARDS);
2683 +        pkt_error = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_ERRORS);
2684 +        tp->stats.rx_dropped = tp->stats.rx_dropped + pkt_drop;
2685 +        tp->stats.rx_errors = tp->stats.rx_errors + pkt_error;
2686 +        spin_unlock_irqrestore(&tp->lock,flags);
2687 +    }
2688 +    return &tp->stats;
2689 +}
2690 +
2691 +static unsigned const ethernet_polynomial = 0x04c11db7U;
2692 +static inline u32 ether_crc (int length, unsigned char *data)
2693 +{
2694 +       int crc = -1;
2695 +       unsigned int i;
2696 +       unsigned int crc_val=0;
2697 +
2698 +       while (--length >= 0) {
2699 +               unsigned char current_octet = *data++;
2700 +               int bit;
2701 +               for (bit = 0; bit < 8; bit++, current_octet >>= 1)
2702 +                       crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
2703 +                            ethernet_polynomial : 0);
2704 +       }
2705 +       crc = ~crc;
2706 +       for (i=0;i<32;i++)
2707 +       {
2708 +               crc_val = crc_val + (((crc << i) & 0x80000000) >> (31-i));
2709 +       }
2710 +       return crc_val;
2711 +}
2712 +
2713 +static void gmac_set_rx_mode(struct net_device *dev)
2714 +{
2715 +    GMAC_RX_FLTR_T      filter;
2716 +       unsigned int        mc_filter[2];       /* Multicast hash filter */
2717 +    int                 bit_nr;
2718 +       unsigned int        i, dev_index;
2719 +
2720 +    dev_index = gmac_select_interface(dev);
2721 +
2722 +//    printk("%s : dev->flags = %x \n",__func__,dev->flags);
2723 +//    dev->flags |= IFF_ALLMULTI;  /* temp */
2724 +    filter.bits32 = 0;
2725 +    filter.bits.error = 0;
2726 +       if (dev->flags & IFF_PROMISC)
2727 +       {
2728 +           filter.bits.error = 1;
2729 +        filter.bits.promiscuous = 1;
2730 +        filter.bits.broadcast = 1;
2731 +        filter.bits.multicast = 1;
2732 +        filter.bits.unicast = 1;
2733 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
2734 +       }
2735 +       else if (dev->flags & IFF_ALLMULTI)
2736 +       {
2737 +        filter.bits.promiscuous = 1;
2738 +        filter.bits.broadcast = 1;
2739 +        filter.bits.multicast = 1;
2740 +        filter.bits.unicast = 1;
2741 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
2742 +       }
2743 +       else
2744 +       {
2745 +               struct dev_mc_list *mclist;
2746 +
2747 +        filter.bits.promiscuous = 1;
2748 +        filter.bits.broadcast = 1;
2749 +        filter.bits.multicast = 1;
2750 +        filter.bits.unicast = 1;
2751 +               mc_filter[1] = mc_filter[0] = 0;
2752 +               for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;i++, mclist = mclist->next)
2753 +               {
2754 +            bit_nr = ether_crc(ETH_ALEN,mclist->dmi_addr) & 0x0000003f;
2755 +            if (bit_nr < 32)
2756 +            {
2757 +                mc_filter[0] = mc_filter[0] | (1<<bit_nr);
2758 +            }
2759 +            else
2760 +            {
2761 +                mc_filter[1] = mc_filter[1] | (1<<(bit_nr-32));
2762 +            }
2763 +               }
2764 +       }
2765 +    filter.bits32 = 0x1f;
2766 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RX_FLTR,filter.bits32,0xffffffff);
2767 +
2768 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_MCAST_FIL0,mc_filter[0],0xffffffff);
2769 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_MCAST_FIL1,mc_filter[1],0xffffffff);
2770 +    return;
2771 +}
2772 +
2773 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
2774 +{
2775 +       struct sockaddr *sock;
2776 +       unsigned int    reg_val;
2777 +       unsigned int    dev_index;
2778 +    unsigned int    i;
2779 +
2780 +    dev_index = gmac_select_interface(dev);
2781 +
2782 +       sock = (struct sockaddr *) addr;
2783 +       for (i = 0; i < 6; i++)
2784 +       {
2785 +               dev->dev_addr[i] = sock->sa_data[i];
2786 +       }
2787 +
2788 +    reg_val = dev->dev_addr[0] + (dev->dev_addr[1]<<8) + (dev->dev_addr[2]<<16) + (dev->dev_addr[3]<<24);
2789 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_STA_ADD0,reg_val,0xffffffff);
2790 +    reg_val = dev->dev_addr[4] + (dev->dev_addr[5]<<8) ;
2791 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_STA_ADD1,reg_val,0x0000ffff);
2792 +    memcpy(&eth0_mac[0],&dev->dev_addr[0],6);
2793 +    printk("Storlink %s address = ",dev->name);
2794 +    printk("%02x",dev->dev_addr[0]);
2795 +    printk("%02x",dev->dev_addr[1]);
2796 +    printk("%02x",dev->dev_addr[2]);
2797 +    printk("%02x",dev->dev_addr[3]);
2798 +    printk("%02x",dev->dev_addr[4]);
2799 +    printk("%02x\n",dev->dev_addr[5]);
2800 +
2801 +    return (0);
2802 +}
2803 +
2804 +static void gmac_tx_timeout(struct net_device *dev)
2805 +{
2806 +       GMAC_TXDMA_CTRL_T               tx_ctrl,tx_ctrl_mask;
2807 +    GMAC_TXDMA_FIRST_DESC_T     txdma_busy;
2808 +    int                                                        dev_index;
2809 +
2810 +    dev_index = gmac_select_interface(dev);
2811 +
2812 +    /* if TX DMA process is stoped , restart it */
2813 +       txdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_FIRST_DESC);
2814 +       if (txdma_busy.bits.td_busy == 0)
2815 +       {
2816 +               /* restart DMA process */
2817 +               tx_ctrl.bits32 = 0;
2818 +               tx_ctrl.bits.td_start = 1;
2819 +               tx_ctrl.bits.td_continue = 1;
2820 +               tx_ctrl_mask.bits32 = 0;
2821 +               tx_ctrl_mask.bits.td_start = 1;
2822 +               tx_ctrl_mask.bits.td_continue = 1;
2823 +               gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,tx_ctrl.bits32,tx_ctrl_mask.bits32);
2824 +       }
2825 +       netif_wake_queue(dev);
2826 +    return;
2827 +}
2828 +
2829 +static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2830 +{
2831 +       int rc = 0;
2832 +    unsigned char *hwa = rq->ifr_ifru.ifru_hwaddr.sa_data;
2833 +
2834 +       if (!netif_running(dev))
2835 +       {
2836 +           printk("Before changing the H/W address,please down the device.\n");
2837 +               return -EINVAL;
2838 +    }
2839 +
2840 +       switch (cmd) {
2841 +       case SIOCETHTOOL:
2842 +        break;
2843 +
2844 +    case SIOCSIFHWADDR:
2845 +        gmac_set_mac_address(dev,hwa);
2846 +        break;
2847 +
2848 +       case SIOCGMIIPHY:       /* Get the address of the PHY in use. */
2849 +       case SIOCDEVPRIVATE:    /* binary compat, remove in 2.5 */
2850 +        break;
2851 +
2852 +       case SIOCGMIIREG:       /* Read the specified MII register. */
2853 +       case SIOCDEVPRIVATE+1:
2854 +               break;
2855 +
2856 +       case SIOCSMIIREG:       /* Write the specified MII register */
2857 +       case SIOCDEVPRIVATE+2:
2858 +               break;
2859 +
2860 +       default:
2861 +               rc = -EOPNOTSUPP;
2862 +               break;
2863 +       }
2864 +
2865 +       return rc;
2866 +}
2867 +
2868 +static void gmac_cleanup_module(void)
2869 +{
2870 +    int i;
2871 +
2872 +    for (i=0;i<GMAC_PHY_IF;i++)
2873 +    {
2874 +        unregister_netdev(gmac_dev[i]);
2875 +    }
2876 +       return ;
2877 +}
2878 +
2879 +static int __init gmac_init_module(void)
2880 +{
2881 +       struct gmac_private *tp;
2882 +       struct net_device *dev[GMAC_PHY_IF];
2883 +       unsigned int i;
2884 +
2885 +#ifdef MODULE
2886 +       printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2887 +#endif
2888 +//     init_waitqueue_entry(&wait, current);
2889 +
2890 +       printk("GMAC Init......\n");
2891 +       for(i = 0; i<GMAC_PHY_IF; i++)
2892 +       {
2893 +               dev[i] = alloc_etherdev(sizeof(struct gmac_private));
2894 +               if (dev[i] == NULL)
2895 +               {
2896 +                       printk (KERN_ERR "Can't allocate ethernet device #%d .\n",i);
2897 +                       return -ENOMEM;
2898 +               }
2899 +        gmac_dev[i] = dev[i];
2900 +
2901 +               SET_MODULE_OWNER(dev[i]);
2902 +
2903 +               tp = dev[i]->priv;
2904 +
2905 +               dev[i]->base_addr = gmac_base_addr[i];
2906 +               dev[i]->irq = gmac_irq[i];
2907 +           dev[i]->open = gmac_open;
2908 +           dev[i]->stop = gmac_close;
2909 +               dev[i]->hard_start_xmit = gmac_start_xmit;
2910 +               dev[i]->get_stats = gmac_get_stats;
2911 +               dev[i]->set_multicast_list = gmac_set_rx_mode;
2912 +               dev[i]->set_mac_address = gmac_set_mac_address;
2913 +               dev[i]->do_ioctl = gmac_netdev_ioctl;
2914 +               dev[i]->tx_timeout = gmac_tx_timeout;
2915 +               dev[i]->watchdog_timeo = TX_TIMEOUT;
2916 +               dev[i]->features |= NETIF_F_SG|NETIF_F_HW_CSUM|NETIF_F_TSO;
2917 +#ifdef CONFIG_SL_NAPI
2918 +        printk("NAPI driver is enabled.\n");
2919 +        if (i==0)
2920 +        {
2921 +               dev[i]->poll = gmac_rx_poll_ga;
2922 +               dev[i]->weight = 64;
2923 +           }
2924 +           else
2925 +           {
2926 +               dev[i]->poll = gmac_rx_poll_gb;
2927 +               dev[i]->weight = 64;
2928 +           }
2929 +#endif
2930 +
2931 +               if (register_netdev(dev[i]))
2932 +               {
2933 +                       gmac_cleanup_module();
2934 +                       return(-1);
2935 +               }
2936 +       }
2937 +
2938 +#ifdef CONFIG_SL3516_ASIC
2939 +{
2940 +    unsigned int    val;
2941 +
2942 +    /* set GMAC global register */
2943 +    val = readl(GMAC_GLOBAL_BASE_ADDR+0x10);
2944 +    val = val | 0x005a0000;
2945 +    writel(val,GMAC_GLOBAL_BASE_ADDR+0x10);
2946 +    writel(0x07f007f0,GMAC_GLOBAL_BASE_ADDR+0x1c);
2947 +    writel(0x77770000,GMAC_GLOBAL_BASE_ADDR+0x20);
2948 +    writel(0x77770000,GMAC_GLOBAL_BASE_ADDR+0x24);
2949 +       val = readl(GMAC_GLOBAL_BASE_ADDR+0x04);
2950 +       if((val&(1<<20))==0){           // GMAC1 enable
2951 +               val = readl(GMAC_GLOBAL_BASE_ADDR+0x30);
2952 +               val = (val & 0xe7ffffff) | 0x08000000;
2953 +               writel(val,GMAC_GLOBAL_BASE_ADDR+0x30);
2954 +       }
2955 +
2956 +}
2957 +#endif
2958 +
2959 +//     printk("%s: dev0=%x  dev1=%x \n",__func__,dev[0],dev[1]);
2960 +//     FLAG_SWITCH = 0 ;
2961 +//     FLAG_SWITCH = SPI_get_identifier();
2962 +//     if(FLAG_SWITCH)
2963 +//     {
2964 +//             printk("Configure ADM699X...\n");
2965 +//             SPI_default();  //Add by jason for ADM699X configuration
2966 +//     }
2967 +       return (0);
2968 +}
2969 +
2970 +
2971 +module_init(gmac_init_module);
2972 +module_exit(gmac_cleanup_module);
2973 +
2974 +static int gmac_phy_thread (void *data)
2975 +{
2976 +       struct net_device   *dev = data;
2977 +       struct gmac_private *tp = dev->priv;
2978 +       unsigned long       timeout;
2979 +
2980 +    daemonize("%s", dev->name);
2981 +       allow_signal(SIGTERM);
2982 +//     reparent_to_init();
2983 +//     spin_lock_irq(&current->sigmask_lock);
2984 +//     sigemptyset(&current->blocked);
2985 +//     recalc_sigpending(current);
2986 +//     spin_unlock_irq(&current->sigmask_lock);
2987 +//     strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
2988 +//     current->comm[sizeof(current->comm) - 1] = '\0';
2989 +
2990 +       while (1)
2991 +       {
2992 +           timeout = next_tick;
2993 +               do
2994 +               {
2995 +                       timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
2996 +               } while (!signal_pending (current) && (timeout > 0));
2997 +
2998 +               if (signal_pending (current))
2999 +               {
3000 +//                     spin_lock_irq(&current->sigmask_lock);
3001 +                       flush_signals(current);
3002 +//                     spin_unlock_irq(&current->sigmask_lock);
3003 +               }
3004 +
3005 +               if (tp->time_to_die)
3006 +                       break;
3007 +
3008 +//        printk("%s : Polling PHY Status...%x\n",__func__,dev);
3009 +               rtnl_lock ();
3010 +        gmac_get_phy_status(dev);
3011 +               rtnl_unlock ();
3012 +       }
3013 +       complete_and_exit (&tp->thr_exited, 0);
3014 +}
3015 +
3016 +static void gmac_set_phy_status(struct net_device *dev)
3017 +{
3018 +    GMAC_STATUS_T   status;
3019 +    unsigned int    reg_val;
3020 +    unsigned int    i = 0;
3021 +    unsigned int    index;
3022 +
3023 +    if (FLAG_SWITCH==1)
3024 +    {
3025 +        return; /* GMAC connects to a switch chip, not PHY */
3026 +    }
3027 +
3028 +    index = gmac_get_dev_index(dev);
3029 +
3030 +    if (index == 0)
3031 +    {
3032 +//     mii_write(phy_addr[index],0x04,0x0461); /* advertisement 10M full duplex, pause capable on */
3033 +//     mii_write(phy_addr[index],0x04,0x0421); /* advertisement 10M half duplex, pause capable on */
3034 +       mii_write(phy_addr[index],0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
3035 +//     mii_write(phy_addr[index],0x04,0x04a1); /* advertisement 100M half duplex, pause capable on */
3036 +#ifdef CONFIG_SL3516_ASIC
3037 +       mii_write(phy_addr[index],0x09,0x0300); /* advertisement 1000M full duplex, pause capable on */
3038 +//     mii_write(phy_addr[index],0x09,0x0000); /* advertisement 1000M full duplex, pause capable on */
3039 +#endif
3040 +    }
3041 +    else
3042 +    {
3043 +//     mii_write(phy_addr[index],0x04,0x0461); /* advertisement 10M full duplex, pause capable on */
3044 +//     mii_write(phy_addr[index],0x04,0x0421); /* advertisement 10M half duplex, pause capable on */
3045 +       mii_write(phy_addr[index],0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
3046 +//     mii_write(phy_addr[index],0x04,0x04a1); /* advertisement 100M half duplex, pause capable on */
3047 +#ifdef CONFIG_SL3516_ASIC
3048 +//     mii_write(phy_addr[index],0x09,0x0000); /* advertisement no 1000M */
3049 +       mii_write(phy_addr[index],0x09,0x0300); /* advertisement 1000M full duplex, pause capable on */
3050 +#endif
3051 +       }
3052 +
3053 +    mii_write(phy_addr[index],0x00,0x1200); /* Enable and Restart Auto-Negotiation */
3054 +    mii_write(phy_addr[index],0x18,0x0041); /* Enable Active led */
3055 +    while (((reg_val=mii_read(phy_addr[index],0x01)) & 0x00000004)!=0x04)
3056 +    {
3057 +        i++;
3058 +        if (i > 30)
3059 +        {
3060 +            break;
3061 +        }
3062 +       msleep(100);
3063 +    }
3064 +    if (i>30)
3065 +    {
3066 +        pre_phy_status[index] = LINK_DOWN;
3067 +               clear_bit(__LINK_STATE_START, &dev->state);
3068 +        netif_stop_queue(dev);
3069 +        storlink_ctl.link = 0;
3070 +        printk("Link Down (%04x) ",reg_val);
3071 +    }
3072 +    else
3073 +    {
3074 +        pre_phy_status[index] = LINK_UP;
3075 +               set_bit(__LINK_STATE_START, &dev->state);
3076 +        netif_wake_queue(dev);
3077 +        storlink_ctl.link = 1;
3078 +        printk("Link Up (%04x) ",reg_val);
3079 +    }
3080 +
3081 +    status.bits32 = 0;
3082 +    reg_val = mii_read(phy_addr[index],10);
3083 +    printk("reg_val0 = %x \n",reg_val);
3084 +    if ((reg_val & 0x0800) == 0x0800)
3085 +    {
3086 +        status.bits.duplex = 1;
3087 +        status.bits.speed = 2;
3088 +        printk(" 1000M/Full \n");
3089 +    }
3090 +    else if ((reg_val & 0x0400) == 0x0400)
3091 +    {
3092 +        status.bits.duplex = 0;
3093 +        status.bits.speed = 2;
3094 +        printk(" 1000M/Half \n");
3095 +    }
3096 +    else
3097 +    {
3098 +        reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5;
3099 +        printk("reg_val1 = %x \n",reg_val);
3100 +        if ((reg_val & 0x08)==0x08) /* 100M full duplex */
3101 +        {
3102 +                status.bits.duplex = 1;
3103 +                status.bits.speed = 1;
3104 +                printk(" 100M/Full \n");
3105 +        }
3106 +        else if ((reg_val & 0x04)==0x04) /* 100M half duplex */
3107 +        {
3108 +                status.bits.duplex = 0;
3109 +                status.bits.speed = 1;
3110 +                printk(" 100M/Half \n");
3111 +        }
3112 +        else if ((reg_val & 0x02)==0x02) /* 10M full duplex */
3113 +        {
3114 +                status.bits.duplex = 1;
3115 +                status.bits.speed = 0;
3116 +                printk(" 10M/Full \n");
3117 +        }
3118 +        else if ((reg_val & 0x01)==0x01) /* 10M half duplex */
3119 +        {
3120 +                status.bits.duplex = 0;
3121 +                status.bits.speed = 0;
3122 +                printk(" 100M/Half \n");
3123 +        }
3124 +    }
3125 +
3126 +    reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5;
3127 +    if ((reg_val & 0x20)==0x20)
3128 +    {
3129 +        flow_control_enable[index] = 1;
3130 +        printk("Flow Control Enable. \n");
3131 +    }
3132 +    else
3133 +    {
3134 +        flow_control_enable[index] = 0;
3135 +        printk("Flow Control Disable. \n");
3136 +    }
3137 +    full_duplex = status.bits.duplex;
3138 +    speed = status.bits.speed;
3139 +}
3140 +
3141 +static void gmac_get_phy_status(struct net_device *dev)
3142 +{
3143 +       GMAC_CONFIG0_T  config0,config0_mask;
3144 +    GMAC_STATUS_T   status;
3145 +    unsigned int    reg_val;
3146 +    unsigned int    index;
3147 +
3148 +    index = gmac_select_interface(dev);
3149 +
3150 +    status.bits32 = 0;
3151 +    status.bits.phy_mode = 1;
3152 +
3153 +#ifdef CONFIG_SL3516_ASIC
3154 +    status.bits.mii_rmii = 2;   /* default value for ASIC version */
3155 +//    status.bits.speed = 1;
3156 +#else
3157 +    if (index==0)
3158 +        status.bits.mii_rmii = 0;
3159 +    else
3160 +        status.bits.mii_rmii = 2;
3161 +#endif
3162 +
3163 +    /* read PHY status register */
3164 +    reg_val = mii_read(phy_addr[index],0x01);
3165 +    if ((reg_val & 0x0024) == 0x0024) /* link is established and auto_negotiate process completed */
3166 +    {
3167 +        /* read PHY Auto-Negotiation Link Partner Ability Register */
3168 +        reg_val = mii_read(phy_addr[index],10);
3169 +        if ((reg_val & 0x0800) == 0x0800)
3170 +        {
3171 +            status.bits.mii_rmii = 3;  /* RGMII 1000Mbps mode */
3172 +            status.bits.duplex = 1;
3173 +            status.bits.speed = 2;
3174 +        }
3175 +        else if ((reg_val & 0x0400) == 0x0400)
3176 +        {
3177 +            status.bits.mii_rmii = 3;  /* RGMII 1000Mbps mode */
3178 +            status.bits.duplex = 0;
3179 +            status.bits.speed = 2;
3180 +        }
3181 +        else
3182 +        {
3183 +            reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5;
3184 +            if ((reg_val & 0x08)==0x08) /* 100M full duplex */
3185 +            {
3186 +                    status.bits.mii_rmii = 2;  /* RGMII 10/100Mbps mode */
3187 +                    status.bits.duplex = 1;
3188 +                    status.bits.speed = 1;
3189 +            }
3190 +            else if ((reg_val & 0x04)==0x04) /* 100M half duplex */
3191 +            {
3192 +                    status.bits.mii_rmii = 2;  /* RGMII 10/100Mbps mode */
3193 +                    status.bits.duplex = 0;
3194 +                    status.bits.speed = 1;
3195 +            }
3196 +            else if ((reg_val & 0x02)==0x02) /* 10M full duplex */
3197 +            {
3198 +                    status.bits.mii_rmii = 2;  /* RGMII 10/100Mbps mode */
3199 +                    status.bits.duplex = 1;
3200 +                    status.bits.speed = 0;
3201 +            }
3202 +            else if ((reg_val & 0x01)==0x01) /* 10M half duplex */
3203 +            {
3204 +                    status.bits.mii_rmii = 2;  /* RGMII 10/100Mbps mode */
3205 +                    status.bits.duplex = 0;
3206 +                    status.bits.speed = 0;
3207 +            }
3208 +        }
3209 +        status.bits.link = LINK_UP; /* link up */
3210 +        netif_wake_queue(dev);
3211 +
3212 +        reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5;
3213 +        if ((reg_val & 0x20)==0x20)
3214 +        {
3215 +            if (flow_control_enable[index] == 0)
3216 +            {
3217 +                config0.bits32 = 0;
3218 +                config0_mask.bits32 = 0;
3219 +                config0.bits.tx_fc_en = 1; /* enable tx flow control */
3220 +                config0.bits.rx_fc_en = 1; /* enable rx flow control */
3221 +                config0_mask.bits.tx_fc_en = 1;
3222 +                config0_mask.bits.rx_fc_en = 1;
3223 +                gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
3224 +//                printk("eth%d Flow Control Enable. \n",index);
3225 +            }
3226 +            flow_control_enable[index] = 1;
3227 +        }
3228 +        else
3229 +        {
3230 +            if (flow_control_enable[index] == 1)
3231 +            {
3232 +                config0.bits32 = 0;
3233 +                config0_mask.bits32 = 0;
3234 +                config0.bits.tx_fc_en = 0; /* disable tx flow control */
3235 +                config0.bits.rx_fc_en = 0; /* disable rx flow control */
3236 +                config0_mask.bits.tx_fc_en = 1;
3237 +                config0_mask.bits.rx_fc_en = 1;
3238 +                gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
3239 +//                printk("eth%d Flow Control Disable. \n",index);
3240 +            }
3241 +            flow_control_enable[index] = 0;
3242 +        }
3243 +
3244 +        if (pre_phy_status[index] == LINK_DOWN)
3245 +        {
3246 +            gmac_enable_tx_rx(dev);
3247 +            pre_phy_status[index] = LINK_UP;
3248 +                       set_bit(__LINK_STATE_START, &dev->state);
3249 +                       storlink_ctl.link = 1;
3250 +//                     printk("eth%d Link Up ...\n",index);
3251 +        }
3252 +    }
3253 +    else
3254 +    {
3255 +        status.bits.link = LINK_DOWN; /* link down */
3256 +        netif_stop_queue(dev);
3257 +        flow_control_enable[index] = 0;
3258 +        storlink_ctl.link = 0;
3259 +        if (pre_phy_status[index] == LINK_UP)
3260 +        {
3261 +            gmac_disable_tx_rx(dev);
3262 +            pre_phy_status[index] = LINK_DOWN;
3263 +                       clear_bit(__LINK_STATE_START, &dev->state);
3264 +//                     printk("eth%d Link Down ...\n",index);
3265 +       }
3266 +
3267 +    }
3268 +
3269 +    reg_val = gmac_read_reg(gmac_base_addr[index] + GMAC_STATUS);
3270 +    if (reg_val != status.bits32)
3271 +    {
3272 +        gmac_write_reg(gmac_base_addr[index] + GMAC_STATUS,status.bits32,0x0000007f);
3273 +    }
3274 +}
3275 +
3276 +/***************************************/
3277 +/* define GPIO module base address     */
3278 +/***************************************/
3279 +#define GPIO_BASE_ADDR  (IO_ADDRESS(SL2312_GPIO_BASE))
3280 +
3281 +/* define GPIO pin for MDC/MDIO */
3282 +
3283 +// for gemini ASIC
3284 +#ifdef CONFIG_SL3516_ASIC
3285 +#define H_MDC_PIN           22
3286 +#define H_MDIO_PIN          21
3287 +#define G_MDC_PIN           22
3288 +#define G_MDIO_PIN          21
3289 +#else
3290 +#define H_MDC_PIN           3
3291 +#define H_MDIO_PIN          2
3292 +#define G_MDC_PIN           0
3293 +#define G_MDIO_PIN          1
3294 +#endif
3295 +
3296 +//#define GPIO_MDC             0x80000000
3297 +//#define GPIO_MDIO            0x00400000
3298 +
3299 +static unsigned int GPIO_MDC = 0;
3300 +static unsigned int GPIO_MDIO = 0;
3301 +static unsigned int GPIO_MDC_PIN = 0;
3302 +static unsigned int GPIO_MDIO_PIN = 0;
3303 +
3304 +// For PHY test definition!!
3305 +#define LPC_EECK               0x02
3306 +#define LPC_EDIO               0x04
3307 +#define LPC_GPIO_SET           3
3308 +#define LPC_BASE_ADDR          IO_ADDRESS(IT8712_IO_BASE)
3309 +#define inb_gpio(x)            inb(LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
3310 +#define outb_gpio(x, y)                outb(y, LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
3311 +
3312 +enum GPIO_REG
3313 +{
3314 +    GPIO_DATA_OUT   = 0x00,
3315 +    GPIO_DATA_IN    = 0x04,
3316 +    GPIO_PIN_DIR    = 0x08,
3317 +    GPIO_BY_PASS    = 0x0c,
3318 +    GPIO_DATA_SET   = 0x10,
3319 +    GPIO_DATA_CLEAR = 0x14,
3320 +};
3321 +/***********************/
3322 +/*    MDC : GPIO[31]   */
3323 +/*    MDIO: GPIO[22]   */
3324 +/***********************/
3325 +
3326 +/***************************************************
3327 +* All the commands should have the frame structure:
3328 +*<PRE><ST><OP><PHYAD><REGAD><TA><DATA><IDLE>
3329 +****************************************************/
3330 +
3331 +/*****************************************************************
3332 +* Inject a bit to NWay register through CSR9_MDC,MDIO
3333 +*******************************************************************/
3334 +void mii_serial_write(char bit_MDO) // write data into mii PHY
3335 +{
3336 +#if 0 //def CONFIG_SL2312_LPC_IT8712
3337 +       unsigned char iomode,status;
3338 +
3339 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3340 +       iomode |= (LPC_EECK|LPC_EDIO) ;                         // Set EECK,EDIO,EECS output
3341 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
3342 +
3343 +       if(bit_MDO)
3344 +       {
3345 +               status = inb_gpio( LPC_GPIO_SET);
3346 +               status |= LPC_EDIO ;            //EDIO high
3347 +               outb_gpio(LPC_GPIO_SET, status);
3348 +       }
3349 +       else
3350 +       {
3351 +               status = inb_gpio( LPC_GPIO_SET);
3352 +               status &= ~(LPC_EDIO) ;         //EDIO low
3353 +               outb_gpio(LPC_GPIO_SET, status);
3354 +       }
3355 +
3356 +       status |= LPC_EECK ;            //EECK high
3357 +       outb_gpio(LPC_GPIO_SET, status);
3358 +
3359 +       status &= ~(LPC_EECK) ;         //EECK low
3360 +       outb_gpio(LPC_GPIO_SET, status);
3361 +
3362 +#else
3363 +    unsigned int addr;
3364 +    unsigned int value;
3365 +
3366 +    addr = GPIO_BASE_ADDR + GPIO_PIN_DIR;
3367 +    value = readl(addr) | GPIO_MDC | GPIO_MDIO; /* set MDC/MDIO Pin to output */
3368 +    writel(value,addr);
3369 +    if(bit_MDO)
3370 +    {
3371 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3372 +        writel(GPIO_MDIO,addr); /* set MDIO to 1 */
3373 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3374 +        writel(GPIO_MDC,addr); /* set MDC to 1 */
3375 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3376 +        writel(GPIO_MDC,addr); /* set MDC to 0 */
3377 +    }
3378 +    else
3379 +    {
3380 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3381 +        writel(GPIO_MDIO,addr); /* set MDIO to 0 */
3382 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3383 +        writel(GPIO_MDC,addr); /* set MDC to 1 */
3384 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3385 +        writel(GPIO_MDC,addr); /* set MDC to 0 */
3386 +    }
3387 +
3388 +#endif
3389 +}
3390 +
3391 +/**********************************************************************
3392 +* read a bit from NWay register through CSR9_MDC,MDIO
3393 +***********************************************************************/
3394 +unsigned int mii_serial_read(void) // read data from mii PHY
3395 +{
3396 +#if 0 //def CONFIG_SL2312_LPC_IT8712
3397 +       unsigned char iomode,status;
3398 +       unsigned int value ;
3399 +
3400 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3401 +       iomode &= ~(LPC_EDIO) ;         // Set EDIO input
3402 +       iomode |= (LPC_EECK) ;          // Set EECK,EECS output
3403 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
3404 +
3405 +       status = inb_gpio( LPC_GPIO_SET);
3406 +       status |= LPC_EECK ;            //EECK high
3407 +       outb_gpio(LPC_GPIO_SET, status);
3408 +
3409 +       status &= ~(LPC_EECK) ;         //EECK low
3410 +       outb_gpio(LPC_GPIO_SET, status);
3411 +
3412 +       value = inb_gpio( LPC_GPIO_SET);
3413 +
3414 +       value = value>>2 ;
3415 +       value &= 0x01;
3416 +
3417 +       return value ;
3418 +
3419 +#else
3420 +    unsigned int *addr;
3421 +    unsigned int value;
3422 +
3423 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_PIN_DIR);
3424 +    value = readl(addr) & ~GPIO_MDIO; //0xffbfffff;   /* set MDC to output and MDIO to input */
3425 +    writel(value,addr);
3426 +
3427 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_SET);
3428 +    writel(GPIO_MDC,addr); /* set MDC to 1 */
3429 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3430 +    writel(GPIO_MDC,addr); /* set MDC to 0 */
3431 +
3432 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_IN);
3433 +    value = readl(addr);
3434 +    value = (value & (1<<GPIO_MDIO_PIN)) >> GPIO_MDIO_PIN;
3435 +    return(value);
3436 +
3437 +#endif
3438 +}
3439 +
3440 +/***************************************
3441 +* preamble + ST
3442 +***************************************/
3443 +void mii_pre_st(void)
3444 +{
3445 +    unsigned char i;
3446 +
3447 +    for(i=0;i<32;i++) // PREAMBLE
3448 +        mii_serial_write(1);
3449 +    mii_serial_write(0); // ST
3450 +    mii_serial_write(1);
3451 +}
3452 +
3453 +
3454 +/******************************************
3455 +* Read MII register
3456 +* phyad -> physical address
3457 +* regad -> register address
3458 +***************************************** */
3459 +unsigned int mii_read(unsigned char phyad,unsigned char regad)
3460 +{
3461 +    unsigned int i,value;
3462 +    unsigned int bit;
3463 +
3464 +    if (phyad == GPHY_ADDR)
3465 +    {
3466 +        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
3467 +        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
3468 +    }
3469 +    else
3470 +    {
3471 +        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
3472 +        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
3473 +    }
3474 +    GPIO_MDC = (1<<GPIO_MDC_PIN);
3475 +    GPIO_MDIO = (1<<GPIO_MDIO_PIN);
3476 +
3477 +    mii_pre_st(); // PRE+ST
3478 +    mii_serial_write(1); // OP
3479 +    mii_serial_write(0);
3480 +
3481 +    for (i=0;i<5;i++) { // PHYAD
3482 +        bit= ((phyad>>(4-i)) & 0x01) ? 1 :0 ;
3483 +        mii_serial_write(bit);
3484 +    }
3485 +
3486 +    for (i=0;i<5;i++) { // REGAD
3487 +        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
3488 +        mii_serial_write(bit);
3489 +    }
3490 +
3491 +    mii_serial_read(); // TA_Z
3492 +//    if((bit=mii_serial_read()) !=0 ) // TA_0
3493 +//    {
3494 +//        return(0);
3495 +//    }
3496 +    value=0;
3497 +    for (i=0;i<16;i++) { // READ DATA
3498 +        bit=mii_serial_read();
3499 +        value += (bit<<(15-i)) ;
3500 +    }
3501 +
3502 +    mii_serial_write(0); // dumy clock
3503 +    mii_serial_write(0); // dumy clock
3504 +//printk("%s: phy_addr=%x reg_addr=%x value=%x \n",__func__,phyad,regad,value);
3505 +    return(value);
3506 +}
3507 +
3508 +/******************************************
3509 +* Write MII register
3510 +* phyad -> physical address
3511 +* regad -> register address
3512 +* value -> value to be write
3513 +***************************************** */
3514 +void mii_write(unsigned char phyad,unsigned char regad,unsigned int value)
3515 +{
3516 +    unsigned int i;
3517 +    char bit;
3518 +
3519 +printk("%s: phy_addr=%x reg_addr=%x value=%x \n",__func__,phyad,regad,value);
3520 +    if (phyad == GPHY_ADDR)
3521 +    {
3522 +        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
3523 +        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
3524 +    }
3525 +    else
3526 +    {
3527 +        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
3528 +        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
3529 +    }
3530 +    GPIO_MDC = (1<<GPIO_MDC_PIN);
3531 +    GPIO_MDIO = (1<<GPIO_MDIO_PIN);
3532 +
3533 +    mii_pre_st(); // PRE+ST
3534 +    mii_serial_write(0); // OP
3535 +    mii_serial_write(1);
3536 +    for (i=0;i<5;i++) { // PHYAD
3537 +        bit= ((phyad>>(4-i)) & 0x01) ? 1 :0 ;
3538 +        mii_serial_write(bit);
3539 +    }
3540 +
3541 +    for (i=0;i<5;i++) { // REGAD
3542 +        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
3543 +        mii_serial_write(bit);
3544 +    }
3545 +    mii_serial_write(1); // TA_1
3546 +    mii_serial_write(0); // TA_0
3547 +
3548 +    for (i=0;i<16;i++) { // OUT DATA
3549 +        bit= ((value>>(15-i)) & 0x01) ? 1 : 0 ;
3550 +        mii_serial_write(bit);
3551 +    }
3552 +    mii_serial_write(0); // dumy clock
3553 +    mii_serial_write(0); // dumy clock
3554 +}
3555 +
3556 +
3557 +
3558 +
3559 +
3560 +
3561 +
3562 +
3563 +
3564 +/*                             NOTES
3565 + *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
3566 + *
3567 + *               Start  OP         *
3568 + *     Function   Bit  Code  Address**  Data     Description
3569 + *     -------------------------------------------------------------------
3570 + *     READ        1    10   A7 - A0             Reads data stored in memory,
3571 + *                                               starting at specified address
3572 + *     EWEN        1    00   11XXXXXX            Write enable must precede
3573 + *                                               all programming modes
3574 + *     ERASE       1    11   A7 - A0             Erase register A7A6A5A4A3A2A1A0
3575 + *     WRITE       1    01   A7 - A0   D15 - D0  Writes register
3576 + *     ERAL        1    00   10XXXXXX            Erase all registers
3577 + *     WRAL        1    00   01XXXXXX  D15 - D0  Writes to all registers
3578 + *     EWDS        1    00   00XXXXXX            Disables all programming
3579 + *                                               instructions
3580 + *    *Note: A value of X for address is a don't care condition.
3581 + *    **Note: There are 8 address bits for the 93C56/66 chips unlike
3582 + *           the 93C46/26/06 chips which have 6 address bits.
3583 + *
3584 + *   The 93Cx6 has a four wire interface: clock, chip select, data in, and
3585 + *   data out.While the ADM6996 uning three interface: clock, chip select,and data line.
3586 + *   The input and output are the same pin. ADM6996 can only recognize the write cmd.
3587 + *   In order to perform above functions, you need
3588 + *   1. to enable the chip select .
3589 + *   2. send one clock of dummy clock
3590 + *   3. send start bit and opcode
3591 + *   4. send 8 bits address and 16 bits data
3592 + *   5. to disable the chip select.
3593 + *                                                     Jason Lee 2003/07/30
3594 + */
3595 +
3596 +/***************************************/
3597 +/* define GPIO module base address     */
3598 +/***************************************/
3599 +#define GPIO_EECS           0x00400000         /*   EECS: GPIO[22]   */
3600 +//#define GPIO_MOSI         0x20000000         /*   EEDO: GPIO[29]   send to 6996*/
3601 +#define GPIO_MISO           0x40000000         /*   EEDI: GPIO[30]   receive from 6996*/
3602 +#define GPIO_EECK           0x80000000         /*   EECK: GPIO[31]   */
3603 +
3604 +#define ADM_EECS               0x01
3605 +#define ADM_EECK               0x02
3606 +#define ADM_EDIO               0x04
3607 +/*************************************************************
3608 +* SPI protocol for ADM6996 control
3609 +**************************************************************/
3610 +#define SPI_OP_LEN          0x03               // the length of start bit and opcode
3611 +#define SPI_OPWRITE         0X05               // write
3612 +#define SPI_OPREAD          0X06               // read
3613 +#define SPI_OPERASE         0X07               // erase
3614 +#define SPI_OPWTEN          0X04               // write enable
3615 +#define SPI_OPWTDIS         0X04               // write disable
3616 +#define SPI_OPERSALL        0X04               // erase all
3617 +#define SPI_OPWTALL         0X04               // write all
3618 +
3619 +#define SPI_ADD_LEN         8                  // bits of Address
3620 +#define SPI_DAT_LEN         16                 // bits of Data
3621 +#define ADM6996_PORT_NO             6                  // the port number of ADM6996
3622 +#define ADM6999_PORT_NO             9                  // the port number of ADM6999
3623 +#ifdef CONFIG_ADM_6996
3624 +       #define ADM699X_PORT_NO         ADM6996_PORT_NO
3625 +#endif
3626 +#ifdef CONFIG_ADM_6999
3627 +       #define ADM699X_PORT_NO         ADM6999_PORT_NO
3628 +#endif
3629 +#define LPC_GPIO_SET           3
3630 +#define LPC_BASE_ADDR                  IO_ADDRESS(IT8712_IO_BASE)
3631 +
3632 +extern int it8712_exist;
3633 +
3634 +#define inb_gpio(x)                    inb(LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
3635 +#define outb_gpio(x, y)                outb(y, LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
3636 +
3637 +/****************************************/
3638 +/*     Function Declare                */
3639 +/****************************************/
3640 +/*
3641 +void SPI_write(unsigned char addr,unsigned int value);
3642 +unsigned int SPI_read(unsigned char table,unsigned char addr);
3643 +void SPI_write_bit(char bit_EEDO);
3644 +unsigned int SPI_read_bit(void);
3645 +void SPI_default(void);
3646 +void SPI_reset(unsigned char rstype,unsigned char port_cnt);
3647 +void SPI_pre_st(void);
3648 +void SPI_CS_enable(unsigned char enable);
3649 +void SPI_Set_VLAN(unsigned char LAN,unsigned int port_mask);
3650 +void SPI_Set_tag(unsigned int port,unsigned tag);
3651 +void SPI_Set_PVID(unsigned int PVID,unsigned int port_mask);
3652 +void SPI_mac_lock(unsigned int port, unsigned char lock);
3653 +void SPI_get_port_state(unsigned int port);
3654 +void SPI_port_enable(unsigned int port,unsigned char enable);
3655 +
3656 +void SPI_get_status(unsigned int port);
3657 +*/
3658 +
3659 +struct PORT_CONFIG
3660 +{
3661 +       unsigned char auto_negotiation; // 0:Disable    1:Enable
3662 +       unsigned char speed;            // 0:10M        1:100M
3663 +       unsigned char duplex;           // 0:Half       1:Full duplex
3664 +       unsigned char Tag;              // 0:Untag      1:Tag
3665 +       unsigned char port_disable;     // 0:port enable        1:disable
3666 +       unsigned char pvid;             // port VLAN ID 0001
3667 +       unsigned char mdix;             // Crossover judgement. 0:Disable 1:Enable
3668 +       unsigned char mac_lock;         // MAC address Lock 0:Disable 1:Enable
3669 +};
3670 +
3671 +struct PORT_STATUS
3672 +{
3673 +       unsigned char link;             // 0:not link   1:link established
3674 +       unsigned char speed;            // 0:10M        1:100M
3675 +       unsigned char duplex;           // 0:Half       1:Full duplex
3676 +       unsigned char flow_ctl;         // 0:flow control disable 1:enable
3677 +       unsigned char mac_lock;         // MAC address Lock 0:Disable 1:Enable
3678 +       unsigned char port_disable;     // 0:port enable        1:disable
3679 +
3680 +       // Serial Management
3681 +       unsigned long rx_pac_count;             //receive packet count
3682 +       unsigned long rx_pac_byte;              //receive packet byte count
3683 +       unsigned long tx_pac_count;             //transmit packet count
3684 +       unsigned long tx_pac_byte;              //transmit packet byte count
3685 +       unsigned long collision_count;          //error count
3686 +       unsigned long error_count ;
3687 +
3688 +       unsigned long rx_pac_count_overflow;            //overflow flag
3689 +       unsigned long rx_pac_byte_overflow;
3690 +       unsigned long tx_pac_count_overflow;
3691 +       unsigned long tx_pac_byte_overflow;
3692 +       unsigned long collision_count_overflow;
3693 +       unsigned long error_count_overflow;
3694 +};
3695 +
3696 +struct PORT_CONFIG port_config[ADM699X_PORT_NO];       // 0~3:LAN , 4:WAN , 5:MII
3697 +static struct PORT_STATUS port_state[ADM699X_PORT_NO];
3698 +
3699 +/******************************************
3700 +* SPI_write
3701 +* addr -> Write Address
3702 +* value -> value to be write
3703 +***************************************** */
3704 +void SPI_write(unsigned char addr,unsigned int value)
3705 +{
3706 +       int     i;
3707 +       char    bit;
3708 +#ifdef CONFIG_IT8712_GPIO
3709 +       char    status;
3710 +#else
3711 +    int     ad1;
3712 +#endif
3713 +
3714 +#ifdef CONFIG_IT8712_GPIO
3715 +       status = inb_gpio(LPC_GPIO_SET);
3716 +       status &= ~(ADM_EDIO) ;         //EDIO low
3717 +       outb_gpio(LPC_GPIO_SET, status);
3718 +#else
3719 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3720 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
3721 +#endif
3722 +       SPI_CS_enable(1);
3723 +
3724 +       SPI_write_bit(0);       //dummy clock
3725 +
3726 +       //send write command (0x05)
3727 +       for(i=SPI_OP_LEN-1;i>=0;i--)
3728 +       {
3729 +               bit = (SPI_OPWRITE>>i)& 0x01;
3730 +               SPI_write_bit(bit);
3731 +       }
3732 +       // send 8 bits address (MSB first, LSB last)
3733 +       for(i=SPI_ADD_LEN-1;i>=0;i--)
3734 +       {
3735 +               bit = (addr>>i)& 0x01;
3736 +               SPI_write_bit(bit);
3737 +       }
3738 +       // send 16 bits data (MSB first, LSB last)
3739 +       for(i=SPI_DAT_LEN-1;i>=0;i--)
3740 +       {
3741 +               bit = (value>>i)& 0x01;
3742 +               SPI_write_bit(bit);
3743 +       }
3744 +
3745 +       SPI_CS_enable(0);       // CS low
3746 +
3747 +       for(i=0;i<0xFFF;i++) ;
3748 +#ifdef CONFIG_IT8712_GPIO
3749 +       status = inb_gpio(LPC_GPIO_SET);
3750 +       status &= ~(ADM_EDIO) ;         //EDIO low
3751 +       outb_gpio(LPC_GPIO_SET, status);
3752 +#else
3753 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3754 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
3755 +#endif
3756 +}
3757 +
3758 +
3759 +/************************************
3760 +* SPI_write_bit
3761 +* bit_EEDO -> 1 or 0 to be written
3762 +************************************/
3763 +void SPI_write_bit(char bit_EEDO)
3764 +{
3765 +#ifdef CONFIG_IT8712_GPIO
3766 +       unsigned char iomode,status;
3767 +
3768 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3769 +       iomode |= (ADM_EECK|ADM_EDIO|ADM_EECS) ;                                // Set EECK,EDIO,EECS output
3770 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
3771 +
3772 +       if(bit_EEDO)
3773 +       {
3774 +               status = inb_gpio( LPC_GPIO_SET);
3775 +               status |= ADM_EDIO ;            //EDIO high
3776 +               outb_gpio(LPC_GPIO_SET, status);
3777 +       }
3778 +       else
3779 +       {
3780 +               status = inb_gpio( LPC_GPIO_SET);
3781 +               status &= ~(ADM_EDIO) ;         //EDIO low
3782 +               outb_gpio(LPC_GPIO_SET, status);
3783 +       }
3784 +
3785 +       status |= ADM_EECK ;            //EECK high
3786 +       outb_gpio(LPC_GPIO_SET, status);
3787 +
3788 +       status &= ~(ADM_EECK) ;         //EECK low
3789 +       outb_gpio(LPC_GPIO_SET, status);
3790 +
3791 +#else
3792 +       unsigned int addr;
3793 +       unsigned int value;
3794 +
3795 +       addr = (GPIO_BASE_ADDR + GPIO_PIN_DIR);
3796 +       value = readl(addr) |GPIO_EECK |GPIO_MISO ;   /* set EECK/MISO Pin to output */
3797 +       writel(value,addr);
3798 +       if(bit_EEDO)
3799 +       {
3800 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3801 +               writel(GPIO_MISO,addr); /* set MISO to 1 */
3802 +               writel(GPIO_EECK,addr); /* set EECK to 1 */
3803 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3804 +               writel(GPIO_EECK,addr); /* set EECK to 0 */
3805 +       }
3806 +       else
3807 +       {
3808 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3809 +               writel(GPIO_MISO,addr); /* set MISO to 0 */
3810 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3811 +               writel(GPIO_EECK,addr); /* set EECK to 1 */
3812 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3813 +               writel(GPIO_EECK,addr); /* set EECK to 0 */
3814 +       }
3815 +
3816 +       return ;
3817 +#endif
3818 +}
3819 +
3820 +/**********************************************************************
3821 +* read a bit from ADM6996 register
3822 +***********************************************************************/
3823 +unsigned int SPI_read_bit(void) // read data from
3824 +{
3825 +#ifdef CONFIG_IT8712_GPIO
3826 +       unsigned char iomode,status;
3827 +       unsigned int value ;
3828 +
3829 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3830 +       iomode &= ~(ADM_EDIO) ;         // Set EDIO input
3831 +       iomode |= (ADM_EECS|ADM_EECK) ;         // Set EECK,EECS output
3832 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
3833 +
3834 +       status = inb_gpio( LPC_GPIO_SET);
3835 +       status |= ADM_EECK ;            //EECK high
3836 +       outb_gpio(LPC_GPIO_SET, status);
3837 +
3838 +       status &= ~(ADM_EECK) ;         //EECK low
3839 +       outb_gpio(LPC_GPIO_SET, status);
3840 +
3841 +       value = inb_gpio( LPC_GPIO_SET);
3842 +
3843 +       value = value>>2 ;
3844 +       value &= 0x01;
3845 +
3846 +       return value ;
3847 +#else
3848 +       unsigned int addr;
3849 +       unsigned int value;
3850 +
3851 +       addr = (GPIO_BASE_ADDR + GPIO_PIN_DIR);
3852 +       value = readl(addr) & (~GPIO_MISO);   // set EECK to output and MISO to input
3853 +       writel(value,addr);
3854 +
3855 +       addr =(GPIO_BASE_ADDR + GPIO_DATA_SET);
3856 +       writel(GPIO_EECK,addr); // set EECK to 1
3857 +       addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3858 +       writel(GPIO_EECK,addr); // set EECK to 0
3859 +
3860 +       addr = (GPIO_BASE_ADDR + GPIO_DATA_IN);
3861 +       value = readl(addr) ;
3862 +       value = value >> 30;
3863 +       return value ;
3864 +#endif
3865 +}
3866 +
3867 +/******************************************
3868 +* SPI_default
3869 +* EEPROM content default value
3870 +*******************************************/
3871 +void SPI_default(void)
3872 +{
3873 +       int i;
3874 +#ifdef CONFIG_ADM_6999
3875 +       SPI_write(0x11,0xFF30);
3876 +       for(i=1;i<8;i++)
3877 +               SPI_write(i,0x840F);
3878 +
3879 +       SPI_write(0x08,0x880F);                 //port 8 Untag, PVID=2
3880 +       SPI_write(0x09,0x881D);                 //port 9 Tag, PVID=2 ,10M
3881 +       SPI_write(0x14,0x017F);                 //Group 0~6,8 as VLAN 1
3882 +       SPI_write(0x15,0x0180);                 //Group 7,8 as VLAN 2
3883 +#endif
3884 +
3885 +#ifdef CONFIG_ADM_6996
3886 +       SPI_write(0x11,0xFF30);
3887 +       SPI_write(0x01,0x840F);                 //port 0~3 Untag ,PVID=1 ,100M ,duplex
3888 +       SPI_write(0x03,0x840F);
3889 +       SPI_write(0x05,0x840F);
3890 +       SPI_write(0x07,0x840F);
3891 +       SPI_write(0x08,0x880F);                 //port 4 Untag, PVID=2
3892 +       SPI_write(0x09,0x881D);                 //port 5 Tag, PVID=2 ,10M
3893 +       SPI_write(0x14,0x0155);                 //Group 0~3,5 as VLAN 1
3894 +       SPI_write(0x15,0x0180);                 //Group 4,5 as VLAN 2
3895 +
3896 +#endif
3897 +
3898 +       for(i=0x16;i<=0x22;i++)
3899 +               SPI_write((unsigned char)i,0x0000);             // clean VLAN¡@map 3~15
3900 +
3901 +       for (i=0;i<NUM_VLAN_IF;i++)                             // Set VLAN ID map 1,2
3902 +               SPI_Set_PVID( VLAN_conf[i].vid,  VLAN_conf[i].portmap);
3903 +
3904 +       for(i=0;i<ADM699X_PORT_NO;i++)                          // reset count
3905 +               SPI_reset(0,i);
3906 +}
3907 +
3908 +/*************************************************
3909 +* SPI_reset
3910 +* rstype -> reset type
3911 +*          0:reset all count for 'port_cnt' port
3912 +*          1:reset specified count 'port_cnt'
3913 +* port_cnt   ->  port number or counter index
3914 +***************************************************/
3915 +void SPI_reset(unsigned char rstype,unsigned char port_cnt)
3916 +{
3917 +
3918 +       int i;
3919 +#ifdef CONFIG_IT8712_GPIO
3920 +    char status;
3921 +#else
3922 +       int ad1;
3923 +#endif
3924 +       char bit;
3925 +
3926 +#ifdef CONFIG_IT8712_GPIO
3927 +       status = inb_gpio(LPC_GPIO_SET);
3928 +       status &= ~(ADM_EDIO) ;         //EDIO low
3929 +       outb_gpio(LPC_GPIO_SET, status);
3930 +#else
3931 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3932 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
3933 +#endif
3934 +
3935 +       SPI_CS_enable(0);       // CS low
3936 +
3937 +       SPI_pre_st(); // PRE+ST
3938 +       SPI_write_bit(0); // OP
3939 +       SPI_write_bit(1);
3940 +
3941 +       SPI_write_bit(1);               // Table select, must be 1 -> reset Counter
3942 +
3943 +       SPI_write_bit(0);               // Device Address
3944 +       SPI_write_bit(0);
3945 +
3946 +       rstype &= 0x01;
3947 +       SPI_write_bit(rstype);          // Reset type 0:clear dedicate port's all counters 1:clear dedicate counter
3948 +
3949 +       for (i=5;i>=0;i--)              // port or cnt index
3950 +       {
3951 +               bit = port_cnt >> i ;
3952 +               bit &= 0x01 ;
3953 +               SPI_write_bit(bit);
3954 +       }
3955 +
3956 +       SPI_write_bit(0);               // dumy clock
3957 +       SPI_write_bit(0);               // dumy clock
3958 +
3959 +#ifdef CONFIG_IT8712_GPIO
3960 +       status = inb_gpio(LPC_GPIO_SET);
3961 +       status &= ~(ADM_EDIO) ;         //EDIO low
3962 +       outb_gpio(LPC_GPIO_SET, status);
3963 +#else
3964 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3965 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
3966 +#endif
3967 +}
3968 +
3969 +/*****************************************************
3970 +* SPI_pre_st
3971 +* preambler: 32 bits '1'   start bit: '01'
3972 +*****************************************************/
3973 +void SPI_pre_st(void)
3974 +{
3975 +       int i;
3976 +
3977 +       for(i=0;i<32;i++) // PREAMBLE
3978 +               SPI_write_bit(1);
3979 +       SPI_write_bit(0); // ST
3980 +       SPI_write_bit(1);
3981 +}
3982 +
3983 +
3984 +/***********************************************************
3985 +* SPI_CS_enable
3986 +* before access ,you have to enable Chip Select. (pull high)
3987 +* When fisish, you should pull low !!
3988 +*************************************************************/
3989 +void SPI_CS_enable(unsigned char enable)
3990 +{
3991 +#ifdef CONFIG_IT8712_GPIO
3992 +
3993 +       unsigned char iomode,status;
3994 +
3995 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3996 +       iomode |= (ADM_EECK|ADM_EDIO|ADM_EECS) ;                                // Set EECK,EDIO,EECS output
3997 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
3998 +
3999 +
4000 +       status = inb_gpio( LPC_GPIO_SET);
4001 +       if(enable)
4002 +               status |= ADM_EECS ;            //EECS high
4003 +       else
4004 +               status &= ~(ADM_EECS) ; //EECS low
4005 +
4006 +       outb_gpio(LPC_GPIO_SET, status);
4007 +
4008 +
4009 +       status |= ADM_EECK ;            //EECK high
4010 +       outb_gpio(LPC_GPIO_SET, status);
4011 +
4012 +       status &= ~(ADM_EECK) ;         //EECK low
4013 +       outb_gpio(LPC_GPIO_SET, status);
4014 +
4015 +#else
4016 +       unsigned int addr,value;
4017 +
4018 +       addr = (GPIO_BASE_ADDR + GPIO_PIN_DIR);
4019 +       value = readl(addr) |GPIO_EECS |GPIO_EECK;   /* set EECS/EECK Pin to output */
4020 +       writel(value,addr);
4021 +
4022 +       if(enable)
4023 +       {
4024 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
4025 +               writel(GPIO_EECS,addr); /* set EECS to 1 */
4026 +
4027 +       }
4028 +       else
4029 +       {
4030 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
4031 +               writel(GPIO_EECS,addr); /* set EECS to 0 */
4032 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
4033 +               writel(GPIO_EECK,addr); /* set EECK to 1 */     // at least one clock after CS low
4034 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
4035 +               writel(GPIO_EECK,addr); /* set EECK to 0 */
4036 +       }
4037 +#endif
4038 +}
4039 +
4040 +/*********************************************************
4041 +* SPI_Set_VLAN: group ports as VLAN
4042 +* LAN  -> VLAN number : 0~16
4043 +* port_mask -> ports which would group as LAN
4044 +*             ex. 0x03 = 0000 0011
4045 +*                      port 0 and port 1
4046 +*********************************************************/
4047 +void SPI_Set_VLAN(unsigned char LAN,unsigned int port_mask)
4048 +{
4049 +       unsigned int i,value=0;
4050 +       unsigned reg_add = 0x13 + LAN ;
4051 +
4052 +       for(i=0;i<ADM6996_PORT_NO;i++)
4053 +       {       if(port_mask&0x01)
4054 +               {
4055 +                       switch(i)
4056 +                       {
4057 +                               case 0: value|=0x0001;  break;  //port0:bit[0]
4058 +                               case 1: value|=0x0004;  break;  //port1:bit[2]
4059 +                               case 2: value|=0x0010;  break;  //port2:bit[4]
4060 +                               case 3: value|=0x0040;  break;  //port3:bit[6]
4061 +                               case 4: value|=0x0080;  break;  //port4:bit[7]
4062 +                               case 5: value|=0x0100;  break;  //port5:bit[8]
4063 +                       }
4064 +               }
4065 +               port_mask >>= 1;
4066 +       }
4067 +
4068 +       SPI_write(reg_add,value);
4069 +}
4070 +
4071 +
4072 +/*******************************************
4073 +* SPI_Set_tag
4074 +* port -> port number to set tag or untag
4075 +* tag  -> 0/set untag,  1/set tag
4076 +* In general, tag is for MII port. LAN and
4077 +* WAN port is configed as untag!!
4078 +********************************************/
4079 +void SPI_Set_tag(unsigned int port,unsigned tag)
4080 +{
4081 +       unsigned int regadd,value;
4082 +
4083 +       // mapping port's register !! (0,1,2,3,4,5) ==> (1,3,5,7,8,9)
4084 +       if(port<=3)
4085 +               regadd=2*port+1;
4086 +       else if(port==4) regadd = 8 ;
4087 +       else regadd = 9 ;
4088 +
4089 +
4090 +       value = SPI_read(0,regadd);             //read original setting
4091 +
4092 +       if(tag)
4093 +               value |= 0x0010 ;               // set tag
4094 +       else
4095 +               value &= 0xFFEF ;               // set untag
4096 +
4097 +       SPI_write(regadd,value);                // write back!!
4098 +}
4099 +
4100 +/************************************************
4101 +* SPI_Set_PVID
4102 +* PVID -> PVID number :
4103 +* port_mask -> ports which would group as LAN
4104 +*             ex. 0x0F = 0000 1111 ==> port 0~3
4105 +************************************************/
4106 +void SPI_Set_PVID(unsigned int PVID,unsigned int port_mask)
4107 +{
4108 +       unsigned int i,value=0;
4109 +
4110 +       PVID &= 0x000F ;
4111 +
4112 +       for(i=0;i<ADM699X_PORT_NO;i++)
4113 +       {       if(port_mask&0x01)
4114 +               {
4115 +#ifdef CONFIG_ADM_6996
4116 +                       switch(i)
4117 +                       {
4118 +                               case 0:
4119 +                                       value = SPI_read(0,0x01);       // read original value
4120 +                                       value &= 0xC3FF ;                       //set PVIC column as 0 first
4121 +                                       value |= PVID << 10 ;           //Set PVID column as PVID
4122 +                                       SPI_write(0x01,value);          //write back
4123 +                                       break;
4124 +                               case 1:
4125 +                                       value = SPI_read(0,0x03);
4126 +                                       value &= 0xC3FF ;
4127 +                                       value |= PVID << 10 ;
4128 +                                       SPI_write(0x03,value);
4129 +                                       break;
4130 +                               case 2:
4131 +                                       value = SPI_read(0,0x05);
4132 +                                       value &= 0xC3FF ;
4133 +                                       value |= PVID << 10 ;
4134 +                                       SPI_write(0x05,value);
4135 +                                       break;
4136 +                               case 3:
4137 +                                       value = SPI_read(0,0x07);
4138 +                                       value &= 0xC3FF ;
4139 +                                       value |= PVID << 10 ;
4140 +                                       SPI_write(0x07,value);
4141 +                                       break;
4142 +                               case 4:
4143 +                                       value = SPI_read(0,0x08);
4144 +                                       value &= 0xC3FF ;
4145 +                                       value |= PVID << 10 ;
4146 +                                       SPI_write(0x08,value);
4147 +                                       break;
4148 +                               case 5:
4149 +                                       value = SPI_read(0,0x09);
4150 +                                       value &= 0xC3FF ;
4151 +                                       value |= PVID << 10 ;
4152 +                                       SPI_write(0x09,value);
4153 +                                       break;
4154 +                       }
4155 +#endif
4156 +#ifdef CONFIG_ADM_6999
4157 +                       value = SPI_read(0,(unsigned char)i+1);
4158 +                       value &= 0xC3FF ;
4159 +                       value |= PVID << 10 ;
4160 +                       SPI_write((unsigned char)i+1,value);
4161 +#endif
4162 +               }
4163 +               port_mask >>= 1;
4164 +       }
4165 +}
4166 +
4167 +
4168 +/************************************************
4169 +* SPI_get_PVID
4170 +* port -> which ports to VID
4171 +************************************************/
4172 +unsigned int SPI_Get_PVID(unsigned int port)
4173 +{
4174 +       unsigned int value=0;
4175 +
4176 +       if (port>=ADM6996_PORT_NO)
4177 +               return 0;
4178 +
4179 +       switch(port)
4180 +       {
4181 +               case 0:
4182 +                       value = SPI_read(0,0x01);       // read original value
4183 +                       value &= 0x3C00 ;               // get VID
4184 +                       value = value >> 10 ;           // Shift
4185 +                       break;
4186 +               case 1:
4187 +                       value = SPI_read(0,0x03);
4188 +                       value &= 0x3C00 ;
4189 +                       value = value >> 10 ;
4190 +                       break;
4191 +               case 2:
4192 +                       value = SPI_read(0,0x05);
4193 +                       value &= 0x3C00 ;
4194 +                       value = value >> 10 ;
4195 +                       break;
4196 +               case 3:
4197 +                       value = SPI_read(0,0x07);
4198 +                       value &= 0x3C00 ;
4199 +                       value = value >> 10 ;
4200 +                       break;
4201 +               case 4:
4202 +                       value = SPI_read(0,0x08);
4203 +                       value &= 0x3C00 ;
4204 +                       value = value >> 10 ;
4205 +                       break;
4206 +               case 5:
4207 +                       value = SPI_read(0,0x09);
4208 +                       value &= 0x3C00 ;
4209 +                       value = value >> 10 ;
4210 +                       break;
4211 +       }
4212 +       return value ;
4213 +}
4214 +
4215 +
4216 +/**********************************************
4217 +* SPI_mac_clone
4218 +* port -> the port which will lock or unlock
4219 +* lock -> 0/the port will be unlock
4220 +*        1/the port will be locked
4221 +**********************************************/
4222 +void SPI_mac_lock(unsigned int port, unsigned char lock)
4223 +{
4224 +       unsigned int i,value=0;
4225 +
4226 +       value = SPI_read(0,0x12);               // read original
4227 +
4228 +       for(i=0;i<ADM6996_PORT_NO;i++)
4229 +       {       if(lock)                                // lock port
4230 +               {
4231 +                       switch(port)
4232 +                       {
4233 +                               case 0: value|=0x0001;  break;  //port0:bit[0]
4234 +                               case 1: value|=0x0004;  break;  //port1:bit[2]
4235 +                               case 2: value|=0x0010;  break;  //port2:bit[4]
4236 +                               case 3: value|=0x0040;  break;  //port3:bit[6]
4237 +                               case 4: value|=0x0080;  break;  //port4:bit[7]
4238 +                               case 5: value|=0x0100;  break;  //port5:bit[8]
4239 +                       }
4240 +               }
4241 +               else
4242 +               {
4243 +                       switch(i)                       // unlock port
4244 +                       {
4245 +                               case 0: value&=0xFFFE;  break;
4246 +                               case 1: value&=0xFFFB;  break;
4247 +                               case 2: value&=0xFFEF;  break;
4248 +                               case 3: value&=0xFFBF;  break;
4249 +                               case 4: value&=0xFF7F;  break;
4250 +                               case 5: value&=0xFEFF;  break;
4251 +                       }
4252 +               }
4253 +       }
4254 +
4255 +       SPI_write(0x12,value);
4256 +}
4257 +
4258 +
4259 +/***************************************************
4260 +* SPI_learn_pause
4261 +* pause = 01-80-c2-00-00-01
4262 +* DA=distination address
4263 +* forward -> 0: if DA == pause then drop and stop mac learning
4264 +*           1: if DA == pause ,then forward it
4265 +***************************************************/
4266 +void SPI_pause_cmd_forward(unsigned char forward)
4267 +{
4268 +       unsigned int value=0;
4269 +
4270 +       value = SPI_read(0,0x2C);               // read original setting
4271 +       if(forward)
4272 +               value |= 0x2000;                // set bit[13] '1'
4273 +       else
4274 +               value &= 0xDFFF;                // set bit[13] '0'
4275 +
4276 +       SPI_write(0x2C,value);
4277 +
4278 +}
4279 +
4280 +
4281 +/************************************************
4282 +* SPI_read
4283 +* table -> which table to be read: 1/count  0/EEPROM
4284 +* addr  -> Address to be read
4285 +* return : Value of the register
4286 +*************************************************/
4287 +unsigned int SPI_read(unsigned char table,unsigned char addr)
4288 +{
4289 +       int i ;
4290 +       unsigned int value=0;
4291 +       unsigned int bit;
4292 +#ifdef CONFIG_IT8712_GPIO
4293 +       unsigned char status;
4294 +#else
4295 +    unsigned int ad1;
4296 +#endif
4297 +
4298 +#ifdef CONFIG_IT8712_GPIO
4299 +       status = inb_gpio(LPC_GPIO_SET);
4300 +       status &= ~(ADM_EDIO) ;         //EDIO low
4301 +       outb_gpio(LPC_GPIO_SET, status);
4302 +#else
4303 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
4304 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
4305 +#endif
4306 +
4307 +       SPI_CS_enable(0);
4308 +
4309 +       SPI_pre_st(); // PRE+ST
4310 +       SPI_write_bit(1); // OPCODE '10' for read
4311 +       SPI_write_bit(0);
4312 +
4313 +       (table==1) ? SPI_write_bit(1) : SPI_write_bit(0) ;      // table select
4314 +
4315 +       SPI_write_bit(0);               // Device Address
4316 +       SPI_write_bit(0);
4317 +
4318 +
4319 +       // send 7 bits address to be read
4320 +       for (i=6;i>=0;i--) {
4321 +               bit= ((addr>>i) & 0x01) ? 1 :0 ;
4322 +               SPI_write_bit(bit);
4323 +       }
4324 +
4325 +
4326 +       // turn around
4327 +       SPI_read_bit(); // TA_Z
4328 +
4329 +       value=0;
4330 +       for (i=31;i>=0;i--) { // READ DATA
4331 +               bit=SPI_read_bit();
4332 +               value |= bit << i ;
4333 +       }
4334 +
4335 +       SPI_read_bit(); // dumy clock
4336 +       SPI_read_bit(); // dumy clock
4337 +
4338 +       if(!table)                                      // EEPROM, only fetch 16 bits data
4339 +       {
4340 +           if(addr&0x01)                               // odd number content (register,register-1)
4341 +                   value >>= 16 ;                      // so we remove the rear 16bits
4342 +           else                                        // even number content (register+1,register),
4343 +                   value &= 0x0000FFFF ;               // so we keep the rear 16 bits
4344 +       }
4345 +
4346 +
4347 +       SPI_CS_enable(0);
4348 +
4349 +#ifdef CONFIG_IT8712_GPIO
4350 +       status = inb_gpio(LPC_GPIO_SET);
4351 +       status &= ~(ADM_EDIO) ;         //EDIO low
4352 +       outb_gpio(LPC_GPIO_SET, status);
4353 +#else
4354 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
4355 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
4356 +#endif
4357 +
4358 +       return(value);
4359 +
4360 +}
4361 +
4362 +
4363 +
4364 +/**************************************************
4365 +* SPI_port_en
4366 +* port -> Number of port to config
4367 +* enable -> 1/ enable this port
4368 +*          0/ disable this port
4369 +**************************************************/
4370 +void SPI_port_enable(unsigned int port,unsigned char enable)
4371 +{
4372 +       unsigned int reg_val ;
4373 +       unsigned char reg_add ;
4374 +
4375 +       if(port<=3)
4376 +               reg_add=2*port+1;
4377 +       else if(port==4) reg_add = 8 ;
4378 +       else reg_add = 9 ;
4379 +
4380 +       reg_val = SPI_read(0,reg_add);
4381 +       if(enable)
4382 +       {
4383 +               reg_val &= 0xFFDF ;
4384 +               SPI_write(reg_add,reg_val);
4385 +       }
4386 +       else
4387 +       {
4388 +               reg_val |= 0x0020 ;
4389 +               SPI_write(reg_add,reg_val);
4390 +       }
4391 +}
4392 +
4393 +/********************************************************
4394 +* get port status
4395 +* port -> specify the port number to get configuration
4396 +*********************************************************/
4397 +void SPI_get_status(unsigned int port)
4398 +{
4399 +/*     unsigned int reg_val,add_offset[6];
4400 +       struct PORT_STATUS *status;
4401 +       status = &port_state[port];
4402 +
4403 +       if(port>(ADM6996_PORT_NO-1))
4404 +               return ;
4405 +
4406 +       // Link estabilish , speed, deplex, flow control ?
4407 +       if(port < 5 )
4408 +       {
4409 +               reg_val = SPI_read(1, 1) ;
4410 +               if(port < 4)
4411 +                       reg_val >>= port*8 ;
4412 +               else
4413 +                       reg_val >>=28 ;
4414 +               status->link = reg_val & 0x00000001 ;
4415 +               status->speed = reg_val  & 0x00000002 ;
4416 +               status->duplex = reg_val & 0x00000004 ;
4417 +               status->flow_ctl = reg_val & 0x00000008 ;
4418 +       }
4419 +       else if(port ==5 )
4420 +       {
4421 +               reg_val = SPI_read(1, 2) ;
4422 +               status->link = reg_val & 0x00000001 ;
4423 +               status->speed = reg_val  & 0x00000002 ;
4424 +               status->duplex = reg_val & 0x00000008 ;
4425 +               status->flow_ctl = reg_val & 0x00000010 ;
4426 +       }
4427 +
4428 +       //   Mac Lock ?
4429 +       reg_val = SPI_read(0,0x12);
4430 +       switch(port)
4431 +       {
4432 +               case 0: status->mac_lock = reg_val & 0x00000001;
4433 +               case 1: status->mac_lock = reg_val & 0x00000004;
4434 +               case 2: status->mac_lock = reg_val & 0x00000010;
4435 +               case 3: status->mac_lock = reg_val & 0x00000040;
4436 +               case 4: status->mac_lock = reg_val & 0x00000080;
4437 +               case 5: status->mac_lock = reg_val & 0x00000100;
4438 +       }
4439 +
4440 +       // port enable ?
4441 +       add_offset[0] = 0x01 ;          add_offset[1] = 0x03 ;
4442 +       add_offset[2] = 0x05 ;          add_offset[3] = 0x07 ;
4443 +       add_offset[4] = 0x08 ;          add_offset[5] = 0x09 ;
4444 +       reg_val = SPI_read(0,add_offset[port]);
4445 +       status->port_disable = reg_val & 0x0020;
4446 +
4447 +
4448 +       //  Packet Count ...
4449 +       add_offset[0] = 0x04 ;          add_offset[1] = 0x06 ;
4450 +       add_offset[2] = 0x08 ;          add_offset[3] = 0x0a ;
4451 +       add_offset[4] = 0x0b ;          add_offset[5] = 0x0c ;
4452 +
4453 +       reg_val = SPI_read(1,add_offset[port]);
4454 +       status->rx_pac_count = reg_val ;
4455 +       reg_val = SPI_read(1,add_offset[port]+9);
4456 +       status->rx_pac_byte = reg_val ;
4457 +       reg_val = SPI_read(1,add_offset[port]+18);
4458 +       status->tx_pac_count = reg_val ;
4459 +       reg_val = SPI_read(1,add_offset[port]+27);
4460 +       status->tx_pac_byte = reg_val ;
4461 +       reg_val = SPI_read(1,add_offset[port]+36);
4462 +       status->collision_count = reg_val ;
4463 +       reg_val = SPI_read(1,add_offset[port]+45);
4464 +       status->error_count = reg_val ;
4465 +       reg_val = SPI_read(1, 0x3A);
4466 +       switch(port)
4467 +       {
4468 +               case 0: status->rx_pac_count_overflow = reg_val & 0x00000001;
4469 +                       status->rx_pac_byte_overflow = reg_val & 0x00000200 ;
4470 +               case 1: status->rx_pac_count_overflow = reg_val & 0x00000004;
4471 +                       status->rx_pac_byte_overflow = reg_val & 0x00000800 ;
4472 +               case 2: status->rx_pac_count_overflow = reg_val & 0x00000010;
4473 +                       status->rx_pac_byte_overflow = reg_val & 0x00002000 ;
4474 +               case 3: status->rx_pac_count_overflow = reg_val & 0x00000040;;
4475 +                       status->rx_pac_byte_overflow = reg_val & 0x00008000 ;
4476 +               case 4: status->rx_pac_count_overflow = reg_val & 0x00000080;
4477 +                       status->rx_pac_byte_overflow = reg_val & 0x00010000 ;
4478 +               case 5: status->rx_pac_count_overflow = reg_val & 0x00000100;
4479 +                       status->rx_pac_byte_overflow = reg_val & 0x00020000 ;
4480 +       }
4481 +
4482 +       reg_val = SPI_read(1, 0x3B);
4483 +       switch(port)
4484 +       {
4485 +               case 0: status->tx_pac_count_overflow = reg_val & 0x00000001;
4486 +                       status->tx_pac_byte_overflow  = reg_val & 0x00000200 ;
4487 +               case 1: status->tx_pac_count_overflow  = reg_val & 0x00000004;
4488 +                       status->tx_pac_byte_overflow  = reg_val & 0x00000800 ;
4489 +               case 2: status->tx_pac_count_overflow  = reg_val & 0x00000010;
4490 +                       status->tx_pac_byte_overflow  = reg_val & 0x00002000 ;
4491 +               case 3: status->tx_pac_count_overflow  = reg_val & 0x00000040;;
4492 +                       status->tx_pac_byte_overflow  = reg_val & 0x00008000 ;
4493 +               case 4: status->tx_pac_count_overflow  = reg_val & 0x00000080;
4494 +                       status->tx_pac_byte_overflow  = reg_val & 0x00010000 ;
4495 +               case 5: status->tx_pac_count_overflow  = reg_val & 0x00000100;
4496 +                       status->tx_pac_byte_overflow  = reg_val & 0x00020000 ;
4497 +       }
4498 +*/
4499 +
4500 +       unsigned int reg_val;
4501 +       struct PORT_STATUS *status;
4502 +       status = &port_state[port];
4503 +
4504 +       if(port>=ADM6999_PORT_NO)
4505 +               return ;
4506 +
4507 +       // Link estabilish , speed, deplex, flow control ?
4508 +       if(port < ADM6999_PORT_NO-1 )
4509 +       {
4510 +               reg_val = SPI_read(1, 0x01) ;
4511 +               reg_val = reg_val >> port*4 ;
4512 +               status->link = reg_val & 0x00000001 ;
4513 +               status->speed = reg_val  & 0x00000002 ;
4514 +               status->duplex = reg_val & 0x00000004 ;
4515 +               status->flow_ctl = reg_val & 0x00000008 ;
4516 +       }
4517 +       else if(port == (ADM6999_PORT_NO-1) )
4518 +       {
4519 +               reg_val = SPI_read(1, 0x02) ;
4520 +               status->link = reg_val & 0x00000001 ;
4521 +               status->speed = reg_val  & 0x00000002 ;
4522 +               status->duplex = reg_val & 0x00000008 ;
4523 +               status->flow_ctl = reg_val & 0x00000010 ;
4524 +       }
4525 +
4526 +       // Mac Lock ?
4527 +       reg_val = SPI_read(0,0x12);
4528 +       reg_val = reg_val >> port ;
4529 +       reg_val = reg_val & 0x01 ;
4530 +       status->mac_lock = reg_val ? 0x01:0x00 ;
4531 +
4532 +       // port enable ?
4533 +       reg_val = SPI_read(0,(unsigned char)port+1);
4534 +       status->port_disable = reg_val & 0x0020;
4535 +
4536 +       //  Packet Count ...
4537 +       reg_val = SPI_read(1,(unsigned char)port+0x04);
4538 +       status->rx_pac_count = reg_val ;
4539 +       reg_val = SPI_read(1,(unsigned char)port+0x0D);
4540 +       status->rx_pac_byte = reg_val ;
4541 +       reg_val = SPI_read(1,(unsigned char)port+0x16);
4542 +       status->tx_pac_count = reg_val ;
4543 +       reg_val = SPI_read(1,(unsigned char)port+0x1F);
4544 +       status->tx_pac_byte = reg_val ;
4545 +       reg_val = SPI_read(1,(unsigned char)port+0x28);
4546 +       status->collision_count = reg_val ;
4547 +       reg_val = SPI_read(1,(unsigned char)port+0x31);
4548 +       status->error_count = reg_val ;
4549 +       reg_val = SPI_read(1, 0x3A);
4550 +       reg_val = reg_val >> port ;
4551 +       status->rx_pac_count_overflow = reg_val & 0x00000001;
4552 +       reg_val = reg_val >> 0x09 ;
4553 +       status->rx_pac_byte_overflow = reg_val & 0x00000001 ;
4554 +
4555 +       reg_val = SPI_read(1, 0x3B);
4556 +       reg_val = reg_val >> port ;
4557 +       status->tx_pac_count_overflow = reg_val & 0x00000001;
4558 +       reg_val = reg_val >> 0x09 ;
4559 +       status->tx_pac_byte_overflow  = reg_val & 0x00000001 ;
4560 +
4561 +       reg_val = SPI_read(1, 0x3C);
4562 +       reg_val = reg_val >> port ;
4563 +       status->collision_count_overflow = reg_val & 0x00000001;
4564 +       reg_val = reg_val >> 0x09 ;
4565 +       status->error_count_overflow  = reg_val & 0x00000001 ;
4566 +
4567 +}
4568 +
4569 +unsigned int SPI_get_identifier(void)
4570 +{
4571 +       unsigned int flag=0;
4572 +
4573 +#ifdef CONFIG_IT8712_GPIO
4574 +
4575 +       if (!it8712_exist) {
4576 +               return -ENODEV;
4577 +       }
4578 +       printk("it8712_gpio init\n");
4579 +
4580 +       /* initialize registers */
4581 +       // switch all multi-function pins to GPIO
4582 +       LPCSetConfig(LDN_GPIO, 0x28, 0xff);
4583 +
4584 +       // set simple I/O base address
4585 +       LPCSetConfig(LDN_GPIO, 0x62, IT8712_GPIO_BASE >> 8);
4586 +       LPCSetConfig(LDN_GPIO, 0x63, (unsigned char) IT8712_GPIO_BASE >> 8);
4587 +
4588 +       // select GPIO to simple I/O
4589 +       LPCSetConfig(LDN_GPIO, 0xc3, 0xff);
4590 +
4591 +       // enable internal pull-up
4592 +       LPCSetConfig(LDN_GPIO, 0xbb, 0xff);
4593 +
4594 +#endif
4595 +
4596 +       flag = SPI_read(1,0x00);
4597 +       printk("Get ADM identifier %6x\n",flag);
4598 +       if ((flag & 0xFFFF0) == 0x21120) {
4599 +               printk("ADM699X Found\n");
4600 +               return 1;
4601 +       }
4602 +       else {
4603 +               printk("ADM699X not Found\n");
4604 +               return 0;
4605 +       }
4606 +}
4607 +
4608 --- /dev/null
4609 +++ b/drivers/net/sl351x_crc16.c
4610 @@ -0,0 +1,93 @@
4611 +/****************************************************************************
4612 +* Name                 : sl351x_crc16.c
4613 +* Description  :
4614 +*              Implement CRC16
4615 +*              refer to RFC1662
4616 +* History
4617 +*
4618 +*      Date            Writer          Description
4619 +*      -----------     -----------     -------------------------------------------------
4620 +*      09/14/2005      Gary Chen       Create
4621 +*
4622 +****************************************************************************/
4623 +
4624 +#define INITFCS16              0xffff  /* Initial FCS value */
4625 +#define GOODFCS16              0xf0b8  /* Good final FCS value */
4626 +#define SWAP_WORD(x)   (unsigned short)((((unsigned short)x & 0x00FF) << 8) |  \
4627 +                                                                                (((unsigned short)x & 0xFF00) >> 8))
4628 +
4629 +/*----------------------------------------------------------------------
4630 +*      x**0 + x**5 + x**12 + x**16
4631 +*----------------------------------------------------------------------*/
4632 +static const unsigned short crc16_tbl[256] = {
4633 +      0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
4634 +      0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
4635 +      0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
4636 +      0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
4637 +      0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
4638 +      0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
4639 +      0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
4640 +      0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
4641 +      0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
4642 +      0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
4643 +      0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
4644 +      0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
4645 +      0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
4646 +      0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
4647 +      0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
4648 +      0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
4649 +      0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
4650 +      0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
4651 +      0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
4652 +      0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
4653 +      0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
4654 +      0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
4655 +      0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
4656 +      0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
4657 +      0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
4658 +      0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
4659 +      0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
4660 +      0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
4661 +      0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
4662 +      0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
4663 +      0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
4664 +      0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
4665 +};
4666 +
4667 +/*----------------------------------------------------------------------
4668 +* hash_crc16
4669 +*----------------------------------------------------------------------*/
4670 +unsigned short hash_crc16(unsigned short crc, unsigned char *datap, unsigned long len)
4671 +{
4672 +    while (len--)
4673 +    {
4674 +        crc = (crc >> 8) ^ crc16_tbl[(crc ^ (*datap++)) & 0xff];
4675 +    }
4676 +
4677 +    return (crc);
4678 +
4679 +}
4680 +
4681 +/*----------------------------------------------------------------------
4682 +* hash_check_crc16
4683 +*----------------------------------------------------------------------*/
4684 +unsigned long hash_check_crc16(unsigned char *datap, unsigned long len)
4685 +{
4686 +    unsigned short crc;
4687 +
4688 +    crc = hash_crc16(INITFCS16, datap, len );
4689 +    return (crc == GOODFCS16) ?  0 : 1;
4690 +}
4691 +
4692 +/*----------------------------------------------------------------------
4693 +* hash_gen_crc16
4694 +*----------------------------------------------------------------------*/
4695 +unsigned short hash_gen_crc16(unsigned char *datap, unsigned long len)
4696 +{
4697 +    unsigned short crc;
4698 +
4699 +    crc = hash_crc16(INITFCS16, datap, len);
4700 +    crc ^= 0xffff;
4701 +
4702 +    return(SWAP_WORD(crc));
4703 +}
4704 --- /dev/null
4705 +++ b/drivers/net/sl351x_gmac.c
4706 @@ -0,0 +1,5622 @@
4707 +/**************************************************************************
4708 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
4709 +*--------------------------------------------------------------------------
4710 +* Name                 : sl351x_gmac.c
4711 +* Description  :
4712 +*              Ethernet device driver for Storlink SL351x FPGA
4713 +*
4714 +* History
4715 +*
4716 +*      Date            Writer          Description
4717 +*      -----------     -----------     -------------------------------------------------
4718 +*      08/22/2005      Gary Chen       Create and implement
4719 +*   27/10/2005  CH Hsu      Porting to Linux
4720 +*
4721 +****************************************************************************/
4722 +#include <linux/module.h>
4723 +#include <linux/kernel.h>
4724 +#include <linux/slab.h>
4725 +#include <linux/mm.h>
4726 +#include <linux/compiler.h>
4727 +#include <linux/pci.h>
4728 +#include <linux/init.h>
4729 +#include <linux/ioport.h>
4730 +#include <linux/netdevice.h>
4731 +#include <linux/etherdevice.h>
4732 +#include <linux/rtnetlink.h>
4733 +#include <linux/delay.h>
4734 +#include <linux/ethtool.h>
4735 +#include <linux/mii.h>
4736 +#include <linux/completion.h>
4737 +#include <asm/hardware.h>
4738 +#include <asm/io.h>
4739 +#include <asm/irq.h>
4740 +#include <asm/semaphore.h>
4741 +#include <asm/arch/irqs.h>
4742 +#include <asm/arch/it8712.h>
4743 +#include <linux/mtd/kvctl.h>
4744 +#include <linux/skbuff.h>
4745 +#include <linux/in.h>
4746 +#include <linux/ip.h>
4747 +#include <linux/tcp.h>
4748 +#include <linux/udp.h>
4749 +
4750 +#include <linux/mtd/kvctl.h>
4751 +
4752 +#define         MIDWAY
4753 +#define         SL_LEPUS
4754 +#define VITESSE_G5SWITCH       1
4755 +
4756 +#ifndef CONFIG_SL351x_RXTOE
4757 +//#define CONFIG_SL351x_RXTOE  1
4758 +#endif
4759 +#undef CONFIG_SL351x_RXTOE
4760 +
4761 +#include <asm/arch/sl2312.h>
4762 +#include <asm/arch/sl351x_gmac.h>
4763 +#include <asm/arch/sl351x_hash_cfg.h>
4764 +#include <asm/arch/sl351x_nat_cfg.h>
4765 +
4766 +#ifdef CONFIG_SL351x_SYSCTL
4767 +#include <linux/sysctl_storlink.h>
4768 +#endif
4769 +
4770 +#ifdef CONFIG_SL351x_RXTOE
4771 +#include <asm/arch/sl351x_toe.h>
4772 +#include <net/tcp.h>
4773 +#include <linux/tcp.h>
4774 +#include <linux/ip.h>
4775 +#endif
4776 +
4777 +// #define SL351x_TEST_WORKAROUND
4778 +#ifdef CONFIG_SL351x_NAT
4779 +#define CONFIG_SL_NAPI                                 1
4780 +#endif
4781 +#define GMAX_TX_INTR_DISABLED                  1
4782 +#define DO_HW_CHKSUM                                   1
4783 +#define ENABLE_TSO                                             1
4784 +#define GMAC_USE_TXQ0                                  1
4785 +// #define NAT_WORKAROUND_BY_RESET_GMAC        1
4786 +// #define HW_RXBUF_BY_KMALLOC                 1
4787 +//#define _DUMP_TX_TCP_CONTENT 1
4788 +#define        br_if_ioctl                                             1
4789 +#define GMAC_LEN_1_2_ISSUE                             1
4790 +
4791 +#define GMAC_EXISTED_FLAG                      0x5566abcd
4792 +#define CONFIG_MAC_NUM                         GMAC_NUM
4793 +#define GMAC0_BASE                                     TOE_GMAC0_BASE
4794 +#define GMAC1_BASE                                     TOE_GMAC1_BASE
4795 +#define PAUSE_SET_HW_FREEQ                     (TOE_HW_FREEQ_DESC_NUM / 2)
4796 +#define PAUSE_REL_HW_FREEQ                     ((TOE_HW_FREEQ_DESC_NUM / 2) + 10)
4797 +#define DEFAULT_RXQ_MAX_CNT                    256
4798 +#ifdef L2_jumbo_frame
4799 +#define TCPHDRLEN(tcp_hdr)  ((ntohs(*((__u16 *)tcp_hdr + 6)) >> 12) & 0x000F)
4800 +#endif
4801 +
4802 +/* define chip information */
4803 +#define DRV_NAME                                       "SL351x"
4804 +#define DRV_VERSION                                    "0.1.4"
4805 +#define SL351x_DRIVER_NAME             DRV_NAME " Giga Ethernet driver " DRV_VERSION
4806 +
4807 +#define toe_gmac_enable_interrupt(irq) enable_irq(irq)
4808 +#define toe_gmac_disable_interrupt(irq)        disable_irq(irq)
4809 +
4810 +#ifdef SL351x_GMAC_WORKAROUND
4811 +#define GMAC_SHORT_FRAME_THRESHOLD             10
4812 +static struct timer_list gmac_workround_timer_obj;
4813 +void sl351x_poll_gmac_hanged_status(u32 data);
4814 +#ifdef CONFIG_SL351x_NAT
4815 +//#define IxscriptMate_1518                            1
4816 +       void sl351x_nat_workaround_init(void);
4817 +       #ifndef NAT_WORKAROUND_BY_RESET_GMAC
4818 +               static void sl351x_nat_workaround_handler(void);
4819 +       #endif
4820 +#endif
4821 +#endif
4822 +
4823 +#ifdef GMAC_LEN_1_2_ISSUE
4824 +       #define _DEBUG_PREFETCH_NUM     256
4825 +static int     _debug_prefetch_cnt;
4826 +static char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
4827 +#endif
4828 +/*************************************************************
4829 + *         Global Variable
4830 + *************************************************************/
4831 +static int     gmac_initialized = 0;
4832 +TOE_INFO_T toe_private_data;
4833 +//static int           do_again = 0;
4834 +spinlock_t gmac_fq_lock;
4835 +unsigned int FLAG_SWITCH;
4836 +
4837 +static unsigned int            next_tick = 3 * HZ;
4838 +static unsigned char           eth_mac[CONFIG_MAC_NUM][6]= {{0x00,0x11,0x11,0x87,0x87,0x87}, {0x00,0x22,0x22,0xab,0xab,0xab}};
4839 +
4840 +#undef CONFIG_SL351x_RXTOE
4841 +extern NAT_CFG_T nat_cfg;
4842 +
4843 +/************************************************/
4844 +/*                 function declare             */
4845 +/************************************************/
4846 +static int gmac_set_mac_address(struct net_device *dev, void *addr);
4847 +static unsigned int gmac_get_phy_vendor(int phy_addr);
4848 +static void gmac_set_phy_status(struct net_device *dev);
4849 +void gmac_get_phy_status(struct net_device *dev);
4850 +static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
4851 +static void gmac_tx_timeout(struct net_device *dev);
4852 +static int gmac_phy_thread (void *data);
4853 +struct net_device_stats * gmac_get_stats(struct net_device *dev);
4854 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev);
4855 +static void gmac_set_rx_mode(struct net_device *dev);
4856 +static irqreturn_t toe_gmac_interrupt (int irq, void *dev_instance);
4857 +static void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp);
4858 +unsigned int mii_read(unsigned char phyad,unsigned char regad);
4859 +void mii_write(unsigned char phyad,unsigned char regad,unsigned int value);
4860 +void mac_init_drv(void);
4861 +
4862 +static void toe_init_free_queue(void);
4863 +static void toe_init_swtx_queue(void);
4864 +static void toe_init_default_queue(void);
4865 +#ifdef CONFIG_SL351x_RXTOE
4866 +static void toe_init_interrupt_queue(void);
4867 +#endif
4868 +static void toe_init_interrupt_config(void);
4869 +static void toe_gmac_sw_reset(void);
4870 +static int toe_gmac_init_chip(struct net_device *dev);
4871 +static void toe_gmac_enable_tx_rx(struct net_device* dev);
4872 +static void toe_gmac_disable_tx_rx(struct net_device *dev);
4873 +static void toe_gmac_hw_start(struct net_device *dev);
4874 +static void toe_gmac_hw_stop(struct net_device *dev);
4875 +static int toe_gmac_clear_counter(struct net_device *dev);
4876 +static void toe_init_gmac(struct net_device *dev);
4877 +static  void toe_gmac_tx_complete(GMAC_INFO_T *tp, unsigned int tx_qid, struct net_device *dev, int interrupt);
4878 +#ifdef CONFIG_SL_NAPI
4879 +static int gmac_rx_poll(struct net_device *dev, int *budget);
4880 +// static void toe_gmac_disable_rx(struct net_device *dev);
4881 +// static void toe_gmac_enable_rx(struct net_device *dev);
4882 +#endif
4883 +
4884 +u32 mac_read_dma_reg(int mac, unsigned int offset);
4885 +void mac_write_dma_reg(int mac, unsigned int offset, u32 data);
4886 +void mac_stop_txdma(struct net_device *dev);
4887 +void mac_get_sw_tx_weight(struct net_device *dev, char *weight);
4888 +void mac_set_sw_tx_weight(struct net_device *dev, char *weight);
4889 +void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
4890 +void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
4891 +static inline void toe_gmac_fill_free_q(void);
4892 +
4893 +#ifdef VITESSE_G5SWITCH
4894 +extern int Get_Set_port_status(void);
4895 +extern int SPI_default(void);
4896 +extern unsigned int SPI_get_identifier(void);
4897 +void gmac_get_switch_status(struct net_device *dev);
4898 +unsigned int Giga_switch=0;
4899 +unsigned int switch_port_no=0;
4900 +unsigned int ever_dwon=0;
4901 +#endif
4902 +
4903 +/************************************************/
4904 +/*            GMAC function declare             */
4905 +/************************************************/
4906 +static int gmac_open (struct net_device *dev);
4907 +static int gmac_close (struct net_device *dev);
4908 +static void gmac_cleanup_module(void);
4909 +static void gmac_get_mac_address(void);
4910 +
4911 +#ifdef CONFIG_SL351x_NAT
4912 +static void toe_init_hwtx_queue(void);
4913 +extern void sl351x_nat_init(void);
4914 +extern void sl351x_nat_input(struct sk_buff *skb, int port, void *l3off, void *l4off);
4915 +extern int sl351x_nat_output(struct sk_buff *skb, int port);
4916 +extern int sl351x_nat_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
4917 +#endif
4918 +
4919 +#ifdef CONFIG_SL351x_RXTOE
4920 +extern void set_toeq_hdr(struct toe_conn* connection, TOE_INFO_T* toe, struct net_device *dev);
4921 +extern void sl351x_toe_init(void);
4922 +extern void toe_gmac_handle_toeq(struct net_device *dev, GMAC_INFO_T* tp, __u32 status);
4923 +extern struct toe_conn* init_toeq(int ipver, void* iph, struct tcphdr* tcp_hdr, TOE_INFO_T* toe, unsigned char* l2hdr);
4924 +#endif
4925 +
4926 +int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2);
4927 +void mac_set_rule_enable_bit(int mac, int rule, int data);
4928 +int mac_set_rule_action(int mac, int rule, int data);
4929 +int mac_get_MRxCRx(int mac, int rule, int ctrlreg);
4930 +void mac_set_MRxCRx(int mac, int rule, int ctrlreg, u32 data);
4931 +
4932 +/*----------------------------------------------------------------------
4933 +*      Ethernet Driver init
4934 +*----------------------------------------------------------------------*/
4935 +
4936 +static int __init gmac_init_module(void)
4937 +{
4938 +       GMAC_INFO_T             *tp;
4939 +       struct net_device       *dev;
4940 +       int             i,j;
4941 +       unsigned int    chip_id;
4942 +//     unsigned int chip_version;
4943 +
4944 +#ifdef CONFIG_SL3516_ASIC
4945 +{
4946 +    unsigned int    val;
4947 +    /* set GMAC global register */
4948 +    val = readl(GMAC_GLOBAL_BASE_ADDR+0x10);
4949 +    val = val | 0x005f0000;
4950 +    writel(val,GMAC_GLOBAL_BASE_ADDR+0x10);
4951 +//    writel(0xb737b737,GMAC_GLOBAL_BASE_ADDR+0x1c); //For Socket Board
4952 +    writel(0x77777777,GMAC_GLOBAL_BASE_ADDR+0x20);
4953 +//    writel(0xa737b747,GMAC_GLOBAL_BASE_ADDR+0x1c);//For Mounting Board
4954 +
4955 +       //debug_Aaron
4956 +    //writel(0xa7f0a7f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For Mounting Board
4957 +    writel(0xa7f0b7f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For Mounting Board
4958 +
4959 +    writel(0x77777777,GMAC_GLOBAL_BASE_ADDR+0x24);
4960 +       writel(0x09200030,GMAC_GLOBAL_BASE_ADDR+0x2C);
4961 +       val = readl(GMAC_GLOBAL_BASE_ADDR+0x04);
4962 +       if((val&(1<<20))==0){           // GMAC1 enable
4963 +               val = readl(GMAC_GLOBAL_BASE_ADDR+0x30);
4964 +               val = (val & 0xe7ffffff) | 0x08000000;
4965 +               writel(val,GMAC_GLOBAL_BASE_ADDR+0x30);
4966 +       }
4967 +}
4968 +#endif
4969 +
4970 +#ifdef VITESSE_G5SWITCH
4971 +       Giga_switch = SPI_get_identifier();
4972 +       if(Giga_switch)
4973 +               switch_port_no = SPI_default();
4974 +#endif
4975 +
4976 +       chip_id = readl(GMAC_GLOBAL_BASE_ADDR+0x0);
4977 +       if (chip_id == 0x3512C1)
4978 +       {
4979 +               writel(0x5787a5f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For 3512 Switch Board
4980 +               writel(0x55557777,GMAC_GLOBAL_BASE_ADDR+0x20);//For 3512 Switch Board
4981 +       }
4982 +//#endif
4983 +
4984 +       mac_init_drv();
4985 +
4986 +       printk (KERN_INFO SL351x_DRIVER_NAME " built at %s %s\n", __DATE__, __TIME__);
4987 +
4988 +//     init_waitqueue_entry(&wait, current);
4989 +
4990 +       // printk("GMAC Init......\n");
4991 +
4992 +       i = 0;
4993 +       for(j = 0; i<CONFIG_MAC_NUM; j++)
4994 +       {
4995 +               i=j;
4996 +               if(Giga_switch){                // if gswitch present, swap eth0/1
4997 +                       if(j==0)
4998 +                               i=1;
4999 +                       else if(j==1)
5000 +                               i=0;
5001 +               }
5002 +
5003 +               tp = (GMAC_INFO_T *)&toe_private_data.gmac[i];
5004 +               tp->dev = NULL;
5005 +               if (tp->existed != GMAC_EXISTED_FLAG) continue;
5006 +
5007 +               dev = alloc_etherdev(0);
5008 +               if (dev == NULL)
5009 +               {
5010 +                       printk (KERN_ERR "Can't allocate ethernet device #%d .\n",i);
5011 +                       return -ENOMEM;
5012 +               }
5013 +
5014 +               dev->priv=tp;
5015 +               tp->dev = dev;
5016 +
5017 +               SET_MODULE_OWNER(dev);
5018 +
5019 +               // spin_lock_init(&tp->lock);
5020 +               spin_lock_init(&gmac_fq_lock);
5021 +               dev->base_addr = tp->base_addr;
5022 +               dev->irq = tp->irq;
5023 +           dev->open = gmac_open;
5024 +           dev->stop = gmac_close;
5025 +               dev->hard_start_xmit = gmac_start_xmit;
5026 +               dev->get_stats = gmac_get_stats;
5027 +               dev->set_multicast_list = gmac_set_rx_mode;
5028 +               dev->set_mac_address = gmac_set_mac_address;
5029 +               dev->do_ioctl = gmac_netdev_ioctl;
5030 +               dev->tx_timeout = gmac_tx_timeout;
5031 +               dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
5032 +#ifdef L2_jumbo_frame
5033 +               dev->mtu = 2018; //2002  ,2018
5034 +#endif
5035 +               if (tp->port_id == 0)
5036 +                       dev->tx_queue_len = TOE_GMAC0_SWTXQ_DESC_NUM;
5037 +               else
5038 +                       dev->tx_queue_len = TOE_GMAC1_SWTXQ_DESC_NUM;
5039 +
5040 +#ifdef DO_HW_CHKSUM
5041 +               dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
5042 +#ifdef ENABLE_TSO
5043 +               dev->features |= NETIF_F_TSO;
5044 +#endif
5045 +#endif
5046 +#ifdef CONFIG_SL_NAPI
5047 +        dev->poll = gmac_rx_poll;
5048 +        dev->weight = 64;
5049 +#endif
5050 +
5051 +               if (register_netdev(dev))
5052 +               {
5053 +                       gmac_cleanup_module();
5054 +                       return(-1);
5055 +               }
5056 +       }
5057 +
5058 +
5059 +//     FLAG_SWITCH = 0 ;
5060 +//     FLAG_SWITCH = SPI_get_identifier();
5061 +//     if(FLAG_SWITCH)
5062 +//     {
5063 +//             printk("Configure ADM699X...\n");
5064 +//             SPI_default();  //Add by jason for ADM699X configuration
5065 +//     }
5066 +       return (0);
5067 +}
5068 +
5069 +/*----------------------------------------------------------------------
5070 +*      gmac_cleanup_module
5071 +*----------------------------------------------------------------------*/
5072 +
5073 +static void gmac_cleanup_module(void)
5074 +{
5075 +    int i;
5076 +
5077 +#ifdef SL351x_GMAC_WORKAROUND
5078 +       del_timer(&gmac_workround_timer_obj);
5079 +#endif
5080 +
5081 +    for (i=0;i<CONFIG_MAC_NUM;i++)
5082 +    {
5083 +       if (toe_private_data.gmac[i].dev)
5084 +       {
5085 +               unregister_netdev(toe_private_data.gmac[i].dev);
5086 +               toe_private_data.gmac[i].dev = NULL;
5087 +        }
5088 +    }
5089 +       return ;
5090 +}
5091 +
5092 +module_init(gmac_init_module);
5093 +module_exit(gmac_cleanup_module);
5094 +
5095 +
5096 +/*----------------------------------------------------------------------
5097 +*      gmac_read_reg
5098 +*----------------------------------------------------------------------*/
5099 +static inline unsigned int gmac_read_reg(unsigned int base, unsigned int offset)
5100 +//static unsigned int gmac_read_reg(unsigned int base, unsigned int offset)
5101 +{
5102 +    volatile unsigned int reg_val;
5103 +
5104 +    reg_val = readl(base + offset);
5105 +       return (reg_val);
5106 +}
5107 +
5108 +/*----------------------------------------------------------------------
5109 +*      gmac_write_reg
5110 +*----------------------------------------------------------------------*/
5111 +static inline void gmac_write_reg(unsigned int base, unsigned int offset,unsigned int data,unsigned int bit_mask)
5112 +//static void gmac_write_reg(unsigned int base, unsigned int offset,unsigned int data,unsigned int bit_mask)
5113 +{
5114 +       volatile unsigned int reg_val;
5115 +    unsigned int *addr;
5116 +
5117 +       reg_val = ( gmac_read_reg(base, offset) & (~bit_mask) ) | (data & bit_mask);
5118 +       addr = (unsigned int *)(base + offset);
5119 +    writel(reg_val,addr);
5120 +       return;
5121 +}
5122 +
5123 +/*----------------------------------------------------------------------
5124 +*      mac_init_drv
5125 +*----------------------------------------------------------------------*/
5126 +void mac_init_drv(void)
5127 +{
5128 +       TOE_INFO_T                      *toe;
5129 +       int                                     i;
5130 +       QUEUE_THRESHOLD_T       threshold;
5131 +       u32                                     *destp;
5132 +       unsigned int            chip_id,chip_version;
5133 +
5134 +       chip_id = readl(GMAC_GLOBAL_BASE_ADDR+0x0);
5135 +       chip_version = chip_id & 0x1 ;
5136 +
5137 +       if (!gmac_initialized)
5138 +       {
5139 +               gmac_initialized = 1;
5140 +
5141 +               // clear non TOE Queue Header Area
5142 +               destp = (u32 *)TOE_NONTOE_QUE_HDR_BASE;
5143 +               for (; destp < (u32 *)NONTOE_Q_HDR_AREA_END; destp++)
5144 +                       *destp = 0x00;
5145 +
5146 +               // clear TOE Queue Header Area
5147 +               destp = (u32 *)TOE_TOE_QUE_HDR_BASE;
5148 +               for (; destp < (u32 *)TOE_Q_HDR_AREA_END; destp++)
5149 +                       *destp = 0x00;
5150 +
5151 +               // init private data
5152 +               toe = (TOE_INFO_T *)&toe_private_data;
5153 +               memset((void *)toe, 0, sizeof(TOE_INFO_T));
5154 +               toe->gmac[0].base_addr = GMAC0_BASE;
5155 +               toe->gmac[1].base_addr = GMAC1_BASE;
5156 +               toe->gmac[0].dma_base_addr = TOE_GMAC0_DMA_BASE;
5157 +               toe->gmac[1].dma_base_addr = TOE_GMAC1_DMA_BASE;
5158 +        toe->gmac[0].auto_nego_cfg = 1;
5159 +        toe->gmac[1].auto_nego_cfg = 1;
5160 +#ifdef CONFIG_SL3516_ASIC
5161 +        toe->gmac[0].speed_cfg = GMAC_SPEED_1000;
5162 +        toe->gmac[1].speed_cfg = GMAC_SPEED_1000;
5163 +#else
5164 +               toe->gmac[0].speed_cfg = GMAC_SPEED_100;
5165 +        toe->gmac[1].speed_cfg = GMAC_SPEED_100;
5166 +#endif
5167 +        toe->gmac[0].full_duplex_cfg = 1;
5168 +        toe->gmac[1].full_duplex_cfg = 1;
5169 +#ifdef CONFIG_SL3516_ASIC
5170 +        toe->gmac[0].phy_mode = GMAC_PHY_RGMII_1000;
5171 +        toe->gmac[1].phy_mode = GMAC_PHY_RGMII_1000;
5172 +#else
5173 +               toe->gmac[0].phy_mode = GMAC_PHY_RGMII_100;
5174 +        toe->gmac[1].phy_mode = GMAC_PHY_RGMII_100;
5175 +#endif
5176 +        toe->gmac[0].port_id = GMAC_PORT0;
5177 +        toe->gmac[1].port_id = GMAC_PORT1;
5178 +        toe->gmac[0].phy_addr = 0x1;
5179 +        toe->gmac[1].phy_addr = 2;
5180 +//      toe->gmac[0].irq = SL2312_INTERRUPT_GMAC0;
5181 +               toe->gmac[0].irq =1;
5182 +//      toe->gmac[1].irq = SL2312_INTERRUPT_GMAC1;
5183 +               toe->gmac[1].irq =2;
5184 +        toe->gmac[0].mac_addr1 = &eth_mac[0][0];
5185 +        toe->gmac[1].mac_addr1 = &eth_mac[1][0];
5186 +
5187 +               for (i=0; i<CONFIG_MAC_NUM; i++)
5188 +               {
5189 +                       unsigned int data, phy_vendor;
5190 +                       gmac_write_reg(toe->gmac[i].base_addr, GMAC_STA_ADD2, 0x55aa55aa, 0xffffffff);
5191 +                       data = gmac_read_reg(toe->gmac[i].base_addr, GMAC_STA_ADD2);
5192 +                       if (data == 0x55aa55aa)
5193 +                       {
5194 +#ifdef VITESSE_G5SWITCH
5195 +                               if(Giga_switch && (i==1)){
5196 +                                       toe->gmac[i].existed = GMAC_EXISTED_FLAG;
5197 +                                       break;
5198 +                               }
5199 +#endif
5200 +                               phy_vendor = gmac_get_phy_vendor(toe->gmac[i].phy_addr);
5201 +                               if (phy_vendor != 0 && phy_vendor != 0xffffffff)
5202 +                                       toe->gmac[i].existed = GMAC_EXISTED_FLAG;
5203 +                       }
5204 +               }
5205 +
5206 +               // Write GLOBAL_QUEUE_THRESHOLD_REG
5207 +               threshold.bits32 = 0;
5208 +               threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
5209 +                                                       TOE_SW_FREEQ_DESC_NUM/2;
5210 +               threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256/4 :
5211 +                                                       TOE_HW_FREEQ_DESC_NUM/4;
5212 +               threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256/4 :
5213 +                                                       TOE_TOE_DESC_NUM/4;
5214 +               threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256/4 :
5215 +                                                       TOE_INTR_DESC_NUM/4;
5216 +               writel(threshold.bits32, TOE_GLOBAL_BASE + GLOBAL_QUEUE_THRESHOLD_REG);
5217 +
5218 +               FLAG_SWITCH = 0;
5219 +               toe_gmac_sw_reset();
5220 +               toe_init_free_queue();
5221 +               toe_init_swtx_queue();
5222 +#ifdef CONFIG_SL351x_NAT
5223 +               toe_init_hwtx_queue();
5224 +#endif
5225 +               toe_init_default_queue();
5226 +#ifdef CONFIG_SL351x_RXTOE
5227 +               toe_init_interrupt_queue();
5228 +#endif
5229 +               toe_init_interrupt_config();
5230 +
5231 +#if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
5232 +               sl351x_hash_init();
5233 +#else
5234 +       {
5235 +               volatile u32 *dp1, *dp2, dword;
5236 +
5237 +               dp1 = (volatile u32 *) TOE_V_BIT_BASE;
5238 +               dp2 = (volatile u32 *) TOE_A_BIT_BASE;
5239 +
5240 +               for (i=0; i<HASH_TOTAL_ENTRIES/32; i++)
5241 +               {
5242 +                       *dp1++ = 0;
5243 +                       dword = *dp2++; // read-clear
5244 +               }
5245 +       }
5246 +#endif
5247 +       }
5248 +
5249 +#ifdef SL351x_GMAC_WORKAROUND
5250 +#ifdef CONFIG_SL351x_NAT
5251 +       sl351x_nat_workaround_init();
5252 +#endif
5253 +       init_timer(&gmac_workround_timer_obj);
5254 +       if (chip_version == 1)
5255 +       {
5256 +               gmac_workround_timer_obj.expires = jiffies * 50;
5257 +       }
5258 +       else
5259 +       {
5260 +               gmac_workround_timer_obj.expires = jiffies + 2;
5261 +       }
5262 +       gmac_workround_timer_obj.data = (unsigned long)&gmac_workround_timer_obj;
5263 +       gmac_workround_timer_obj.function = (void *)&sl351x_poll_gmac_hanged_status;
5264 +       add_timer(&gmac_workround_timer_obj);
5265 +#endif
5266 +}
5267 +
5268 +/*----------------------------------------------------------------------
5269 +*      toe_init_free_queue
5270 +*      (1) Initialize the Free Queue Descriptor Base Address & size
5271 +*              Register: TOE_GLOBAL_BASE + 0x0004
5272 +*      (2) Initialize DMA Read/Write pointer for
5273 +*              SW Free Queue and HW Free Queue
5274 +*      (3)     Initialize DMA Descriptors for
5275 +*              SW Free Queue and HW Free Queue,
5276 +*----------------------------------------------------------------------*/
5277 +static void toe_init_free_queue(void)
5278 +{
5279 +       int                             i;
5280 +       TOE_INFO_T                      *toe;
5281 +       DMA_RWPTR_T                     rwptr_reg;
5282 +//     unsigned int            rwptr_addr;
5283 +       unsigned int            desc_buf;
5284 +       GMAC_RXDESC_T           *sw_desc_ptr;
5285 +       struct sk_buff          *skb;
5286 +#ifdef CONFIG_SL351x_NAT
5287 +       GMAC_RXDESC_T           *desc_ptr;
5288 +       unsigned int            buf_ptr;
5289 +#endif
5290 +
5291 +       toe = (TOE_INFO_T *)&toe_private_data;
5292 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T)),
5293 +                                               (dma_addr_t *)&toe->sw_freeq_desc_base_dma) ;
5294 +       sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
5295 +       if (!desc_buf)
5296 +       {
5297 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5298 +               return;
5299 +       }
5300 +       memset((void *)desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
5301 +
5302 +       // DMA Queue Base & Size
5303 +       writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
5304 +                       TOE_GLOBAL_BASE + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
5305 +
5306 +       // init descriptor base
5307 +       toe->swfq_desc_base = desc_buf;
5308 +
5309 +       // SW Free Queue Read/Write Pointer
5310 +       rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
5311 +       rwptr_reg.bits.rptr = 0;
5312 +       toe->fq_rx_rwptr.bits32 = rwptr_reg.bits32;
5313 +       writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
5314 +
5315 +       // SW Free Queue Descriptors
5316 +       for (i=0; i<TOE_SW_FREEQ_DESC_NUM; i++)
5317 +       {
5318 +               sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
5319 +               sw_desc_ptr->word1.bits.sw_id = i;      // used to locate skb
5320 +               if ( (skb = dev_alloc_skb(SW_RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
5321 +               {
5322 +                       printk("%s::skb buffer allocation fail !\n",__func__); while(1);
5323 +               }
5324 +               REG32(skb->data) = (unsigned int)skb;
5325 +               skb_reserve(skb, SKB_RESERVE_BYTES);
5326 +               // toe->rx_skb[i] = skb;
5327 +               sw_desc_ptr->word2.buf_adr = (unsigned int)__pa(skb->data);
5328 +//             consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
5329 +               sw_desc_ptr++;
5330 +       }
5331 +
5332 +#ifdef CONFIG_SL351x_NAT
5333 +       if (sizeof(skb->cb) < 64)
5334 +       {
5335 +                       printk("==> %s:: sk structure is incorrect -->Change to cb[64] !\n",__func__); while(1);
5336 +       }
5337 +       // init hardware free queues
5338 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_HW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T)),
5339 +                                               (dma_addr_t *)&toe->hw_freeq_desc_base_dma) ;
5340 +       desc_ptr = (GMAC_RXDESC_T *)desc_buf;
5341 +       if (!desc_buf)
5342 +       {
5343 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5344 +               return;
5345 +       }
5346 +       memset((void *)desc_buf, 0, TOE_HW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
5347 +
5348 +       // DMA Queue Base & Size
5349 +       writel((toe->hw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_HW_FREEQ_DESC_POWER,
5350 +                       TOE_GLOBAL_BASE + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
5351 +
5352 +       // init descriptor base
5353 +       toe->hwfq_desc_base = desc_buf;
5354 +
5355 +       // HW Free Queue Read/Write Pointer
5356 +       rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
5357 +       rwptr_reg.bits.rptr = 0;
5358 +       writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
5359 +#ifndef HW_RXBUF_BY_KMALLOC
5360 +       buf_ptr = (unsigned int)DMA_MALLOC(TOE_HW_FREEQ_DESC_NUM * HW_RX_BUF_SIZE,
5361 +                                               (dma_addr_t *)&toe->hwfq_buf_base_dma);
5362 +#else
5363 +       buf_ptr = (unsigned int)kmalloc(TOE_HW_FREEQ_DESC_NUM * HW_RX_BUF_SIZE, GFP_KERNEL);
5364 +       toe->hwfq_buf_base_dma = __pa(buf_ptr);
5365 +#endif
5366 +       if (!buf_ptr)
5367 +       {
5368 +               printk("===> %s::Failed to allocate HW TxQ Buffers!\n",__func__);
5369 +               while(1);       // could not be happened, if happened, adjust the buffer descriptor number
5370 +               return;
5371 +       }
5372 +
5373 +       toe->hwfq_buf_base = buf_ptr;
5374 +       toe->hwfq_buf_end_dma = toe->hwfq_buf_base_dma + (TOE_HW_FREEQ_DESC_NUM * HW_RX_BUF_SIZE);
5375 +       buf_ptr = (unsigned int)toe->hwfq_buf_base_dma;
5376 +       for (i=0; i<TOE_HW_FREEQ_DESC_NUM; i++)
5377 +       {
5378 +               desc_ptr->word0.bits.buffer_size = HW_RX_BUF_SIZE;
5379 +               desc_ptr->word1.bits.sw_id = i;
5380 +               desc_ptr->word2.buf_adr = (unsigned int)buf_ptr;
5381 +//             consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
5382 +               // consistent_sync((unsigned int)buf_ptr, HW_RX_BUF_SIZE, PCI_DMA_TODEVICE);
5383 +               desc_ptr++;
5384 +               buf_ptr += HW_RX_BUF_SIZE;
5385 +       }
5386 +#else
5387 +       // DMA Queue Base & Size
5388 +       writel((0) | TOE_SW_FREEQ_DESC_POWER,
5389 +                       TOE_GLOBAL_BASE + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
5390 +       rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
5391 +       rwptr_reg.bits.rptr = 0;
5392 +       writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
5393 +
5394 +#endif
5395 +}
5396 +/*----------------------------------------------------------------------
5397 +*      toe_init_swtx_queue
5398 +*      (2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
5399 +*              GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
5400 +*      (2) Initialize DMA Read/Write pointer for
5401 +*              GMAC 0/1 SW TX Q0-5
5402 +*----------------------------------------------------------------------*/
5403 +static void toe_init_swtx_queue(void)
5404 +{
5405 +       int                             i;
5406 +       TOE_INFO_T                      *toe;
5407 +       DMA_RWPTR_T                     rwptr_reg;
5408 +       unsigned int            rwptr_addr;
5409 +       unsigned int            desc_buf;
5410 +
5411 +
5412 +       toe = (TOE_INFO_T *)&toe_private_data;
5413 +
5414 +       // GMAC-0, SW-TXQ
5415 +       // The GMAC-0 and GMAC-0 maybe have different descriptor number
5416 +       // so, not use for instruction
5417 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
5418 +                                               (dma_addr_t *)&toe->gmac[0].swtxq_desc_base_dma) ;
5419 +       toe->gmac[0].swtxq_desc_base = desc_buf;
5420 +       if (!desc_buf)
5421 +       {
5422 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5423 +               return  ;
5424 +       }
5425 +       memset((void *)desc_buf, 0,     TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
5426 +       writel((toe->gmac[0].swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC0_SWTXQ_DESC_POWER,
5427 +                       TOE_GMAC0_DMA_BASE+ GMAC_SW_TX_QUEUE_BASE_REG);
5428 +
5429 +       // GMAC0 SW TX Q0-Q5
5430 +       rwptr_reg.bits.wptr = 0;
5431 +       rwptr_reg.bits.rptr = 0;
5432 +       rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_SW_TX_QUEUE0_PTR_REG;
5433 +       for (i=0; i<TOE_SW_TXQ_NUM; i++)
5434 +       {
5435 +               toe->gmac[0].swtxq[i].rwptr_reg = rwptr_addr;
5436 +               toe->gmac[0].swtxq[i].desc_base = desc_buf;
5437 +               toe->gmac[0].swtxq[i].total_desc_num = TOE_GMAC0_SWTXQ_DESC_NUM;
5438 +               desc_buf += TOE_GMAC0_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
5439 +               writel(rwptr_reg.bits32, rwptr_addr);
5440 +               rwptr_addr+=4;
5441 +       }
5442 +
5443 +       // GMAC-1, SW-TXQ
5444 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC1_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
5445 +                                               (dma_addr_t *)&toe->gmac[1].swtxq_desc_base_dma) ;
5446 +       toe->gmac[1].swtxq_desc_base = desc_buf;
5447 +       if (!desc_buf)
5448 +       {
5449 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5450 +               return  ;
5451 +       }
5452 +       memset((void *)desc_buf, 0,     TOE_GMAC1_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
5453 +       writel((toe->gmac[1].swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC1_SWTXQ_DESC_POWER,
5454 +                       TOE_GMAC1_DMA_BASE+ GMAC_SW_TX_QUEUE_BASE_REG);
5455 +
5456 +
5457 +       // GMAC1 SW TX Q0-Q5
5458 +       rwptr_reg.bits.wptr = 0;
5459 +       rwptr_reg.bits.rptr = 0;
5460 +       rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_SW_TX_QUEUE0_PTR_REG;
5461 +       for (i=0; i<TOE_SW_TXQ_NUM; i++)
5462 +       {
5463 +               toe->gmac[1].swtxq[i].rwptr_reg = rwptr_addr;
5464 +               toe->gmac[1].swtxq[i].desc_base = desc_buf;
5465 +               toe->gmac[1].swtxq[i].total_desc_num = TOE_GMAC1_SWTXQ_DESC_NUM;
5466 +               desc_buf += TOE_GMAC1_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
5467 +               writel(rwptr_reg.bits32, rwptr_addr);
5468 +               rwptr_addr+=4;
5469 +       }
5470 +}
5471 +
5472 +/*----------------------------------------------------------------------
5473 +*      toe_init_hwtx_queue
5474 +*      (2) Initialize the GMAC 0/1 HW TXQ Queue Descriptor Base Address & size
5475 +*              GMAC_HW_TX_QUEUE_BASE_REG(0x0054)
5476 +*      (2) Initialize DMA Read/Write pointer for
5477 +*              GMAC 0/1 HW TX Q0-5
5478 +*----------------------------------------------------------------------*/
5479 +#ifdef CONFIG_SL351x_NAT
5480 +static void toe_init_hwtx_queue(void)
5481 +{
5482 +       int                             i;
5483 +       TOE_INFO_T                      *toe;
5484 +       DMA_RWPTR_T                     rwptr_reg;
5485 +       unsigned int            rwptr_addr;
5486 +       unsigned int            desc_buf;
5487 +
5488 +       toe = (TOE_INFO_T *)&toe_private_data;
5489 +       // GMAC-0, HW-TXQ
5490 +       // The GMAC-0 and GMAC-0 maybe have different descriptor number
5491 +       // so, not use for instruction
5492 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC0_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
5493 +                                               (dma_addr_t *)&toe->gmac[0].hwtxq_desc_base_dma) ;
5494 +       toe->gmac[0].hwtxq_desc_base = desc_buf;
5495 +       if (!desc_buf)
5496 +       {
5497 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5498 +               return  ;
5499 +       }
5500 +       memset((void *)desc_buf, 0,     TOE_GMAC0_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
5501 +       writel((toe->gmac[0].hwtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC0_HWTXQ_DESC_POWER,
5502 +                       TOE_GMAC0_DMA_BASE+ GMAC_HW_TX_QUEUE_BASE_REG);
5503 +
5504 +       // GMAC0 HW TX Q0-Q5
5505 +       rwptr_reg.bits.wptr = 0;
5506 +       rwptr_reg.bits.rptr = 0;
5507 +       rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
5508 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
5509 +       {
5510 +               toe->gmac[0].hwtxq[i].desc_base = desc_buf;
5511 +               desc_buf += TOE_GMAC0_HWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
5512 +               writel(rwptr_reg.bits32, rwptr_addr);
5513 +               rwptr_addr+=4;
5514 +       }
5515 +
5516 +       // GMAC-1, HW-TXQ
5517 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC1_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
5518 +                                               (dma_addr_t *)&toe->gmac[1].hwtxq_desc_base_dma) ;
5519 +       toe->gmac[1].hwtxq_desc_base = desc_buf;
5520 +       if (!desc_buf)
5521 +       {
5522 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5523 +               return  ;
5524 +       }
5525 +       memset((void *)desc_buf, 0,     TOE_GMAC1_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
5526 +       writel((toe->gmac[1].hwtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC1_HWTXQ_DESC_POWER,
5527 +                       TOE_GMAC1_DMA_BASE+ GMAC_HW_TX_QUEUE_BASE_REG);
5528 +
5529 +       // GMAC1 HW TX Q0-Q5
5530 +       rwptr_reg.bits.wptr = 0;
5531 +       rwptr_reg.bits.rptr = 0;
5532 +       rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
5533 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
5534 +       {
5535 +               toe->gmac[1].hwtxq[i].desc_base = desc_buf;
5536 +               desc_buf += TOE_GMAC1_HWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
5537 +               writel(rwptr_reg.bits32, rwptr_addr);
5538 +               rwptr_addr+=4;
5539 +       }
5540 +}
5541 +#endif
5542 +
5543 +/*----------------------------------------------------------------------
5544 +*      toe_init_default_queue
5545 +*      (1) Initialize the default 0/1 Queue Header
5546 +*              Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
5547 +*                                TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
5548 +*      (2)     Initialize Descriptors of Default Queue 0/1
5549 +*----------------------------------------------------------------------*/
5550 +static void toe_init_default_queue(void)
5551 +{
5552 +       TOE_INFO_T                              *toe;
5553 +       volatile NONTOE_QHDR_T  *qhdr;
5554 +       GMAC_RXDESC_T                   *desc_ptr;
5555 +       DMA_SKB_SIZE_T                  skb_size;
5556 +
5557 +       toe = (TOE_INFO_T *)&toe_private_data;
5558 +       desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T)),
5559 +                                                                                       (dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
5560 +       if (!desc_ptr)
5561 +       {
5562 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5563 +               return  ;
5564 +       }
5565 +       memset((void *)desc_ptr, 0, TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T));
5566 +       toe->gmac[0].default_desc_base = (unsigned int)desc_ptr;
5567 +       toe->gmac[0].default_desc_num = TOE_DEFAULT_Q0_DESC_NUM;
5568 +       qhdr = (volatile NONTOE_QHDR_T *)TOE_DEFAULT_Q0_HDR_BASE;
5569 +       qhdr->word0.base_size = ((unsigned int)toe->gmac[0].default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q0_DESC_POWER;
5570 +       qhdr->word1.bits32 = 0;
5571 +       toe->gmac[0].rx_rwptr.bits32 = 0;
5572 +       toe->gmac[0].default_qhdr = (NONTOE_QHDR_T *)qhdr;
5573 +       desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q1_DESC_NUM * sizeof(GMAC_RXDESC_T)),
5574 +                                                                                       (dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
5575 +       if (!desc_ptr)
5576 +       {
5577 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5578 +               return  ;
5579 +       }
5580 +       memset((void *)desc_ptr, 0, TOE_DEFAULT_Q1_DESC_NUM * sizeof(GMAC_RXDESC_T));
5581 +       toe->gmac[1].default_desc_base = (unsigned int)desc_ptr;
5582 +       toe->gmac[1].default_desc_num = TOE_DEFAULT_Q1_DESC_NUM;
5583 +       qhdr = (volatile NONTOE_QHDR_T *)TOE_DEFAULT_Q1_HDR_BASE;
5584 +       qhdr->word0.base_size = ((unsigned int)toe->gmac[1].default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q1_DESC_POWER;
5585 +       qhdr->word1.bits32 = 0;
5586 +       toe->gmac[1].rx_rwptr.bits32 = 0;
5587 +       toe->gmac[1].default_qhdr = (NONTOE_QHDR_T *)qhdr;
5588 +
5589 +       skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
5590 +       skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
5591 +       writel(skb_size.bits32, TOE_GLOBAL_BASE + GLOBAL_DMA_SKB_SIZE_REG);
5592 +}
5593 +
5594 +/*----------------------------------------------------------------------
5595 +*      toe_init_interrupt_queue
5596 +*      (1) Initialize the Interrupt Queue Header
5597 +*              Register: TOE_INTR_Q_HDR_BASE (0x60002080)
5598 +*      (2)     Initialize Descriptors of Interrupt Queues
5599 +*----------------------------------------------------------------------*/
5600 +#ifdef CONFIG_SL351x_RXTOE
5601 +static void toe_init_interrupt_queue(void)
5602 +{
5603 +       TOE_INFO_T                              *toe;
5604 +       volatile NONTOE_QHDR_T  *qhdr;
5605 +       INTR_QHDR_T                             *desc_ptr;
5606 +       // unsigned int                 desc_buf_addr;
5607 +       int                                             i;
5608 +
5609 +       toe = (TOE_INFO_T *)&toe_private_data;
5610 +       desc_ptr = (INTR_QHDR_T *)DMA_MALLOC((TOE_INTR_QUEUE_NUM * TOE_INTR_DESC_NUM * sizeof(INTR_QHDR_T)),
5611 +                                                                                       (dma_addr_t *)&toe->intr_desc_base_dma);
5612 +       if (!desc_ptr)
5613 +       {
5614 +               printk("%s::DMA_MALLOC interrupt queue fail !\n",__func__);
5615 +               return  ;
5616 +       }
5617 +       /*
5618 +       desc_buf_addr = (unsigned int)DMA_MALLOC((TOE_INTR_DESC_NUM * sizeof(TOE_QHDR_T)),
5619 +                                                                                               (dma_addr_t *)&toe->intr_buf_base_dma);
5620 +       if (!desc_buf_addr)
5621 +       {
5622 +               printk("%s::DMA_MALLOC interrupt desc fail !\n",__func__);
5623 +               return  ;
5624 +       }*/
5625 +       printk("#### %s::Intr Q desc %x\n", __func__, (u32)desc_ptr);
5626 +
5627 +       memset((void *)desc_ptr, 0, TOE_INTR_QUEUE_NUM * TOE_INTR_DESC_NUM * sizeof(INTR_QHDR_T));
5628 +//     memset((void *)desc_buf_addr, 0, TOE_INTR_DESC_NUM * sizeof(TOE_QHDR_T));
5629 +       toe->intr_desc_base = (unsigned int)desc_ptr;
5630 +       toe->intr_desc_num = TOE_INTR_DESC_NUM;
5631 +
5632 +       qhdr = (volatile NONTOE_QHDR_T *)TOE_INTR_Q_HDR_BASE;
5633 +//     intrq = (INTRQ_INFO_T*) &toe->intrq[0];
5634 +       for (i=0; i<TOE_INTR_QUEUE_NUM; i++, qhdr++)
5635 +       {
5636 +               qhdr->word0.base_size = ((unsigned int)toe->intr_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_INTR_DESC_POWER;
5637 +               qhdr->word1.bits32 = 0;
5638 +               desc_ptr += TOE_INTR_DESC_NUM;
5639 +       }
5640 +}
5641 +
5642 +#endif
5643 +
5644 +/*----------------------------------------------------------------------
5645 +*      toe_init_interrupt_config
5646 +*      Interrupt Select Registers are used to map interrupt to int0 or int1
5647 +*      Int0 and int1 are wired to CPU 0/1 GMAC 0/1
5648 +*      Interrupt Device Inteface data are used to pass device info to
5649 +*              upper device deiver or store status/statistics
5650 +*      ISR handler
5651 +*              (1) If status bit ON but masked, the prinf error message (bug issue)
5652 +*              (2) If select bits are for me, handle it, else skip to let
5653 +*                      the other ISR handles it.
5654 +*  Notes:
5655 +*              GMACx init routine (for eCOS) or open routine (for Linux)
5656 +*       enable the interrupt bits only which are selected for him.
5657 +*
5658 +*      Default Setting:
5659 +*              GMAC0 intr bits ------> int0 ----> eth0
5660 +*              GMAC1 intr bits ------> int1 ----> eth1
5661 +*              TOE intr -------------> int0 ----> eth0
5662 +*              Classification Intr --> int0 ----> eth0
5663 +*              Default Q0 -----------> int0 ----> eth0
5664 +*              Default Q1 -----------> int1 ----> eth1
5665 +*----------------------------------------------------------------------*/
5666 +static void toe_init_interrupt_config(void)
5667 +{
5668 +       // clear all status bits
5669 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
5670 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
5671 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
5672 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
5673 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
5674 +
5675 +       // Init select registers
5676 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
5677 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
5678 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
5679 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
5680 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
5681 +
5682 +       // disable all interrupt
5683 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_0_REG);
5684 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
5685 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_2_REG);
5686 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_3_REG);
5687 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
5688 +}
5689 +
5690 +/*----------------------------------------------------------------------
5691 +*      toe_init_gmac
5692 +*----------------------------------------------------------------------*/
5693 +static void toe_init_gmac(struct net_device *dev)
5694 +{
5695 +       GMAC_INFO_T             *tp = dev->priv;
5696 +       TOE_INFO_T              *toe;
5697 +       u32                     data;
5698 +
5699 +       if (!gmac_initialized)
5700 +               return ;
5701 +
5702 +       if (!tp->existed)
5703 +               return;
5704 +
5705 +       tp->dev = dev;
5706 +       tp->flow_control_enable = 1;
5707 +       tp->pre_phy_status = LINK_DOWN;
5708 +       tp->full_duplex_status = tp->full_duplex_cfg;
5709 +       tp->speed_status = tp->speed_status;
5710 +
5711 +#if 0
5712 +   /* get mac address from FLASH */
5713 +    gmac_get_mac_address();
5714 +#endif
5715 +
5716 +    /* set PHY register to start autonegition process */
5717 +    gmac_set_phy_status(dev);
5718 +
5719 +       /* GMAC initialization */
5720 +       if ( toe_gmac_init_chip(dev) )
5721 +       {
5722 +               printk ("GMAC %d init fail\n", tp->port_id);
5723 +       }
5724 +
5725 +    /* clear statistic counter */
5726 +    toe_gmac_clear_counter(dev);
5727 +
5728 +       memset((void *)&tp->ifStatics, 0, sizeof(struct net_device_stats));
5729 +
5730 +       /* -----------------------------------------------------------
5731 +       Enable GMAC interrupt & disable loopback
5732 +       Notes:
5733 +               GMACx init routine (for eCOS) or open routine (for Linux)
5734 +               enable the interrupt bits only which are selected for him.
5735 +       --------------------------------------------------------------*/
5736 +       toe = (TOE_INFO_T *)&toe_private_data;
5737 +
5738 +       // Enable Interrupt Bits
5739 +       if (tp->port_id == 0)
5740 +       {
5741 +               tp->intr0_selected =    GMAC0_TXDERR_INT_BIT     | GMAC0_TXPERR_INT_BIT         |
5742 +                                       GMAC0_RXDERR_INT_BIT     | GMAC0_RXPERR_INT_BIT         |
5743 +                                   GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
5744 +                                   GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
5745 +                                   GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
5746 +                                   GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
5747 +                                   GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
5748 +                                   GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
5749 +
5750 +#ifdef GMAX_TX_INTR_DISABLED
5751 +           tp->intr0_enabled =         0;
5752 +#else
5753 +           tp->intr0_enabled =         GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
5754 +#endif
5755 +
5756 +           tp->intr1_selected =        TOE_IQ_ALL_BITS                  | TOE_CLASS_RX_INT_BITS        |
5757 +                                                       GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
5758 +                                                       GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
5759 +                                                       DEFAULT_Q0_INT_BIT;
5760 +           tp->intr1_enabled =         DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
5761 +           tp->intr2_selected =        0xffffffff;      // TOE Queue 32-63 FUUL Intr
5762 +           tp->intr2_enabled =         0xffffffff;
5763 +           tp->intr3_selected =        0xffffffff;      // TOE Queue 0-31 FUUL Intr
5764 +           tp->intr3_enabled =         0xffffffff;
5765 +           tp->intr4_selected =        GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
5766 +                                                       HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
5767 +           tp->intr4_enabled =         GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
5768 +
5769 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
5770 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
5771 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG) & ~tp->intr1_selected;
5772 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
5773 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG) & ~tp->intr2_selected;
5774 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
5775 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG) & ~tp->intr3_selected;
5776 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
5777 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) & ~tp->intr4_selected;
5778 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
5779 +       }
5780 +       else
5781 +       {
5782 +               tp->intr0_selected =    GMAC1_TXDERR_INT_BIT     | GMAC1_TXPERR_INT_BIT         |
5783 +                                       GMAC1_RXDERR_INT_BIT     | GMAC1_RXPERR_INT_BIT         |
5784 +                                   GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
5785 +                                   GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
5786 +                                   GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
5787 +                                   GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
5788 +                                   GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
5789 +                                   GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
5790 +#ifdef GMAX_TX_INTR_DISABLED
5791 +           tp->intr0_enabled =         0;
5792 +#else
5793 +           tp->intr0_enabled =         GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
5794 +#endif
5795 +
5796 +           tp->intr1_selected =        DEFAULT_Q1_INT_BIT;
5797 +           tp->intr1_enabled =         DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
5798 +           tp->intr2_selected =        0;       // TOE Queue 32-63 FUUL Intr
5799 +           tp->intr2_enabled =         0;
5800 +           tp->intr3_selected =        0;       // TOE Queue 0-31 FUUL Intr
5801 +           tp->intr3_enabled =         0;
5802 +           tp->intr4_selected =        GMAC1_INT_BITS;
5803 +           tp->intr4_enabled =         GMAC1_INT_BITS;
5804 +
5805 +           if (toe->gmac[0].existed != GMAC_EXISTED_FLAG)
5806 +           {
5807 +               tp->intr1_selected      |=      TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS |
5808 +                                                               GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
5809 +                                                               GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT;
5810 +               tp->intr1_enabled       |=      TOE_IQ_ALL_BITS;
5811 +               tp->intr2_selected      |=      0xffffffff;      // TOE Queue 32-63 FUUL Intr
5812 +               tp->intr2_enabled       |=      0xffffffff;
5813 +               tp->intr3_selected      |=      0xffffffff;      // TOE Queue 0-31 FUUL Intr
5814 +               tp->intr3_enabled       |=      0xffffffff;
5815 +               tp->intr4_selected      |=      CLASS_RX_FULL_INT_BITS |
5816 +                                                               HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
5817 +               tp->intr4_enabled       |=      SWFQ_EMPTY_INT_BIT;
5818 +               }
5819 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) | tp->intr0_selected;
5820 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
5821 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG) | tp->intr1_selected;
5822 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
5823 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG) | tp->intr2_selected;
5824 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
5825 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG) | tp->intr3_selected;
5826 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
5827 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) | tp->intr4_selected;
5828 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
5829 +       }
5830 +
5831 +       // enable only selected bits
5832 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_0_REG,
5833 +                                       tp->intr0_enabled, tp->intr0_selected);
5834 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_1_REG,
5835 +                                       tp->intr1_enabled, tp->intr1_selected);
5836 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_2_REG,
5837 +                                       tp->intr2_enabled, tp->intr2_selected);
5838 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_3_REG,
5839 +                                       tp->intr3_enabled, tp->intr3_selected);
5840 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
5841 +                                       tp->intr4_enabled, tp->intr4_selected);
5842 +
5843 +    /* start DMA process */
5844 +       toe_gmac_hw_start(dev);
5845 +
5846 +    /* enable tx/rx register */
5847 +    toe_gmac_enable_tx_rx(dev);
5848 +
5849 +//     toe_gmac_enable_interrupt(tp->irq);
5850 +
5851 +    return ;
5852 +}
5853 +
5854 +
5855 +/*----------------------------------------------------------------------
5856 +* toe_gmac_sw_reset
5857 +*----------------------------------------------------------------------*/
5858 +static void toe_gmac_sw_reset(void)
5859 +{
5860 +       unsigned int    reg_val;
5861 +       reg_val = readl(GMAC_GLOBAL_BASE_ADDR+GLOBAL_RESET_REG) | 0x00000060;   /* GMAC0 S/W reset */
5862 +    writel(reg_val,GMAC_GLOBAL_BASE_ADDR+GLOBAL_RESET_REG);
5863 +    udelay(100);
5864 +    return;
5865 +}
5866 +
5867 +/*----------------------------------------------------------------------
5868 +*      toe_gmac_init_chip
5869 +*----------------------------------------------------------------------*/
5870 +static int toe_gmac_init_chip(struct net_device *dev)
5871 +{
5872 +       GMAC_INFO_T     *tp = dev->priv;
5873 +       GMAC_CONFIG2_T  config2_val;
5874 +       GMAC_CONFIG0_T  config0,config0_mask;
5875 +       GMAC_CONFIG1_T  config1;
5876 +       #ifdef CONFIG_SL351x_NAT
5877 +       GMAC_CONFIG3_T  config3_val;
5878 +       #endif
5879 +       GMAC_TX_WCR0_T  hw_weigh;
5880 +       GMAC_TX_WCR1_T  sw_weigh;
5881 +//     GMAC_HASH_ENABLE_REG0_T hash_ctrl;
5882 +//
5883 +#if 0 /* mac address will be set in late_initcall */
5884 +       struct sockaddr sock;
5885 +       // GMAC_AHB_WEIGHT_T    ahb_weight, ahb_weight_mask;
5886 +
5887 +
5888 +       /* set station MAC address1 and address2 */
5889 +       memcpy(&sock.sa_data[0],&eth_mac[tp->port_id][0],6);
5890 +       gmac_set_mac_address(dev,(void *)&sock);
5891 +#endif
5892 +
5893 +       /* set RX_FLTR register to receive all multicast packet */
5894 +       gmac_write_reg(tp->base_addr, GMAC_RX_FLTR, 0x00000007,0x0000001f);
5895 +       //    gmac_write_reg(tp->base_addr, GMAC_RX_FLTR, 0x00000007,0x0000001f);
5896 +       //gmac_write_reg(tp->base_addr, GMAC_RX_FLTR,0x00000007,0x0000001f);
5897 +
5898 +       /* set per packet buffer size */
5899 +       //      config1.bits32 = 0x002004;      //next version
5900 +       /* set flow control threshold */
5901 +       config1.bits32 = 0;
5902 +       config1.bits.set_threshold = 32 / 2;
5903 +       config1.bits.rel_threshold = 32 / 4 * 3;
5904 +       gmac_write_reg(tp->base_addr, GMAC_CONFIG1, config1.bits32, 0xffffffff);
5905 +
5906 +       /* set flow control threshold */
5907 +       config2_val.bits32 = 0;
5908 +       config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM/2;
5909 +       config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM*3/4;
5910 +       gmac_write_reg(tp->base_addr, GMAC_CONFIG2, config2_val.bits32,0xffffffff);
5911 +
5912 +       #ifdef CONFIG_SL351x_NAT
5913 +       /* set HW free queue flow control threshold */
5914 +       config3_val.bits32 = 0;
5915 +       config3_val.bits.set_threshold = PAUSE_SET_HW_FREEQ;
5916 +       config3_val.bits.rel_threshold = PAUSE_REL_HW_FREEQ;
5917 +       gmac_write_reg(tp->base_addr, GMAC_CONFIG3, config3_val.bits32,0xffffffff);
5918 +       #endif
5919 +       /* set_mcast_filter mask*/
5920 +       //      gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,0x0,0xffffffff);
5921 +       //  gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,0x0,0xffffffff);
5922 +
5923 +       /* disable TX/RX and disable internal loop back */
5924 +       config0.bits32 = 0;
5925 +       config0_mask.bits32 = 0;
5926 +
5927 +       //debug_Aaron
5928 +#ifdef L2_jumbo_frame
5929 +       config0.bits.max_len = 5;
5930 +#else
5931 +       config0.bits.max_len = 2;
5932 +#endif
5933 +
5934 +       if (tp->flow_control_enable==1)
5935 +       {
5936 +               config0.bits.tx_fc_en = 1; /* enable tx flow control */
5937 +               config0.bits.rx_fc_en = 1; /* enable rx flow control */
5938 +               printk("Enable MAC Flow Control...\n");
5939 +       }
5940 +       else
5941 +       {
5942 +               config0.bits.tx_fc_en = 0; /* disable tx flow control */
5943 +               config0.bits.rx_fc_en = 0; /* disable rx flow control */
5944 +               printk("Disable MAC Flow Control...\n");
5945 +       }
5946 +       config0.bits.dis_rx = 1;  /* disable rx */
5947 +       config0.bits.dis_tx = 1;  /* disable tx */
5948 +       config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
5949 +       config0.bits.rx_err_detect = 1;
5950 +       config0.bits.rgmii_en = 0;
5951 +       config0.bits.rgmm_edge = 1;
5952 +       config0.bits.rxc_inv = 0;
5953 +       config0.bits.ipv4_rx_chksum = 1;  /* enable H/W to check ip checksum */
5954 +       config0.bits.ipv6_rx_chksum = 1;  /* enable H/W to check ip checksum */
5955 +       config0.bits.port0_chk_hwq = 1; // GaryChen 3/24/2006 2:26PM
5956 +       config0.bits.port1_chk_hwq = 1; // GaryChen 3/24/2006 2:26PM
5957 +       config0.bits.port0_chk_toeq = 1;
5958 +       config0.bits.port1_chk_toeq = 1;
5959 +       config0.bits.port0_chk_classq = 1;
5960 +       config0.bits.port1_chk_classq = 1;
5961 +
5962 +       config0_mask.bits.max_len = 7;
5963 +       config0_mask.bits.tx_fc_en = 1;
5964 +       config0_mask.bits.rx_fc_en = 1;
5965 +       config0_mask.bits.dis_rx = 1;
5966 +       config0_mask.bits.dis_tx = 1;
5967 +       config0_mask.bits.loop_back = 1;
5968 +       config0_mask.bits.rgmii_en = 1;
5969 +       config0_mask.bits.rgmm_edge = 1;
5970 +       config0_mask.bits.rxc_inv = 1;
5971 +       config0_mask.bits.ipv4_rx_chksum = 1;
5972 +       config0_mask.bits.ipv6_rx_chksum = 1;
5973 +       config0_mask.bits.port0_chk_hwq = 1;
5974 +       config0_mask.bits.port1_chk_hwq = 1;
5975 +       config0_mask.bits.port0_chk_toeq = 1;
5976 +       config0_mask.bits.port1_chk_toeq = 1;
5977 +       config0_mask.bits.port0_chk_classq = 1;
5978 +       config0_mask.bits.port1_chk_classq = 1;
5979 +       config0_mask.bits.rx_err_detect = 1;
5980 +
5981 +       #if 0
5982 +       config0.bits.dis_rx = 1;  /* disable rx */
5983 +       config0.bits.dis_tx = 1;  /* disable tx */
5984 +       config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
5985 +       config0.bits.txc_inv = 0;
5986 +       config0.bits.rgmii_en = 0;
5987 +       config0.bits.rgmm_edge = 1;
5988 +       config0.bits.rxc_inv = 1;
5989 +       config0.bits.ipv4_tss_rx_en = 1;  /* enable H/W to check ip checksum */
5990 +       config0.bits.ipv6_tss_rx_en = 1;  /* enable H/W to check ip checksum */
5991 +
5992 +       config0_mask.bits.max_len = 3;
5993 +       config0_mask.bits.tx_fc_en = 1;
5994 +       config0_mask.bits.rx_fc_en = 1;
5995 +       config0_mask.bits.dis_rx = 1;
5996 +       config0_mask.bits.dis_tx = 1;
5997 +       config0_mask.bits.loop_back = 1;
5998 +       config0_mask.bits.rgmii_en = 1;
5999 +       config0_mask.bits.rgmm_edge = 1;
6000 +       config0_mask.bits.txc_inv = 1;
6001 +       config0_mask.bits.rxc_inv = 1;
6002 +       config0_mask.bits.ipv4_tss_rx_en = 1;
6003 +       config0_mask.bits.ipv6_tss_rx_en = 1;
6004 +       #endif
6005 +
6006 +       gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6007 +
6008 +       #if 1
6009 +       hw_weigh.bits32 = 0;
6010 +       hw_weigh.bits.hw_tq3 = 1;
6011 +       hw_weigh.bits.hw_tq2 = 1;
6012 +       hw_weigh.bits.hw_tq1 = 1;
6013 +       hw_weigh.bits.hw_tq0 = 1;
6014 +       gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_0_REG, hw_weigh.bits32, 0xffffffff);
6015 +
6016 +       sw_weigh.bits32 = 0;
6017 +       sw_weigh.bits.sw_tq5 = 1;
6018 +       sw_weigh.bits.sw_tq4 = 1;
6019 +       sw_weigh.bits.sw_tq3 = 1;
6020 +       sw_weigh.bits.sw_tq2 = 1;
6021 +       sw_weigh.bits.sw_tq1 = 1;
6022 +       sw_weigh.bits.sw_tq0 = 1;
6023 +       gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_1_REG, sw_weigh.bits32, 0xffffffff);
6024 +       #endif
6025 +
6026 +       #if 0
6027 +       ahb_weight.bits32 = 0;
6028 +       ahb_weight_mask.bits32 = 0;
6029 +       ahb_weight.bits.rx_weight = 1;
6030 +       ahb_weight.bits.tx_weight = 1;
6031 +       ahb_weight.bits.hash_weight = 1;
6032 +       ahb_weight.bits.pre_req = 0x1f;
6033 +       ahb_weight.bits.tqDV_threshold = 0;
6034 +       ahb_weight_mask.bits.rx_weight = 0x1f;
6035 +       ahb_weight_mask.bits.tx_weight = 0x1f;
6036 +       ahb_weight_mask.bits.hash_weight = 0x1f;
6037 +       ahb_weight_mask.bits.pre_req = 0x1f;
6038 +       ahb_weight_mask.bits.tqDV_threshold = 0x1f;
6039 +       gmac_write_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG, ahb_weight.bits32, ahb_weight_mask.bits32);
6040 +       #endif
6041 +
6042 +       #if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
6043 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR0, IPPROTO_TCP, 0xffffffff);
6044 +       #endif
6045 +       #ifdef CONFIG_SL351x_NAT
6046 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR1, IPPROTO_UDP, 0xffffffff);
6047 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR2, IPPROTO_GRE, 0xffffffff);
6048 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR3, 0xff, 0xffffffff);
6049 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR4, 0xff, 0xffffffff);
6050 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR5, 0xff, 0xffffffff);
6051 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR6, 0xff, 0xffffffff);
6052 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR7, 0xff, 0xffffffff);
6053 +
6054 +       sl351x_nat_init();
6055 +       #endif
6056 +
6057 +       #ifdef CONFIG_SL351x_RXTOE
6058 +       /* setup matching rule to TOE */
6059 +       sl351x_toe_init();
6060 +       #endif
6061 +
6062 +       // for A1 ASIC version
6063 +//     hash_ctrl.bits32 = 0;
6064 +//     hash_ctrl.bits.timing = 6;
6065 +//     gmac_write_reg(tp->dma_base_addr, GMAC_HASH_ENGINE_REG0, hash_ctrl.bits32, 0xffffffff);
6066 +
6067 +       return (0);
6068 +}
6069 +
6070 +/*----------------------------------------------------------------------
6071 +*      toe_gmac_enable_tx_rx
6072 +*----------------------------------------------------------------------*/
6073 +static void toe_gmac_enable_tx_rx(struct net_device *dev)
6074 +{
6075 +       GMAC_INFO_T             *tp = dev->priv;
6076 +       GMAC_CONFIG0_T  config0,config0_mask;
6077 +
6078 +    /* enable TX/RX */
6079 +    config0.bits32 = 0;
6080 +    config0_mask.bits32 = 0;
6081 +    config0.bits.dis_rx = 0;  /* enable rx */
6082 +    config0.bits.dis_tx = 0;  /* enable tx */
6083 +    config0_mask.bits.dis_rx = 1;
6084 +    config0_mask.bits.dis_tx = 1;
6085 +    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6086 +}
6087 +/*----------------------------------------------------------------------
6088 +*      toe_gmac_disable_rx
6089 +*----------------------------------------------------------------------*/
6090 +#if 0
6091 +static void toe_gmac_disable_rx(struct net_device *dev)
6092 +{
6093 +       GMAC_INFO_T             *tp = dev->priv;
6094 +       GMAC_CONFIG0_T  config0,config0_mask;
6095 +
6096 +    /* enable TX/RX */
6097 +    config0.bits32 = 0;
6098 +    config0_mask.bits32 = 0;
6099 +    config0.bits.dis_rx = 1;  /* disable rx */
6100 +//    config0.bits.dis_tx = 1;  /* disable tx */
6101 +    config0_mask.bits.dis_rx = 1;
6102 +//     config0_mask.bits.dis_tx = 1;
6103 +    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6104 +}
6105 +#endif
6106 +/*----------------------------------------------------------------------
6107 +*      toe_gmac_enable_rx
6108 +*----------------------------------------------------------------------*/
6109 +#if 0
6110 +static void toe_gmac_enable_rx(struct net_device *dev)
6111 +{
6112 +       GMAC_INFO_T             *tp = dev->priv;
6113 +       GMAC_CONFIG0_T  config0,config0_mask;
6114 +
6115 +    /* enable TX/RX */
6116 +    config0.bits32 = 0;
6117 +    config0_mask.bits32 = 0;
6118 +    config0.bits.dis_rx = 0;  /* enable rx */
6119 +//    config0.bits.dis_tx = 0;  /* enable tx */
6120 +    config0_mask.bits.dis_rx = 1;
6121 +//    config0_mask.bits.dis_tx = 1;
6122 +    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6123 +}
6124 +#endif
6125 +/*----------------------------------------------------------------------
6126 +*      toe_gmac_disable_tx_rx
6127 +*----------------------------------------------------------------------*/
6128 +static void toe_gmac_disable_tx_rx(struct net_device *dev)
6129 +{
6130 +       GMAC_INFO_T             *tp = dev->priv;
6131 +       GMAC_CONFIG0_T  config0,config0_mask;
6132 +
6133 +    /* enable TX/RX */
6134 +    config0.bits32 = 0;
6135 +    config0_mask.bits32 = 0;
6136 +    config0.bits.dis_rx = 1;  /* disable rx */
6137 +    config0.bits.dis_tx = 1;  /* disable tx */
6138 +    config0_mask.bits.dis_rx = 1;
6139 +    config0_mask.bits.dis_tx = 1;
6140 +    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6141 +}
6142 +
6143 +/*----------------------------------------------------------------------
6144 +*      toe_gmac_hw_start
6145 +*----------------------------------------------------------------------*/
6146 +static void toe_gmac_hw_start(struct net_device *dev)
6147 +{
6148 +       GMAC_INFO_T                             *tp = (GMAC_INFO_T *)dev->priv;
6149 +       GMAC_DMA_CTRL_T                 dma_ctrl, dma_ctrl_mask;
6150 +
6151 +
6152 +    /* program dma control register */
6153 +       dma_ctrl.bits32 = 0;
6154 +       dma_ctrl.bits.rd_enable = 1;
6155 +       dma_ctrl.bits.td_enable = 1;
6156 +       dma_ctrl.bits.loopback = 0;
6157 +       dma_ctrl.bits.drop_small_ack = 0;
6158 +       dma_ctrl.bits.rd_prot = 0;
6159 +       dma_ctrl.bits.rd_burst_size = 3;
6160 +       dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
6161 +       dma_ctrl.bits.rd_bus = 3;
6162 +       dma_ctrl.bits.td_prot = 0;
6163 +       dma_ctrl.bits.td_burst_size = 3;
6164 +       dma_ctrl.bits.td_bus = 3;
6165 +
6166 +       dma_ctrl_mask.bits32 = 0;
6167 +       dma_ctrl_mask.bits.rd_enable = 1;
6168 +       dma_ctrl_mask.bits.td_enable = 1;
6169 +       dma_ctrl_mask.bits.loopback = 1;
6170 +       dma_ctrl_mask.bits.drop_small_ack = 1;
6171 +       dma_ctrl_mask.bits.rd_prot = 3;
6172 +       dma_ctrl_mask.bits.rd_burst_size = 3;
6173 +       dma_ctrl_mask.bits.rd_insert_bytes = 3;
6174 +       dma_ctrl_mask.bits.rd_bus = 3;
6175 +       dma_ctrl_mask.bits.td_prot = 0x0f;
6176 +       dma_ctrl_mask.bits.td_burst_size = 3;
6177 +       dma_ctrl_mask.bits.td_bus = 3;
6178 +
6179 +       gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6180 +
6181 +    return;
6182 +}
6183 +
6184 +/*----------------------------------------------------------------------
6185 +*      toe_gmac_hw_stop
6186 +*----------------------------------------------------------------------*/
6187 +static void toe_gmac_hw_stop(struct net_device *dev)
6188 +{
6189 +       GMAC_INFO_T                     *tp = (GMAC_INFO_T *)dev->priv;
6190 +       GMAC_DMA_CTRL_T         dma_ctrl, dma_ctrl_mask;
6191 +
6192 +    /* program dma control register */
6193 +       dma_ctrl.bits32 = 0;
6194 +       dma_ctrl.bits.rd_enable = 0;
6195 +       dma_ctrl.bits.td_enable = 0;
6196 +
6197 +       dma_ctrl_mask.bits32 = 0;
6198 +       dma_ctrl_mask.bits.rd_enable = 1;
6199 +       dma_ctrl_mask.bits.td_enable = 1;
6200 +
6201 +       gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6202 +}
6203 +
6204 +/*----------------------------------------------------------------------
6205 +*      toe_gmac_clear_counter
6206 +*----------------------------------------------------------------------*/
6207 +static int toe_gmac_clear_counter (struct net_device *dev)
6208 +{
6209 +       GMAC_INFO_T     *tp = (GMAC_INFO_T *)dev->priv;
6210 +
6211 +    /* clear counter */
6212 +    gmac_read_reg(tp->base_addr, GMAC_IN_DISCARDS);
6213 +    gmac_read_reg(tp->base_addr, GMAC_IN_ERRORS);
6214 +    gmac_read_reg(tp->base_addr, GMAC_IN_MCAST);
6215 +    gmac_read_reg(tp->base_addr, GMAC_IN_BCAST);
6216 +    gmac_read_reg(tp->base_addr, GMAC_IN_MAC1);
6217 +    gmac_read_reg(tp->base_addr, GMAC_IN_MAC2);
6218 +               tp->ifStatics.tx_bytes = 0;
6219 +               tp->ifStatics.tx_packets = 0;
6220 +               tp->ifStatics.tx_errors = 0;
6221 +               tp->ifStatics.rx_bytes = 0;
6222 +               tp->ifStatics.rx_packets = 0;
6223 +               tp->ifStatics.rx_errors = 0;
6224 +               tp->ifStatics.rx_dropped = 0;
6225 +       return (0);
6226 +}
6227 +
6228 +
6229 +/*----------------------------------------------------------------------
6230 +*      toe_gmac_tx_complete
6231 +*----------------------------------------------------------------------*/
6232 +static  void toe_gmac_tx_complete(GMAC_INFO_T *tp, unsigned int tx_qid,
6233 +                                                                               struct net_device *dev, int interrupt)
6234 +{
6235 +       volatile GMAC_TXDESC_T  *curr_desc;
6236 +       GMAC_TXDESC_0_T                 word0;
6237 +       GMAC_TXDESC_1_T                 word1;
6238 +       unsigned int                    desc_count;
6239 +//     struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
6240 +       GMAC_SWTXQ_T                    *swtxq;
6241 +       DMA_RWPTR_T                             rwptr;
6242 +
6243 +       /* get tx H/W completed descriptor virtual address */
6244 +       /* check tx status and accumulate tx statistics */
6245 +       swtxq = &tp->swtxq[tx_qid];
6246 +       swtxq->intr_cnt++;
6247 +       for (;;)
6248 +       {
6249 +               rwptr.bits32 = readl(swtxq->rwptr_reg);
6250 +               if (rwptr.bits.rptr == swtxq->finished_idx)
6251 +                       break;
6252 +       curr_desc = (volatile GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
6253 +//             consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
6254 +               word0.bits32 = curr_desc->word0.bits32;
6255 +               word1.bits32 = curr_desc->word1.bits32;
6256 +
6257 +               if (word0.bits.status_tx_ok)
6258 +               {
6259 +                       tp->ifStatics.tx_bytes += word1.bits.byte_count;
6260 +                       desc_count = word0.bits.desc_count;
6261 +                       if (desc_count==0)
6262 +                       {
6263 +                               printk("%s::Desc 0x%x = 0x%x, desc_count=%d\n",__func__, (u32)curr_desc, word0.bits32, desc_count);
6264 +                               while(1);
6265 +                       }
6266 +                       while (--desc_count)
6267 +                       {
6268 +                               word0.bits.status_tx_ok = 0;
6269 +                               curr_desc->word0.bits32 = word0.bits32;
6270 +                               swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
6271 +                               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
6272 +                               word0.bits32 = curr_desc->word0.bits32;
6273 +#ifdef _DUMP_TX_TCP_CONTENT
6274 +                               if (curr_desc->word0.bits.buffer_size < 16)
6275 +                               {
6276 +                                       int a;
6277 +                                       char *datap;
6278 +                                       printk("\t Tx Finished Desc 0x%x Len %d Addr 0x%08x: ", (u32)curr_desc, curr_desc->word0.bits.buffer_size, curr_desc->word2.buf_adr);
6279 +                                       datap = (char *)__va(curr_desc->word2.buf_adr);
6280 +                                       for (a=0; a<8 && a<curr_desc->word0.bits.buffer_size; a++, datap++)
6281 +                                       {
6282 +                                               printk("0x%02x ", *datap);
6283 +                                       }
6284 +                                       printk("\n");
6285 +                               }
6286 +#endif
6287 +                       }
6288 +
6289 +                       word0.bits.status_tx_ok = 0;
6290 +                       if (swtxq->tx_skb[swtxq->finished_idx])
6291 +                       {
6292 +                               if (interrupt)
6293 +                                       dev_kfree_skb_irq(swtxq->tx_skb[swtxq->finished_idx]);
6294 +                               else
6295 +                                       dev_kfree_skb(swtxq->tx_skb[swtxq->finished_idx]);
6296 +                               swtxq->tx_skb[swtxq->finished_idx] = NULL;
6297 +                       }
6298 +                       curr_desc->word0.bits32 = word0.bits32;
6299 +                       swtxq->curr_finished_desc = (GMAC_TXDESC_T *)curr_desc;
6300 +                       swtxq->total_finished++;
6301 +                       tp->ifStatics.tx_packets++;
6302 +                       swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
6303 +               }
6304 +               else
6305 +               {
6306 +                       // tp->ifStatics.tx_errors++;
6307 +                       // printk("%s::Tx Descriptor is !!!\n",__func__);
6308 +                       // wait ready by breaking
6309 +                       break;
6310 +               }
6311 +       }
6312 +
6313 +       if (netif_queue_stopped(dev))
6314 +       {
6315 +               netif_wake_queue(dev);
6316 +       }
6317 +}
6318 +
6319 +/*----------------------------------------------------------------------
6320 +*      gmac_start_xmit
6321 +*----------------------------------------------------------------------*/
6322 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
6323 +{
6324 +       GMAC_INFO_T                     *tp= dev->priv;
6325 +//     static unsigned int     pcount = 0;
6326 +//     unsigned int                    tx_qid;
6327 +    DMA_RWPTR_T                                rwptr;
6328 +       volatile GMAC_TXDESC_T  *curr_desc;
6329 +       int                                     snd_pages = skb_shinfo(skb)->nr_frags + 1;  /* get number of descriptor */
6330 +       int                                     frag_id = 0;
6331 +       int                                     len, total_len = skb->len;
6332 +       struct net_device_stats *isPtr;
6333 +       unsigned int                    free_desc;
6334 +       GMAC_SWTXQ_T                    *swtxq;
6335 +       register unsigned long  word0, word1, word2, word3;
6336 +       unsigned short                  wptr, rptr;
6337 +#ifdef L2_jumbo_frame
6338 +       int header_len = skb->len;
6339 +       struct iphdr    *ip_hdr;
6340 +    struct tcphdr      *tcp_hdr;
6341 +    int             tcp_hdr_len;
6342 +    unsigned char      *ptr;
6343 +    int             data_len,a;
6344 +    unsigned int    val;
6345 +#endif
6346 +
6347 +#ifdef GMAC_LEN_1_2_ISSUE
6348 +       int                                             total_pages;
6349 +       total_pages = snd_pages;
6350 +#endif
6351 +
6352 +       isPtr = (struct net_device_stats *)&tp->ifStatics;
6353 +#if 1
6354 +       if (skb->len >= 0x10000)
6355 +       {
6356 +//             spin_unlock(&tp->tx_mutex);
6357 +               isPtr->tx_dropped++;
6358 +               printk("%s::[GMAC %d] skb->len %d >= 64K\n", __func__, tp->port_id, skb->len);
6359 +               netif_stop_queue(dev);
6360 +               return 1;
6361 +    }
6362 +#endif
6363 +
6364 +#if 0
6365 +       if (storlink_ctl.recvfile==2)
6366 +       {
6367 +           printk("snd_pages=%d skb->len=%d\n",snd_pages,skb->len);
6368 +       }
6369 +#endif
6370 +
6371 +#ifdef GMAC_USE_TXQ0
6372 +       #define tx_qid  0
6373 +#endif
6374 +
6375 +       swtxq = &tp->swtxq[tx_qid];
6376 +
6377 +//     spin_lock(&tp->tx_mutex);
6378 +    rwptr.bits32 = readl(swtxq->rwptr_reg);
6379 +       wptr = rwptr.bits.wptr;
6380 +       rptr = rwptr.bits.rptr;
6381 +
6382 +       // check finished desc or empty BD
6383 +       // cannot check by read ptr of RW PTR register,
6384 +       // because the HW complete to send but the SW may NOT handle it
6385 +#ifndef        GMAX_TX_INTR_DISABLED
6386 +       if (wptr >= swtxq->finished_idx)
6387 +               free_desc = swtxq->total_desc_num - wptr - 1 + swtxq->finished_idx;
6388 +       else
6389 +               free_desc = swtxq->finished_idx - wptr - 1;
6390 +
6391 +       if (free_desc < snd_pages)
6392 +       {
6393 +//             spin_unlock(&tp->tx_mutex);
6394 +               isPtr->tx_dropped++;
6395 +//             printk("GMAC %d No available descriptor!\n", tp->port_id);
6396 +               netif_stop_queue(dev);
6397 +               return 1;
6398 +    }
6399 +#else
6400 +       toe_gmac_tx_complete(tp, tx_qid, dev, 0);
6401 +
6402 +       if (wptr >= swtxq->finished_idx)
6403 +               free_desc = swtxq->total_desc_num - wptr - 1 + swtxq->finished_idx;
6404 +       else
6405 +               free_desc = swtxq->finished_idx - wptr - 1;
6406 +       if (free_desc < snd_pages)
6407 +       {
6408 +//             spin_unlock(&tp->tx_mutex);
6409 +               isPtr->tx_dropped++;
6410 +//             printk("GMAC %d No available descriptor!\n", tp->port_id);
6411 +               netif_stop_queue(dev);
6412 +               return 1;
6413 +    }
6414 +
6415 +#if 0
6416 +       printk("1: free_desc=%d, wptr=%d, finished_idx=%d\n", free_desc, wptr, swtxq->finished_idx);
6417 +       if ((free_desc < (snd_pages << 2)) ||
6418 +           (free_desc < (swtxq->total_desc_num >> 2)))
6419 +       {
6420 +               printk("2: free_desc = %d\n", free_desc);
6421 +               toe_gmac_tx_complete(tp, tx_qid, dev, 0);
6422 +               rwptr.bits32 = readl(swtxq->rwptr_reg);
6423 +               wptr = rwptr.bits.wptr;
6424 +               if (wptr>= swtxq->finished_idx)
6425 +                       free_desc = swtxq->total_desc_num - wptr -1 + swtxq->finished_idx;
6426 +               else
6427 +                       free_desc = swtxq->finished_idx - wptr - 1;
6428 +       }
6429 +#endif
6430 +#endif
6431 +
6432 +#ifdef L2_jumbo_frame
6433 +//             data_len = skb->len - 14 - ip_hdr->ihl *4 - tcp_hdr_len;
6434 +//             if ((skb->nh.iph->protocol == __constant_htons(ETH_P_IP)) && ((skb->nh.iph->protocol & 0x00ff)  == IPPROTO_TCP))
6435 +//             if (skb->nh.iph->protocol == 0x006 && (skb->nh.iph->protocol == __constant_htons(ETH_P_IP)))
6436 +               if (((skb->nh.iph->protocol & 0x00ff)  == IPPROTO_TCP))
6437 +               {
6438 +                               ip_hdr = (struct iphdr*)(skb->nh.iph);
6439 +                               tcp_hdr = (struct tcphdr*)(skb->h.th);
6440 +                               tcp_hdr_len = TCPHDRLEN(tcp_hdr) * 4;
6441 +                               tcp_hdr_len = TCPHDRLEN(tcp_hdr) * 4;
6442 +
6443 +                               if ((skb->h.th->syn) && (tcp_hdr_len > 20))
6444 +                               {
6445 +                                       ptr = (unsigned char *)(tcp_hdr+1);
6446 +                                       if ((ptr[0] == 0x02) && (ptr[1] == 0x04) && (ptr[2] == 0x07) && (ptr[3] == 0xba)) // 0x07 aa=2016-54=1962  ,0x07ba=2032-54=1978
6447 +                                       {
6448 +                                               ptr[2]=0x20;    //23
6449 +                                               ptr[3]=0x00;    //00
6450 +                                               printk("-----> Change MSS to 8K \n" );
6451 +                                       }
6452 +                               }
6453 +               }
6454 +//             if ((ip_hdr->protocol & 0x00ff) != IPPROTO_TCP)
6455 +//             if ((tcp_hdr_len > 20) && (skb->h.th->syn))
6456 +#endif
6457 +
6458 +
6459 +#if 0
6460 +       if (snd_pages > 1)
6461 +               printk("-----> snd_pages=%d\n", snd_pages);
6462 +       if (total_len > 1514)
6463 +       {
6464 +               printk("-----> total_len=%d\n", total_len);
6465 +       }
6466 +#endif
6467 +
6468 +    while (snd_pages)
6469 +    {
6470 +       char *pkt_datap;
6471 +
6472 +       curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
6473 +//             consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
6474 +#if 0
6475 +//#if (GMAC_DEBUG==1)
6476 +       // if curr_desc->word2.buf_adr !=0 means that the ISR does NOT handle it
6477 +       // if (curr_desc->word2.buf_adr)
6478 +       if (swtxq->tx_skb[wptr])
6479 +       {
6480 +               printk("Error! Stop due to TX descriptor's buffer is not freed!\n");
6481 +               while(1);
6482 +               dev_kfree_skb(swtxq->tx_skb[wptr]);
6483 +               swtxq->tx_skb[wptr] = NULL;
6484 +               }
6485 +#endif
6486 +
6487 +               if (frag_id == 0)
6488 +               {
6489 +#if 0
6490 +                       int i;
6491 +                       pkt_datap = skb->data;
6492 +                       len = total_len;
6493 +                       for (i=0; i<skb_shinfo(skb)->nr_frags; i++)
6494 +                       {
6495 +                               skb_frag_t* frag = &skb_shinfo(skb)->frags[i];
6496 +                               len -= frag->size;
6497 +                       }
6498 +#else
6499 +                       pkt_datap = skb->data;
6500 +                       len = total_len - skb->data_len;
6501 +#endif
6502 +               }
6503 +               else
6504 +               {
6505 +                       skb_frag_t* frag = &skb_shinfo(skb)->frags[frag_id-1];
6506 +                       pkt_datap = page_address(frag->page) + frag->page_offset;
6507 +                       len = frag->size;
6508 +                       if (len > total_len)
6509 +                       {
6510 +                               printk("===> Fatal Error! Send Frag size %d > Total Size %d!!!!!\n",
6511 +                                       len, total_len);
6512 +                       }
6513 +               }
6514 +
6515 +               /* set TX descriptor */
6516 +               /* copy packet to descriptor buffer address */
6517 +               // curr_desc->word0.bits32 = len;    /* total frame byte count */
6518 +               word0 = len;
6519 +#ifdef L2_jumbo_frame
6520 +               word3 = (dev->mtu+14) | EOFIE_BIT;  //2016 ,2032
6521 +#else
6522 +               word3 = 1514 | EOFIE_BIT;
6523 +#endif
6524 +
6525 +#ifdef DO_HW_CHKSUM
6526 +#ifdef L2_jumbo_frame
6527 +               if (total_len >= (dev->mtu+14) && (skb->nh.iph->protocol == 0x011) && skb->nh.iph && (skb->nh.iph->frag_off & __constant_htons(0x3fff)))
6528 +#else
6529 +               if (total_len <= 1514 && ip_hdr(skb) && (ip_hdr(skb)->frag_off & __constant_htons(0x3fff)))
6530 +#endif
6531 +                       word1  = total_len |
6532 +                                       TSS_IP_CHKSUM_BIT  |
6533 +                                       TSS_IPV6_ENABLE_BIT |
6534 +                                       TSS_MTU_ENABLE_BIT;
6535 +               else
6536 +                       word1 = total_len |
6537 +                                       TSS_UDP_CHKSUM_BIT |
6538 +                                       TSS_TCP_CHKSUM_BIT |
6539 +                                       TSS_IP_CHKSUM_BIT  |
6540 +                                       TSS_IPV6_ENABLE_BIT |
6541 +                                       TSS_MTU_ENABLE_BIT;
6542 +#else
6543 +               word1 = total_len | TSS_MTU_ENABLE_BIT;
6544 +#endif
6545 +               word2 = (unsigned long)__pa(pkt_datap);
6546 +
6547 +               if (frag_id == 0)
6548 +               {
6549 +                       word3 |= SOF_BIT;       // SOF
6550 +               }
6551 +
6552 +               if (snd_pages == 1)
6553 +               {
6554 +                       word3 |= EOF_BIT;       // EOF
6555 +                       swtxq->tx_skb[wptr] = skb;
6556 +#ifdef CONFIG_SL351x_NAT
6557 +                       if (nat_cfg.enabled && sl351x_nat_output(skb, tp->port_id))
6558 +                               word1 |= TSS_IP_FIXED_LEN_BIT;
6559 +#endif
6560 +               }
6561 +               else
6562 +                       swtxq->tx_skb[wptr] = NULL;
6563 +               // word1 |= TSS_IP_FIXED_LEN_BIT;
6564 +#if 1
6565 +#ifdef CONFIG_SL351x_RXTOE
6566 +               // check if this frame has the mission to enable toe hash entry..
6567 +               // if rx_max_pktsize ==0, do not enable RXTOE
6568 +               if (TCP_SKB_CB(skb)->connection && storlink_ctl.rx_max_pktsize) {
6569 +                       set_toeq_hdr(TCP_SKB_CB(skb)->connection, &toe_private_data, dev);
6570 +               }
6571 +#endif
6572 +#endif
6573 +#ifdef _DUMP_TX_TCP_CONTENT
6574 +               if (len < 16 && frag_id && skb->h.th && (skb->h.th->source == __constant_htons(445) || skb->h.th->source == __constant_htons(139)))
6575 +               {
6576 +                       int a;
6577 +                       char *datap;
6578 +                       printk("Tx Desc 0x%x Frag %d Len %d [IP-ID 0x%x] 0x%08x: ", (u32)curr_desc, frag_id, len, htons(skb->nh.iph->id), (u32)pkt_datap);
6579 +                       datap = (char *)pkt_datap;
6580 +                       for (a=0; a<8 && a<len; a++, datap++)
6581 +                       {
6582 +                               printk("0x%02x ", *datap);
6583 +                       }
6584 +                       printk("\n");
6585 +               }
6586 +#endif
6587 +
6588 +#ifdef GMAC_LEN_1_2_ISSUE
6589 +               if ((total_pages!=snd_pages) && (len == 1 || len == 2 ) && ((u32)pkt_datap & 0x03))
6590 +               {
6591 +                       memcpy((void *)&_debug_prefetch_buf[_debug_prefetch_cnt][0], pkt_datap, len);
6592 +                       pkt_datap = (char *)&_debug_prefetch_buf[_debug_prefetch_cnt][0];
6593 +                       word2 = (unsigned long)__pa(pkt_datap);
6594 +                       _debug_prefetch_cnt++;
6595 +                       if (_debug_prefetch_cnt >= _DEBUG_PREFETCH_NUM)
6596 +                               _debug_prefetch_cnt = 0;
6597 +               }
6598 +#endif
6599 +
6600 +               consistent_sync((void *)pkt_datap, len, PCI_DMA_TODEVICE);
6601 +               wmb();
6602 +               curr_desc->word0.bits32 = word0;
6603 +               curr_desc->word1.bits32 = word1;
6604 +               curr_desc->word2.bits32 = word2;
6605 +               curr_desc->word3.bits32 = word3;
6606 +               swtxq->curr_tx_desc = (GMAC_TXDESC_T *)curr_desc;
6607 +//             consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_TODEVICE);
6608 +#ifdef _DUMP_TX_TCP_CONTENT
6609 +               if (len < 16 && frag_id && skb->h.th && (skb->h.th->source == __constant_htons(445) || skb->h.th->source == __constant_htons(139)))
6610 +               {
6611 +                       int a;
6612 +                       char *datap;
6613 +                       printk("\t 0x%08x: ", (u32)pkt_datap);
6614 +                       datap = (char *)pkt_datap;
6615 +                       for (a=0; a<8 && a<len; a++, datap++)
6616 +                       {
6617 +                               printk("0x%02x ", *datap);
6618 +                       }
6619 +                       printk("\n");
6620 +               }
6621 +#endif
6622 +               free_desc--;
6623 +               wmb();
6624 +               wptr = RWPTR_ADVANCE_ONE(wptr, swtxq->total_desc_num);
6625 +               frag_id++;
6626 +               snd_pages--;
6627 +       }
6628 +
6629 +    swtxq->total_sent++;
6630 +       SET_WPTR(swtxq->rwptr_reg, wptr);
6631 +       dev->trans_start = jiffies;
6632 +
6633 +
6634 +       // printk("MAC %d Qid %d rwptr = 0x%x, curr_desc=0x%x\n", skb->tx_port_id, tx_qid, rwptr.bits32, curr_desc);
6635 +//#ifdef       GMAX_TX_INTR_DISABLED
6636 +//             toe_gmac_tx_complete(tp, tx_qid, dev, 0);
6637 +//#endif
6638 +       return (0);
6639 +}
6640 +
6641 +/*----------------------------------------------------------------------
6642 +* gmac_set_mac_address
6643 +*----------------------------------------------------------------------*/
6644 +
6645 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
6646 +{
6647 +       GMAC_INFO_T             *tp= dev->priv;
6648 +       struct sockaddr *sock;
6649 +       unsigned int    reg_val;
6650 +    unsigned int    i;
6651 +
6652 +       sock = (struct sockaddr *) addr;
6653 +       for (i = 0; i < 6; i++)
6654 +       {
6655 +               dev->dev_addr[i] = sock->sa_data[i];
6656 +       }
6657 +
6658 +    reg_val = dev->dev_addr[0] + (dev->dev_addr[1]<<8) + (dev->dev_addr[2]<<16) + (dev->dev_addr[3]<<24);
6659 +    gmac_write_reg(tp->base_addr,GMAC_STA_ADD0,reg_val,0xffffffff);
6660 +    reg_val = dev->dev_addr[4] + (dev->dev_addr[5]<<8);
6661 +    gmac_write_reg(tp->base_addr,GMAC_STA_ADD1,reg_val,0x0000ffff);
6662 +       memcpy(&eth_mac[tp->port_id][0],&dev->dev_addr[0],6);
6663 +
6664 +    printk("Storlink %s address = ",dev->name);
6665 +    printk("%02x",dev->dev_addr[0]);
6666 +    printk("%02x",dev->dev_addr[1]);
6667 +    printk("%02x",dev->dev_addr[2]);
6668 +    printk("%02x",dev->dev_addr[3]);
6669 +    printk("%02x",dev->dev_addr[4]);
6670 +    printk("%02x\n",dev->dev_addr[5]);
6671 +
6672 +    return (0);
6673 +}
6674 +
6675 +/*----------------------------------------------------------------------
6676 +* gmac_get_mac_address
6677 +*      get mac address from FLASH
6678 +*----------------------------------------------------------------------*/
6679 +static void gmac_get_mac_address(void)
6680 +{
6681 +#ifdef CONFIG_MTD
6682 +       extern int get_vlaninfo(vlaninfo* vlan);
6683 +    static vlaninfo    vlan[2];
6684 +
6685 +    if (get_vlaninfo(&vlan[0]))
6686 +    {
6687 +        memcpy((void *)&eth_mac[0][0],vlan[0].mac,6);
6688 +        // VLAN_conf[0].vid = vlan[0].vlanid;
6689 +        // VLAN_conf[0].portmap = vlan[0].vlanmap;
6690 +        memcpy((void *)&eth_mac[1][0],vlan[1].mac,6);
6691 +        // VLAN_conf[1].vid = vlan[1].vlanid;
6692 +        // VLAN_conf[1].portmap = vlan[1].vlanmap;
6693 +    }
6694 +#else
6695 +    unsigned int reg_val;
6696 +
6697 +    reg_val = readl(IO_ADDRESS(TOE_GMAC0_BASE)+0xac);
6698 +    eth_mac[0][4] = (reg_val & 0xff00) >> 8;
6699 +    eth_mac[0][5] = reg_val & 0x00ff;
6700 +    reg_val = readl(IO_ADDRESS(SL2312_SECURITY_BASE)+0xac);
6701 +    eth_mac[1][4] = (reg_val & 0xff00) >> 8;
6702 +    eth_mac[1][5] = reg_val & 0x00ff;
6703 +#endif
6704 +    return;
6705 +}
6706 +
6707 +
6708 +/*----------------------------------------------------------------------
6709 +* mac_stop_txdma
6710 +*----------------------------------------------------------------------*/
6711 +void mac_stop_txdma(struct net_device *dev)
6712 +{
6713 +       GMAC_INFO_T                             *tp = (GMAC_INFO_T *)dev->priv;
6714 +       GMAC_DMA_CTRL_T                 dma_ctrl, dma_ctrl_mask;
6715 +       GMAC_TXDMA_FIRST_DESC_T txdma_busy;
6716 +
6717 +       // wait idle
6718 +       do
6719 +       {
6720 +               txdma_busy.bits32 = gmac_read_reg(tp->dma_base_addr, GMAC_DMA_TX_FIRST_DESC_REG);
6721 +       } while (txdma_busy.bits.td_busy);
6722 +
6723 +    /* program dma control register */
6724 +       dma_ctrl.bits32 = 0;
6725 +       dma_ctrl.bits.rd_enable = 0;
6726 +       dma_ctrl.bits.td_enable = 0;
6727 +
6728 +       dma_ctrl_mask.bits32 = 0;
6729 +       dma_ctrl_mask.bits.rd_enable = 1;
6730 +       dma_ctrl_mask.bits.td_enable = 1;
6731 +
6732 +       gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6733 +}
6734 +
6735 +/*----------------------------------------------------------------------
6736 +* mac_start_txdma
6737 +*----------------------------------------------------------------------*/
6738 +void mac_start_txdma(struct net_device *dev)
6739 +{
6740 +       GMAC_INFO_T                     *tp = (GMAC_INFO_T *)dev->priv;
6741 +       GMAC_DMA_CTRL_T         dma_ctrl, dma_ctrl_mask;
6742 +
6743 +    /* program dma control register */
6744 +       dma_ctrl.bits32 = 0;
6745 +       dma_ctrl.bits.rd_enable = 1;
6746 +       dma_ctrl.bits.td_enable = 1;
6747 +
6748 +       dma_ctrl_mask.bits32 = 0;
6749 +       dma_ctrl_mask.bits.rd_enable = 1;
6750 +       dma_ctrl_mask.bits.td_enable = 1;
6751 +
6752 +       gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6753 +}
6754 +
6755 +
6756 +/*----------------------------------------------------------------------
6757 +* gmac_get_stats
6758 +*----------------------------------------------------------------------*/
6759 +
6760 +struct net_device_stats * gmac_get_stats(struct net_device *dev)
6761 +{
6762 +    GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
6763 +    // unsigned int        flags;
6764 +    unsigned int        pkt_drop;
6765 +    unsigned int        pkt_error;
6766 +
6767 +    if (netif_running(dev))
6768 +    {
6769 +        /* read H/W counter */
6770 +        // spin_lock_irqsave(&tp->lock,flags);
6771 +        pkt_drop = gmac_read_reg(tp->base_addr,GMAC_IN_DISCARDS);
6772 +        pkt_error = gmac_read_reg(tp->base_addr,GMAC_IN_ERRORS);
6773 +        tp->ifStatics.rx_dropped = tp->ifStatics.rx_dropped + pkt_drop;
6774 +        tp->ifStatics.rx_errors = tp->ifStatics.rx_errors + pkt_error;
6775 +        // spin_unlock_irqrestore(&tp->lock,flags);
6776 +    }
6777 +    return &tp->ifStatics;
6778 +}
6779 +
6780 +
6781 +
6782 +/*----------------------------------------------------------------------
6783 +* mac_get_sw_tx_weight
6784 +*----------------------------------------------------------------------*/
6785 +void mac_get_sw_tx_weight(struct net_device *dev, char *weight)
6786 +{
6787 +       GMAC_TX_WCR1_T  sw_weigh;
6788 +    GMAC_INFO_T                *tp = (GMAC_INFO_T *)dev->priv;
6789 +
6790 +       sw_weigh.bits32 = gmac_read_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_1_REG);
6791 +
6792 +       weight[0] = sw_weigh.bits.sw_tq0;
6793 +       weight[1] = sw_weigh.bits.sw_tq1;
6794 +       weight[2] = sw_weigh.bits.sw_tq2;
6795 +       weight[3] = sw_weigh.bits.sw_tq3;
6796 +       weight[4] = sw_weigh.bits.sw_tq4;
6797 +       weight[5] = sw_weigh.bits.sw_tq5;
6798 +}
6799 +
6800 +/*----------------------------------------------------------------------
6801 +* mac_set_sw_tx_weight
6802 +*----------------------------------------------------------------------*/
6803 +void mac_set_sw_tx_weight(struct net_device *dev, char *weight)
6804 +{
6805 +       GMAC_TX_WCR1_T  sw_weigh;
6806 +    GMAC_INFO_T                *tp = (GMAC_INFO_T *)dev->priv;
6807 +
6808 +       sw_weigh.bits32 = 0;
6809 +       sw_weigh.bits.sw_tq0 = weight[0];
6810 +       sw_weigh.bits.sw_tq1 = weight[1];
6811 +       sw_weigh.bits.sw_tq2 = weight[2];
6812 +       sw_weigh.bits.sw_tq3 = weight[3];
6813 +       sw_weigh.bits.sw_tq4 = weight[4];
6814 +       sw_weigh.bits.sw_tq5 = weight[5];
6815 +
6816 +       gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_1_REG, sw_weigh.bits32, 0xffffffff);
6817 +}
6818 +
6819 +/*----------------------------------------------------------------------
6820 +* mac_get_hw_tx_weight
6821 +*----------------------------------------------------------------------*/
6822 +void mac_get_hw_tx_weight(struct net_device *dev, char *weight)
6823 +{
6824 +       GMAC_TX_WCR0_T  hw_weigh;
6825 +    GMAC_INFO_T                *tp = (GMAC_INFO_T *)dev->priv;
6826 +
6827 +       hw_weigh.bits32 = gmac_read_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_0_REG);
6828 +
6829 +       weight[0] = hw_weigh.bits.hw_tq0;
6830 +       weight[1] = hw_weigh.bits.hw_tq1;
6831 +       weight[2] = hw_weigh.bits.hw_tq2;
6832 +       weight[3] = hw_weigh.bits.hw_tq3;
6833 +}
6834 +
6835 +/*----------------------------------------------------------------------
6836 +* mac_set_hw_tx_weight
6837 +*----------------------------------------------------------------------*/
6838 +void mac_set_hw_tx_weight(struct net_device *dev, char *weight)
6839 +{
6840 +       GMAC_TX_WCR0_T  hw_weigh;
6841 +    GMAC_INFO_T                *tp = (GMAC_INFO_T *)dev->priv;
6842 +
6843 +       hw_weigh.bits32 = 0;
6844 +       hw_weigh.bits.hw_tq0 = weight[0];
6845 +       hw_weigh.bits.hw_tq1 = weight[1];
6846 +       hw_weigh.bits.hw_tq2 = weight[2];
6847 +       hw_weigh.bits.hw_tq3 = weight[3];
6848 +
6849 +       gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_0_REG, hw_weigh.bits32, 0xffffffff);
6850 +}
6851 +
6852 +/*----------------------------------------------------------------------
6853 +* mac_start_tx_dma
6854 +*----------------------------------------------------------------------*/
6855 +int mac_start_tx_dma(int mac)
6856 +{
6857 +       GMAC_DMA_CTRL_T dma_ctrl, dma_ctrl_mask;
6858 +
6859 +       dma_ctrl.bits32 = 0;
6860 +       dma_ctrl.bits.td_enable = 1;
6861 +
6862 +       dma_ctrl_mask.bits32 = 0;
6863 +       dma_ctrl_mask.bits.td_enable = 1;
6864 +
6865 +       if (mac == 0)
6866 +       gmac_write_reg(TOE_GMAC0_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6867 +       else
6868 +       gmac_write_reg(TOE_GMAC1_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6869 +       return  1;
6870 +}
6871 +
6872 +/*----------------------------------------------------------------------
6873 +* mac_stop_tx_dma
6874 +*----------------------------------------------------------------------*/
6875 +int mac_stop_tx_dma(int mac)
6876 +{
6877 +       GMAC_DMA_CTRL_T dma_ctrl, dma_ctrl_mask;
6878 +
6879 +       dma_ctrl.bits32 = 0;
6880 +       dma_ctrl.bits.td_enable = 0;
6881 +
6882 +       dma_ctrl_mask.bits32 = 0;
6883 +       dma_ctrl_mask.bits.td_enable = 1;
6884 +
6885 +       if (mac == 0)
6886 +       gmac_write_reg(TOE_GMAC0_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6887 +       else
6888 +       gmac_write_reg(TOE_GMAC1_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6889 +       return  1;
6890 +}
6891 +
6892 +/*----------------------------------------------------------------------
6893 +* mac_read_reg(int mac, unsigned int offset)
6894 +*----------------------------------------------------------------------*/
6895 +unsigned int mac_read_reg(int mac, unsigned int offset)
6896 +{
6897 +       switch (mac)
6898 +       {
6899 +               case 0:
6900 +                       return gmac_read_reg(TOE_GMAC0_BASE, offset);
6901 +               case 1:
6902 +                       return gmac_read_reg(TOE_GMAC1_BASE, offset);
6903 +               default:
6904 +                       return 0;
6905 +       }
6906 +}
6907 +
6908 +/*----------------------------------------------------------------------
6909 +* mac_write_reg
6910 +*----------------------------------------------------------------------*/
6911 +void mac_write_reg(int mac, unsigned int offset, unsigned data)
6912 +{
6913 +       switch (mac)
6914 +       {
6915 +               case 0:
6916 +                       gmac_write_reg(GMAC0_BASE, offset, data, 0xffffffff);
6917 +                       break;
6918 +               case 1:
6919 +                       gmac_write_reg(GMAC1_BASE, offset, data, 0xffffffff);
6920 +                       break;
6921 +       }
6922 +}
6923 +
6924 +/*----------------------------------------------------------------------
6925 +* mac_read_dma_reg(int mac, unsigned int offset)
6926 +*----------------------------------------------------------------------*/
6927 +u32 mac_read_dma_reg(int mac, unsigned int offset)
6928 +{
6929 +       switch (mac)
6930 +       {
6931 +               case 0:
6932 +                       return gmac_read_reg(TOE_GMAC0_DMA_BASE, offset);
6933 +               case 1:
6934 +                       return gmac_read_reg(TOE_GMAC1_DMA_BASE, offset);
6935 +               default:
6936 +                       return 0;
6937 +       }
6938 +}
6939 +
6940 +/*----------------------------------------------------------------------
6941 +* mac_write_dma_reg
6942 +*----------------------------------------------------------------------*/
6943 +void mac_write_dma_reg(int mac, unsigned int offset, u32 data)
6944 +{
6945 +       switch (mac)
6946 +       {
6947 +               case 0:
6948 +                       gmac_write_reg(TOE_GMAC0_DMA_BASE, offset, data, 0xffffffff);
6949 +                       break;
6950 +               case 1:
6951 +                       gmac_write_reg(TOE_GMAC1_DMA_BASE, offset, data, 0xffffffff);
6952 +                       break;
6953 +       }
6954 +}
6955 +
6956 +/*----------------------------------------------------------------------
6957 +* ether_crc
6958 +*----------------------------------------------------------------------*/
6959 +static unsigned const ethernet_polynomial = 0x04c11db7U;
6960 +static unsigned int ether_crc (int length, unsigned char *data)
6961 +{
6962 +       int crc = -1;
6963 +       unsigned int i;
6964 +       unsigned int crc_val=0;
6965 +
6966 +       while (--length >= 0) {
6967 +               unsigned char current_octet = *data++;
6968 +               int bit;
6969 +               for (bit = 0; bit < 8; bit++, current_octet >>= 1)
6970 +                       crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
6971 +                            ethernet_polynomial : 0);
6972 +       }
6973 +       crc = ~crc;
6974 +       for (i=0;i<32;i++)
6975 +       {
6976 +               crc_val = crc_val + (((crc << i) & 0x80000000) >> (31-i));
6977 +       }
6978 +       return crc_val;
6979 +}
6980 +
6981 +
6982 +
6983 +/*----------------------------------------------------------------------
6984 +* mac_set_rx_mode
6985 +*----------------------------------------------------------------------*/
6986 +void mac_set_rx_mode(int pid, unsigned int data)
6987 +{
6988 +       unsigned int    base;
6989 +
6990 +       base = (pid == 0) ? GMAC0_BASE : GMAC1_BASE;
6991 +
6992 +    gmac_write_reg(base, GMAC_RX_FLTR, data, 0x0000001f);
6993 +    return;
6994 +}
6995 +
6996 +
6997 +/*----------------------------------------------------------------------
6998 +* gmac_open
6999 +*----------------------------------------------------------------------*/
7000 +
7001 +static int gmac_open (struct net_device *dev)
7002 +{
7003 +       GMAC_INFO_T  *tp = (GMAC_INFO_T *)dev->priv;
7004 +       int                                     retval;
7005 +       TOE_INFO_T                              *toe;
7006 +       toe = (TOE_INFO_T *)&toe_private_data;
7007 +
7008 +    /* hook ISR */
7009 +       retval = request_irq (dev->irq, toe_gmac_interrupt, IRQF_DISABLED, dev->name, dev);
7010 +       if (retval)
7011 +               return retval;
7012 +
7013 +       toe_init_gmac(dev);
7014 +
7015 +       if(!FLAG_SWITCH)
7016 +       {
7017 +       init_waitqueue_head (&tp->thr_wait);
7018 +       init_completion(&tp->thr_exited);
7019 +
7020 +       tp->time_to_die = 0;
7021 +       tp->thr_pid = kernel_thread (gmac_phy_thread, dev, CLONE_FS | CLONE_FILES);
7022 +       if (tp->thr_pid < 0)
7023 +       {
7024 +               printk (KERN_WARNING "%s: unable to start kernel thread\n",dev->name);
7025 +       }
7026 +    }
7027 +
7028 +       tp->operation = 1;
7029 +
7030 +       netif_start_queue (dev);
7031 +
7032 +       return (0);
7033 +}
7034 +
7035 +/*----------------------------------------------------------------------
7036 +* gmac_close
7037 +*----------------------------------------------------------------------*/
7038 +static int gmac_close(struct net_device *dev)
7039 +{
7040 +    TOE_INFO_T                 *toe;
7041 +//     GMAC_RXDESC_T           *sw_desc_ptr,*desc_ptr;
7042 +//     unsigned int            buf_ptr;
7043 +       GMAC_INFO_T     *tp = dev->priv;
7044 +       unsigned int            ret;
7045 +
7046 +       toe = (TOE_INFO_T *)&toe_private_data;
7047 +
7048 +       tp->operation = 0;
7049 +
7050 +    netif_stop_queue(dev);
7051 +    mdelay(20);
7052 +
7053 +    /* stop tx/rx packet */
7054 +    toe_gmac_disable_tx_rx(dev);
7055 +    mdelay(20);
7056 +
7057 +    /* stop the chip's Tx and Rx DMA processes */
7058 +       toe_gmac_hw_stop(dev);
7059 +
7060 +       toe_gmac_disable_interrupt(tp->irq);
7061 +
7062 +    /* disable interrupts by clearing the interrupt mask */
7063 +    synchronize_irq();
7064 +    free_irq(dev->irq,dev);
7065 +
7066 +//     DMA_MFREE(sw_desc_ptr, (TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),(dma_addr_t *)&toe->sw_freeq_desc_base_dma);
7067 +//     DMA_MFREE(desc_ptr, TOE_HW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),(dma_addr_t *)&toe->hw_freeq_desc_base_dma);
7068 +//     DMA_MFREE(buf_ptr, TOE_HW_FREEQ_DESC_NUM) * HW_RX_BUF_SIZE),(dma_addr_t *)&toe->hwfq_buf_base_dma);
7069 +//     DMA_MFREE(toe->gmac[0].swtxq_desc_base , TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[0].swtxq_desc_base_dma);
7070 +//     DMA_MFREE(toe->gmac[1].swtxq_desc_base , TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[1].swtxq_desc_base_dma);
7071 +//     DMA_MFREE(toe->gmac[0].hwtxq_desc_base_dma , TOE_GMAC0_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[0].hwtxq_desc_base_dma);
7072 +//     DMA_MFREE(toe->gmac[1].hwtxq_desc_base_dma , TOE_GMAC0_SWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[1].hwtxq_desc_base_dma);
7073 +//     DMA_MFREE(toe->gmac[0].default_desc_base_dma ,TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
7074 +//     DMA_MFREE(toe->gmac[1].default_desc_base_dma , TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
7075 +//     DMA_MFREE(toe->intr_desc_base_dma , TOE_INTR_QUEUE_NUM * TOE_INTR_DESC_NUM * sizeof(GMAC_RXDESC_T),(dma_addr_t *)&toe->intr_desc_base_dma);
7076 +//     DMA_MFREE(toe->intr_buf_base_dma , TOE_INTR_DESC_NUM * sizeof(TOE_QHDR_T),(dma_addr_t *)&toe->intr_buf_base_dma);
7077 +
7078 +       if(!FLAG_SWITCH)
7079 +       {
7080 +       if (tp->thr_pid >= 0)
7081 +       {
7082 +                   tp->time_to_die = 1;
7083 +               wmb();
7084 +               ret = kill_proc (tp->thr_pid, SIGTERM, 1);
7085 +               if (ret)
7086 +               {
7087 +                       printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
7088 +                       return ret;
7089 +               }
7090 +//             wait_for_completion (&tp->thr_exited);
7091 +       }
7092 +    }
7093 +
7094 +    return (0);
7095 +}
7096 +
7097 +/*----------------------------------------------------------------------
7098 +* toe_gmac_fill_free_q
7099 +* allocate buffers for free queue.
7100 +*----------------------------------------------------------------------*/
7101 +static inline void toe_gmac_fill_free_q(void)
7102 +{
7103 +       struct sk_buff  *skb;
7104 +       volatile DMA_RWPTR_T    fq_rwptr;
7105 +       volatile GMAC_RXDESC_T  *fq_desc;
7106 +       unsigned long   flags;
7107 +       // unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
7108 +
7109 +       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7110 +       spin_lock_irqsave(&gmac_fq_lock, flags);
7111 +       //while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
7112 +       //                              TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
7113 +       while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
7114 +                                       TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
7115 +               if ((skb = dev_alloc_skb(SW_RX_BUF_SIZE)) == NULL) {
7116 +                       printk("%s::skb allocation fail!\n", __func__);
7117 +                       //while(1);
7118 +                       break;
7119 +               }
7120 +               REG32(skb->data) = (unsigned int)skb;
7121 +               skb_reserve(skb, SKB_RESERVE_BYTES);
7122 +               // fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7123 +               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
7124 +                       TOE_SW_FREEQ_DESC_NUM);
7125 +               fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base+fq_rwptr.bits.wptr;
7126 +               fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
7127 +               SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
7128 +               toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
7129 +       }
7130 +       spin_unlock_irqrestore(&gmac_fq_lock, flags);
7131 +}
7132 +// EXPORT_SYMBOL(toe_gmac_fill_free_q);
7133 +
7134 +/*----------------------------------------------------------------------
7135 +* toe_gmac_interrupt
7136 +*----------------------------------------------------------------------*/
7137 +static irqreturn_t toe_gmac_interrupt (int irq, void *dev_instance)
7138 +{
7139 +       struct net_device   *dev = (struct net_device *)dev_instance;
7140 +       TOE_INFO_T                      *toe;
7141 +       GMAC_INFO_T             *tp = (GMAC_INFO_T *)dev->priv;
7142 +       unsigned int            status0;
7143 +       unsigned int            status1;
7144 +       unsigned int            status2;
7145 +       unsigned int            status3;
7146 +       unsigned int            status4;
7147 +
7148 +//     struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
7149 +       toe = (TOE_INFO_T *)&toe_private_data;
7150 +//     handle NAPI
7151 +#ifdef CONFIG_SL_NAPI
7152 +if (storlink_ctl.pauseoff == 1)
7153 +{
7154 +/* disable GMAC interrupt */
7155 +    //toe_gmac_disable_interrupt(tp->irq);
7156 +
7157 +//     isPtr->interrupts++;
7158 +       /* read Interrupt status */
7159 +       status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
7160 +       status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
7161 +       status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
7162 +       status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
7163 +       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
7164 +       // prompt warning if status bit ON but not enabled
7165 +#if 0
7166 +       if (status0 & ~tp->intr0_enabled)
7167 +               printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
7168 +                               status0, tp->intr0_enabled);
7169 +       if (status1 & ~tp->intr1_enabled)
7170 +               printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
7171 +                               status1, tp->intr1_enabled);
7172 +       if (status2 & ~tp->intr2_enabled)
7173 +               printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
7174 +                               status2, tp->intr2_enabled);
7175 +       if (status3 & ~tp->intr3_enabled)
7176 +               printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
7177 +                               status3, tp->intr3_enabled);
7178 +       if (status4 & ~tp->intr4_enabled)
7179 +               printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
7180 +                               status4, tp->intr4_enabled);
7181 +#endif
7182 +
7183 +       if (status0)
7184 +               writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
7185 +       if (status1)
7186 +               writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
7187 +       if (status2)
7188 +               writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
7189 +       if (status3)
7190 +               writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
7191 +       if (status4)
7192 +               writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
7193 +#if 0
7194 +       /* handle freeq interrupt first */
7195 +       if (status4 & tp->intr4_enabled) {
7196 +               if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
7197 +               {
7198 +                       // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7199 +                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
7200 +                       //      tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7201 +
7202 +                       if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
7203 +                               toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
7204 +                       if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
7205 +                               toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
7206 +                       printk("\nfreeq int\n");
7207 +                       toe_gmac_fill_free_q();
7208 +                       tp->sw_fq_empty_cnt++;
7209 +
7210 +               }
7211 +       }
7212 +#endif
7213 +       // Interrupt Status 1
7214 +       if (status1 & tp->intr1_enabled)
7215 +       {
7216 +               #define G1_INTR0_BITS   (GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
7217 +               #define G0_INTR0_BITS   (GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
7218 +               // Handle GMAC 0/1 HW Tx queue 0-3 EOF events
7219 +               // Only count
7220 +               // TOE, Classification, and default queues interrupts are handled by ISR
7221 +               // because they should pass packets to upper layer
7222 +               if (tp->port_id == 0)
7223 +               {
7224 +                       if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
7225 +                       {
7226 +                               if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
7227 +                                       tp->hwtxq[3].eof_cnt++;
7228 +                               if (status1 & GMAC0_HWTQ02_EOF_INT_BIT)
7229 +                                       tp->hwtxq[2].eof_cnt++;
7230 +                               if (status1 & GMAC0_HWTQ01_EOF_INT_BIT)
7231 +                                       tp->hwtxq[1].eof_cnt++;
7232 +                               if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
7233 +                                       tp->hwtxq[0].eof_cnt++;
7234 +                       }
7235 +                               if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
7236 +                               {
7237 +                                       if (likely(netif_rx_schedule_prep(dev)))
7238 +                               {
7239 +                                       unsigned int data32;
7240 +                                       // disable GMAC-0 rx interrupt
7241 +                                       // class-Q & TOE-Q are implemented in future
7242 +                                       //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
7243 +                                       //data32 &= ~DEFAULT_Q0_INT_BIT;
7244 +                                               //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
7245 +                                               //printk("\%s: DEFAULT_Q0_INT_BIT===================>>>>>>>>>>>>\n",__func__);
7246 +                                               writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
7247 +                                               //tp->total_q_cnt_napi=0;
7248 +                                               //rx_time = jiffies;
7249 +                                               //rx_old_bytes = isPtr->rx_bytes;
7250 +                               __netif_rx_schedule(dev);
7251 +                               }
7252 +                       }
7253 +               }
7254 +               else if (tp->port_id == 1)
7255 +               {
7256 +                       if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
7257 +                       {
7258 +                               if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
7259 +                                       tp->hwtxq[3].eof_cnt++;
7260 +                               if (status1 & GMAC1_HWTQ12_EOF_INT_BIT)
7261 +                                       tp->hwtxq[2].eof_cnt++;
7262 +                               if (status1 & GMAC1_HWTQ11_EOF_INT_BIT)
7263 +                                       tp->hwtxq[1].eof_cnt++;
7264 +                               if (status1 & GMAC1_HWTQ10_EOF_INT_BIT)
7265 +                                       tp->hwtxq[0].eof_cnt++;
7266 +                       }
7267 +
7268 +                       if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
7269 +                       {
7270 +                               if (likely(netif_rx_schedule_prep(dev)))
7271 +                       {
7272 +                               unsigned int data32;
7273 +                               // disable GMAC-0 rx interrupt
7274 +                               // class-Q & TOE-Q are implemented in future
7275 +                               //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
7276 +                               //data32 &= ~DEFAULT_Q1_INT_BIT;
7277 +                                       //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
7278 +                                       //printk("\%s: 1111111111--->DEFAULT_Q1_INT_BIT===================>>>>>>>>>>>>\n",__func__);
7279 +                                       writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
7280 +                                       //tp->total_q_cnt_napi=0;
7281 +                                       //rx_time = jiffies;
7282 +                                       //rx_old_bytes = isPtr->rx_bytes;
7283 +                               __netif_rx_schedule(dev);
7284 +                       }
7285 +                       }
7286 +               }
7287 +       }
7288 +
7289 +       // Interrupt Status 0
7290 +       if (status0 & tp->intr0_enabled)
7291 +       {
7292 +               #define ERR_INTR_BITS   (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |  \
7293 +                                                                GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |  \
7294 +                                                                GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |  \
7295 +                                                                GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT)
7296 +
7297 +               if (status0 &  ERR_INTR_BITS)
7298 +               {
7299 +                       if ((status0 & GMAC0_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXDERR_INT_BIT))
7300 +                       {
7301 +                               tp->txDerr_cnt[0]++;
7302 +                               printk("GMAC0 TX AHB Bus Error!\n");
7303 +                       }
7304 +                       if ((status0 & GMAC0_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXPERR_INT_BIT))
7305 +                       {
7306 +                               tp->txPerr_cnt[0]++;
7307 +                               printk("GMAC0 Tx Descriptor Protocol Error!\n");
7308 +                       }
7309 +                       if ((status0 & GMAC1_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXDERR_INT_BIT))
7310 +                       {
7311 +                               tp->txDerr_cnt[1]++;
7312 +                               printk("GMAC1 Tx AHB Bus Error!\n");
7313 +                       }
7314 +                       if ((status0 & GMAC1_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXPERR_INT_BIT))
7315 +                       {
7316 +                               tp->txPerr_cnt[1]++;
7317 +                               printk("GMAC1 Tx Descriptor Protocol Error!\n");
7318 +                       }
7319 +
7320 +                       if ((status0 & GMAC0_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXDERR_INT_BIT))
7321 +                       {
7322 +                               tp->RxDerr_cnt[0]++;
7323 +                               printk("GMAC0 Rx AHB Bus Error!\n");
7324 +                       }
7325 +                       if ((status0 & GMAC0_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXPERR_INT_BIT))
7326 +                       {
7327 +                               tp->RxPerr_cnt[0]++;
7328 +                               printk("GMAC0 Rx Descriptor Protocol Error!\n");
7329 +                       }
7330 +                       if ((status0 & GMAC1_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXDERR_INT_BIT))
7331 +                       {
7332 +                               tp->RxDerr_cnt[1]++;
7333 +                               printk("GMAC1 Rx AHB Bus Error!\n");
7334 +                       }
7335 +                       if ((status0 & GMAC1_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXPERR_INT_BIT))
7336 +                       {
7337 +                               tp->RxPerr_cnt[1]++;
7338 +                               printk("GMAC1 Rx Descriptor Protocol Error!\n");
7339 +                       }
7340 +               }
7341 +
7342 +#ifndef        GMAX_TX_INTR_DISABLED
7343 +               if (tp->port_id == 1 && netif_running(dev) &&
7344 +                       (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
7345 +                       ||
7346 +                       ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT))))
7347 +               {
7348 +                       toe_gmac_tx_complete(&toe_private_data.gmac[1], 0, dev, 1);
7349 +               }
7350 +
7351 +               if (tp->port_id == 0 && netif_running(dev) &&
7352 +                       (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
7353 +                       ||
7354 +                       ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT))))
7355 +               {
7356 +                       toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
7357 +               }
7358 +#endif
7359 +       }
7360 +       // Interrupt Status 4
7361 +       if (status4 & tp->intr4_enabled)
7362 +       {
7363 +               #define G1_INTR4_BITS           (0xff000000)
7364 +               #define G0_INTR4_BITS           (0x00ff0000)
7365 +
7366 +               if (tp->port_id == 0)
7367 +               {
7368 +                       if ((status4 & G0_INTR4_BITS) && (tp->intr4_enabled & G0_INTR4_BITS))
7369 +                       {
7370 +                               if (status4 & GMAC0_RESERVED_INT_BIT)
7371 +                                       printk("GMAC0_RESERVED_INT_BIT is ON\n");
7372 +                               if (status4 & GMAC0_MIB_INT_BIT)
7373 +                                       tp->mib_full_cnt++;
7374 +                               if (status4 & GMAC0_RX_PAUSE_ON_INT_BIT)
7375 +                                       tp->rx_pause_on_cnt++;
7376 +                               if (status4 & GMAC0_TX_PAUSE_ON_INT_BIT)
7377 +                                       tp->tx_pause_on_cnt++;
7378 +                               if (status4 & GMAC0_RX_PAUSE_OFF_INT_BIT)
7379 +                                       tp->rx_pause_off_cnt++;
7380 +                               if (status4 & GMAC0_TX_PAUSE_OFF_INT_BIT)
7381 +                                       tp->rx_pause_off_cnt++;
7382 +                               if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
7383 +                                       tp->rx_overrun_cnt++;
7384 +                               if (status4 & GMAC0_STATUS_CHANGE_INT_BIT)
7385 +                                       tp->status_changed_cnt++;
7386 +                       }
7387 +               }
7388 +               else if (tp->port_id == 1)
7389 +               {
7390 +                       if ((status4 & G1_INTR4_BITS) && (tp->intr4_enabled & G1_INTR4_BITS))
7391 +                       {
7392 +                               if (status4 & GMAC1_RESERVED_INT_BIT)
7393 +                                       printk("GMAC1_RESERVED_INT_BIT is ON\n");
7394 +                               if (status4 & GMAC1_MIB_INT_BIT)
7395 +                                       tp->mib_full_cnt++;
7396 +                               if (status4 & GMAC1_RX_PAUSE_ON_INT_BIT)
7397 +                               {
7398 +                                       printk("Gmac pause on\n");
7399 +                                       tp->rx_pause_on_cnt++;
7400 +                               }
7401 +                               if (status4 & GMAC1_TX_PAUSE_ON_INT_BIT)
7402 +                               {
7403 +                                       printk("Gmac pause on\n");
7404 +                                       tp->tx_pause_on_cnt++;
7405 +                               }
7406 +                               if (status4 & GMAC1_RX_PAUSE_OFF_INT_BIT)
7407 +                               {
7408 +                                       printk("Gmac pause off\n");
7409 +                                       tp->rx_pause_off_cnt++;
7410 +                               }
7411 +                               if (status4 & GMAC1_TX_PAUSE_OFF_INT_BIT)
7412 +                               {
7413 +                                       printk("Gmac pause off\n");
7414 +                                       tp->rx_pause_off_cnt++;
7415 +                               }
7416 +                               if (status4 & GMAC1_RX_OVERRUN_INT_BIT)
7417 +                               {
7418 +                                       //printk("Gmac Rx Overrun \n");
7419 +                                       tp->rx_overrun_cnt++;
7420 +                               }
7421 +                               if (status4 & GMAC1_STATUS_CHANGE_INT_BIT)
7422 +                                       tp->status_changed_cnt++;
7423 +                       }
7424 +               }
7425 +       }
7426 +
7427 +       //toe_gmac_enable_interrupt(tp->irq);
7428 +#ifdef IxscriptMate_1518
7429 +       if (storlink_ctl.pauseoff == 1)
7430 +       {
7431 +               GMAC_CONFIG0_T config0;
7432 +               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7433 +               config0.bits.dis_rx = 0;
7434 +               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7435 +               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7436 +               config0.bits.dis_rx = 0;
7437 +               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7438 +       }
7439 +#endif
7440 +//      enable_irq(gmac_irq[dev_index]);
7441 +       //printk("gmac_interrupt complete!\n\n");
7442 +//     return IRQ_RETVAL(handled);
7443 +       return  IRQ_RETVAL(1);
7444 +}
7445 +else
7446 +{
7447 +#endif //endif NAPI
7448 +
7449 +
7450 +       /* disable GMAC interrupt */
7451 +    toe_gmac_disable_interrupt(tp->irq);
7452 +
7453 +//     isPtr->interrupts++;
7454 +       /* read Interrupt status */
7455 +       status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
7456 +       status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
7457 +       status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
7458 +       status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
7459 +       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
7460 +       // prompt warning if status bit ON but not enabled
7461 +#if 0
7462 +       if (status0 & ~tp->intr0_enabled)
7463 +               printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
7464 +                               status0, tp->intr0_enabled);
7465 +       if (status1 & ~tp->intr1_enabled)
7466 +               printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
7467 +                               status1, tp->intr1_enabled);
7468 +       if (status2 & ~tp->intr2_enabled)
7469 +               printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
7470 +                               status2, tp->intr2_enabled);
7471 +       if (status3 & ~tp->intr3_enabled)
7472 +               printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
7473 +                               status3, tp->intr3_enabled);
7474 +       if (status4 & ~tp->intr4_enabled)
7475 +               printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
7476 +                               status4, tp->intr4_enabled);
7477 +#endif
7478 +#define        INTERRUPT_SELECT                        1
7479 +       if (status0)
7480 +               writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
7481 +       if (status1)
7482 +               writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
7483 +       if (status2)
7484 +               writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
7485 +       if (status3)
7486 +               writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
7487 +       if (status4)
7488 +               writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
7489 +
7490 +       /* handle freeq interrupt first */
7491 +       if (status4 & tp->intr4_enabled) {
7492 +               if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
7493 +               {
7494 +                       // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7495 +                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
7496 +                       //      tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7497 +
7498 +                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
7499 +                       //      SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7500 +                       if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
7501 +                               toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
7502 +                       if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
7503 +                               toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
7504 +                       printk("\nfreeq int\n");
7505 +                       toe_gmac_fill_free_q();
7506 +                       tp->sw_fq_empty_cnt++;
7507 +
7508 +                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
7509 +                               SWFQ_EMPTY_INT_BIT);
7510 +               }
7511 +       }
7512 +
7513 +       // Interrupt Status 1
7514 +       if (status1 & tp->intr1_enabled)
7515 +       {
7516 +               #define G1_INTR0_BITS   (GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
7517 +               #define G0_INTR0_BITS   (GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
7518 +               // Handle GMAC 0/1 HW Tx queue 0-3 EOF events
7519 +               // Only count
7520 +               // TOE, Classification, and default queues interrupts are handled by ISR
7521 +               // because they should pass packets to upper layer
7522 +               if (tp->port_id == 0)
7523 +               {
7524 +#ifndef        INTERRUPT_SELECT
7525 +                       if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
7526 +                       {
7527 +                               if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
7528 +                                       tp->hwtxq[3].eof_cnt++;
7529 +                               if (status1 & GMAC0_HWTQ02_EOF_INT_BIT)
7530 +                                       tp->hwtxq[2].eof_cnt++;
7531 +                               if (status1 & GMAC0_HWTQ01_EOF_INT_BIT)
7532 +                                       tp->hwtxq[1].eof_cnt++;
7533 +                               if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
7534 +                                       tp->hwtxq[0].eof_cnt++;
7535 +#endif //INTERRUPT_SELECT
7536 +#ifndef        INTERRUPT_SELECT
7537 +                       }
7538 +#endif //INTERRUPT_SELECT
7539 +                       if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
7540 +                       {
7541 +                               tp->default_q_intr_cnt++;
7542 +                               toe_gmac_handle_default_rxq(dev, tp);
7543 +                       }
7544 +#ifdef CONFIG_SL351x_RXTOE
7545 +                       if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
7546 +                           (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
7547 +                               //printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
7548 +                               toe_gmac_handle_toeq(dev, tp, status1);
7549 +                               //toe_gmac_handle_toeq(dev, toe, tp, status1);
7550 +                       }
7551 +#endif
7552 +               }
7553 +               else if (tp->port_id == 1)
7554 +               {
7555 +#ifndef        INTERRUPT_SELECT
7556 +                       if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
7557 +                       {
7558 +                               if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
7559 +                                       tp->hwtxq[3].eof_cnt++;
7560 +                               if (status1 & GMAC1_HWTQ12_EOF_INT_BIT)
7561 +                                       tp->hwtxq[2].eof_cnt++;
7562 +                               if (status1 & GMAC1_HWTQ11_EOF_INT_BIT)
7563 +                                       tp->hwtxq[1].eof_cnt++;
7564 +                               if (status1 & GMAC1_HWTQ10_EOF_INT_BIT)
7565 +                                       tp->hwtxq[0].eof_cnt++;
7566 +#endif //INTERRUPT_SELECT
7567 +#ifndef        INTERRUPT_SELECT
7568 +                       }
7569 +#endif //INTERRUPT_SELECT
7570 +                       if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
7571 +                       {
7572 +                               tp->default_q_intr_cnt++;
7573 +                               toe_gmac_handle_default_rxq(dev, tp);
7574 +                       }
7575 +#ifdef CONFIG_SL351x_RXTOE
7576 +                       if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
7577 +                           (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
7578 +                               //printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
7579 +                               toe_gmac_handle_toeq(dev, tp, status1);
7580 +                               //toe_gmac_handle_toeq(dev, toe, tp, status1);
7581 +                       }
7582 +#endif
7583 +               }
7584 +       }
7585 +
7586 +
7587 +       // Interrupt Status 0
7588 +       if (status0 & tp->intr0_enabled)
7589 +       {
7590 +
7591 +               #define ERR_INTR_BITS   (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |  \
7592 +                                                                GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |  \
7593 +                                                                GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |  \
7594 +                                                                GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT)
7595 +#ifndef        INTERRUPT_SELECT
7596 +               if (status0 &  ERR_INTR_BITS)
7597 +               {
7598 +                       if ((status0 & GMAC0_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXDERR_INT_BIT))
7599 +                       {
7600 +                               tp->txDerr_cnt[0]++;
7601 +                               printk("GMAC0 TX AHB Bus Error!\n");
7602 +                       }
7603 +                       if ((status0 & GMAC0_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXPERR_INT_BIT))
7604 +                       {
7605 +                               tp->txPerr_cnt[0]++;
7606 +                               printk("GMAC0 Tx Descriptor Protocol Error!\n");
7607 +                       }
7608 +                       if ((status0 & GMAC1_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXDERR_INT_BIT))
7609 +                       {
7610 +                               tp->txDerr_cnt[1]++;
7611 +                               printk("GMAC1 Tx AHB Bus Error!\n");
7612 +                       }
7613 +                       if ((status0 & GMAC1_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXPERR_INT_BIT))
7614 +                       {
7615 +                               tp->txPerr_cnt[1]++;
7616 +                               printk("GMAC1 Tx Descriptor Protocol Error!\n");
7617 +                       }
7618 +
7619 +                       if ((status0 & GMAC0_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXDERR_INT_BIT))
7620 +                       {
7621 +                               tp->RxDerr_cnt[0]++;
7622 +                               printk("GMAC0 Rx AHB Bus Error!\n");
7623 +                       }
7624 +                       if ((status0 & GMAC0_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXPERR_INT_BIT))
7625 +                       {
7626 +                               tp->RxPerr_cnt[0]++;
7627 +                               printk("GMAC0 Rx Descriptor Protocol Error!\n");
7628 +                       }
7629 +                       if ((status0 & GMAC1_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXDERR_INT_BIT))
7630 +                       {
7631 +                               tp->RxDerr_cnt[1]++;
7632 +                               printk("GMAC1 Rx AHB Bus Error!\n");
7633 +                       }
7634 +                       if ((status0 & GMAC1_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXPERR_INT_BIT))
7635 +                       {
7636 +                               tp->RxPerr_cnt[1]++;
7637 +                               printk("GMAC1 Rx Descriptor Protocol Error!\n");
7638 +                       }
7639 +               }
7640 +#endif //INTERRUPT_SELECT
7641 +#ifndef        GMAX_TX_INTR_DISABLED
7642 +               if (tp->port_id == 1 && netif_running(dev) &&
7643 +                       (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
7644 +                       ||
7645 +                       ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT))))
7646 +               {
7647 +                       toe_gmac_tx_complete(&toe_private_data.gmac[1], 0, dev, 1);
7648 +               }
7649 +
7650 +               if (tp->port_id == 0 && netif_running(dev) &&
7651 +                       (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
7652 +                       ||
7653 +                       ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT))))
7654 +               {
7655 +                       toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
7656 +               }
7657 +#endif
7658 +               // clear enabled status bits
7659 +       }
7660 +       // Interrupt Status 4
7661 +#ifndef        INTERRUPT_SELECT
7662 +       if (status4 & tp->intr4_enabled)
7663 +       {
7664 +               #define G1_INTR4_BITS           (0xff000000)
7665 +               #define G0_INTR4_BITS           (0x00ff0000)
7666 +
7667 +               if (tp->port_id == 0)
7668 +               {
7669 +                       if ((status4 & G0_INTR4_BITS) && (tp->intr4_enabled & G0_INTR4_BITS))
7670 +                       {
7671 +                               if (status4 & GMAC0_RESERVED_INT_BIT)
7672 +                                       printk("GMAC0_RESERVED_INT_BIT is ON\n");
7673 +                               if (status4 & GMAC0_MIB_INT_BIT)
7674 +                                       tp->mib_full_cnt++;
7675 +                               if (status4 & GMAC0_RX_PAUSE_ON_INT_BIT)
7676 +                                       tp->rx_pause_on_cnt++;
7677 +                               if (status4 & GMAC0_TX_PAUSE_ON_INT_BIT)
7678 +                                       tp->tx_pause_on_cnt++;
7679 +                               if (status4 & GMAC0_RX_PAUSE_OFF_INT_BIT)
7680 +                                       tp->rx_pause_off_cnt++;
7681 +                               if (status4 & GMAC0_TX_PAUSE_OFF_INT_BIT)
7682 +                                       tp->rx_pause_off_cnt++;
7683 +                               if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
7684 +                                       tp->rx_overrun_cnt++;
7685 +                               if (status4 & GMAC0_STATUS_CHANGE_INT_BIT)
7686 +                                       tp->status_changed_cnt++;
7687 +                       }
7688 +               }
7689 +               else if (tp->port_id == 1)
7690 +               {
7691 +                       if ((status4 & G1_INTR4_BITS) && (tp->intr4_enabled & G1_INTR4_BITS))
7692 +                       {
7693 +                               if (status4 & GMAC1_RESERVED_INT_BIT)
7694 +                                       printk("GMAC1_RESERVED_INT_BIT is ON\n");
7695 +                               if (status4 & GMAC1_MIB_INT_BIT)
7696 +                                       tp->mib_full_cnt++;
7697 +                               if (status4 & GMAC1_RX_PAUSE_ON_INT_BIT)
7698 +                               {
7699 +                                       //printk("Gmac pause on\n");
7700 +                                       tp->rx_pause_on_cnt++;
7701 +                               }
7702 +                               if (status4 & GMAC1_TX_PAUSE_ON_INT_BIT)
7703 +                               {
7704 +                                       //printk("Gmac pause on\n");
7705 +                                       tp->tx_pause_on_cnt++;
7706 +                               }
7707 +                               if (status4 & GMAC1_RX_PAUSE_OFF_INT_BIT)
7708 +                               {
7709 +                                       //printk("Gmac pause off\n");
7710 +                                       tp->rx_pause_off_cnt++;
7711 +                               }
7712 +                               if (status4 & GMAC1_TX_PAUSE_OFF_INT_BIT)
7713 +                               {
7714 +                                       //printk("Gmac pause off\n");
7715 +                                       tp->rx_pause_off_cnt++;
7716 +                               }
7717 +                               if (status4 & GMAC1_RX_OVERRUN_INT_BIT)
7718 +                               {
7719 +                                       //printk("Gmac Rx Overrun \n");
7720 +                                       tp->rx_overrun_cnt++;
7721 +                               }
7722 +                               if (status4 & GMAC1_STATUS_CHANGE_INT_BIT)
7723 +                                       tp->status_changed_cnt++;
7724 +                       }
7725 +               }
7726 +#if 0
7727 +               if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
7728 +               {
7729 +                       // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7730 +//                     mac_stop_rxdma(tp->sc);
7731 +                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
7732 +                               tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7733 +
7734 +                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
7735 +                               SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7736 +                       toe_gmac_fill_free_q();
7737 +                       tp->sw_fq_empty_cnt++;
7738 +
7739 +                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
7740 +                               SWFQ_EMPTY_INT_BIT);
7741 +//#if 0
7742 +/*                     if (netif_running(dev))
7743 +                               toe_gmac_handle_default_rxq(dev, tp);
7744 +                       printk("SWFQ_EMPTY_INT_BIT is ON!\n");  // should not be happened */
7745 +//#endif
7746 +               }
7747 +#endif
7748 +       }
7749 +#endif //INTERRUPT_SELECT
7750 +       toe_gmac_enable_interrupt(tp->irq);
7751 +//enable gmac rx function when do RFC 2544
7752 +#ifdef IxscriptMate_1518
7753 +       if (storlink_ctl.pauseoff == 1)
7754 +       {
7755 +               GMAC_CONFIG0_T config0;
7756 +               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7757 +               config0.bits.dis_rx = 0;
7758 +               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7759 +               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7760 +               config0.bits.dis_rx = 0;
7761 +               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7762 +       }
7763 +#endif
7764 +       //printk("gmac_interrupt complete!\n\n");
7765 +//     return IRQ_RETVAL(handled);
7766 +       return  IRQ_RETVAL(1);
7767 +#ifdef CONFIG_SL_NAPI
7768 +}
7769 +#endif
7770 +}
7771 +
7772 +/*----------------------------------------------------------------------
7773 +*      toe_gmac_handle_default_rxq
7774 +*      (1) Get rx Buffer for default Rx queue
7775 +*      (2) notify or call upper-routine to handle it
7776 +*      (3) get a new buffer and insert it into SW free queue
7777 +*      (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
7778 +*----------------------------------------------------------------------*/
7779 +//static inline void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
7780 +static void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
7781 +{
7782 +       TOE_INFO_T                      *toe;
7783 +    GMAC_RXDESC_T      *curr_desc;
7784 +       struct sk_buff          *skb;
7785 +    DMA_RWPTR_T                        rwptr;
7786 +       unsigned int            pkt_size;
7787 +       int                                     max_cnt;
7788 +       unsigned int        desc_count;
7789 +       unsigned int        good_frame, chksum_status, rx_status;
7790 +       struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
7791 +
7792 +//when do ixia RFC 2544 test and packet size is select 1518 bytes,disable gmace rx function immediately after one interrupt come in.
7793 +#ifdef IxscriptMate_1518
7794 +       if (storlink_ctl.pauseoff == 1)
7795 +       {
7796 +               GMAC_CONFIG0_T config0;
7797 +               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7798 +               config0.bits.dis_rx = 1;
7799 +               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7800 +               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7801 +               config0.bits.dis_rx = 1;
7802 +               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7803 +       }
7804 +#endif
7805 +       rwptr.bits32 = readl(&tp->default_qhdr->word1);
7806 +#if 0
7807 +       if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
7808 +       {
7809 +               mac_stop_txdma((struct net_device *)tp->dev);
7810 +               printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
7811 +                               rwptr.bits32, tp->rx_rwptr.bits.rptr);
7812 +               while(1);
7813 +       }
7814 +#endif
7815 +       toe = (TOE_INFO_T *)&toe_private_data;
7816 +       max_cnt = DEFAULT_RXQ_MAX_CNT;
7817 +       while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr)
7818 +//     while (rwptr.bits.rptr != rwptr.bits.wptr)
7819 +       {
7820 +//if packet size is not 1518 for RFC 2544,enable gmac rx function.The other packet size have RX workaround.
7821 +#ifdef IxscriptMate_1518
7822 +       if (storlink_ctl.pauseoff == 1)
7823 +               {
7824 +                       if (pkt_size != 1514)
7825 +                       {
7826 +                                               GMAC_CONFIG0_T config0;
7827 +                                               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7828 +                                               config0.bits.dis_rx = 0;
7829 +                                               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7830 +                                               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7831 +                                               config0.bits.dis_rx = 0;
7832 +                                               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7833 +                       }
7834 +               }
7835 +#endif
7836 +       curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
7837 +//             consistent_sync(curr_desc, sizeof(GMAC_RXDESC_T), PCI_DMA_FROMDEVICE);
7838 +               tp->default_q_cnt++;
7839 +       tp->rx_curr_desc = (unsigned int)curr_desc;
7840 +       rx_status = curr_desc->word0.bits.status;
7841 +       chksum_status = curr_desc->word0.bits.chksum_status;
7842 +       tp->rx_status_cnt[rx_status]++;
7843 +       tp->rx_chksum_cnt[chksum_status]++;
7844 +        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
7845 +               desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
7846 +               good_frame=1;
7847 +               if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
7848 +                       || (pkt_size < 60)
7849 +                   || (chksum_status & 0x4)
7850 +                       || rx_status)
7851 +               {
7852 +                       good_frame = 0;
7853 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
7854 +                               printk("%s::derr (GMAC-%d)!!!\n", __func__, tp->port_id);
7855 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
7856 +                               printk("%s::perr (GMAC-%d)!!!\n", __func__, tp->port_id);
7857 +                       if (rx_status)
7858 +                       {
7859 +                               if (rx_status == 4 || rx_status == 7)
7860 +                                       isPtr->rx_crc_errors++;
7861 +//                             printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
7862 +                       }
7863 +#ifdef SL351x_GMAC_WORKAROUND
7864 +                       else if (pkt_size < 60)
7865 +                       {
7866 +                               if (tp->short_frames_cnt < GMAC_SHORT_FRAME_THRESHOLD)
7867 +                                       tp->short_frames_cnt++;
7868 +                               if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
7869 +                               {
7870 +                                       GMAC_CONFIG0_T config0;
7871 +                                       config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7872 +                                       config0.bits.dis_rx = 1;
7873 +                                       writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7874 +                                       config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7875 +                                       config0.bits.dis_rx = 1;
7876 +                                       writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7877 +                               }
7878 +                       }
7879 +#endif
7880 +//                     if (chksum_status)
7881 +//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
7882 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
7883 +                       dev_kfree_skb_irq(skb);
7884 +               }
7885 +               if (good_frame)
7886 +               {
7887 +                       if (curr_desc->word0.bits.drop)
7888 +                               printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
7889 +//                     if (chksum_status)
7890 +//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
7891 +
7892 +               /* get frame information from the first descriptor of the frame */
7893 +#ifdef SL351x_GMAC_WORKAROUND
7894 +                       if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
7895 +                       {
7896 +                               GMAC_CONFIG0_T config0;
7897 +                               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7898 +                               config0.bits.dis_rx = 0;
7899 +                               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7900 +                               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7901 +                               config0.bits.dis_rx = 0;
7902 +                               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7903 +                       }
7904 +                       tp->short_frames_cnt = 0;
7905 +#endif
7906 +                       isPtr->rx_packets++;
7907 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr - SKB_RESERVE_BYTES)));
7908 +                       if (!skb)
7909 +                       {
7910 +                               printk("Fatal Error!!skb==NULL\n");
7911 +                               goto next_rx;
7912 +                       }
7913 +                       tp->curr_rx_skb = skb;
7914 +                       // consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
7915 +
7916 +       //              curr_desc->word2.buf_adr = 0;
7917 +
7918 +                       skb_reserve (skb, RX_INSERT_BYTES);     /* 16 byte align the IP fields. */
7919 +                       skb_put(skb, pkt_size);
7920 +                       skb->dev = dev;
7921 +                       if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
7922 +                       {
7923 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
7924 +#ifdef CONFIG_SL351x_NAT
7925 +                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
7926 +                               {
7927 +                                       struct iphdr    *ip_hdr;
7928 +                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
7929 +                                       sl351x_nat_input(skb,
7930 +                                                                       tp->port_id,
7931 +                                                                       (void *)curr_desc->word3.bits.l3_offset,
7932 +                                                                       (void *)curr_desc->word3.bits.l4_offset);
7933 +                               }
7934 +#endif
7935 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
7936 +#if 0
7937 +#ifdef CONFIG_SL351x_RXTOE
7938 +                               if (storlink_ctl.rx_max_pktsize) {
7939 +                                       struct iphdr    *ip_hdr;
7940 +                                       struct tcphdr   *tcp_hdr;
7941 +                                       int ip_hdrlen;
7942 +
7943 +                                       ip_hdr = (struct iphdr*)&(skb->data[0]);
7944 +                                       if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
7945 +                                          ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
7946 +                                               ip_hdrlen = ip_hdr->ihl << 2;
7947 +                                               tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
7948 +                                               if (tcp_hdr->syn) {
7949 +                                                       struct toe_conn* connection = init_toeq(ip_hdr->version,
7950 +                                                                       ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
7951 +                                                       TCP_SKB_CB(skb)->connection = connection;
7952 +                                                       //      hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
7953 +                                                       //              printk("%s::skb data %x, conn %x, mode %x\n",
7954 +                                                       //                      __func__, skb->data, connection, connection->mode);
7955 +                                               }
7956 +                                       }
7957 +                               }
7958 +#endif
7959 +#endif
7960 +                       }
7961 +                       else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
7962 +                       {
7963 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
7964 +#ifdef CONFIG_SL351x_NAT
7965 +                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
7966 +                               {
7967 +                                       struct iphdr            *ip_hdr;
7968 +                                       //struct tcphdr         *tcp_hdr;
7969 +                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
7970 +                                       //tcp_hdr = (struct tcphdr *)&(skb->data[curr_desc->word3.bits.l4_offset]);
7971 +                                       if (ip_hdr->protocol == IPPROTO_UDP)
7972 +                                       {
7973 +                                               sl351x_nat_input(skb,
7974 +                                                                               tp->port_id,
7975 +                                                                               (void *)curr_desc->word3.bits.l3_offset,
7976 +                                                                               (void *)curr_desc->word3.bits.l4_offset);
7977 +                                       }
7978 +                                       else if (ip_hdr->protocol == IPPROTO_GRE)
7979 +                                       {
7980 +                                               sl351x_nat_input(skb,
7981 +                                                                       tp->port_id,
7982 +                                                                       (void *)curr_desc->word3.bits.l3_offset,
7983 +                                                                       (void *)curr_desc->word3.bits.l4_offset);
7984 +                                       }
7985 +                               }
7986 +#endif
7987 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
7988 +                       }
7989 +                       else
7990 +                       {
7991 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
7992 +                       }
7993 +
7994 +                       netif_rx(skb);  /* socket rx */
7995 +                       dev->last_rx = jiffies;
7996 +
7997 +                       isPtr->rx_bytes += pkt_size;
7998 +
7999 +        }
8000 +
8001 +next_rx:
8002 +               // advance one for Rx default Q 0/1
8003 +               rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
8004 +               SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
8005 +       tp->rx_rwptr.bits32 = rwptr.bits32;
8006 +
8007 +               toe_gmac_fill_free_q();
8008 +       }
8009 +}
8010 +
8011 +/*----------------------------------------------------------------------
8012 +* gmac_get_phy_vendor
8013 +*----------------------------------------------------------------------*/
8014 +static unsigned int gmac_get_phy_vendor(int phy_addr)
8015 +{
8016 +    unsigned int       reg_val;
8017 +    reg_val=(mii_read(phy_addr,0x02) << 16) + mii_read(phy_addr,0x03);
8018 +    return reg_val;
8019 +}
8020 +
8021 +/*----------------------------------------------------------------------
8022 +* gmac_set_phy_status
8023 +*----------------------------------------------------------------------*/
8024 +void gmac_set_phy_status(struct net_device *dev)
8025 +{
8026 +       GMAC_INFO_T *tp = dev->priv;
8027 +       GMAC_STATUS_T   status;
8028 +       unsigned int    reg_val, ability,wan_port_id;
8029 +       unsigned int    i = 0;
8030 +
8031 +#ifdef VITESSE_G5SWITCH
8032 +       if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1)){
8033 +#if 0
8034 +               rcv_mask = SPI_read(2,0,0x10);                  // Receive mask
8035 +               rcv_mask |= 0x4F;
8036 +               for(i=0;i<4;i++){
8037 +                       reg_val = BIT(26)|(i<<21)|(10<<16);
8038 +                       SPI_write(3,0,1,reg_val);
8039 +                       msleep(10);
8040 +                       reg_val = SPI_read(3,0,2);
8041 +                       if(reg_val & 0x0c00){
8042 +                               printk("Port%d:Giga mode\n",i);
8043 +                               SPI_write(1,i,0x00,0x300701B1);
8044 +                               SPI_write(1,i,0x00,0x10070181);
8045 +                               switch_pre_link[i]=LINK_UP;
8046 +                               switch_pre_speed[i]=GMAC_SPEED_1000;
8047 +                       }
8048 +                       else{
8049 +                               reg_val = BIT(26)|(i<<21)|(5<<16);
8050 +                               SPI_write(3,0,1,reg_val);
8051 +                               msleep(10);
8052 +                               ability = (reg_val = SPI_read(3,0,2)&0x5e0) >>5;
8053 +                               if ((ability & 0x0C)) /* 100M full duplex */
8054 +                               {
8055 +                                       SPI_write(1,i,0x00,0x30050472);
8056 +                                       SPI_write(1,i,0x00,0x10050442);
8057 +                                       printk("Port%d:100M\n",i);
8058 +                                       switch_pre_link[i]=LINK_UP;
8059 +                               switch_pre_speed[i]=GMAC_SPEED_100;
8060 +                               }
8061 +                               else if((ability & 0x03)) /* 10M full duplex */
8062 +                               {
8063 +                                       SPI_write(1,i,0x00,0x30050473);
8064 +                                       SPI_write(1,i,0x00,0x10050443);
8065 +                                       printk("Port%d:10M\n",i);
8066 +                                       switch_pre_link[i]=LINK_UP;
8067 +                                       switch_pre_speed[i]=GMAC_SPEED_10;
8068 +                               }
8069 +                               else{
8070 +                                       SPI_write(1,i,0x00,BIT(16));                    // disable RX
8071 +                                       SPI_write(5,0,0x0E,BIT(i));                     // dicard packet
8072 +                                       while((SPI_read(5,0,0x0C)&BIT(i))==0)           // wait to be empty
8073 +                                               msleep(1);
8074 +
8075 +                                       SPI_write(1,i,0x00,0x20000030);                 // PORT_RST
8076 +                                       switch_pre_link[i]=LINK_DOWN;
8077 +                                       switch_pre_speed[i]=GMAC_SPEED_10;
8078 +                                       rcv_mask &= ~BIT(i);
8079 +                                       SPI_write(2,0,0x10,rcv_mask);                   // Disable Receive
8080 +                               }
8081 +                       }
8082 +               }
8083 +#endif
8084 +               gmac_get_switch_status(dev);
8085 +               gmac_write_reg(tp->base_addr, GMAC_STATUS, 0x7d, 0x0000007f);
8086 +//             SPI_write(2,0,0x10,rcv_mask);                   // Enable Receive
8087 +               return ;
8088 +       }
8089 +#endif
8090 +
8091 +       reg_val = gmac_get_phy_vendor(tp->phy_addr);
8092 +       printk("GMAC-%d Addr %d Vendor ID: 0x%08x\n", tp->port_id, tp->phy_addr, reg_val);
8093 +
8094 +       switch (tp->phy_mode)
8095 +       {
8096 +               case GMAC_PHY_GMII:
8097 +               mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
8098 +               #ifdef CONFIG_SL3516_ASIC
8099 +               mii_write(tp->phy_addr,0x09,0x0300); /* advertise 1000M full/half duplex */
8100 +               #else
8101 +               mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M full/half duplex */
8102 +               #endif
8103 +               break;
8104 +               case GMAC_PHY_RGMII_100:
8105 +               mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
8106 +               mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M */
8107 +               break;
8108 +               case GMAC_PHY_RGMII_1000:
8109 +               mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
8110 +               #ifdef CONFIG_SL3516_ASIC
8111 +               mii_write(tp->phy_addr,0x09,0x0300); /* advertise 1000M full/half duplex */
8112 +               #else
8113 +               mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M full/half duplex */
8114 +               #endif
8115 +               break;
8116 +               case GMAC_PHY_MII:
8117 +               default:
8118 +               mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
8119 +               mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M */
8120 +               break;
8121 +       }
8122 +
8123 +       mii_write(tp->phy_addr,0x18,0x0041);    // Phy active led
8124 +       if (tp->auto_nego_cfg)
8125 +       {
8126 +               reg_val = 0x1200 | (1 << 15);
8127 +               mii_write(tp->phy_addr,0x00,reg_val); /* Enable and Restart Auto-Negotiation */
8128 +               mdelay(500);
8129 +               reg_val &= ~(1 << 15);
8130 +               mii_write(tp->phy_addr, 0x00, reg_val);
8131 +       }
8132 +       else
8133 +       {
8134 +               reg_val = 0;
8135 +               reg_val |= (tp->full_duplex_cfg) ? (1 << 8) : 0;
8136 +               reg_val |= (tp->speed_cfg == GMAC_SPEED_1000) ? (1 << 6) : 0;
8137 +               reg_val |= (tp->speed_cfg == GMAC_SPEED_100) ? (1 << 13) : 0;
8138 +               mii_write(tp->phy_addr, 0x00, reg_val);
8139 +               mdelay(100);
8140 +
8141 +               reg_val |= (1 << 15);   // Reset PHY;
8142 +               mii_write(tp->phy_addr, 0x00, reg_val);
8143 +       }
8144 +
8145 +       status.bits32 = 0;
8146 +       /* set PHY operation mode */
8147 +       status.bits.mii_rmii = tp->phy_mode;
8148 +       status.bits.reserved = 1;
8149 +       mdelay(100);
8150 +       while (((reg_val=mii_read(tp->phy_addr,0x01)) & 0x00000004)!=0x04)
8151 +       {
8152 +               msleep(100);
8153 +               i++;
8154 +               if (i > 30)
8155 +               break;
8156 +       }
8157 +       if (i>30)
8158 +       {
8159 +               tp->pre_phy_status = LINK_DOWN;
8160 +               status.bits.link = LINK_DOWN;
8161 +               //              clear_bit(__LINK_STATE_START, &dev->state);
8162 +               printk("Link Down (0x%04x) ", reg_val);
8163 +               if(Giga_switch == 1)
8164 +               {
8165 +                               wan_port_id = 1;
8166 +#ifdef CONFIG_SL351x_SYSCTL
8167 +                               storlink_ctl.link[ wan_port_id] = 0;
8168 +#endif
8169 +               }
8170 +               else
8171 +               {
8172 +#ifdef CONFIG_SL351x_SYSCTL
8173 +                               storlink_ctl.link[ tp->port_id] = 0;
8174 +#endif
8175 +               }
8176 +       }
8177 +       else
8178 +       {
8179 +               tp->pre_phy_status = LINK_UP;
8180 +               status.bits.link = LINK_UP;
8181 +               //              set_bit(__LINK_STATE_START, &dev->state);
8182 +               printk("Link Up (0x%04x) ",reg_val);
8183 +               if(Giga_switch == 1)
8184 +               {
8185 +                               wan_port_id = 1;
8186 +#ifdef CONFIG_SL351x_SYSCTL
8187 +                               storlink_ctl.link[ wan_port_id] = 1;
8188 +#endif
8189 +               }
8190 +               else
8191 +               {
8192 +#ifdef CONFIG_SL351x_SYSCTL
8193 +                               storlink_ctl.link[ tp->port_id] = 1;
8194 +#endif
8195 +               }
8196 +       }
8197 +       //    value = mii_read(PHY_ADDR,0x05);
8198 +
8199 +       ability = (mii_read(tp->phy_addr,0x05) & 0x05E0) >> 5;
8200 +
8201 +       //#ifdef CONFIG_SL3516_ASIC
8202 +       reg_val = mii_read(tp->phy_addr,10);
8203 +       printk("MII REG 10 = 0x%x\n",reg_val);
8204 +
8205 +       if ((reg_val & 0x0800) == 0x0800)
8206 +       {
8207 +               status.bits.duplex = 1;
8208 +               status.bits.speed = 2;
8209 +               if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
8210 +               status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
8211 +
8212 +               printk(" 1000M/Full \n");
8213 +       }
8214 +       else if ((reg_val & 0x0400) == 0x0400)
8215 +       {
8216 +               status.bits.duplex = 0;
8217 +               status.bits.speed = 2;
8218 +               if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
8219 +               status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
8220 +
8221 +               printk(" 1000M/Half \n");
8222 +       }
8223 +       //#endif
8224 +       else
8225 +       {
8226 +               #ifdef CONFIG_SL3516_ASIC
8227 +               if (status.bits.mii_rmii == GMAC_PHY_RGMII_1000)
8228 +               status.bits.mii_rmii = GMAC_PHY_RGMII_100;
8229 +               #endif
8230 +               printk("MII REG 5 (bit 5:15) = 0x%x\n", ability);
8231 +               if ((ability & 0x08)==0x08) /* 100M full duplex */
8232 +               {
8233 +                       status.bits.duplex = 1;
8234 +                       status.bits.speed = 1;
8235 +                       printk(" 100M/Full\n");
8236 +
8237 +               }
8238 +               else if ((ability & 0x04)==0x04) /* 100M half duplex */
8239 +               {
8240 +                       status.bits.duplex = 0;
8241 +                       status.bits.speed = 1;
8242 +                       printk(" 100M/Half\n");
8243 +
8244 +               }
8245 +               else if ((ability & 0x02)==0x02) /* 10M full duplex */
8246 +               {
8247 +                       status.bits.duplex = 1;
8248 +                       status.bits.speed = 0;
8249 +                       printk(" 10M/Full\n");
8250 +
8251 +               }
8252 +               else if ((ability & 0x01)==0x01) /* 10M half duplex */
8253 +               {
8254 +                       status.bits.duplex = 0;
8255 +                       status.bits.speed = 0;
8256 +                       printk(" 10M/Half\n");
8257 +
8258 +               }
8259 +       }
8260 +       if ((ability & 0x20)==0x20)
8261 +       {
8262 +               tp->flow_control_enable = 1;
8263 +               printk("Flow Control Enable.\n");
8264 +       }
8265 +       else
8266 +       {
8267 +               tp->flow_control_enable = 0;
8268 +               printk("Flow Control Disable.\n");
8269 +       }
8270 +       tp->full_duplex_status = status.bits.duplex;
8271 +       tp->speed_status = status.bits.speed;
8272 +       if (!tp->auto_nego_cfg)
8273 +       {
8274 +               status.bits.duplex = tp->full_duplex_cfg;
8275 +               status.bits.speed = tp->speed_cfg;
8276 +       }
8277 +       toe_gmac_disable_tx_rx(dev);
8278 +       mdelay(10);
8279 +       gmac_write_reg(tp->base_addr, GMAC_STATUS, status.bits32, 0x0000007f);
8280 +       toe_gmac_enable_tx_rx(dev);
8281 +}
8282 +
8283 +/*----------------------------------------------------------------------
8284 +* gmac_phy_thread
8285 +*----------------------------------------------------------------------*/
8286 +static int gmac_phy_thread (void *data)
8287 +{
8288 +       struct net_device   *dev = data;
8289 +       GMAC_INFO_T *tp = dev->priv;
8290 +       unsigned long       timeout;
8291 +
8292 +    daemonize("%s", dev->name);
8293 +       allow_signal(SIGTERM);
8294 +//     reparent_to_init();
8295 +//     spin_lock_irq(&current->sigmask_lock);
8296 +//     sigemptyset(&current->blocked);
8297 +//     recalc_sigpending(current);
8298 +//     spin_unlock_irq(&current->sigmask_lock);
8299 +//     strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
8300 +//     current->comm[sizeof(current->comm) - 1] = '\0';
8301 +
8302 +       while (1)
8303 +       {
8304 +           timeout = next_tick;
8305 +               do
8306 +               {
8307 +                       timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
8308 +               } while (!signal_pending (current) && (timeout > 0));
8309 +
8310 +               if (signal_pending (current))
8311 +               {
8312 +//                     spin_lock_irq(&current->sigmask_lock);
8313 +                       flush_signals(current);
8314 +//                     spin_unlock_irq(&current->sigmask_lock);
8315 +               }
8316 +
8317 +               if (tp->time_to_die)
8318 +                       break;
8319 +
8320 +               // printk("%s : Polling MAC %d PHY Status...\n",__func__, tp->port_id);
8321 +               rtnl_lock ();
8322 +               if (tp->auto_nego_cfg){
8323 +#ifdef VITESSE_G5SWITCH
8324 +                       if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1))
8325 +                               gmac_get_switch_status(dev);
8326 +                       else
8327 +#endif
8328 +                               gmac_get_phy_status(dev); //temp remove
8329 +               }
8330 +               rtnl_unlock ();
8331 +       }
8332 +       complete_and_exit (&tp->thr_exited, 0);
8333 +}
8334 +
8335 +/*----------------------------------------------------------------------
8336 +* gmac_get_switch_status
8337 +*----------------------------------------------------------------------*/
8338 +#ifdef VITESSE_G5SWITCH
8339 +void gmac_get_switch_status(struct net_device *dev)
8340 +{
8341 +       GMAC_INFO_T *tp = dev->priv;
8342 +       GMAC_CONFIG0_T  config0,config0_mask;
8343 +       unsigned int    switch_port_id;
8344 +       int get_link=0;
8345 +
8346 +       get_link = Get_Set_port_status();
8347 +       if(get_link){                           // link
8348 +               if(ever_dwon){
8349 +                       ever_dwon = 0;
8350 +                       toe_gmac_enable_tx_rx(dev);
8351 +                       netif_wake_queue(dev);
8352 +                       set_bit(__LINK_STATE_START, &dev->state);
8353 +               }
8354 +       }
8355 +       else{                                   // all down
8356 +               //printk("All link down\n");
8357 +               ever_dwon=1;
8358 +               netif_stop_queue(dev);
8359 +               toe_gmac_disable_tx_rx(dev);
8360 +               clear_bit(__LINK_STATE_START, &dev->state);
8361 +       }
8362 +
8363 +       if ( tp->port_id == 1 )
8364 +               switch_port_id = 0;
8365 +#ifdef CONFIG_SL351x_SYSCTL
8366 +       if (get_link)
8367 +       {
8368 +               storlink_ctl.link[switch_port_id] = 1;
8369 +       }
8370 +       else
8371 +       {
8372 +               storlink_ctl.link[switch_port_id] = 0;
8373 +       }
8374 +       if (storlink_ctl.pauseoff == 1)
8375 +               {
8376 +                       if (tp->flow_control_enable == 1)
8377 +                       {
8378 +                               config0.bits32 = 0;
8379 +                               config0_mask.bits32 = 0;
8380 +                               config0.bits.tx_fc_en = 0; /* disable tx flow control */
8381 +                               config0.bits.rx_fc_en = 0; /* disable rx flow control */
8382 +                               config0_mask.bits.tx_fc_en = 1;
8383 +                               config0_mask.bits.rx_fc_en = 1;
8384 +                               gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
8385 +                               printk("Disable SWITCH Flow Control...\n");
8386 +                       }
8387 +                               tp->flow_control_enable = 0;
8388 +               }
8389 +               else
8390 +#endif
8391 +               {
8392 +                       if (tp->flow_control_enable == 0)
8393 +                       {
8394 +                               config0.bits32 = 0;
8395 +                               config0_mask.bits32 = 0;
8396 +                               config0.bits.tx_fc_en = 1; /* enable tx flow control */
8397 +                               config0.bits.rx_fc_en = 1; /* enable rx flow control */
8398 +                               config0_mask.bits.tx_fc_en = 1;
8399 +                               config0_mask.bits.rx_fc_en = 1;
8400 +                               gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
8401 +                               printk("Enable SWITCH Flow Control...\n");
8402 +                       }
8403 +                       tp->flow_control_enable = 1;
8404 +               }
8405 +       return ;
8406 +
8407 +}
8408 +#endif
8409 +
8410 +/*----------------------------------------------------------------------
8411 +* gmac_get_phy_status
8412 +*----------------------------------------------------------------------*/
8413 +void gmac_get_phy_status(struct net_device *dev)
8414 +{
8415 +       GMAC_INFO_T *tp = dev->priv;
8416 +       GMAC_CONFIG0_T  config0,config0_mask;
8417 +       GMAC_STATUS_T   status, old_status;
8418 +       unsigned int    reg_val,ability,wan_port_id;
8419 +
8420 +       old_status.bits32 = status.bits32 = gmac_read_reg(tp->base_addr, GMAC_STATUS);
8421 +
8422 +
8423 +       /* read PHY status register */
8424 +       reg_val = mii_read(tp->phy_addr,0x01);
8425 +       if ((reg_val & 0x0024) == 0x0024) /* link is established and auto_negotiate process completed */
8426 +       {
8427 +               ability = (mii_read(tp->phy_addr,0x05) & 0x05E0) >> 5;
8428 +               /* read PHY Auto-Negotiation Link Partner Ability Register */
8429 +               #ifdef CONFIG_SL3516_ASIC
8430 +               reg_val = mii_read(tp->phy_addr,10);
8431 +               if ((reg_val & 0x0800) == 0x0800)
8432 +               {
8433 +                       status.bits.duplex = 1;
8434 +                       status.bits.speed = 2;
8435 +                       if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
8436 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
8437 +               }
8438 +               else if ((reg_val & 0x0400) == 0x0400)
8439 +               {
8440 +                       status.bits.duplex = 0;
8441 +                       status.bits.speed = 2;
8442 +                       if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
8443 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
8444 +               }
8445 +               else
8446 +               #endif
8447 +               {
8448 +                       #ifdef CONFIG_SL3516_ASIC
8449 +                       if (status.bits.mii_rmii == GMAC_PHY_RGMII_1000)
8450 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100;
8451 +                       #endif
8452 +                       if ((ability & 0x08)==0x08) /* 100M full duplex */
8453 +                       {
8454 +                               status.bits.duplex = 1;
8455 +                               status.bits.speed = 1;
8456 +                       }
8457 +                       else if ((ability & 0x04)==0x04) /* 100M half duplex */
8458 +                       {
8459 +                               status.bits.duplex = 0;
8460 +                               status.bits.speed = 1;
8461 +                       }
8462 +                       else if ((ability & 0x02)==0x02) /* 10M full duplex */
8463 +                       {
8464 +                               status.bits.duplex = 1;
8465 +                               status.bits.speed = 0;
8466 +                       }
8467 +                       else if ((ability & 0x01)==0x01) /* 10M half duplex */
8468 +                       {
8469 +                               status.bits.duplex = 0;
8470 +                               status.bits.speed = 0;
8471 +                       }
8472 +               }
8473 +               status.bits.link = LINK_UP; /* link up */
8474 +               if(Giga_switch==1)
8475 +               {
8476 +                               wan_port_id = 1;
8477 +#ifdef CONFIG_SL351x_SYSCTL
8478 +                               storlink_ctl.link[ wan_port_id] = 1;
8479 +               }
8480 +               else
8481 +               {
8482 +                               storlink_ctl.link[ tp->port_id] = 1;
8483 +#endif
8484 +               }
8485 +               if ((ability & 0x20)==0x20)
8486 +               {
8487 +                       if (tp->flow_control_enable == 0)
8488 +                       {
8489 +                               config0.bits32 = 0;
8490 +                               config0_mask.bits32 = 0;
8491 +                               config0.bits.tx_fc_en = 1; /* enable tx flow control */
8492 +                               config0.bits.rx_fc_en = 1; /* enable rx flow control */
8493 +                               config0_mask.bits.tx_fc_en = 1;
8494 +                               config0_mask.bits.rx_fc_en = 1;
8495 +                               gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
8496 +                               printk("GMAC-%d Flow Control Enable.\n", tp->port_id);
8497 +                       }
8498 +                       tp->flow_control_enable = 1;
8499 +               }
8500 +               else
8501 +               {
8502 +                       if (tp->flow_control_enable == 1)
8503 +                       {
8504 +                               config0.bits32 = 0;
8505 +                               config0_mask.bits32 = 0;
8506 +                               config0.bits.tx_fc_en = 0; /* disable tx flow control */
8507 +                               config0.bits.rx_fc_en = 0; /* disable rx flow control */
8508 +                               config0_mask.bits.tx_fc_en = 1;
8509 +                               config0_mask.bits.rx_fc_en = 1;
8510 +                               gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
8511 +                               printk("GMAC-%d Flow Control Disable.\n", tp->port_id);
8512 +                       }
8513 +                       tp->flow_control_enable = 0;
8514 +               }
8515 +
8516 +               if (tp->pre_phy_status == LINK_DOWN)
8517 +               {
8518 +                       printk("GMAC-%d LINK_UP......\n",tp->port_id);
8519 +                       tp->pre_phy_status = LINK_UP;
8520 +               }
8521 +       }
8522 +       else
8523 +       {
8524 +               status.bits.link = LINK_DOWN; /* link down */
8525 +               if(Giga_switch == 1)
8526 +               {
8527 +                               wan_port_id = 1;
8528 +#ifdef CONFIG_SL351x_SYSCTL
8529 +                               storlink_ctl.link[ wan_port_id] = 0;
8530 +               }
8531 +               else
8532 +               {
8533 +                               storlink_ctl.link[ tp->port_id] = 0;
8534 +#endif
8535 +               }
8536 +               if (tp->pre_phy_status == LINK_UP)
8537 +               {
8538 +                       printk("GMAC-%d LINK_Down......\n",tp->port_id);
8539 +                       tp->pre_phy_status = LINK_DOWN;
8540 +               }
8541 +       }
8542 +
8543 +       tp->full_duplex_status = status.bits.duplex;
8544 +       tp->speed_status = status.bits.speed;
8545 +       if (!tp->auto_nego_cfg)
8546 +       {
8547 +               status.bits.duplex = tp->full_duplex_cfg;
8548 +               status.bits.speed = tp->speed_cfg;
8549 +       }
8550 +
8551 +       if (old_status.bits32 != status.bits32)
8552 +       {
8553 +               netif_stop_queue(dev);
8554 +               toe_gmac_disable_tx_rx(dev);
8555 +               clear_bit(__LINK_STATE_START, &dev->state);
8556 +               printk("GMAC-%d Change Status Bits 0x%x-->0x%x\n",tp->port_id, old_status.bits32, status.bits32);
8557 +               mdelay(10); // let GMAC consume packet
8558 +               gmac_write_reg(tp->base_addr, GMAC_STATUS, status.bits32, 0x0000007f);
8559 +               if (status.bits.link == LINK_UP)
8560 +               {
8561 +                       toe_gmac_enable_tx_rx(dev);
8562 +                       netif_wake_queue(dev);
8563 +                       set_bit(__LINK_STATE_START, &dev->state);
8564 +               }
8565 +       }
8566 +}
8567 +
8568 +/***************************************/
8569 +/* define GPIO module base address     */
8570 +/***************************************/
8571 +#define GPIO_BASE_ADDR  (IO_ADDRESS(SL2312_GPIO_BASE))
8572 +#define GPIO_BASE_ADDR1  (IO_ADDRESS(SL2312_GPIO_BASE1))
8573 +
8574 +/* define GPIO pin for MDC/MDIO */
8575 +#ifdef CONFIG_SL3516_ASIC
8576 +#define H_MDC_PIN           22
8577 +#define H_MDIO_PIN          21
8578 +#define G_MDC_PIN           22
8579 +#define G_MDIO_PIN          21
8580 +#else
8581 +#define H_MDC_PIN           3
8582 +#define H_MDIO_PIN          2
8583 +#define G_MDC_PIN           0
8584 +#define G_MDIO_PIN          1
8585 +#endif
8586 +
8587 +//#define GPIO_MDC             0x80000000
8588 +//#define GPIO_MDIO            0x00400000
8589 +
8590 +static unsigned int GPIO_MDC = 0;
8591 +static unsigned int GPIO_MDIO = 0;
8592 +static unsigned int GPIO_MDC_PIN = 0;
8593 +static unsigned int GPIO_MDIO_PIN = 0;
8594 +
8595 +// For PHY test definition!!
8596 +#define LPC_EECK               0x02
8597 +#define LPC_EDIO               0x04
8598 +#define LPC_GPIO_SET           3
8599 +#define LPC_BASE_ADDR          IO_ADDRESS(IT8712_IO_BASE)
8600 +#define inb_gpio(x)            inb(LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
8601 +#define outb_gpio(x, y)                outb(y, LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
8602 +
8603 +enum GPIO_REG
8604 +{
8605 +    GPIO_DATA_OUT   = 0x00,
8606 +    GPIO_DATA_IN    = 0x04,
8607 +    GPIO_PIN_DIR    = 0x08,
8608 +    GPIO_BY_PASS    = 0x0c,
8609 +    GPIO_DATA_SET   = 0x10,
8610 +    GPIO_DATA_CLEAR = 0x14,
8611 +};
8612 +/***********************/
8613 +/*    MDC : GPIO[31]   */
8614 +/*    MDIO: GPIO[22]   */
8615 +/***********************/
8616 +
8617 +/***************************************************
8618 +* All the commands should have the frame structure:
8619 +*<PRE><ST><OP><PHYAD><REGAD><TA><DATA><IDLE>
8620 +****************************************************/
8621 +
8622 +/*****************************************************************
8623 +* Inject a bit to NWay register through CSR9_MDC,MDIO
8624 +*******************************************************************/
8625 +void mii_serial_write(char bit_MDO) // write data into mii PHY
8626 +{
8627 +#ifdef CONFIG_SL2312_LPC_IT8712
8628 +       unsigned char iomode,status;
8629 +
8630 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
8631 +       iomode |= (LPC_EECK|LPC_EDIO) ;                         // Set EECK,EDIO,EECS output
8632 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
8633 +
8634 +       if(bit_MDO)
8635 +       {
8636 +               status = inb_gpio( LPC_GPIO_SET);
8637 +               status |= LPC_EDIO ;            //EDIO high
8638 +               outb_gpio(LPC_GPIO_SET, status);
8639 +       }
8640 +       else
8641 +       {
8642 +               status = inb_gpio( LPC_GPIO_SET);
8643 +               status &= ~(LPC_EDIO) ;         //EDIO low
8644 +               outb_gpio(LPC_GPIO_SET, status);
8645 +       }
8646 +
8647 +       status |= LPC_EECK ;            //EECK high
8648 +       outb_gpio(LPC_GPIO_SET, status);
8649 +
8650 +       status &= ~(LPC_EECK) ;         //EECK low
8651 +       outb_gpio(LPC_GPIO_SET, status);
8652 +
8653 +#else
8654 +    unsigned int addr;
8655 +    unsigned int value;
8656 +
8657 +    addr = GPIO_BASE_ADDR + GPIO_PIN_DIR;
8658 +    value = readl(addr) | GPIO_MDC | GPIO_MDIO; /* set MDC/MDIO Pin to output */
8659 +    writel(value,addr);
8660 +    if(bit_MDO)
8661 +    {
8662 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
8663 +        writel(GPIO_MDIO,addr); /* set MDIO to 1 */
8664 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
8665 +        writel(GPIO_MDC,addr); /* set MDC to 1 */
8666 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
8667 +        writel(GPIO_MDC,addr); /* set MDC to 0 */
8668 +    }
8669 +    else
8670 +    {
8671 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
8672 +        writel(GPIO_MDIO,addr); /* set MDIO to 0 */
8673 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
8674 +        writel(GPIO_MDC,addr); /* set MDC to 1 */
8675 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
8676 +        writel(GPIO_MDC,addr); /* set MDC to 0 */
8677 +    }
8678 +
8679 +#endif
8680 +}
8681 +
8682 +/**********************************************************************
8683 +* read a bit from NWay register through CSR9_MDC,MDIO
8684 +***********************************************************************/
8685 +unsigned int mii_serial_read(void) // read data from mii PHY
8686 +{
8687 +#ifdef CONFIG_SL2312_LPC_IT8712
8688 +       unsigned char iomode,status;
8689 +       unsigned int value ;
8690 +
8691 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
8692 +       iomode &= ~(LPC_EDIO) ;         // Set EDIO input
8693 +       iomode |= (LPC_EECK) ;          // Set EECK,EECS output
8694 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
8695 +
8696 +       status = inb_gpio( LPC_GPIO_SET);
8697 +       status |= LPC_EECK ;            //EECK high
8698 +       outb_gpio(LPC_GPIO_SET, status);
8699 +
8700 +       status &= ~(LPC_EECK) ;         //EECK low
8701 +       outb_gpio(LPC_GPIO_SET, status);
8702 +
8703 +       value = inb_gpio( LPC_GPIO_SET);
8704 +
8705 +       value = value>>2 ;
8706 +       value &= 0x01;
8707 +
8708 +       return value ;
8709 +
8710 +#else
8711 +    unsigned int *addr;
8712 +    unsigned int value;
8713 +
8714 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_PIN_DIR);
8715 +    value = readl(addr) & ~GPIO_MDIO; //0xffbfffff;   /* set MDC to output and MDIO to input */
8716 +    writel(value,addr);
8717 +
8718 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_SET);
8719 +    writel(GPIO_MDC,addr); /* set MDC to 1 */
8720 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
8721 +    writel(GPIO_MDC,addr); /* set MDC to 0 */
8722 +
8723 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_IN);
8724 +    value = readl(addr);
8725 +    value = (value & (1<<GPIO_MDIO_PIN)) >> GPIO_MDIO_PIN;
8726 +    return(value);
8727 +
8728 +#endif
8729 +}
8730 +
8731 +/***************************************
8732 +* preamble + ST
8733 +***************************************/
8734 +void mii_pre_st(void)
8735 +{
8736 +    unsigned char i;
8737 +
8738 +    for(i=0;i<32;i++) // PREAMBLE
8739 +        mii_serial_write(1);
8740 +    mii_serial_write(0); // ST
8741 +    mii_serial_write(1);
8742 +}
8743 +
8744 +
8745 +/******************************************
8746 +* Read MII register
8747 +* phyad -> physical address
8748 +* regad -> register address
8749 +***************************************** */
8750 +unsigned int mii_read(unsigned char phyad,unsigned char regad)
8751 +{
8752 +    unsigned int i,value;
8753 +    unsigned int bit;
8754 +
8755 +    if (phyad == GPHY_ADDR)
8756 +    {
8757 +        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
8758 +        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
8759 +    }
8760 +    else
8761 +    {
8762 +        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
8763 +        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
8764 +    }
8765 +    GPIO_MDC = (1<<GPIO_MDC_PIN);
8766 +    GPIO_MDIO = (1<<GPIO_MDIO_PIN);
8767 +
8768 +    mii_pre_st(); // PRE+ST
8769 +    mii_serial_write(1); // OP
8770 +    mii_serial_write(0);
8771 +
8772 +    for (i=0;i<5;i++) { // PHYAD
8773 +        bit= ((phyad>>(4-i)) & 0x01) ? 1 :0 ;
8774 +        mii_serial_write(bit);
8775 +    }
8776 +
8777 +    for (i=0;i<5;i++) { // REGAD
8778 +        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
8779 +        mii_serial_write(bit);
8780 +    }
8781 +
8782 +    mii_serial_read(); // TA_Z
8783 +//    if((bit=mii_serial_read()) !=0 ) // TA_0
8784 +//    {
8785 +//        return(0);
8786 +//    }
8787 +    value=0;
8788 +    for (i=0;i<16;i++) { // READ DATA
8789 +        bit=mii_serial_read();
8790 +        value += (bit<<(15-i)) ;
8791 +    }
8792 +
8793 +    mii_serial_write(0); // dumy clock
8794 +    mii_serial_write(0); // dumy clock
8795 +
8796 +       //printk("%s: phy_addr=0x%x reg_addr=0x%x value=0x%x \n",__func__,phyad,regad,value);
8797 +    return(value);
8798 +}
8799 +
8800 +/******************************************
8801 +* Write MII register
8802 +* phyad -> physical address
8803 +* regad -> register address
8804 +* value -> value to be write
8805 +***************************************** */
8806 +void mii_write(unsigned char phyad,unsigned char regad,unsigned int value)
8807 +{
8808 +    unsigned int i;
8809 +    char bit;
8810 +
8811 +       printk("%s: phy_addr=0x%x reg_addr=0x%x value=0x%x \n",__func__,phyad,regad,value);
8812 +    if (phyad == GPHY_ADDR)
8813 +    {
8814 +        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
8815 +        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
8816 +    }
8817 +    else
8818 +    {
8819 +        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
8820 +        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
8821 +    }
8822 +    GPIO_MDC = (1<<GPIO_MDC_PIN);
8823 +    GPIO_MDIO = (1<<GPIO_MDIO_PIN);
8824 +
8825 +    mii_pre_st(); // PRE+ST
8826 +    mii_serial_write(0); // OP
8827 +    mii_serial_write(1);
8828 +    for (i=0;i<5;i++) { // PHYAD
8829 +        bit= ((phyad>>(4-i)) & 0x01) ? 1 :0 ;
8830 +        mii_serial_write(bit);
8831 +    }
8832 +
8833 +    for (i=0;i<5;i++) { // REGAD
8834 +        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
8835 +        mii_serial_write(bit);
8836 +    }
8837 +    mii_serial_write(1); // TA_1
8838 +    mii_serial_write(0); // TA_0
8839 +
8840 +    for (i=0;i<16;i++) { // OUT DATA
8841 +        bit= ((value>>(15-i)) & 0x01) ? 1 : 0 ;
8842 +        mii_serial_write(bit);
8843 +    }
8844 +    mii_serial_write(0); // dumy clock
8845 +    mii_serial_write(0); // dumy clock
8846 +}
8847 +
8848 +/*----------------------------------------------------------------------
8849 +* gmac_set_rx_mode
8850 +*----------------------------------------------------------------------*/
8851 +static void gmac_set_rx_mode(struct net_device *dev)
8852 +{
8853 +    GMAC_RX_FLTR_T      filter;
8854 +       unsigned int        mc_filter[2];       /* Multicast hash filter */
8855 +    int                 bit_nr;
8856 +       unsigned int        i;
8857 +       GMAC_INFO_T             *tp = dev->priv;
8858 +
8859 +//    printk("%s : dev->flags = %x \n",__func__,dev->flags);
8860 +//    dev->flags |= IFF_ALLMULTI;  /* temp */
8861 +    filter.bits32 = 0;
8862 +    filter.bits.error = 0;
8863 +       if (dev->flags & IFF_PROMISC)
8864 +       {
8865 +           filter.bits.error = 1;
8866 +        filter.bits.promiscuous = 1;
8867 +        filter.bits.broadcast = 1;
8868 +        filter.bits.multicast = 1;
8869 +        filter.bits.unicast = 1;
8870 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
8871 +       }
8872 +       else if (dev->flags & IFF_ALLMULTI)
8873 +       {
8874 +//        filter.bits.promiscuous = 1;
8875 +        filter.bits.broadcast = 1;
8876 +        filter.bits.multicast = 1;
8877 +        filter.bits.unicast = 1;
8878 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
8879 +       }
8880 +       else
8881 +       {
8882 +               struct dev_mc_list *mclist;
8883 +
8884 +//        filter.bits.promiscuous = 1;
8885 +        filter.bits.broadcast = 1;
8886 +        filter.bits.multicast = 1;
8887 +        filter.bits.unicast = 1;
8888 +               mc_filter[1] = mc_filter[0] = 0;
8889 +               for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;i++, mclist = mclist->next)
8890 +               {
8891 +            bit_nr = ether_crc(ETH_ALEN,mclist->dmi_addr) & 0x0000003f;
8892 +            if (bit_nr < 32)
8893 +            {
8894 +                mc_filter[0] = mc_filter[0] | (1<<bit_nr);
8895 +            }
8896 +            else
8897 +            {
8898 +                mc_filter[1] = mc_filter[1] | (1<<(bit_nr-32));
8899 +            }
8900 +               }
8901 +       }
8902 +    gmac_write_reg(tp->base_addr,GMAC_RX_FLTR,filter.bits32,0xffffffff);  //chech base address!!!
8903 +    gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,mc_filter[0],0xffffffff);
8904 +    gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,mc_filter[1],0xffffffff);
8905 +    return;
8906 +}
8907 +
8908 +#ifdef CONFIG_SL_NAPI
8909 +/*----------------------------------------------------------------------
8910 +* gmac_rx_poll
8911 +*----------------------------------------------------------------------*/
8912 +static int gmac_rx_poll(struct net_device *dev, int *budget)
8913 +{
8914 +       TOE_INFO_T                      *toe;
8915 +    GMAC_RXDESC_T      *curr_desc;
8916 +       struct sk_buff          *skb;
8917 +    DMA_RWPTR_T                        rwptr;
8918 +       unsigned int            pkt_size;
8919 +       unsigned int        desc_count;
8920 +       unsigned int        good_frame, chksum_status, rx_status;
8921 +       int                 rx_pkts_num = 0;
8922 +       int                 quota = min(dev->quota, *budget);
8923 +       GMAC_INFO_T                     *tp = (GMAC_INFO_T *)dev->priv;
8924 +       unsigned int            status4;
8925 +       volatile DMA_RWPTR_T    fq_rwptr;
8926 +       int                                     max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
8927 +       //unsigned long         rx_old_bytes;
8928 +       struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
8929 +       //unsigned long long    rx_time;
8930 +
8931 +
8932 +
8933 +#if 1
8934 +       if (do_again)
8935 +       {
8936 +                       toe_gmac_fill_free_q();
8937 +                       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
8938 +                       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
8939 +                       //printk("\n%s:: do_again toe_gmac_fill_free_q =======>status4=0x%x =====fq_rwptr =0x%8x======>JKJKJKJKJKJKJKJKJ \n", __func__,status4,fq_rwptr.bits32);
8940 +                       if (fq_rwptr.bits.wptr != fq_rwptr.bits.rptr)
8941 +                       {
8942 +                                               //status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
8943 +                                               do_again =0;
8944 +                                               //netif_rx_complete(dev);
8945 +                                               gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4, 0x1);
8946 +                                               fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
8947 +                                               rwptr.bits32 = readl(&tp->default_qhdr->word1);
8948 +                       }
8949 +                       else
8950 +                               return 1;
8951 +       }
8952 +#endif
8953 +       rwptr.bits32 = readl(&tp->default_qhdr->word1);
8954 +#if 0
8955 +       if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
8956 +       {
8957 +               mac_stop_txdma((struct net_device *)tp->dev);
8958 +               printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
8959 +                               rwptr.bits32, tp->rx_rwptr.bits.rptr);
8960 +               while(1);
8961 +       }
8962 +#endif
8963 +       toe = (TOE_INFO_T *)&toe_private_data;
8964 +
8965 +       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
8966 +       //printk("%s:---Before-------------->Default Queue HW RW ptr (0x%8x),   fq_rwptr =0x%8x \n",__func__,rwptr.bits32,fq_rwptr.bits32 );
8967 +       //printk("%s:---Before while   rx_pkts_num=%d------rx_finished_idx=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rx_finished_idx,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
8968 +//     while ((--max_cnt) && (rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
8969 +
8970 +       while ((rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
8971 +       {
8972 +
8973 +       curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
8974 +               tp->default_q_cnt++;
8975 +       tp->rx_curr_desc = (unsigned int)curr_desc;
8976 +       rx_status = curr_desc->word0.bits.status;
8977 +       chksum_status = curr_desc->word0.bits.chksum_status;
8978 +       tp->rx_status_cnt[rx_status]++;
8979 +       tp->rx_chksum_cnt[chksum_status]++;
8980 +        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
8981 +               desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
8982 +               good_frame=1;
8983 +               if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
8984 +                       || (pkt_size < 60)
8985 +                   || (chksum_status & 0x4)
8986 +                   || rx_status )
8987 +//                     || rx_status || (rwptr.bits.rptr > rwptr.bits.wptr ))
8988 +               {
8989 +                       good_frame = 0;
8990 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
8991 +                               printk("%s::derr (GMAC-%d)!!!\n", __func__, tp->port_id);
8992 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
8993 +                               printk("%s::perr (GMAC-%d)!!!\n", __func__, tp->port_id);
8994 +                       if (rx_status)
8995 +                       {
8996 +                               if (rx_status == 4 || rx_status == 7)
8997 +                                       isPtr->rx_crc_errors++;
8998 +//                             printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
8999 +                       }
9000 +#ifdef SL351x_GMAC_WORKAROUND
9001 +                       else if (pkt_size < 60)
9002 +                       {
9003 +                               if (tp->short_frames_cnt < GMAC_SHORT_FRAME_THRESHOLD)
9004 +                                       tp->short_frames_cnt++;
9005 +                               if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
9006 +                               {
9007 +                                       GMAC_CONFIG0_T config0;
9008 +                                       config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
9009 +                                       config0.bits.dis_rx = 1;
9010 +                                       writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
9011 +                                       config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
9012 +                                       config0.bits.dis_rx = 1;
9013 +                                       writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
9014 +                               }
9015 +                       }
9016 +#endif
9017 +//                     if (chksum_status)
9018 +//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
9019 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
9020 +                       dev_kfree_skb_irq(skb);
9021 +               }
9022 +               if (good_frame)
9023 +               {
9024 +                       if (curr_desc->word0.bits.drop)
9025 +                               printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
9026 +//                     if (chksum_status)
9027 +//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
9028 +
9029 +#ifdef SL351x_GMAC_WORKAROUND
9030 +                       if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
9031 +                       {
9032 +                               GMAC_CONFIG0_T config0;
9033 +                               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
9034 +                               config0.bits.dis_rx = 0;
9035 +                               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
9036 +                               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
9037 +                               config0.bits.dis_rx = 0;
9038 +                               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
9039 +                       }
9040 +                       tp->short_frames_cnt = 0;
9041 +#endif
9042 +               /* get frame information from the first descriptor of the frame */
9043 +                       isPtr->rx_packets++;
9044 +                       //consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
9045 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
9046 +                       tp->curr_rx_skb = skb;
9047 +       //              curr_desc->word2.buf_adr = 0;
9048 +
9049 +                   //skb_reserve (skb, SKB_RESERVE_BYTES);
9050 +                       skb_reserve (skb, RX_INSERT_BYTES);     /* 2 byte align the IP fields. */
9051 +                       //if ((skb->tail+pkt_size) > skb->end )
9052 +                       //printk("%s::------------->Here skb->len=%d,pkt_size= %d,skb->head=0x%x,skb->tail= 0x%x, skb->end= 0x%x\n", __func__, skb->len, pkt_size,skb->head,skb->tail,skb->end);
9053 +                       skb_put(skb, pkt_size);
9054 +
9055 +
9056 +                       skb->dev = dev;
9057 +                       if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
9058 +                       {
9059 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
9060 +#ifdef CONFIG_SL351x_NAT
9061 +                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
9062 +                               {
9063 +                                       struct iphdr    *ip_hdr;
9064 +                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
9065 +                                       sl351x_nat_input(skb,
9066 +                                                                       tp->port_id,
9067 +                                                                       (void *)curr_desc->word3.bits.l3_offset,
9068 +                                                                       (void *)curr_desc->word3.bits.l4_offset);
9069 +                               }
9070 +#endif
9071 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
9072 +#if 0
9073 +#ifdef CONFIG_SL351x_RXTOE
9074 +                               if (storlink_ctl.rx_max_pktsize) {
9075 +                                       struct iphdr    *ip_hdr;
9076 +                                       struct tcphdr   *tcp_hdr;
9077 +                                       int ip_hdrlen;
9078 +
9079 +                                       ip_hdr = (struct iphdr*)&(skb->data[0]);
9080 +                                       if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
9081 +                                          ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
9082 +                                               ip_hdrlen = ip_hdr->ihl << 2;
9083 +                                               tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
9084 +                                               if (tcp_hdr->syn) {
9085 +                                                       struct toe_conn* connection = init_toeq(ip_hdr->version,
9086 +                                                                       ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
9087 +                                                       TCP_SKB_CB(skb)->connection = connection;
9088 +                                                       //      hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
9089 +                                                       //              printk("%s::skb data %x, conn %x, mode %x\n",
9090 +                                                       //                      __func__, skb->data, connection, connection->mode);
9091 +                                               }
9092 +                                       }
9093 +                               }
9094 +#endif
9095 +#endif
9096 +                       }
9097 +                       else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
9098 +                       {
9099 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
9100 +#ifdef CONFIG_SL351x_NAT
9101 +                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
9102 +                               {
9103 +                                       struct iphdr    *ip_hdr;
9104 +                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
9105 +                                       if (ip_hdr->protocol == IPPROTO_UDP)
9106 +                                       {
9107 +                                               sl351x_nat_input(skb,
9108 +                                                                               tp->port_id,
9109 +                                                                               (void *)curr_desc->word3.bits.l3_offset,
9110 +                                                                               (void *)curr_desc->word3.bits.l4_offset);
9111 +                                       }
9112 +                                       else if (ip_hdr->protocol == IPPROTO_GRE)
9113 +                                       {
9114 +                                               sl351x_nat_input(skb,
9115 +                                                                       tp->port_id,
9116 +                                                                       (void *)curr_desc->word3.bits.l3_offset,
9117 +                                                                       (void *)curr_desc->word3.bits.l4_offset);
9118 +                                       }
9119 +                               }
9120 +#endif
9121 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
9122 +                       }
9123 +                       else
9124 +                       {
9125 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
9126 +                       }
9127 +                       //netif_rx(skb);  /* socket rx */
9128 +                       netif_receive_skb(skb); //For NAPI
9129 +                       dev->last_rx = jiffies;
9130 +
9131 +                       isPtr->rx_bytes += pkt_size;
9132 +                       //printk("------------------->isPtr->rx_bytes = %d\n",isPtr->rx_bytes);
9133 +
9134 +
9135 +        }
9136 +               // advance one for Rx default Q 0/1
9137 +               rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
9138 +               SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
9139 +       tp->rx_rwptr.bits32 = rwptr.bits32;
9140 +               rx_pkts_num++;
9141 +               //rwptr.bits32 = readl(&tp->default_qhdr->word1);//try read default_qhdr again
9142 +               //fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
9143 +               //printk("%s:---Loop  -------->rx_pkts_num=%d------------>Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits32,fq_rwptr.bits32 );
9144 +#if 0
9145 +               if ((status4 & 0x1) == 0)
9146 +               {
9147 +                       //if (!((dev->last_rx <= (rx_time + 2)) &&  (isPtr->rx_bytes > (rx_old_bytes + 1000000 ))))
9148 +                       if (tp->total_q_cnt_napi < 1024)
9149 +                       {
9150 +                               tp->total_q_cnt_napi++;
9151 +                               toe_gmac_fill_free_q();  //for iperf test disable
9152 +                       }
9153 +                       //else
9154 +                               //printk("%s:---isPtr->rx_bytes =%u , rx_old_bytes =%u\n",__func__,isPtr->rx_bytes,rx_old_bytes );
9155 +
9156 +               }
9157 +#endif
9158 +               //rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
9159 +               //printk("%s:---Loop  -------->rx_pkts_num=%d----rwptr.bits.rptr=0x%x-------->Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits32,fq_rwptr.bits32 );
9160 +               //printk("%s:---Loop  rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
9161 +       }
9162 +       // advance one for Rx default Q 0/1
9163 +
9164 +               //rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
9165 +               //SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
9166 +       //tp->rx_rwptr.bits32 = rwptr.bits32;
9167 +       //rwptr.bits.rptr = rwptr.bits.rptr;
9168 +
9169 +       dev->quota -= rx_pkts_num;
9170 +       *budget -= rx_pkts_num;
9171 +
9172 +       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);//try read SWFQ empty again
9173 +       //fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
9174 +       rwptr.bits32 = readl(&tp->default_qhdr->word1); //try read default_qhdr again
9175 +       //printk("%s:---After    rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
9176 +//     if (rwptr.bits.rptr > rwptr.bits.wptr )
9177 +//                     {
9178 +                               //toe_gmac_disable_rx(dev);
9179 +                               //wait_event_interruptible_timeout(freeq_wait,
9180 +                                       //(rx_pkts_num == 100), CMTP_INTEROP_TIMEOUT);
9181 +                               //printk("\n%s:: return 22222=======> rx_pkts_num =%d,   rwptr.bits.rptr=%d,   rwptr.bits.wptr = %d ====---------=======>JKJKJKJKJK\n",
9182 +                                       //__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
9183 +//                             return 1;
9184 +//                     }
9185 +
9186 +       if (rwptr.bits.rptr == rwptr.bits.wptr)
9187 +       {
9188 +               unsigned int data32;
9189 +                       //printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr]   rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
9190 +
9191 +           /* Receive descriptor is empty now */
9192 +#if 1
9193 +     if (status4 & 0x1)
9194 +                       {
9195 +                               do_again =1;
9196 +                               //writel(0x40400000, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_4_REG); //disable SWFQ empty interrupt
9197 +                               //toe_gmac_disable_interrupt(tp->irq);
9198 +                               tp->sw_fq_empty_cnt++;
9199 +                               //toe_gmac_disable_rx(dev);
9200 +                               writel(0x07960202, TOE_GMAC0_BASE+GMAC_CONFIG0);
9201 +                               writel(0x07960202, TOE_GMAC1_BASE+GMAC_CONFIG0);
9202 +                               //printk("\n%s ::  freeq int-----tp->sw_fq_empty_cnt  =%d---------====================----------------->\n",__func__,tp->sw_fq_empty_cnt);
9203 +                               //while ((fq_rwptr.bits.wptr >= (fq_rwptr.bits.rptr+256)) || (fq_rwptr.bits.wptr <= (fq_rwptr.bits.rptr+256)))
9204 +                               //{
9205 +                                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
9206 +                                       //0x1);
9207 +                               //printk("\n%s::fq_rwptr.wrptr = %x =======> ===========>here \n", __func__,fq_rwptr.bits32);
9208 +                               //if ((status4 & 0x1) == 0)
9209 +                                       //break;
9210 +                                return 1;
9211 +                               //}
9212 +
9213 +                       }
9214 +#endif
9215 +        //toe_gmac_fill_free_q();
9216 +        netif_rx_complete(dev);
9217 +        // enable GMAC-0 rx interrupt
9218 +        // class-Q & TOE-Q are implemented in future
9219 +        //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
9220 +        //if (tp->port_id == 0)
9221 +               //data32 |= DEFAULT_Q0_INT_BIT;
9222 +        //else
9223 +               //data32 |= DEFAULT_Q1_INT_BIT;
9224 +        //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
9225 +               writel(0x3, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
9226 +               //printk("\n%s::netif_rx_complete-->  rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x ====---------=======>JKJKJKJKJK\n",
9227 +               //__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
9228 +        writel(0x07960200, TOE_GMAC0_BASE+GMAC_CONFIG0);
9229 +               writel(0x07960200, TOE_GMAC1_BASE+GMAC_CONFIG0);
9230 +        return 0;
9231 +    }
9232 +    else
9233 +    {
9234 +        //printk("\n%s:: return 1 -->status4= 0x%x,rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x  ======> \n", __func__,status4,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
9235 +        return 1;
9236 +    }
9237 +}
9238 +#endif
9239 +
9240 +/*----------------------------------------------------------------------
9241 +* gmac_tx_timeout
9242 +*----------------------------------------------------------------------*/
9243 +void gmac_tx_timeout(struct net_device *dev)
9244 +{
9245 +       GMAC_INFO_T                             *tp = (GMAC_INFO_T *)dev->priv;
9246 +
9247 +#ifdef CONFIG_SL351x_SYSCTL
9248 +       if (tp->operation && storlink_ctl.link[tp->port_id])
9249 +#else
9250 +       if (tp->operation)
9251 +#endif
9252 +       {
9253 +               netif_wake_queue(dev);
9254 +       }
9255 +}
9256 +
9257 +
9258 +
9259 +/*----------------------------------------------------------------------
9260 +* mac_set_rule_reg
9261 +*----------------------------------------------------------------------*/
9262 +int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2)
9263 +{
9264 +       int             total_key_dwords;
9265 +
9266 +       total_key_dwords = 1;
9267 +
9268 +       if (reg0 & MR_L2_BIT)
9269 +       {
9270 +               if (reg0 & MR_DA_BIT) total_key_dwords += 2;
9271 +               if (reg0 & MR_SA_BIT) total_key_dwords += 2;
9272 +               if ((reg0 & MR_DA_BIT) && ( reg0 & MR_SA_BIT)) total_key_dwords--;
9273 +               if (reg0 & (MR_PPPOE_BIT | MR_VLAN_BIT)) total_key_dwords++;
9274 +       }
9275 +       if (reg0 & MR_L3_BIT)
9276 +       {
9277 +               if (reg0 & (MR_IP_HDR_LEN_BIT | MR_TOS_TRAFFIC_BIT | MR_SPR_BITS))
9278 +                       total_key_dwords++;
9279 +               if (reg0 & MR_FLOW_LABLE_BIT) total_key_dwords++;
9280 +               if ((reg0 & MR_IP_VER_BIT) == 0) // IPv4
9281 +               {
9282 +                       if (reg1 & 0xff000000) total_key_dwords += 1;
9283 +                       if (reg1 & 0x00ff0000) total_key_dwords += 1;
9284 +               }
9285 +               else
9286 +               {
9287 +                       if (reg1 & 0xff000000) total_key_dwords += 4;
9288 +                       if (reg1 & 0x00ff0000) total_key_dwords += 4;
9289 +               }
9290 +       }
9291 +       if (reg0 & MR_L4_BIT)
9292 +       {
9293 +               if (reg1 & 0x0000f000) total_key_dwords += 1;
9294 +               if (reg1 & 0x00000f00) total_key_dwords += 1;
9295 +               if (reg1 & 0x000000f0) total_key_dwords += 1;
9296 +               if (reg1 & 0x0000000f) total_key_dwords += 1;
9297 +               if (reg2 & 0xf0000000) total_key_dwords += 1;
9298 +               if (reg2 & 0x0f000000) total_key_dwords += 1;
9299 +       }
9300 +       if (reg0 & MR_L7_BIT)
9301 +       {
9302 +               if (reg2 & 0x00f00000) total_key_dwords += 1;
9303 +               if (reg2 & 0x000f0000) total_key_dwords += 1;
9304 +               if (reg2 & 0x0000f000) total_key_dwords += 1;
9305 +               if (reg2 & 0x00000f00) total_key_dwords += 1;
9306 +               if (reg2 & 0x000000f0) total_key_dwords += 1;
9307 +               if (reg2 & 0x0000000f) total_key_dwords += 1;
9308 +       }
9309 +
9310 +       if (total_key_dwords > HASH_MAX_KEY_DWORD)
9311 +               return -1;
9312 +
9313 +       if (total_key_dwords == 0 && enabled)
9314 +               return -2;
9315 +
9316 +       mac_set_rule_enable_bit(mac, rule, 0);
9317 +       if (enabled)
9318 +       {
9319 +               mac_set_MRxCRx(mac, rule, 0, reg0);
9320 +               mac_set_MRxCRx(mac, rule, 1, reg1);
9321 +               mac_set_MRxCRx(mac, rule, 2, reg2);
9322 +               mac_set_rule_action(mac, rule, total_key_dwords);
9323 +               mac_set_rule_enable_bit(mac, rule, enabled);
9324 +       }
9325 +       else
9326 +       {
9327 +               mac_set_rule_action(mac, rule, 0);
9328 +       }
9329 +       return total_key_dwords;
9330 +}
9331 +
9332 +/*----------------------------------------------------------------------
9333 +* mac_get_rule_enable_bit
9334 +*----------------------------------------------------------------------*/
9335 +int mac_get_rule_enable_bit(int mac, int rule)
9336 +{
9337 +       switch (rule)
9338 +       {
9339 +               case 0: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) >> 15) & 1);
9340 +               case 1: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) >> 31) & 1);
9341 +               case 2: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) >> 15) & 1);
9342 +               case 3: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) >> 31) & 1);
9343 +               default: return 0;
9344 +       }
9345 +}
9346 +
9347 +/*----------------------------------------------------------------------
9348 +* mac_set_rule_enable_bit
9349 +*----------------------------------------------------------------------*/
9350 +void mac_set_rule_enable_bit(int mac, int rule, int data)
9351 +{
9352 +       u32 reg;
9353 +
9354 +       if (data & ~1)
9355 +               return;
9356 +
9357 +       switch (rule)
9358 +       {
9359 +               case 0:
9360 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(1<<15)) | (data << 15);
9361 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg);
9362 +                       break;
9363 +               case 1:
9364 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(1<<31)) | (data << 31);
9365 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg);
9366 +                       break;
9367 +               case 2:
9368 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(1<<15)) | (data << 15);
9369 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1, reg);
9370 +                       break;
9371 +               case 3:
9372 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(1<<31)) | (data << 31);
9373 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1, reg);
9374 +       }
9375 +}
9376 +
9377 +/*----------------------------------------------------------------------
9378 +* mac_set_rule_action
9379 +*----------------------------------------------------------------------*/
9380 +int mac_set_rule_action(int mac, int rule, int data)
9381 +{
9382 +       u32 reg;
9383 +
9384 +       if (data > 32)
9385 +               return -1;
9386 +
9387 +       if (data)
9388 +               data = (data << 6) | (data + HASH_ACTION_DWORDS);
9389 +       switch (rule)
9390 +       {
9391 +               case 0:
9392 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(0x7ff));
9393 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg | data);
9394 +                       break;
9395 +               case 1:
9396 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(0x7ff<<16));
9397 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg | (data << 16));
9398 +                       break;
9399 +               case 2:
9400 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(0x7ff));
9401 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1,  reg | data);
9402 +                       break;
9403 +               case 3:
9404 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(0x7ff<<16));
9405 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1, reg | (data << 16));
9406 +                       break;
9407 +               default:
9408 +                       return -1;
9409 +       }
9410 +
9411 +       return 0;
9412 +}
9413 +/*----------------------------------------------------------------------
9414 +* mac_get_MRxCRx
9415 +*----------------------------------------------------------------------*/
9416 +int mac_get_MRxCRx(int mac, int rule, int ctrlreg)
9417 +{
9418 +       int reg;
9419 +
9420 +       switch (rule)
9421 +       {
9422 +               case 0: reg = GMAC_MR0CR0 + ctrlreg * 4; break;
9423 +               case 1: reg = GMAC_MR1CR0 + ctrlreg * 4; break;
9424 +               case 2: reg = GMAC_MR2CR0 + ctrlreg * 4; break;
9425 +               case 3: reg = GMAC_MR3CR0 + ctrlreg * 4; break;
9426 +               default: return 0;
9427 +       }
9428 +       return mac_read_dma_reg(mac, reg);
9429 +}
9430 +
9431 +/*----------------------------------------------------------------------
9432 +* mac_set_MRxCRx
9433 +*----------------------------------------------------------------------*/
9434 +void mac_set_MRxCRx(int mac, int rule, int ctrlreg, u32 data)
9435 +{
9436 +       int reg;
9437 +
9438 +       switch (rule)
9439 +       {
9440 +               case 0: reg = GMAC_MR0CR0 + ctrlreg * 4; break;
9441 +               case 1: reg = GMAC_MR1CR0 + ctrlreg * 4; break;
9442 +               case 2: reg = GMAC_MR2CR0 + ctrlreg * 4; break;
9443 +               case 3: reg = GMAC_MR3CR0 + ctrlreg * 4; break;
9444 +               default: return;
9445 +       }
9446 +       mac_write_dma_reg(mac, reg, data);
9447 +}
9448 +
9449 +/*----------------------------------------------------------------------
9450 +* mac_set_rule_priority
9451 +*----------------------------------------------------------------------*/
9452 +void mac_set_rule_priority(int mac, int p0, int p1, int p2, int p3)
9453 +{
9454 +       int                     i;
9455 +       GMAC_MRxCR0_T   reg[4];
9456 +
9457 +       for (i=0; i<4; i++)
9458 +               reg[i].bits32 = mac_get_MRxCRx(mac, i, 0);
9459 +
9460 +       reg[0].bits.priority = p0;
9461 +       reg[1].bits.priority = p1;
9462 +       reg[2].bits.priority = p2;
9463 +       reg[3].bits.priority = p3;
9464 +
9465 +       for (i=0; i<4; i++)
9466 +               mac_set_MRxCRx(mac, i, 0, reg[i].bits32);
9467 +}
9468 +
9469 +/*----------------------------------------------------------------------
9470 +* gmac_netdev_ioctl
9471 +*----------------------------------------------------------------------*/
9472 +static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
9473 +{
9474 +       int                             rc = 0;
9475 +    unsigned char              *hwa = rq->ifr_ifru.ifru_hwaddr.sa_data;
9476 +
9477 +#ifdef br_if_ioctl
9478 +    struct                             ethtool_cmd ecmd;       //br_if.c will call this ioctl
9479 +       GMAC_INFO_T             *tp = dev->priv;
9480 +#endif
9481 +
9482 +#ifdef         CONFIG_SL351x_NAT
9483 +       if (cmd == SIOCDEVPRIVATE)
9484 +               return sl351x_nat_ioctl(dev, rq, cmd);
9485 +#endif
9486 +
9487 +       switch (cmd) {
9488 +       case SIOCETHTOOL:
9489 +#ifdef br_if_ioctl     //br_if.c will call this ioctl
9490 +               if (!netif_running(dev))
9491 +               {
9492 +                       printk("Before changing the H/W address,please down the device.\n");
9493 +                       return -EINVAL;
9494 +               }
9495 +               memset((void *) &ecmd, 0, sizeof (ecmd));
9496 +                   ecmd.supported =
9497 +                       SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII |
9498 +                    SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
9499 +                    SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
9500 +                           ecmd.port = PORT_TP;
9501 +                   ecmd.transceiver = XCVR_EXTERNAL;
9502 +                   ecmd.phy_address = tp->phy_addr;
9503 +                   switch (tp->speed_status)
9504 +                   {
9505 +                   case GMAC_SPEED_10: ecmd.speed = SPEED_10; break;
9506 +                   case GMAC_SPEED_100: ecmd.speed = SPEED_100; break;
9507 +                   case GMAC_SPEED_1000: ecmd.speed = SPEED_1000; break;
9508 +                   default: ecmd.speed = SPEED_10; break;
9509 +                  }
9510 +                   ecmd.duplex = tp->full_duplex_status ? DUPLEX_FULL : DUPLEX_HALF;
9511 +                   ecmd.advertising = ADVERTISED_TP;
9512 +                   ecmd.advertising |= ADVERTISED_Autoneg;
9513 +                   ecmd.autoneg = AUTONEG_ENABLE;
9514 +                    if (copy_to_user(rq->ifr_data, &ecmd, sizeof (ecmd)))
9515 +                       return -EFAULT;
9516 +#endif
9517 +
9518 +        break;
9519 +
9520 +    case SIOCSIFHWADDR:
9521 +               if (!netif_running(dev))
9522 +               {
9523 +                       printk("Before changing the H/W address,please down the device.\n");
9524 +                       return -EINVAL;
9525 +               }
9526 +        gmac_set_mac_address(dev,hwa);
9527 +        break;
9528 +
9529 +       case SIOCGMIIPHY:       /* Get the address of the PHY in use. */
9530 +        break;
9531 +
9532 +       case SIOCGMIIREG:       /* Read the specified MII register. */
9533 +               break;
9534 +
9535 +       case SIOCSMIIREG:       /* Write the specified MII register */
9536 +               break;
9537 +
9538 +       default:
9539 +               rc = -EOPNOTSUPP;
9540 +               break;
9541 +       }
9542 +
9543 +       return rc;
9544 +}
9545 +
9546 +#ifdef SL351x_GMAC_WORKAROUND
9547 +
9548 +#define GMAC_TX_STATE_OFFSET   0x60
9549 +#define GMAC_RX_STATE_OFFSET   0x64
9550 +#define GMAC_POLL_HANGED_NUM   200
9551 +#define GMAC_RX_HANGED_STATE   0x4b2000
9552 +#define GMAC_RX_HANGED_MASK            0xdff000
9553 +#define GMAC_TX_HANGED_STATE   0x34012
9554 +#define GMAC_TX_HANGED_MASK            0xfffff
9555 +#define TOE_GLOBAL_REG_SIZE            (0x78/sizeof(u32))
9556 +#define TOE_DMA_REG_SIZE               (0xd0/sizeof(u32))
9557 +#define TOE_GMAC_REG_SIZE              (0x30/sizeof(u32))
9558 +#define GMAC0_RX_HANG_BIT              (1 << 0)
9559 +#define GMAC0_TX_HANG_BIT              (1 << 1)
9560 +#define GMAC1_RX_HANG_BIT              (1 << 2)
9561 +#define GMAC1_TX_HANG_BIT              (1 << 3)
9562 +
9563 +int            gmac_in_do_workaround;
9564 +#if 0
9565 +int            debug_cnt, poll_max_cnt;
9566 +#endif
9567 +u32            gmac_workaround_cnt[4];
9568 +u32            toe_global_reg[TOE_GLOBAL_REG_SIZE];
9569 +u32            toe_dma_reg[GMAC_NUM][TOE_DMA_REG_SIZE];
9570 +u32            toe_gmac_reg[GMAC_NUM][TOE_GMAC_REG_SIZE];
9571 +u32            gmac_short_frame_workaround_cnt[2];
9572 +
9573 +static void sl351x_gmac_release_buffers(void);
9574 +static void sl351x_gmac_release_swtx_q(void);
9575 +static void sl351x_gmac_release_rx_q(void);
9576 +#ifdef _TOEQ_CLASSQ_READY_
9577 +static void sl351x_gmac_release_class_q(void);
9578 +static void sl351x_gmac_release_toe_q(void);
9579 +static void sl351x_gmac_release_intr_q(void);
9580 +#endif
9581 +static void sl351x_gmac_release_sw_free_q(void);
9582 +static void sl351x_gmac_release_hw_free_q(void);
9583 +#ifdef CONFIG_SL351x_NAT
9584 +static int get_free_desc_cnt(unsigned long rwptr, int total);
9585 +static void sl351x_gmac_release_hwtx_q(void);
9586 +u32     sl351x_nat_workaround_cnt;
9587 +#endif
9588 +void sl351x_gmac_save_reg(void);
9589 +void sl351x_gmac_restore_reg(void);
9590 +
9591 +
9592 +/*----------------------------------------------------------------------
9593 +*      sl351x_poll_gmac_hanged_status
9594 +*      - Called by timer routine, period 10ms
9595 +*      - If (state != 0 && state == prev state && )
9596 +*----------------------------------------------------------------------*/
9597 +void sl351x_poll_gmac_hanged_status(u32 data)
9598 +{
9599 +       int                     i;
9600 +       u32                     state;
9601 +       TOE_INFO_T              *toe;
9602 +       GMAC_INFO_T             *tp;
9603 +       u32                             hanged_state;
9604 +       // int                          old_operation[GMAC_NUM];
9605 +#ifdef CONFIG_SL351x_NAT
9606 +       u32                             hw_free_cnt;
9607 +#endif
9608 +
9609 +       if (gmac_in_do_workaround)
9610 +               return;
9611 +
9612 +       gmac_in_do_workaround = 1;
9613 +
9614 +       toe = (TOE_INFO_T *)&toe_private_data;
9615 +       hanged_state = 0;
9616 +
9617 +#ifdef SL351x_TEST_WORKAROUND
9618 +       if (toe->gmac[0].operation || toe->gmac[1].operation)
9619 +       {
9620 +               debug_cnt++;
9621 +               if (debug_cnt == (30 * HZ))
9622 +               {
9623 +                       debug_cnt = 0;
9624 +                       hanged_state = GMAC0_RX_HANG_BIT;
9625 +                       goto do_workaround;
9626 +               }
9627 +       }
9628 +#endif
9629 +       if (toe->gmac[0].operation)
9630 +               hanged_state |= GMAC0_RX_HANG_BIT | GMAC0_TX_HANG_BIT;
9631 +
9632 +#if (GMAC_NUM > 1)
9633 +       if (toe->gmac[1].operation)
9634 +               hanged_state |= GMAC1_RX_HANG_BIT | GMAC1_TX_HANG_BIT;
9635 +#endif
9636 +
9637 +       for (i=0; i<GMAC_POLL_HANGED_NUM; i++)
9638 +       {
9639 +               if (hanged_state & GMAC0_RX_HANG_BIT)
9640 +               {
9641 +                       state = readl(TOE_GMAC0_BASE + GMAC_RX_STATE_OFFSET) & GMAC_RX_HANGED_MASK;
9642 +                       if (state != GMAC_RX_HANGED_STATE)
9643 +                               hanged_state &= ~GMAC0_RX_HANG_BIT;
9644 +               }
9645 +               if (hanged_state & GMAC0_TX_HANG_BIT)
9646 +               {
9647 +                       state = readl(TOE_GMAC0_BASE + GMAC_TX_STATE_OFFSET) & GMAC_TX_HANGED_MASK;
9648 +                       if (state != GMAC_TX_HANGED_STATE)
9649 +                               hanged_state &= ~GMAC0_TX_HANG_BIT;
9650 +               }
9651 +#if (GMAC_NUM > 1)
9652 +               if (hanged_state & GMAC1_RX_HANG_BIT)
9653 +               {
9654 +                       state = readl(TOE_GMAC1_BASE + GMAC_RX_STATE_OFFSET) & GMAC_RX_HANGED_MASK;
9655 +                       if (state != GMAC_RX_HANGED_STATE)
9656 +                               hanged_state &= ~GMAC1_RX_HANG_BIT;
9657 +               }
9658 +               if (hanged_state & GMAC1_TX_HANG_BIT)
9659 +               {
9660 +                       state = readl(TOE_GMAC1_BASE + GMAC_TX_STATE_OFFSET) & GMAC_TX_HANGED_MASK;
9661 +                       if (state != GMAC_TX_HANGED_STATE)
9662 +                               hanged_state &= ~GMAC1_TX_HANG_BIT;
9663 +               }
9664 +#endif
9665 +               if (!hanged_state)
9666 +               {
9667 +#if 0
9668 +                       if (i < poll_max_cnt)
9669 +                               poll_max_cnt = i;
9670 +#endif
9671 +                       if (toe->gmac[0].short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
9672 +                       {
9673 +                               gmac_short_frame_workaround_cnt[0]++;
9674 +                               toe->gmac[0].short_frames_cnt = 0;
9675 +                               goto do_workaround;
9676 +                       }
9677 +#if (GMAC_NUM > 1)
9678 +                       if (toe->gmac[1].short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
9679 +                       {
9680 +                               gmac_short_frame_workaround_cnt[1]++;
9681 +                               toe->gmac[1].short_frames_cnt = 0;
9682 +                               goto do_workaround;
9683 +                       }
9684 +#endif
9685 +
9686 +#ifdef CONFIG_SL351x_NAT
9687 +                       hw_free_cnt = readl(TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
9688 +                       hw_free_cnt = get_free_desc_cnt(hw_free_cnt, TOE_HW_FREEQ_DESC_NUM);
9689 +#ifdef NAT_WORKAROUND_BY_RESET_GMAC
9690 +                       if (readl(TOE_GLOBAL_BASE + 0x4084) && (hw_free_cnt <= PAUSE_SET_HW_FREEQ))
9691 +                       {
9692 +                               sl351x_nat_workaround_cnt++;
9693 +                               goto do_workaround;
9694 +                       }
9695 +#else
9696 +                       if (readl(TOE_GLOBAL_BASE + 0x4084) && (hw_free_cnt <= (PAUSE_SET_HW_FREEQ*2)))
9697 +                       {
9698 +                               sl351x_nat_workaround_cnt++;
9699 +                               sl351x_nat_workaround_handler();
9700 +                       }
9701 +#endif
9702 +#endif
9703 +                       gmac_in_do_workaround = 0;
9704 +                       add_timer(&gmac_workround_timer_obj);
9705 +                       return;
9706 +               }
9707 +       }
9708 +
9709 +do_workaround:
9710 +
9711 +       gmac_initialized = 0;
9712 +       if (hanged_state)
9713 +       {
9714 +               if (hanged_state & GMAC0_RX_HANG_BIT) gmac_workaround_cnt[0]++;
9715 +               if (hanged_state & GMAC0_TX_HANG_BIT) gmac_workaround_cnt[1]++;
9716 +               if (hanged_state & GMAC1_RX_HANG_BIT) gmac_workaround_cnt[2]++;
9717 +               if (hanged_state & GMAC1_TX_HANG_BIT) gmac_workaround_cnt[3]++;
9718 +       }
9719 +
9720 +       for (i=0; i<GMAC_NUM; i++)
9721 +       {
9722 +               tp=(GMAC_INFO_T *)&toe->gmac[i];
9723 +               // old_operation[i] = tp->operation;
9724 +               if (tp->operation)
9725 +               {
9726 +                       netif_stop_queue(tp->dev);
9727 +                       clear_bit(__LINK_STATE_START, &tp->dev->state);
9728 +                       toe_gmac_disable_interrupt(tp->irq);
9729 +                       toe_gmac_disable_tx_rx(tp->dev);
9730 +                       toe_gmac_hw_stop(tp->dev);
9731 +               }
9732 +       }
9733 +
9734 +       // clear all status bits
9735 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
9736 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
9737 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
9738 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
9739 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
9740 +
9741 +#if 0
9742 +       if ((hanged_state & GMAC0_RX_HANG_BIT) &&
9743 +               (readl(TOE_GMAC0_DMA_BASE + 0xdc) & 0xf0))
9744 +       {
9745 +               struct sk_buff *skb;
9746 +               unsigned int buf;
9747 +               buf = readl(TOE_GMAC0_DMA_BASE + 0x68) & ~3;
9748 +#ifdef CONFIG_SL351x_NAT
9749 +               if (buf < toe->hwfq_buf_base_dma || buf > toe->hwfq_buf_end_dma)
9750 +#endif
9751 +               {
9752 +                       skb = (struct sk_buff *)(REG32(buf - SKB_RESERVE_BYTES));
9753 +                       printk("GMAC-0 free a loss SKB 0x%x\n", (u32)skb);
9754 +                       dev_kfree_skb(skb);
9755 +               }
9756 +       }
9757 +       if ((hanged_state & GMAC1_RX_HANG_BIT)  &&
9758 +               (readl(TOE_GMAC1_DMA_BASE + 0xdc) & 0xf0))
9759 +       {
9760 +               struct sk_buff *skb;
9761 +               unsigned int buf;
9762 +               buf = readl(TOE_GMAC1_DMA_BASE + 0x68) & ~3;
9763 +#ifdef CONFIG_SL351x_NAT
9764 +               if (buf < toe->hwfq_buf_base_dma || buf > toe->hwfq_buf_end_dma)
9765 +#endif
9766 +               {
9767 +                       skb = (struct sk_buff *)(REG32(buf - SKB_RESERVE_BYTES));
9768 +                       printk("GMAC-1 free a loss SKB 0x%x\n", (u32)skb);
9769 +                       dev_kfree_skb(skb);
9770 +               }
9771 +       }
9772 +#endif
9773 +
9774 +       sl351x_gmac_release_buffers();
9775 +       sl351x_gmac_save_reg();
9776 +       toe_gmac_sw_reset();
9777 +       sl351x_gmac_restore_reg();
9778 +
9779 +       if (toe->gmac[0].default_qhdr->word1.bits32)
9780 +       {
9781 +               // printk("===> toe->gmac[0].default_qhdr->word1 = 0x%x\n", toe->gmac[0].default_qhdr->word1);
9782 +               sl351x_gmac_release_rx_q();
9783 +               writel(0, &toe->gmac[0].default_qhdr->word1);
9784 +       }
9785 +       if (toe->gmac[1].default_qhdr->word1.bits32)
9786 +       {
9787 +               // printk("===> toe->gmac[1].default_qhdr->word1 = 0x%x\n", toe->gmac[1].default_qhdr->word1);
9788 +               sl351x_gmac_release_rx_q();
9789 +               writel(0, &toe->gmac[1].default_qhdr->word1);
9790 +       }
9791 +
9792 +       gmac_initialized = 1;
9793 +
9794 +#ifdef         CONFIG_SL351x_NAT
9795 +       writel(0, TOE_GLOBAL_BASE + 0x4084);
9796 +#endif
9797 +
9798 +       for (i=0; i<GMAC_NUM; i++)
9799 +       {
9800 +               tp=(GMAC_INFO_T *)&toe->gmac[i];
9801 +               if (tp->operation)
9802 +               {
9803 +                       toe_gmac_enable_interrupt(tp->irq);
9804 +                       toe_gmac_hw_start(tp->dev);
9805 +                       toe_gmac_enable_tx_rx(tp->dev);
9806 +                       netif_wake_queue(tp->dev);
9807 +                       set_bit(__LINK_STATE_START, &tp->dev->state);
9808 +               }
9809 +       }
9810 +
9811 +       gmac_in_do_workaround = 0;
9812 +       add_timer(&gmac_workround_timer_obj);
9813 +}
9814 +
9815 +/*----------------------------------------------------------------------
9816 +*      get_free_desc_cnt
9817 +*----------------------------------------------------------------------*/
9818 +#ifdef CONFIG_SL351x_NAT
9819 +static int get_free_desc_cnt(unsigned long rwptr, int total)
9820 +{
9821 +       unsigned short wptr = rwptr & 0xffff;
9822 +       unsigned short rptr = rwptr >> 16;
9823 +
9824 +       if (wptr >= rptr)
9825 +               return (total - wptr + rptr);
9826 +       else
9827 +               return (rptr - wptr);
9828 +}
9829 +#endif
9830 +/*----------------------------------------------------------------------
9831 +*      sl351x_gmac_release_buffers
9832 +*----------------------------------------------------------------------*/
9833 +static void sl351x_gmac_release_buffers(void)
9834 +{
9835 +       // Free buffers & Descriptors in all SW Tx Queues
9836 +       sl351x_gmac_release_swtx_q();
9837 +
9838 +       // Free buffers in Default Rx Queues
9839 +       sl351x_gmac_release_rx_q();
9840 +
9841 +#ifdef _TOEQ_CLASSQ_READY_
9842 +       // Free buffers in Classification Queues
9843 +       sl351x_gmac_release_class_q();
9844 +
9845 +       // Free buffers in TOE Queues
9846 +       sl351x_gmac_release_toe_q();
9847 +
9848 +       // Free buffers in Interrupt Queues
9849 +       sl351x_gmac_release_intr_q();
9850 +#endif
9851 +
9852 +       // Free buffers & descriptors in SW free queue
9853 +       sl351x_gmac_release_sw_free_q();
9854 +
9855 +       // Free buffers & descriptors in HW free queue
9856 +       sl351x_gmac_release_hw_free_q();
9857 +
9858 +#ifdef CONFIG_SL351x_NAT
9859 +       // Free buffers & descriptors in HW free queue
9860 +       sl351x_gmac_release_hwtx_q();
9861 +#endif
9862 +}
9863 +/*----------------------------------------------------------------------
9864 +*      sl351x_gmac_release_swtx_q
9865 +*----------------------------------------------------------------------*/
9866 +static void sl351x_gmac_release_swtx_q(void)
9867 +{
9868 +       int                             i, j;
9869 +       GMAC_TXDESC_T   *curr_desc;
9870 +       unsigned int    desc_count;
9871 +       TOE_INFO_T              *toe;
9872 +       GMAC_INFO_T             *tp;
9873 +       GMAC_SWTXQ_T    *swtxq;
9874 +       DMA_RWPTR_T             rwptr;
9875 +
9876 +       toe = (TOE_INFO_T *)&toe_private_data;
9877 +       tp = (GMAC_INFO_T *)&toe->gmac[0];
9878 +       for (i=0; i<GMAC_NUM; i++, tp++)
9879 +       {
9880 +               if (!tp->existed) continue;
9881 +               swtxq = (GMAC_SWTXQ_T *)&tp->swtxq[0];
9882 +               for (j=0; j<TOE_SW_TXQ_NUM; j++, swtxq++)
9883 +               {
9884 +                       for (;;)
9885 +                       {
9886 +                               rwptr.bits32 = readl(swtxq->rwptr_reg);
9887 +                               if (rwptr.bits.rptr == swtxq->finished_idx)
9888 +                               break;
9889 +                               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
9890 +                               // if (curr_desc->word0.bits.status_tx_ok)
9891 +                               {
9892 +                                       desc_count = curr_desc->word0.bits.desc_count;
9893 +                                       while (--desc_count)
9894 +                                       {
9895 +                                               curr_desc->word0.bits.status_tx_ok = 0;
9896 +                                               swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
9897 +                                               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
9898 +                                       }
9899 +
9900 +                                       curr_desc->word0.bits.status_tx_ok = 0;
9901 +                                       if (swtxq->tx_skb[swtxq->finished_idx])
9902 +                                       {
9903 +                                               dev_kfree_skb_irq(swtxq->tx_skb[swtxq->finished_idx]);
9904 +                                               swtxq->tx_skb[swtxq->finished_idx] = NULL;
9905 +                                       }
9906 +                               }
9907 +                               swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
9908 +                       }
9909 +                       writel(0, swtxq->rwptr_reg);
9910 +                       swtxq->finished_idx = 0;
9911 +               }
9912 +       }
9913 +
9914 +}
9915 +/*----------------------------------------------------------------------
9916 +*      sl351x_gmac_release_rx_q
9917 +*----------------------------------------------------------------------*/
9918 +static void sl351x_gmac_release_rx_q(void)
9919 +{
9920 +       int                             i;
9921 +       TOE_INFO_T              *toe;
9922 +       GMAC_INFO_T             *tp;
9923 +       DMA_RWPTR_T             rwptr;
9924 +       volatile GMAC_RXDESC_T  *curr_desc;
9925 +       struct sk_buff                  *skb;
9926 +
9927 +       toe = (TOE_INFO_T *)&toe_private_data;
9928 +       tp = (GMAC_INFO_T *)&toe->gmac[0];
9929 +       for (i=0; i<GMAC_NUM; i++, tp++)
9930 +       {
9931 +               if (!tp->existed) continue;
9932 +               rwptr.bits32 = readl(&tp->default_qhdr->word1);
9933 +               while (rwptr.bits.rptr != rwptr.bits.wptr)
9934 +               {
9935 +                       curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
9936 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
9937 +                       dev_kfree_skb_irq(skb);
9938 +                       rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
9939 +                       SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
9940 +                       rwptr.bits32 = readl(&tp->default_qhdr->word1);
9941 +               }  // while
9942 +               writel(0, &tp->default_qhdr->word1);
9943 +               tp->rx_rwptr.bits32 = 0;
9944 +       } // for
9945 +
9946 +}
9947 +/*----------------------------------------------------------------------
9948 +*      sl351x_gmac_release_class_q
9949 +*----------------------------------------------------------------------*/
9950 +#ifdef _TOEQ_CLASSQ_READY_
9951 +static void sl351x_gmac_release_class_q(void)
9952 +{
9953 +       int                             i;
9954 +       TOE_INFO_T              *toe;
9955 +       CLASSQ_INFO_T   *classq;
9956 +       DMA_RWPTR_T             rwptr;
9957 +       volatile GMAC_RXDESC_T  *curr_desc;
9958 +       struct sk_buff                  *skb;
9959 +
9960 +       toe = (TOE_INFO_T *)&toe_private_data;
9961 +       classq = (CLASSQ_INFO_T *)&toe->classq[0];
9962 +       for (i=0; i<TOE_CLASS_QUEUE_NUM; i++, classq++)
9963 +       {
9964 +               rwptr.bits32 = readl(&classq->qhdr->word1);
9965 +               while (rwptr.bits.rptr != rwptr.bits.wptr)
9966 +               {
9967 +                       curr_desc = (GMAC_RXDESC_T *)classq->desc_base + rwptr.bits.rptr;
9968 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
9969 +                       dev_kfree_skb_irq(skb);
9970 +                       rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, classq->desc_num);
9971 +                       SET_RPTR(&classq->qhdr->word1, rwptr.bits.rptr);
9972 +                       rwptr.bits32 = readl(&classq->qhdr->word1);
9973 +               }  // while
9974 +               writel(0, &classq->qhdr->word1);
9975 +               classq->rwptr.bits32 = 0;
9976 +       } // for
9977 +
9978 +}
9979 +#endif
9980 +/*----------------------------------------------------------------------
9981 +*      sl351x_gmac_release_toe_q
9982 +*----------------------------------------------------------------------*/
9983 +#ifdef _TOEQ_CLASSQ_READY_
9984 +static void sl351x_gmac_release_toe_q(void)
9985 +{
9986 +       int                             i;
9987 +       TOE_INFO_T              *toe;
9988 +       TOEQ_INFO_T             *toeq_info;
9989 +       TOE_QHDR_T              *toe_qhdr;
9990 +       DMA_RWPTR_T             rwptr;
9991 +       volatile GMAC_RXDESC_T  *curr_desc;
9992 +       unsigned int    rptr, wptr;
9993 +       GMAC_RXDESC_T   *toe_curr_desc;
9994 +       struct sk_buff                  *skb;
9995 +
9996 +       toe = (TOE_INFO_T *)&toe_private_data;
9997 +       toe_qhdr = (TOE_QHDR_T *)TOE_TOE_QUE_HDR_BASE;
9998 +       for (i=0; i<TOE_TOE_QUEUE_NUM; i++, toe_qhdr++)
9999 +       {
10000 +               toeq_info = (TOEQ_INFO_T *)&toe->toeq[i];
10001 +               wptr = toe_qhdr->word1.bits.wptr;
10002 +               rptr = toe_qhdr->word1.bits.rptr;
10003 +               while (rptr != wptr)
10004 +               {
10005 +                       toe_curr_desc = (GMAC_RXDESC_T *)toeq_info->desc_base + rptr;
10006 +                       skb = (struct sk_buff *)(REG32(__va(toe_curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
10007 +                       dev_kfree_skb_irq(skb);
10008 +                       rptr = RWPTR_ADVANCE_ONE(rptr, toeq_info->desc_num);
10009 +                       SET_RPTR(&toe_qhdr->word1.bits32, rptr);
10010 +                       wptr = toe_qhdr->word1.bits.wptr;
10011 +                       rptr = toe_qhdr->word1.bits.rptr;
10012 +               }
10013 +               toe_qhdr->word1.bits32 = 0;
10014 +               toeq_info->rwptr.bits32 = 0;
10015 +       }
10016 +}
10017 +#endif
10018 +/*----------------------------------------------------------------------
10019 +*      sl351x_gmac_release_intr_q
10020 +*----------------------------------------------------------------------*/
10021 +#ifdef _TOEQ_CLASSQ_READY_
10022 +static void sl351x_gmac_release_intr_q(void)
10023 +{
10024 +}
10025 +#endif
10026 +/*----------------------------------------------------------------------
10027 +*      sl351x_gmac_release_sw_free_q
10028 +*----------------------------------------------------------------------*/
10029 +static void sl351x_gmac_release_sw_free_q(void)
10030 +{
10031 +       TOE_INFO_T                              *toe;
10032 +       volatile DMA_RWPTR_T    fq_rwptr;
10033 +       volatile GMAC_RXDESC_T  *fq_desc;
10034 +
10035 +       toe = (TOE_INFO_T *)&toe_private_data;
10036 +       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
10037 +
10038 +       while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr)
10039 +       {
10040 +               struct sk_buff *skb;
10041 +               if ((skb = dev_alloc_skb(SW_RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
10042 +               {
10043 +                       printk("%s::skb buffer allocation fail !\n",__func__); while(1);
10044 +               }
10045 +               // *(unsigned int *)(skb->data) = (unsigned int)skb;
10046 +               REG32(skb->data) = (unsigned long)skb;
10047 +               skb_reserve(skb, SKB_RESERVE_BYTES);
10048 +
10049 +               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
10050 +               fq_desc = (volatile GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
10051 +               fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
10052 +               SET_WPTR(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
10053 +               fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
10054 +       }
10055 +
10056 +       toe->fq_rx_rwptr.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
10057 +       toe->fq_rx_rwptr.bits.rptr = 0;
10058 +       writel(toe->fq_rx_rwptr.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
10059 +
10060 +}
10061 +/*----------------------------------------------------------------------
10062 +*      sl351x_gmac_release_hw_free_q
10063 +*----------------------------------------------------------------------*/
10064 +static void sl351x_gmac_release_hw_free_q(void)
10065 +{
10066 +       DMA_RWPTR_T                     rwptr_reg;
10067 +
10068 +#ifdef CONFIG_SL351x_NAT
10069 +       int                                     i;
10070 +       TOE_INFO_T                      *toe;
10071 +       GMAC_RXDESC_T           *desc_ptr;
10072 +       unsigned int            buf_ptr;
10073 +
10074 +       toe = (TOE_INFO_T *)&toe_private_data;
10075 +       desc_ptr = (GMAC_RXDESC_T *)toe->hwfq_desc_base;
10076 +       buf_ptr = (unsigned int)toe->hwfq_buf_base_dma;
10077 +       for (i=0; i<TOE_HW_FREEQ_DESC_NUM; i++)
10078 +       {
10079 +               desc_ptr->word0.bits.buffer_size = HW_RX_BUF_SIZE;
10080 +               desc_ptr->word1.bits.sw_id = i;
10081 +               desc_ptr->word2.buf_adr = (unsigned int)buf_ptr;
10082 +               desc_ptr++;
10083 +               buf_ptr += HW_RX_BUF_SIZE;
10084 +       }
10085 +#endif
10086 +       rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
10087 +       rwptr_reg.bits.rptr = 0;
10088 +       writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
10089 +}
10090 +
10091 +/*----------------------------------------------------------------------
10092 +*      sl351x_gmac_release_hw_free_q
10093 +*----------------------------------------------------------------------*/
10094 +#ifdef CONFIG_SL351x_NAT
10095 +static void sl351x_gmac_release_hwtx_q(void)
10096 +{
10097 +       int                             i;
10098 +       unsigned int    rwptr_addr;
10099 +
10100 +       rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
10101 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
10102 +       {
10103 +               writel(0, rwptr_addr);
10104 +               rwptr_addr+=4;
10105 +       }
10106 +       rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
10107 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
10108 +       {
10109 +               writel(0, rwptr_addr);
10110 +               rwptr_addr+=4;
10111 +       }
10112 +}
10113 +#endif
10114 +
10115 +/*----------------------------------------------------------------------
10116 +*      sl351x_gmac_save_reg
10117 +*----------------------------------------------------------------------*/
10118 +void sl351x_gmac_save_reg(void)
10119 +{
10120 +       int     i;
10121 +       volatile u32    *destp;
10122 +       unsigned int    srce_addr;
10123 +
10124 +       srce_addr = TOE_GLOBAL_BASE;
10125 +       destp = (volatile u32 *)toe_global_reg;
10126 +       for (i=0; i<TOE_GLOBAL_REG_SIZE; i++, destp++, srce_addr+=4)
10127 +               *destp = readl(srce_addr);
10128 +
10129 +       srce_addr = TOE_GMAC0_DMA_BASE;
10130 +       destp = (volatile u32 *)&toe_dma_reg[0][0];
10131 +       for (i=0; i<TOE_DMA_REG_SIZE; i++, destp++, srce_addr+=4)
10132 +       {
10133 +               if (srce_addr ==  (TOE_GMAC0_DMA_BASE+0x38))
10134 +                       srce_addr = (TOE_GMAC0_DMA_BASE+0x50);
10135 +               if (srce_addr ==  (TOE_GMAC0_DMA_BASE+0x58))
10136 +                       srce_addr = (TOE_GMAC0_DMA_BASE+0x70);
10137 +
10138 +               *destp = readl(srce_addr);
10139 +       }
10140 +       srce_addr = TOE_GMAC1_DMA_BASE;
10141 +       destp = (volatile u32 *)&toe_dma_reg[1][0];
10142 +       for (i=0; i<TOE_DMA_REG_SIZE; i++, destp++, srce_addr+=4)
10143 +       {
10144 +               if (srce_addr ==  (TOE_GMAC0_DMA_BASE+0x38))
10145 +                       srce_addr = (TOE_GMAC0_DMA_BASE+0x50);
10146 +               if (srce_addr ==  (TOE_GMAC0_DMA_BASE+0x58))
10147 +                       srce_addr = (TOE_GMAC0_DMA_BASE+0x70);
10148 +
10149 +               *destp = readl(srce_addr);
10150 +       }
10151 +
10152 +       srce_addr = TOE_GMAC0_BASE;
10153 +       destp = (volatile u32 *)&toe_gmac_reg[0][0];
10154 +       for (i=0; i<TOE_GMAC_REG_SIZE; i++, destp++, srce_addr+=4)
10155 +               *destp = readl(srce_addr);
10156 +
10157 +       srce_addr = TOE_GMAC1_BASE;
10158 +       destp = (volatile u32 *)&toe_gmac_reg[1][0];
10159 +       for (i=0; i<TOE_GMAC_REG_SIZE; i++, destp++, srce_addr+=4)
10160 +               *destp = readl(srce_addr);
10161 +}
10162 +
10163 +/*----------------------------------------------------------------------
10164 +*      sl351x_gmac_restore_reg
10165 +*----------------------------------------------------------------------*/
10166 +void sl351x_gmac_restore_reg(void)
10167 +{
10168 +       int     i;
10169 +       volatile u32    *srcep;
10170 +       unsigned int    dest_addr;
10171 +
10172 +       srcep = (volatile u32 *)&toe_dma_reg[0][0];
10173 +       dest_addr = TOE_GMAC0_DMA_BASE;
10174 +       for (i=0; i<TOE_DMA_REG_SIZE; i++, dest_addr+=4, srcep++)
10175 +       {
10176 +               if (dest_addr == (TOE_GMAC0_DMA_BASE+0x38))
10177 +                       dest_addr = (TOE_GMAC0_DMA_BASE+0x50);
10178 +               if (dest_addr == (TOE_GMAC0_DMA_BASE+0x58))
10179 +                       dest_addr = (TOE_GMAC0_DMA_BASE+0x70);
10180 +
10181 +               writel(*srcep, dest_addr);
10182 +               // gmac_write_reg(dest_addr, 0, *srcep, 0xffffffff);
10183 +       }
10184 +       srcep = (volatile u32 *)&toe_dma_reg[1][0];
10185 +       dest_addr = TOE_GMAC1_DMA_BASE;
10186 +       for (i=0; i<TOE_DMA_REG_SIZE; i++, dest_addr+=4, srcep++)
10187 +       {
10188 +               if (dest_addr == (TOE_GMAC0_DMA_BASE+0x38))
10189 +                       dest_addr = (TOE_GMAC0_DMA_BASE+0x50);
10190 +               if (dest_addr == (TOE_GMAC0_DMA_BASE+0x58))
10191 +                       dest_addr = (TOE_GMAC0_DMA_BASE+0x70);
10192 +
10193 +               writel(*srcep, dest_addr);
10194 +               // gmac_write_reg(dest_addr, 0, *srcep, 0xffffffff);
10195 +       }
10196 +
10197 +       srcep = (volatile u32 *)&toe_gmac_reg[0][0];
10198 +       dest_addr = TOE_GMAC0_BASE;
10199 +       for (i=0; i<TOE_GMAC_REG_SIZE; i++, dest_addr+=4, srcep++)
10200 +               writel(*srcep, dest_addr);
10201 +
10202 +       srcep = (volatile u32 *)&toe_gmac_reg[1][0];
10203 +       dest_addr = TOE_GMAC1_BASE;
10204 +       for (i=0; i<TOE_GMAC_REG_SIZE; i++, dest_addr+=4, srcep++)
10205 +               writel(*srcep, dest_addr);
10206 +
10207 +       srcep = (volatile u32 *)toe_global_reg;
10208 +       dest_addr = TOE_GLOBAL_BASE;
10209 +       for (i=0; i<TOE_GLOBAL_REG_SIZE; i++, dest_addr+=4, srcep++)
10210 +               writel(*srcep, dest_addr);
10211 +
10212 +}
10213 +
10214 +#ifdef CONFIG_SL351x_NAT
10215 +/*----------------------------------------------------------------------
10216 +*      sl351x_nat_workaround_init
10217 +*----------------------------------------------------------------------*/
10218 +#define NAT_WORAROUND_DESC_POWER       (6)
10219 +#define NAT_WORAROUND_DESC_NUM         (2 << NAT_WORAROUND_DESC_POWER)
10220 +dma_addr_t sl351x_nat_workaround_desc_dma;
10221 +void sl351x_nat_workaround_init(void)
10222 +{
10223 +       unsigned int    desc_buf;
10224 +
10225 +       desc_buf = (unsigned int)DMA_MALLOC((NAT_WORAROUND_DESC_NUM * sizeof(GMAC_RXDESC_T)),
10226 +                                               (dma_addr_t *)&sl351x_nat_workaround_desc_dma) ;
10227 +       memset((void *)desc_buf, 0, NAT_WORAROUND_DESC_NUM * sizeof(GMAC_RXDESC_T));
10228 +
10229 +       // DMA Queue Base & Size
10230 +       writel((sl351x_nat_workaround_desc_dma & DMA_Q_BASE_MASK) | NAT_WORAROUND_DESC_POWER,
10231 +                       TOE_GLOBAL_BASE + 0x4080);
10232 +       writel(0, TOE_GLOBAL_BASE + 0x4084);
10233 +}
10234 +
10235 +/*----------------------------------------------------------------------
10236 +*      sl351x_nat_workaround_handler
10237 +*----------------------------------------------------------------------*/
10238 +#ifndef NAT_WORKAROUND_BY_RESET_GMAC
10239 +static void sl351x_nat_workaround_handler(void)
10240 +{
10241 +       int                                     i;
10242 +       DMA_RWPTR_T                     rwptr;
10243 +       GMAC_RXDESC_T           *desc_ptr;
10244 +       unsigned int            buf_ptr;
10245 +       TOE_INFO_T                      *toe;
10246 +       GMAC_CONFIG0_T          config0;
10247 +       unsigned int            rwptr_addr;
10248 +
10249 +       toe = (TOE_INFO_T *)&toe_private_data;
10250 +
10251 +       // disable Rx of GMAC-0 & 1
10252 +       config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
10253 +       config0.bits.dis_rx = 1;
10254 +       writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
10255 +       config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
10256 +       config0.bits.dis_rx = 1;
10257 +       writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
10258 +
10259 +       // wait GMAC-0 HW Tx finished
10260 +       rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
10261 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
10262 +       {
10263 +               rwptr.bits32 = readl(rwptr_addr);
10264 +               if (rwptr.bits.rptr != rwptr.bits.wptr)
10265 +                       return; // wait the HW to send packets and release buffers
10266 +               rwptr_addr+=4;
10267 +       }
10268 +       rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
10269 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
10270 +       {
10271 +               rwptr.bits32 = readl(rwptr_addr);
10272 +               if (rwptr.bits.rptr != rwptr.bits.wptr)
10273 +                       return; // wait the HW to send packets and release buffers
10274 +               rwptr_addr+=4;
10275 +       }
10276 +
10277 +       // printk("sl351x_nat_workaround_handler %d\n", sl351x_nat_workaround_cnt);
10278 +       desc_ptr = (GMAC_RXDESC_T *)toe->hwfq_desc_base;
10279 +       buf_ptr = (unsigned int)toe->hwfq_buf_base_dma;
10280 +       for (i=0; i<TOE_HW_FREEQ_DESC_NUM; i++)
10281 +       {
10282 +               desc_ptr->word0.bits.buffer_size = HW_RX_BUF_SIZE;
10283 +               desc_ptr->word1.bits.sw_id = i;
10284 +               desc_ptr->word2.buf_adr = (unsigned int)buf_ptr;
10285 +               desc_ptr++;
10286 +               buf_ptr += HW_RX_BUF_SIZE;
10287 +       }
10288 +       rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
10289 +       rwptr.bits.wptr = RWPTR_RECEDE_ONE(rwptr.bits.rptr, TOE_HW_FREEQ_DESC_NUM);
10290 +       writel(rwptr.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
10291 +       writel(0, TOE_GLOBAL_BASE + 0x4084);
10292 +
10293 +       // Enable Rx of GMAC-0 & 1
10294 +       config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
10295 +       config0.bits.dis_rx = 0;
10296 +       writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
10297 +       config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
10298 +       config0.bits.dis_rx = 0;
10299 +       writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
10300 +}
10301 +#endif
10302 +#endif // CONFIG_SL351x_NAT
10303 +
10304 +#endif // SL351x_GMAC_WORKAROUND
10305 +
10306 +/* get the mac addresses from flash
10307 + *can't do this in module_init because mtd driver is initialized after ethernet
10308 + */
10309 +static __init int sl351x_mac_address_init(void)
10310 +{
10311 +       GMAC_INFO_T             *tp;
10312 +       struct sockaddr sock;
10313 +       int i;
10314 +
10315 +       /* get mac address from FLASH */
10316 +       gmac_get_mac_address();
10317 +
10318 +       for (i = 0; i < GMAC_NUM; i++) {
10319 +               tp = (GMAC_INFO_T *)&toe_private_data.gmac[i];
10320 +               memcpy(&sock.sa_data[0],&eth_mac[tp->port_id][0],6);
10321 +               gmac_set_mac_address(tp->dev,(void *)&sock);
10322 +       }
10323 +
10324 +        return 0;
10325 +}
10326 +late_initcall(sl351x_mac_address_init);
10327 +
10328 +
10329 --- /dev/null
10330 +++ b/drivers/net/sl351x_hash.c
10331 @@ -0,0 +1,713 @@
10332 +/**************************************************************************
10333 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
10334 +*--------------------------------------------------------------------------
10335 +* Name                 : sl351x_hash.c
10336 +* Description  :
10337 +*              Handle Storlink SL351x Hash Functions
10338 +*
10339 +* History
10340 +*
10341 +*      Date            Writer          Description
10342 +*----------------------------------------------------------------------------
10343 +*      03/13/2006      Gary Chen       Create and implement
10344 +*
10345 +****************************************************************************/
10346 +#include <linux/module.h>
10347 +#include <linux/kernel.h>
10348 +#include <linux/compiler.h>
10349 +#include <linux/pci.h>
10350 +#include <linux/init.h>
10351 +#include <linux/ioport.h>
10352 +#include <linux/netdevice.h>
10353 +#include <linux/etherdevice.h>
10354 +#include <linux/rtnetlink.h>
10355 +#include <linux/delay.h>
10356 +#include <linux/ethtool.h>
10357 +#include <linux/mii.h>
10358 +#include <linux/completion.h>
10359 +#include <asm/hardware.h>
10360 +#include <asm/io.h>
10361 +#include <asm/irq.h>
10362 +#include <asm/semaphore.h>
10363 +#include <asm/arch/irqs.h>
10364 +#include <asm/arch/it8712.h>
10365 +#include <linux/mtd/kvctl.h>
10366 +#include <linux/skbuff.h>
10367 +#include <linux/in.h>
10368 +#include <linux/ip.h>
10369 +#include <linux/tcp.h>
10370 +#include <linux/list.h>
10371 +#define         MIDWAY
10372 +#define         SL_LEPUS
10373 +
10374 +#include <asm/arch/sl2312.h>
10375 +#include <asm/arch/sl351x_gmac.h>
10376 +#include <asm/arch/sl351x_hash_cfg.h>
10377 +
10378 +#ifndef RXTOE_DEBUG
10379 +#define RXTOE_DEBUG
10380 +#endif
10381 +#undef RXTOE_DEBUG
10382 +
10383 +/*----------------------------------------------------------------------
10384 +* Definition
10385 +*----------------------------------------------------------------------*/
10386 +#define        hash_printf                             printk
10387 +
10388 +#define HASH_TIMER_PERIOD              (30)    // seconds
10389 +#define HASH_ILLEGAL_INDEX             0xffff
10390 +
10391 +/*----------------------------------------------------------------------
10392 +* Variables
10393 +*----------------------------------------------------------------------*/
10394 +u32                                    hash_nat_owner_bits[HASH_TOTAL_ENTRIES/32];
10395 +char                           hash_tables[HASH_TOTAL_ENTRIES][HASH_MAX_BYTES] __attribute__ ((aligned(16)));
10396 +static struct timer_list hash_timer_obj;
10397 +LIST_HEAD(hash_timeout_list);
10398 +
10399 +/*----------------------------------------------------------------------
10400 +* Functions
10401 +*----------------------------------------------------------------------*/
10402 +void dm_long(u32 location, int length);
10403 +static void hash_timer_func(u32 data);
10404 +
10405 +/*----------------------------------------------------------------------
10406 +* hash_init
10407 +*----------------------------------------------------------------------*/
10408 +void sl351x_hash_init(void)
10409 +{
10410 +       int i;
10411 +       volatile u32 *dp1, *dp2, dword;
10412 +
10413 +       dp1 = (volatile u32 *) TOE_V_BIT_BASE;
10414 +       dp2 = (volatile u32 *) TOE_A_BIT_BASE;
10415 +
10416 +       for (i=0; i<HASH_TOTAL_ENTRIES/32; i++)
10417 +       {
10418 +               *dp1++ = 0;
10419 +               dword = *dp2++; // read-clear
10420 +       }
10421 +       memset((void *)&hash_nat_owner_bits, 0, sizeof(hash_nat_owner_bits));
10422 +       memset((void *)&hash_tables, 0, sizeof(hash_tables));
10423 +
10424 +       init_timer(&hash_timer_obj);
10425 +       hash_timer_obj.expires = jiffies + (HASH_TIMER_PERIOD * HZ);
10426 +       hash_timer_obj.data = (unsigned long)&hash_timer_obj;
10427 +       hash_timer_obj.function = (void *)&hash_timer_func;
10428 +       add_timer(&hash_timer_obj);
10429 +
10430 +#if (HASH_MAX_BYTES == 128)
10431 +       writel((unsigned long)__pa(&hash_tables) | 3,   // 32 words
10432 +                       TOE_GLOBAL_BASE + GLOBAL_HASH_TABLE_BASE_REG);
10433 +#elif (HASH_MAX_BYTES == 64)
10434 +       writel((unsigned long)__pa(&hash_tables) | 2,   // 16 words
10435 +                       TOE_GLOBAL_BASE + GLOBAL_HASH_TABLE_BASE_REG);
10436 +#else
10437 +       #error Incorrect setting for HASH_MAX_BYTES
10438 +#endif
10439 +
10440 +}
10441 +/*----------------------------------------------------------------------
10442 +* hash_add_entry
10443 +*----------------------------------------------------------------------*/
10444 +int hash_add_entry(HASH_ENTRY_T *entry)
10445 +{
10446 +       int     rc;
10447 +       u32     key[HASH_MAX_DWORDS];
10448 +       rc = hash_build_keys((u32 *)&key, entry);
10449 +       if (rc < 0)
10450 +               return -1;
10451 +       hash_write_entry(entry, (unsigned char*) &key[0]);
10452 +//     hash_set_valid_flag(entry->index, 1);
10453 +//     printk("Dump hash key!\n");
10454 +//     dump_hash_key(entry);
10455 +       return entry->index;
10456 +}
10457 +
10458 +/*----------------------------------------------------------------------
10459 +* hash_set_valid_flag
10460 +*----------------------------------------------------------------------*/
10461 +void hash_set_valid_flag(int index, int valid)
10462 +{
10463 +       register u32 reg32;
10464 +
10465 +       reg32 = TOE_V_BIT_BASE + (index/32) * 4;
10466 +
10467 +       if (valid)
10468 +       {
10469 +               writel(readl(reg32) | (1 << (index%32)), reg32);
10470 +       }
10471 +       else
10472 +       {
10473 +               writel(readl(reg32) & ~(1 << (index%32)), reg32);
10474 +       }
10475 +}
10476 +
10477 +/*----------------------------------------------------------------------
10478 +* hash_set_nat_owner_flag
10479 +*----------------------------------------------------------------------*/
10480 +void hash_set_nat_owner_flag(int index, int valid)
10481 +{
10482 +       if (valid)
10483 +       {
10484 +               hash_nat_owner_bits[index/32] |= (1 << (index % 32));
10485 +       }
10486 +       else
10487 +       {
10488 +               hash_nat_owner_bits[index/32] &= ~(1 << (index % 32));
10489 +       }
10490 +}
10491 +
10492 +
10493 +/*----------------------------------------------------------------------
10494 +* hash_build_keys
10495 +*----------------------------------------------------------------------*/
10496 +int hash_build_keys(u32 *destp, HASH_ENTRY_T *entry)
10497 +{
10498 +       u32     data;
10499 +       unsigned char   *cp;
10500 +       int                             i, j;
10501 +       unsigned short  index;
10502 +       int                     total;
10503 +
10504 +       memset((void *)destp, 0, HASH_MAX_BYTES);
10505 +       cp = (unsigned char *)destp;
10506 +
10507 +       if (entry->key_present.port || entry->key_present.Ethertype)
10508 +       {
10509 +               HASH_PUSH_WORD(cp, entry->key.Ethertype);               // word 0
10510 +               HASH_PUSH_BYTE(cp, entry->key.port);                    // Byte 2
10511 +               HASH_PUSH_BYTE(cp, 0);                                                  // Byte 3
10512 +       }
10513 +       else
10514 +       {
10515 +               HASH_PUSH_DWORD(cp, 0);
10516 +       }
10517 +
10518 +       if (entry->key_present.da || entry->key_present.sa)
10519 +       {
10520 +               unsigned char mac[4];
10521 +               if (entry->key_present.da)
10522 +               {
10523 +                       for (i=0; i<4; i++)
10524 +                               HASH_PUSH_BYTE(cp, entry->key.da[i]);
10525 +               }
10526 +               mac[0] = (entry->key_present.da) ? entry->key.da[4] : 0;
10527 +               mac[1] = (entry->key_present.da) ? entry->key.da[5] : 0;
10528 +               mac[2] = (entry->key_present.sa) ? entry->key.sa[0] : 0;
10529 +               mac[3] = (entry->key_present.sa) ? entry->key.sa[1] : 0;
10530 +               data = mac[0] + (mac[1]<<8) + (mac[2]<<16) + (mac[3]<<24);
10531 +               HASH_PUSH_DWORD(cp, data);
10532 +               if (entry->key_present.sa)
10533 +               {
10534 +                       for (i=2; i<6; i++)
10535 +                               HASH_PUSH_BYTE(cp, entry->key.sa[i]);
10536 +               }
10537 +       }
10538 +
10539 +       if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
10540 +       {
10541 +               HASH_PUSH_WORD(cp, entry->key.vlan_id);         // low word
10542 +               HASH_PUSH_WORD(cp, entry->key.pppoe_sid);       // high word
10543 +       }
10544 +       if (entry->key_present.ipv4_hdrlen || entry->key_present.ip_tos || entry->key_present.ip_protocol)
10545 +       {
10546 +               HASH_PUSH_BYTE(cp, entry->key.ip_protocol);             // Byte 0
10547 +               HASH_PUSH_BYTE(cp, entry->key.ip_tos);                  // Byte 1
10548 +               HASH_PUSH_BYTE(cp, entry->key.ipv4_hdrlen);             // Byte 2
10549 +               HASH_PUSH_BYTE(cp, 0);                                                  // Byte 3
10550 +       }
10551 +
10552 +       if (entry->key_present.ipv6_flow_label)
10553 +       {
10554 +               HASH_PUSH_DWORD(cp, entry->key.ipv6_flow_label);        // low word
10555 +       }
10556 +       if (entry->key_present.sip)
10557 +       {
10558 +               // input (entry->key.sip[i]) is network-oriented
10559 +               // output (hash key) is host-oriented
10560 +               for (i=3; i>=0; i--)
10561 +                       HASH_PUSH_BYTE(cp, entry->key.sip[i]);
10562 +               if (entry->key.ipv6)
10563 +               {
10564 +                       for (i=4; i<16; i+=4)
10565 +                       {
10566 +                               for (j=i+3; j>=i; j--)
10567 +                                       HASH_PUSH_BYTE(cp, entry->key.sip[j]);
10568 +                       }
10569 +               }
10570 +       }
10571 +       if (entry->key_present.dip)
10572 +       {
10573 +               // input (entry->key.sip[i]) is network-oriented
10574 +               // output (hash key) is host-oriented
10575 +               for (i=3; i>=0; i--)
10576 +                       HASH_PUSH_BYTE(cp, entry->key.dip[i]);
10577 +               if (entry->key.ipv6)
10578 +               {
10579 +                       for (i=4; i<16; i+=4)
10580 +                       {
10581 +                               for (j=i+3; j>=i; j--)
10582 +                                       HASH_PUSH_BYTE(cp, entry->key.dip[j]);
10583 +                       }
10584 +               }
10585 +       }
10586 +
10587 +       if (entry->key_present.l4_bytes_0_3)
10588 +       {
10589 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
10590 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
10591 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
10592 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
10593 +       }
10594 +       if (entry->key_present.l4_bytes_4_7)
10595 +       {
10596 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[4]);
10597 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[5]);
10598 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[6]);
10599 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[7]);
10600 +       }
10601 +       if (entry->key_present.l4_bytes_8_11)
10602 +       {
10603 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[8]);
10604 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[9]);
10605 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[10]);
10606 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[11]);
10607 +       }
10608 +       if (entry->key_present.l4_bytes_12_15)
10609 +       {
10610 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[12]);
10611 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[13]);
10612 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[14]);
10613 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[15]);
10614 +       }
10615 +       if (entry->key_present.l4_bytes_16_19)
10616 +       {
10617 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[16]);
10618 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[17]);
10619 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[18]);
10620 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[19]);
10621 +       }
10622 +       if (entry->key_present.l4_bytes_20_23)
10623 +       {
10624 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[20]);
10625 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[21]);
10626 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[22]);
10627 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[23]);
10628 +       }
10629 +       if (entry->key_present.l7_bytes_0_3)
10630 +       {
10631 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[0]);
10632 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[1]);
10633 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[2]);
10634 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[3]);
10635 +       }
10636 +       if (entry->key_present.l7_bytes_4_7)
10637 +       {
10638 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[4]);
10639 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[5]);
10640 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[6]);
10641 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[7]);
10642 +       }
10643 +       if (entry->key_present.l7_bytes_8_11)
10644 +       {
10645 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[8]);
10646 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[9]);
10647 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[10]);
10648 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[11]);
10649 +       }
10650 +       if (entry->key_present.l7_bytes_12_15)
10651 +       {
10652 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[12]);
10653 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[13]);
10654 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[14]);
10655 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[15]);
10656 +       }
10657 +       if (entry->key_present.l7_bytes_16_19)
10658 +       {
10659 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[16]);
10660 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[17]);
10661 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[18]);
10662 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[19]);
10663 +       }
10664 +       if (entry->key_present.l7_bytes_20_23)
10665 +       {
10666 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[20]);
10667 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[21]);
10668 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[22]);
10669 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[23]);
10670 +       }
10671 +
10672 +       // get hash index
10673 +       total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
10674 +
10675 +       if (total > HASH_MAX_KEY_DWORD)
10676 +       {
10677 +               //hash_printf("Total key words (%d) is too large (> %d)!\n",
10678 +               //                              total, HASH_MAX_KEY_DWORD);
10679 +               return -1;
10680 +       }
10681 +
10682 +       if (entry->key_present.port || entry->key_present.Ethertype)
10683 +               index = hash_gen_crc16((unsigned char *)destp, total * 4);
10684 +       else
10685 +       {
10686 +               if (total == 1)
10687 +               {
10688 +                       hash_printf("No key is assigned!\n");
10689 +                       return -1;
10690 +               }
10691 +
10692 +               index = hash_gen_crc16((unsigned char *)(destp+1), (total-1) * 4);
10693 +       }
10694 +
10695 +       entry->index = index & HASH_BITS_MASK;
10696 +
10697 +       //hash_printf("Total key words = %d, Hash Index= %d\n",
10698 +       //                              total, entry->index);
10699 +
10700 +       cp = (unsigned char *)destp;
10701 +       cp+=3;
10702 +       HASH_PUSH_BYTE(cp, entry->rule);        // rule
10703 +
10704 +       entry->total_dwords = total;
10705 +
10706 +       return total;
10707 +}
10708 +
10709 +/*----------------------------------------------------------------------
10710 +* hash_build_nat_keys
10711 +*----------------------------------------------------------------------*/
10712 +void hash_build_nat_keys(u32 *destp, HASH_ENTRY_T *entry)
10713 +{
10714 +       unsigned char   *cp;
10715 +       int                             i;
10716 +       unsigned short  index;
10717 +       int                     total;
10718 +
10719 +       memset((void *)destp, 0, HASH_MAX_BYTES);
10720 +
10721 +       cp = (unsigned char *)destp + 2;
10722 +       HASH_PUSH_BYTE(cp, entry->key.port);
10723 +       cp++;
10724 +
10725 +       if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
10726 +       {
10727 +               HASH_PUSH_WORD(cp, entry->key.vlan_id);         // low word
10728 +               HASH_PUSH_WORD(cp, entry->key.pppoe_sid);       // high word
10729 +       }
10730 +
10731 +       HASH_PUSH_BYTE(cp, entry->key.ip_protocol);
10732 +       cp+=3;
10733 +
10734 +       // input (entry->key.sip[i]) is network-oriented
10735 +       // output (hash key) is host-oriented
10736 +       for (i=3; i>=0; i--)
10737 +               HASH_PUSH_BYTE(cp, entry->key.sip[i]);
10738 +
10739 +       // input (entry->key.sip[i]) is network-oriented
10740 +       // output (hash key) is host-oriented
10741 +       for (i=3; i>=0; i--)
10742 +               HASH_PUSH_BYTE(cp, entry->key.dip[i]);
10743 +
10744 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
10745 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
10746 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
10747 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
10748 +
10749 +       // get hash index
10750 +       total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
10751 +
10752 +       index = hash_gen_crc16((unsigned char *)destp, total * 4);
10753 +       entry->index = index & ((1 << HASH_BITS) - 1);
10754 +
10755 +       cp = (unsigned char *)destp;
10756 +       cp+=3;
10757 +       HASH_PUSH_BYTE(cp, entry->rule);        // rule
10758 +
10759 +       entry->total_dwords = total;
10760 +}
10761 +
10762 +/*----------------------------------------------------------------------
10763 +* hash_build_toe_keys
10764 +*----------------------------------------------------------------------*/
10765 +int hash_build_toe_keys(u32 *destp, HASH_ENTRY_T *entry)
10766 +{
10767 +       unsigned long   data;
10768 +       unsigned char   *cp;
10769 +       unsigned short  index;
10770 +       int     i;
10771 +       int total;
10772 +       //printk("%s\n", __func__);
10773 +       memset((void*)destp, 0, HASH_MAX_BYTES);
10774 +       cp = (unsigned char*)destp;
10775 +
10776 +       if(entry->key_present.port || entry->key_present.Ethertype) {
10777 +               data = (entry->key.port << 16) + entry->key.Ethertype;
10778 +               HASH_PUSH_DWORD(cp, data);
10779 +       } else
10780 +               HASH_PUSH_DWORD(cp, 0);
10781 +
10782 +       if (entry->key_present.da || entry->key_present.sa) {
10783 +               unsigned char   mac[4];
10784 +               if (entry->key_present.da) {
10785 +                       data = (entry->key.da[0]) + (entry->key.da[1] << 8) +
10786 +                                  (entry->key.da[2] << 16) + (entry->key.da[3] <<24);
10787 +                       HASH_PUSH_DWORD(cp, data);
10788 +               }
10789 +               mac[0] = (entry->key_present.da) ? entry->key.da[4] : 0;
10790 +               mac[1] = (entry->key_present.da) ? entry->key.da[5] : 0;
10791 +               mac[2] = (entry->key_present.sa) ? entry->key.sa[0] : 0;
10792 +               mac[3] = (entry->key_present.sa) ? entry->key.sa[1] : 0;
10793 +               data = mac[0] + (mac[1]<<8) + (mac[2]<<16) + (mac[3]<<24);
10794 +               HASH_PUSH_DWORD(cp, data);
10795 +               if (entry->key_present.sa) {
10796 +                       data = (entry->key.sa[2]) + (entry->key.sa[3] << 8) +
10797 +                                  (entry->key.sa[4] << 16) + (entry->key.sa[5] <<24);
10798 +                       HASH_PUSH_DWORD(cp, data);
10799 +               }
10800 +       }
10801 +
10802 +       if (entry->key_present.ip_protocol) {
10803 +               unsigned char ip_protocol;
10804 +               ip_protocol = entry->key.ip_protocol;
10805 +               data = ip_protocol;
10806 +               HASH_PUSH_DWORD(cp, data);
10807 +       }
10808 +
10809 +       if (entry->key_present.ipv6_flow_label) {
10810 +               unsigned long flow_label;
10811 +               flow_label  = entry->key.ipv6_flow_label;
10812 +               data = flow_label & 0xfffff;
10813 +               HASH_PUSH_DWORD(cp, data);
10814 +       }
10815 +
10816 +       if (entry->key_present.sip)     {
10817 +               {
10818 +                       data = IPIV(entry->key.sip[0], entry->key.sip[1],
10819 +                                       entry->key.sip[2], entry->key.sip[3]);
10820 +                       HASH_PUSH_DWORD(cp, data);
10821 +                       if (entry->key.ipv6) {
10822 +                               for (i=4; i<16; i+=4) {
10823 +                                       data = IPIV(entry->key.sip[i+0], entry->key.sip[i+1],
10824 +                                                       entry->key.sip[i+2], entry->key.sip[i+3]);
10825 +                                       HASH_PUSH_DWORD(cp, data);
10826 +                               }
10827 +                       }
10828 +               }
10829 +       }
10830 +
10831 +       if (entry->key_present.dip)     {
10832 +               {
10833 +                       data = IPIV(entry->key.dip[0], entry->key.dip[1],
10834 +                                               entry->key.dip[2], entry->key.dip[3]);
10835 +                       HASH_PUSH_DWORD(cp, data);
10836 +                       if (entry->key.ipv6) {
10837 +                               for (i=4; i<16; i+=4) {
10838 +                                       data = IPIV(entry->key.dip[i+0], entry->key.dip[i+1],
10839 +                                                               entry->key.dip[i+2], entry->key.dip[i+3]);
10840 +                                       HASH_PUSH_DWORD(cp, data);
10841 +                               }
10842 +                       }
10843 +               }
10844 +       }
10845 +       if (entry->key_present.l4_bytes_0_3)
10846 +       {
10847 +               unsigned char *datap;
10848 +               datap = &entry->key.l4_bytes[0];
10849 +               data =  datap[0] +      (datap[1] << 8) + (datap[2] << 16) + (datap[3] << 24);
10850 +               HASH_PUSH_DWORD(cp, data);
10851 +       }
10852 +       if (entry->key_present.l7_bytes_0_3)
10853 +       {
10854 +               unsigned char *datap;
10855 +               datap = &entry->key.l7_bytes[0];
10856 +               data =  datap[0] +      (datap[1] << 8) + (datap[2] << 16) + (datap[3] << 24);
10857 +               HASH_PUSH_DWORD(cp, data);
10858 +       }
10859 +       if (entry->key_present.l7_bytes_4_7)
10860 +       {
10861 +               unsigned char *datap;
10862 +               datap = &entry->key.l7_bytes[4];
10863 +               data =  datap[0] +      (datap[1] << 8) + (datap[2] << 16) + (datap[3] << 24);
10864 +               HASH_PUSH_DWORD(cp, data);
10865 +       }
10866 +
10867 +       total = (unsigned long)((unsigned long)cp - (unsigned long)destp) / (sizeof(u32));
10868 +       if (total > HASH_MAX_KEY_DWORD) {
10869 +               //printf("Total key words (%d) is too large (> %d)!\n",
10870 +               //              total, HASH_MAX_KEY_DWORD);
10871 +               return -1;
10872 +       }
10873 +       index = hash_gen_crc16((unsigned char*)(destp + 1), (total-1)*4);
10874 +       entry->index = index & ((1 << HASH_BITS)-1);
10875 +
10876 +       cp = (unsigned char*) destp;
10877 +       cp += 3;
10878 +       HASH_PUSH_BYTE(cp, entry->rule);
10879 +       entry->total_dwords = total;
10880 +       return total;
10881 +}
10882 +
10883 +/*----------------------------------------------------------------------
10884 +* hash_add_toe_entry
10885 +*----------------------------------------------------------------------*/
10886 +int hash_add_toe_entry(HASH_ENTRY_T *entry)
10887 +{
10888 +       int     rc;
10889 +       u32     key[HASH_MAX_DWORDS];
10890 +
10891 +       rc = hash_build_toe_keys((u32 *)&key, entry);
10892 +       if (rc < 0)
10893 +               return -1;
10894 +       hash_write_entry(entry, (unsigned char*) &key[0]);
10895 +       //hash_dump_entry(entry->index);
10896 +//     hash_set_valid_flag(entry->index, 1);
10897 +//     printk("Dump hash key!\n");
10898 +//     dump_hash_key(entry);
10899 +       return entry->index;
10900 +}
10901 +
10902 +
10903 +/*----------------------------------------------------------------------
10904 +* hash_write_entry
10905 +*----------------------------------------------------------------------*/
10906 +int hash_write_entry(HASH_ENTRY_T *entry, unsigned char *key)
10907 +{
10908 +       int             i;
10909 +       u32             *srcep, *destp, *destp2;
10910 +
10911 +       srcep = (u32 *)key;
10912 +       destp2 = destp = (u32 *)&hash_tables[entry->index][0];
10913 +
10914 +       for (i=0; i<(entry->total_dwords); i++, srcep++, destp++)
10915 +               *destp = *srcep;
10916 +
10917 +       srcep = (u32 *)&entry->action;
10918 +       *destp++ = *srcep;
10919 +
10920 +       srcep = (u32 *)&entry->param;
10921 +       for (i=0; i<(sizeof(ENTRY_PARAM_T)/sizeof(*destp)); i++, srcep++, destp++)
10922 +               *destp = *srcep;
10923 +
10924 +       memset(destp, 0, (HASH_MAX_DWORDS-entry->total_dwords-HASH_ACTION_DWORDS) * sizeof(u32));
10925 +
10926 +       consistent_sync(destp2, (entry->total_dwords+HASH_ACTION_DWORDS) * 4, PCI_DMA_TODEVICE);
10927 +       return 0;
10928 +}
10929 +
10930 +/*----------------------------------------------------------------------
10931 +* hash_timer_func
10932 +*----------------------------------------------------------------------*/
10933 +static void hash_timer_func(u32 data)
10934 +{
10935 +       int                                     i, j, idx;
10936 +       volatile u32            *own_p, *valid_p;
10937 +       u32                                     own_bits, a_bits;
10938 +       int                                     period = HASH_TIMER_PERIOD;
10939 +
10940 +       valid_p = (volatile u32 *)TOE_V_BIT_BASE;
10941 +       own_p = (volatile u32 *)hash_nat_owner_bits;
10942 +       for (i=0, idx=0; i<(HASH_TOTAL_ENTRIES/32); i++, own_p++, valid_p++, idx+=32)
10943 +       {
10944 +               a_bits = readl(TOE_A_BIT_BASE + (i*4));
10945 +               own_bits = *own_p;
10946 +               if (own_bits)
10947 +               {
10948 +                       for (j=0; own_bits && j<32; j++)
10949 +                       {
10950 +                               if (own_bits & 1)
10951 +                               {
10952 +                                       short *counter_p, *interval_p;
10953 +                                       NAT_HASH_ENTRY_T        *nat_entry;
10954 +                                       GRE_HASH_ENTRY_T        *gre_entry;
10955 +                                       nat_entry = (NAT_HASH_ENTRY_T *)hash_get_entry(idx+j);
10956 +                                       gre_entry = (GRE_HASH_ENTRY_T *)nat_entry;
10957 +                                       if (nat_entry->key.ip_protocol == IPPROTO_GRE)
10958 +                                       {
10959 +                                               counter_p = (short *)&gre_entry->tmo.counter;
10960 +                                               interval_p = (short *)&gre_entry->tmo.interval;
10961 +                                       }
10962 +                                       else
10963 +                                       {
10964 +                                               counter_p = (short *)&nat_entry->tmo.counter;
10965 +                                               interval_p = (short *)&nat_entry->tmo.interval;
10966 +                                       }
10967 +                                       if (a_bits & 1)
10968 +                                       {
10969 +                                               *counter_p = *interval_p;
10970 +                                       }
10971 +                                       else
10972 +                                       {
10973 +                                               *counter_p -= HASH_TIMER_PERIOD;
10974 +                                               if (*counter_p <= 0)
10975 +                                               {
10976 +                                                       *valid_p &= ~(1 << j);          // invalidate it
10977 +                                                       *own_p &= ~(1 << j);            // release ownership for NAT
10978 +                                                       *counter_p = 0;
10979 +                                                       // hash_printf("%lu %s: Clear hash index: %d\n", jiffies/HZ, __func__, i*32+j);
10980 +                                               }
10981 +                                               else if (period > *counter_p)
10982 +                                               {
10983 +                                                       period = *counter_p;
10984 +                                               }
10985 +                                       }
10986 +                               }
10987 +                               a_bits >>= 1;
10988 +                               own_bits >>=1;
10989 +                       }
10990 +               }
10991 +       }
10992 +
10993 +       hash_timer_obj.expires = jiffies + (period * HZ);
10994 +       add_timer((struct timer_list *)data);
10995 +}
10996 +
10997 +/*----------------------------------------------------------------------
10998 +* dm_long
10999 +*----------------------------------------------------------------------*/
11000 +void dm_long(u32 location, int length)
11001 +{
11002 +       u32             *start_p, *curr_p, *end_p;
11003 +       u32             *datap, data;
11004 +       int             i;
11005 +
11006 +       //if (length > 1024)
11007 +       //      length = 1024;
11008 +
11009 +       start_p = (u32 *)location;
11010 +       end_p = (u32 *)location + length;
11011 +       curr_p = (u32 *)((u32)location & 0xfffffff0);
11012 +       datap = (u32 *)location;
11013 +       while (curr_p < end_p)
11014 +       {
11015 +               hash_printf("0x%08x: ",(u32)curr_p & 0xfffffff0);
11016 +               for (i=0; i<4; i++)
11017 +               {
11018 +                       if (curr_p < start_p || curr_p >= end_p)
11019 +               hash_printf("         ");
11020 +                       else
11021 +                       {
11022 +                               data = *datap;
11023 +                               hash_printf("%08X ", data);
11024 +                       }
11025 +                       if (i==1)
11026 +              hash_printf("- ");
11027 +
11028 +                       curr_p++;
11029 +                       datap++;
11030 +               }
11031 +        hash_printf("\n");
11032 +       }
11033 +}
11034 +
11035 +/*----------------------------------------------------------------------
11036 +* hash_dump_entry
11037 +*----------------------------------------------------------------------*/
11038 +void hash_dump_entry(int index)
11039 +{
11040 +       hash_printf("Hash Index %d:\n", index);
11041 +       dm_long((u32)&hash_tables[index][0], HASH_MAX_DWORDS);
11042 +}
11043 +
11044 +
11045 --- /dev/null
11046 +++ b/drivers/net/sl351x_nat.c
11047 @@ -0,0 +1,1736 @@
11048 +/****************************************************************************
11049 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
11050 +*----------------------------------------------------------------------------
11051 +* Name                 : sl351x_nat.c
11052 +* Description  :
11053 +*              Handle Storlink SL351x NAT Functions
11054 +*
11055 +*
11056 +* Packet Flow:
11057 +*
11058 +*            (xmit)+<--- SW NAT -->+(xmit)
11059 +*                  |       ^^      |
11060 +*                  |       ||      |
11061 +*                  |       ||      |
11062 +*   Client <---> GMAC-x  HW-NAT  GMAC-y  <---> Server
11063 +*
11064 +*
11065 +* History
11066 +*
11067 +*      Date            Writer          Description
11068 +*----------------------------------------------------------------------------
11069 +*      03/13/2006      Gary Chen       Create and implement
11070 +*
11071 +*
11072 +****************************************************************************/
11073 +#include <linux/module.h>
11074 +#include <linux/kernel.h>
11075 +#include <linux/compiler.h>
11076 +#include <linux/pci.h>
11077 +#include <linux/init.h>
11078 +#include <linux/ioport.h>
11079 +#include <linux/netdevice.h>
11080 +#include <linux/etherdevice.h>
11081 +#include <linux/rtnetlink.h>
11082 +#include <linux/delay.h>
11083 +#include <linux/ethtool.h>
11084 +#include <linux/mii.h>
11085 +#include <linux/completion.h>
11086 +#include <asm/hardware.h>
11087 +#include <asm/io.h>
11088 +#include <asm/irq.h>
11089 +#include <asm/semaphore.h>
11090 +#include <asm/arch/irqs.h>
11091 +#include <asm/arch/it8712.h>
11092 +#include <linux/mtd/kvctl.h>
11093 +#include <linux/skbuff.h>
11094 +#include <linux/if_ether.h>
11095 +#include <linux/if_pppox.h>
11096 +#include <linux/in.h>
11097 +#include <linux/ip.h>
11098 +#include <linux/tcp.h>
11099 +#include <linux/udp.h>
11100 +#include <linux/ppp_defs.h>
11101 +
11102 +#define         MIDWAY
11103 +#define         SL_LEPUS
11104 +
11105 +#include <asm/arch/sl2312.h>
11106 +#include <asm/arch/sl351x_gmac.h>
11107 +#include <asm/arch/sl351x_hash_cfg.h>
11108 +#include <asm/arch/sl351x_nat_cfg.h>
11109 +#ifdef CONFIG_NETFILTER
11110 +// #include <linux/netfilter/nf_conntrack.h>
11111 +#include <linux/netfilter/nf_conntrack_tcp.h>
11112 +#endif
11113 +
11114 +//#define NAT_DEBUG_MSG                1
11115 +#define _NOT_CHECK_SIP_DIP
11116 +//#define      SL351x_NAT_TEST_BY_SMARTBITS            1       // Initialize 32 hash entries and test by SmartBITS
11117 +#define VITESSE_G5SWITCH       1
11118 +
11119 +#ifdef CONFIG_SL351x_NAT
11120 +
11121 +/*----------------------------------------------------------------------
11122 +* Definition
11123 +*----------------------------------------------------------------------*/
11124 +#ifdef CONFIG_SL3516_ASIC
11125 +#define CONFIG_SL351x_NAT_TCP_UDP
11126 +#define CONFIG_SL351x_NAT_GRE
11127 +#define CONFIG_SL351x_TCP_UDP_RULE_ID  0
11128 +#define CONFIG_SL351x_GRE_RULE_ID              1
11129 +#else
11130 +#define CONFIG_SL351x_NAT_TCP_UDP
11131 +//#define CONFIG_SL351x_NAT_GRE
11132 +#define CONFIG_SL351x_TCP_UDP_RULE_ID  0
11133 +#define CONFIG_SL351x_GRE_RULE_ID              0
11134 +#endif
11135 +
11136 +#define        nat_printf                                      printk
11137 +#define NAT_FTP_CTRL_PORT                      (21)    // TCP
11138 +#define NAT_H323_PORT                          (1720)  // TCP
11139 +#define NAT_T120_PORT                          (1503)  // TCP
11140 +#define NAT_PPTP_PORT                          (1723)  // TCP
11141 +#define NAT_TFTP_PORT                          (69)    // UDP
11142 +#define NAT_DNS_PORT                           (53)    // UDP
11143 +#define NAT_NTP_PORT                           (123)   // UDP
11144 +#define NAT_RAS_PORT                           (1719)  // UDP
11145 +#define NAT_BOOTP67_PORT                       (67)    // UDP
11146 +#define NAT_BOOTP68_PORT                       (68)    // UDP
11147 +
11148 +#define NAT_TCP_PORT_MAX                       64
11149 +#define NAT_UDP_PORT_MAX                       64
11150 +
11151 +#define GRE_PROTOCOL                           (0x880b)
11152 +#define GRE_PROTOCOL_SWAP                      __constant_htons(0x880b)
11153 +
11154 +#ifdef VITESSE_G5SWITCH
11155 +extern int Giga_switch;
11156 +#endif
11157 +
11158 +typedef struct
11159 +{
11160 +       u16             flags_ver;
11161 +       u16             protocol;
11162 +       u16             payload_length;
11163 +       u16             call_id;
11164 +       u32             seq;
11165 +       u32             ack;
11166 +} GRE_PKTHDR_T;
11167 +
11168 +/*----------------------------------------------------------------------
11169 +* NAT Configuration
11170 +*
11171 +* Note: Any change for network setting, the NAT configuration should
11172 +*       be changed also.
11173 +*      cfg->lan_port   0 if GMAC-0, 1: if GMAC-1
11174 +*      cfg->wan_port   0 if GMAC-0, 1: if GMAC-1
11175 +*      cfg->lan_ipaddr, cfg->lan_gateway, cfg->lan_netmask
11176 +*      cfg->wan_ipaddr, cfg->wan_gateway, cfg->wan_netmask
11177 +*
11178 +*----------------------------------------------------------------------*/
11179 +NAT_CFG_T              nat_cfg;
11180 +static int             nat_initialized;
11181 +u32                    nat_collision;
11182 +
11183 +#ifdef CONFIG_SL351x_NAT_TCP_UDP
11184 +static u16             fixed_tcp_port_list[]={NAT_FTP_CTRL_PORT,
11185 +                                                                               NAT_H323_PORT,
11186 +                                                                               // NAT_T120_PORT,
11187 +                                                                               NAT_PPTP_PORT,
11188 +                                                                               0};
11189 +static u16             fixed_udp_port_list[]={NAT_DNS_PORT,
11190 +                                                                               NAT_NTP_PORT,
11191 +                                                                               NAT_TFTP_PORT,
11192 +                                                                               NAT_RAS_PORT,
11193 +                                                                               NAT_BOOTP67_PORT,
11194 +                                                                               NAT_BOOTP68_PORT,
11195 +                                                                               0};
11196 +#endif
11197 +
11198 +// #define _HAVE_DYNAMIC_PORT_LIST
11199 +#ifdef _HAVE_DYNAMIC_PORT_LIST
11200 +static u16             dynamic_tcp_port_list[NAT_TCP_PORT_MAX+1];
11201 +static u16             dynamic_udp_port_list[NAT_UDP_PORT_MAX+1]};
11202 +#endif
11203 +
11204 +/*----------------------------------------------------------------------
11205 +* Functions
11206 +*----------------------------------------------------------------------*/
11207 +int sl351x_nat_tcp_udp_output(struct sk_buff *skb, int port);
11208 +int sl351x_nat_udp_output(struct sk_buff *skb, int port);
11209 +int sl351x_nat_gre_output(struct sk_buff *skb, int port);
11210 +
11211 +extern int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2);
11212 +extern void hash_dump_entry(int index);
11213 +extern void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
11214 +extern void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
11215 +
11216 +#ifdef SL351x_NAT_TEST_BY_SMARTBITS
11217 +static void nat_init_test_entry(void);
11218 +#endif
11219 +/*----------------------------------------------------------------------
11220 +* sl351x_nat_init
11221 +*      initialize a NAT matching rule
11222 +*      Called by SL351x Driver
11223 +*              key             : port, protocol, Sip, Dip, Sport, Dport
11224 +*              Action  : Srce Q: HW Free Queue,
11225 +*                                Dest Q: HW TxQ
11226 +*                                Change DA
11227 +*                                Change SA
11228 +*                 Change Sip or Dip
11229 +*                        Change Sport or Dport
11230 +*----------------------------------------------------------------------*/
11231 +void sl351x_nat_init(void)
11232 +{
11233 +       int                                     rc;
11234 +       GMAC_MRxCR0_T           mrxcr0;
11235 +       GMAC_MRxCR1_T           mrxcr1;
11236 +       GMAC_MRxCR2_T           mrxcr2;
11237 +       NAT_CFG_T                       *cfg;
11238 +
11239 +       if (nat_initialized)
11240 +               return;
11241 +
11242 +       nat_initialized = 1;
11243 +
11244 +       if ((sizeof(NAT_HASH_ENTRY_T) > HASH_MAX_BYTES) ||
11245 +               (sizeof(GRE_HASH_ENTRY_T) > HASH_MAX_BYTES))
11246 +       {
11247 +               nat_printf("NAT_HASH_ENTRY_T structure Size is too larger!\n");
11248 +               while(1);
11249 +       }
11250 +
11251 +       cfg = (NAT_CFG_T *)&nat_cfg;
11252 +       memset((void *)cfg, 0, sizeof(NAT_CFG_T));
11253 +#ifdef _HAVE_DYNAMIC_PORT_LIST
11254 +       memset((void *)dynamic_tcp_port_list, 0, sizeof(dynamic_tcp_port_list));
11255 +       memset((void *)dynamic_udp_port_list, 0, sizeof(dynamic_udp_port_list));
11256 +#endif
11257 +
11258 +#ifdef VITESSE_G5SWITCH
11259 +       if(Giga_switch)
11260 +       {
11261 +               cfg->enabled                    = 1;
11262 +               cfg->tcp_udp_rule_id    = CONFIG_SL351x_TCP_UDP_RULE_ID;
11263 +               cfg->gre_rule_id                = CONFIG_SL351x_GRE_RULE_ID;
11264 +               cfg->lan_port                   = 1;
11265 +               cfg->wan_port                   = 0;
11266 +               cfg->default_hw_txq     = 3;
11267 +               cfg->tcp_tmo_interval   = 60;
11268 +               cfg->udp_tmo_interval   = 180;
11269 +               cfg->gre_tmo_interval   = 60;
11270 +       }
11271 +       else
11272 +       {
11273 +               cfg->enabled                    = 1;
11274 +               cfg->tcp_udp_rule_id    = CONFIG_SL351x_TCP_UDP_RULE_ID;
11275 +               cfg->gre_rule_id                = CONFIG_SL351x_GRE_RULE_ID;
11276 +               cfg->lan_port                   = 0;
11277 +               cfg->wan_port                   = 1;
11278 +               cfg->default_hw_txq     = 3;
11279 +               cfg->tcp_tmo_interval   = 60;
11280 +               cfg->udp_tmo_interval   = 180;
11281 +               cfg->gre_tmo_interval   = 60;
11282 +
11283 +       }
11284 +#endif
11285 +
11286 +#if 1  //      debug purpose
11287 +       cfg->ipcfg[0].total                             = 1;
11288 +       cfg->ipcfg[0].entry[0].ipaddr   = IPIV(192,168,2,92);
11289 +       cfg->ipcfg[0].entry[0].netmask  = IPIV(255,255,255,0);
11290 +       cfg->ipcfg[1].total                             = 1;
11291 +       cfg->ipcfg[1].entry[0].ipaddr   = IPIV(192,168,1,200);
11292 +       cfg->ipcfg[1].entry[0].netmask  = IPIV(255,255,255,0);
11293 +#endif
11294 +
11295 +#if 1
11296 +       cfg->xport.total = 0;
11297 +#else
11298 +       cfg->xport.total = 4;
11299 +
11300 +       // H.323/H.225 Call setup
11301 +       cfg->xport.entry[0].protocol = IPPROTO_TCP;
11302 +       cfg->xport.entry[0].sport_start = 0;
11303 +       cfg->xport.entry[0].sport_end = 0;
11304 +       cfg->xport.entry[0].dport_start = 1720;
11305 +       cfg->xport.entry[0].dport_end = 1720;
11306 +       cfg->xport.entry[1].protocol = IPPROTO_TCP;
11307 +       cfg->xport.entry[1].sport_start = 1720;
11308 +       cfg->xport.entry[1].sport_end = 1720;
11309 +       cfg->xport.entry[1].dport_start = 0;
11310 +       cfg->xport.entry[1].dport_end = 0;
11311 +
11312 +       // RAS Setup
11313 +       cfg->xport.entry[2].protocol = IPPROTO_UDP;
11314 +       cfg->xport.entry[2].sport_start = 0;
11315 +       cfg->xport.entry[2].sport_end = 0;
11316 +       cfg->xport.entry[2].dport_start = 1719;
11317 +       cfg->xport.entry[2].dport_end = 1719;
11318 +       cfg->xport.entry[3].protocol = IPPROTO_UDP;
11319 +       cfg->xport.entry[3].sport_start = 1719;
11320 +       cfg->xport.entry[3].sport_end = 1719;
11321 +       cfg->xport.entry[3].dport_start = 0;
11322 +       cfg->xport.entry[3].dport_end = 0;
11323 +#endif
11324 +
11325 +#ifdef CONFIG_SL351x_NAT_TCP_UDP
11326 +       mrxcr0.bits32 = 0;
11327 +       mrxcr1.bits32 = 0;
11328 +       mrxcr2.bits32 = 0;
11329 +       mrxcr0.bits.port = 1;
11330 +       mrxcr0.bits.l3 = 1;
11331 +       mrxcr0.bits.l4 = 1;
11332 +       mrxcr1.bits.sip = 1;
11333 +       mrxcr1.bits.dip = 1;
11334 +       mrxcr1.bits.l4_byte0_15 = 0x0f; // Byte 0-3
11335 +       mrxcr0.bits.sprx = 3;
11336 +
11337 +       rc = mac_set_rule_reg(cfg->lan_port, cfg->tcp_udp_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
11338 +       if (rc < 0)
11339 +       {
11340 +               nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->lan_port, cfg->tcp_udp_rule_id);
11341 +       }
11342 +
11343 +       if (cfg->lan_port != cfg->wan_port)
11344 +       {
11345 +               rc = mac_set_rule_reg(cfg->wan_port, cfg->tcp_udp_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
11346 +               if (rc < 0)
11347 +               {
11348 +                       nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->wan_port, cfg->tcp_udp_rule_id);
11349 +               }
11350 +       }
11351 +#endif
11352 +
11353 +#ifdef CONFIG_SL351x_NAT_GRE
11354 +       mrxcr0.bits32 = 0;
11355 +       mrxcr1.bits32 = 0;
11356 +       mrxcr2.bits32 = 0;
11357 +       mrxcr0.bits.port = 1;
11358 +       mrxcr0.bits.l3 = 1;
11359 +       mrxcr0.bits.l4 = 1;
11360 +       mrxcr1.bits.sip = 1;
11361 +       mrxcr1.bits.dip = 1;
11362 +       mrxcr1.bits.l4_byte0_15 = 0xcc; // Byte 2, 3, 6, 7
11363 +       mrxcr0.bits.sprx = 4;                   // see GMAC driver about SPR
11364 +
11365 +       rc = mac_set_rule_reg(cfg->lan_port, cfg->gre_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
11366 +       if (rc < 0)
11367 +       {
11368 +               nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->lan_port, cfg->gre_rule_id);
11369 +       }
11370 +
11371 +       if (cfg->lan_port != cfg->wan_port)
11372 +       {
11373 +               rc = mac_set_rule_reg(cfg->wan_port, cfg->gre_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
11374 +               if (rc < 0)
11375 +               {
11376 +                       nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->wan_port, cfg->gre_rule_id);
11377 +               }
11378 +       }
11379 +#endif
11380 +
11381 +#ifdef SL351x_NAT_TEST_BY_SMARTBITS
11382 +       nat_init_test_entry();
11383 +#endif
11384 +}
11385 +
11386 +/*----------------------------------------------------------------------
11387 +* nat_build_keys
11388 +*      Note: To call this routine, the key->rule_id MUST be zero
11389 +*----------------------------------------------------------------------*/
11390 +static inline int nat_build_keys(NAT_KEY_T *key)
11391 +{
11392 +       return hash_gen_crc16((unsigned char *)key, NAT_KEY_SIZE) & HASH_BITS_MASK;
11393 +}
11394 +
11395 +/*----------------------------------------------------------------------
11396 +* gre_build_keys
11397 +*      Note: To call this routine, the key->rule_id MUST be zero
11398 +*----------------------------------------------------------------------*/
11399 +static inline int gre_build_keys(GRE_KEY_T *key)
11400 +{
11401 +       return hash_gen_crc16((unsigned char *)key, GRE_KEY_SIZE) & HASH_BITS_MASK;
11402 +}
11403 +
11404 +/*----------------------------------------------------------------------
11405 +* nat_write_hash_entry
11406 +*----------------------------------------------------------------------*/
11407 +static inline int nat_write_hash_entry(int index, void *hash_entry)
11408 +{
11409 +       int             i;
11410 +       u32             *srcep, *destp, *destp2;
11411 +
11412 +       srcep = (u32 *)hash_entry;
11413 +       destp = destp2 = (u32 *)&hash_tables[index][0];
11414 +
11415 +       for (i=0; i<(NAT_HASH_ENTRY_SIZE/sizeof(u32)); i++)
11416 +               *destp++ = *srcep++;
11417 +
11418 +       consistent_sync(destp2, NAT_HASH_ENTRY_SIZE, PCI_DMA_TODEVICE);
11419 +       return 0;
11420 +}
11421 +
11422 +/*----------------------------------------------------------------------
11423 +* gre_write_hash_entry
11424 +*----------------------------------------------------------------------*/
11425 +static inline int gre_write_hash_entry(int index, void *hash_entry)
11426 +{
11427 +       int             i;
11428 +       u32             *srcep, *destp, *destp2;
11429 +
11430 +       srcep = (u32 *)hash_entry;
11431 +       destp = destp2 = (u32 *)&hash_tables[index][0];
11432 +
11433 +       for (i=0; i<(GRE_HASH_ENTRY_SIZE/sizeof(u32)); i++)
11434 +               *destp++ = *srcep++;
11435 +
11436 +       consistent_sync(destp2, GRE_HASH_ENTRY_SIZE, PCI_DMA_TODEVICE);
11437 +       return 0;
11438 +}
11439 +
11440 +/*----------------------------------------------------------------------
11441 +* sl351x_nat_find_ipcfg
11442 +*      return NULL if not found
11443 +*----------------------------------------------------------------------*/
11444 +static NAT_IP_ENTRY_T *sl351x_nat_find_ipcfg(u32 ipaddr, int port)
11445 +{
11446 +       int                             i;
11447 +       NAT_IP_ENTRY_T  *ipcfg;
11448 +
11449 +       ipcfg = (NAT_IP_ENTRY_T *)&nat_cfg.ipcfg[port].entry[0];
11450 +       for (i=0; i<nat_cfg.ipcfg[port].total; i++, ipcfg++)
11451 +       {
11452 +               if (ipaddr == ipcfg->ipaddr)
11453 +               {
11454 +                       return ipcfg;
11455 +               }
11456 +       }
11457 +       return NULL;
11458 +}
11459 +
11460 +/*----------------------------------------------------------------------
11461 +* sl351x_nat_assign_qid
11462 +*----------------------------------------------------------------------*/
11463 +static int sl351x_nat_assign_qid(u8 proto, u32 sip, u32 dip, u16 sport, u16 dport)
11464 +{
11465 +       int                             i, total, qid;
11466 +       NAT_WRULE_ENTRY_T       *entry;
11467 +
11468 +       for (qid = 0; qid<CONFIG_NAT_TXQ_NUM; qid++)
11469 +       {
11470 +               if (qid == nat_cfg.default_hw_txq)
11471 +                       continue;
11472 +
11473 +               entry = (NAT_WRULE_ENTRY_T *)&nat_cfg.wrule[qid].entry[0];
11474 +               total = nat_cfg.wrule[qid].total;
11475 +               for (i=0; i<total; i++, entry++)
11476 +               {
11477 +                       if (!entry->protocol || entry->protocol==proto)
11478 +                       {
11479 +                               //if (!entry->sip_start && !entry->dip_start && !entry->sport_start && !entry->dport_start)
11480 +                               //      continue; // UI take care
11481 +                               if (entry->sip_start && !((sip >= entry->sip_start) &&
11482 +                                                                          (sip <= entry->sip_end)))
11483 +                                       continue;
11484 +                               if (entry->dip_start && !((dip >= entry->dip_start) &&
11485 +                                                                          (dip <= entry->dip_end)))
11486 +                                       continue;
11487 +                               if (entry->sport_start && !((sport >= entry->sport_start) &&
11488 +                                                                          (sport <= entry->sport_end)))
11489 +                                       continue;
11490 +                               if (entry->dport_start && !((dport >= entry->dport_start)
11491 +                                                                      && (dport <= entry->dport_end)))
11492 +                                       continue;
11493 +                               return qid;
11494 +                       }
11495 +               }
11496 +       }
11497 +       return nat_cfg.default_hw_txq;
11498 +}
11499 +
11500 +/*----------------------------------------------------------------------
11501 +* sl351x_nat_input
11502 +*      Handle NAT input frames
11503 +*      Called by SL351x Driver - Handle Default Rx Queue
11504 +*      Notes: The caller must make sure that the l3off & l4offset should not be zero.
11505 +*      SL351x NAT Frames should meet the following conditions:
11506 +*      1. TCP or UDP frame
11507 +*      2. Cannot be special ALGs ports which TCP/UDP data is updated
11508 +*      3. LAN-IN Frames:
11509 +*              Source IP is in the LAN subnet and Destination is not in the LAN subnet
11510 +*      4. WAN-IN Frames
11511 +*              Destination IP is in the WAN port IP
11512 +*
11513 +*      Example Ports
11514 +*      1. TCP/UDP data is updated
11515 +*              (a) FTP Control Packet
11516 +*              (b) VoIP Packets
11517 +*              (c) etc. (add in future)
11518 +*      2. UDP Low packet rate, not worth
11519 +*              (b) TFTP Destination Port is 69
11520 +*              (b) DNS  53
11521 +*              (c) NTP  123
11522 +*              (d) etc. (add in future)
11523 +*----------------------------------------------------------------------*/
11524 +void sl351x_nat_input(struct sk_buff *skb, int port, void *l3off, void *l4off)
11525 +{
11526 +       int                             i, found;
11527 +       u32                                     sip, dip;
11528 +       u16                                     sport, dport;
11529 +       struct ethhdr           *ether_hdr;
11530 +       struct iphdr            *ip_hdr;
11531 +       struct tcphdr           *tcp_hdr;
11532 +       struct pppoe_hdr        *pppoe_hdr;
11533 +       NAT_CB_T                        *nat_cb;
11534 +       u8                                      proto, pppoe_frame=0;
11535 +       NAT_CFG_T                       *cfg;
11536 +       u16                                     ppp_proto;
11537 +       NAT_IP_ENTRY_T          *ipcfg;
11538 +       NAT_XPORT_ENTRY_T       *xentry;
11539 +       GRE_PKTHDR_T            *gre_hdr;
11540 +#ifdef CONFIG_SL351x_NAT_TCP_UDP
11541 +       u16                             *port_ptr;
11542 +#endif
11543 +
11544 +       cfg = (NAT_CFG_T *)&nat_cfg;
11545 +       if (!cfg->enabled || !cfg->ipcfg[port].total)
11546 +               return;
11547 +
11548 +       ip_hdr = (struct iphdr *)&(skb->data[(u32)l3off]);
11549 +       proto = ip_hdr->protocol;
11550 +
11551 +       tcp_hdr = (struct tcphdr *)&(skb->data[(u32)l4off]);
11552 +       gre_hdr = (GRE_PKTHDR_T *)tcp_hdr;
11553 +       sport = ntohs(tcp_hdr->source);
11554 +       dport = ntohs(tcp_hdr->dest);
11555 +
11556 +       sip = ntohl(ip_hdr->saddr);
11557 +       dip = ntohl(ip_hdr->daddr);
11558 +
11559 +       if (dip == IPIV(255,255,255,255))
11560 +               return;
11561 +
11562 +       if (port == cfg->lan_port)
11563 +       {
11564 +               ipcfg = (NAT_IP_ENTRY_T *)&cfg->ipcfg[port].entry[0];
11565 +               for (i=0, found=0; i<cfg->ipcfg[port].total; i++, ipcfg++)
11566 +               {
11567 +                       u32 subnet = ipcfg->ipaddr & ipcfg->netmask;
11568 +                       if (((sip & ipcfg->netmask) == subnet) &&
11569 +                               ((dip & ipcfg->netmask) != subnet))
11570 +                       {
11571 +                               found = 1;
11572 +                               break;
11573 +                       }
11574 +               }
11575 +               if (!found)
11576 +                       return;
11577 +       }
11578 +       else
11579 +       {
11580 +#ifndef _NOT_CHECK_SIP_DIP     // enable it if know and get the wan ip address
11581 +               if (!sl351x_nat_find_ipcfg(dip, port))
11582 +               {
11583 +                       printk("WAN->LAN Incorrect Dip %d.%d.%d.%d\n", HIPQUAD(dip));
11584 +                       return;
11585 +               }
11586 +#endif
11587 +               ether_hdr = (struct ethhdr *)skb->data;
11588 +               pppoe_hdr = (struct pppoe_hdr *)(ether_hdr + 1);
11589 +               ppp_proto = *(u16 *)&pppoe_hdr->tag[0];
11590 +               if (ether_hdr->h_proto == __constant_htons(ETH_P_PPP_SES)       // 0x8864
11591 +                       && ppp_proto == __constant_htons(PPP_IP) )                              // 0x21
11592 +               {
11593 +                       pppoe_frame = 1;
11594 +               }
11595 +       }
11596 +
11597 +#ifdef CONFIG_SL351x_NAT_TCP_UDP
11598 +       if (proto == IPPROTO_TCP)
11599 +       {
11600 +#ifdef NAT_DEBUG_MSG
11601 +               nat_printf("From   GMAC-%d: 0x%-4X TCP %d.%d.%d.%d [%d] --> %d.%d.%d.%d [%d]",
11602 +                               port, ntohs(ip_hdr->id),
11603 +                               NIPQUAD(ip_hdr->saddr), sport,
11604 +                               NIPQUAD(ip_hdr->daddr), dport);
11605 +               if (tcp_flag_word(tcp_hdr) & TCP_FLAG_SYN) nat_printf(" SYN");
11606 +               if (tcp_flag_word(tcp_hdr) & TCP_FLAG_FIN) nat_printf(" FIN");
11607 +               if (tcp_flag_word(tcp_hdr) & TCP_FLAG_RST) nat_printf(" RST");
11608 +               if (tcp_flag_word(tcp_hdr) & TCP_FLAG_ACK) nat_printf(" ACK");
11609 +               nat_printf("\n");
11610 +#endif
11611 +               // if (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN | TCP_FLAG_FIN | TCP_FLAG_RST))
11612 +               if (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN))
11613 +               {
11614 +                       return;
11615 +               }
11616 +               port_ptr = fixed_tcp_port_list;
11617 +               for (i=0; *port_ptr; i++, port_ptr++)
11618 +               {
11619 +                       if (sport == *port_ptr || dport == *port_ptr)
11620 +                               return;
11621 +               }
11622 +#ifdef _HAVE_DYNAMIC_PORT_LIST
11623 +               port_ptr = dynamic_tcp_port_list;
11624 +               for (i=0; *port_ptr; i++, port_ptr++)
11625 +               {
11626 +                       if (sport == *port_ptr || dport == *port_ptr)
11627 +                               return;
11628 +               }
11629 +#endif
11630 +       }
11631 +       else if (proto == IPPROTO_UDP)
11632 +       {
11633 +#ifdef NAT_DEBUG_MSG
11634 +               nat_printf("From   GMAC-%d: 0x%-4X UDP %d.%d.%d.%d [%d] --> %d.%d.%d.%d [%d]",
11635 +                               port, ntohs(ip_hdr->id),
11636 +                               NIPQUAD(ip_hdr->saddr), sport,
11637 +                               NIPQUAD(ip_hdr->daddr), dport);
11638 +               nat_printf("\n");
11639 +#endif
11640 +               port_ptr = fixed_udp_port_list;
11641 +               for (i=0; *port_ptr; i++, port_ptr++)
11642 +               {
11643 +                       if (sport == *port_ptr || dport == *port_ptr)
11644 +                               return;
11645 +               }
11646 +#ifdef _HAVE_DYNAMIC_PORT_LIST
11647 +               port_ptr = dynamic_udp_port_list;
11648 +               for (i=0; *port_ptr; i++, port_ptr++)
11649 +               {
11650 +                       if (sport == *port_ptr || dport == *port_ptr)
11651 +                               return;
11652 +               }
11653 +#endif
11654 +       }
11655 +       else
11656 +#endif // CONFIG_SL351x_NAT_TCP_UDP
11657 +#ifdef CONFIG_SL351x_NAT_GRE
11658 +       if (proto == IPPROTO_GRE)
11659 +       {
11660 +               if (gre_hdr->protocol != GRE_PROTOCOL_SWAP)
11661 +                       return;
11662 +#ifdef NAT_DEBUG_MSG
11663 +               nat_printf("From   GMAC-%d: 0x%-4X GRE %d.%d.%d.%d [%d] --> %d.%d.%d.%d",
11664 +                               port, ntohs(ip_hdr->id),
11665 +                               NIPQUAD(ip_hdr->saddr), ntohs(gre_hdr->call_id),
11666 +                               NIPQUAD(ip_hdr->daddr));
11667 +               nat_printf("\n");
11668 +#endif
11669 +       }
11670 +       else
11671 +#endif
11672 +               return;
11673 +
11674 +
11675 +       // check xport list
11676 +       xentry = (NAT_XPORT_ENTRY_T *)&cfg->xport.entry[0];
11677 +       for (i=0; i<cfg->xport.total; i++, xentry++)
11678 +       {
11679 +               if (!xentry->protocol || xentry->protocol == proto)
11680 +               {
11681 +                       //if (!xentry->sport_start && !xentry->dport_start) // UI take care
11682 +                       //      continue;
11683 +                       if (xentry->sport_start && !((sport >= xentry->sport_start) &&
11684 +                                                                          (sport <= xentry->sport_end)))
11685 +                               continue;
11686 +                       if (xentry->dport_start && !((dport >= xentry->dport_start)
11687 +                                                                      && (dport <= xentry->dport_end)))
11688 +                               continue;
11689 +                       return;
11690 +               }
11691 +       }
11692 +
11693 +       nat_cb = NAT_SKB_CB(skb);
11694 +       if (((u32)nat_cb & 3))
11695 +       {
11696 +               nat_printf("%s ERROR! nat_cb is not alignment!!!!!!\n", __func__);
11697 +               return;
11698 +       }
11699 +       nat_cb->tag = NAT_CB_TAG;
11700 +       memcpy(nat_cb->sa, skb->data+6, 6);
11701 +       nat_cb->sip = ip_hdr->saddr;
11702 +       nat_cb->dip = ip_hdr->daddr;
11703 +       if (proto == IPPROTO_GRE)
11704 +       {
11705 +               nat_cb->sport = gre_hdr->protocol;
11706 +               nat_cb->dport = gre_hdr->call_id;
11707 +       }
11708 +       else
11709 +       {
11710 +               nat_cb->sport = tcp_hdr->source;
11711 +               nat_cb->dport = tcp_hdr->dest;
11712 +       }
11713 +       nat_cb->pppoe_frame = pppoe_frame;
11714 +}
11715 +
11716 +/*----------------------------------------------------------------------
11717 +* sl351x_nat_output
11718 +*      Handle NAT output frames
11719 +*      Called by SL351x Driver - Transmit
11720 +*
11721 +*      1. If not SL351x NAT frames, return FALSE
11722 +*      2. LAN-to-WAN frames
11723 +*              (1) Sip must be WAN IP
11724 +*      3. If TCP SY/RST/FIN frame, return
11725 +*      4. Build the hash key and get the hash index
11726 +*      5. If V-Bit is ON, return.
11727 +*      6. Write hash entry and validate it
11728 +*
11729 +*----------------------------------------------------------------------*/
11730 +int sl351x_nat_output(struct sk_buff *skb, int port)
11731 +{
11732 +       struct iphdr            *ip_hdr;
11733 +       u8                                      proto;
11734 +       NAT_CB_T                        *nat_cb;
11735 +
11736 +       nat_cb = NAT_SKB_CB(skb);
11737 +       if (nat_cb->tag != NAT_CB_TAG)
11738 +               return 0;
11739 +
11740 +       if (((u32)nat_cb & 3))
11741 +       {
11742 +               nat_printf("%s ERROR! nat_cb is not alignment!!!!!!\n", __func__);
11743 +               return 0;
11744 +       }
11745 +       ip_hdr = (struct iphdr *)skb->h.ipiph;
11746 +       proto = ip_hdr->protocol;
11747 +
11748 +       switch (proto)
11749 +       {
11750 +               case IPPROTO_TCP:
11751 +               case IPPROTO_UDP:
11752 +                       return sl351x_nat_tcp_udp_output(skb, port);
11753 +               case IPPROTO_GRE:
11754 +                       return sl351x_nat_gre_output(skb, port);
11755 +       }
11756 +       return 0;
11757 +}
11758 +
11759 +/*----------------------------------------------------------------------
11760 +* sl351x_nat_tcp_udp_output
11761 +*      Handle NAT TCP/UDP output frames
11762 +*----------------------------------------------------------------------*/
11763 +int sl351x_nat_tcp_udp_output(struct sk_buff *skb, int port)
11764 +{
11765 +       u32                                     sip, dip;
11766 +       struct ethhdr           *ether_hdr;
11767 +       struct iphdr            *ip_hdr;
11768 +       struct tcphdr           *tcp_hdr;
11769 +       struct pppoe_hdr        *pppoe_hdr;
11770 +       NAT_CB_T                        *nat_cb;
11771 +       NAT_CFG_T                       *cfg;
11772 +       u8                                      proto;
11773 +       u16                                     sport, dport, ppp_proto;
11774 +       u32                                     hash_data[HASH_MAX_DWORDS];
11775 +       NAT_HASH_ENTRY_T        *hash_entry;
11776 +       int                                     hash_index;
11777 +       struct ip_conntrack *nat_ip_conntrack;
11778 +       enum ip_conntrack_info ctinfo;
11779 +
11780 +       nat_cb = NAT_SKB_CB(skb);
11781 +       cfg = (NAT_CFG_T *)&nat_cfg;
11782 +
11783 +       ether_hdr = (struct ethhdr *)skb->data;
11784 +       ip_hdr = (struct iphdr *)skb->h.ipiph;
11785 +       tcp_hdr = (struct tcphdr *)((u32)ip_hdr + (ip_hdr->ihl<<2));
11786 +       sip = ntohl(ip_hdr->saddr);
11787 +       dip = ntohl(ip_hdr->daddr);
11788 +       proto = ip_hdr->protocol;
11789 +       sport = ntohs(tcp_hdr->source);
11790 +       dport = ntohs(tcp_hdr->dest);
11791 +
11792 +#ifdef NAT_DEBUG_MSG
11793 +       {
11794 +               nat_printf("To   GMAC-%d: 0x%-4X [%d] %d.%d.%d.%d [%d] --> %d.%d.%d.%d [%d]",
11795 +                               port, ntohs(ip_hdr->id), proto,
11796 +                               NIPQUAD(ip_hdr->saddr), sport,
11797 +                               NIPQUAD(ip_hdr->daddr), dport);
11798 +               if (proto == IPPROTO_TCP)
11799 +               {
11800 +                       if (tcp_flag_word(tcp_hdr) & TCP_FLAG_SYN) nat_printf(" SYN");
11801 +                       if (tcp_flag_word(tcp_hdr) & TCP_FLAG_FIN) nat_printf(" FIN");
11802 +                       if (tcp_flag_word(tcp_hdr) & TCP_FLAG_RST) nat_printf(" RST");
11803 +                       if (tcp_flag_word(tcp_hdr) & TCP_FLAG_ACK) nat_printf(" ACK");
11804 +               }
11805 +               nat_printf("\n");
11806 +       }
11807 +#endif
11808 +       nat_ip_conntrack = ip_conntrack_get(skb, &ctinfo);
11809 +       if (!nat_ip_conntrack)
11810 +       {
11811 +               nat_printf("IP conntrack info is not found!\n");
11812 +               return 0;
11813 +       }
11814 +       // nat_printf("nat_ip_conntrack = 0x%x, status=0x%lx, ctinfo=%d\n", (u32)nat_ip_conntrack, nat_ip_conntrack->status, ctinfo);
11815 +       // if (nat_ip_conntrack->master || nat_ip_conntrack->helper)
11816 +       if (nat_ip_conntrack->helper)
11817 +       {
11818 +               nat_printf("Sport=%d Dport=%d master=0x%x, helper=0x%x\n", sport, dport, (u32)nat_ip_conntrack->master, (u32)nat_ip_conntrack->helper);
11819 +               return 0;
11820 +       }
11821 +
11822 +       //if (proto == IPPROTO_TCP && !(nat_ip_conntrack->status & IPS_ASSURED))
11823 +       //      return 0;
11824 +
11825 +#ifdef NAT_DEBUG_MSG
11826 +       nat_printf("nat_ip_conntrack=0x%x, nat_cb->state=%d\n", (u32)nat_ip_conntrack, nat_cb->state);
11827 +       nat_printf("lan2wan_hash_index=%d,  wan2lan_hash_index=%d\n", nat_ip_conntrack->lan2wan_hash_index, nat_ip_conntrack->wan2lan_hash_index);
11828 +       nat_printf("lan2wan_collision=%d, wan2lan_collision=%d\n", nat_ip_conntrack->lan2wan_collision, nat_ip_conntrack->wan2lan_collision);
11829 +#endif
11830 +       if (proto == IPPROTO_TCP)
11831 +       {
11832 +               if (nat_cb->state >= TCP_CONNTRACK_FIN_WAIT && nat_cb->state <= TCP_CONNTRACK_CLOSE)
11833 +               {
11834 +                       if      (nat_ip_conntrack->lan2wan_hash_index)
11835 +                       {
11836 +#ifdef NAT_DEBUG_MSG
11837 +                               nat_printf("Invalidate LAN->WAN hash entry %d\n", nat_ip_conntrack->lan2wan_hash_index - 1);
11838 +#endif
11839 +                               hash_nat_disable_owner(nat_ip_conntrack->lan2wan_hash_index - 1);
11840 +                               hash_invalidate_entry(nat_ip_conntrack->lan2wan_hash_index - 1);
11841 +                               nat_ip_conntrack->lan2wan_hash_index = 0;
11842 +                       }
11843 +                       if      (nat_ip_conntrack->wan2lan_hash_index)
11844 +                       {
11845 +#ifdef NAT_DEBUG_MSG
11846 +                               nat_printf("Invalidate WAN->LAN hash entry %d\n", nat_ip_conntrack->wan2lan_hash_index - 1);
11847 +#endif
11848 +                               hash_nat_disable_owner(nat_ip_conntrack->wan2lan_hash_index - 1);
11849 +                               hash_invalidate_entry(nat_ip_conntrack->wan2lan_hash_index - 1);
11850 +                               nat_ip_conntrack->wan2lan_hash_index = 0;
11851 +                       }
11852 +                       return 0;
11853 +
11854 +               }
11855 +               else if (nat_cb->state != TCP_CONNTRACK_ESTABLISHED)
11856 +               {
11857 +                       return 0;
11858 +               }
11859 +       }
11860 +       if (proto == IPPROTO_TCP && (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN | TCP_FLAG_FIN | TCP_FLAG_RST)))
11861 +       // if (proto == IPPROTO_TCP &&  (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN)))
11862 +               return 0;
11863 +
11864 +       hash_entry = (NAT_HASH_ENTRY_T *)&hash_data;
11865 +       if (port == cfg->wan_port)      // LAN-to-WAN
11866 +       {
11867 +               if (nat_ip_conntrack->lan2wan_hash_index || nat_ip_conntrack->lan2wan_collision)
11868 +                       return 0;
11869 +#ifndef _NOT_CHECK_SIP_DIP     // enable it if know and get the wan ip address
11870 +               if (!sl351x_nat_find_ipcfg(sip, port))
11871 +               {
11872 +                       printk("LAN->WAN Incorrect Sip %d.%d.%d.%d\n", HIPQUAD(sip));
11873 +                       return 0;
11874 +               }
11875 +#endif
11876 +               // Note: unused fields (including rule_id) MUST be zero
11877 +               hash_entry->key.Ethertype       = 0;
11878 +               hash_entry->key.port_id         = cfg->lan_port;
11879 +               hash_entry->key.rule_id         = 0;
11880 +               hash_entry->key.ip_protocol = proto;
11881 +               hash_entry->key.reserved1       = 0;
11882 +               hash_entry->key.reserved2       = 0;
11883 +               hash_entry->key.sip             = ntohl(nat_cb->sip);
11884 +               hash_entry->key.dip             = ntohl(nat_cb->dip);
11885 +               hash_entry->key.sport           = nat_cb->sport;
11886 +               hash_entry->key.dport           = nat_cb->dport;
11887 +
11888 +               hash_index = nat_build_keys(&hash_entry->key);
11889 +
11890 +#ifdef NAT_DEBUG_LAN_HASH_TIMEOUT
11891 +               if (hash_get_nat_owner_flag(hash_index))
11892 +                       return 0;
11893 +#endif
11894 +               if (hash_get_valid_flag(hash_index))
11895 +               {
11896 +                       nat_ip_conntrack->lan2wan_collision = 1;
11897 +                       nat_collision++;
11898 +#if 0
11899 +                       if (proto == IPPROTO_TCP && (tcp_flag_word(tcp_hdr) & (TCP_FLAG_FIN | TCP_FLAG_RST)))
11900 +                       {
11901 +                               if (memcmp((void *)&hash_entry->key, hash_get_entry(hash_index), sizeof(NAT_KEY_T)) == 0)
11902 +                               {
11903 +                                       hash_nat_disable_owner(hash_index);
11904 +                                       hash_invalidate_entry(hash_index); // Must last one, else HW Tx fast SW
11905 +                                       // nat_printf("Invalidate nat hash entry %d\n", hash_index);
11906 +                               }
11907 +                       }
11908 +#endif
11909 +                       return 0;
11910 +               }
11911 +
11912 +               // write hash entry
11913 +               hash_entry->key.rule_id = cfg->tcp_udp_rule_id;
11914 +               memcpy(hash_entry->param.da, skb->data, 6);
11915 +               memcpy(hash_entry->param.sa, skb->data+6, 6);
11916 +               hash_entry->param.Sip = sip;
11917 +               hash_entry->param.Dip = dip;
11918 +               hash_entry->param.Sport = sport;
11919 +               hash_entry->param.Dport = dport;
11920 +               hash_entry->param.vlan = 0;
11921 +               hash_entry->param.sw_id = 0;
11922 +               hash_entry->param.mtu = 0;
11923 +               // check PPPoE
11924 +               pppoe_hdr = (struct pppoe_hdr *)(ether_hdr + 1);
11925 +               ppp_proto = *(u16 *)&pppoe_hdr->tag[0];
11926 +               if (ether_hdr->h_proto == __constant_htons(ETH_P_PPP_SES)       // 0x8864
11927 +                       && ppp_proto == __constant_htons(PPP_IP) )                              // 0x21
11928 +               {
11929 +                       hash_entry->action.dword = NAT_PPPOE_LAN2WAN_ACTIONS;
11930 +                       hash_entry->param.pppoe = htons(pppoe_hdr->sid);
11931 +               }
11932 +               else
11933 +               {
11934 +                       hash_entry->action.dword = NAT_LAN2WAN_ACTIONS;
11935 +                       hash_entry->param.pppoe = 0;
11936 +               }
11937 +               hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(proto, sip, dip, sport, dport);
11938 +               hash_entry->action.bits.dest_qid +=     (cfg->wan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
11939 +               hash_entry->tmo.counter = hash_entry->tmo.interval =
11940 +                                               (proto == IPPROTO_TCP) ? cfg->tcp_tmo_interval : cfg->udp_tmo_interval;
11941 +               nat_write_hash_entry(hash_index, hash_entry);
11942 +               // nat_printf("%lu Validate a LAN hash entry %d\n", jiffies/HZ, hash_index);
11943 +               // hash_dump_entry(hash_index);
11944 +               hash_nat_enable_owner(hash_index);
11945 +               hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
11946 +               nat_ip_conntrack->lan2wan_hash_index = hash_index + 1;
11947 +               nat_ip_conntrack->hw_nat |= 1;
11948 +               return 0;
11949 +       }
11950 +       else // WAN-to-LAN
11951 +       {
11952 +               if (nat_ip_conntrack->wan2lan_hash_index || nat_ip_conntrack->wan2lan_collision)
11953 +                       return 0;
11954 +
11955 +               // Note: unused fields (including rule_id) MUST be zero
11956 +               hash_entry->key.Ethertype       = 0;
11957 +               hash_entry->key.port_id         = cfg->wan_port;
11958 +               hash_entry->key.rule_id         = 0;
11959 +               hash_entry->key.ip_protocol = proto;
11960 +               hash_entry->key.reserved1       = 0;
11961 +               hash_entry->key.reserved2       = 0;
11962 +               hash_entry->key.sip             = ntohl(nat_cb->sip);
11963 +               hash_entry->key.dip             = ntohl(nat_cb->dip);
11964 +               hash_entry->key.sport           = nat_cb->sport;
11965 +               hash_entry->key.dport           = nat_cb->dport;
11966 +
11967 +               hash_index = nat_build_keys(&hash_entry->key);
11968 +
11969 +#ifdef NAT_DEBUG_WAN_HASH_TIMEOUT
11970 +               if (hash_get_nat_owner_flag(hash_index))
11971 +                       return 0;
11972 +#endif
11973 +               if (hash_get_valid_flag(hash_index))
11974 +               {
11975 +                       nat_ip_conntrack->wan2lan_collision = 1;
11976 +                       nat_collision++;
11977 +#if 0
11978 +                       if (proto == IPPROTO_TCP && (tcp_flag_word(tcp_hdr) & (TCP_FLAG_FIN | TCP_FLAG_RST)))
11979 +                       {
11980 +                               if (memcmp((void *)&hash_entry->key, hash_get_entry(hash_index), sizeof(NAT_KEY_T)) == 0)
11981 +                               {
11982 +                                       hash_nat_disable_owner(hash_index);
11983 +                                       hash_invalidate_entry(hash_index); // Must last one, else HW Tx fast SW
11984 +                                       // nat_printf("Invalidate nat hash entry %d\n", hash_index);
11985 +                               }
11986 +                       }
11987 +#endif
11988 +                       return 0;
11989 +               }
11990 +
11991 +               // write hash entry
11992 +               hash_entry->key.rule_id = cfg->tcp_udp_rule_id;
11993 +               memcpy(hash_entry->param.da, skb->data, 6);
11994 +               memcpy(hash_entry->param.sa, skb->data+6, 6);
11995 +               hash_entry->param.Sip = sip;
11996 +               hash_entry->param.Dip = dip;
11997 +               hash_entry->param.Sport = sport;
11998 +               hash_entry->param.Dport = dport;
11999 +               hash_entry->param.vlan = 0;
12000 +               hash_entry->param.pppoe = 0;
12001 +               hash_entry->param.sw_id = 0;
12002 +               hash_entry->param.mtu = 0;
12003 +               hash_entry->action.dword = (nat_cb->pppoe_frame) ? NAT_PPPOE_WAN2LAN_ACTIONS : NAT_WAN2LAN_ACTIONS;
12004 +               hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(proto, sip, dip, sport, dport);
12005 +               hash_entry->action.bits.dest_qid += (cfg->lan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;;
12006 +               hash_entry->tmo.counter = hash_entry->tmo.interval =
12007 +                                               (proto == IPPROTO_TCP) ? cfg->tcp_tmo_interval : cfg->udp_tmo_interval;
12008 +               nat_write_hash_entry(hash_index, hash_entry);
12009 +
12010 +               // nat_printf("%lu Validate a WAN hash entry %d\n", jiffies/HZ, hash_index);
12011 +               // hash_dump_entry(hash_index);
12012 +               hash_nat_enable_owner(hash_index);
12013 +               hash_validate_entry(hash_index); // Must last one, else HW Tx fast SW
12014 +               nat_ip_conntrack->wan2lan_hash_index = hash_index + 1;
12015 +               nat_ip_conntrack->hw_nat |= 2;
12016 +               return 0;
12017 +       }
12018 +       return 0;
12019 +}
12020 +
12021 +/*----------------------------------------------------------------------
12022 +* sl351x_nat_gre_output
12023 +*      Handle NAT GRE output frames
12024 +*----------------------------------------------------------------------*/
12025 +int sl351x_nat_gre_output(struct sk_buff *skb, int port)
12026 +{
12027 +       u32                                     sip, dip;
12028 +       struct ethhdr           *ether_hdr;
12029 +       struct iphdr            *ip_hdr;
12030 +       struct pppoe_hdr        *pppoe_hdr;
12031 +       GRE_PKTHDR_T            *gre_hdr;
12032 +       NAT_CB_T                        *nat_cb;
12033 +       NAT_CFG_T                       *cfg;
12034 +       u16                                     ppp_proto;
12035 +       u32                                     hash_data[HASH_MAX_DWORDS];
12036 +       GRE_HASH_ENTRY_T        *hash_entry;
12037 +       int                                     hash_index;
12038 +       struct ip_conntrack *nat_ip_conntrack;
12039 +       enum ip_conntrack_info ctinfo;
12040 +
12041 +       nat_cb = NAT_SKB_CB(skb);
12042 +       cfg = (NAT_CFG_T *)&nat_cfg;
12043 +
12044 +       ether_hdr = (struct ethhdr *)skb->data;
12045 +       ip_hdr = (struct iphdr *)skb->h.ipiph;
12046 +       gre_hdr = (GRE_PKTHDR_T *)((u32)ip_hdr + (ip_hdr->ihl<<2));
12047 +       sip = ntohl(ip_hdr->saddr);
12048 +       dip = ntohl(ip_hdr->daddr);
12049 +
12050 +#ifdef NAT_DEBUG_MSG
12051 +       {
12052 +               nat_printf("To   GMAC-%d: 0x%-4X GRE %d.%d.%d.%d [%d] --> %d.%d.%d.%d",
12053 +                               port, ntohs(ip_hdr->id),
12054 +                               NIPQUAD(ip_hdr->saddr), ntohs(gre_hdr->call_id),
12055 +                               NIPQUAD(ip_hdr->daddr));
12056 +               nat_printf("\n");
12057 +       }
12058 +#endif
12059 +       nat_ip_conntrack = ip_conntrack_get(skb, &ctinfo);
12060 +       if (nat_ip_conntrack)
12061 +       {
12062 +               // if (nat_ip_conntrack->master || nat_ip_conntrack->helper)
12063 +               if (nat_ip_conntrack->helper)
12064 +               {
12065 +                       nat_printf("GRE Call-ID=%d, master=0x%x, helper=0x%x\n", ntohs(gre_hdr->call_id), (u32)nat_ip_conntrack->master, (u32)nat_ip_conntrack->helper);
12066 +                       return 0;
12067 +               }
12068 +               if (!(nat_ip_conntrack->status & IPS_ASSURED))
12069 +                       return 0;
12070 +       }
12071 +
12072 +       hash_entry = (GRE_HASH_ENTRY_T *)&hash_data;
12073 +       if (port == cfg->wan_port)      // LAN-to-WAN
12074 +       {
12075 +#ifdef _NOT_CHECK_SIP_DIP      // enable it if know and get the wan ip address
12076 +               if (!sl351x_nat_find_ipcfg(sip, port))
12077 +               {
12078 +                       printk("LAN->WAN Incorrect Sip %d.%d.%d.%d\n", HIPQUAD(sip));
12079 +                       return 0;
12080 +               }
12081 +#endif
12082 +               // Note: unused fields (including rule_id) MUST be zero
12083 +               hash_entry->key.Ethertype       = 0;
12084 +               hash_entry->key.port_id         = cfg->lan_port;
12085 +               hash_entry->key.rule_id         = 0;
12086 +               hash_entry->key.ip_protocol = IPPROTO_GRE;
12087 +               hash_entry->key.reserved1       = 0;
12088 +               hash_entry->key.reserved2       = 0;
12089 +               hash_entry->key.reserved3       = 0;
12090 +               hash_entry->key.reserved4       = 0;
12091 +               hash_entry->key.sip             = ntohl(nat_cb->sip);
12092 +               hash_entry->key.dip             = ntohl(nat_cb->dip);
12093 +               hash_entry->key.protocol        = nat_cb->sport;
12094 +               hash_entry->key.call_id         = nat_cb->dport;
12095 +
12096 +               hash_index = gre_build_keys(&hash_entry->key);
12097 +
12098 +#ifdef NAT_DEBUG_LAN_HASH_TIMEOUT
12099 +               if (hash_get_nat_owner_flag(hash_index))
12100 +                       return 0;
12101 +#endif
12102 +               if (hash_get_valid_flag(hash_index))
12103 +               {
12104 +                       return 0;
12105 +               }
12106 +
12107 +               // write hash entry
12108 +               hash_entry->key.rule_id = cfg->gre_rule_id;
12109 +               memcpy(hash_entry->param.da, skb->data, 6);
12110 +               memcpy(hash_entry->param.sa, skb->data+6, 6);
12111 +               hash_entry->param.Sip = sip;
12112 +               hash_entry->param.Dip = dip;
12113 +               hash_entry->param.Sport = 0;
12114 +               hash_entry->param.Dport = ntohs(gre_hdr->call_id);
12115 +               hash_entry->param.vlan = 0;
12116 +               hash_entry->param.sw_id = 0;
12117 +               hash_entry->param.mtu = 0;
12118 +               // check PPPoE
12119 +               pppoe_hdr = (struct pppoe_hdr *)(ether_hdr + 1);
12120 +               ppp_proto = *(u16 *)&pppoe_hdr->tag[0];
12121 +               if (ether_hdr->h_proto == __constant_htons(ETH_P_PPP_SES)       // 0x8864
12122 +                       && ppp_proto == __constant_htons(PPP_IP) )                              // 0x21
12123 +               {
12124 +                       hash_entry->action.dword = NAT_PPPOE_PPTP_LAN2WAN_ACTIONS;
12125 +                       hash_entry->param.pppoe = htons(pppoe_hdr->sid);
12126 +               }
12127 +               else
12128 +               {
12129 +                       hash_entry->action.dword = NAT_PPTP_LAN2WAN_ACTIONS;
12130 +                       hash_entry->param.pppoe = 0;
12131 +               }
12132 +               hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(IPPROTO_GRE, sip, dip, 0, ntohs(gre_hdr->call_id));
12133 +               hash_entry->action.bits.dest_qid +=     (cfg->wan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
12134 +               hash_entry->tmo.counter = hash_entry->tmo.interval = cfg->gre_tmo_interval;
12135 +               gre_write_hash_entry(hash_index, hash_entry);
12136 +               // nat_printf("%lu Validate a LAN hash entry %d\n", jiffies/HZ, hash_index);
12137 +               // hash_dump_entry(hash_index);
12138 +               hash_nat_enable_owner(hash_index);
12139 +               hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
12140 +               return 0;
12141 +       }
12142 +       else // WAN-to-LAN
12143 +       {
12144 +               // Note: unused fields (including rule_id) MUST be zero
12145 +               hash_entry->key.Ethertype       = 0;
12146 +               hash_entry->key.port_id         = cfg->wan_port;
12147 +               hash_entry->key.rule_id         = 0;
12148 +               hash_entry->key.ip_protocol = IPPROTO_GRE;
12149 +               hash_entry->key.reserved1       = 0;
12150 +               hash_entry->key.reserved2       = 0;
12151 +               hash_entry->key.reserved3       = 0;
12152 +               hash_entry->key.reserved4       = 0;
12153 +               hash_entry->key.sip             = ntohl(nat_cb->sip);
12154 +               hash_entry->key.dip             = ntohl(nat_cb->dip);
12155 +               hash_entry->key.protocol        = nat_cb->sport;
12156 +               hash_entry->key.call_id         = nat_cb->dport;
12157 +
12158 +               hash_index = gre_build_keys(&hash_entry->key);
12159 +
12160 +#ifdef NAT_DEBUG_WAN_HASH_TIMEOUT
12161 +               if (hash_get_nat_owner_flag(hash_index))
12162 +                       return 0;
12163 +#endif
12164 +               if (hash_get_valid_flag(hash_index))
12165 +               {
12166 +                       return 0;
12167 +               }
12168 +
12169 +               // write hash entry
12170 +               hash_entry->key.rule_id = cfg->gre_rule_id;
12171 +               memcpy(hash_entry->param.da, skb->data, 6);
12172 +               memcpy(hash_entry->param.sa, skb->data+6, 6);
12173 +               hash_entry->param.Sip = sip;
12174 +               hash_entry->param.Dip = dip;
12175 +               hash_entry->param.Sport = 0;
12176 +               hash_entry->param.Dport = ntohs(gre_hdr->call_id);
12177 +               hash_entry->param.vlan = 0;
12178 +               hash_entry->param.pppoe = 0;
12179 +               hash_entry->param.sw_id = 0;
12180 +               hash_entry->param.mtu = 0;
12181 +               hash_entry->action.dword = (nat_cb->pppoe_frame) ? NAT_PPPOE_PPTP_WAN2LAN_ACTIONS : NAT_PPTP_WAN2LAN_ACTIONS;
12182 +               hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(IPPROTO_GRE, sip, dip, 0, ntohs(gre_hdr->call_id));
12183 +               hash_entry->action.bits.dest_qid += (cfg->lan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;;
12184 +               hash_entry->tmo.counter = hash_entry->tmo.interval = cfg->gre_tmo_interval;
12185 +               gre_write_hash_entry(hash_index, hash_entry);
12186 +
12187 +               // nat_printf("%lu Validate a WAN hash entry %d\n", jiffies/HZ, hash_index);
12188 +               // hash_dump_entry(hash_index);
12189 +               hash_nat_enable_owner(hash_index);
12190 +               hash_validate_entry(hash_index); // Must last one, else HW Tx fast SW
12191 +               return 0;
12192 +       }
12193 +       return 0;
12194 +}
12195 +
12196 +
12197 +#ifdef _HAVE_DYNAMIC_PORT_LIST
12198 +/*----------------------------------------------------------------------
12199 +* sl_nat_add_port
12200 +*----------------------------------------------------------------------*/
12201 +void sl_nat_add_port(u8 protocol, u16 port)
12202 +{
12203 +       int     i;
12204 +       u16             *port_ptr;
12205 +
12206 +       if (protocol == IPPROTO_TCP)
12207 +               port_ptr = dynamic_tcp_port_list;
12208 +       else if (protocol == IPPROTO_UDP)
12209 +               port_ptr = dynamic_udp_port_list;
12210 +       else
12211 +               return;
12212 +
12213 +       for (i=0; *port_ptr; i++)
12214 +       {
12215 +               if (port == *port_ptr)
12216 +                       return;
12217 +               port_ptr++;
12218 +       }
12219 +       port_ptr++;
12220 +       *port_ptr = port;
12221 +}
12222 +
12223 +/*----------------------------------------------------------------------
12224 +* sl_nat_remove_port
12225 +*----------------------------------------------------------------------*/
12226 +void sl_nat_remove_port(u8 protocol, u16 port)
12227 +{
12228 +       int     i, j;
12229 +       u16             *port_ptr, *next;
12230 +
12231 +       if (protocol == IPPROTO_TCP)
12232 +               port_ptr = dynamic_tcp_port_list;
12233 +       else if (protocol == IPPROTO_UDP)
12234 +               port_ptr = dynamic_udp_port_list;
12235 +       else
12236 +               return;
12237 +
12238 +       for (i=0; *port_ptr; i++, port_ptr++)
12239 +       {
12240 +               if (port == *port_ptr)
12241 +               {
12242 +                       port_next = port_ptr + 1;
12243 +                       for (j=i+1; *port_next; i++, j++)
12244 +                               *port_ptr++ = *port_next++;
12245 +                       *port_ptr = 0;
12246 +                       return;
12247 +               }
12248 +       }
12249 +}
12250 +#endif
12251 +
12252 +/*----------------------------------------------------------------------
12253 +* sl351x_nat_ioctl
12254 +*----------------------------------------------------------------------*/
12255 +int sl351x_nat_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
12256 +{
12257 +       GMAC_INFO_T             *tp = (GMAC_INFO_T *)dev->priv;
12258 +       int                             i, j, port_id;
12259 +    NATCMD_HDR_T               nat_hdr;
12260 +    NAT_REQ_E                  ctrl;
12261 +       unsigned char           *req_datap;
12262 +       NAT_IP_ENTRY_T          *ipcfg;
12263 +       NAT_XPORT_ENTRY_T       *xport_entry;
12264 +       NAT_WRULE_ENTRY_T       *wrule_entry;
12265 +       unsigned int            qid;
12266 +
12267 +       if (copy_from_user((void *)&nat_hdr, rq->ifr_data, sizeof(nat_hdr)))
12268 +               return -EFAULT;
12269 +       req_datap = (unsigned char *)rq->ifr_data + sizeof(nat_hdr);
12270 +       port_id = tp->port_id;
12271 +       switch (nat_hdr.cmd) {
12272 +       case NATSSTATUS:
12273 +               if (!capable(CAP_NET_ADMIN))
12274 +                       return -EPERM;
12275 +               if (nat_hdr.len != sizeof(NAT_STATUS_T))
12276 +                       return -EPERM;
12277 +               if (copy_from_user((void *)&ctrl.status, req_datap, sizeof(ctrl.status)))
12278 +                       return -EFAULT;
12279 +               if (ctrl.status.enable != 0 && ctrl.status.enable != 1)
12280 +                       return -EPERM;
12281 +               // sl351x_nat_set_enabled_flag(ctrl.status.enable);
12282 +               if (nat_cfg.enabled && (ctrl.status.enable == 0))
12283 +               {
12284 +                       for (i=0; i<HASH_TOTAL_ENTRIES; i++)
12285 +                       {
12286 +                               if (hash_get_nat_owner_flag(i))
12287 +                               {
12288 +                                       hash_nat_disable_owner(i);
12289 +                                       hash_invalidate_entry(i);
12290 +                               }
12291 +                       }
12292 +               }
12293 +               nat_cfg.enabled = ctrl.status.enable;
12294 +               break;
12295 +       case NATGSTATUS:
12296 +               if (nat_hdr.len != sizeof(NAT_STATUS_T))
12297 +                       return -EPERM;
12298 +               ctrl.status.enable = nat_cfg.enabled;
12299 +               if (copy_to_user(req_datap, (void *)&ctrl.status, sizeof(ctrl.status)))
12300 +                       return -EFAULT;
12301 +               break;
12302 +       case NATSETPORT:
12303 +               if (!capable(CAP_NET_ADMIN))
12304 +                       return -EPERM;
12305 +               if (nat_hdr.len != sizeof(NAT_PORTCFG_T))
12306 +                       return -EPERM;
12307 +               if (copy_from_user((void *)&ctrl.portcfg, req_datap, sizeof(ctrl.portcfg)))
12308 +                       return -EFAULT;
12309 +               if (ctrl.portcfg.portmap == 0)
12310 +                       nat_cfg.lan_port = port_id;
12311 +               else if (ctrl.portcfg.portmap == 1)
12312 +                       nat_cfg.wan_port = port_id;
12313 +               else
12314 +                       return -EPERM;
12315 +               break;
12316 +       case NATGETPORT:
12317 +               if (nat_hdr.len != sizeof(NAT_PORTCFG_T))
12318 +                       return -EPERM;
12319 +               if (nat_cfg.lan_port == port_id)
12320 +                       ctrl.portcfg.portmap = 0;
12321 +               else if (nat_cfg.wan_port == port_id)
12322 +                       ctrl.portcfg.portmap = 1;
12323 +               else
12324 +                       return -EPERM;
12325 +               if (copy_to_user(req_datap, (void *)&ctrl.portcfg, sizeof(ctrl.portcfg)))
12326 +                       return -EFAULT;
12327 +               break;
12328 +       case NATADDIP:
12329 +               if (!capable(CAP_NET_ADMIN))
12330 +                       return -EPERM;
12331 +               if (nat_hdr.len != sizeof(NAT_IPCFG_T))
12332 +                       return -EPERM;
12333 +               i = nat_cfg.ipcfg[port_id].total;
12334 +               if (i >= CONFIG_NAT_MAX_IP_NUM)
12335 +                       return -E2BIG;
12336 +               if (copy_from_user((void *)&nat_cfg.ipcfg[port_id].entry[i], req_datap, sizeof(NAT_IPCFG_T)))
12337 +                       return -EFAULT;
12338 +               nat_cfg.ipcfg[port_id].total++;
12339 +               break;
12340 +       case NATDELIP:
12341 +               if (!capable(CAP_NET_ADMIN))
12342 +                       return -EPERM;
12343 +               if (nat_hdr.len != sizeof(NAT_IPCFG_T))
12344 +                       return -EPERM;
12345 +               if (copy_from_user((void *)&ctrl.ipcfg, req_datap, sizeof(ctrl.ipcfg)))
12346 +                       return -EFAULT;
12347 +               ipcfg = (NAT_IP_ENTRY_T *)&nat_cfg.ipcfg[port_id].entry[0];
12348 +               for (i=0; i<nat_cfg.ipcfg[port_id].total; i++, ipcfg++)
12349 +               {
12350 +                       if (ipcfg->ipaddr == ctrl.ipcfg.entry.ipaddr)
12351 +                       {
12352 +                               NAT_IP_ENTRY_T *ipcfg_next;
12353 +                               ipcfg_next = ipcfg + 1;
12354 +                               for (j=i+1; j < nat_cfg.ipcfg[port_id].total; i++, j++)
12355 +                               {
12356 +                                       memcpy((void *)ipcfg, (void *)ipcfg_next, sizeof(NAT_IP_ENTRY_T));
12357 +                                       ipcfg++;
12358 +                                       ipcfg_next++;
12359 +                               }
12360 +                               ipcfg->ipaddr = 0;
12361 +                               ipcfg->netmask = 0;
12362 +                               nat_cfg.ipcfg[port_id].total--;
12363 +                               return 0;
12364 +                       }
12365 +               }
12366 +               return -ENOENT;
12367 +       case NATGETIP:
12368 +               if (nat_hdr.len != sizeof(NAT_IPCFG_ALL_T))
12369 +                       return -EPERM;
12370 +               if (copy_to_user(req_datap, (void *)&nat_cfg.ipcfg[port_id], sizeof(NAT_IPCFG_ALL_T)))
12371 +                       return -EFAULT;
12372 +               break;
12373 +       case NATAXPORT:
12374 +               if (!capable(CAP_NET_ADMIN))
12375 +                       return -EPERM;
12376 +               if (nat_hdr.len != sizeof(NAT_XPORT_T))
12377 +                       return -EPERM;
12378 +               i = nat_cfg.xport.total;
12379 +               if (i >= CONFIG_NAT_MAX_XPORT)
12380 +                       return -E2BIG;
12381 +               if (copy_from_user((void *)&nat_cfg.xport.entry[i], req_datap, sizeof(NAT_XPORT_T)))
12382 +                       return -EFAULT;
12383 +               nat_cfg.xport.total++;
12384 +               break;
12385 +       case NATDXPORT:
12386 +               if (!capable(CAP_NET_ADMIN))
12387 +                       return -EPERM;
12388 +               if (nat_hdr.len != sizeof(NAT_XPORT_T))
12389 +                       return -EPERM;
12390 +               if (copy_from_user((void *)&ctrl.xport, req_datap, sizeof(NAT_XPORT_T)))
12391 +                       return -EFAULT;
12392 +               xport_entry = (NAT_XPORT_ENTRY_T *)&nat_cfg.xport.entry[0];
12393 +               for (i=0; i<nat_cfg.xport.total; i++, xport_entry++)
12394 +               {
12395 +                       if (memcmp((void *)xport_entry, (void *)&ctrl.xport, sizeof(NAT_XPORT_ENTRY_T)) == 0)
12396 +                       {
12397 +                               NAT_XPORT_ENTRY_T *xport_next;
12398 +                               xport_next = xport_entry + 1;
12399 +                               for (j=i+1; j < nat_cfg.xport.total; i++, j++)
12400 +                               {
12401 +                                       memcpy((void *)xport_entry, (void *)xport_next, sizeof(NAT_XPORT_ENTRY_T));
12402 +                                       xport_entry++;
12403 +                                       xport_next++;
12404 +                               }
12405 +                               memset((void *)xport_entry, 0, sizeof(NAT_XPORT_ENTRY_T));
12406 +                               nat_cfg.xport.total--;
12407 +                               return 0;
12408 +                       }
12409 +               }
12410 +               return -ENOENT;
12411 +       case NATGXPORT:
12412 +               if (nat_hdr.len != sizeof(NAT_XPORT_ALL_T))
12413 +                       return -EPERM;
12414 +               if (copy_to_user(req_datap, (void *)&nat_cfg.xport, sizeof(NAT_XPORT_ALL_T)))
12415 +                       return -EFAULT;
12416 +               break;
12417 +       case NATSWEIGHT:
12418 +               if (!capable(CAP_NET_ADMIN))
12419 +                       return -EPERM;
12420 +               if (nat_hdr.len != sizeof(NAT_WEIGHT_T))
12421 +                       return -EPERM;
12422 +               if (copy_from_user((void *)&nat_cfg.weight, req_datap, sizeof(NAT_WEIGHT_T)))
12423 +                       return -EFAULT;
12424 +               mac_set_hw_tx_weight(dev, (char *)&nat_cfg.weight);
12425 +               break;
12426 +       case NATGWEIGHT:
12427 +               if (nat_hdr.len != sizeof(NAT_WEIGHT_T))
12428 +                       return -EPERM;
12429 +               mac_get_hw_tx_weight(dev, (char *)&nat_cfg.weight);
12430 +               if (copy_to_user(req_datap, (void *)&nat_cfg.weight, sizeof(NAT_WEIGHT_T)))
12431 +                       return -EFAULT;
12432 +               break;
12433 +       case NATAWRULE:
12434 +               if (!capable(CAP_NET_ADMIN))
12435 +                       return -EPERM;
12436 +               if (nat_hdr.len != sizeof(NAT_WRULE_T))
12437 +                       return -EPERM;
12438 +               if (copy_from_user((void *)&qid, req_datap, sizeof(qid)))
12439 +                       return -EFAULT;
12440 +               if (qid > CONFIG_NAT_TXQ_NUM)
12441 +                       return -EPERM;
12442 +               i = nat_cfg.wrule[qid].total;
12443 +               if (i >= CONFIG_NAT_MAX_WRULE)
12444 +                       return -E2BIG;
12445 +               if (copy_from_user((void *)&nat_cfg.wrule[qid].entry[i], req_datap+sizeof(qid), sizeof(NAT_WRULE_T)))
12446 +                       return -EFAULT;
12447 +               nat_cfg.wrule[qid].total++;
12448 +               break;
12449 +       case NATDWRULE:
12450 +               if (!capable(CAP_NET_ADMIN))
12451 +                       return -EPERM;
12452 +               if (nat_hdr.len != sizeof(NAT_WRULE_T))
12453 +                       return -EPERM;
12454 +               if (copy_from_user((void *)&ctrl.wrule, req_datap, sizeof(NAT_WRULE_T)))
12455 +                       return -EFAULT;
12456 +               qid = ctrl.wrule.qid;
12457 +               if (qid >= CONFIG_NAT_TXQ_NUM)
12458 +                       return -EPERM;
12459 +               wrule_entry = (NAT_WRULE_ENTRY_T *)&nat_cfg.wrule[qid].entry[0];
12460 +               for (i=0; i<nat_cfg.wrule[qid].total; i++, wrule_entry++)
12461 +               {
12462 +                       if (memcmp((void *)wrule_entry, (void *)&ctrl.wrule.entry, sizeof(NAT_WRULE_ENTRY_T)) == 0)
12463 +                       {
12464 +                               NAT_WRULE_ENTRY_T *wrule_next;
12465 +                               wrule_next = wrule_entry + 1;
12466 +                               for (j=i+1; j < nat_cfg.wrule[qid].total; i++, j++)
12467 +                               {
12468 +                                       memcpy((void *)wrule_entry, (void *)wrule_next, sizeof(NAT_WRULE_ENTRY_T));
12469 +                                       wrule_entry++;
12470 +                                       wrule_next++;
12471 +                               }
12472 +                               memset((void *)wrule_entry, 0, sizeof(NAT_WRULE_ENTRY_T));
12473 +                               nat_cfg.wrule[qid].total--;
12474 +                               return 0;
12475 +                       }
12476 +               }
12477 +               return -ENOENT;
12478 +       case NATGWRULE:
12479 +               if (nat_hdr.len != sizeof(NAT_WRULE_ALL_T))
12480 +                       return -EPERM;
12481 +               if (copy_from_user((void *)&qid, req_datap, sizeof(qid)))
12482 +                       return -EFAULT;
12483 +               if (qid >= CONFIG_NAT_TXQ_NUM)
12484 +                       return -EPERM;
12485 +               if (copy_to_user(req_datap, (void *)&nat_cfg.wrule[qid], sizeof(NAT_WRULE_ALL_T)))
12486 +                       return -EFAULT;
12487 +               break;
12488 +       case NATSDEFQ:
12489 +               if (!capable(CAP_NET_ADMIN))
12490 +                       return -EPERM;
12491 +               if (nat_hdr.len != sizeof(NAT_QUEUE_T))
12492 +                       return -EPERM;
12493 +               if (copy_from_user((void *)&nat_cfg.default_hw_txq, req_datap, sizeof(u32)))
12494 +                       return -EFAULT;
12495 +               break;
12496 +       case NATGDEFQ:
12497 +               if (nat_hdr.len != sizeof(NAT_QUEUE_T))
12498 +                       return -EPERM;
12499 +               if (copy_to_user(req_datap, (void *)&nat_cfg.default_hw_txq, sizeof(u32)))
12500 +                       return -EFAULT;
12501 +       case NATRMIPCFG:
12502 +               nat_cfg.ipcfg[port_id].total = 0;
12503 +               break;
12504 +       case NATTESTENTRY:
12505 +               if (!capable(CAP_NET_ADMIN))
12506 +                       return -EPERM;
12507 +               if (nat_hdr.len != sizeof(NAT_TESTENTRY_T))
12508 +                       return -EPERM;
12509 +               if (copy_from_user((void *)&ctrl.init_entry, req_datap, sizeof(ctrl.init_entry)))
12510 +                       return -EFAULT;
12511 +               if (ctrl.init_entry.init_enable != 0 && ctrl.init_entry.init_enable != 1)
12512 +                       return -EPERM;
12513 +               nat_cfg.init_enabled = ctrl.init_entry.init_enable;
12514 +               break;
12515 +
12516 +       default:
12517 +               return -EPERM;
12518 +       }
12519 +
12520 +       return 0;
12521 +}
12522 +
12523 +/*----------------------------------------------------------------------
12524 +*      nat_init_test_entry
12525 +*      Initialize NAT test hash entries
12526 +*
12527 +*      SmartBits P1  -----> Lepus GMAC 0 --------------+
12528 +*                                                                                                      |
12529 +*                                                                                                      |
12530 +*             P3  <----- Lepus GMAC 1 -- HW TxQ0 <--+
12531 +*                                                                        -- HW TxQ1 <--+
12532 +*                                                                        -- HW TxQ2 <--+
12533 +*                                                                        -- HW TxQ3 <--+
12534 +*
12535 +*      SmartBits P1  <----- Lepus GMAC 0 -- HW TxQ0 <--+
12536 +*                                                                        -- HW TxQ1 <--+
12537 +*                                     -- HW TxQ2 <--+
12538 +*                                                                        -- HW TxQ3 <--+
12539 +*                                                                                                      |
12540 +*                                                                                                      |
12541 +*             P3  -----> Lepus GMAC 1 --------------+
12542 +*
12543 +*   LAN GMAC0 <--------------------------------------------> GMAC1 WAN
12544 +*      192.168.[x].[y]:50 --> 168.95.[x].[y]:80 ---TXQ[y-1]---> 192.168.2.254:200[y] --> 168.95.[x].[y]:80
12545 +*      192.168.[x].[y]:50 <-- 168.95.[x].[y]:80 <--TXQ[y-1]---- 192.168.2.254:200[y] <-- 168.95.[x].[y]:80
12546 +*   where:
12547 +*              [x] : Packet Type
12548 +*              [y] : Tx Queue, 1 for TxQ0, 2 for TxQ1, 3 for TxQ2, 4 for TxQ3,
12549 +*
12550 +*
12551 +* Packet Type:
12552 +* 1. TCP Frames <---> TCP Frames
12553 +*   LAN GMAC0 <--------------------------------> GMAC1 WAN
12554 +*      192.168.1.1:50 --> 168.95.1.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.1.1:80
12555 +*      192.168.1.1:50 <-- 168.95.1.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.1.1:80
12556 +*
12557 +*      192.168.1.2:50 --> 168.95.1.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.1.2:80
12558 +*      192.168.1.2:50 <-- 168.95.1.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.1.2:80
12559 +*
12560 +*      192.168.1.3:50 --> 168.95.1.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.1.3:80
12561 +*      192.168.1.3:50 <-- 168.95.1.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.1.3:80
12562 +*
12563 +*      192.168.1.4:50 --> 168.95.1.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.1.4:80
12564 +*      192.168.1.4:50 <-- 168.95.1.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.1.4:80
12565 +*
12566 +* 2 TCP Frames <----> PPPoE + TCP Frames
12567 +*   LAN GMAC0 <--------------------------------> GMAC1 WAN
12568 +*      192.168.2.1:50 --> 168.95.2.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.2.1:80
12569 +*      192.168.2.1:50 <-- 168.95.2.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.2.1:80
12570 +*
12571 +*      192.168.2.2:50 --> 168.95.2.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.2.2:80
12572 +*      192.168.2.2:50 <-- 168.95.2.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.2.2:80
12573 +*
12574 +*      192.168.2.3:50 --> 168.95.2.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.2.3:80
12575 +*      192.168.2.3:50 <-- 168.95.2.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.2.3:80
12576 +*
12577 +*      192.168.2.4:50 --> 168.95.2.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.2.4:80
12578 +*      192.168.2.4:50 <-- 168.95.2.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.2.4:80
12579 +*
12580 +* 3 TCP Frames <----> VLAN + PPPoE + TCP Frames
12581 +*   LAN GMAC0 <--------------------------------> GMAC1 WAN
12582 +*      192.168.3.1:50 --> 168.95.3.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.3.1:80
12583 +*      192.168.3.1:50 <-- 168.95.3.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.3.1:80
12584 +*
12585 +*      192.168.3.2:50 --> 168.95.3.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.3.2:80
12586 +*      192.168.3.2:50 <-- 168.95.3.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.3.2:80
12587 +*
12588 +*      192.168.3.3:50 --> 168.95.3.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.3.3:80
12589 +*      192.168.3.3:50 <-- 168.95.3.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.3.3:80
12590 +*
12591 +*      192.168.3.4:50 --> 168.95.3.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.3.4:80
12592 +*      192.168.3.4:50 <-- 168.95.3.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.3.4:80
12593 +*
12594 +* 4 VLAN-A + TCP Frames <----> VLAN-B + PPPoE + TCP Frames
12595 +*   LAN GMAC0 <--------------------------------> GMAC1 WAN
12596 +*      192.168.4.1:50 --> 168.95.4.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.4.1:80
12597 +*      192.168.4.1:50 <-- 168.95.4.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.4.1:80
12598 +*
12599 +*      192.168.4.2:50 --> 168.95.4.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.4.2:80
12600 +*      192.168.4.2:50 <-- 168.95.4.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.4.2:80
12601 +*
12602 +*      192.168.4.3:50 --> 168.95.4.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.4.3:80
12603 +*      192.168.4.3:50 <-- 168.95.4.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.4.3:80
12604 +*
12605 +*      192.168.4.4:50 --> 168.95.4.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.4.4:80
12606 +*      192.168.4.4:50 <-- 168.95.4.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.4.4:80
12607 +*
12608 +*
12609 +*
12610 +*----------------------------------------------------------------------*/
12611 +#ifdef SL351x_NAT_TEST_BY_SMARTBITS
12612 +#define        NAT_IPIV(a,b,c,d)                       ((a<<24)+(b<<16)+(c<<8)+d)
12613 +#define     NAT_TEST_CLIENT_IP                         NAT_IPIV(192,168,1,1)
12614 +#define     NAT_TEST_SERVER_IP                         NAT_IPIV(168,95,1,1)
12615 +#define                NAT_TEST_LAN_IP                         NAT_IPIV(192,168,1,254)
12616 +#define                NAT_TEST_WAN_IP                         NAT_IPIV(192,168,2,254)
12617 +#define     NAT_TEST_MAP_PORT_BASE             2001
12618 +#define     NAT_TEST_SPORT                             50
12619 +#define     NAT_TEST_DPORT                             80
12620 +#define     NAT_TEST_PROTOCOL                  6
12621 +u8                     nat_test_lan_target_da[6]={0x00,0x11,0x22,0x33,0x44,0x55};
12622 +u8                     nat_test_wan_target_da[6]={0x00,0xaa,0xbb,0xcc,0xdd,0xee};
12623 +u8                     nat_test_lan_my_da[6]={0x00,0x11,0x11,0x11,0x11,0x11};
12624 +u8                     nat_test_wan_my_da[6]={0x00,0x22,0x22,0x22,0x22,0x22};
12625 +static void nat_init_test_entry(void)
12626 +{
12627 +       int                             i, j ;
12628 +       NAT_HASH_ENTRY_T        *hash_entry;
12629 +       u32                                     sip, dip;
12630 +       u32                                     hash_data[HASH_MAX_DWORDS];
12631 +       NAT_CFG_T                       *cfg;
12632 +       int                                     hash_index;
12633 +
12634 +       cfg = (NAT_CFG_T *)&nat_cfg;
12635 +       hash_entry = (NAT_HASH_ENTRY_T *)&hash_data;
12636 +       hash_entry->key.Ethertype       = 0;
12637 +       hash_entry->key.rule_id         = 0;
12638 +       hash_entry->key.ip_protocol = IPPROTO_TCP;
12639 +       hash_entry->key.reserved1       = 0;
12640 +       hash_entry->key.reserved2       = 0;
12641 +       // hash_entry->key.sip          = NAT_TEST_CLIENT_IP;
12642 +       // hash_entry->key.dip          = NAT_TEST_SERVER_IP;
12643 +       hash_entry->key.sport           = htons(NAT_TEST_SPORT);
12644 +       hash_entry->key.dport           = htons(NAT_TEST_DPORT);
12645 +       hash_entry->key.rule_id = cfg->tcp_udp_rule_id;
12646 +       hash_entry->action.dword = NAT_LAN2WAN_ACTIONS;
12647 +
12648 +       sip = NAT_TEST_CLIENT_IP;
12649 +       dip = NAT_TEST_SERVER_IP;
12650 +
12651 +       // Init TCP <------> TCP hash entries
12652 +       // LAN --> WAN
12653 +       // (1) TCP --> TCP
12654 +       // (2) TCP --> PPPoE + TCP
12655 +       // (3) TCP --> VLAN-B + PPPoE + TCP
12656 +       // (4) TCP + VLAN-A --> VLAN-B + PPPoE + TCP
12657 +       memcpy(hash_entry->param.da, nat_test_wan_target_da, 6);
12658 +       memcpy(hash_entry->param.sa, nat_test_wan_my_da, 6);
12659 +       hash_entry->key.port_id = cfg->lan_port;
12660 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
12661 +       {
12662 +               if (i < 2)
12663 +               {
12664 +                       hash_entry->action.bits.dest_qid = i+2;
12665 +               }
12666 +               else
12667 +               {
12668 +                       hash_entry->action.bits.dest_qid = i;
12669 +               }
12670 +               hash_entry->action.bits.dest_qid += (cfg->wan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
12671 +               hash_entry->param.Sport = NAT_TEST_MAP_PORT_BASE+i;
12672 +               hash_entry->param.Dport = NAT_TEST_DPORT;
12673 +               for (j=0; j<4; j++)
12674 +               {
12675 +                       hash_entry->key.sip = sip + i + j*0x100;
12676 +                       hash_entry->key.dip = dip + i + j*0x100;
12677 +                       hash_entry->param.Dip = hash_entry->key.dip;
12678 +                       hash_entry->param.Sip = NAT_TEST_WAN_IP;
12679 +                       switch (j)
12680 +                       {
12681 +                       case 0:
12682 +                               hash_entry->action.bits.pppoe = 0;
12683 +                               hash_entry->param.pppoe = 0;
12684 +                               hash_entry->action.bits.vlan = 0;
12685 +                               hash_entry->param.vlan = 0;
12686 +                               break;
12687 +                       case 1:
12688 +                               hash_entry->action.bits.pppoe = 1;
12689 +                               hash_entry->param.pppoe = i+1;
12690 +                               hash_entry->action.bits.vlan = 0;
12691 +                               hash_entry->param.vlan = 0;
12692 +                               break;
12693 +                       case 2:
12694 +                               hash_entry->action.bits.pppoe = 1;
12695 +                               hash_entry->param.pppoe = i+1;
12696 +                               hash_entry->action.bits.vlan = 1;
12697 +                               hash_entry->param.vlan = i+10;
12698 +                               break;
12699 +                       case 3:
12700 +                               hash_entry->action.bits.pppoe = 1;
12701 +                               hash_entry->param.pppoe = i+1;
12702 +                               hash_entry->action.bits.vlan = 1;
12703 +                               hash_entry->param.vlan = i+10;
12704 +                               break;
12705 +                       }
12706 +                       hash_entry->tmo.counter = hash_entry->tmo.interval = 0x7fff;
12707 +                       hash_index = nat_build_keys(&hash_entry->key);
12708 +                       nat_write_hash_entry(hash_index, hash_entry);
12709 +                       hash_nat_enable_owner(hash_index);
12710 +                       hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
12711 +               }
12712 +       }
12713 +
12714 +
12715 +       // WAN --> LAN
12716 +       hash_entry->key.port_id         = cfg->wan_port;
12717 +       hash_entry->key.sport           = htons(NAT_TEST_DPORT);
12718 +       hash_entry->key.dport           = htons(NAT_TEST_DPORT);
12719 +       hash_entry->key.rule_id         = cfg->tcp_udp_rule_id;
12720 +       hash_entry->action.dword        = NAT_WAN2LAN_ACTIONS;
12721 +       hash_entry->key.sport           = htons(NAT_TEST_DPORT);
12722 +       memcpy(hash_entry->param.da, nat_test_lan_target_da, 6);
12723 +       memcpy(hash_entry->param.sa, nat_test_lan_my_da, 6);
12724 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
12725 +       {
12726 +               hash_entry->key.dport = htons(NAT_TEST_MAP_PORT_BASE + i);
12727 +               if (i < 2)
12728 +               {
12729 +                       hash_entry->action.bits.dest_qid = i+2;
12730 +               }
12731 +               else
12732 +               {
12733 +                       hash_entry->action.bits.dest_qid = i;
12734 +               }
12735 +               hash_entry->action.bits.dest_qid += (cfg->lan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
12736 +               hash_entry->param.Dport = NAT_TEST_SPORT;
12737 +               hash_entry->param.Sport = NAT_TEST_DPORT;
12738 +               hash_entry->param.da[5] = i;
12739 +               for (j=0; j<4; j++)
12740 +               {
12741 +                       hash_entry->key.sip = (dip + i + j*0x100);
12742 +                       hash_entry->key.dip = (NAT_TEST_WAN_IP);
12743 +                       hash_entry->param.Sip = hash_entry->key.sip;
12744 +                       hash_entry->param.Dip = sip + i + j*0x100;
12745 +                       switch (j)
12746 +                       {
12747 +                       case 0:
12748 +                               hash_entry->action.bits.pppoe = 0;
12749 +                               hash_entry->param.pppoe = 0;
12750 +                               hash_entry->action.bits.vlan = 0;
12751 +                               hash_entry->param.vlan = 0;
12752 +                               break;
12753 +                       case 1:
12754 +                               hash_entry->action.bits.pppoe = 2;
12755 +                               hash_entry->param.pppoe = i+1;
12756 +                               hash_entry->action.bits.vlan = 0;
12757 +                               hash_entry->param.vlan = 0;
12758 +                               break;
12759 +                       case 2:
12760 +                               hash_entry->action.bits.pppoe = 2;
12761 +                               hash_entry->param.pppoe = i+1;
12762 +                               hash_entry->action.bits.vlan = 2;
12763 +                               hash_entry->param.vlan = i+5;
12764 +                               break;
12765 +                       case 3:
12766 +                               hash_entry->action.bits.pppoe = 1;
12767 +                               hash_entry->param.pppoe = i+1;
12768 +                               hash_entry->action.bits.vlan = 1;
12769 +                               hash_entry->param.vlan = i+5;
12770 +                               break;
12771 +                       }
12772 +                       hash_entry->tmo.counter = hash_entry->tmo.interval = 0x7fff;
12773 +                       hash_index = nat_build_keys(&hash_entry->key);
12774 +                       nat_write_hash_entry(hash_index, hash_entry);
12775 +                       hash_nat_enable_owner(hash_index);
12776 +                       hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
12777 +               }
12778 +       }
12779 +}
12780 +#endif // SL351x_NAT_TEST_BY_SMARTBITS
12781 +
12782 +#endif // CONFIG_SL351x_NAT
12783 +
12784 --- /dev/null
12785 +++ b/drivers/net/sl351x_proc.c
12786 @@ -0,0 +1,578 @@
12787 +/****************************************************************************
12788 +* Copyright 2006 Storlink Corp.  All rights reserved.
12789 +*----------------------------------------------------------------------------
12790 +* Name                 : sl351x_proc.c
12791 +* Description  :
12792 +*              Handle Proc Routines for Storlink SL351x Platform
12793 +*
12794 +* History
12795 +*
12796 +*      Date            Writer          Description
12797 +*----------------------------------------------------------------------------
12798 +*      04/13/2006      Gary Chen       Create and implement
12799 +*
12800 +*
12801 +****************************************************************************/
12802 +#include <linux/module.h>
12803 +#include <linux/kernel.h>
12804 +#include <linux/compiler.h>
12805 +#include <linux/pci.h>
12806 +#include <linux/init.h>
12807 +#include <linux/ioport.h>
12808 +#include <linux/netdevice.h>
12809 +#include <linux/etherdevice.h>
12810 +#include <linux/rtnetlink.h>
12811 +#include <linux/delay.h>
12812 +#include <linux/ethtool.h>
12813 +#include <linux/mii.h>
12814 +#include <linux/completion.h>
12815 +#include <asm/hardware.h>
12816 +#include <asm/io.h>
12817 +#include <asm/irq.h>
12818 +#include <asm/semaphore.h>
12819 +#include <asm/arch/irqs.h>
12820 +#include <asm/arch/it8712.h>
12821 +#include <linux/mtd/kvctl.h>
12822 +#include <linux/skbuff.h>
12823 +#include <linux/if_ether.h>
12824 +#include <linux/if_pppox.h>
12825 +#include <linux/in.h>
12826 +#include <linux/ip.h>
12827 +#include <linux/tcp.h>
12828 +#include <linux/ppp_defs.h>
12829 +#ifdef CONFIG_NETFILTER
12830 +// #include <linux/netfilter_ipv4/ip_conntrack.h>
12831 +#endif
12832 +#include <linux/proc_fs.h>
12833 +#include <linux/seq_file.h>
12834 +#include <linux/percpu.h>
12835 +#ifdef CONFIG_SYSCTL
12836 +#include <linux/sysctl.h>
12837 +#endif
12838 +
12839 +#define         MIDWAY
12840 +#define         SL_LEPUS
12841 +
12842 +// #define PROC_DEBUG_MSG      1
12843 +
12844 +#include <asm/arch/sl2312.h>
12845 +#include <asm/arch/sl351x_gmac.h>
12846 +#include <asm/arch/sl351x_hash_cfg.h>
12847 +#include <asm/arch/sl351x_nat_cfg.h>
12848 +#include <asm/arch/sl351x_toe.h>
12849 +
12850 +#ifdef CONFIG_PROC_FS
12851 +/*----------------------------------------------------------------------
12852 +* Definition
12853 +*----------------------------------------------------------------------*/
12854 +#define        proc_printf                                     printk
12855 +#define SL351x_GMAC_PROC_NAME          "sl351x_gmac"
12856 +#define SL351x_NAT_PROC_NAME           "sl351x_nat"
12857 +#define SL351x_TOE_PROC_NAME           "sl351x_toe"
12858 +
12859 +/*----------------------------------------------------------------------
12860 +* Function Definition
12861 +*----------------------------------------------------------------------*/
12862 +#ifdef CONFIG_SL351x_NAT
12863 +static int nat_ct_open(struct inode *inode, struct file *file);
12864 +static void *nat_ct_seq_start(struct seq_file *s, loff_t *pos);
12865 +static void nat_ct_seq_stop(struct seq_file *s, void *v);
12866 +static void *nat_ct_seq_next(struct seq_file *s, void *v, loff_t *pos);
12867 +static int nat_ct_seq_show(struct seq_file *s, void *v);
12868 +#endif
12869 +
12870 +#ifdef CONFIG_SL351x_RXTOE
12871 +static int toe_ct_open(struct inode *inode, struct file *file);
12872 +static void *toe_ct_seq_start(struct seq_file *s, loff_t *pos);
12873 +static void toe_ct_seq_stop(struct seq_file *s, void *v);
12874 +static void *toe_ct_seq_next(struct seq_file *s, void *v, loff_t *pos);
12875 +static int toe_ct_seq_show(struct seq_file *s, void *v);
12876 +extern int sl351x_get_toe_conn_flag(int index);
12877 +extern struct toe_conn * sl351x_get_toe_conn_info(int index);
12878 +#endif
12879 +
12880 +static int gmac_ct_open(struct inode *inode, struct file *file);
12881 +static void *gmac_ct_seq_start(struct seq_file *s, loff_t *pos);
12882 +static void gmac_ct_seq_stop(struct seq_file *s, void *v);
12883 +static void *gmac_ct_seq_next(struct seq_file *s, void *v, loff_t *pos);
12884 +static int gmac_ct_seq_show(struct seq_file *s, void *v);
12885 +
12886 +
12887 +/*----------------------------------------------------------------------
12888 +* Data
12889 +*----------------------------------------------------------------------*/
12890 +#ifdef CONFIG_SYSCTL
12891 +// static struct ctl_table_header *nat_ct_sysctl_header;
12892 +#endif
12893 +
12894 +#ifdef CONFIG_SL351x_NAT
12895 +static struct seq_operations nat_ct_seq_ops = {
12896 +       .start = nat_ct_seq_start,
12897 +       .next  = nat_ct_seq_next,
12898 +       .stop  = nat_ct_seq_stop,
12899 +       .show  = nat_ct_seq_show
12900 +};
12901 +
12902 +static struct file_operations nat_file_ops= {
12903 +       .owner   = THIS_MODULE,
12904 +       .open    = nat_ct_open,
12905 +       .read    = seq_read,
12906 +       .llseek  = seq_lseek,
12907 +       .release = seq_release
12908 +};
12909 +#endif // CONFIG_SL351x_NAT
12910 +
12911 +#ifdef CONFIG_SL351x_RXTOE
12912 +static struct seq_operations toe_ct_seq_ops = {
12913 +       .start = toe_ct_seq_start,
12914 +       .next  = toe_ct_seq_next,
12915 +       .stop  = toe_ct_seq_stop,
12916 +       .show  = toe_ct_seq_show
12917 +};
12918 +
12919 +static struct file_operations toe_file_ops= {
12920 +       .owner   = THIS_MODULE,
12921 +       .open    = toe_ct_open,
12922 +       .read    = seq_read,
12923 +       .llseek  = seq_lseek,
12924 +       .release = seq_release
12925 +};
12926 +#endif
12927 +
12928 +static struct seq_operations gmac_ct_seq_ops = {
12929 +       .start = gmac_ct_seq_start,
12930 +       .next  = gmac_ct_seq_next,
12931 +       .stop  = gmac_ct_seq_stop,
12932 +       .show  = gmac_ct_seq_show
12933 +};
12934 +
12935 +static struct file_operations gmac_file_ops= {
12936 +       .owner   = THIS_MODULE,
12937 +       .open    = gmac_ct_open,
12938 +       .read    = seq_read,
12939 +       .llseek  = seq_lseek,
12940 +       .release = seq_release
12941 +};
12942 +
12943 +#ifdef SL351x_GMAC_WORKAROUND
12944 +extern u32 gmac_workaround_cnt[4];
12945 +extern u32 gmac_short_frame_workaround_cnt[2];
12946 +#ifdef CONFIG_SL351x_NAT
12947 +       extern u32 sl351x_nat_workaround_cnt;
12948 +#endif
12949 +#endif
12950 +/*----------------------------------------------------------------------
12951 +* nat_ct_open
12952 +*----------------------------------------------------------------------*/
12953 +#ifdef CONFIG_SL351x_NAT
12954 +static int nat_ct_open(struct inode *inode, struct file *file)
12955 +{
12956 +       return seq_open(file, &nat_ct_seq_ops);
12957 +}
12958 +#endif // CONFIG_SL351x_NAT
12959 +/*----------------------------------------------------------------------
12960 +* nat_ct_seq_start
12961 +* find the first
12962 +*----------------------------------------------------------------------*/
12963 +#ifdef CONFIG_SL351x_NAT
12964 +static void *nat_ct_seq_start(struct seq_file *s, loff_t *pos)
12965 +{
12966 +       int i;
12967 +
12968 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
12969 +       for (i=*pos; i<HASH_TOTAL_ENTRIES; i++)
12970 +       {
12971 +               if (hash_get_nat_owner_flag(i))
12972 +               {
12973 +                       *pos = i;
12974 +                       return (void *)(i+1);
12975 +               }
12976 +       }
12977 +       return NULL;
12978 +}
12979 +#endif // CONFIG_SL351x_NAT
12980 +/*----------------------------------------------------------------------
12981 +* nat_ct_seq_stop
12982 +*----------------------------------------------------------------------*/
12983 +#ifdef CONFIG_SL351x_NAT
12984 +static void nat_ct_seq_stop(struct seq_file *s, void *v)
12985 +{
12986 +}
12987 +#endif // CONFIG_SL351x_NAT
12988 +/*----------------------------------------------------------------------
12989 +* nat_ct_seq_next
12990 +*----------------------------------------------------------------------*/
12991 +#ifdef CONFIG_SL351x_NAT
12992 +static void *nat_ct_seq_next(struct seq_file *s, void *v, loff_t *pos)
12993 +{
12994 +       int i;
12995 +
12996 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
12997 +       (*pos)++;
12998 +       for (i=*pos; i<HASH_TOTAL_ENTRIES; i++)
12999 +       {
13000 +               if (hash_get_nat_owner_flag(i))
13001 +               {
13002 +                       *pos = i;
13003 +                       return (void *)(i+1);
13004 +               }
13005 +       }
13006 +       return NULL;
13007 +}
13008 +#endif // CONFIG_SL351x_NAT
13009 +/*----------------------------------------------------------------------
13010 +* nat_ct_seq_show
13011 +*----------------------------------------------------------------------*/
13012 +#ifdef CONFIG_SL351x_NAT
13013 +static int nat_ct_seq_show(struct seq_file *s, void *v)
13014 +{
13015 +       int                             idx;
13016 +       NAT_HASH_ENTRY_T        *nat_entry;
13017 +       GRE_HASH_ENTRY_T        *gre_entry;
13018 +
13019 +       idx = (int)v;
13020 +       if (idx<=0 || idx >HASH_TOTAL_ENTRIES)
13021 +               return -ENOSPC;
13022 +
13023 +       idx--;
13024 +       nat_entry = (NAT_HASH_ENTRY_T *)&hash_tables[idx];
13025 +       gre_entry = (GRE_HASH_ENTRY_T *)nat_entry;
13026 +       if (nat_entry->key.ip_protocol == IPPROTO_GRE)
13027 +       {
13028 +               if (seq_printf(s, "%4d: KEY MAC-%d [%d] %u.%u.%u.%u [%u]-->%u.%u.%u.%u\n",
13029 +                                       idx, gre_entry->key.port_id, gre_entry->key.ip_protocol,
13030 +                                       HIPQUAD(gre_entry->key.sip), ntohs(gre_entry->key.call_id),
13031 +                                       HIPQUAD(gre_entry->key.dip)))
13032 +                       return -ENOSPC;
13033 +               if (seq_printf(s, "      PARAMETER: %u.%u.%u.%u -->%u.%u.%u.%u [%u] Timeout:%ds\n",
13034 +                                       HIPQUAD(gre_entry->param.Sip),
13035 +                                       HIPQUAD(gre_entry->param.Dip), gre_entry->param.Dport,
13036 +                                       gre_entry->tmo.counter))
13037 +                       return -ENOSPC;
13038 +       }
13039 +       else
13040 +       {
13041 +               if (seq_printf(s, "%4d: KEY MAC-%d [%d] %u.%u.%u.%u [%u]-->%u.%u.%u.%u [%u]\n",
13042 +                                       idx, nat_entry->key.port_id, nat_entry->key.ip_protocol,
13043 +                                       HIPQUAD(nat_entry->key.sip), ntohs(nat_entry->key.sport),
13044 +                                       HIPQUAD(nat_entry->key.dip), ntohs(nat_entry->key.dport)))
13045 +                       return -ENOSPC;
13046 +               if (seq_printf(s, "      PARAMETER: %u.%u.%u.%u [%u]-->%u.%u.%u.%u [%u] Timeout:%ds\n",
13047 +                                       HIPQUAD(nat_entry->param.Sip), nat_entry->param.Sport,
13048 +                                       HIPQUAD(nat_entry->param.Dip), nat_entry->param.Dport,
13049 +                                       nat_entry->tmo.counter))
13050 +                       return -ENOSPC;
13051 +       }
13052 +       return 0;
13053 +}
13054 +#endif // CONFIG_SL351x_NAT
13055 +
13056 +/*----------------------------------------------------------------------
13057 +* toe_ct_open
13058 +*----------------------------------------------------------------------*/
13059 +#ifdef CONFIG_SL351x_RXTOE
13060 +static int toe_ct_open(struct inode *inode, struct file *file)
13061 +{
13062 +       return seq_open(file, &toe_ct_seq_ops);
13063 +}
13064 +#endif
13065 +/*----------------------------------------------------------------------
13066 +* toe_ct_seq_start
13067 +* find the first
13068 +*----------------------------------------------------------------------*/
13069 +#ifdef CONFIG_SL351x_RXTOE
13070 +static void *toe_ct_seq_start(struct seq_file *s, loff_t *pos)
13071 +{
13072 +       int i;
13073 +
13074 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
13075 +       for (i=*pos; i<TOE_TOE_QUEUE_NUM; i++)
13076 +       {
13077 +               if (sl351x_get_toe_conn_flag(i))
13078 +               {
13079 +                       *pos = i;
13080 +                       return (void *)(i+1);
13081 +               }
13082 +       }
13083 +       return NULL;
13084 +}
13085 +#endif
13086 +/*----------------------------------------------------------------------
13087 +* toe_ct_seq_stop
13088 +*----------------------------------------------------------------------*/
13089 +#ifdef CONFIG_SL351x_RXTOE
13090 +static void toe_ct_seq_stop(struct seq_file *s, void *v)
13091 +{
13092 +}
13093 +#endif
13094 +/*----------------------------------------------------------------------
13095 +* toe_ct_seq_next
13096 +*----------------------------------------------------------------------*/
13097 +#ifdef CONFIG_SL351x_RXTOE
13098 +static void *toe_ct_seq_next(struct seq_file *s, void *v, loff_t *pos)
13099 +{
13100 +       int i;
13101 +
13102 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
13103 +       (*pos)++;
13104 +       for (i=*pos; i<TOE_TOE_QUEUE_NUM; i++)
13105 +       {
13106 +               if (sl351x_get_toe_conn_flag(i))
13107 +               {
13108 +                       *pos = i;
13109 +                       return (void *)(i+1);
13110 +               }
13111 +       }
13112 +       return NULL;
13113 +}
13114 +#endif
13115 +/*----------------------------------------------------------------------
13116 +* toe_ct_seq_show
13117 +*----------------------------------------------------------------------*/
13118 +#ifdef CONFIG_SL351x_RXTOE
13119 +static int toe_ct_seq_show(struct seq_file *s, void *v)
13120 +{
13121 +       int                             idx;
13122 +       struct toe_conn         *toe_entry;
13123 +
13124 +       idx = (int)v;
13125 +       if (idx<=0 || idx >TOE_TOE_QUEUE_NUM)
13126 +               return -ENOSPC;
13127 +
13128 +       idx--;
13129 +       toe_entry = (struct toe_conn *)sl351x_get_toe_conn_info(idx);
13130 +       if (!toe_entry)
13131 +               return -ENOSPC;
13132 +
13133 +       if (seq_printf(s, "%4d: Qid %d MAC-%d TCP %u.%u.%u.%u [%u]-->%u.%u.%u.%u [%u]\n",
13134 +                               idx, toe_entry->qid, toe_entry->gmac->port_id,
13135 +                               NIPQUAD(toe_entry->saddr[0]), ntohs(toe_entry->source),
13136 +                               NIPQUAD(toe_entry->daddr[0]), ntohs(toe_entry->dest)))
13137 +                       return -ENOSPC;
13138 +       return 0;
13139 +}
13140 +#endif
13141 +/*----------------------------------------------------------------------
13142 +* gmac_ct_open
13143 +*----------------------------------------------------------------------*/
13144 +static int gmac_ct_open(struct inode *inode, struct file *file)
13145 +{
13146 +       return seq_open(file, &gmac_ct_seq_ops);
13147 +}
13148 +
13149 +/*----------------------------------------------------------------------
13150 +* gmac_ct_seq_start
13151 +* find the first
13152 +*----------------------------------------------------------------------*/
13153 +static void *gmac_ct_seq_start(struct seq_file *s, loff_t *pos)
13154 +{
13155 +       int i;
13156 +       i = (int)*pos + 1;;
13157 +
13158 +       if (i > 9)
13159 +               return NULL;
13160 +       else
13161 +               return (void *)i;
13162 +}
13163 +
13164 +/*----------------------------------------------------------------------
13165 +* gmac_ct_seq_stop
13166 +*----------------------------------------------------------------------*/
13167 +static void gmac_ct_seq_stop(struct seq_file *s, void *v)
13168 +{
13169 +}
13170 +
13171 +/*----------------------------------------------------------------------
13172 +* gmac_ct_seq_next
13173 +*----------------------------------------------------------------------*/
13174 +static void *gmac_ct_seq_next(struct seq_file *s, void *v, loff_t *pos)
13175 +{
13176 +       int i;
13177 +
13178 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
13179 +
13180 +       (*pos)++;
13181 +       i = (int)*pos + 1;;
13182 +
13183 +       if (i > 9)
13184 +               return NULL;
13185 +       else
13186 +               return (void *)i;
13187 +}
13188 +
13189 +/*----------------------------------------------------------------------
13190 +* seq_dm_long
13191 +*----------------------------------------------------------------------*/
13192 +static void seq_dm_long(struct seq_file *s, u32 location, int length)
13193 +{
13194 +       u32             *start_p, *curr_p, *end_p;
13195 +       u32             *datap, data;
13196 +       int             i;
13197 +
13198 +       //if (length > 1024)
13199 +       //      length = 1024;
13200 +
13201 +       start_p = (u32 *)location;
13202 +       end_p = (u32 *)location + length;
13203 +       curr_p = (u32 *)((u32)location & 0xfffffff0);
13204 +       datap = (u32 *)location;
13205 +       while (curr_p < end_p)
13206 +       {
13207 +               cond_resched();
13208 +               seq_printf(s, "0x%08x: ",(u32)curr_p & 0xfffffff0);
13209 +               for (i=0; i<4; i++)
13210 +               {
13211 +                       if (curr_p < start_p || curr_p >= end_p)
13212 +               seq_printf(s, "         ");
13213 +                       else
13214 +                       {
13215 +                               data = *datap;
13216 +                               seq_printf(s, "%08X ", data);
13217 +                       }
13218 +                       if (i==1)
13219 +              seq_printf(s, "- ");
13220 +
13221 +                       curr_p++;
13222 +                       datap++;
13223 +               }
13224 +        seq_printf(s, "\n");
13225 +       }
13226 +}
13227 +
13228 +/*----------------------------------------------------------------------
13229 +* gmac_ct_seq_show
13230 +*----------------------------------------------------------------------*/
13231 +static int gmac_ct_seq_show(struct seq_file *s, void *v)
13232 +{
13233 +       switch ((int)v)
13234 +       {
13235 +               case 1:
13236 +                       seq_printf(s, "\nGMAC Global Registers\n");
13237 +                       seq_dm_long(s, TOE_GLOBAL_BASE, 32);
13238 +                       break;
13239 +               case 2:
13240 +                       seq_printf(s, "\nGMAC Non-TOE Queue Header\n");
13241 +                       seq_dm_long(s, TOE_NONTOE_QUE_HDR_BASE, 12);
13242 +                       break;
13243 +               case 3:
13244 +                       seq_printf(s, "\nGMAC TOE Queue Header\n");
13245 +                       seq_dm_long(s, TOE_TOE_QUE_HDR_BASE, 12);
13246 +                       break;
13247 +               case 4:
13248 +                       seq_printf(s, "\nGMAC-0 DMA Registers\n");
13249 +                       seq_dm_long(s, TOE_GMAC0_DMA_BASE, 52);
13250 +                       break;
13251 +               case 5:
13252 +                       seq_printf(s, "\nGMAC-0 Registers\n");
13253 +                       seq_dm_long(s, TOE_GMAC0_BASE, 32);
13254 +                       break;
13255 +               case 6:
13256 +                       seq_printf(s, "\nGMAC-1 DMA Registers\n");
13257 +                       seq_dm_long(s, TOE_GMAC1_DMA_BASE, 52);
13258 +                       break;
13259 +               case 7:
13260 +                       seq_printf(s, "\nGMAC-1 Registers\n");
13261 +                       seq_dm_long(s, TOE_GMAC1_BASE, 32);
13262 +                       break;
13263 +               case 8:
13264 +                       seq_printf(s, "\nGLOBAL Registers\n");
13265 +                       seq_dm_long(s, GMAC_GLOBAL_BASE_ADDR, 16);
13266 +                       break;
13267 +               case 9:
13268 +#ifdef SL351x_GMAC_WORKAROUND
13269 +                       seq_printf(s, "\nGMAC-0 Rx/Tx/Short Workaround: %u, %u, %u\n", gmac_workaround_cnt[0], gmac_workaround_cnt[1], gmac_short_frame_workaround_cnt[0]);
13270 +                       seq_printf(s, "GMAC-1 Rx/Tx/Short Workaround: %u, %u, %u\n", gmac_workaround_cnt[2], gmac_workaround_cnt[3], gmac_short_frame_workaround_cnt[1]);
13271 +#ifdef CONFIG_SL351x_NAT
13272 +                       seq_printf(s, "NAT Workaround: %u\n", sl351x_nat_workaround_cnt);
13273 +#endif
13274 +#endif
13275 +                       break;
13276 +               default:
13277 +                       return -ENOSPC;
13278 +       }
13279 +       return 0;
13280 +}
13281 +
13282 +/*----------------------------------------------------------------------
13283 +* init
13284 +*----------------------------------------------------------------------*/
13285 +static int __init init(void)
13286 +{
13287 +       struct proc_dir_entry *proc_gmac=NULL;
13288 +
13289 +#ifdef CONFIG_SL351x_NAT
13290 +       struct proc_dir_entry *proc_nat=NULL;
13291 +#endif
13292 +
13293 +#ifdef CONFIG_SL351x_RXTOE
13294 +       struct proc_dir_entry *proc_toe=NULL;
13295 +#endif
13296 +
13297 +#ifdef CONFIG_SYSCTL
13298 +       // nat_ct_sysctl_header = NULL;
13299 +#endif
13300 +       proc_gmac = proc_net_fops_create(SL351x_GMAC_PROC_NAME, 0440, &gmac_file_ops);
13301 +       if (!proc_gmac) goto init_bad;
13302 +
13303 +#ifdef CONFIG_SL351x_NAT
13304 +       proc_nat = proc_net_fops_create(SL351x_NAT_PROC_NAME, 0440, &nat_file_ops);
13305 +       if (!proc_nat) goto init_bad;
13306 +#endif // CONFIG_SL351x_NAT
13307 +
13308 +#ifdef CONFIG_SL351x_RXTOE
13309 +       proc_toe = proc_net_fops_create(SL351x_TOE_PROC_NAME, 0440, &toe_file_ops);
13310 +       if (!proc_toe) goto init_bad;
13311 +#endif
13312 +
13313 +#ifdef CONFIG_SYSCTL
13314 +       // nat_ct_sysctl_header = register_sysctl_table(nat_ct_net_table, 0);
13315 +       // if (!nat_ct_sysctl_header) goto init_bad;
13316 +#endif
13317 +
13318 +       return 0;
13319 +
13320 +init_bad:
13321 +       if (proc_gmac) proc_net_remove(SL351x_GMAC_PROC_NAME);
13322 +
13323 +#ifdef CONFIG_SL351x_NAT
13324 +       if (proc_nat) proc_net_remove(SL351x_NAT_PROC_NAME);
13325 +#endif
13326 +
13327 +#ifdef CONFIG_SL351x_RXTOE
13328 +       if (proc_toe) proc_net_remove(SL351x_NAT_PROC_NAME);
13329 +#endif
13330 +
13331 +#ifdef CONFIG_SYSCTL
13332 +       // if (nat_ct_sysctl_header) unregister_sysctl_table(nat_ct_sysctl_header);
13333 +#endif
13334 +       proc_printf("SL351x NAT Proc: can't create proc or register sysctl.\n");
13335 +       return -ENOMEM;
13336 +}
13337 +
13338 +/*----------------------------------------------------------------------
13339 +* fini
13340 +*----------------------------------------------------------------------*/
13341 +static void __exit fini(void)
13342 +{
13343 +       proc_net_remove(SL351x_GMAC_PROC_NAME);
13344 +
13345 +#ifdef CONFIG_SL351x_NAT
13346 +       proc_net_remove(SL351x_NAT_PROC_NAME);
13347 +#endif
13348 +
13349 +#ifdef CONFIG_SL351x_RXTOE
13350 +       proc_net_remove(SL351x_TOE_PROC_NAME);
13351 +#endif
13352 +
13353 +#ifdef CONFIG_SYSCTL
13354 +       // unregister_sysctl_table(nat_ct_sysctl_header);
13355 +#endif
13356 +}
13357 +
13358 +/*----------------------------------------------------------------------
13359 +* module
13360 +*----------------------------------------------------------------------*/
13361 +module_init(init);
13362 +module_exit(fini);
13363 +
13364 +#endif // CONFIG_PROC_FS
13365 --- /dev/null
13366 +++ b/drivers/net/sl351x_toe.c
13367 @@ -0,0 +1,1083 @@
13368 +/**************************************************************************
13369 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
13370 +*--------------------------------------------------------------------------
13371 +* Name                 : sl351x_toe.c
13372 +* Description  :
13373 +*              Provide TOE routines for SL351x
13374 +*
13375 +* History
13376 +*
13377 +*      Date            Writer          Description
13378 +*----------------------------------------------------------------------------
13379 +*                              Xiaochong
13380 +*
13381 +****************************************************************************/
13382 +
13383 +#include <linux/pci.h>
13384 +#include <linux/ip.h>
13385 +#include <linux/ipv6.h>
13386 +#include <linux/tcp.h>
13387 +#include <linux/slab.h>
13388 +#include <linux/etherdevice.h>
13389 +#include <asm/io.h>
13390 +#include <linux/sysctl_storlink.h>
13391 +#include <net/tcp.h>
13392 +#include <linux/if_ether.h>
13393 +#include <asm/arch/sl351x_gmac.h>
13394 +#include <asm/arch/sl351x_toe.h>
13395 +#include <asm/arch/sl351x_hash_cfg.h>
13396 +#include <asm/arch/sl351x_nat_cfg.h>
13397 +
13398 +static int in_toe_isr;
13399 +static int toe_initialized=0;
13400 +
13401 +static struct toe_conn toe_connections[TOE_TOE_QUEUE_NUM];
13402 +EXPORT_SYMBOL(toe_connections);
13403 +static __u32 toe_connection_bits[TOE_TOE_QUEUE_NUM/32] __attribute__ ((aligned(16)));
13404 +struct sk_buff* gen_pure_ack(struct toe_conn* connection, TOE_QHDR_T* toe_qhdr, INTR_QHDR_T *intr_curr_desc);
13405 +
13406 +extern struct storlink_sysctl  storlink_ctl;
13407 +extern TOE_INFO_T toe_private_data;
13408 +extern spinlock_t gmac_fq_lock;
13409 +extern void mac_write_dma_reg(int mac, unsigned int offset, u32 data);
13410 +extern int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2);
13411 +extern int hash_add_toe_entry(HASH_ENTRY_T *entry);
13412 +extern void toe_gmac_fill_free_q(void);
13413 +
13414 +#define _DEBUG_SKB_            1
13415 +#ifdef _DEBUG_SKB_
13416 +/*---------------------------------------------------------------------------
13417 + * _debug_skb
13418 + *-------------------------------------------------------------------------*/
13419 +static inline void _debug_skb(struct sk_buff *skb, GMAC_RXDESC_T *toe_curr_desc, u32 data)
13420 +{
13421 +       if ((u32)skb < 0x1000)
13422 +       {
13423 +               printk("%s skb=%x\n", __func__, (u32)skb);
13424 +               while(1);
13425 +       }
13426 +       REG32(__va(toe_curr_desc->word2.buf_adr)-SKB_RESERVE_BYTES) = data;
13427 +}
13428 +#else
13429 +#define _debug_skb(x, y, z)
13430 +#endif
13431 +
13432 +/*---------------------------------------------------------------------------
13433 + * get_connection_seq_num
13434 + *-------------------------------------------------------------------------*/
13435 +u32 get_connection_seq_num(unsigned short qid)
13436 +{
13437 +       TOE_QHDR_T      *toe_qhdr;
13438 +
13439 +       toe_qhdr = (TOE_QHDR_T*)TOE_TOE_QUE_HDR_BASE;
13440 +       toe_qhdr += qid;
13441 +       return (u32)toe_qhdr->word3.seq_num;
13442 +}
13443 +EXPORT_SYMBOL(get_connection_seq_num);
13444 +
13445 +/*---------------------------------------------------------------------------
13446 + * get_connection_ack_num
13447 + *-------------------------------------------------------------------------*/
13448 +u32 get_connection_ack_num(unsigned short qid)
13449 +{
13450 +       TOE_QHDR_T      *toe_qhdr;
13451 +
13452 +       toe_qhdr = (TOE_QHDR_T*)TOE_TOE_QUE_HDR_BASE;
13453 +       toe_qhdr += qid;
13454 +       return (u32)toe_qhdr->word4.ack_num;
13455 +}
13456 +EXPORT_SYMBOL(get_connection_ack_num);
13457 +
13458 +/*---------------------------------------------------------------------------
13459 + * dump_toe_qhdr
13460 + *-------------------------------------------------------------------------*/
13461 +void dump_toe_qhdr(TOE_QHDR_T *toe_qhdr)
13462 +{
13463 +       printk("TOE w1 %x, w2 %x, w3 %x\n", toe_qhdr->word1.bits32,
13464 +               toe_qhdr->word2.bits32, toe_qhdr->word3.bits32);
13465 +       printk("w4 %x, w5 %x, w6 %x\n", toe_qhdr->word4.bits32,
13466 +               toe_qhdr->word5.bits32, toe_qhdr->word6.bits32);
13467 +}
13468 +
13469 +/*---------------------------------------------------------------------------
13470 + * dump_intrq_desc
13471 + *-------------------------------------------------------------------------*/
13472 +void dump_intrq_desc(INTR_QHDR_T *intr_curr_desc)
13473 +{
13474 +       printk("INTR w0 %x, w1 %x, seq %x\n", intr_curr_desc->word0.bits32,
13475 +               intr_curr_desc->word1.bits32, intr_curr_desc->word2.bits32);
13476 +       printk("ack %x, w4 %x\n", intr_curr_desc->word3.bits32,
13477 +               intr_curr_desc->word4.bits32);
13478 +}
13479 +
13480 +/*---------------------------------------------------------------------------
13481 + * This routine will initialize a TOE matching rule
13482 + * called by SL351x GMAC driver.
13483 + *-------------------------------------------------------------------------*/
13484 +void sl351x_toe_init(void)
13485 +{
13486 +       GMAC_MRxCR0_T   mrxcr0;
13487 +       GMAC_MRxCR1_T   mrxcr1;
13488 +       GMAC_MRxCR2_T   mrxcr2;
13489 +       int     rule, rc;
13490 +
13491 +       if (toe_initialized)
13492 +               return;
13493 +
13494 +       toe_initialized = 1;
13495 +
13496 +#ifndef CONFIG_SL351x_NAT
13497 +       mrxcr0.bits32 = 0;
13498 +       mrxcr1.bits32 = 0;
13499 +       mrxcr2.bits32 = 0;
13500 +       mrxcr0.bits.l3 = 1;
13501 +       mrxcr0.bits.l4 = 1;
13502 +       mrxcr1.bits.sip = 1;
13503 +       mrxcr1.bits.dip = 1;
13504 +       mrxcr1.bits.l4_byte0_15 = 0x0f;
13505 +       mrxcr0.bits.sprx = 1;
13506 +       rule = 0;
13507 +       rc = mac_set_rule_reg(0, rule, 1, mrxcr0.bits32, mrxcr1.bits32,
13508 +                                               mrxcr2.bits32);
13509 +       if (rc<0) {
13510 +               printk("%s::Set MAC 0 rule fail!\n", __func__);
13511 +       }
13512 +       rc = mac_set_rule_reg(1, rule, 1, mrxcr0.bits32, mrxcr1.bits32,
13513 +                                               mrxcr2.bits32);
13514 +       if (rc<0) {
13515 +               printk("%s::Set MAC 1 rule fail!\n", __func__);
13516 +       }
13517 +#endif // CONFIG_SL351x_NAT
13518 +}
13519 +
13520 +/*---------------------------------------------------------------------------
13521 + * dump_intrq_desc
13522 + * assign an interrupt queue number to a give tcp queue
13523 + *-------------------------------------------------------------------------*/
13524 +int get_interrupt_queue_id(int tcp_qid)
13525 +{
13526 +       return (int)(tcp_qid & 0x0003);
13527 +}
13528 +
13529 +/*---------------------------------------------------------------------------
13530 + * reset_connection_index
13531 + * reset the connection bit by given index
13532 + *-------------------------------------------------------------------------*/
13533 +void reset_connection_index(__u8 index)
13534 +{
13535 +       __u32 mask = ~(0xffffffff & (1<< (index&0x1f)));
13536 +       toe_connection_bits[index>>5] = toe_connection_bits[index>>5] & mask;
13537 +}
13538 +
13539 +/*---------------------------------------------------------------------------
13540 + * update_timer
13541 + *-------------------------------------------------------------------------*/
13542 +void update_timer(struct toe_conn* connection)
13543 +{
13544 +//     if (time_before(jiffies, connection->last_rx_jiffies+3))
13545 +//     if ((jiffies + 0xffffffff - connection->last_rx_jiffies) & 0x3)
13546 +//     if (connection->last_rx_jiffies > jiffies)
13547 +//             printk("%s::jif %g, last_rx_jif %g\n", __func__, jiffies, connection->last_rx_jiffies);
13548 +/*     if ((long)(jiffies + 2)< 3) { // overflow...
13549 +               printk("%s::jiffies %x\n", __func__, jiffies);
13550 +       } */
13551 +//     if ((long)(jiffies - connection->last_rx_jiffies)< 2)
13552 +//             return;
13553 +       connection->last_rx_jiffies = jiffies;
13554 +       // gary chen mod_timer(&connection->rx_timer, jiffies+2);
13555 +       connection->rx_timer.expires = jiffies + 2;
13556 +       add_timer(&connection->rx_timer);
13557 +//     printk("%s::nt %x, lj %x\n", __func__, (jiffies+2), connection->last_rx_jiffies);
13558 +}
13559 +
13560 +/*---------------------------------------------------------------------------
13561 + * gen_pure_ack
13562 + *-------------------------------------------------------------------------*/
13563 +struct sk_buff* gen_pure_ack(struct toe_conn* connection, TOE_QHDR_T* toe_qhdr,
13564 +INTR_QHDR_T *intr_curr_desc)
13565 +{
13566 +       struct sk_buff  *skb;
13567 +       struct iphdr    *ip_hdr;
13568 +       struct tcphdr   *tcp_hdr;
13569 +       struct ethhdr   *eth_hdr;
13570 +
13571 +       if ((skb= dev_alloc_skb(RX_BUF_SIZE))==NULL) {
13572 +               printk("%s::alloc pure ack fail!\n", __func__);
13573 +               return NULL;
13574 +       }
13575 +       skb_reserve(skb, RX_INSERT_BYTES);
13576 +       memset(skb->data, 0, 60);
13577 +
13578 +       eth_hdr = (struct ethhdr*)&(skb->data[0]);
13579 +       memcpy(eth_hdr, &connection->l2_hdr, sizeof(struct ethhdr));
13580 +
13581 +       ip_hdr = (struct iphdr*)&(skb->data[14]);
13582 +       ip_hdr->version = connection->ip_ver;
13583 +       ip_hdr->ihl = 20>>2;
13584 +       ip_hdr->tot_len = ntohs(40);
13585 +       ip_hdr->frag_off = htons(IP_DF);
13586 +       ip_hdr->ttl = 128;
13587 +       ip_hdr->protocol = 0x06;
13588 +       ip_hdr->saddr = connection->saddr[0];
13589 +       ip_hdr->daddr = connection->daddr[0];
13590 +//     printk("%s ip sa %x, da %x\n",
13591 +//             __func__, ntohl(ip_hdr->saddr), ntohl(ip_hdr->daddr));
13592 +
13593 +       tcp_hdr = (struct tcphdr*)&(skb->data[34]);
13594 +       tcp_hdr->source = connection->source;
13595 +       tcp_hdr->dest = connection->dest;
13596 +       if (intr_curr_desc) {
13597 +               tcp_hdr->seq = htonl(intr_curr_desc->word2.seq_num);
13598 +               tcp_hdr->ack_seq = htonl(intr_curr_desc->word3.ack_num);
13599 +               tcp_hdr->window = htons(intr_curr_desc->word0.bits.win_size);
13600 +       } else {
13601 +               tcp_hdr->seq = htonl(toe_qhdr->word3.seq_num);
13602 +               tcp_hdr->ack_seq = htonl(toe_qhdr->word4.ack_num);
13603 +               tcp_hdr->window = htons(toe_qhdr->word6.bits.WinSize);
13604 +       }
13605 +       tcp_hdr->ack = 1;
13606 +       tcp_hdr->doff = 20 >> 2;
13607 +#if 0
13608 +       if (!intr_curr_desc) {
13609 +               unsigned char byte;
13610 +               for (i=0; i<20; i++) {
13611 +                       byte = skb->data[34+i];
13612 +                       printk("%x ", byte);
13613 +               }
13614 +               printk("\n");
13615 +       }
13616 +#endif
13617 +       TCP_SKB_CB(skb)->connection = connection;
13618 +       return skb;
13619 +}
13620 +
13621 +/*---------------------------------------------------------------------------
13622 + * connection_rx_timer
13623 + *-------------------------------------------------------------------------*/
13624 +void connection_rx_timer(unsigned long *data)
13625 +{
13626 +       struct toe_conn *connection = (struct toe_conn*)data;
13627 +       unsigned int    tcp_qid, toeq_wptr;
13628 +       unsigned int    pkt_size, desc_count;
13629 +       struct sk_buff  *skb;
13630 +       GMAC_RXDESC_T   *toe_curr_desc;
13631 +       TOE_QHDR_T      *toe_qhdr;
13632 +       struct net_device       *dev;
13633 +       unsigned long   conn_flags;
13634 +       DMA_RWPTR_T             toeq_rwptr;
13635 +       unsigned short  timeout_descs;
13636 +
13637 +       if (in_toe_isr)
13638 +               printk("%s::in_toe_isr=%d!\n", __func__, in_toe_isr);
13639 +
13640 +       if (connection) {
13641 +               /* should we disable gmac interrupt first? */
13642 +               if (!connection->gmac)
13643 +                       printk("%s::conn gmac %x!\n", __func__, (u32)connection->gmac);
13644 +               local_irq_save(conn_flags);
13645 +               if (!spin_trylock(&connection->conn_lock)) {
13646 +                       local_irq_restore(conn_flags);
13647 +                       // timer should be updated by the toeq isr. So no need to update here.
13648 +                       printk("%s::conn_lock is held by ISR!\n", __func__);
13649 +                       return;
13650 +               }
13651 +               disable_irq(connection->gmac->irq);
13652 +
13653 +               /* disable hash entry and get toeq desc. */
13654 +               hash_set_valid_flag(connection->hash_entry_index, 0);
13655 +               do{} while(0);  /* wait until HW finish */
13656 +
13657 +               dev = connection->dev;
13658 +               if (!dev)
13659 +                       printk("%s::conn dev NULL!\n", __func__);
13660 +               tcp_qid = connection->qid;
13661 +               toe_qhdr = (TOE_QHDR_T *)(TOE_TOE_QUE_HDR_BASE +
13662 +                             tcp_qid * sizeof(TOE_QHDR_T));
13663 +               toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
13664 +               toeq_wptr = toe_qhdr->word1.bits.wptr;
13665 +               timeout_descs = toeq_wptr - toeq_rwptr.bits.rptr;
13666 +
13667 +               if (toeq_rwptr.bits.rptr == toeq_wptr) {
13668 +                       if (toe_qhdr->word5.bits32) {
13669 +                               // shall we check toe_qhdr->word2.bits?
13670 +                               skb = gen_pure_ack(connection, toe_qhdr, (INTR_QHDR_T *)NULL);
13671 +                               skb_put(skb, 54);
13672 +                               skb->dev = connection->dev;
13673 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
13674 +                               skb->protocol = eth_type_trans(skb, connection->dev);
13675 +                               netif_rx(skb);
13676 +                               connection->dev->last_rx = jiffies;
13677 +                       }
13678 +               } else {
13679 +                       while (toeq_rwptr.bits.rptr != toeq_rwptr.bits.wptr) {
13680 +                               /* we just simply send those packets to tcp? */
13681 +                               toe_curr_desc = (GMAC_RXDESC_T*)(toe_private_data.toe_desc_base[tcp_qid]
13682 +                                       + toeq_rwptr.bits.rptr * sizeof(GMAC_RXDESC_T));
13683 +                               connection->curr_desc = toe_curr_desc;
13684 +                               if (toe_curr_desc->word3.bits.ctrl_flag) {
13685 +                                       printk("%s::ctrl flag! %x, conn rptr %d, to %d, jif %x, conn_jif %x\n",
13686 +                                               __func__, toe_curr_desc->word3.bits32,
13687 +                                               connection->toeq_rwptr.bits.rptr, timeout_descs,
13688 +                                               (u32)jiffies, (u32)connection->last_rx_jiffies);
13689 +                               }
13690 +                               desc_count = toe_curr_desc->word0.bits.desc_count;
13691 +                               pkt_size = toe_curr_desc->word1.bits.byte_count;
13692 +                               consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
13693 +                                       PCI_DMA_FROMDEVICE);
13694 +                               skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr)-
13695 +                                       SKB_RESERVE_BYTES));
13696 +                               _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x02);
13697 +                               connection->curr_rx_skb = skb;
13698 +                               skb_reserve(skb, RX_INSERT_BYTES);
13699 +                               skb_put(skb, pkt_size);
13700 +                               skb->dev = dev;
13701 +                               skb->protocol = eth_type_trans(skb, dev);
13702 +                               {
13703 +                                       struct iphdr* ip_hdr = (struct iphdr*)&(skb->data[0]);
13704 +                                       if (toe_curr_desc->word3.bits.ctrl_flag)
13705 +                                               printk("%s::ip id %x\n", __func__, ntohs(ip_hdr->id));
13706 +                               }
13707 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
13708 +
13709 +                               netif_rx(skb);
13710 +                               dev->last_rx = jiffies;
13711 +#if 0
13712 +                               if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
13713 +                                       printk("%s::alloc buf fail!\n", __func__);
13714 +                               }
13715 +                               *(unsigned int*)(skb->data) = (unsigned int)skb;
13716 +                               connection->curr_rx_skb = skb;
13717 +                               skb_reserve(skb, SKB_RESERVE_BYTES);
13718 +                               spin_lock_irqsave(&connection->gmac->rx_mutex, flags);
13719 +                               fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
13720 +                               if (toe_private_data.fq_rx_rwptr.bits.wptr != fq_rwptr.bits.wptr) {
13721 +                                       mac_stop_txdma((struct net_device*)connection->dev);
13722 +                                       spin_unlock_irqrestore(&connection->gmac->rx_mutex, flags);
13723 +                                       while(1);
13724 +                               }
13725 +                               fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base + fq_rwptr.bits.wptr;
13726 +                               fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
13727 +                               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
13728 +                               SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
13729 +                               toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
13730 +                               spin_unlock_irqrestore(&connection->gmac->rx_mutex, flags);
13731 +#endif
13732 +//                             spin_lock_irqsave(&connection->gmac->rx_mutex, flags);
13733 +                               toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
13734 +                               SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
13735 +//                             spin_unlock_irqrestore(&connection->gmac->rx_mutex, flags);
13736 +                               connection->toeq_rwptr.bits32 = toeq_rwptr.bits32;
13737 +                       }
13738 +                       toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
13739 +//                     toe_gmac_fill_free_q();
13740 +               }
13741 +               connection->last_rx_jiffies = jiffies;
13742 +               if (connection->status != TCP_CONN_CLOSED)
13743 +                       mod_timer(&connection->rx_timer, jiffies+2);
13744 +               if (connection->status != TCP_CONN_ESTABLISHED)
13745 +                       printk("%s::conn status %x\n", __func__, connection->status);
13746 +               hash_set_valid_flag(connection->hash_entry_index, 1);
13747 +               enable_irq(connection->gmac->irq);
13748 +               // Gary Chen spin_unlock_irqrestore(&connection->conn_lock, conn_flags);
13749 +       }
13750 +}
13751 +
13752 +/*---------------------------------------------------------------------------
13753 + * free_toeq_descs
13754 + *-------------------------------------------------------------------------*/
13755 +void free_toeq_descs(int qid, TOE_INFO_T *toe)
13756 +{
13757 +       void    *desc_ptr;
13758 +
13759 +       desc_ptr = (void*)toe->toe_desc_base[qid];
13760 +       pci_free_consistent(NULL, TOE_TOE_DESC_NUM*sizeof(GMAC_RXDESC_T), desc_ptr,
13761 +          (dma_addr_t)toe->toe_desc_base_dma[qid]);
13762 +       toe->toe_desc_base[qid] = 0;
13763 +}
13764 +
13765 +/*---------------------------------------------------------------------------
13766 + * set_toeq_hdr
13767 + *-------------------------------------------------------------------------*/
13768 +void set_toeq_hdr(struct toe_conn*     connection, TOE_INFO_T* toe, struct net_device *dev)
13769 +{
13770 +       volatile TOE_QHDR_T     *toe_qhdr;
13771 +       volatile unsigned int   toeq_wptr; // toeq_rptr
13772 +       volatile GMAC_RXDESC_T  *toe_curr_desc;
13773 +       struct sk_buff  *skb;
13774 +       unsigned int    pkt_size;
13775 +       DMA_RWPTR_T     toeq_rwptr;
13776 +
13777 +       if (connection->status == TCP_CONN_CLOSING) {
13778 +               connection->status = TCP_CONN_CLOSED;
13779 +               hash_set_valid_flag(connection->hash_entry_index, 0);
13780 +               // remove timer first.
13781 +               // del_timer_sync(&(connection->rx_timer));
13782 +               // check if any queued frames last time.
13783 +               toe_qhdr = (volatile TOE_QHDR_T*)TOE_TOE_QUE_HDR_BASE;
13784 +               toe_qhdr += connection->qid;
13785 +               toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
13786 +
13787 +               //toeq_rptr = toe_qhdr->word1.bits.rptr;
13788 +               toeq_wptr = toe_qhdr->word1.bits.wptr;
13789 +               while (toeq_rwptr.bits.rptr != toeq_wptr) {
13790 +                       printk("%s::pending frames in TOE Queue before closing!\n", __func__);
13791 +                       toe_curr_desc = (GMAC_RXDESC_T*)(toe->toe_desc_base[connection->qid] +
13792 +                               toe_qhdr->word1.bits.rptr*sizeof(GMAC_RXDESC_T));
13793 +                       connection->curr_desc = (GMAC_RXDESC_T *)toe_curr_desc;
13794 +                       pkt_size = toe_curr_desc->word1.bits.byte_count;
13795 +                       consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
13796 +                               PCI_DMA_FROMDEVICE);
13797 +                       skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr) -
13798 +                               SKB_RESERVE_BYTES));
13799 +                       _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x03);
13800 +                       connection->curr_rx_skb = skb;
13801 +                       skb_reserve(skb, RX_INSERT_BYTES);
13802 +                       skb_put(skb, pkt_size);
13803 +                       skb->dev = connection->dev;
13804 +                       skb->protocol = eth_type_trans(skb, connection->dev);
13805 +                       skb->ip_summed = CHECKSUM_UNNECESSARY;
13806 +                       netif_rx(skb);
13807 +                       connection->dev->last_rx = jiffies;
13808 +
13809 +                       toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
13810 +                       SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
13811 +               }
13812 +               free_toeq_descs(connection->qid, toe);
13813 +               // shall we re-fill free queue?
13814 +
13815 +               reset_connection_index(connection->qid);
13816 +               //memset(connection, 0, sizeof(struct toe_conn));
13817 +               printk(" del timer and close connection %x, qid %d\n", (u32)connection, connection->qid);
13818 +               return;
13819 +       }
13820 +       /* enable or setup toe queue header */
13821 +       if (connection->status == TCP_CONN_CONNECTING && storlink_ctl.rx_max_pktsize) {
13822 +               volatile TOE_QHDR_T     *qhdr;
13823 +               int iq_id;
13824 +               connection->status = TCP_CONN_ESTABLISHED;
13825 +               qhdr = (volatile TOE_QHDR_T*)((unsigned int)TOE_TOE_QUE_HDR_BASE +
13826 +                              connection->qid * sizeof(TOE_QHDR_T));
13827 +
13828 +               iq_id = get_interrupt_queue_id(connection->qid);
13829 +               connection->dev = dev;
13830 +               connection->gmac = dev->priv;
13831 +               connection->toeq_rwptr.bits32 = 0;
13832 +
13833 +//             qhdr->word6.bits.iq_num = iq_id;
13834 +               qhdr->word6.bits.MaxPktSize = (connection->max_pktsize)>>2; // in word.
13835 +               qhdr->word7.bits.AckThreshold = connection->ack_threshold;
13836 +               qhdr->word7.bits.SeqThreshold = connection->seq_threshold;
13837 +
13838 +               // init timer.
13839 +#if 1
13840 +               init_timer(&connection->rx_timer);
13841 +               connection->rx_timer.expires = jiffies + 5;
13842 +               connection->rx_timer.data = (unsigned long)connection;
13843 +               connection->rx_timer.function = (void *)&connection_rx_timer;
13844 +               add_timer(&connection->rx_timer);
13845 +               connection->last_rx_jiffies = jiffies;
13846 +               printk("init_timer %x\n", (u32)jiffies);
13847 +#endif
13848 +               hash_set_valid_flag(connection->hash_entry_index, 1);
13849 +               return;
13850 +       } else {
13851 +               printk("%s::conn status %x, rx_pktsize %d\n",
13852 +                       __func__, connection->status, storlink_ctl.rx_max_pktsize);
13853 +       }
13854 +}
13855 +
13856 +/*---------------------------------------------------------------------------
13857 + * get_connection_index
13858 + * get_connection_index will find an available index for the connection,
13859 + * when allocate a new connection is needed.
13860 + * we find available Qid from AV bits and write to hash_table, so that when RxTOE
13861 + * packet is received, sw_id from ToeQ descriptor is also the Qid of conneciton Q.
13862 + *-------------------------------------------------------------------------*/
13863 +int get_connection_index(void)
13864 +{
13865 +       int i=0, j=0, index=-1;
13866 +       __u32   connection_bits;
13867 +
13868 +       for (i = 0; i< TOE_TOE_QUEUE_NUM/32; i++) {
13869 +               connection_bits = ~(toe_connection_bits[i]);
13870 +               if (connection_bits == 0)
13871 +                       // all 32 bits are used.
13872 +                       continue;
13873 +
13874 +               for (j=0; j<32; j++) {
13875 +                       if (connection_bits & 0x01) {
13876 +                               index = i*32 + j;
13877 +                               return index;
13878 +                       }
13879 +                       connection_bits = connection_bits >> 1;
13880 +               }
13881 +       }
13882 +       return index;
13883 +}
13884 +
13885 +/*---------------------------------------------------------------------------
13886 + * set_toe_connection
13887 + *-------------------------------------------------------------------------*/
13888 +void set_toe_connection(int index, int val)
13889 +{
13890 +       if (val) {
13891 +               toe_connection_bits[index/32] |= (1<<(index%32));
13892 +       } else {
13893 +               toe_connection_bits[index/32] &= (~(1<<(index%32)));
13894 +       }
13895 +}
13896 +
13897 +/*---------------------------------------------------------------------------
13898 + * sl351x_get_toe_conn_flag
13899 + *-------------------------------------------------------------------------*/
13900 +int sl351x_get_toe_conn_flag(int index)
13901 +{
13902 +       if (index < TOE_TOE_QUEUE_NUM)
13903 +               return (toe_connection_bits[index/32] & (1 << (index %32)));
13904 +       else
13905 +               return 0;
13906 +}
13907 +
13908 +/*---------------------------------------------------------------------------
13909 + * sl351x_get_toe_conn_info
13910 + *-------------------------------------------------------------------------*/
13911 +struct toe_conn * sl351x_get_toe_conn_info(int index)
13912 +{
13913 +       if (index < TOE_TOE_QUEUE_NUM)
13914 +               return (struct toe_conn *)&toe_connections[index];
13915 +       else
13916 +               return NULL;
13917 +}
13918 +
13919 +/*---------------------------------------------------------------------------
13920 + * create_sw_toe_connection
13921 + *-------------------------------------------------------------------------*/
13922 +struct toe_conn* create_sw_toe_connection(int qid, int ip_ver, void* ip_hdr,
13923 +       struct tcphdr* tcp_hdr)
13924 +{
13925 +       struct toe_conn*        connection =  &(toe_connections[qid]);
13926 +
13927 +       connection->ip_ver = (__u8)ip_ver;
13928 +       connection->qid = (__u8)qid;
13929 +       connection->source = (__u16)tcp_hdr->source;
13930 +       connection->dest = (__u16)tcp_hdr->dest;
13931 +       if (ip_ver == 4) {
13932 +               struct iphdr* iph = (struct iphdr*) ip_hdr;
13933 +               connection->saddr[0] = (__u32)iph->saddr;
13934 +               connection->daddr[0] = (__u32)iph->daddr;
13935 +//             printk("%s::saddr %x, daddr %x\n", __func__,
13936 +//                     ntohl(connection->saddr[0]), ntohl(connection->daddr[0]));
13937 +       } else if (ip_ver == 6) {
13938 +               struct ipv6hdr *iph = (struct ipv6hdr*)ip_hdr;
13939 +               int i=0;
13940 +               for (i=0; i<4; i++) {
13941 +                       connection->saddr[i] = (__u32)iph->saddr.in6_u.u6_addr32[i];
13942 +                       connection->daddr[i] = (__u32)iph->daddr.in6_u.u6_addr32[i];
13943 +               }
13944 +       }
13945 +       connection->status = TCP_CONN_CREATION;
13946 +       return connection;
13947 +}
13948 +
13949 +/*---------------------------------------------------------------------------
13950 + * fill_toeq_buf
13951 + *-------------------------------------------------------------------------*/
13952 +int fill_toeq_buf(int index, TOE_INFO_T* toe)
13953 +{
13954 +       volatile TOE_QHDR_T     *qhdr;
13955 +       //struct toe_conn* connection;
13956 +       GMAC_RXDESC_T   *desc_ptr;
13957 +
13958 +       if (!toe->toe_desc_base[index]) {
13959 +               // first time. init.
13960 +               desc_ptr = (GMAC_RXDESC_T*)(pci_alloc_consistent(NULL, TOE_TOE_DESC_NUM
13961 +                           *sizeof(GMAC_RXDESC_T), (dma_addr_t*)&toe->toe_desc_base_dma[index]));
13962 +
13963 +               toe->toe_desc_num = TOE_TOE_DESC_NUM;
13964 +               toe->toe_desc_base[index] = (unsigned int)desc_ptr;
13965 +       }
13966 +       qhdr = (volatile TOE_QHDR_T*)((unsigned int)TOE_TOE_QUE_HDR_BASE +
13967 +                                                                       index*sizeof(TOE_QHDR_T));
13968 +       //connection = (struct toe_conn*)&(toe_connections[index]);
13969 +
13970 +       qhdr->word0.base_size = ((unsigned int)toe->toe_desc_base_dma[index]&TOE_QHDR0_BASE_MASK)
13971 +                                       | TOE_TOE_DESC_POWER;
13972 +       qhdr->word1.bits32 = 0;
13973 +       qhdr->word2.bits32 = 0;
13974 +       qhdr->word3.bits32 = 0;
13975 +       qhdr->word4.bits32 = 0;
13976 +       qhdr->word5.bits32 = 0;
13977 +       return 1;
13978 +}
13979 +
13980 +/*---------------------------------------------------------------------------
13981 + * create_toe_hash_entry_smb
13982 + * add SMB header in hash entry.
13983 + *-------------------------------------------------------------------------*/
13984 +int create_toe_hash_entry_smb(int ip_ver, void* ip_hdr, struct tcphdr* tcp_hdr,
13985 +       int sw_id)
13986 +{
13987 +       HASH_ENTRY_T    hash_entry, *entry;
13988 +       int     hash_entry_index;
13989 +       int i;
13990 +
13991 +       entry = (HASH_ENTRY_T*)&hash_entry;
13992 +       memset((void*)entry, 0, sizeof(HASH_ENTRY_T));
13993 +       entry->rule = 0;
13994 +
13995 +       /* enable fields of hash key */
13996 +       entry->key_present.ip_protocol = 1;
13997 +       entry->key_present.sip = 1;
13998 +       entry->key_present.dip = 1;
13999 +       entry->key_present.l4_bytes_0_3 = 1;    // src port and dest port
14000 +       entry->key_present.l7_bytes_0_3 = 0;    // do we need to enable NETBIOS? how?
14001 +       entry->key_present.l7_bytes_4_7 = 1;    // "SMB" header
14002 +
14003 +       /* hash key */
14004 +       entry->key.ip_protocol = IPPROTO_TCP;
14005 +       if (ip_ver == 4) {
14006 +               struct iphdr *iph = (struct iphdr*)ip_hdr;
14007 +               memcpy(entry->key.sip, &iph->saddr, 4);
14008 +               memcpy(entry->key.dip, &iph->daddr, 4);
14009 +       } else if (ip_ver == 6) {
14010 +               struct ipv6hdr *iph = (struct ipv6hdr*)ip_hdr;
14011 +               for (i=0; i<4; i++) {
14012 +                       memcpy(&(entry->key.sip[i*4]), &(iph->saddr.in6_u.u6_addr32[i]), 4);
14013 +                       memcpy(&(entry->key.dip[i*4]), &(iph->daddr.in6_u.u6_addr32[i]), 4);
14014 +               }
14015 +       }
14016 +       *(__u16*)&entry->key.l4_bytes[0] = tcp_hdr->source;
14017 +       *(__u16*)&entry->key.l4_bytes[2] = tcp_hdr->dest;
14018 +
14019 +       entry->key.l7_bytes[4] = 0xff;
14020 +       entry->key.l7_bytes[5] = 0x53;
14021 +       entry->key.l7_bytes[6] = 0x4d;
14022 +       entry->key.l7_bytes[7] = 0x42;
14023 +
14024 +       /* action of hash entry match */
14025 +       entry->action.sw_id = 1;
14026 +       entry->action.dest_qid = (__u8)TOE_TOE_QID(sw_id);
14027 +       entry->action.srce_qid = 0;
14028 +       hash_entry_index = hash_add_toe_entry(entry);
14029 +
14030 +       return hash_entry_index;
14031 +}
14032 +
14033 +// best performance of tcp streaming.
14034 +/*---------------------------------------------------------------------------
14035 + * create_toe_hash_entry_smb
14036 + * add SMB header in hash entry.
14037 + *-------------------------------------------------------------------------*/
14038 +int create_toe_hash_entry_ftp(int ip_ver, void* ip_hdr, struct tcphdr* tcphdr)
14039 +{
14040 +       return 0;
14041 +}
14042 +
14043 +// is hash entry for nfs needed?
14044 +
14045 +/*
14046 + * Create a TOE hash entry by given ip addresses and tcp port numbers.
14047 + * hash entry index will be saved in sw connection.
14048 + */
14049 +/*---------------------------------------------------------------------------
14050 + * create_toe_hash_entry
14051 + *-------------------------------------------------------------------------*/
14052 +int create_toe_hash_entry(int ip_ver, void* ip_hdr, struct tcphdr* tcp_hdr, int sw_id)
14053 +{
14054 +       HASH_ENTRY_T    hash_entry, *entry;
14055 +//     unsigned long   hash_key[HASH_MAX_DWORDS];
14056 +       int     hash_entry_index;
14057 +
14058 +       entry = (HASH_ENTRY_T*) &hash_entry;
14059 +       memset((void*)entry, 0, sizeof(HASH_ENTRY_T));
14060 +       entry->rule = 0;
14061 +       /* enable fields of hash key */
14062 +       entry->key_present.ip_protocol = 1;
14063 +       entry->key_present.sip = 1;
14064 +       entry->key_present.dip = 1;
14065 +       entry->key_present.l4_bytes_0_3 = 1;    // src port and dest port
14066 +
14067 +       /* hash key */
14068 +       entry->key.ip_protocol = IPPROTO_TCP;
14069 +       if (ip_ver == 4) {
14070 +               // key of ipv4
14071 +               struct iphdr* iph = (struct iphdr*)ip_hdr;
14072 +               memcpy(entry->key.sip, &iph->saddr, 4);
14073 +               memcpy(entry->key.dip, &iph->daddr, 4);
14074 +       } else if (ip_ver == 6) {
14075 +               // key of ipv6
14076 +               int i=0;
14077 +               struct ipv6hdr *iph = (struct ipv6hdr*)ip_hdr;
14078 +               for (i=0; i<4; i++) {
14079 +                       memcpy(&(entry->key.sip[i*4]), &(iph->saddr.in6_u.u6_addr32[i]), 4);
14080 +                       memcpy(&(entry->key.dip[i*4]), &(iph->daddr.in6_u.u6_addr32[i]), 4);
14081 +               }
14082 +       }
14083 +       *(__u16*)&entry->key.l4_bytes[0] = tcp_hdr->source;
14084 +       *(__u16*)&entry->key.l4_bytes[2] = tcp_hdr->dest;
14085 +       // is it necessary to write ip version to hash key?
14086 +
14087 +       /* action of hash entry match */
14088 +       entry->action.sw_id = 1;
14089 +       entry->action.dest_qid = (__u8)TOE_TOE_QID(sw_id);
14090 +       entry->action.srce_qid = 0;     // 0 for SW FreeQ. 1 for HW FreeQ.
14091 +       hash_entry_index = hash_add_toe_entry(entry);
14092 +//     printk("\n%s. sw_id %d, hash_entry index %x\n",
14093 +//             __func__, TOE_TOE_QID(sw_id), hash_entry_index);
14094 +       return hash_entry_index;
14095 +}
14096 +
14097 +/*---------------------------------------------------------------------------
14098 + * init_toeq
14099 + * 1. Reserve a TOE Queue id first, to get the sw toe_connection.
14100 + * 2. Setup the hash entry with given iphdr and tcphdr, save hash entry index
14101 + *    in sw toe_connection.
14102 + * 3. Prepare sw toe_connection and allocate buffers.
14103 + * 4. Validate hash entry.
14104 + *-------------------------------------------------------------------------*/
14105 +struct toe_conn* init_toeq(int ipver, void* iph, struct tcphdr* tcp_hdr,
14106 +       TOE_INFO_T* toe, unsigned char* l2hdr)
14107 +{
14108 +//     printk("\t*** %s, ipver %d\n", __func__, ipver);
14109 +       int qid=-1;
14110 +       struct toe_conn* connection;
14111 +       int hash_entry_index;
14112 +       // int i=0;
14113 +       unsigned short  dest_port = ntohs(tcp_hdr->dest);
14114 +
14115 +       if (dest_port == 445) {
14116 +               printk("%s::SMB/CIFS connection\n", __func__);
14117 +       } else if (dest_port == 20) {
14118 +               printk("%s::ftp-data connection\n", __func__);
14119 +       } else if (dest_port == 2049) {
14120 +               printk("%s::nfs daemon connection\n", __func__);
14121 +       }
14122 +       qid = get_connection_index();
14123 +       if (qid<0)
14124 +               return 0;       // setup toeq failure
14125 +       set_toe_connection(qid, 1); // reserve this sw toeq.
14126 +
14127 +       //connection = (struct toe_conn*)&(toe_connections[qid]);
14128 +       hash_entry_index = create_toe_hash_entry(ipver, iph, tcp_hdr, qid);
14129 +       if (hash_entry_index <0) {
14130 +               printk("%s::release toe hash entry!\n", __func__);
14131 +               set_toe_connection(qid, 0); // release this sw toeq.
14132 +               return 0;
14133 +       }
14134 +       connection = create_sw_toe_connection(qid, ipver, iph, tcp_hdr);
14135 +       connection->hash_entry_index = (__u16) hash_entry_index;
14136 +
14137 +       fill_toeq_buf(qid, toe);
14138 +       memcpy(&connection->l2_hdr, l2hdr, sizeof(struct ethhdr));
14139 +       spin_lock_init(&connection->conn_lock);
14140 +
14141 +       return connection;
14142 +}
14143 +
14144 +#if 0
14145 +/*----------------------------------------------------------------------
14146 +*   toe_init_toe_queue
14147 +*   (1) Initialize the TOE Queue Header
14148 +*       Register: TOE_TOE_QUE_HDR_BASE (0x60003000)
14149 +*   (2) Initialize Descriptors of TOE Queues
14150 +*----------------------------------------------------------------------*/
14151 +void toe_init_toe_queue(TOE_INFO_T* toe)
14152 +{
14153 +}
14154 +EXPORT_SYMBOL(toe_init_toe_queue);
14155 +#endif
14156 +
14157 +/*---------------------------------------------------------------------------
14158 + * dump_jumbo_skb
14159 + *-------------------------------------------------------------------------*/
14160 +void dump_jumbo_skb(struct jumbo_frame *jumbo_skb)
14161 +{
14162 +       if (jumbo_skb->skb0) {
14163 +//             printk("%s. jumbo skb %x, len %d\n",
14164 +//                     __func__, jumbo_skb->skb0->data, jumbo_skb->skb0->len);
14165 +               netif_rx(jumbo_skb->skb0);
14166 +       }
14167 +       jumbo_skb->skb0 = 0;
14168 +       jumbo_skb->tail = 0;
14169 +       jumbo_skb->iphdr0 = 0;
14170 +       jumbo_skb->tcphdr0 = 0;
14171 +}
14172 +
14173 +/* ---------------------------------------------------------------------
14174 + * Append skb to skb0. skb0 is the jumbo frame that will be passed to
14175 + * kernel tcp.
14176 + * --------------------------------------------------------------------*/
14177 +void rx_append_skb(struct jumbo_frame *jumbo_skb, struct sk_buff* skb, int payload_len)
14178 +{
14179 +       struct iphdr* iphdr0 = (struct iphdr*)&(skb->data[0]);
14180 +       int ip_hdrlen = iphdr0->ihl << 2;
14181 +       struct tcphdr* tcphdr0 = (struct tcphdr*)&(skb->data[ip_hdrlen]);
14182 +
14183 +       if (!jumbo_skb->skb0) {
14184 +               // head of the jumbo frame.
14185 +               jumbo_skb->skb0 = skb;
14186 +               jumbo_skb->tail = 0;
14187 +               jumbo_skb->iphdr0 = iphdr0;
14188 +               jumbo_skb->tcphdr0 = tcphdr0;
14189 +       } else {
14190 +               if (!jumbo_skb->tail)
14191 +                       skb_shinfo(jumbo_skb->skb0)->frag_list = skb;
14192 +               else
14193 +                       (jumbo_skb->tail)->next = skb;
14194 +               jumbo_skb->tail = skb;
14195 +
14196 +               // do we need to change truesize as well?
14197 +               jumbo_skb->skb0->len += payload_len;
14198 +               jumbo_skb->skb0->data_len += payload_len;
14199 +
14200 +               jumbo_skb->iphdr0->tot_len = htons(ntohs(jumbo_skb->iphdr0->tot_len)+payload_len);
14201 +               jumbo_skb->tcphdr0->ack_seq = tcphdr0->ack_seq;
14202 +               jumbo_skb->tcphdr0->window = tcphdr0->window;
14203 +
14204 +               skb->len += payload_len;
14205 +               skb->data_len = 0;
14206 +               skb->data += ntohs(iphdr0->tot_len) - payload_len;
14207 +       }
14208 +}
14209 +
14210 +/*----------------------------------------------------------------------
14211 +* toe_gmac_handle_toeq
14212 +* (1) read interrupt Queue to get TOE Q.
14213 +* (2) get packet fro TOE Q and send to upper layer handler.
14214 +* (3) allocate new buffers and put to TOE Q. Intr Q buffer is recycled.
14215 +*----------------------------------------------------------------------*/
14216 +void toe_gmac_handle_toeq(struct net_device *dev, GMAC_INFO_T* tp, __u32 status)
14217 +{
14218 +       //volatile INTRQ_INFO_T *intrq_info;
14219 +       //TOEQ_INFO_T           *toeq_info;
14220 +       volatile NONTOE_QHDR_T  *intr_qhdr;
14221 +       volatile TOE_QHDR_T             *toe_qhdr;
14222 +       volatile INTR_QHDR_T    *intr_curr_desc;
14223 +       TOE_INFO_T      *toe = &toe_private_data;
14224 +
14225 +       volatile GMAC_RXDESC_T  *toe_curr_desc; // , *fq_desc;// *tmp_desc;
14226 +       volatile DMA_RWPTR_T    intr_rwptr, toeq_rwptr;  // fq_rwptr;
14227 +
14228 +       unsigned int    pkt_size, desc_count, tcp_qid;
14229 +       volatile unsigned int   toeq_wptr;
14230 +       struct toe_conn*                connection;
14231 +       int             i, frag_id = 0;
14232 +       // unsigned long        toeq_flags;
14233 +       struct jumbo_frame      jumbo_skb;
14234 +       struct sk_buff  *skb;
14235 +       __u32   interrupt_status;
14236 +
14237 +       in_toe_isr++;
14238 +
14239 +       interrupt_status = status >> 24;
14240 +       // get interrupt queue header
14241 +       intr_qhdr = (volatile NONTOE_QHDR_T*)TOE_INTR_Q_HDR_BASE;
14242 +       memset(&jumbo_skb, 0, sizeof(struct jumbo_frame));
14243 +
14244 +       for (i=0; i<TOE_INTR_QUEUE_NUM; i++, intr_qhdr++) {
14245 +               if (!(interrupt_status & 0x0001)) {
14246 +                       // no interrupt of this IntQ
14247 +                       interrupt_status = interrupt_status >> 1;
14248 +                       continue;
14249 +               }
14250 +               interrupt_status = interrupt_status >> 1;
14251 +               intr_rwptr.bits32 = readl(&intr_qhdr->word1);
14252 +
14253 +               while ( intr_rwptr.bits.rptr != intr_rwptr.bits.wptr) {
14254 +                       int max_pktsize = 1;
14255 +                       // get interrupt queue descriptor.
14256 +                       intr_curr_desc = (INTR_QHDR_T*)toe->intr_desc_base +
14257 +                               i* TOE_INTR_DESC_NUM + intr_rwptr.bits.rptr;
14258 +//                     printk("%s::int %x\n", __func__, intr_curr_desc->word1.bits32);
14259 +                       // get toeq id
14260 +                       tcp_qid = (u8)intr_curr_desc->word1.bits.tcp_qid - (u8)TOE_TOE_QID(0);
14261 +                       // get toeq queue header
14262 +                       toe_qhdr = (volatile TOE_QHDR_T*) TOE_TOE_QUE_HDR_BASE;
14263 +                       toe_qhdr += tcp_qid;
14264 +                       connection = &toe_connections[tcp_qid];
14265 +                       del_timer(&connection->rx_timer);
14266 +                       // Gary Chen spin_lock_irqsave(&connection->conn_lock, toeq_flags);
14267 +                       // handling interrupts of this TOE Q.
14268 +                       if (intr_curr_desc->word1.bits.ctl || intr_curr_desc->word1.bits.osq ||
14269 +                               intr_curr_desc->word1.bits.abn)
14270 +                               max_pktsize = 0;
14271 +                       if (!max_pktsize || intr_curr_desc->word1.bits.TotalPktSize) {
14272 +                               desc_count=0;
14273 +                               // wptr in intl queue is where this TOE interrupt should stop.
14274 +                               toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
14275 +                               toeq_wptr = intr_curr_desc->word0.bits.wptr;
14276 +                               if (connection->toeq_rwptr.bits.rptr != toeq_rwptr.bits.rptr)
14277 +                                       printk("conn rptr %d, hw rptr %d\n",
14278 +                                               connection->toeq_rwptr.bits.rptr, toeq_rwptr.bits.rptr);
14279 +
14280 +                               if (intr_curr_desc->word1.bits.ctl &&
14281 +                                       (toeq_rwptr.bits.rptr == toeq_wptr)) {
14282 +                                       printk("\nctrl frame, but not in TOE queue! conn rptr %d, hw wptr %d\n",
14283 +                                               connection->toeq_rwptr.bits.rptr, toeq_wptr);
14284 +//                                     dump_toe_qhdr(toe_qhdr);
14285 +//                                     dump_intrq_desc(intr_curr_desc);
14286 +                               }
14287 +                               // while (toeq_rwptr.bits.rptr != intr_curr_desc->word0.bits.wptr) {
14288 +                               while (toe_qhdr->word1.bits.rptr != intr_curr_desc->word0.bits.wptr) {
14289 +                                       frag_id++;
14290 +                                       toe_curr_desc = (volatile GMAC_RXDESC_T *)(toe->toe_desc_base[tcp_qid]
14291 +                                               + toe_qhdr->word1.bits.rptr *sizeof(GMAC_RXDESC_T));
14292 +                                       connection->curr_desc = (GMAC_RXDESC_T *)toe_curr_desc;
14293 +                                       desc_count = toe_curr_desc->word0.bits.desc_count;
14294 +                                       pkt_size = toe_curr_desc->word1.bits.byte_count;
14295 +                                       consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
14296 +                                               PCI_DMA_FROMDEVICE);
14297 +                                       skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr)-
14298 +                                               SKB_RESERVE_BYTES));
14299 +                                       _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x01);
14300 +                                       connection->curr_rx_skb = skb;
14301 +                                       skb_reserve(skb, RX_INSERT_BYTES);
14302 +                                       if ((skb->len + pkt_size) > (1514+16))
14303 +                                       {
14304 +                                               printk("skb->len=%d, pkt_size=%d\n",skb->len, pkt_size);
14305 +                                               while(1);
14306 +                                       }
14307 +
14308 +                                       skb_put(skb, pkt_size);
14309 +                                       skb->dev = dev;
14310 +                                       skb->protocol = eth_type_trans(skb, dev);
14311 +                                       skb->ip_summed = CHECKSUM_UNNECESSARY;
14312 +
14313 +                                       if (toe_curr_desc->word3.bits32 & 0x1b000000)
14314 +                                               dump_jumbo_skb(&jumbo_skb);
14315 +
14316 +                                       rx_append_skb(&jumbo_skb, skb, pkt_size-toe_curr_desc->word3.bits.l7_offset);
14317 +//                                     spin_lock_irqsave(&gmac_fq_lock, flags);
14318 +                                       toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
14319 +                                       SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
14320 +//                                     spin_unlock_irqrestore(&gmac_fq_lock, flags);
14321 +                                       if (storlink_ctl.fqint_threshold)
14322 +                                               continue;
14323 +#if 0
14324 +//#if (HANDLE_FREEQ_METHOD == HANDLE_FREEQ_INDIVIDUAL)
14325 +                                       if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
14326 +                                               printk("%s::toe queue alloc buffer ", __func__);
14327 +                                       }
14328 +                                       *(unsigned int*)(skb->data) = (unsigned int)skb;
14329 +                                       connection->curr_rx_skb = skb;
14330 +                                       skb_reserve(skb, SKB_RESERVE_BYTES);
14331 +
14332 +                                       spin_lock_irqsave(&gmac_fq_lock, flags);
14333 +                                       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
14334 +                                       if (toe->fq_rx_rwptr.bits.wptr != fq_rwptr.bits.wptr) {
14335 +                                               printk("%s::fq_rx_rwptr %x\n", __func__, toe->fq_rx_rwptr.bits32);
14336 +                                               mac_stop_txdma((struct net_device*) tp->dev);
14337 +                                               spin_unlock_irqrestore(&gmac_fq_lock, flags);
14338 +                                               while(1);
14339 +                                       }
14340 +                                       fq_desc = (GMAC_RXDESC_T*)toe->swfq_desc_base + fq_rwptr.bits.wptr;
14341 +                                       fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
14342 +
14343 +                                       fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
14344 +                                       SET_WPTR(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
14345 +                                       toe->fq_rx_rwptr.bits32 = fq_rwptr.bits32;
14346 +                                       spin_unlock_irqrestore(&gmac_fq_lock, flags);
14347 +#endif
14348 +                               } // end of this multi-desc.
14349 +                               dump_jumbo_skb(&jumbo_skb);
14350 +                               dev->last_rx = jiffies;
14351 +                               connection->toeq_rwptr.bits32 = toeq_rwptr.bits32;
14352 +                       } else if (intr_curr_desc->word1.bits.sat) {
14353 +                               toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
14354 +                               toeq_wptr = intr_curr_desc->word0.bits.wptr;
14355 +                               if (connection->toeq_rwptr.bits.rptr != toeq_rwptr.bits.rptr)
14356 +                                       printk("SAT. conn rptr %d, hw rptr %d\n",
14357 +                                               connection->toeq_rwptr.bits.rptr, toeq_rwptr.bits.rptr);
14358 +/*
14359 +                                       printk("%s::SAT int!, ackcnt %x, seqcnt %x, rptr %d, wptr %d, ack %x, qhack %x\n",
14360 +                                               __func__, intr_curr_desc->word4.bits.AckCnt, intr_curr_desc->word4.bits.SeqCnt,
14361 +                                               toeq_rptr, toeq_wptr, intr_curr_desc->word3.ack_num, toe_qhdr->word4.ack_num);*/
14362 +                               /* pure ack */
14363 +                               if (toeq_rwptr.bits.rptr == toeq_wptr) {
14364 +                                       if (intr_curr_desc->word4.bits32) {
14365 +                                               skb = gen_pure_ack(connection, (TOE_QHDR_T *)toe_qhdr, (INTR_QHDR_T *)intr_curr_desc);
14366 +                                               skb_put(skb, 60);
14367 +                                               skb->dev = connection->dev;
14368 +                                               skb->ip_summed = CHECKSUM_UNNECESSARY;
14369 +                                               skb->protocol = eth_type_trans(skb, connection->dev);
14370 +                                               netif_rx(skb);
14371 +                                       } else
14372 +                                               printk("%s::SAT Interrupt!. But cnt is 0!\n", __func__);
14373 +                               } else {
14374 +                                       // while (toeq_rwptr.bits.rptr != toeq_wptr) {
14375 +                                       while (toe_qhdr->word1.bits.rptr != intr_curr_desc->word0.bits.wptr) {
14376 +                                               toe_curr_desc = (volatile GMAC_RXDESC_T*)(toe->toe_desc_base[tcp_qid]
14377 +                                                       + toe_qhdr->word1.bits.rptr * sizeof(GMAC_RXDESC_T));
14378 +                                               connection->curr_desc = (GMAC_RXDESC_T *)toe_curr_desc;
14379 +                                               desc_count = toe_curr_desc->word0.bits.desc_count;
14380 +                                               pkt_size = toe_curr_desc->word1.bits.byte_count;
14381 +                                               consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
14382 +                                                       PCI_DMA_FROMDEVICE);
14383 +                                               // if ( ((toeq_rwptr.bits.rptr +1)&(TOE_TOE_DESC_NUM-1)) == toeq_wptr) {
14384 +                                               if ( RWPTR_ADVANCE_ONE(toe_qhdr->word1.bits.rptr, TOE_TOE_DESC_NUM) == toeq_wptr) {
14385 +                                                       skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr) -
14386 +                                                               SKB_RESERVE_BYTES));
14387 +                                                       _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x04);
14388 +                                                       connection->curr_rx_skb = skb;
14389 +                                                       skb_reserve(skb, RX_INSERT_BYTES);
14390 +                                                       skb_put(skb, pkt_size);
14391 +                                                       skb->dev = dev;
14392 +                                                       skb->protocol = eth_type_trans(skb, dev);
14393 +                                                       skb->ip_summed = CHECKSUM_UNNECESSARY;
14394 +                                                       // printk("toeq_rptr %d, wptr %d\n", toeq_rptr, toeq_wptr);
14395 +                                                       netif_rx(skb);
14396 +                                                       dev->last_rx = jiffies;
14397 +/*
14398 +                                                       if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
14399 +
14400 +                                                       }
14401 +                                                       *(unsigned int*)(skb->data) = (unsigned int) skb;
14402 +                                                       skb_reserve(skb, SKB_RESERVE_BYTES); */
14403 +                                               } else {
14404 +                                                       // reuse this skb, append to free queue..
14405 +                                                       skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr)-
14406 +                                                               SKB_RESERVE_BYTES));
14407 +                                                       _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x05);
14408 +                                                       connection->curr_rx_skb = skb;
14409 +                                                       dev_kfree_skb_irq(skb);
14410 +                                               }
14411 +#if 0
14412 +                                               spin_lock_irqsave(&gmac_fq_lock, flags);
14413 +                                               fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
14414 +/*                                             if (toe->fq_rx_rwptr.bits.wptr != fq_rwptr.bits.wptr) {
14415 +                                                       printk("%s::fq_rx_rwptr %x\n", __func__, toe->fq_rx_rwptr.bits32);
14416 +                                                       mac_stop_txdma((struct net_device*) tp->dev);
14417 +                                                       spin_unlock_irqrestore(&gmac_fq_lock, flags);
14418 +                                                       while(1);
14419 +                                               } */
14420 +                                               fq_desc = (GMAC_RXDESC_T*)toe->swfq_desc_base + fq_rwptr.bits.wptr;
14421 +                                               fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
14422 +
14423 +                                               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
14424 +                                               SET_WPTR(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
14425 +                                               toe->fq_rx_rwptr.bits32 = fq_rwptr.bits32;
14426 +       //                                      spin_unlock_irqrestore(&gmac_fq_lock, flags);
14427 +#endif
14428 +//                                             spin_lock_irqsave(&gmac_fq_lock, flags);
14429 +                                               toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
14430 +                                               SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
14431 +//                                             spin_unlock_irqrestore(&gmac_fq_lock, flags);
14432 +                                       }
14433 +                               } // end of ACK with options.
14434 +                               connection->toeq_rwptr.bits32 = toeq_rwptr.bits32;
14435 +                               // Gary Chen spin_unlock_irqrestore(&connection->conn_lock, toeq_flags);
14436 +//                             }
14437 +                       };
14438 +                       update_timer(connection);
14439 +                       // any protection against interrupt queue header?
14440 +                       intr_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(intr_rwptr.bits.rptr, TOE_INTR_DESC_NUM);
14441 +                       SET_RPTR(&intr_qhdr->word1, intr_rwptr.bits.rptr);
14442 +                       intr_rwptr.bits32 = readl(&intr_qhdr->word1);
14443 +                       toe_gmac_fill_free_q();
14444 +               } // end of this interrupt Queue processing.
14445 +       } // end of all interrupt Queues.
14446 +
14447 +       in_toe_isr = 0;
14448 +}
14449 +
14450 +
14451 --- /dev/null
14452 +++ b/drivers/net/sl_lepus_hash.c
14453 @@ -0,0 +1,553 @@
14454 +/**************************************************************************
14455 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
14456 +*--------------------------------------------------------------------------
14457 +* Name                 : sl_lepus_hash.c
14458 +* Description  :
14459 +*              Handle Storlink Lepus Hash Functions
14460 +*
14461 +* History
14462 +*
14463 +*      Date            Writer          Description
14464 +*----------------------------------------------------------------------------
14465 +*      03/13/2006      Gary Chen       Create and implement
14466 +*
14467 +****************************************************************************/
14468 +#include <linux/module.h>
14469 +#include <linux/kernel.h>
14470 +#include <linux/compiler.h>
14471 +#include <linux/pci.h>
14472 +#include <linux/init.h>
14473 +#include <linux/ioport.h>
14474 +#include <linux/netdevice.h>
14475 +#include <linux/etherdevice.h>
14476 +#include <linux/rtnetlink.h>
14477 +#include <linux/delay.h>
14478 +#include <linux/ethtool.h>
14479 +#include <linux/mii.h>
14480 +#include <linux/completion.h>
14481 +#include <asm/hardware.h>
14482 +#include <asm/io.h>
14483 +#include <asm/irq.h>
14484 +#include <asm/semaphore.h>
14485 +#include <asm/arch/irqs.h>
14486 +#include <asm/arch/it8712.h>
14487 +#include <linux/mtd/kvctl.h>
14488 +#include <linux/skbuff.h>
14489 +#include <linux/ip.h>
14490 +#include <linux/tcp.h>
14491 +#include <linux/list.h>
14492 +#define         MIDWAY
14493 +#define         SL_LEPUS
14494 +
14495 +#include <asm/arch/sl2312.h>
14496 +#include <asm/arch/sl_lepus_gmac.h>
14497 +#include <asm/arch/sl_hash_cfg.h>
14498 +
14499 +#ifndef RXTOE_DEBUG
14500 +#define RXTOE_DEBUG
14501 +#endif
14502 +#undef RXTOE_DEBUG
14503 +
14504 +/*----------------------------------------------------------------------
14505 +* Definition
14506 +*----------------------------------------------------------------------*/
14507 +#define        hash_printf                             printk
14508 +
14509 +#define HASH_TIMER_PERIOD              (60*HZ) // seconds
14510 +#define HASH_ILLEGAL_INDEX             0xffff
14511 +
14512 +/*----------------------------------------------------------------------
14513 +* Variables
14514 +*----------------------------------------------------------------------*/
14515 +u32                                    hash_activate_bits[HASH_TOTAL_ENTRIES/32];
14516 +u32                                    hash_nat_owner_bits[HASH_TOTAL_ENTRIES/32];
14517 +char                           hash_tables[HASH_TOTAL_ENTRIES][HASH_MAX_BYTES] __attribute__ ((aligned(16)));
14518 +static struct timer_list hash_timer_obj;
14519 +LIST_HEAD(hash_timeout_list);
14520 +
14521 +/*----------------------------------------------------------------------
14522 +* Functions
14523 +*----------------------------------------------------------------------*/
14524 +void dm_long(u32 location, int length);
14525 +static void hash_timer_func(u32 data);
14526 +
14527 +/*----------------------------------------------------------------------
14528 +* hash_init
14529 +*----------------------------------------------------------------------*/
14530 +void hash_init(void)
14531 +{
14532 +       int i;
14533 +       volatile u32 *dp1, *dp2, dword;
14534 +
14535 +       dp1 = (volatile u32 *) TOE_V_BIT_BASE;
14536 +       dp2 = (volatile u32 *) TOE_A_BIT_BASE;
14537 +
14538 +       for (i=0; i<HASH_TOTAL_ENTRIES/32; i++)
14539 +       {
14540 +               *dp1++ = 0;
14541 +               dword = *dp2++; // read-clear
14542 +       }
14543 +       memset((void *)&hash_nat_owner_bits, 0, sizeof(hash_nat_owner_bits));
14544 +       memset((void *)&hash_tables, 0, sizeof(hash_tables));
14545 +
14546 +       init_timer(&hash_timer_obj);
14547 +       hash_timer_obj.expires = jiffies + HASH_TIMER_PERIOD;
14548 +       hash_timer_obj.data = (unsigned long)&hash_timer_obj;
14549 +       hash_timer_obj.function = (void *)&hash_timer_func;
14550 +       add_timer(&hash_timer_obj);
14551 +
14552 +#if (HASH_MAX_BYTES == 128)
14553 +       writel((unsigned long)__pa(&hash_tables) | 3,   // 32 words
14554 +                       TOE_GLOBAL_BASE + GLOBAL_HASH_TABLE_BASE_REG);
14555 +#elif (HASH_MAX_BYTES == 64)
14556 +       writel((unsigned long)__pa(&hash_tables) | 2,   // 16 words
14557 +                       TOE_GLOBAL_BASE + GLOBAL_HASH_TABLE_BASE_REG);
14558 +#else
14559 +       #error Incorrect setting for HASH_MAX_BYTES
14560 +#endif
14561 +
14562 +}
14563 +/*----------------------------------------------------------------------
14564 +* hash_add_entry
14565 +*----------------------------------------------------------------------*/
14566 +int hash_add_entry(HASH_ENTRY_T *entry)
14567 +{
14568 +       int     rc;
14569 +       u32     key[HASH_MAX_DWORDS];
14570 +       rc = hash_build_keys((u32 *)&key, entry);
14571 +       if (rc < 0)
14572 +               return -1;
14573 +       hash_write_entry(entry, (unsigned char*) &key[0]);
14574 +//     hash_set_valid_flag(entry->index, 1);
14575 +//     printk("Dump hash key!\n");
14576 +//     dump_hash_key(entry);
14577 +       return entry->index;
14578 +}
14579 +
14580 +/*----------------------------------------------------------------------
14581 +* hash_set_valid_flag
14582 +*----------------------------------------------------------------------*/
14583 +void hash_set_valid_flag(int index, int valid)
14584 +{
14585 +       register u32 reg32;
14586 +
14587 +       reg32 = TOE_V_BIT_BASE + (index/32) * 4;
14588 +
14589 +       if (valid)
14590 +       {
14591 +               writel(readl(reg32) | (1 << (index%32)), reg32);
14592 +       }
14593 +       else
14594 +       {
14595 +               writel(readl(reg32) & ~(1 << (index%32)), reg32);
14596 +       }
14597 +}
14598 +
14599 +/*----------------------------------------------------------------------
14600 +* hash_set_nat_owner_flag
14601 +*----------------------------------------------------------------------*/
14602 +void hash_set_nat_owner_flag(int index, int valid)
14603 +{
14604 +       if (valid)
14605 +       {
14606 +               hash_nat_owner_bits[index/32] |= (1 << (index % 32));
14607 +       }
14608 +       else
14609 +       {
14610 +               hash_nat_owner_bits[index/32] &= ~(1 << (index % 32));
14611 +       }
14612 +}
14613 +
14614 +
14615 +/*----------------------------------------------------------------------
14616 +* hash_build_keys
14617 +*----------------------------------------------------------------------*/
14618 +int hash_build_keys(u32 *destp, HASH_ENTRY_T *entry)
14619 +{
14620 +       u32     data;
14621 +       unsigned char   *cp;
14622 +       int                             i, j;
14623 +       unsigned short  index;
14624 +       int                     total;
14625 +
14626 +       memset((void *)destp, 0, HASH_MAX_BYTES);
14627 +       cp = (unsigned char *)destp;
14628 +
14629 +       if (entry->key_present.port || entry->key_present.Ethertype)
14630 +       {
14631 +               HASH_PUSH_WORD(cp, entry->key.Ethertype);               // word 0
14632 +               HASH_PUSH_BYTE(cp, entry->key.port);                    // Byte 2
14633 +               HASH_PUSH_BYTE(cp, 0);                                                  // Byte 3
14634 +       }
14635 +       else
14636 +       {
14637 +               HASH_PUSH_DWORD(cp, 0);
14638 +       }
14639 +
14640 +       if (entry->key_present.da || entry->key_present.sa)
14641 +       {
14642 +               unsigned char mac[4];
14643 +               if (entry->key_present.da)
14644 +               {
14645 +                       for (i=0; i<4; i++)
14646 +                               HASH_PUSH_BYTE(cp, entry->key.da[i]);
14647 +               }
14648 +               mac[0] = (entry->key_present.da) ? entry->key.da[4] : 0;
14649 +               mac[1] = (entry->key_present.da) ? entry->key.da[5] : 0;
14650 +               mac[2] = (entry->key_present.sa) ? entry->key.sa[0] : 0;
14651 +               mac[3] = (entry->key_present.sa) ? entry->key.sa[1] : 0;
14652 +               data = mac[0] + (mac[1]<<8) + (mac[2]<<16) + (mac[3]<<24);
14653 +               HASH_PUSH_DWORD(cp, data);
14654 +               if (entry->key_present.sa)
14655 +               {
14656 +                       for (i=2; i<6; i++)
14657 +                               HASH_PUSH_BYTE(cp, entry->key.sa[i]);
14658 +               }
14659 +       }
14660 +
14661 +       if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
14662 +       {
14663 +               HASH_PUSH_WORD(cp, entry->key.vlan_id);         // low word
14664 +               HASH_PUSH_WORD(cp, entry->key.pppoe_sid);       // high word
14665 +       }
14666 +       if (entry->key_present.ipv4_hdrlen || entry->key_present.ip_tos || entry->key_present.ip_protocol)
14667 +       {
14668 +               HASH_PUSH_BYTE(cp, entry->key.ip_protocol);             // Byte 0
14669 +               HASH_PUSH_BYTE(cp, entry->key.ip_tos);                  // Byte 1
14670 +               HASH_PUSH_BYTE(cp, entry->key.ipv4_hdrlen);             // Byte 2
14671 +               HASH_PUSH_BYTE(cp, 0);                                                  // Byte 3
14672 +       }
14673 +
14674 +       if (entry->key_present.ipv6_flow_label)
14675 +       {
14676 +               HASH_PUSH_DWORD(cp, entry->key.ipv6_flow_label);        // low word
14677 +       }
14678 +       if (entry->key_present.sip)
14679 +       {
14680 +               // input (entry->key.sip[i]) is network-oriented
14681 +               // output (hash key) is host-oriented
14682 +               for (i=3; i>=0; i--)
14683 +                       HASH_PUSH_BYTE(cp, entry->key.sip[i]);
14684 +               if (entry->key.ipv6)
14685 +               {
14686 +                       for (i=4; i<16; i+=4)
14687 +                       {
14688 +                               for (j=i+3; j>=i; j--)
14689 +                                       HASH_PUSH_BYTE(cp, entry->key.sip[j]);
14690 +                       }
14691 +               }
14692 +       }
14693 +       if (entry->key_present.dip)
14694 +       {
14695 +               // input (entry->key.sip[i]) is network-oriented
14696 +               // output (hash key) is host-oriented
14697 +               for (i=3; i>=0; i--)
14698 +                       HASH_PUSH_BYTE(cp, entry->key.dip[i]);
14699 +               if (entry->key.ipv6)
14700 +               {
14701 +                       for (i=4; i<16; i+=4)
14702 +                       {
14703 +                               for (j=i+3; j>=i; j--)
14704 +                                       HASH_PUSH_BYTE(cp, entry->key.dip[j]);
14705 +                       }
14706 +               }
14707 +       }
14708 +
14709 +       if (entry->key_present.l4_bytes_0_3)
14710 +       {
14711 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
14712 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
14713 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
14714 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
14715 +       }
14716 +       if (entry->key_present.l4_bytes_4_7)
14717 +       {
14718 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[4]);
14719 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[5]);
14720 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[6]);
14721 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[7]);
14722 +       }
14723 +       if (entry->key_present.l4_bytes_8_11)
14724 +       {
14725 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[8]);
14726 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[9]);
14727 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[10]);
14728 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[11]);
14729 +       }
14730 +       if (entry->key_present.l4_bytes_12_15)
14731 +       {
14732 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[12]);
14733 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[13]);
14734 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[14]);
14735 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[15]);
14736 +       }
14737 +       if (entry->key_present.l4_bytes_16_19)
14738 +       {
14739 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[16]);
14740 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[17]);
14741 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[18]);
14742 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[19]);
14743 +       }
14744 +       if (entry->key_present.l4_bytes_20_23)
14745 +       {
14746 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[20]);
14747 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[21]);
14748 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[22]);
14749 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[23]);
14750 +       }
14751 +       if (entry->key_present.l7_bytes_0_3)
14752 +       {
14753 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[0]);
14754 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[1]);
14755 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[2]);
14756 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[3]);
14757 +       }
14758 +       if (entry->key_present.l7_bytes_4_7)
14759 +       {
14760 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[4]);
14761 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[5]);
14762 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[6]);
14763 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[7]);
14764 +       }
14765 +       if (entry->key_present.l7_bytes_8_11)
14766 +       {
14767 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[8]);
14768 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[9]);
14769 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[10]);
14770 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[11]);
14771 +       }
14772 +       if (entry->key_present.l7_bytes_12_15)
14773 +       {
14774 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[12]);
14775 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[13]);
14776 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[14]);
14777 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[15]);
14778 +       }
14779 +       if (entry->key_present.l7_bytes_16_19)
14780 +       {
14781 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[16]);
14782 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[17]);
14783 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[18]);
14784 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[19]);
14785 +       }
14786 +       if (entry->key_present.l7_bytes_20_23)
14787 +       {
14788 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[20]);
14789 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[21]);
14790 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[22]);
14791 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[23]);
14792 +       }
14793 +
14794 +       // get hash index
14795 +       total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
14796 +
14797 +       if (total > HASH_MAX_KEY_DWORD)
14798 +       {
14799 +               //hash_printf("Total key words (%d) is too large (> %d)!\n",
14800 +               //                              total, HASH_MAX_KEY_DWORD);
14801 +               return -1;
14802 +       }
14803 +
14804 +       if (entry->key_present.port || entry->key_present.Ethertype)
14805 +               index = hash_gen_crc16((unsigned char *)destp, total * 4);
14806 +       else
14807 +       {
14808 +               if (total == 1)
14809 +               {
14810 +                       hash_printf("No key is assigned!\n");
14811 +                       return -1;
14812 +               }
14813 +
14814 +               index = hash_gen_crc16((unsigned char *)(destp+1), (total-1) * 4);
14815 +       }
14816 +
14817 +       entry->index = index & HASH_BITS_MASK;
14818 +
14819 +       //hash_printf("Total key words = %d, Hash Index= %d\n",
14820 +       //                              total, entry->index);
14821 +
14822 +       cp = (unsigned char *)destp;
14823 +       cp+=3;
14824 +       HASH_PUSH_BYTE(cp, entry->rule);        // rule
14825 +
14826 +       entry->total_dwords = total;
14827 +
14828 +       return total;
14829 +}
14830 +
14831 +/*----------------------------------------------------------------------
14832 +* hash_build_nat_keys
14833 +*----------------------------------------------------------------------*/
14834 +void hash_build_nat_keys(u32 *destp, HASH_ENTRY_T *entry)
14835 +{
14836 +       unsigned char   *cp;
14837 +       int                             i;
14838 +       unsigned short  index;
14839 +       int                     total;
14840 +
14841 +       memset((void *)destp, 0, HASH_MAX_BYTES);
14842 +
14843 +       cp = (unsigned char *)destp + 2;
14844 +       HASH_PUSH_BYTE(cp, entry->key.port);
14845 +       cp++;
14846 +
14847 +       if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
14848 +       {
14849 +               HASH_PUSH_WORD(cp, entry->key.vlan_id);         // low word
14850 +               HASH_PUSH_WORD(cp, entry->key.pppoe_sid);       // high word
14851 +       }
14852 +
14853 +       HASH_PUSH_BYTE(cp, entry->key.ip_protocol);
14854 +       cp+=3;
14855 +
14856 +       // input (entry->key.sip[i]) is network-oriented
14857 +       // output (hash key) is host-oriented
14858 +       for (i=3; i>=0; i--)
14859 +               HASH_PUSH_BYTE(cp, entry->key.sip[i]);
14860 +
14861 +       // input (entry->key.sip[i]) is network-oriented
14862 +       // output (hash key) is host-oriented
14863 +       for (i=3; i>=0; i--)
14864 +               HASH_PUSH_BYTE(cp, entry->key.dip[i]);
14865 +
14866 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
14867 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
14868 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
14869 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
14870 +
14871 +       // get hash index
14872 +       total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
14873 +
14874 +       index = hash_gen_crc16((unsigned char *)destp, total * 4);
14875 +       entry->index = index & ((1 << HASH_BITS) - 1);
14876 +
14877 +       cp = (unsigned char *)destp;
14878 +       cp+=3;
14879 +       HASH_PUSH_BYTE(cp, entry->rule);        // rule
14880 +
14881 +       entry->total_dwords = total;
14882 +}
14883 +
14884 +
14885 +/*----------------------------------------------------------------------
14886 +* hash_write_entry
14887 +*----------------------------------------------------------------------*/
14888 +int hash_write_entry(HASH_ENTRY_T *entry, unsigned char *key)
14889 +{
14890 +       int             i;
14891 +       u32             *srcep, *destp, *destp2;
14892 +
14893 +       srcep = (u32 *)key;
14894 +       destp2 = destp = (u32 *)&hash_tables[entry->index][0];
14895 +
14896 +       for (i=0; i<(entry->total_dwords); i++, srcep++, destp++)
14897 +               *destp = *srcep;
14898 +
14899 +       srcep = (u32 *)&entry->action;
14900 +       *destp++ = *srcep;
14901 +
14902 +       srcep = (u32 *)&entry->param;
14903 +       for (i=0; i<(sizeof(ENTRY_PARAM_T)/sizeof(*destp)); i++, srcep++, destp++)
14904 +               *destp = *srcep;
14905 +
14906 +       memset(destp, 0, (HASH_MAX_DWORDS-entry->total_dwords-HASH_ACTION_DWORDS) * sizeof(u32));
14907 +
14908 +       consistent_sync(destp2, (entry->total_dwords+HASH_ACTION_DWORDS) * 4, PCI_DMA_TODEVICE);
14909 +       return 0;
14910 +}
14911 +
14912 +/*----------------------------------------------------------------------
14913 +* hash_timer_func
14914 +*----------------------------------------------------------------------*/
14915 +static void hash_timer_func(u32 data)
14916 +{
14917 +       int                             i, j;
14918 +       volatile u32    *active_p, *own_p, *valid_p;
14919 +       u32                             a_bits, own_bits;
14920 +
14921 +       valid_p = (volatile u32 *)TOE_V_BIT_BASE;
14922 +       active_p = (volatile u32 *)hash_activate_bits;
14923 +       own_p = (volatile u32 *)hash_nat_owner_bits;
14924 +       for (i=0; i<(HASH_TOTAL_ENTRIES/32); i++, own_p++, active_p++, valid_p++)
14925 +       {
14926 +               *active_p |= readl(TOE_A_BIT_BASE + (i*4));
14927 +               a_bits = *active_p;
14928 +               own_bits = *own_p;
14929 +               if (own_bits)
14930 +               {
14931 +#ifndef DEBUG_NAT_MIXED_HW_SW_TX
14932 +                       a_bits = own_bits & ~a_bits;
14933 +#else
14934 +                       a_bits = own_bits & a_bits;
14935 +#endif
14936 +                       for (j=0; a_bits && j<32; j++)
14937 +                       {
14938 +                               if (a_bits & 1)
14939 +                               {
14940 +                                       *valid_p &= ~(1 << j);          // invalidate it
14941 +#if !(defined(NAT_DEBUG_LAN_HASH_TIMEOUT) || defined(NAT_DEBUG_WAN_HASH_TIMEOUT))
14942 +                                       *own_p &= ~(1 << j);            // release ownership for NAT
14943 +#endif
14944 +// #ifdef DEBUG_NAT_MIXED_HW_SW_TX
14945 +#if 0
14946 +                                       hash_printf("%lu %s: Clear hash index: %d\n", jiffies/HZ, __func__, i*32+j);
14947 +#endif
14948 +                               }
14949 +                               a_bits >>= 1;
14950 +                       }
14951 +                       *active_p &= ~own_bits;         // deactivate it for next polling
14952 +               }
14953 +       }
14954 +
14955 +       hash_timer_obj.expires = jiffies + HASH_TIMER_PERIOD;
14956 +       add_timer((struct timer_list *)data);
14957 +}
14958 +
14959 +/*----------------------------------------------------------------------
14960 +* dm_long
14961 +*----------------------------------------------------------------------*/
14962 +void dm_long(u32 location, int length)
14963 +{
14964 +       u32             *start_p, *curr_p, *end_p;
14965 +       u32             *datap, data;
14966 +       int             i;
14967 +
14968 +       //if (length > 1024)
14969 +       //      length = 1024;
14970 +
14971 +       start_p = (u32 *)location;
14972 +       end_p = (u32 *)location + length;
14973 +       curr_p = (u32 *)((u32)location & 0xfffffff0);
14974 +       datap = (u32 *)location;
14975 +       while (curr_p < end_p)
14976 +       {
14977 +               hash_printf("0x%08x: ",(u32)curr_p & 0xfffffff0);
14978 +               for (i=0; i<4; i++)
14979 +               {
14980 +                       if (curr_p < start_p || curr_p >= end_p)
14981 +               hash_printf("         ");
14982 +                       else
14983 +                       {
14984 +                               data = *datap;
14985 +                               hash_printf("%08X ", data);
14986 +                       }
14987 +                       if (i==1)
14988 +              hash_printf("- ");
14989 +
14990 +                       curr_p++;
14991 +                       datap++;
14992 +               }
14993 +        hash_printf("\n");
14994 +       }
14995 +}
14996 +
14997 +/*----------------------------------------------------------------------
14998 +* hash_dump_entry
14999 +*----------------------------------------------------------------------*/
15000 +void hash_dump_entry(int index)
15001 +{
15002 +       hash_printf("Hash Index %d:\n", index);
15003 +       dm_long((u32)&hash_tables[index][0], HASH_MAX_DWORDS);
15004 +}
15005 +
15006 +
15007 --- /dev/null
15008 +++ b/drivers/net/sl_switch.c
15009 @@ -0,0 +1,650 @@
15010 +#include <linux/module.h>
15011 +#include <linux/kernel.h>
15012 +#include <linux/init.h>
15013 +#include <linux/ioport.h>
15014 +#include <linux/delay.h>
15015 +#include <asm/hardware.h>
15016 +#include <asm/io.h>
15017 +
15018 +#define GMAC_GLOBAL_BASE_ADDR       (IO_ADDRESS(SL2312_GLOBAL_BASE))
15019 +#define GPIO_BASE_ADDR1  (IO_ADDRESS(SL2312_GPIO_BASE1))
15020 +enum GPIO_REG
15021 +{
15022 +    GPIO_DATA_OUT   = 0x00,
15023 +    GPIO_DATA_IN    = 0x04,
15024 +    GPIO_PIN_DIR    = 0x08,
15025 +    GPIO_BY_PASS    = 0x0c,
15026 +    GPIO_DATA_SET   = 0x10,
15027 +    GPIO_DATA_CLEAR = 0x14,
15028 +};
15029 +
15030 +#define GMAC_SPEED_10                  0
15031 +#define GMAC_SPEED_100                 1
15032 +#define GMAC_SPEED_1000                        2
15033 +
15034 +enum phy_state
15035 +{
15036 +    LINK_DOWN   = 0,
15037 +    LINK_UP     = 1
15038 +};
15039 +
15040 +#ifndef BIT
15041 +#define BIT(x)                                         (1 << (x))
15042 +#endif
15043 +
15044 +//int Get_Set_port_status();
15045 +unsigned int SPI_read_bit(void);
15046 +void SPI_write_bit(char bit_EEDO);
15047 +void SPI_write(unsigned char block,unsigned char subblock,unsigned char addr,unsigned int value);
15048 +unsigned int SPI_read(unsigned char block,unsigned char subblock,unsigned char addr);
15049 +int SPI_default(void);
15050 +void SPI_CS_enable(unsigned char enable);
15051 +unsigned int SPI_get_identifier(void);
15052 +void phy_write(unsigned char port_no,unsigned char reg,unsigned int val);
15053 +unsigned int phy_read(unsigned char port_no,unsigned char reg);
15054 +void phy_write_masked(unsigned char port_no,unsigned char reg,unsigned int val,unsigned int mask);
15055 +void init_seq_7385(unsigned char port_no) ;
15056 +void phy_receiver_init (unsigned char port_no);
15057 +
15058 +#define PORT_NO                4
15059 +int switch_pre_speed[PORT_NO]={0,0,0,0};
15060 +int switch_pre_link[PORT_NO]={0,0,0,0};
15061 +
15062 +
15063 +
15064 +
15065 +
15066 +/*                             NOTES
15067 + *   The Protocol of the SPI are as follows:
15068 + *
15069 + *                        Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
15070 + *     byte0     |   Block id  | r/w | sub-block        |
15071 + *     byte1     |             Address                  |
15072 + *     byte2     |             Data                     |
15073 + *     byte3     |             Data                     |
15074 + *     byte4     |             Data                     |
15075 + *     byte5     |             Data                     |
15076 + */
15077 +
15078 +
15079 +
15080 +
15081 +/***************************************/
15082 +/* define GPIO module base address     */
15083 +/***************************************/
15084 +#define GPIO_EECS           0x80000000         /*   EECS: GPIO[22]   */
15085 +#define GPIO_MOSI           0x20000000         /*   EEDO: GPIO[29]   send to 6996*/
15086 +#define GPIO_MISO           0x40000000         /*   EEDI: GPIO[30]   receive from 6996*/
15087 +#define GPIO_EECK           0x10000000         /*   EECK: GPIO[31]   */
15088 +
15089 +/*************************************************************
15090 +* SPI protocol for ADM6996 control
15091 +**************************************************************/
15092 +#define SPI_OP_LEN          0x08               // the length of start bit and opcode
15093 +#define SPI_OPWRITE         0X05               // write
15094 +#define SPI_OPREAD          0X06               // read
15095 +#define SPI_OPERASE         0X07               // erase
15096 +#define SPI_OPWTEN          0X04               // write enable
15097 +#define SPI_OPWTDIS         0X04               // write disable
15098 +#define SPI_OPERSALL        0X04               // erase all
15099 +#define SPI_OPWTALL         0X04               // write all
15100 +
15101 +#define SPI_ADD_LEN         8                  // bits of Address
15102 +#define SPI_DAT_LEN         32                 // bits of Data
15103 +
15104 +
15105 +/****************************************/
15106 +/*     Function Declare                */
15107 +/****************************************/
15108 +
15109 +//unsigned int SPI_read_bit(void);
15110 +//void SPI_write_bit(char bit_EEDO);
15111 +//unsigned int SPI_read_bit(void);
15112 +/******************************************
15113 +* SPI_write
15114 +* addr -> Write Address
15115 +* value -> value to be write
15116 +***************************************** */
15117 +void phy_receiver_init (unsigned char port_no)
15118 +{
15119 +    phy_write(port_no,31,0x2a30);
15120 +    phy_write_masked(port_no, 12, 0x0200, 0x0300);
15121 +    phy_write(port_no,31,0);
15122 +}
15123 +
15124 +void phy_write(unsigned char port_no,unsigned char reg,unsigned int val)
15125 +{
15126 +       unsigned int cmd;
15127 +
15128 +       cmd = (port_no<<21)|(reg<<16)|val;
15129 +       SPI_write(3,0,1,cmd);
15130 +}
15131 +
15132 +unsigned int phy_read(unsigned char port_no,unsigned char reg)
15133 +{
15134 +       unsigned int cmd,reg_val;
15135 +
15136 +       cmd = BIT(26)|(port_no<<21)|(reg<<16);
15137 +       SPI_write(3,0,1,cmd);
15138 +       msleep(2);
15139 +       reg_val = SPI_read(3,0,2);
15140 +       return reg_val;
15141 +}
15142 +
15143 +void phy_write_masked(unsigned char port_no,unsigned char reg,unsigned int val,unsigned int mask)
15144 +{
15145 +       unsigned int cmd,reg_val;
15146 +
15147 +       cmd = BIT(26)|(port_no<<21)|(reg<<16);  // Read reg_val
15148 +       SPI_write(3,0,1,cmd);
15149 +       mdelay(2);
15150 +       reg_val = SPI_read(3,0,2);
15151 +       reg_val &= ~mask;                       // Clear masked bit
15152 +       reg_val |= (val&mask) ;                 // set masked bit ,if true
15153 +       cmd = (port_no<<21)|(reg<<16)|reg_val;
15154 +       SPI_write(3,0,1,cmd);
15155 +}
15156 +
15157 +void init_seq_7385(unsigned char port_no)
15158 +{
15159 +       unsigned char rev;
15160 +
15161 +       phy_write(port_no, 31, 0x2a30);
15162 +       phy_write_masked(port_no, 8, 0x0200, 0x0200);
15163 +       phy_write(port_no, 31, 0x52b5);
15164 +       phy_write(port_no, 16, 0xb68a);
15165 +       phy_write_masked(port_no, 18, 0x0003, 0xff07);
15166 +       phy_write_masked(port_no, 17, 0x00a2, 0x00ff);
15167 +       phy_write(port_no, 16, 0x968a);
15168 +       phy_write(port_no, 31, 0x2a30);
15169 +       phy_write_masked(port_no, 8, 0x0000, 0x0200);
15170 +       phy_write(port_no, 31, 0x0000); /* Read revision */
15171 +       rev = phy_read(port_no, 3) & 0x000f;
15172 +       if (rev == 0)
15173 +       {
15174 +               phy_write(port_no, 31, 0x2a30);
15175 +               phy_write_masked(port_no, 8, 0x0200, 0x0200);
15176 +               phy_write(port_no, 31, 0x52b5);
15177 +               phy_write(port_no, 18, 0x0000);
15178 +               phy_write(port_no, 17, 0x0689);
15179 +               phy_write(port_no, 16, 0x8f92);
15180 +               phy_write(port_no, 31, 0x52B5);
15181 +               phy_write(port_no, 18, 0x0000);
15182 +               phy_write(port_no, 17, 0x0E35);
15183 +               phy_write(port_no, 16, 0x9786);
15184 +               phy_write(port_no, 31, 0x2a30);
15185 +               phy_write_masked(port_no, 8, 0x0000, 0x0200);
15186 +               phy_write(port_no, 23, 0xFF80);
15187 +               phy_write(port_no, 23, 0x0000);
15188 +       }
15189 +       phy_write(port_no, 31, 0x0000);
15190 +       phy_write(port_no, 18, 0x0048);
15191 +       if (rev == 0)
15192 +       {
15193 +               phy_write(port_no, 31, 0x2a30);
15194 +               phy_write(port_no, 20, 0x6600);
15195 +               phy_write(port_no, 31, 0x0000);
15196 +               phy_write(port_no, 24, 0xa24e);
15197 +       }
15198 +       else
15199 +       {
15200 +               phy_write(port_no, 31, 0x2a30);
15201 +               phy_write_masked(port_no, 22, 0x0240, 0x0fc0);
15202 +               phy_write_masked(port_no, 20, 0x4000, 0x6000);
15203 +               phy_write(port_no, 31, 1);
15204 +               phy_write_masked(port_no, 20, 0x6000, 0xe000);
15205 +               phy_write(port_no, 31, 0x0000);
15206 +       }
15207 +}
15208 +
15209 +int Get_Set_port_status()
15210 +{
15211 +       unsigned int    reg_val,ability,rcv_mask,mac_config;
15212 +       int is_link=0;
15213 +       int i;
15214 +
15215 +       rcv_mask = SPI_read(2,0,0x10);                  // Receive mask
15216 +
15217 +       for(i=0;i<4;i++){
15218 +               reg_val = phy_read(i,1);
15219 +               if ((reg_val & 0x0024) == 0x0024) /* link is established and auto_negotiate process completed */
15220 +               {
15221 +                       is_link=1;
15222 +                       if(switch_pre_link[i]==LINK_DOWN){              // Link Down ==> Link up
15223 +
15224 +                               rcv_mask |= BIT(i);                     // Enable receive
15225 +
15226 +                               reg_val = phy_read(i,10);
15227 +                               if(reg_val & 0x0c00){
15228 +                                       printk("Port%d:Giga mode\n",i);
15229 +//                                     SPI_write(1,i,0x00,0x300701B1);
15230 +                                       mac_config = 0x00060004|(6<<6);
15231 +
15232 +                                       SPI_write(1,i,0x00,((mac_config & 0xfffffff8) | 1) | 0x20000030);       // reset port
15233 +                                       mac_config |= (( BIT(i) << 19) | 0x08000000);
15234 +                                       SPI_write(1,i,0x00,mac_config);
15235 +                                       SPI_write(1,i,0x04,0x000300ff);         // flow control
15236 +
15237 +                                       reg_val = SPI_read(5,0,0x12);
15238 +                                       reg_val &= ~BIT(i);
15239 +                                       SPI_write(5,0,0x12,reg_val);
15240 +
15241 +                                       reg_val = SPI_read(1,i,0x00);
15242 +                                       reg_val |= 0x10010000;
15243 +                                       SPI_write(1,i,0x00,reg_val);
15244 +//                                     SPI_write(1,i,0x00,0x10070181);
15245 +                                       switch_pre_link[i]=LINK_UP;
15246 +                                       switch_pre_speed[i]=GMAC_SPEED_1000;
15247 +                               }
15248 +                               else{
15249 +                                       reg_val = phy_read(i,5);
15250 +                                       ability = (reg_val&0x5e0) >>5;
15251 +                                       if ((ability & 0x0C)) /* 100M */
15252 +                                       {
15253 +//                                             SPI_write(1,i,0x00,0x30050472);
15254 +                                               if((ability&0x08)==0)           // Half
15255 +                                                       mac_config = 0x00040004 |(17<<6);
15256 +                                               else                            // Full
15257 +                                                       mac_config = 0x00040004 |(17<<6);
15258 +
15259 +                                               SPI_write(1,i,0x00,((mac_config & 0xfffffff8) | 1) | 0x20000030);       // reset port
15260 +                                               mac_config |= (( BIT(i) << 19) | 0x08000000);
15261 +                                               SPI_write(1,i,0x00,mac_config);
15262 +                                               SPI_write(1,i,0x04,0x000300ff);         // flow control
15263 +
15264 +                                               reg_val = SPI_read(5,0,0x12);
15265 +                                               reg_val &= ~BIT(i);
15266 +                                               SPI_write(5,0,0x12,reg_val);
15267 +
15268 +                                               reg_val = SPI_read(1,i,0x00);
15269 +                                               reg_val &= ~0x08000000;
15270 +                                               reg_val |= 0x10010000;
15271 +                                               SPI_write(1,i,0x00,reg_val);
15272 +//                                             SPI_write(1,i,0x00,0x10050442);
15273 +                                               printk("Port%d:100M\n",i);
15274 +                                               switch_pre_link[i]=LINK_UP;
15275 +                                               switch_pre_speed[i]=GMAC_SPEED_100;
15276 +                                       }
15277 +                                       else if((ability & 0x03)) /* 10M */
15278 +                                       {
15279 +//                                             SPI_write(1,i,0x00,0x30050473);
15280 +                                               if((ability&0x2)==0)            // Half
15281 +                                                       mac_config = 0x00040004 |(17<<6);
15282 +                                               else                            // Full
15283 +                                                       mac_config = 0x00040004 |(17<<6);
15284 +
15285 +                                               SPI_write(1,i,0x00,((mac_config & 0xfffffff8) | 1) | 0x20000030);       // reset port
15286 +                                               mac_config |= (( BIT(i) << 19) | 0x08000000);
15287 +                                               SPI_write(1,i,0x00,mac_config);
15288 +                                               SPI_write(1,i,0x04,0x000300ff);         // flow control
15289 +
15290 +                                               reg_val = SPI_read(5,0,0x12);
15291 +                                               reg_val &= ~BIT(i);
15292 +                                               SPI_write(5,0,0x12,reg_val);
15293 +
15294 +                                               reg_val = SPI_read(1,i,0x00);
15295 +                                               reg_val &= ~0x08000000;
15296 +                                               reg_val |= 0x10010000;
15297 +                                               SPI_write(1,i,0x00,reg_val);
15298 +//                                             SPI_write(1,i,0x00,0x10050443);
15299 +                                               printk("Port%d:10M\n",i);
15300 +                                               switch_pre_link[i]=LINK_UP;
15301 +                                               switch_pre_speed[i]=GMAC_SPEED_10;
15302 +                                       }
15303 +                                       else{
15304 +                                               SPI_write(1,i,0x00,0x20000030);
15305 +                                               printk("Port%d:Unknown mode\n",i);
15306 +                                               switch_pre_link[i]=LINK_DOWN;
15307 +                                               switch_pre_speed[i]=GMAC_SPEED_10;
15308 +                                       }
15309 +                               }
15310 +                       }
15311 +                       else{                                           // Link up ==> Link UP
15312 +
15313 +                       }
15314 +               }
15315 +               else{                                                   // Link Down
15316 +                       if(switch_pre_link[i]==LINK_UP){
15317 +                               printk("Port%d:Link Down\n",i);
15318 +                               //phy_receiver_init(i);
15319 +                               reg_val = SPI_read(1,i,0);
15320 +                               reg_val &= ~BIT(16);
15321 +                               SPI_write(1,i,0x00,reg_val);                    // disable RX
15322 +                               SPI_write(5,0,0x0E,BIT(i));                     // dicard packet
15323 +                               while((SPI_read(5,0,0x0C)&BIT(i))==0)           // wait to be empty
15324 +                                       msleep(1);
15325 +                               SPI_write(1,i,0x00,0x20000030);                 // PORT_RST
15326 +                               SPI_write(5,0,0x0E,SPI_read(5,0,0x0E) & ~BIT(i));// accept packet
15327 +
15328 +                               reg_val = SPI_read(5,0,0x12);
15329 +                               reg_val |= BIT(i);
15330 +                               SPI_write(5,0,0x12,reg_val);
15331 +                       }
15332 +                       switch_pre_link[i]=LINK_DOWN;
15333 +                       rcv_mask &= ~BIT(i);                    // disable receive
15334 +               }
15335 +       }
15336 +
15337 +       SPI_write(2,0,0x10,rcv_mask);                   // Receive mask
15338 +       return is_link;
15339 +
15340 +}
15341 +EXPORT_SYMBOL(Get_Set_port_status);
15342 +
15343 +void SPI_write(unsigned char block,unsigned char subblock,unsigned char addr,unsigned int value)
15344 +{
15345 +       int     i;
15346 +       char    bit;
15347 +       unsigned int data;
15348 +
15349 +       SPI_CS_enable(1);
15350 +
15351 +       data = (block<<5) | 0x10 | subblock;
15352 +
15353 +       //send write command
15354 +       for(i=SPI_OP_LEN-1;i>=0;i--)
15355 +       {
15356 +               bit = (data>>i)& 0x01;
15357 +               SPI_write_bit(bit);
15358 +       }
15359 +
15360 +       // send 8 bits address (MSB first, LSB last)
15361 +       for(i=SPI_ADD_LEN-1;i>=0;i--)
15362 +       {
15363 +               bit = (addr>>i)& 0x01;
15364 +               SPI_write_bit(bit);
15365 +       }
15366 +       // send 32 bits data (MSB first, LSB last)
15367 +       for(i=SPI_DAT_LEN-1;i>=0;i--)
15368 +       {
15369 +               bit = (value>>i)& 0x01;
15370 +               SPI_write_bit(bit);
15371 +       }
15372 +
15373 +       SPI_CS_enable(0);       // CS low
15374 +
15375 +}
15376 +
15377 +
15378 +/************************************
15379 +* SPI_write_bit
15380 +* bit_EEDO -> 1 or 0 to be written
15381 +************************************/
15382 +void SPI_write_bit(char bit_EEDO)
15383 +{
15384 +       unsigned int addr;
15385 +       unsigned int value;
15386 +
15387 +       addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
15388 +       value = readl(addr) |GPIO_EECK |GPIO_MOSI ;   /* set EECK/MISO Pin to output */
15389 +       writel(value,addr);
15390 +       if(bit_EEDO)
15391 +       {
15392 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_SET);
15393 +               writel(GPIO_MOSI,addr); /* set MISO to 1 */
15394 +
15395 +       }
15396 +       else
15397 +       {
15398 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15399 +               writel(GPIO_MOSI,addr); /* set MISO to 0 */
15400 +       }
15401 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_SET);
15402 +       writel(GPIO_EECK,addr); /* set EECK to 1 */
15403 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15404 +       writel(GPIO_EECK,addr); /* set EECK to 0 */
15405 +
15406 +       //return ;
15407 +}
15408 +
15409 +/**********************************************************************
15410 +* read a bit from ADM6996 register
15411 +***********************************************************************/
15412 +unsigned int SPI_read_bit(void) // read data from
15413 +{
15414 +       unsigned int addr;
15415 +       unsigned int value;
15416 +
15417 +       addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
15418 +       value = readl(addr) & (~GPIO_MISO);   // set EECK to output and MISO to input
15419 +       writel(value,addr);
15420 +
15421 +       addr =(GPIO_BASE_ADDR1 + GPIO_DATA_SET);
15422 +       writel(GPIO_EECK,addr); // set EECK to 1
15423 +
15424 +
15425 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_IN);
15426 +       value = readl(addr) ;
15427 +
15428 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15429 +       writel(GPIO_EECK,addr); // set EECK to 0
15430 +
15431 +
15432 +       value = value >> 30;
15433 +       return value ;
15434 +}
15435 +
15436 +/******************************************
15437 +* SPI_default
15438 +* EEPROM content default value
15439 +*******************************************/
15440 +int SPI_default(void)
15441 +{
15442 +       int i;
15443 +       unsigned reg_val,cmd;
15444 +
15445 +#if 0
15446 +       SPI_write(7,0,0x1C,0x01);                               // map code space to 0
15447 +
15448 +       reg_val = SPI_read(7,0,0x10);
15449 +       reg_val |= 0x0146;
15450 +       reg_val &= ~0x0001;
15451 +       SPI_write(7,0,0x10,reg_val);                            // reset iCPU and enable ext_access
15452 +       SPI_write(7,0,0x11,0x0000);                             // start address
15453 +       for(i=0;i<sizeof(vts_img);i++){
15454 +               SPI_write(7,0,0x12,vts_img[i]);                 // fill in ROM data
15455 +       }
15456 +       reg_val |= BIT(0)|BIT(3);
15457 +       SPI_write(7,0,0x10,reg_val);                            // release iCPU
15458 +       SPI_write(7,0,0x10,SPI_read(7,0,0x10)&~BIT(7));                         // release iCPU
15459 +       return ;
15460 +#endif
15461 +
15462 +
15463 +       for(i=0;i<15;i++){
15464 +               if(i!=6 && i!=7)
15465 +                       SPI_write(3,2,0,0x1010400+i);           // Initial memory
15466 +               mdelay(1);
15467 +       }
15468 +
15469 +       mdelay(30);
15470 +
15471 +       SPI_write(2,0,0xB0,0x05);                       // Clear MAC table
15472 +       SPI_write(2,0,0xD0,0x03);                       // Clear VLAN
15473 +
15474 +       //for(i=0;i<5;i++)
15475 +       SPI_write(1,6,0x19,0x2C);                       // Double Data rate
15476 +
15477 +       for(i=0;i<4;i++){
15478 +               SPI_write(1,i,0x00,0x30050472);         // MAC configure
15479 +               SPI_write(1,i,0x00,0x10050442);         // MAC configure
15480 +               SPI_write(1,i,0x10,0x5F4);              // Max length
15481 +               SPI_write(1,i,0x04,0x00030000);         // Flow control
15482 +               SPI_write(1,i,0xDF,0x00000001);         // Flow control
15483 +               SPI_write(1,i,0x08,0x000050c2);         // Flow control mac high
15484 +               SPI_write(1,i,0x0C,0x002b00f1);         // Flow control mac low
15485 +               SPI_write(1,i,0x6E,BIT(3));             // forward pause frame
15486 +       }
15487 +       SPI_write(1,i,0x00,0x20000030);                 // set port 4 as reset
15488 +
15489 +       SPI_write(1,6,0x00,0x300701B1);                 // MAC configure
15490 +       SPI_write(1,6,0x00,0x10070181);                 // MAC configure
15491 +       SPI_write(1,6,0x10,0x5F4);                      // Max length
15492 +       SPI_write(1,6,0x04,0x00030000);         // Flow control
15493 +       SPI_write(1,6,0xDF,0x00000002);         // Flow control
15494 +       SPI_write(1,6,0x08,0x000050c2);         // Flow control mac high
15495 +       SPI_write(1,6,0x0C,0x002b00f1);         // Flow control mac low
15496 +       SPI_write(1,6,0x6E,BIT(3));             // forward pause frame
15497 +
15498 +
15499 +       //SPI_write(7,0,0x05,0x31);                     // MII delay for loader
15500 +       //SPI_write(7,0,0x05,0x01);                     // MII delay for kernel
15501 +       SPI_write(7,0,0x05,0x33);
15502 +
15503 +       SPI_write(2,0,0x10,0x4F);                       // Receive mask
15504 +
15505 +       mdelay(50);
15506 +
15507 +       SPI_write(7,0,0x14,0x02);                       // Release Reset
15508 +
15509 +       mdelay(3);
15510 +
15511 +       for(i=0;i<4;i++){
15512 +               init_seq_7385(i);
15513 +               phy_receiver_init(i);
15514 +               cmd = BIT(26)|(i<<21)|(0x1B<<16);       // Config LED
15515 +               SPI_write(3,0,1,cmd);
15516 +               mdelay(10);
15517 +               reg_val = SPI_read(3,0,2);
15518 +               reg_val &= 0xFF00;
15519 +               reg_val |= 0x61;
15520 +               cmd = (i<<21)|(0x1B<<16)|reg_val;
15521 +               SPI_write(3,0,1,cmd);
15522 +
15523 +               cmd = BIT(26)|(i<<21)|(0x04<<16);       // Pause enable
15524 +               SPI_write(3,0,1,cmd);
15525 +               mdelay(10);
15526 +               reg_val = SPI_read(3,0,2);
15527 +               reg_val |= BIT(10)|BIT(11);
15528 +               cmd = (i<<21)|(0x04<<16)|reg_val;
15529 +               SPI_write(3,0,1,cmd);
15530 +
15531 +               cmd = BIT(26)|(i<<21)|(0x0<<16);        // collision test and re-negotiation
15532 +               SPI_write(3,0,1,cmd);
15533 +               mdelay(10);
15534 +               reg_val = SPI_read(3,0,2);
15535 +               reg_val |= BIT(7)|BIT(8)|BIT(9);
15536 +               cmd = (i<<21)|(0x0<<16)|reg_val;
15537 +               SPI_write(3,0,1,cmd);
15538 +       }
15539 +       init_seq_7385(i);
15540 +       writel(0x5787a7f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For switch timing
15541 +       return 4;               // return port_no
15542 +}
15543 +EXPORT_SYMBOL(SPI_default);
15544 +
15545 +/***********************************************************
15546 +* SPI_CS_enable
15547 +* before access ,you have to enable Chip Select. (pull high)
15548 +* When fisish, you should pull low !!
15549 +*************************************************************/
15550 +void SPI_CS_enable(unsigned char enable)
15551 +{
15552 +
15553 +       unsigned int addr,value;
15554 +
15555 +       addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
15556 +       value = readl(addr) |GPIO_EECS |GPIO_EECK;   /* set EECS/EECK Pin to output */
15557 +       writel(value,addr);
15558 +
15559 +       if(enable)
15560 +       {
15561 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15562 +               writel(GPIO_EECK,addr); /* set EECK to 0 */     // pull low clk first
15563 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15564 +               writel(GPIO_EECS,addr); /* set EECS to 0 */
15565 +
15566 +       }
15567 +       else
15568 +       {
15569 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_SET);
15570 +               writel(GPIO_EECK,addr); /* set EECK to 1 */     // pull high clk before disable
15571 +               writel(GPIO_EECS,addr); /* set EECS to 1 */
15572 +       }
15573 +}
15574 +
15575 +
15576 +/************************************************
15577 +* SPI_read
15578 +* table -> which table to be read: 1/count  0/EEPROM
15579 +* addr  -> Address to be read
15580 +* return : Value of the register
15581 +*************************************************/
15582 +unsigned int SPI_read(unsigned char block,unsigned char subblock,unsigned char addr)
15583 +{
15584 +       int     i;
15585 +       char    bit;
15586 +       unsigned int data,value=0;
15587 +
15588 +       SPI_CS_enable(1);
15589 +
15590 +       data = (block<<5) | subblock;
15591 +
15592 +       //send write command
15593 +       for(i=SPI_OP_LEN-1;i>=0;i--)
15594 +       {
15595 +               bit = (data>>i)& 0x01;
15596 +               SPI_write_bit(bit);
15597 +       }
15598 +
15599 +       // send 8 bits address (MSB first, LSB last)
15600 +       for(i=SPI_ADD_LEN-1;i>=0;i--)
15601 +       {
15602 +               bit = (addr>>i)& 0x01;
15603 +               SPI_write_bit(bit);
15604 +       }
15605 +
15606 +       // dummy read for chip ready
15607 +       for(i=0;i<8;i++)
15608 +               SPI_read_bit();
15609 +
15610 +
15611 +       // read 32 bits data (MSB first, LSB last)
15612 +       for(i=SPI_DAT_LEN-1;i>=0;i--)
15613 +       {
15614 +               bit = SPI_read_bit();
15615 +               value |= bit<<i;
15616 +       }
15617 +
15618 +       SPI_CS_enable(0);       // CS low
15619 +       return(value);
15620 +
15621 +}
15622 +
15623 +void pull_low_gpio(unsigned int val)
15624 +{
15625 +
15626 +       unsigned int addr,value;
15627 +
15628 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15629 +       writel(val,addr); /* set pin low to save power*/
15630 +
15631 +       addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
15632 +       value = readl(addr) & ~ val;   /* set Pin to input */
15633 +       writel(value,addr);
15634 +
15635 +//     value = readl(GMAC_GLOBAL_BASE_ADDR+0x0C);      // reset GPIO1 module(self clear)
15636 +//     value |= BIT(21);
15637 +//     writel(value,GMAC_GLOBAL_BASE_ADDR+0x0C);
15638 +}
15639 +
15640 +unsigned int SPI_get_identifier(void)
15641 +{
15642 +       unsigned int flag=0;
15643 +
15644 +       SPI_write(7,0,0x01,0x01);
15645 +       flag = SPI_read(7,0,0x18);  // chip id
15646 +       if((flag & 0x0ffff000)==0x07385000){
15647 +               printk("Get VSC-switch ID 0x%08x\n",flag);
15648 +               //Giga_switch = 1;;
15649 +               return 1;
15650 +       }
15651 +       else{
15652 +               printk("VSC-switch not found\n");
15653 +               //Giga_switch = 0;
15654 +               pull_low_gpio(GPIO_EECK|GPIO_MOSI|GPIO_MISO|GPIO_EECS); // reduce power consume
15655 +               return 0;
15656 +       }
15657 +}
15658 +EXPORT_SYMBOL(SPI_get_identifier);
15659 +
15660 --- /dev/null
15661 +++ b/include/asm-arm/arch-sl2312/sl351x_gmac.h
15662 @@ -0,0 +1,2223 @@
15663 +/****************************************************************************
15664 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
15665 +*--------------------------------------------------------------------------
15666 +* Name                 : sl351x_gmac.h
15667 +* Description  :
15668 +*              Define for device driver of Storlink SL351x network Engine
15669 +*
15670 +* Historych
15671 +*
15672 +*      Date            Writer          Description
15673 +*      -----------     -----------     -------------------------------------------------
15674 +*      08/22/2005      Gary Chen       Create and implement
15675 +*
15676 +****************************************************************************/
15677 +#ifndef _GMAC_SL351x_H
15678 +#define _GMAC_SL351x_H
15679 +#include <linux/skbuff.h>
15680 +
15681 +#define SL351x_GMAC_WORKAROUND         1
15682 +
15683 +#undef BIG_ENDIAN
15684 +#define BIG_ENDIAN                             0
15685 +#define GMAC_DEBUG                             1
15686 +#define GMAC_NUM                                       2
15687 +//#define      L2_jumbo_frame                          1
15688 +
15689 +#define _PACKED_                                       __attribute__ ((aligned(1), packed))
15690 +
15691 +#ifndef BIT
15692 +#define BIT(x)                                         (1 << (x))
15693 +#endif
15694 +
15695 +#define REG32(addr)                            (*(volatile unsigned long  * const)(addr))
15696 +
15697 +#define DMA_MALLOC(size,handle)                pci_alloc_consistent(NULL,size,handle)
15698 +#define DMA_MFREE(mem,size,handle)     pci_free_consistent(NULL,size,mem,handle)
15699 +
15700 +// Define frame size
15701 +#define ETHER_ADDR_LEN                         6
15702 +#define GMAC_MAX_ETH_FRAME_SIZE                1514
15703 +#define GMAC_TX_BUF_SIZE                       ((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
15704 +#define MAX_ISR_WORK                   20
15705 +
15706 +#ifdef L2_jumbo_frame
15707 +#define SW_RX_BUF_SIZE                         9234    // 2048 ,9234
15708 +#else
15709 +#define SW_RX_BUF_SIZE                         1536    // 2048
15710 +#endif
15711 +
15712 +#define HW_RX_BUF_SIZE                         1536    // 2048
15713 +
15714 +#define GMAC_DEV_TX_TIMEOUT            (10*HZ)                 //add by CH
15715 +#define        SKB_RESERVE_BYTES                       16
15716 +
15717 +/**********************************************************************
15718 + * Base Register
15719 + **********************************************************************/
15720 +#define TOE_BASE                                       (IO_ADDRESS(SL2312_TOE_BASE))
15721 +#define GMAC_GLOBAL_BASE_ADDR       (IO_ADDRESS(SL2312_GLOBAL_BASE))
15722 +
15723 +#define TOE_GLOBAL_BASE                                (TOE_BASE + 0x0000)
15724 +#define TOE_NONTOE_QUE_HDR_BASE                (TOE_BASE + 0x2000)
15725 +#define TOE_TOE_QUE_HDR_BASE           (TOE_BASE + 0x3000)
15726 +#define TOE_V_BIT_BASE                         (TOE_BASE + 0x4000)
15727 +#define TOE_A_BIT_BASE                         (TOE_BASE + 0x6000)
15728 +#define TOE_GMAC0_DMA_BASE                     (TOE_BASE + 0x8000)
15729 +#define TOE_GMAC0_BASE                         (TOE_BASE + 0xA000)
15730 +#define TOE_GMAC1_DMA_BASE                     (TOE_BASE + 0xC000)
15731 +#define TOE_GMAC1_BASE                         (TOE_BASE + 0xE000)
15732 +
15733 +/**********************************************************************
15734 + * Queue ID
15735 + **********************************************************************/
15736 +#define TOE_SW_FREE_QID                                0x00
15737 +#define TOE_HW_FREE_QID                                0x01
15738 +#define TOE_GMAC0_SW_TXQ0_QID          0x02
15739 +#define TOE_GMAC0_SW_TXQ1_QID          0x03
15740 +#define TOE_GMAC0_SW_TXQ2_QID          0x04
15741 +#define TOE_GMAC0_SW_TXQ3_QID          0x05
15742 +#define TOE_GMAC0_SW_TXQ4_QID          0x06
15743 +#define TOE_GMAC0_SW_TXQ5_QID          0x07
15744 +#define TOE_GMAC0_HW_TXQ0_QID          0x08
15745 +#define TOE_GMAC0_HW_TXQ1_QID          0x09
15746 +#define TOE_GMAC0_HW_TXQ2_QID          0x0A
15747 +#define TOE_GMAC0_HW_TXQ3_QID          0x0B
15748 +#define TOE_GMAC1_SW_TXQ0_QID          0x12
15749 +#define TOE_GMAC1_SW_TXQ1_QID          0x13
15750 +#define TOE_GMAC1_SW_TXQ2_QID          0x14
15751 +#define TOE_GMAC1_SW_TXQ3_QID          0x15
15752 +#define TOE_GMAC1_SW_TXQ4_QID          0x16
15753 +#define TOE_GMAC1_SW_TXQ5_QID          0x17
15754 +#define TOE_GMAC1_HW_TXQ0_QID          0x18
15755 +#define TOE_GMAC1_HW_TXQ1_QID          0x19
15756 +#define TOE_GMAC1_HW_TXQ2_QID          0x1A
15757 +#define TOE_GMAC1_HW_TXQ3_QID          0x1B
15758 +#define TOE_GMAC0_DEFAULT_QID          0x20
15759 +#define TOE_GMAC1_DEFAULT_QID          0x21
15760 +#define TOE_CLASSIFICATION_QID(x)      (0x22 + x)      // 0x22 ~ 0x2F
15761 +#define TOE_TOE_QID(x)                         (0x40 + x)      // 0x40 ~ 0x7F
15762 +
15763 +/**********************************************************************
15764 + * TOE DMA Queue Number should be 2^n, n = 6...12
15765 + * TOE DMA Queues are the following queue types:
15766 + *             SW Free Queue, HW Free Queue,
15767 + *             GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
15768 + * They have same descriptor numbers.
15769 + * The base address and descriptor number are configured at
15770 + * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
15771 + **********************************************************************/
15772 +#define TOE_SW_FREEQ_DESC_POWER                10
15773 +#define TOE_SW_FREEQ_DESC_NUM          (1<<TOE_SW_FREEQ_DESC_POWER)
15774 +#define TOE_HW_FREEQ_DESC_POWER                8
15775 +#define TOE_HW_FREEQ_DESC_NUM          (1<<TOE_HW_FREEQ_DESC_POWER)
15776 +#define TOE_GMAC0_SWTXQ_DESC_POWER     8
15777 +#define TOE_GMAC0_SWTXQ_DESC_NUM       (1<<TOE_GMAC0_SWTXQ_DESC_POWER)
15778 +#define TOE_GMAC0_HWTXQ_DESC_POWER     8
15779 +#define TOE_GMAC0_HWTXQ_DESC_NUM       (1<<TOE_GMAC0_HWTXQ_DESC_POWER)
15780 +#define TOE_GMAC1_SWTXQ_DESC_POWER     8
15781 +#define TOE_GMAC1_SWTXQ_DESC_NUM       (1<<TOE_GMAC1_SWTXQ_DESC_POWER)
15782 +#define TOE_GMAC1_HWTXQ_DESC_POWER     8
15783 +#define TOE_GMAC1_HWTXQ_DESC_NUM       (1<<TOE_GMAC1_HWTXQ_DESC_POWER)
15784 +#define TOE_DEFAULT_Q0_DESC_POWER      8
15785 +#define TOE_DEFAULT_Q0_DESC_NUM                (1<<TOE_DEFAULT_Q0_DESC_POWER)
15786 +#define TOE_DEFAULT_Q1_DESC_POWER      8
15787 +#define TOE_DEFAULT_Q1_DESC_NUM                (1<<TOE_DEFAULT_Q1_DESC_POWER)
15788 +#define TOE_TOE_DESC_POWER                     8
15789 +#define TOE_TOE_DESC_NUM                       (1<<TOE_TOE_DESC_POWER)
15790 +#define TOE_CLASS_DESC_POWER           8
15791 +#define TOE_CLASS_DESC_NUM                     (1<<TOE_CLASS_DESC_POWER)
15792 +#define TOE_INTR_DESC_POWER                    8
15793 +#define TOE_INTR_DESC_NUM                      (1<<TOE_INTR_DESC_POWER)
15794 +
15795 +#define TOE_TOE_QUEUE_MAX                      64
15796 +#define TOE_TOE_QUEUE_NUM                      64
15797 +#define TOE_CLASS_QUEUE_MAX                    14
15798 +#define TOE_CLASS_QUEUE_NUM                    14
15799 +#define TOE_INTR_QUEUE_MAX                     4
15800 +#define TOE_INTR_QUEUE_NUM                     4
15801 +#define TOE_SW_TXQ_MAX                         6
15802 +#define TOE_SW_TXQ_NUM                         1
15803 +#define TOE_HW_TXQ_MAX                         4
15804 +#define TOE_HW_TXQ_NUM                         4
15805 +#define _max(x,y)                                      ((x>y) ? x :y)
15806 +#define TX_DESC_NUM                                    _max(TOE_GMAC0_SWTXQ_DESC_NUM, TOE_GMAC1_SWTXQ_DESC_NUM)
15807 +
15808 +#define RWPTR_ADVANCE_ONE(x, max)      ((x == (max -1)) ? 0 : x+1)
15809 +#define RWPTR_RECEDE_ONE(x, max)       ((x == 0) ? (max -1) : x-1)
15810 +#define SET_WPTR(addr, data)           (*(volatile u16 * const)((u32)(addr)+2) = (u16)data)
15811 +#define SET_RPTR(addr, data)           (*(volatile u16 * const)((u32)(addr)) = (u16)data)
15812 +
15813 +/**********************************************************************
15814 + * Global registers
15815 + * #define TOE_GLOBAL_BASE                     (TOE_BASE + 0x0000)
15816 + * Base 0x60000000
15817 + **********************************************************************/
15818 +#define GLOBAL_TOE_VERSION_REG                 0x0000
15819 +#define GLOBAL_SW_FREEQ_BASE_SIZE_REG  0x0004
15820 +#define GLOBAL_HW_FREEQ_BASE_SIZE_REG  0x0008
15821 +#define GLOBAL_DMA_SKB_SIZE_REG                        0x0010
15822 +#define GLOBAL_SWFQ_RWPTR_REG                  0x0014
15823 +#define GLOBAL_HWFQ_RWPTR_REG                  0x0018
15824 +#define GLOBAL_INTERRUPT_STATUS_0_REG  0x0020
15825 +#define GLOBAL_INTERRUPT_ENABLE_0_REG  0x0024
15826 +#define GLOBAL_INTERRUPT_SELECT_0_REG  0x0028
15827 +#define GLOBAL_INTERRUPT_STATUS_1_REG  0x0030
15828 +#define GLOBAL_INTERRUPT_ENABLE_1_REG  0x0034
15829 +#define GLOBAL_INTERRUPT_SELECT_1_REG  0x0038
15830 +#define GLOBAL_INTERRUPT_STATUS_2_REG  0x0040
15831 +#define GLOBAL_INTERRUPT_ENABLE_2_REG  0x0044
15832 +#define GLOBAL_INTERRUPT_SELECT_2_REG  0x0048
15833 +#define GLOBAL_INTERRUPT_STATUS_3_REG  0x0050
15834 +#define GLOBAL_INTERRUPT_ENABLE_3_REG  0x0054
15835 +#define GLOBAL_INTERRUPT_SELECT_3_REG  0x0058
15836 +#define GLOBAL_INTERRUPT_STATUS_4_REG  0x0060
15837 +#define GLOBAL_INTERRUPT_ENABLE_4_REG  0x0064
15838 +#define GLOBAL_INTERRUPT_SELECT_4_REG  0x0068
15839 +#define GLOBAL_HASH_TABLE_BASE_REG             0x006C
15840 +#define GLOBAL_QUEUE_THRESHOLD_REG             0x0070
15841 +
15842 +/**********************************************************************
15843 + * GMAC 0/1 DMA/TOE register
15844 + * #define TOE_GMAC0_DMA_BASE          (TOE_BASE + 0x8000)
15845 + * #define TOE_GMAC1_DMA_BASE          (TOE_BASE + 0xC000)
15846 + * Base 0x60008000 or 0x6000C000
15847 + **********************************************************************/
15848 +#define GMAC_DMA_CTRL_REG                              0x0000
15849 +#define GMAC_TX_WEIGHTING_CTRL_0_REG   0x0004
15850 +#define GMAC_TX_WEIGHTING_CTRL_1_REG   0x0008
15851 +#define GMAC_SW_TX_QUEUE0_PTR_REG              0x000C
15852 +#define GMAC_SW_TX_QUEUE1_PTR_REG              0x0010
15853 +#define GMAC_SW_TX_QUEUE2_PTR_REG              0x0014
15854 +#define GMAC_SW_TX_QUEUE3_PTR_REG              0x0018
15855 +#define GMAC_SW_TX_QUEUE4_PTR_REG              0x001C
15856 +#define GMAC_SW_TX_QUEUE5_PTR_REG              0x0020
15857 +#define GMAC_HW_TX_QUEUE0_PTR_REG              0x0024
15858 +#define GMAC_HW_TX_QUEUE1_PTR_REG              0x0028
15859 +#define GMAC_HW_TX_QUEUE2_PTR_REG              0x002C
15860 +#define GMAC_HW_TX_QUEUE3_PTR_REG              0x0030
15861 +#define GMAC_DMA_TX_FIRST_DESC_REG             0x0038
15862 +#define GMAC_DMA_TX_CURR_DESC_REG              0x003C
15863 +#define GMAC_DMA_TX_DESC_WORD0_REG             0x0040
15864 +#define GMAC_DMA_TX_DESC_WORD1_REG             0x0044
15865 +#define GMAC_DMA_TX_DESC_WORD2_REG             0x0048
15866 +#define GMAC_DMA_TX_DESC_WORD3_REG             0x004C
15867 +#define GMAC_SW_TX_QUEUE_BASE_REG              0x0050
15868 +#define GMAC_HW_TX_QUEUE_BASE_REG              0x0054
15869 +#define GMAC_DMA_RX_FIRST_DESC_REG             0x0058
15870 +#define GMAC_DMA_RX_CURR_DESC_REG              0x005C
15871 +#define GMAC_DMA_RX_DESC_WORD0_REG             0x0060
15872 +#define GMAC_DMA_RX_DESC_WORD1_REG             0x0064
15873 +#define GMAC_DMA_RX_DESC_WORD2_REG             0x0068
15874 +#define GMAC_DMA_RX_DESC_WORD3_REG             0x006C
15875 +#define GMAC_HASH_ENGINE_REG0                  0x0070
15876 +#define GMAC_HASH_ENGINE_REG1                  0x0074
15877 +#define GMAC_MR0CR0                                            0x0078  // matching rule 0 Control register 0
15878 +#define GMAC_MR0CR1                                            0x007C  // matching rule 0 Control register 1
15879 +#define GMAC_MR0CR2                                            0x0080  // matching rule 0 Control register 2
15880 +#define GMAC_MR1CR0                                            0x0084  // matching rule 1 Control register 0
15881 +#define GMAC_MR1CR1                                            0x0088  // matching rule 1 Control register 1
15882 +#define GMAC_MR1CR2                                            0x008C  // matching rule 1 Control register 2
15883 +#define GMAC_MR2CR0                                            0x0090  // matching rule 2 Control register 0
15884 +#define GMAC_MR2CR1                                            0x0094  // matching rule 2 Control register 1
15885 +#define GMAC_MR2CR2                                            0x0098  // matching rule 2 Control register 2
15886 +#define GMAC_MR3CR0                                            0x009C  // matching rule 3 Control register 0
15887 +#define GMAC_MR3CR1                                            0x00A0  // matching rule 3 Control register 1
15888 +#define GMAC_MR3CR2                                            0x00A4  // matching rule 3 Control register 2
15889 +#define GMAC_SPR0                                              0x00A8  // Support Protocol Regsister 0
15890 +#define GMAC_SPR1                                              0x00AC  // Support Protocol Regsister 1
15891 +#define GMAC_SPR2                                              0x00B0  // Support Protocol Regsister 2
15892 +#define GMAC_SPR3                                              0x00B4  // Support Protocol Regsister 3
15893 +#define GMAC_SPR4                                              0x00B8  // Support Protocol Regsister 4
15894 +#define GMAC_SPR5                                              0x00BC  // Support Protocol Regsister 5
15895 +#define GMAC_SPR6                                              0x00C0  // Support Protocol Regsister 6
15896 +#define GMAC_SPR7                                              0x00C4  // Support Protocol Regsister 7
15897 +#define GMAC_AHB_WEIGHT_REG                            0x00C8  // GMAC Hash/Rx/Tx AHB Weighting register
15898 +
15899 +/**********************************************************************
15900 + * TOE GMAC 0/1 register
15901 + * #define TOE_GMAC0_BASE                              (TOE_BASE + 0xA000)
15902 + * #define TOE_GMAC1_BASE                              (TOE_BASE + 0xE000)
15903 + * Base 0x6000A000 or 0x6000E000
15904 + **********************************************************************/
15905 +enum GMAC_REGISTER {
15906 +       GMAC_STA_ADD0   = 0x0000,
15907 +       GMAC_STA_ADD1   = 0x0004,
15908 +       GMAC_STA_ADD2   = 0x0008,
15909 +       GMAC_RX_FLTR    = 0x000c,
15910 +       GMAC_MCAST_FIL0 = 0x0010,
15911 +       GMAC_MCAST_FIL1 = 0x0014,
15912 +       GMAC_CONFIG0    = 0x0018,
15913 +       GMAC_CONFIG1    = 0x001c,
15914 +       GMAC_CONFIG2    = 0x0020,
15915 +       GMAC_CONFIG3    = 0x0024,
15916 +       GMAC_RESERVED   = 0x0028,
15917 +       GMAC_STATUS             = 0x002c,
15918 +       GMAC_IN_DISCARDS= 0x0030,
15919 +       GMAC_IN_ERRORS  = 0x0034,
15920 +       GMAC_IN_MCAST   = 0x0038,
15921 +       GMAC_IN_BCAST   = 0x003c,
15922 +       GMAC_IN_MAC1    = 0x0040,       // for STA 1 MAC Address
15923 +       GMAC_IN_MAC2    = 0x0044        // for STA 2 MAC Address
15924 +};
15925 +/**********************************************************************
15926 + * TOE version Register (offset 0x0000)
15927 + **********************************************************************/
15928 +typedef union
15929 +{
15930 +       unsigned int bits32;
15931 +       struct bit
15932 +       {
15933 +#if (BIG_ENDIAN==1)
15934 +
15935 +               unsigned int reserved           : 15;   // bit 31:17
15936 +               unsigned int v_bit_mode         : 1;    // bit 16               1: 128-entry
15937 +               unsigned int device_id          : 12;   // bit 15:4     Device ID
15938 +               unsigned int revision_id        : 4;    // bit  3:0     Revision ID
15939 +#else
15940 +               unsigned int revision_id        : 4;    // bit  3:0     Revision ID
15941 +               unsigned int device_id          : 12;   // bit 15:4     Device ID
15942 +               unsigned int v_bit_mode         : 1;    // bit 16               1: 128-entry
15943 +               unsigned int reserved           : 15;   // bit 31:17
15944 +#endif
15945 +       } bits;
15946 +} TOE_VERSION_T;
15947 +
15948 +
15949 +/**********************************************************************
15950 + * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
15951 + **********************************************************************/
15952 +typedef union
15953 +{
15954 +       unsigned int bits32;
15955 +       unsigned int base_size;
15956 +} DMA_Q_BASE_SIZE_T;
15957 +#define DMA_Q_BASE_MASK        (~0x0f)
15958 +
15959 +/**********************************************************************
15960 + * DMA SKB Buffer register (offset 0x0008)
15961 + **********************************************************************/
15962 +typedef union
15963 +{
15964 +       unsigned int bits32;
15965 +       struct bit_0008
15966 +       {
15967 +#if (BIG_ENDIAN==1)
15968 +
15969 +               unsigned int hw_skb_size        : 16;   // bit 31:16    HW Free poll SKB Size
15970 +               unsigned int sw_skb_size        : 16;   // bit 15:0     SW Free poll SKB Size
15971 +#else
15972 +               unsigned int sw_skb_size        : 16;   // bit 15:0     SW Free poll SKB Size
15973 +               unsigned int hw_skb_size        : 16;   // bit 31:16    HW Free poll SKB Size
15974 +#endif
15975 +       } bits;
15976 +} DMA_SKB_SIZE_T;
15977 +
15978 +/**********************************************************************
15979 + * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
15980 + **********************************************************************/
15981 +typedef union
15982 +{
15983 +       unsigned int bits32;
15984 +       struct bit_000c
15985 +       {
15986 +#if (BIG_ENDIAN==1)
15987 +
15988 +               unsigned int wptr                       : 16;   // bit 31:16    Write Ptr, RW
15989 +               unsigned int rptr                       : 16;   // bit 15:0             Read Ptr, RO
15990 +#else
15991 +               unsigned int rptr                       : 16;   // bit 15:0             Read Ptr, RO
15992 +               unsigned int wptr                       : 16;   // bit 31:16    Write Ptr, RW
15993 +#endif
15994 +       } bits;
15995 +} DMA_RWPTR_T;
15996 +
15997 +/**********************************************************************
15998 + * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
15999 + **********************************************************************/
16000 +// see DMA_RWPTR_T structure
16001 +
16002 +/**********************************************************************
16003 + * Interrupt Status Register 0         (offset 0x0020)
16004 + * Interrupt Mask Register 0   (offset 0x0024)
16005 + * Interrupt Select Register 0         (offset 0x0028)
16006 + **********************************************************************/
16007 +typedef union
16008 +{
16009 +       unsigned int bits32;
16010 +       struct bit_0020
16011 +       {
16012 +#if (BIG_ENDIAN==1)
16013 +               unsigned int txDerr1            : 1;    // bit 31       GMAC1 AHB Bus Error while Tx
16014 +               unsigned int txPerr1            : 1;    // bit 30       GMAC1 Tx Descriptor Protocol Error
16015 +               unsigned int txDerr0            : 1;    // bit 29       GMAC0 AHB Bus Error while Tx
16016 +               unsigned int txPerr0            : 1;    // bit 28       GMAC0 Tx Descriptor Protocol Error
16017 +               unsigned int rxDerr1            : 1;    // bit 27       GMAC1 AHB Bus Error while Rx
16018 +               unsigned int rxPerr1            : 1;    // bit 26       GMAC1 Rx Descriptor Protocol Error
16019 +               unsigned int rxDerr0            : 1;    // bit 25       GMAC0 AHB Bus Error while Rx
16020 +               unsigned int rxPerr0            : 1;    // bit 24       GMAC0 Rx Descriptor Protocol Error
16021 +               unsigned int swtq15_fin         : 1;    // bit 23       GMAC1 SW Tx Queue 5 Finish Interrupt
16022 +               unsigned int swtq14_fin         : 1;    // bit 22       GMAC1 SW Tx Queue 4 Finish Interrupt
16023 +               unsigned int swtq13_fin         : 1;    // bit 21       GMAC1 SW Tx Queue 3 Finish Interrupt
16024 +               unsigned int swtq12_fin         : 1;    // bit 20       GMAC1 SW Tx Queue 2 Finish Interrupt
16025 +               unsigned int swtq11_fin         : 1;    // bit 19       GMAC1 SW Tx Queue 1 Finish Interrupt
16026 +               unsigned int swtq10_fin         : 1;    // bit 18       GMAC1 SW Tx Queue 0 Finish Interrupt
16027 +               unsigned int swtq05_fin         : 1;    // bit 17       GMAC0 SW Tx Queue 5 Finish Interrupt
16028 +               unsigned int swtq04_fin         : 1;    // bit 16       GMAC0 SW Tx Queue 4 Finish Interrupt
16029 +               unsigned int swtq03_fin         : 1;    // bit 15       GMAC0 SW Tx Queue 3 Finish Interrupt
16030 +               unsigned int swtq02_fin         : 1;    // bit 14       GMAC0 SW Tx Queue 2 Finish Interrupt
16031 +               unsigned int swtq01_fin         : 1;    // bit 13       GMAC0 SW Tx Queue 1 Finish Interrupt
16032 +               unsigned int swtq00_fin         : 1;    // bit 12       GMAC0 SW Tx Queue 0 Finish Interrupt
16033 +               unsigned int swtq15_eof         : 1;    // bit 11       GMAC1 SW Tx Queue 5 EOF Interrupt
16034 +               unsigned int swtq14_eof         : 1;    // bit 10       GMAC1 SW Tx Queue 4 EOF Interrupt
16035 +               unsigned int swtq13_eof         : 1;    // bit 9        GMAC1 SW Tx Queue 3 EOF Interrupt
16036 +               unsigned int swtq12_eof         : 1;    // bit 8        GMAC1 SW Tx Queue 2 EOF Interrupt
16037 +               unsigned int swtq11_eof         : 1;    // bit 7        GMAC1 SW Tx Queue 1 EOF Interrupt
16038 +               unsigned int swtq10_eof         : 1;    // bit 6        GMAC1 SW Tx Queue 0 EOF Interrupt
16039 +               unsigned int swtq05_eof         : 1;    // bit 5        GMAC0 SW Tx Queue 5 EOF Interrupt
16040 +               unsigned int swtq04_eof         : 1;    // bit 4        GMAC0 SW Tx Queue 4 EOF Interrupt
16041 +               unsigned int swtq03_eof         : 1;    // bit 3        GMAC0 SW Tx Queue 3 EOF Interrupt
16042 +               unsigned int swtq02_eof         : 1;    // bit 2        GMAC0 SW Tx Queue 2 EOF Interrupt
16043 +               unsigned int swtq01_eof         : 1;    // bit 1        GMAC0 SW Tx Queue 1 EOF Interrupt
16044 +               unsigned int swtq00_eof         : 1;    // bit 0        GMAC0 SW Tx Queue 0 EOF Interrupt
16045 +#else
16046 +               unsigned int swtq00_eof         : 1;    // bit 0        GMAC0 SW Tx Queue 0 EOF Interrupt
16047 +               unsigned int swtq01_eof         : 1;    // bit 1        GMAC0 SW Tx Queue 1 EOF Interrupt
16048 +               unsigned int swtq02_eof         : 1;    // bit 2        GMAC0 SW Tx Queue 2 EOF Interrupt
16049 +               unsigned int swtq03_eof         : 1;    // bit 3        GMAC0 SW Tx Queue 3 EOF Interrupt
16050 +               unsigned int swtq04_eof         : 1;    // bit 4        GMAC0 SW Tx Queue 4 EOF Interrupt
16051 +               unsigned int swtq05_eof         : 1;    // bit 5        GMAC0 SW Tx Queue 5 EOF Interrupt
16052 +               unsigned int swtq10_eof         : 1;    // bit 6        GMAC1 SW Tx Queue 0 EOF Interrupt
16053 +               unsigned int swtq11_eof         : 1;    // bit 7        GMAC1 SW Tx Queue 1 EOF Interrupt
16054 +               unsigned int swtq12_eof         : 1;    // bit 8        GMAC1 SW Tx Queue 2 EOF Interrupt
16055 +               unsigned int swtq13_eof         : 1;    // bit 9        GMAC1 SW Tx Queue 3 EOF Interrupt
16056 +               unsigned int swtq14_eof         : 1;    // bit 10       GMAC1 SW Tx Queue 4 EOF Interrupt
16057 +               unsigned int swtq15_eof         : 1;    // bit 11       GMAC1 SW Tx Queue 5 EOF Interrupt
16058 +               unsigned int swtq00_fin         : 1;    // bit 12       GMAC0 SW Tx Queue 0 Finish Interrupt
16059 +               unsigned int swtq01_fin         : 1;    // bit 13       GMAC0 SW Tx Queue 1 Finish Interrupt
16060 +               unsigned int swtq02_fin         : 1;    // bit 14       GMAC0 SW Tx Queue 2 Finish Interrupt
16061 +               unsigned int swtq03_fin         : 1;    // bit 15       GMAC0 SW Tx Queue 3 Finish Interrupt
16062 +               unsigned int swtq04_fin         : 1;    // bit 16       GMAC0 SW Tx Queue 4 Finish Interrupt
16063 +               unsigned int swtq05_fin         : 1;    // bit 17       GMAC0 SW Tx Queue 5 Finish Interrupt
16064 +               unsigned int swtq10_fin         : 1;    // bit 18       GMAC1 SW Tx Queue 0 Finish Interrupt
16065 +               unsigned int swtq11_fin         : 1;    // bit 19       GMAC1 SW Tx Queue 1 Finish Interrupt
16066 +               unsigned int swtq12_fin         : 1;    // bit 20       GMAC1 SW Tx Queue 2 Finish Interrupt
16067 +               unsigned int swtq13_fin         : 1;    // bit 21       GMAC1 SW Tx Queue 3 Finish Interrupt
16068 +               unsigned int swtq14_fin         : 1;    // bit 22       GMAC1 SW Tx Queue 4 Finish Interrupt
16069 +               unsigned int swtq15_fin         : 1;    // bit 23       GMAC1 SW Tx Queue 5 Finish Interrupt
16070 +               unsigned int rxPerr0            : 1;    // bit 24       GMAC0 Rx Descriptor Protocol Error
16071 +               unsigned int rxDerr0            : 1;    // bit 25       GMAC0 AHB Bus Error while Rx
16072 +               unsigned int rxPerr1            : 1;    // bit 26       GMAC1 Rx Descriptor Protocol Error
16073 +               unsigned int rxDerr1            : 1;    // bit 27       GMAC1 AHB Bus Error while Rx
16074 +               unsigned int txPerr0            : 1;    // bit 28       GMAC0 Tx Descriptor Protocol Error
16075 +               unsigned int txDerr0            : 1;    // bit 29       GMAC0 AHB Bus Error while Tx
16076 +               unsigned int txPerr1            : 1;    // bit 30       GMAC1 Tx Descriptor Protocol Error
16077 +               unsigned int txDerr1            : 1;    // bit 31       GMAC1 AHB Bus Error while Tx
16078 +#endif
16079 +       } bits;
16080 +} INTR_REG0_T;
16081 +
16082 +#define GMAC1_TXDERR_INT_BIT           BIT(31)
16083 +#define GMAC1_TXPERR_INT_BIT           BIT(30)
16084 +#define GMAC0_TXDERR_INT_BIT           BIT(29)
16085 +#define GMAC0_TXPERR_INT_BIT           BIT(28)
16086 +#define GMAC1_RXDERR_INT_BIT           BIT(27)
16087 +#define GMAC1_RXPERR_INT_BIT           BIT(26)
16088 +#define GMAC0_RXDERR_INT_BIT           BIT(25)
16089 +#define GMAC0_RXPERR_INT_BIT           BIT(24)
16090 +#define GMAC1_SWTQ15_FIN_INT_BIT       BIT(23)
16091 +#define GMAC1_SWTQ14_FIN_INT_BIT       BIT(22)
16092 +#define GMAC1_SWTQ13_FIN_INT_BIT       BIT(21)
16093 +#define GMAC1_SWTQ12_FIN_INT_BIT       BIT(20)
16094 +#define GMAC1_SWTQ11_FIN_INT_BIT       BIT(19)
16095 +#define GMAC1_SWTQ10_FIN_INT_BIT       BIT(18)
16096 +#define GMAC0_SWTQ05_FIN_INT_BIT       BIT(17)
16097 +#define GMAC0_SWTQ04_FIN_INT_BIT       BIT(16)
16098 +#define GMAC0_SWTQ03_FIN_INT_BIT       BIT(15)
16099 +#define GMAC0_SWTQ02_FIN_INT_BIT       BIT(14)
16100 +#define GMAC0_SWTQ01_FIN_INT_BIT       BIT(13)
16101 +#define GMAC0_SWTQ00_FIN_INT_BIT       BIT(12)
16102 +#define GMAC1_SWTQ15_EOF_INT_BIT       BIT(11)
16103 +#define GMAC1_SWTQ14_EOF_INT_BIT       BIT(10)
16104 +#define GMAC1_SWTQ13_EOF_INT_BIT       BIT(9)
16105 +#define GMAC1_SWTQ12_EOF_INT_BIT       BIT(8)
16106 +#define GMAC1_SWTQ11_EOF_INT_BIT       BIT(7)
16107 +#define GMAC1_SWTQ10_EOF_INT_BIT       BIT(6)
16108 +#define GMAC0_SWTQ05_EOF_INT_BIT       BIT(5)
16109 +#define GMAC0_SWTQ04_EOF_INT_BIT       BIT(4)
16110 +#define GMAC0_SWTQ03_EOF_INT_BIT       BIT(3)
16111 +#define GMAC0_SWTQ02_EOF_INT_BIT       BIT(2)
16112 +#define GMAC0_SWTQ01_EOF_INT_BIT       BIT(1)
16113 +#define GMAC0_SWTQ00_EOF_INT_BIT       BIT(0)
16114 +
16115 +
16116 +/**********************************************************************
16117 + * Interrupt Status Register 1         (offset 0x0030)
16118 + * Interrupt Mask Register 1   (offset 0x0034)
16119 + * Interrupt Select Register 1         (offset 0x0038)
16120 + **********************************************************************/
16121 +typedef union
16122 +{
16123 +       unsigned int bits32;
16124 +       struct bit_0030
16125 +       {
16126 +#if (BIG_ENDIAN==1)
16127 +               unsigned int toe_iq3_full       : 1;    // bit 31       TOE Interrupt Queue 3 Full Interrupt
16128 +               unsigned int toe_iq2_full       : 1;    // bit 30       TOE Interrupt Queue 2 Full Interrupt
16129 +               unsigned int toe_iq1_full       : 1;    // bit 29       TOE Interrupt Queue 1 Full Interrupt
16130 +               unsigned int toe_iq0_full       : 1;    // bit 28       TOE Interrupt Queue 0 Full Interrupt
16131 +               unsigned int toe_iq3_intr       : 1;    // bit 27       TOE Interrupt Queue 3 with Interrupts
16132 +               unsigned int toe_iq2_intr       : 1;    // bit 26       TOE Interrupt Queue 2 with Interrupts
16133 +               unsigned int toe_iq1_intr       : 1;    // bit 25       TOE Interrupt Queue 1 with Interrupts
16134 +               unsigned int toe_iq0_intr       : 1;    // bit 24       TOE Interrupt Queue 0 with Interrupts
16135 +               unsigned int hwtq13_eof         : 1;    // bit 23       GMAC1 HW Tx Queue3 EOF Interrupt
16136 +               unsigned int hwtq12_eof         : 1;    // bit 22       GMAC1 HW Tx Queue2 EOF Interrupt
16137 +               unsigned int hwtq11_eof         : 1;    // bit 21       GMAC1 HW Tx Queue1 EOF Interrupt
16138 +               unsigned int hwtq10_eof         : 1;    // bit 20       GMAC1 HW Tx Queue0 EOF Interrupt
16139 +               unsigned int hwtq03_eof         : 1;    // bit 19       GMAC0 HW Tx Queue3 EOF Interrupt
16140 +               unsigned int hwtq02_eof         : 1;    // bit 18       GMAC0 HW Tx Queue2 EOF Interrupt
16141 +               unsigned int hwtq01_eof         : 1;    // bit 17       GMAC0 HW Tx Queue1 EOF Interrupt
16142 +               unsigned int hwtq00_eof         : 1;    // bit 16       GMAC0 HW Tx Queue0 EOF Interrupt
16143 +               unsigned int class_rx           : 14;   // bit 15:2     Classification Queue Rx Interrupt
16144 +               unsigned int default_q1_eof     : 1;    // bit 1        Default Queue 1 EOF Interrupt
16145 +               unsigned int default_q0_eof     : 1;    // bit 0        Default Queue 0 EOF Interrupt
16146 +#else
16147 +               unsigned int default_q0_eof     : 1;    // bit 0        Default Queue 0 EOF Interrupt
16148 +               unsigned int default_q1_eof     : 1;    // bit 1        Default Queue 1 EOF Interrupt
16149 +               unsigned int class_rx           : 14;   // bit 15:2     Classification Queue Rx Interrupt
16150 +               unsigned int hwtq00_eof         : 1;    // bit 16       GMAC0 HW Tx Queue0 EOF Interrupt
16151 +               unsigned int hwtq01_eof         : 1;    // bit 17       GMAC0 HW Tx Queue1 EOF Interrupt
16152 +               unsigned int hwtq02_eof         : 1;    // bit 18       GMAC0 HW Tx Queue2 EOF Interrupt
16153 +               unsigned int hwtq03_eof         : 1;    // bit 19       GMAC0 HW Tx Queue3 EOF Interrupt
16154 +               unsigned int hwtq10_eof         : 1;    // bit 20       GMAC1 HW Tx Queue0 EOF Interrupt
16155 +               unsigned int hwtq11_eof         : 1;    // bit 21       GMAC1 HW Tx Queue1 EOF Interrupt
16156 +               unsigned int hwtq12_eof         : 1;    // bit 22       GMAC1 HW Tx Queue2 EOF Interrupt
16157 +               unsigned int hwtq13_eof         : 1;    // bit 23       GMAC1 HW Tx Queue3 EOF Interrupt
16158 +               unsigned int toe_iq0_intr       : 1;    // bit 24       TOE Interrupt Queue 0 with Interrupts
16159 +               unsigned int toe_iq1_intr       : 1;    // bit 25       TOE Interrupt Queue 1 with Interrupts
16160 +               unsigned int toe_iq2_intr       : 1;    // bit 26       TOE Interrupt Queue 2 with Interrupts
16161 +               unsigned int toe_iq3_intr       : 1;    // bit 27       TOE Interrupt Queue 3 with Interrupts
16162 +               unsigned int toe_iq0_full       : 1;    // bit 28       TOE Interrupt Queue 0 Full Interrupt
16163 +               unsigned int toe_iq1_full       : 1;    // bit 29       TOE Interrupt Queue 1 Full Interrupt
16164 +               unsigned int toe_iq2_full       : 1;    // bit 30       TOE Interrupt Queue 2 Full Interrupt
16165 +               unsigned int toe_iq3_full       : 1;    // bit 31       TOE Interrupt Queue 3 Full Interrupt
16166 +#endif
16167 +       } bits;
16168 +} INTR_REG1_T;
16169 +
16170 +#define TOE_IQ3_FULL_INT_BIT           BIT(31)
16171 +#define TOE_IQ2_FULL_INT_BIT           BIT(30)
16172 +#define TOE_IQ1_FULL_INT_BIT           BIT(29)
16173 +#define TOE_IQ0_FULL_INT_BIT           BIT(28)
16174 +#define TOE_IQ3_INT_BIT                                BIT(27)
16175 +#define TOE_IQ2_INT_BIT                                BIT(26)
16176 +#define TOE_IQ1_INT_BIT                                BIT(25)
16177 +#define TOE_IQ0_INT_BIT                                BIT(24)
16178 +#define GMAC1_HWTQ13_EOF_INT_BIT       BIT(23)
16179 +#define GMAC1_HWTQ12_EOF_INT_BIT       BIT(22)
16180 +#define GMAC1_HWTQ11_EOF_INT_BIT       BIT(21)
16181 +#define GMAC1_HWTQ10_EOF_INT_BIT       BIT(20)
16182 +#define GMAC0_HWTQ03_EOF_INT_BIT       BIT(19)
16183 +#define GMAC0_HWTQ02_EOF_INT_BIT       BIT(18)
16184 +#define GMAC0_HWTQ01_EOF_INT_BIT       BIT(17)
16185 +#define GMAC0_HWTQ00_EOF_INT_BIT       BIT(16)
16186 +#define CLASS_RX_INT_BIT(x)                    BIT((x+2))
16187 +#define DEFAULT_Q1_INT_BIT                     BIT(1)
16188 +#define DEFAULT_Q0_INT_BIT                     BIT(0)
16189 +
16190 +#define TOE_IQ_INT_BITS                                (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
16191 +                                                       TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
16192 +#define        TOE_IQ_FULL_BITS                        (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
16193 +                                                       TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
16194 +#define        TOE_IQ_ALL_BITS                         (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
16195 +#define TOE_CLASS_RX_INT_BITS          0xfffc
16196 +
16197 +/**********************************************************************
16198 + * Interrupt Status Register 2         (offset 0x0040)
16199 + * Interrupt Mask Register 2   (offset 0x0044)
16200 + * Interrupt Select Register 2         (offset 0x0048)
16201 + **********************************************************************/
16202 +typedef union
16203 +{
16204 +       unsigned int bits32;
16205 +       struct bit_0040
16206 +       {
16207 +#if (BIG_ENDIAN==1)
16208 +               unsigned int toe_q31_full       : 1;    // bit 31       TOE Queue 31 Full Interrupt
16209 +               unsigned int toe_q30_full       : 1;    // bit 30       TOE Queue 30 Full Interrupt
16210 +               unsigned int toe_q29_full       : 1;    // bit 29       TOE Queue 29 Full Interrupt
16211 +               unsigned int toe_q28_full       : 1;    // bit 28       TOE Queue 28 Full Interrupt
16212 +               unsigned int toe_q27_full       : 1;    // bit 27       TOE Queue 27 Full Interrupt
16213 +               unsigned int toe_q26_full       : 1;    // bit 26       TOE Queue 26 Full Interrupt
16214 +               unsigned int toe_q25_full       : 1;    // bit 25       TOE Queue 25 Full Interrupt
16215 +               unsigned int toe_q24_full       : 1;    // bit 24       TOE Queue 24 Full Interrupt
16216 +               unsigned int toe_q23_full       : 1;    // bit 23       TOE Queue 23 Full Interrupt
16217 +               unsigned int toe_q22_full       : 1;    // bit 22       TOE Queue 22 Full Interrupt
16218 +               unsigned int toe_q21_full       : 1;    // bit 21       TOE Queue 21 Full Interrupt
16219 +               unsigned int toe_q20_full       : 1;    // bit 20       TOE Queue 20 Full Interrupt
16220 +               unsigned int toe_q19_full       : 1;    // bit 19       TOE Queue 19 Full Interrupt
16221 +               unsigned int toe_q18_full       : 1;    // bit 18       TOE Queue 18 Full Interrupt
16222 +               unsigned int toe_q17_full       : 1;    // bit 17       TOE Queue 17 Full Interrupt
16223 +               unsigned int toe_q16_full       : 1;    // bit 16       TOE Queue 16 Full Interrupt
16224 +               unsigned int toe_q15_full       : 1;    // bit 15       TOE Queue 15 Full Interrupt
16225 +               unsigned int toe_q14_full       : 1;    // bit 14       TOE Queue 14 Full Interrupt
16226 +               unsigned int toe_q13_full       : 1;    // bit 13       TOE Queue 13 Full Interrupt
16227 +               unsigned int toe_q12_full       : 1;    // bit 12       TOE Queue 12 Full Interrupt
16228 +               unsigned int toe_q11_full       : 1;    // bit 11       TOE Queue 11 Full Interrupt
16229 +               unsigned int toe_q10_full       : 1;    // bit 10       TOE Queue 10 Full Interrupt
16230 +               unsigned int toe_q9_full        : 1;    // bit 9        TOE Queue 9 Full Interrupt
16231 +               unsigned int toe_q8_full        : 1;    // bit 8        TOE Queue 8 Full Interrupt
16232 +               unsigned int toe_q7_full        : 1;    // bit 7        TOE Queue 7 Full Interrupt
16233 +               unsigned int toe_q6_full        : 1;    // bit 6        TOE Queue 6 Full Interrupt
16234 +               unsigned int toe_q5_full        : 1;    // bit 5        TOE Queue 5 Full Interrupt
16235 +               unsigned int toe_q4_full        : 1;    // bit 4        TOE Queue 4 Full Interrupt
16236 +               unsigned int toe_q3_full        : 1;    // bit 3        TOE Queue 3 Full Interrupt
16237 +               unsigned int toe_q2_full        : 1;    // bit 2        TOE Queue 2 Full Interrupt
16238 +               unsigned int toe_q1_full        : 1;    // bit 1        TOE Queue 1 Full Interrupt
16239 +               unsigned int toe_q0_full        : 1;    // bit 0        TOE Queue 0 Full Interrupt
16240 +#else
16241 +               unsigned int toe_q0_full        : 1;    // bit 0        TOE Queue 0 Full Interrupt
16242 +               unsigned int toe_q1_full        : 1;    // bit 1        TOE Queue 1 Full Interrupt
16243 +               unsigned int toe_q2_full        : 1;    // bit 2        TOE Queue 2 Full Interrupt
16244 +               unsigned int toe_q3_full        : 1;    // bit 3        TOE Queue 3 Full Interrupt
16245 +               unsigned int toe_q4_full        : 1;    // bit 4        TOE Queue 4 Full Interrupt
16246 +               unsigned int toe_q5_full        : 1;    // bit 5        TOE Queue 5 Full Interrupt
16247 +               unsigned int toe_q6_full        : 1;    // bit 6        TOE Queue 6 Full Interrupt
16248 +               unsigned int toe_q7_full        : 1;    // bit 7        TOE Queue 7 Full Interrupt
16249 +               unsigned int toe_q8_full        : 1;    // bit 8        TOE Queue 8 Full Interrupt
16250 +               unsigned int toe_q9_full        : 1;    // bit 9        TOE Queue 9 Full Interrupt
16251 +               unsigned int toe_q10_full       : 1;    // bit 10       TOE Queue 10 Full Interrupt
16252 +               unsigned int toe_q11_full       : 1;    // bit 11       TOE Queue 11 Full Interrupt
16253 +               unsigned int toe_q12_full       : 1;    // bit 12       TOE Queue 12 Full Interrupt
16254 +               unsigned int toe_q13_full       : 1;    // bit 13       TOE Queue 13 Full Interrupt
16255 +               unsigned int toe_q14_full       : 1;    // bit 14       TOE Queue 14 Full Interrupt
16256 +               unsigned int toe_q15_full       : 1;    // bit 15       TOE Queue 15 Full Interrupt
16257 +               unsigned int toe_q16_full       : 1;    // bit 16       TOE Queue 16 Full Interrupt
16258 +               unsigned int toe_q17_full       : 1;    // bit 17       TOE Queue 17 Full Interrupt
16259 +               unsigned int toe_q18_full       : 1;    // bit 18       TOE Queue 18 Full Interrupt
16260 +               unsigned int toe_q19_full       : 1;    // bit 19       TOE Queue 19 Full Interrupt
16261 +               unsigned int toe_q20_full       : 1;    // bit 20       TOE Queue 20 Full Interrupt
16262 +               unsigned int toe_q21_full       : 1;    // bit 21       TOE Queue 21 Full Interrupt
16263 +               unsigned int toe_q22_full       : 1;    // bit 22       TOE Queue 22 Full Interrupt
16264 +               unsigned int toe_q23_full       : 1;    // bit 23       TOE Queue 23 Full Interrupt
16265 +               unsigned int toe_q24_full       : 1;    // bit 24       TOE Queue 24 Full Interrupt
16266 +               unsigned int toe_q25_full       : 1;    // bit 25       TOE Queue 25 Full Interrupt
16267 +               unsigned int toe_q26_full       : 1;    // bit 26       TOE Queue 26 Full Interrupt
16268 +               unsigned int toe_q27_full       : 1;    // bit 27       TOE Queue 27 Full Interrupt
16269 +               unsigned int toe_q28_full       : 1;    // bit 28       TOE Queue 28 Full Interrupt
16270 +               unsigned int toe_q29_full       : 1;    // bit 29       TOE Queue 29 Full Interrupt
16271 +               unsigned int toe_q30_full       : 1;    // bit 30       TOE Queue 30 Full Interrupt
16272 +               unsigned int toe_q31_full       : 1;    // bit 31       TOE Queue 31 Full Interrupt
16273 +#endif
16274 +       } bits;
16275 +} INTR_REG2_T;
16276 +
16277 +#define TOE_QL_FULL_INT_BIT(x)         BIT(x)
16278 +
16279 +/**********************************************************************
16280 + * Interrupt Status Register 3         (offset 0x0050)
16281 + * Interrupt Mask Register 3   (offset 0x0054)
16282 + * Interrupt Select Register 3         (offset 0x0058)
16283 + **********************************************************************/
16284 +typedef union
16285 +{
16286 +       unsigned int bits32;
16287 +       struct bit_0050
16288 +       {
16289 +#if (BIG_ENDIAN==1)
16290 +               unsigned int toe_q63_full       : 1;    // bit 63       TOE Queue 63 Full Interrupt
16291 +               unsigned int toe_q62_full       : 1;    // bit 62       TOE Queue 62 Full Interrupt
16292 +               unsigned int toe_q61_full       : 1;    // bit 61       TOE Queue 61 Full Interrupt
16293 +               unsigned int toe_q60_full       : 1;    // bit 60       TOE Queue 60 Full Interrupt
16294 +               unsigned int toe_q59_full       : 1;    // bit 59       TOE Queue 59 Full Interrupt
16295 +               unsigned int toe_q58_full       : 1;    // bit 58       TOE Queue 58 Full Interrupt
16296 +               unsigned int toe_q57_full       : 1;    // bit 57       TOE Queue 57 Full Interrupt
16297 +               unsigned int toe_q56_full       : 1;    // bit 56       TOE Queue 56 Full Interrupt
16298 +               unsigned int toe_q55_full       : 1;    // bit 55       TOE Queue 55 Full Interrupt
16299 +               unsigned int toe_q54_full       : 1;    // bit 54       TOE Queue 54 Full Interrupt
16300 +               unsigned int toe_q53_full       : 1;    // bit 53       TOE Queue 53 Full Interrupt
16301 +               unsigned int toe_q52_full       : 1;    // bit 52       TOE Queue 52 Full Interrupt
16302 +               unsigned int toe_q51_full       : 1;    // bit 51       TOE Queue 51 Full Interrupt
16303 +               unsigned int toe_q50_full       : 1;    // bit 50       TOE Queue 50 Full Interrupt
16304 +               unsigned int toe_q49_full       : 1;    // bit 49       TOE Queue 49 Full Interrupt
16305 +               unsigned int toe_q48_full       : 1;    // bit 48       TOE Queue 48 Full Interrupt
16306 +               unsigned int toe_q47_full       : 1;    // bit 47       TOE Queue 47 Full Interrupt
16307 +               unsigned int toe_q46_full       : 1;    // bit 46       TOE Queue 46 Full Interrupt
16308 +               unsigned int toe_q45_full       : 1;    // bit 45       TOE Queue 45 Full Interrupt
16309 +               unsigned int toe_q44_full       : 1;    // bit 44       TOE Queue 44 Full Interrupt
16310 +               unsigned int toe_q43_full       : 1;    // bit 43       TOE Queue 43 Full Interrupt
16311 +               unsigned int toe_q42_full       : 1;    // bit 42       TOE Queue 42 Full Interrupt
16312 +               unsigned int toe_q41_full       : 1;    // bit 41       TOE Queue 41 Full Interrupt
16313 +               unsigned int toe_q40_full       : 1;    // bit 40       TOE Queue 40 Full Interrupt
16314 +               unsigned int toe_q39_full       : 1;    // bit 39       TOE Queue 39 Full Interrupt
16315 +               unsigned int toe_q38_full       : 1;    // bit 38       TOE Queue 38 Full Interrupt
16316 +               unsigned int toe_q37_full       : 1;    // bit 37       TOE Queue 37 Full Interrupt
16317 +               unsigned int toe_q36_full       : 1;    // bit 36       TOE Queue 36 Full Interrupt
16318 +               unsigned int toe_q35_full       : 1;    // bit 35       TOE Queue 35 Full Interrupt
16319 +               unsigned int toe_q34_full       : 1;    // bit 34       TOE Queue 34 Full Interrupt
16320 +               unsigned int toe_q33_full       : 1;    // bit 33       TOE Queue 33 Full Interrupt
16321 +               unsigned int toe_q32_full       : 1;    // bit 32       TOE Queue 32 Full Interrupt
16322 +#else
16323 +               unsigned int toe_q32_full       : 1;    // bit 32       TOE Queue 32 Full Interrupt
16324 +               unsigned int toe_q33_full       : 1;    // bit 33       TOE Queue 33 Full Interrupt
16325 +               unsigned int toe_q34_full       : 1;    // bit 34       TOE Queue 34 Full Interrupt
16326 +               unsigned int toe_q35_full       : 1;    // bit 35       TOE Queue 35 Full Interrupt
16327 +               unsigned int toe_q36_full       : 1;    // bit 36       TOE Queue 36 Full Interrupt
16328 +               unsigned int toe_q37_full       : 1;    // bit 37       TOE Queue 37 Full Interrupt
16329 +               unsigned int toe_q38_full       : 1;    // bit 38       TOE Queue 38 Full Interrupt
16330 +               unsigned int toe_q39_full       : 1;    // bit 39       TOE Queue 39 Full Interrupt
16331 +               unsigned int toe_q40_full       : 1;    // bit 40       TOE Queue 40 Full Interrupt
16332 +               unsigned int toe_q41_full       : 1;    // bit 41       TOE Queue 41 Full Interrupt
16333 +               unsigned int toe_q42_full       : 1;    // bit 42       TOE Queue 42 Full Interrupt
16334 +               unsigned int toe_q43_full       : 1;    // bit 43       TOE Queue 43 Full Interrupt
16335 +               unsigned int toe_q44_full       : 1;    // bit 44       TOE Queue 44 Full Interrupt
16336 +               unsigned int toe_q45_full       : 1;    // bit 45       TOE Queue 45 Full Interrupt
16337 +               unsigned int toe_q46_full       : 1;    // bit 46       TOE Queue 46 Full Interrupt
16338 +               unsigned int toe_q47_full       : 1;    // bit 47       TOE Queue 47 Full Interrupt
16339 +               unsigned int toe_q48_full       : 1;    // bit 48       TOE Queue 48 Full Interrupt
16340 +               unsigned int toe_q49_full       : 1;    // bit 49       TOE Queue 49 Full Interrupt
16341 +               unsigned int toe_q50_full       : 1;    // bit 50       TOE Queue 50 Full Interrupt
16342 +               unsigned int toe_q51_full       : 1;    // bit 51       TOE Queue 51 Full Interrupt
16343 +               unsigned int toe_q52_full       : 1;    // bit 52       TOE Queue 52 Full Interrupt
16344 +               unsigned int toe_q53_full       : 1;    // bit 53       TOE Queue 53 Full Interrupt
16345 +               unsigned int toe_q54_full       : 1;    // bit 54       TOE Queue 54 Full Interrupt
16346 +               unsigned int toe_q55_full       : 1;    // bit 55       TOE Queue 55 Full Interrupt
16347 +               unsigned int toe_q56_full       : 1;    // bit 56       TOE Queue 56 Full Interrupt
16348 +               unsigned int toe_q57_full       : 1;    // bit 57       TOE Queue 57 Full Interrupt
16349 +               unsigned int toe_q58_full       : 1;    // bit 58       TOE Queue 58 Full Interrupt
16350 +               unsigned int toe_q59_full       : 1;    // bit 59       TOE Queue 59 Full Interrupt
16351 +               unsigned int toe_q60_full       : 1;    // bit 60       TOE Queue 60 Full Interrupt
16352 +               unsigned int toe_q61_full       : 1;    // bit 61       TOE Queue 61 Full Interrupt
16353 +               unsigned int toe_q62_full       : 1;    // bit 62       TOE Queue 62 Full Interrupt
16354 +               unsigned int toe_q63_full       : 1;    // bit 63       TOE Queue 63 Full Interrupt
16355 +#endif
16356 +       } bits;
16357 +} INTR_REG3_T;
16358 +
16359 +#define TOE_QH_FULL_INT_BIT(x)         BIT(x-32)
16360 +
16361 +/**********************************************************************
16362 + * Interrupt Status Register 4         (offset 0x0060)
16363 + * Interrupt Mask Register 4   (offset 0x0064)
16364 + * Interrupt Select Register 4         (offset 0x0068)
16365 + **********************************************************************/
16366 +typedef union
16367 +{
16368 +       unsigned char byte;
16369 +       struct bit_0060
16370 +       {
16371 +#if (BIG_ENDIAN==1)
16372 +               unsigned char reserved          : 1;    //
16373 +               unsigned char cnt_full          : 1;    // MIB counters half full interrupt
16374 +               unsigned char rx_pause_on       : 1;    // received pause on frame interrupt
16375 +               unsigned char tx_pause_on       : 1;    // transmit pause on frame interrupt
16376 +               unsigned char rx_pause_off  : 1;        // received pause off frame interrupt
16377 +               unsigned char tx_pause_off      : 1;    // received pause off frame interrupt
16378 +               unsigned char rx_overrun        : 1;    // GMAC Rx FIFO overrun interrupt
16379 +               unsigned char status_changed: 1;        // Status Changed Intr for RGMII Mode
16380 +#else
16381 +               unsigned char status_changed: 1;        // Status Changed Intr for RGMII Mode
16382 +               unsigned char rx_overrun        : 1;   // GMAC Rx FIFO overrun interrupt
16383 +               unsigned char tx_pause_off      : 1;    // received pause off frame interrupt
16384 +               unsigned char rx_pause_off  : 1;        // received pause off frame interrupt
16385 +               unsigned char tx_pause_on       : 1;    // transmit pause on frame interrupt
16386 +               unsigned char rx_pause_on       : 1;    // received pause on frame interrupt
16387 +               unsigned char cnt_full          : 1;    // MIB counters half full interrupt
16388 +               unsigned char reserved          : 1;    //
16389 +#endif
16390 +       } _PACKED_ bits;
16391 +} _PACKED_ GMAC_INTR_T;
16392 +
16393 +typedef union
16394 +{
16395 +       unsigned int bits32;
16396 +       struct bit_0060_2
16397 +       {
16398 +#if (BIG_ENDIAN==1)
16399 +               GMAC_INTR_T             gmac1;
16400 +               GMAC_INTR_T             gmac0;
16401 +               unsigned int    class_qf_int: 14;       // bit 15:2 Classification Rx Queue13-0 Full Intr.
16402 +               unsigned int    hwfq_empty      : 1;    // bit 1        Hardware Free Queue Empty Intr.
16403 +               unsigned int    swfq_empty      : 1;    // bit 0        Software Free Queue Empty Intr.
16404 +#else
16405 +#endif
16406 +               unsigned int    swfq_empty      : 1;    // bit 0        Software Free Queue Empty Intr.
16407 +               unsigned int    hwfq_empty      : 1;    // bit 1        Hardware Free Queue Empty Intr.
16408 +               unsigned int    class_qf_int: 14;       // bit 15:2 Classification Rx Queue13-0 Full Intr.
16409 +               GMAC_INTR_T             gmac0;
16410 +               GMAC_INTR_T             gmac1;
16411 +       } bits;
16412 +} INTR_REG4_T;
16413 +
16414 +#define GMAC1_RESERVED_INT_BIT         BIT(31)
16415 +#define GMAC1_MIB_INT_BIT                      BIT(30)
16416 +#define GMAC1_RX_PAUSE_ON_INT_BIT      BIT(29)
16417 +#define GMAC1_TX_PAUSE_ON_INT_BIT      BIT(28)
16418 +#define GMAC1_RX_PAUSE_OFF_INT_BIT     BIT(27)
16419 +#define GMAC1_TX_PAUSE_OFF_INT_BIT     BIT(26)
16420 +#define GMAC1_RX_OVERRUN_INT_BIT       BIT(25)
16421 +#define GMAC1_STATUS_CHANGE_INT_BIT    BIT(24)
16422 +#define GMAC0_RESERVED_INT_BIT         BIT(23)
16423 +#define GMAC0_MIB_INT_BIT                      BIT(22)
16424 +#define GMAC0_RX_PAUSE_ON_INT_BIT      BIT(21)
16425 +#define GMAC0_TX_PAUSE_ON_INT_BIT      BIT(20)
16426 +#define GMAC0_RX_PAUSE_OFF_INT_BIT     BIT(19)
16427 +#define GMAC0_TX_PAUSE_OFF_INT_BIT     BIT(18)
16428 +#define GMAC0_RX_OVERRUN_INT_BIT       BIT(17)
16429 +#define GMAC0_STATUS_CHANGE_INT_BIT    BIT(16)
16430 +#define CLASS_RX_FULL_INT_BIT(x)       BIT((x+2))
16431 +#define HWFQ_EMPTY_INT_BIT                     BIT(1)
16432 +#define SWFQ_EMPTY_INT_BIT                     BIT(0)
16433 +
16434 +#if 1
16435 +#define GMAC0_INT_BITS                         (GMAC0_MIB_INT_BIT)
16436 +#define GMAC1_INT_BITS                         (GMAC1_MIB_INT_BIT)
16437 +#else
16438 +#define GMAC0_INT_BITS                         (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
16439 +                                                                        GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT |        \
16440 +                                                                        GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT |      \
16441 +                                                                        GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
16442 +#define GMAC1_INT_BITS                         (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
16443 +                                                                        GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT |        \
16444 +                                                                        GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT |      \
16445 +                                                                        GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
16446 +#endif
16447 +
16448 +#define CLASS_RX_FULL_INT_BITS         0xfffc
16449 +
16450 +/**********************************************************************
16451 + * GLOBAL_QUEUE_THRESHOLD_REG  (offset 0x0070)
16452 + **********************************************************************/
16453 +typedef union
16454 +{
16455 +       unsigned int bits32;
16456 +       struct bit_0070_2
16457 +       {
16458 +#if (BIG_ENDIAN==1)
16459 +               unsigned int    toe_class       : 8;    // 31:24
16460 +               unsigned int    intrq           : 8;    // 23:16
16461 +               unsigned int    hwfq_empty      : 8;    // 15:8         Hardware Free Queue Empty Threshold
16462 +               unsigned int    swfq_empty      : 8;    //  7:0         Software Free Queue Empty Threshold
16463 +#else
16464 +#endif
16465 +               unsigned int    swfq_empty      : 8;    //  7:0         Software Free Queue Empty Threshold
16466 +               unsigned int    hwfq_empty      : 8;    // 15:8         Hardware Free Queue Empty Threshold
16467 +               unsigned int    intrq           : 8;    // 23:16
16468 +               unsigned int    toe_class       : 8;    // 31:24
16469 +       } bits;
16470 +} QUEUE_THRESHOLD_T;
16471 +
16472 +
16473 +/**********************************************************************
16474 + * GMAC DMA Control Register
16475 + * GMAC0 offset 0x8000
16476 + * GMAC1 offset 0xC000
16477 + **********************************************************************/
16478 +typedef union
16479 +{
16480 +       unsigned int bits32;
16481 +       struct bit_8000
16482 +       {
16483 +#if (BIG_ENDIAN==1)
16484 +               unsigned int    rd_enable               : 1;    // bit 31       Rx DMA Enable
16485 +               unsigned int    td_enable               : 1;    // bit 30       Tx DMA Enable
16486 +               unsigned int    loopback                : 1;    // bit 29       Loopback TxDMA to RxDMA
16487 +               unsigned int    drop_small_ack  : 1;    // bit 28       1: Drop, 0: Accept
16488 +               unsigned int    reserved                : 10;   // bit 27:18
16489 +               unsigned int    rd_insert_bytes : 2;    // bit 17:16
16490 +               unsigned int    rd_prot                 : 4;    // bit 15:12 DMA Protection Control
16491 +               unsigned int    rd_burst_size   : 2;    // bit 11:10 DMA max burst size for every AHB request
16492 +               unsigned int    rd_bus              : 2;        // bit 9:8      Peripheral Bus Width
16493 +               unsigned int    td_prot                 : 4;    // bit 7:4  TxDMA protection control
16494 +               unsigned int    td_burst_size   : 2;    // bit 3:2      TxDMA max burst size for every AHB request
16495 +               unsigned int    td_bus              : 2;        // bit 1:0  Peripheral Bus Width
16496 +#else
16497 +               unsigned int    td_bus              : 2;        // bit 1:0  Peripheral Bus Width
16498 +               unsigned int    td_burst_size   : 2;    // bit 3:2      TxDMA max burst size for every AHB request
16499 +               unsigned int    td_prot                 : 4;    // bit 7:4  TxDMA protection control
16500 +               unsigned int    rd_bus              : 2;        // bit 9:8      Peripheral Bus Width
16501 +               unsigned int    rd_burst_size   : 2;    // bit 11:10 DMA max burst size for every AHB request
16502 +               unsigned int    rd_prot                 : 4;    // bit 15:12 DMA Protection Control
16503 +               unsigned int    rd_insert_bytes : 2;    // bit 17:16
16504 +               unsigned int    reserved                : 10;   // bit 27:18
16505 +               unsigned int    drop_small_ack  : 1;    // bit 28       1: Drop, 0: Accept
16506 +               unsigned int    loopback                : 1;    // bit 29       Loopback TxDMA to RxDMA
16507 +               unsigned int    td_enable               : 1;    // bit 30       Tx DMA Enable
16508 +               unsigned int    rd_enable               : 1;    // bit 31       Rx DMA Enable
16509 +#endif
16510 +       } bits;
16511 +} GMAC_DMA_CTRL_T;
16512 +
16513 +/**********************************************************************
16514 + * GMAC Tx Weighting Control Register 0
16515 + * GMAC0 offset 0x8004
16516 + * GMAC1 offset 0xC004
16517 + **********************************************************************/
16518 +typedef union
16519 +{
16520 +       unsigned int bits32;
16521 +       struct bit_8004
16522 +       {
16523 +#if (BIG_ENDIAN==1)
16524 +               unsigned int    reserved                : 8;    // bit 31:24
16525 +               unsigned int    hw_tq3                  : 6;    // bit 23:18    HW TX Queue 0
16526 +               unsigned int    hw_tq2                  : 6;    // bit 17:12    HW TX Queue 1
16527 +               unsigned int    hw_tq1                  : 6;    // bit 11:6             HW TX Queue 2
16528 +               unsigned int    hw_tq0                  : 6;    // bit 5:0              HW TX Queue 3
16529 +#else
16530 +               unsigned int    hw_tq0                  : 6;    // bit 5:0              HW TX Queue 3
16531 +               unsigned int    hw_tq1                  : 6;    // bit 11:6             HW TX Queue 2
16532 +               unsigned int    hw_tq2                  : 6;    // bit 17:12    HW TX Queue 1
16533 +               unsigned int    hw_tq3                  : 6;    // bit 23:18    HW TX Queue 0
16534 +               unsigned int    reserved                : 8;    // bit 31:24
16535 +#endif
16536 +       } bits;
16537 +} GMAC_TX_WCR0_T;      // Weighting Control Register 0
16538 +
16539 +/**********************************************************************
16540 + * GMAC Tx Weighting Control Register 1
16541 + * GMAC0 offset 0x8008
16542 + * GMAC1 offset 0xC008
16543 + **********************************************************************/
16544 +typedef union
16545 +{
16546 +       unsigned int bits32;
16547 +       struct bit_8008
16548 +       {
16549 +#if (BIG_ENDIAN==1)
16550 +               unsigned int    reserved                : 2;    // bit 31:30
16551 +               unsigned int    sw_tq5                  : 5;    // bit 29:25    SW TX Queue 5
16552 +               unsigned int    sw_tq4                  : 5;    // bit 24:20    SW TX Queue 4
16553 +               unsigned int    sw_tq3                  : 5;    // bit 19:15    SW TX Queue 3
16554 +               unsigned int    sw_tq2                  : 5;    // bit 14:10    SW TX Queue 2
16555 +               unsigned int    sw_tq1                  : 5;    // bit 9:5              SW TX Queue 1
16556 +               unsigned int    sw_tq0                  : 5;    // bit 4:0              SW TX Queue 0
16557 +#else
16558 +               unsigned int    sw_tq0                  : 5;    // bit 4:0              SW TX Queue 0
16559 +               unsigned int    sw_tq1                  : 5;    // bit 9:5              SW TX Queue 1
16560 +               unsigned int    sw_tq2                  : 5;    // bit 14:10    SW TX Queue 2
16561 +               unsigned int    sw_tq3                  : 5;    // bit 19:15    SW TX Queue 3
16562 +               unsigned int    sw_tq4                  : 5;    // bit 24:20    SW TX Queue 4
16563 +               unsigned int    sw_tq5                  : 5;    // bit 29:25    SW TX Queue 5
16564 +               unsigned int    reserved                : 2;    // bit 31:30
16565 +#endif
16566 +       } bits;
16567 +} GMAC_TX_WCR1_T;      // Weighting Control Register 1
16568 +
16569 +/**********************************************************************
16570 + * Queue Read/Write Pointer
16571 + * GMAC SW TX Queue 0~5 Read/Write Pointer register
16572 + * GMAC0 offset 0x800C ~ 0x8020
16573 + * GMAC1 offset 0xC00C ~ 0xC020
16574 + * GMAC HW TX Queue 0~3 Read/Write Pointer register
16575 + * GMAC0 offset 0x8024 ~ 0x8030
16576 + * GMAC1 offset 0xC024 ~ 0xC030
16577 + **********************************************************************/
16578 +// see DMA_RWPTR_T structure
16579 +
16580 +/**********************************************************************
16581 + * GMAC DMA Tx First Description Address Register
16582 + * GMAC0 offset 0x8038
16583 + * GMAC1 offset 0xC038
16584 + **********************************************************************/
16585 +typedef union
16586 +{
16587 +       unsigned int bits32;
16588 +       struct bit_8038
16589 +       {
16590 +#if (BIG_ENDIAN==1)
16591 +               unsigned int td_first_des_ptr   : 28;   // bit 31:4     first descriptor address
16592 +               unsigned int td_busy                    :  1;   // bit 3        1: TxDMA busy; 0: TxDMA idle
16593 +               unsigned int reserved                   :  3;
16594 +#else
16595 +               unsigned int reserved                   :  3;
16596 +               unsigned int td_busy                    :  1;   // bit 3        1: TxDMA busy; 0: TxDMA idle
16597 +               unsigned int td_first_des_ptr   : 28;   // bit 31:4     first descriptor address
16598 +#endif
16599 +       } bits;
16600 +} GMAC_TXDMA_FIRST_DESC_T;
16601 +
16602 +/**********************************************************************
16603 + * GMAC DMA Tx Current Description Address Register
16604 + * GMAC0 offset 0x803C
16605 + * GMAC1 offset 0xC03C
16606 + **********************************************************************/
16607 +typedef union
16608 +{
16609 +       unsigned int bits32;
16610 +       struct bit_803C
16611 +       {
16612 +#if (BIG_ENDIAN==1)
16613 +               unsigned int td_curr_desc_ptr   : 28;   // bit 31:4     current descriptor address
16614 +               unsigned int reserved                   :  4;
16615 +#else
16616 +               unsigned int reserved                   :  4;
16617 +               unsigned int td_curr_desc_ptr   : 28;   // bit 31:4     current descriptor address
16618 +#endif
16619 +       } bits;
16620 +} GMAC_TXDMA_CURR_DESC_T;
16621 +
16622 +/**********************************************************************
16623 + * GMAC DMA Tx Description Word 0 Register
16624 + * GMAC0 offset 0x8040
16625 + * GMAC1 offset 0xC040
16626 + **********************************************************************/
16627 +typedef union
16628 +{
16629 +       unsigned int bits32;
16630 +       struct bit_8040
16631 +       {
16632 +#if (BIG_ENDIAN==1)
16633 +               unsigned int reserved           : 1;    // bit 31
16634 +               unsigned int derr                       : 1;    // bit 30        data error during processing this descriptor
16635 +               unsigned int perr                       : 1;    // bit 29        protocol error during processing this descriptor
16636 +               unsigned int status_rvd         : 6;    // bit 28:23 Tx Status, Reserved bits
16637 +               unsigned int status_tx_ok       : 1;    // bit 22    Tx Status, 1: Successful 0: Failed
16638 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
16639 +               unsigned int buffer_size        : 16;   // bit 15:0  Transfer size
16640 +#else
16641 +               unsigned int buffer_size        : 16;   // bit 15:0  Transfer size
16642 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
16643 +               unsigned int status_tx_ok       : 1;    // bit 22    Tx Status, 1: Successful 0: Failed
16644 +               unsigned int status_rvd         : 6;    // bit 28:23 Tx Status, Reserved bits
16645 +               unsigned int perr                       : 1;    // bit 29        protocol error during processing this descriptor
16646 +               unsigned int derr                       : 1;    // bit 30        data error during processing this descriptor
16647 +               unsigned int reserved           : 1;    // bit 31
16648 +#endif
16649 +       } bits;
16650 +} GMAC_TXDESC_0_T;
16651 +
16652 +/**********************************************************************
16653 + * GMAC DMA Tx Description Word 1 Register
16654 + * GMAC0 offset 0x8044
16655 + * GMAC1 offset 0xC044
16656 + **********************************************************************/
16657 +typedef union
16658 +{
16659 +       unsigned int bits32;
16660 +       struct txdesc_word1
16661 +       {
16662 +#if (BIG_ENDIAN==1)
16663 +               unsigned int    reserved        : 9;    // bit 31:23    Tx Flag, Reserved
16664 +               unsigned int    ip_fixed_len: 1;        // bit 22
16665 +               unsigned int    bypass_tss      : 1;    // bit 21
16666 +               unsigned int    udp_chksum      : 1;    // bit 20               UDP Checksum Enable
16667 +               unsigned int    tcp_chksum      : 1;    // bit 19               TCP Checksum Enable
16668 +               unsigned int    ipv6_enable     : 1;    // bit 18               IPV6 Tx Enable
16669 +               unsigned int    ip_chksum       : 1;    // bit 17               IPV4 Header Checksum Enable
16670 +               unsigned int    mtu_enable      : 1;    // bit 16               TSS segmentation use MTU setting
16671 +               unsigned int    byte_count      : 16;   // bit 15: 0    Tx Frame Byte Count
16672 +#else
16673 +               unsigned int    byte_count      : 16;   // bit 15: 0    Tx Frame Byte Count
16674 +               unsigned int    mtu_enable      : 1;    // bit 16               TSS segmentation use MTU setting
16675 +               unsigned int    ip_chksum       : 1;    // bit 17               IPV4 Header Checksum Enable
16676 +               unsigned int    ipv6_enable     : 1;    // bit 18               IPV6 Tx Enable
16677 +               unsigned int    tcp_chksum      : 1;    // bit 19               TCP Checksum Enable
16678 +               unsigned int    udp_chksum      : 1;    // bit 20               UDP Checksum Enable
16679 +               unsigned int    bypass_tss      : 1;    // bit 21
16680 +               unsigned int    ip_fixed_len: 1;        // bit 22
16681 +               unsigned int    reserved        : 9;    // bit 31:23    Tx Flag, Reserved
16682 +#endif
16683 +       } bits;
16684 +} GMAC_TXDESC_1_T;
16685 +
16686 +#define TSS_IP_FIXED_LEN_BIT   BIT(22)
16687 +#define TSS_UDP_CHKSUM_BIT             BIT(20)
16688 +#define TSS_TCP_CHKSUM_BIT             BIT(19)
16689 +#define TSS_IPV6_ENABLE_BIT            BIT(18)
16690 +#define TSS_IP_CHKSUM_BIT              BIT(17)
16691 +#define TSS_MTU_ENABLE_BIT             BIT(16)
16692 +
16693 +/**********************************************************************
16694 + * GMAC DMA Tx Description Word 2 Register
16695 + * GMAC0 offset 0x8048
16696 + * GMAC1 offset 0xC048
16697 + **********************************************************************/
16698 +typedef union
16699 +{
16700 +       unsigned int    bits32;
16701 +       unsigned int    buf_adr;
16702 +} GMAC_TXDESC_2_T;
16703 +
16704 +/**********************************************************************
16705 + * GMAC DMA Tx Description Word 3 Register
16706 + * GMAC0 offset 0x804C
16707 + * GMAC1 offset 0xC04C
16708 + **********************************************************************/
16709 +typedef union
16710 +{
16711 +       unsigned int bits32;
16712 +       struct txdesc_word3
16713 +       {
16714 +#if (BIG_ENDIAN==1)
16715 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
16716 +               unsigned int    eofie           : 1;    // bit 29               End of frame interrupt enable
16717 +               unsigned int    reserved        : 18;   // bit 28:11
16718 +               unsigned int    mtu_size        : 11;   // bit 10: 0    Tx Frame Byte Count
16719 +#else
16720 +               unsigned int    mtu_size        : 11;   // bit 10: 0    Tx Frame Byte Count
16721 +               unsigned int    reserved        : 18;   // bit 28:11
16722 +               unsigned int    eofie           : 1;    // bit 29               End of frame interrupt enable
16723 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
16724 +#endif
16725 +       } bits;
16726 +} GMAC_TXDESC_3_T;
16727 +#define SOF_EOF_BIT_MASK       0x3fffffff
16728 +#define SOF_BIT                                0x80000000
16729 +#define EOF_BIT                                0x40000000
16730 +#define EOFIE_BIT                      BIT(29)
16731 +#define MTU_SIZE_BIT_MASK      0x7ff
16732 +
16733 +/**********************************************************************
16734 + * GMAC Tx Descriptor
16735 + **********************************************************************/
16736 +typedef struct
16737 +{
16738 +       GMAC_TXDESC_0_T word0;
16739 +       GMAC_TXDESC_1_T word1;
16740 +       GMAC_TXDESC_2_T word2;
16741 +       GMAC_TXDESC_3_T word3;
16742 +} GMAC_TXDESC_T;
16743 +
16744 +
16745 +/**********************************************************************
16746 + * GMAC DMA Rx First Description Address Register
16747 + * GMAC0 offset 0x8058
16748 + * GMAC1 offset 0xC058
16749 + **********************************************************************/
16750 +typedef union
16751 +{
16752 +       unsigned int bits32;
16753 +       struct bit_8058
16754 +       {
16755 +#if (BIG_ENDIAN==1)
16756 +               unsigned int rd_first_des_ptr   : 28;   // bit 31:4 first descriptor address
16757 +               unsigned int rd_busy                    :  1;   // bit 3        1-RxDMA busy; 0-RxDMA idle
16758 +               unsigned int reserved                   :  3;   // bit 2:0
16759 +#else
16760 +               unsigned int reserved                   :  3;   // bit 2:0
16761 +               unsigned int rd_busy                    :  1;   // bit 3        1-RxDMA busy; 0-RxDMA idle
16762 +               unsigned int rd_first_des_ptr   : 28;   // bit 31:4 first descriptor address
16763 +#endif
16764 +       } bits;
16765 +} GMAC_RXDMA_FIRST_DESC_T;
16766 +
16767 +/**********************************************************************
16768 + * GMAC DMA Rx Current Description Address Register
16769 + * GMAC0 offset 0x805C
16770 + * GMAC1 offset 0xC05C
16771 + **********************************************************************/
16772 +typedef union
16773 +{
16774 +       unsigned int bits32;
16775 +       struct bit_805C
16776 +       {
16777 +#if (BIG_ENDIAN==1)
16778 +               unsigned int rd_curr_des_ptr    : 28;   // bit 31:4 current descriptor address
16779 +               unsigned int reserved                   :  4;   // bit 3:0
16780 +#else
16781 +               unsigned int reserved                   :  4;   // bit 3:0
16782 +               unsigned int rd_curr_des_ptr    : 28;   // bit 31:4 current descriptor address
16783 +#endif
16784 +       } bits;
16785 +} GMAC_RXDMA_CURR_DESC_T;
16786 +
16787 +/**********************************************************************
16788 + * GMAC DMA Rx Description Word 0 Register
16789 + * GMAC0 offset 0x8060
16790 + * GMAC1 offset 0xC060
16791 + **********************************************************************/
16792 +typedef union
16793 +{
16794 +       unsigned int bits32;
16795 +       struct bit_8060
16796 +       {
16797 +#if (BIG_ENDIAN==1)
16798 +               unsigned int drop                       : 1;    // bit 31        TOE/CIS Queue Full dropped packet to default queue
16799 +               unsigned int derr                       : 1;    // bit 30        data error during processing this descriptor
16800 +               unsigned int perr                       : 1;    // bit 29        protocol error during processing this descriptor
16801 +               unsigned int chksum_status      : 3;    // bit 28:26 Check Sum Status
16802 +               unsigned int status                     : 4;    // bit 24:22 Status of rx frame
16803 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
16804 +               unsigned int buffer_size        : 16;   // bit 15:0  number of descriptors used for the current frame
16805 +#else
16806 +               unsigned int buffer_size        : 16;   // bit 15:0  number of descriptors used for the current frame
16807 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
16808 +               unsigned int status                     : 4;    // bit 24:22 Status of rx frame
16809 +               unsigned int chksum_status      : 3;    // bit 28:26 Check Sum Status
16810 +               unsigned int perr                       : 1;    // bit 29        protocol error during processing this descriptor
16811 +               unsigned int derr                       : 1;    // bit 30        data error during processing this descriptor
16812 +               unsigned int drop                       : 1;    // bit 31        TOE/CIS Queue Full dropped packet to default queue
16813 +#endif
16814 +       } bits;
16815 +} GMAC_RXDESC_0_T;
16816 +
16817 +#define                GMAC_RXDESC_0_T_derr                            BIT(30)
16818 +#define                GMAC_RXDESC_0_T_perr                            BIT(29)
16819 +#define                GMAC_RXDESC_0_T_chksum_status(x)        BIT((x+26))
16820 +#define                GMAC_RXDESC_0_T_status(x)                       BIT((x+22))
16821 +#define                GMAC_RXDESC_0_T_desc_count(x)           BIT((x+16))
16822 +
16823 +#define        RX_CHKSUM_IP_UDP_TCP_OK                 0
16824 +#define        RX_CHKSUM_IP_OK_ONLY                    1
16825 +#define        RX_CHKSUM_NONE                                  2
16826 +#define        RX_CHKSUM_IP_ERR_UNKNOWN                4
16827 +#define        RX_CHKSUM_IP_ERR                                5
16828 +#define        RX_CHKSUM_TCP_UDP_ERR                   6
16829 +#define RX_CHKSUM_NUM                                  8
16830 +
16831 +#define RX_STATUS_GOOD_FRAME                   0
16832 +#define RX_STATUS_TOO_LONG_GOOD_CRC            1
16833 +#define RX_STATUS_RUNT_FRAME                   2
16834 +#define RX_STATUS_SFD_NOT_FOUND                        3
16835 +#define RX_STATUS_CRC_ERROR                            4
16836 +#define RX_STATUS_TOO_LONG_BAD_CRC             5
16837 +#define RX_STATUS_ALIGNMENT_ERROR              6
16838 +#define RX_STATUS_TOO_LONG_BAD_ALIGN   7
16839 +#define RX_STATUS_RX_ERR                               8
16840 +#define RX_STATUS_DA_FILTERED                  9
16841 +#define RX_STATUS_BUFFER_FULL                  10
16842 +#define RX_STATUS_NUM                                  16
16843 +
16844 +
16845 +/**********************************************************************
16846 + * GMAC DMA Rx Description Word 1 Register
16847 + * GMAC0 offset 0x8064
16848 + * GMAC1 offset 0xC064
16849 + **********************************************************************/
16850 +typedef union
16851 +{
16852 +       unsigned int bits32;
16853 +       struct rxdesc_word1
16854 +       {
16855 +#if (BIG_ENDIAN==1)
16856 +               unsigned int    sw_id           : 16;   // bit 31:16    Software ID
16857 +               unsigned int    byte_count      : 16;   // bit 15: 0    Rx Frame Byte Count
16858 +#else
16859 +               unsigned int    byte_count      : 16;   // bit 15: 0    Rx Frame Byte Count
16860 +               unsigned int    sw_id           : 16;   // bit 31:16    Software ID
16861 +#endif
16862 +       } bits;
16863 +} GMAC_RXDESC_1_T;
16864 +
16865 +/**********************************************************************
16866 + * GMAC DMA Rx Description Word 2 Register
16867 + * GMAC0 offset 0x8068
16868 + * GMAC1 offset 0xC068
16869 + **********************************************************************/
16870 +typedef union
16871 +{
16872 +       unsigned int    bits32;
16873 +       unsigned int    buf_adr;
16874 +} GMAC_RXDESC_2_T;
16875 +
16876 +#define RX_INSERT_NONE         0
16877 +#define RX_INSERT_1_BYTE       1
16878 +#define RX_INSERT_2_BYTE       2
16879 +#define RX_INSERT_3_BYTE       3
16880 +
16881 +#define RX_INSERT_BYTES                RX_INSERT_2_BYTE
16882 +/**********************************************************************
16883 + * GMAC DMA Rx Description Word 3 Register
16884 + * GMAC0 offset 0x806C
16885 + * GMAC1 offset 0xC06C
16886 + **********************************************************************/
16887 +typedef union
16888 +{
16889 +       unsigned int bits32;
16890 +       struct rxdesc_word3
16891 +       {
16892 +#if (BIG_ENDIAN==1)
16893 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
16894 +               unsigned int    eofie           : 1;    // bit 29               End of frame interrupt enable
16895 +               unsigned int    ctrl_flag       : 1;    // bit 28               Control Flag is present
16896 +               unsigned int    out_of_seq      : 1;    // bit 27               Out of Sequence packet
16897 +               unsigned int    option          : 1;    // bit 26               IPV4 option or IPV6 extension header
16898 +               unsigned int    abnormal        : 1;    // bit 25               abnormal case found
16899 +               unsigned int    dup_ack         : 1;    // bit 24               Duplicated ACK detected
16900 +               unsigned int    l7_offset       : 8;    // bit 23: 16   L7 data offset
16901 +               unsigned int    l4_offset       : 8;    // bit 15: 8    L4 data offset
16902 +               unsigned int    l3_offset       : 8;    // bit 7: 0             L3 data offset
16903 +#else
16904 +               unsigned int    l3_offset       : 8;    // bit 7: 0             L3 data offset
16905 +               unsigned int    l4_offset       : 8;    // bit 15: 8    L4 data offset
16906 +               unsigned int    l7_offset       : 8;    // bit 23: 16   L7 data offset
16907 +               unsigned int    dup_ack         : 1;    // bit 24               Duplicated ACK detected
16908 +               unsigned int    abnormal        : 1;    // bit 25               abnormal case found
16909 +               unsigned int    option          : 1;    // bit 26               IPV4 option or IPV6 extension header
16910 +               unsigned int    out_of_seq      : 1;    // bit 27               Out of Sequence packet
16911 +               unsigned int    ctrl_flag       : 1;    // bit 28               Control Flag is present
16912 +               unsigned int    eofie           : 1;    // bit 29               End of frame interrupt enable
16913 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
16914 +#endif
16915 +       } bits;
16916 +} GMAC_RXDESC_3_T;
16917 +
16918 +/**********************************************************************
16919 + * GMAC Rx Descriptor
16920 + **********************************************************************/
16921 +typedef struct
16922 +{
16923 +       GMAC_RXDESC_0_T word0;
16924 +       GMAC_RXDESC_1_T word1;
16925 +       GMAC_RXDESC_2_T word2;
16926 +       GMAC_RXDESC_3_T word3;
16927 +} GMAC_RXDESC_T;
16928 +
16929 +/**********************************************************************
16930 + * GMAC Hash Engine Enable/Action Register 0 Offset Register
16931 + * GMAC0 offset 0x8070
16932 + * GMAC1 offset 0xC070
16933 + **********************************************************************/
16934 +typedef union
16935 +{
16936 +       unsigned int bits32;
16937 +       struct bit_8070
16938 +       {
16939 +#if (BIG_ENDIAN==1)
16940 +               unsigned int    mr1en           : 1;    // bit 31               Enable Matching Rule 1
16941 +               unsigned int    reserved1       : 1;    // bit 30
16942 +               unsigned int    timing          : 3;    // bit 29:27
16943 +               unsigned int    mr1_action      : 5;    // bit 26:22    Matching Rule 1 action offset
16944 +               unsigned int    mr1hel          : 6;    // bit 21:16    match rule 1 hash entry size
16945 +               unsigned int    mr0en           : 1;    // bit 15               Enable Matching Rule 0
16946 +               unsigned int    reserved0       : 4;    // bit 14:11
16947 +               unsigned int    mr0_action      : 5;    // bit 10:6             Matching Rule 0 action offset
16948 +               unsigned int    mr0hel          : 6;    // bit 5:0              match rule 0 hash entry size
16949 +#else
16950 +               unsigned int    mr0hel          : 6;    // bit 5:0              match rule 0 hash entry size
16951 +               unsigned int    mr0_action      : 5;    // bit 10:6             Matching Rule 0 action offset
16952 +               unsigned int    reserved0       : 4;    // bit 14:11
16953 +               unsigned int    mr0en           : 1;    // bit 15               Enable Matching Rule 0
16954 +               unsigned int    mr1hel          : 6;    // bit 21:16    match rule 1 hash entry size
16955 +               unsigned int    mr1_action      : 5;    // bit 26:22    Matching Rule 1 action offset
16956 +               unsigned int    timing          : 3;    // bit 29:27
16957 +               unsigned int    reserved1       : 1;    // bit 30
16958 +               unsigned int    mr1en           : 1;    // bit 31               Enable Matching Rule 1
16959 +#endif
16960 +       } bits;
16961 +} GMAC_HASH_ENABLE_REG0_T;
16962 +
16963 +/**********************************************************************
16964 + * GMAC Hash Engine Enable/Action Register 1 Offset Register
16965 + * GMAC0 offset 0x8074
16966 + * GMAC1 offset 0xC074
16967 + **********************************************************************/
16968 +typedef union
16969 +{
16970 +       unsigned int bits32;
16971 +       struct bit_8074
16972 +       {
16973 +#if (BIG_ENDIAN==1)
16974 +               unsigned int    mr3en           : 1;    // bit 31               Enable Matching Rule 3
16975 +               unsigned int    reserved3       : 4;    // bit 30:27
16976 +               unsigned int    mr3_action      : 5;    // bit 26:22    Matching Rule 3 action offset
16977 +               unsigned int    mr3hel          : 6;    // bit 21:16    match rule 3 hash entry size
16978 +               unsigned int    mr2en           : 1;    // bit 15               Enable Matching Rule 2
16979 +               unsigned int    reserved2       : 4;    // bit 14:11
16980 +               unsigned int    mr2_action      : 5;    // bit 10:6             Matching Rule 2 action offset
16981 +               unsigned int    mr2hel          : 6;    // bit 5:0              match rule 2 hash entry size
16982 +#else
16983 +               unsigned int    mr2hel          : 6;    // bit 5:0              match rule 2 hash entry size
16984 +               unsigned int    mr2_action      : 5;    // bit 10:6             Matching Rule 2 action offset
16985 +               unsigned int    reserved2       : 4;    // bit 14:11
16986 +               unsigned int    mr2en           : 1;    // bit 15               Enable Matching Rule 2
16987 +               unsigned int    mr3hel          : 6;    // bit 21:16    match rule 3 hash entry size
16988 +               unsigned int    mr3_action      : 5;    // bit 26:22    Matching Rule 3 action offset
16989 +               unsigned int    reserved1       : 4;    // bit 30:27
16990 +               unsigned int    mr3en           : 1;    // bit 31               Enable Matching Rule 3
16991 +#endif
16992 +       } bits;
16993 +} GMAC_HASH_ENABLE_REG1_T;
16994 +
16995 +
16996 +/**********************************************************************
16997 + * GMAC Matching Rule Control Register 0
16998 + * GMAC0 offset 0x8078
16999 + * GMAC1 offset 0xC078
17000 + **********************************************************************/
17001 +typedef union
17002 +{
17003 +       unsigned int bits32;
17004 +       struct bit_8078
17005 +       {
17006 +#if (BIG_ENDIAN==1)
17007 +               unsigned int    l2                      : 1;    // bit 31               L2 matching enable
17008 +               unsigned int    l3                      : 1;    // bit 30               L3 matching enable
17009 +               unsigned int    l4                      : 1;    // bit 29               L4 matching enable
17010 +               unsigned int    l7                      : 1;    // bit 28               L7 matching enable
17011 +               unsigned int    port            : 1;    // bit 27               PORT ID matching enable
17012 +               unsigned int    priority        : 3;    // bit 26:24    priority if multi-rules matched
17013 +               unsigned int    da                      : 1;    // bit 23               MAC DA enable
17014 +               unsigned int    sa                      : 1;    // bit 22               MAC SA enable
17015 +               unsigned int    ether_type      : 1;    // bit 21               Ethernet type enable
17016 +               unsigned int    vlan            : 1;    // bit 20               VLAN ID enable
17017 +               unsigned int    pppoe           : 1;    // bit 19               PPPoE Session ID enable
17018 +               unsigned int    reserved1       : 3;    // bit 18:16
17019 +               unsigned int    ip_version      : 1;    // bit 15               0: IPV4, 1: IPV6
17020 +               unsigned int    ip_hdr_len      : 1;    // bit 14               IPV4 Header length
17021 +               unsigned int    flow_lable      : 1;    // bit 13               IPV6 Flow label
17022 +               unsigned int    tos_traffic     : 1;    // bit 12               IPV4 TOS or IPV6 Traffice Class
17023 +               unsigned int    reserved2       : 4;    // bit 11:8
17024 +               unsigned int    sprx            : 8;    // bit 7:0              Support Protocol Register 7:0
17025 +#else
17026 +               unsigned int    sprx            : 8;    // bit 7:0              Support Protocol Register 7:0
17027 +               unsigned int    reserved2       : 4;    // bit 11:8
17028 +               unsigned int    tos_traffic     : 1;    // bit 12               IPV4 TOS or IPV6 Traffice Class
17029 +               unsigned int    flow_lable      : 1;    // bit 13               IPV6 Flow label
17030 +               unsigned int    ip_hdr_len      : 1;    // bit 14               IPV4 Header length
17031 +               unsigned int    ip_version      : 1;    // bit 15               0: IPV4, 1: IPV6
17032 +               unsigned int    reserved1       : 3;    // bit 18:16
17033 +               unsigned int    pppoe           : 1;    // bit 19               PPPoE Session ID enable
17034 +               unsigned int    vlan            : 1;    // bit 20               VLAN ID enable
17035 +               unsigned int    ether_type      : 1;    // bit 21               Ethernet type enable
17036 +               unsigned int    sa                      : 1;    // bit 22               MAC SA enable
17037 +               unsigned int    da                      : 1;    // bit 23               MAC DA enable
17038 +               unsigned int    priority        : 3;    // bit 26:24    priority if multi-rules matched
17039 +               unsigned int    port            : 1;    // bit 27               PORT ID matching enable
17040 +               unsigned int    l7                      : 1;    // bit 28               L7 matching enable
17041 +               unsigned int    l4                      : 1;    // bit 29               L4 matching enable
17042 +               unsigned int    l3                      : 1;    // bit 30               L3 matching enable
17043 +               unsigned int    l2                      : 1;    // bit 31               L2 matching enable
17044 +#endif
17045 +       } bits;
17046 +} GMAC_MRxCR0_T;
17047 +
17048 +#define MR_L2_BIT                      BIT(31)
17049 +#define MR_L3_BIT                      BIT(30)
17050 +#define MR_L4_BIT                      BIT(29)
17051 +#define MR_L7_BIT                      BIT(28)
17052 +#define MR_PORT_BIT                    BIT(27)
17053 +#define MR_PRIORITY_BIT                BIT(26)
17054 +#define MR_DA_BIT                      BIT(23)
17055 +#define MR_SA_BIT                      BIT(22)
17056 +#define MR_ETHER_TYPE_BIT      BIT(21)
17057 +#define MR_VLAN_BIT                    BIT(20)
17058 +#define MR_PPPOE_BIT           BIT(19)
17059 +#define MR_IP_VER_BIT          BIT(15)
17060 +#define MR_IP_HDR_LEN_BIT      BIT(14)
17061 +#define MR_FLOW_LABLE_BIT      BIT(13)
17062 +#define MR_TOS_TRAFFIC_BIT     BIT(12)
17063 +#define MR_SPR_BIT(x)          BIT(x)
17064 +#define MR_SPR_BITS            0xff
17065 +
17066 +/**********************************************************************
17067 + * GMAC Matching Rule Control Register 1
17068 + * GMAC0 offset 0x807C
17069 + * GMAC1 offset 0xC07C
17070 + **********************************************************************/
17071 + typedef union
17072 +{
17073 +       unsigned int bits32;
17074 +       struct bit_807C
17075 +       {
17076 +#if (BIG_ENDIAN==1)
17077 +               unsigned int    sip                     : 1;    // bit 31               Srce IP
17078 +               unsigned int    sip_netmask     : 7;    // bit 30:24    Srce IP net mask, number of mask bits
17079 +               unsigned int    dip                     : 1;    // bit 23               Dest IP
17080 +               unsigned int    dip_netmask     : 7;    // bit 22:16    Dest IP net mask, number of mask bits
17081 +               unsigned int    l4_byte0_15     : 16;   // bit 15: 0
17082 +#else
17083 +               unsigned int    l4_byte0_15     : 16;   // bit 15: 0
17084 +               unsigned int    dip_netmask     : 7;    // bit 22:16    Dest IP net mask, number of mask bits
17085 +               unsigned int    dip                     : 1;    // bit 23               Dest IP
17086 +               unsigned int    sip_netmask     : 7;    // bit 30:24    Srce IP net mask, number of mask bits
17087 +               unsigned int    sip                     : 1;    // bit 31               Srce IP
17088 +#endif
17089 +       } bits;
17090 +} GMAC_MRxCR1_T;
17091 +
17092 +/**********************************************************************
17093 + * GMAC Matching Rule Control Register 2
17094 + * GMAC0 offset 0x8080
17095 + * GMAC1 offset 0xC080
17096 + **********************************************************************/
17097 + typedef union
17098 +{
17099 +       unsigned int bits32;
17100 +       struct bit_8080
17101 +       {
17102 +#if (BIG_ENDIAN==1)
17103 +               unsigned int    l4_byte16_24: 8;        // bit 31: 24
17104 +               unsigned int    l7_byte0_23     : 24;   // bit 23:0
17105 +#else
17106 +               unsigned int    l7_byte0_23     : 24;   // bit 23:0
17107 +               unsigned int    l4_byte16_24: 8;        // bit 31: 24
17108 +#endif
17109 +       } bits;
17110 +} GMAC_MRxCR2_T;
17111 +
17112 +
17113 +/**********************************************************************
17114 + * GMAC Support registers
17115 + * GMAC0 offset 0x80A8
17116 + * GMAC1 offset 0xC0A8
17117 + **********************************************************************/
17118 + typedef union
17119 +{
17120 +       unsigned int bits32;
17121 +       struct bit_80A8
17122 +       {
17123 +#if (BIG_ENDIAN==1)
17124 +               unsigned int    reserved: 21;   // bit 31:11
17125 +               unsigned int    swap    : 3;    // bit 10:8             Swap
17126 +               unsigned int    protocol: 8;    // bit 7:0              Supported protocol
17127 +#else
17128 +               unsigned int    protocol: 8;    // bit 7:0              Supported protocol
17129 +               unsigned int    swap    : 3;    // bit 10:8             Swap
17130 +               unsigned int    reserved: 21;   // bit 31:11
17131 +#endif
17132 +       } bits;
17133 +} GMAC_SPR_T;
17134 +
17135 +/**********************************************************************
17136 + * GMAC_AHB_WEIGHT registers
17137 + * GMAC0 offset 0x80C8
17138 + * GMAC1 offset 0xC0C8
17139 + **********************************************************************/
17140 + typedef union
17141 +{
17142 +       unsigned int bits32;
17143 +       struct bit_80C8
17144 +       {
17145 +#if (BIG_ENDIAN==1)
17146 +               unsigned int    reserved                : 7;    // 31:25
17147 +               unsigned int    tqDV_threshold  : 5;    // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
17148 +               unsigned int    pre_req                 : 5;    // 19:15 Rx Data Pre Request FIFO Threshold
17149 +               unsigned int    tx_weight               : 5;    // 14:10
17150 +               unsigned int    rx_weight               : 5;    // 9:5
17151 +               unsigned int    hash_weight             : 5;    // 4:0
17152 +#else
17153 +               unsigned int    hash_weight             : 5;    // 4:0
17154 +               unsigned int    rx_weight               : 5;    // 9:5
17155 +               unsigned int    tx_weight               : 5;    // 14:10
17156 +               unsigned int    pre_req                 : 5;    // 19:15 Rx Data Pre Request FIFO Threshold
17157 +               unsigned int    tqDV_threshold  : 5;    // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
17158 +               unsigned int    reserved                : 7;    // 31:25
17159 +#endif
17160 +       } bits;
17161 +} GMAC_AHB_WEIGHT_T;
17162 +/**********************************************************************
17163 + * the register structure of GMAC
17164 + **********************************************************************/
17165 +
17166 +/**********************************************************************
17167 + * GMAC RX FLTR
17168 + * GMAC0 Offset 0xA00C
17169 + * GMAC1 Offset 0xE00C
17170 + **********************************************************************/
17171 +typedef union
17172 +{
17173 +       unsigned int bits32;
17174 +       struct bit1_000c
17175 +       {
17176 +#if (BIG_ENDIAN==1)
17177 +               unsigned int                            : 27;
17178 +               unsigned int error                      :  1;   /* enable receive of all error frames */
17179 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
17180 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
17181 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
17182 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
17183 +#else
17184 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
17185 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
17186 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
17187 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
17188 +               unsigned int error                      :  1;   /* enable receive of all error frames */
17189 +               unsigned int                            : 27;
17190 +#endif
17191 +       } bits;
17192 +} GMAC_RX_FLTR_T;
17193 +
17194 +/**********************************************************************
17195 + * GMAC Configuration 0
17196 + * GMAC0 Offset 0xA018
17197 + * GMAC1 Offset 0xE018
17198 + **********************************************************************/
17199 +typedef union
17200 +{
17201 +       unsigned int bits32;
17202 +       struct bit1_0018
17203 +       {
17204 +#if (BIG_ENDIAN==1)
17205 +               unsigned int reserved           :  2;   // 31
17206 +               unsigned int port1_chk_classq :  1;     // 29
17207 +               unsigned int port0_chk_classq :  1;     // 28
17208 +               unsigned int port1_chk_toeq     :  1;   // 27
17209 +               unsigned int port0_chk_toeq     :  1;   // 26
17210 +               unsigned int port1_chk_hwq      :  1;   // 25
17211 +               unsigned int port0_chk_hwq      :  1;   // 24
17212 +               unsigned int rx_err_detect  :  1;       // 23
17213 +               unsigned int ipv6_exthdr_order: 1;      // 22
17214 +               unsigned int rxc_inv            :  1;   // 21
17215 +               unsigned int rgmm_edge          :  1;   // 20
17216 +        unsigned int rx_tag_remove  :  1;   /* 19: Remove Rx VLAN tag */
17217 +        unsigned int ipv6_rx_chksum :  1;   /* 18: IPv6 RX Checksum enable */
17218 +        unsigned int ipv4_rx_chksum :  1;   /* 17: IPv4 RX Checksum enable */
17219 +        unsigned int rgmii_en       :  1;   /* 16: RGMII in-band status enable */
17220 +               unsigned int tx_fc_en           :  1;   /* 15: TX flow control enable */
17221 +               unsigned int rx_fc_en           :  1;   /* 14: RX flow control enable */
17222 +               unsigned int sim_test           :  1;   /* 13: speed up timers in simulation */
17223 +               unsigned int dis_col            :  1;   /* 12: disable 16 collisions abort function */
17224 +               unsigned int dis_bkoff          :  1;   /* 11: disable back-off function */
17225 +               unsigned int max_len            :  3;   /* 8-10 maximum receive frame length allowed */
17226 +               unsigned int adj_ifg            :  4;   /* 4-7: adjust IFG from 96+/-56 */
17227 +        unsigned int flow_ctrl      :  1;   /* 3: flow control also trigged by Rx queues */
17228 +               unsigned int loop_back          :  1;   /* 2: transmit data loopback enable */
17229 +               unsigned int dis_rx                     :  1;   /* 1: disable receive */
17230 +               unsigned int dis_tx                     :  1;   /* 0: disable transmit */
17231 +#else
17232 +               unsigned int dis_tx                     :  1;   /* 0: disable transmit */
17233 +               unsigned int dis_rx                     :  1;   /* 1: disable receive */
17234 +               unsigned int loop_back          :  1;   /* 2: transmit data loopback enable */
17235 +        unsigned int flow_ctrl      :  1;   /* 3: flow control also trigged by Rx queues */
17236 +               unsigned int adj_ifg            :  4;   /* 4-7: adjust IFG from 96+/-56 */
17237 +               unsigned int max_len            :  3;   /* 8-10 maximum receive frame length allowed */
17238 +               unsigned int dis_bkoff          :  1;   /* 11: disable back-off function */
17239 +               unsigned int dis_col            :  1;   /* 12: disable 16 collisions abort function */
17240 +               unsigned int sim_test           :  1;   /* 13: speed up timers in simulation */
17241 +               unsigned int rx_fc_en           :  1;   /* 14: RX flow control enable */
17242 +               unsigned int tx_fc_en           :  1;   /* 15: TX flow control enable */
17243 +        unsigned int rgmii_en       :  1;   /* 16: RGMII in-band status enable */
17244 +        unsigned int ipv4_rx_chksum :  1;   /* 17: IPv4 RX Checksum enable */
17245 +        unsigned int ipv6_rx_chksum :  1;   /* 18: IPv6 RX Checksum enable */
17246 +        unsigned int rx_tag_remove  :  1;   /* 19: Remove Rx VLAN tag */
17247 +               unsigned int rgmm_edge          :  1;   // 20
17248 +               unsigned int rxc_inv            :  1;   // 21
17249 +               unsigned int ipv6_exthdr_order: 1;      // 22
17250 +               unsigned int rx_err_detect  :  1;       // 23
17251 +               unsigned int port0_chk_hwq      :  1;   // 24
17252 +               unsigned int port1_chk_hwq      :  1;   // 25
17253 +               unsigned int port0_chk_toeq     :  1;   // 26
17254 +               unsigned int port1_chk_toeq     :  1;   // 27
17255 +               unsigned int port0_chk_classq :  1;     // 28
17256 +               unsigned int port1_chk_classq :  1;     // 29
17257 +               unsigned int reserved           :  2;   // 31
17258 +#endif
17259 +       } bits;
17260 +} GMAC_CONFIG0_T;
17261 +
17262 +/**********************************************************************
17263 + * GMAC Configuration 1
17264 + * GMAC0 Offset 0xA01C
17265 + * GMAC1 Offset 0xE01C
17266 + **********************************************************************/
17267 +typedef union
17268 +{
17269 +       unsigned int bits32;
17270 +       struct bit1_001c
17271 +       {
17272 +#if (BIG_ENDIAN==1)
17273 +               unsigned int reserved           : 16;
17274 +               unsigned int rel_threshold      : 8;    /* flow control release threshold */
17275 +               unsigned int set_threshold      : 8;    /* flow control set threshold */
17276 +#else
17277 +               unsigned int set_threshold      : 8;    /* flow control set threshold */
17278 +               unsigned int rel_threshold      : 8;    /* flow control release threshold */
17279 +               unsigned int reserved           : 16;
17280 +#endif
17281 +       } bits;
17282 +} GMAC_CONFIG1_T;
17283 +
17284 +#define GMAC_FLOWCTRL_SET_MAX          32
17285 +#define GMAC_FLOWCTRL_SET_MIN          0
17286 +#define GMAC_FLOWCTRL_RELEASE_MAX      32
17287 +#define GMAC_FLOWCTRL_RELEASE_MIN      0
17288 +
17289 +/**********************************************************************
17290 + * GMAC Configuration 2
17291 + * GMAC0 Offset 0xA020
17292 + * GMAC1 Offset 0xE020
17293 + **********************************************************************/
17294 +typedef union
17295 +{
17296 +       unsigned int bits32;
17297 +       struct bit1_0020
17298 +       {
17299 +#if (BIG_ENDIAN==1)
17300 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
17301 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
17302 +#else
17303 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
17304 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
17305 +#endif
17306 +       } bits;
17307 +} GMAC_CONFIG2_T;
17308 +
17309 +/**********************************************************************
17310 + * GMAC Configuration 3
17311 + * GMAC0 Offset 0xA024
17312 + * GMAC1 Offset 0xE024
17313 + **********************************************************************/
17314 +typedef union
17315 +{
17316 +       unsigned int bits32;
17317 +       struct bit1_0024
17318 +       {
17319 +#if (BIG_ENDIAN==1)
17320 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
17321 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
17322 +#else
17323 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
17324 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
17325 +#endif
17326 +       } bits;
17327 +} GMAC_CONFIG3_T;
17328 +
17329 +
17330 +/**********************************************************************
17331 + * GMAC STATUS
17332 + * GMAC0 Offset 0xA02C
17333 + * GMAC1 Offset 0xE02C
17334 + **********************************************************************/
17335 +typedef union
17336 +{
17337 +       unsigned int bits32;
17338 +       struct bit1_002c
17339 +       {
17340 +#if (BIG_ENDIAN==1)
17341 +               unsigned int                            : 25;
17342 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
17343 +               unsigned int reserved           :  1;
17344 +               unsigned int duplex                     :  1;   /* duplex mode */
17345 +               unsigned int speed                      :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
17346 +               unsigned int link                       :  1;   /* link status */
17347 +#else
17348 +               unsigned int link                       :  1;   /* link status */
17349 +               unsigned int speed                      :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
17350 +               unsigned int duplex                     :  1;   /* duplex mode */
17351 +               unsigned int reserved           :  1;
17352 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
17353 +               unsigned int                            : 25;
17354 +#endif
17355 +       } bits;
17356 +} GMAC_STATUS_T;
17357 +
17358 +#define GMAC_SPEED_10                  0
17359 +#define GMAC_SPEED_100                 1
17360 +#define GMAC_SPEED_1000                        2
17361 +
17362 +#define GMAC_PHY_MII                   0
17363 +#define GMAC_PHY_GMII                  1
17364 +#define GMAC_PHY_RGMII_100             2
17365 +#define GMAC_PHY_RGMII_1000            3
17366 +
17367 +/**********************************************************************
17368 + * Queue Header
17369 + *     (1) TOE Queue Header
17370 + *     (2) Non-TOE Queue Header
17371 + *     (3) Interrupt Queue Header
17372 + *
17373 + * memory Layout
17374 + *     TOE Queue Header
17375 + *      0x60003000 +---------------------------+ 0x0000
17376 + *                             |     TOE Queue 0 Header        |
17377 + *                             |         8 * 4 Bytes       |
17378 + *                             +---------------------------+ 0x0020
17379 + *                             |     TOE Queue 1 Header        |
17380 + *                             |         8 * 4 Bytes           |
17381 + *                             +---------------------------+ 0x0040
17382 + *                             |       ......                          |
17383 + *                             |                                               |
17384 + *                             +---------------------------+
17385 + *
17386 + *     Non TOE Queue Header
17387 + *      0x60002000 +---------------------------+ 0x0000
17388 + *                             |   Default Queue 0 Header  |
17389 + *                             |         2 * 4 Bytes           |
17390 + *                             +---------------------------+ 0x0008
17391 + *                             |   Default Queue 1 Header      |
17392 + *                             |         2 * 4 Bytes           |
17393 + *                             +---------------------------+ 0x0010
17394 + *                             |   Classification Queue 0      |
17395 + *                             |         2 * 4 Bytes           |
17396 + *                             +---------------------------+
17397 + *                             |   Classification Queue 1      |
17398 + *                             |         2 * 4 Bytes           |
17399 + *                             +---------------------------+ (n * 8 + 0x10)
17400 + *                             |               ...                             |
17401 + *                             |         2 * 4 Bytes           |
17402 + *                             +---------------------------+ (13 * 8 + 0x10)
17403 + *                             |   Classification Queue 13     |
17404 + *                             |         2 * 4 Bytes           |
17405 + *                             +---------------------------+ 0x80
17406 + *                             |      Interrupt Queue 0        |
17407 + *                             |         2 * 4 Bytes           |
17408 + *                             +---------------------------+
17409 + *                             |      Interrupt Queue 1        |
17410 + *                             |         2 * 4 Bytes           |
17411 + *                             +---------------------------+
17412 + *                             |      Interrupt Queue 2        |
17413 + *                             |         2 * 4 Bytes           |
17414 + *                             +---------------------------+
17415 + *                             |      Interrupt Queue 3        |
17416 + *                             |         2 * 4 Bytes           |
17417 + *                             +---------------------------+
17418 + *
17419 + **********************************************************************/
17420 +#define TOE_QUEUE_HDR_ADDR(n)          (TOE_TOE_QUE_HDR_BASE + n * 32)
17421 +#define TOE_Q_HDR_AREA_END                     (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX+1))
17422 +#define TOE_DEFAULT_Q0_HDR_BASE                (TOE_NONTOE_QUE_HDR_BASE + 0x00)
17423 +#define TOE_DEFAULT_Q1_HDR_BASE                (TOE_NONTOE_QUE_HDR_BASE + 0x08)
17424 +#define TOE_CLASS_Q_HDR_BASE           (TOE_NONTOE_QUE_HDR_BASE + 0x10)
17425 +#define TOE_INTR_Q_HDR_BASE                    (TOE_NONTOE_QUE_HDR_BASE + 0x80)
17426 +#define INTERRUPT_QUEUE_HDR_ADDR(n)    (TOE_INTR_Q_HDR_BASE + n * 8)
17427 +#define NONTOE_Q_HDR_AREA_END          (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX+1))
17428 +/**********************************************************************
17429 + * TOE Queue Header Word 0
17430 + **********************************************************************/
17431 +typedef union
17432 +{
17433 +       unsigned int bits32;
17434 +       unsigned int base_size;
17435 +} TOE_QHDR0_T;
17436 +
17437 +#define TOE_QHDR0_BASE_MASK    (~0x0f)
17438 +
17439 +/**********************************************************************
17440 + * TOE Queue Header Word 1
17441 + **********************************************************************/
17442 +typedef union
17443 +{
17444 +       unsigned int bits32;
17445 +       struct bit_qhdr1
17446 +       {
17447 +#if (BIG_ENDIAN==1)
17448 +
17449 +               unsigned int wptr                       : 16;   // bit 31:16
17450 +               unsigned int rptr                       : 16;   // bit 15:0
17451 +#else
17452 +               unsigned int rptr                       : 16;   // bit 15:0
17453 +               unsigned int wptr                       : 16;   // bit 31:16
17454 +#endif
17455 +       } bits;
17456 +} TOE_QHDR1_T;
17457 +
17458 +/**********************************************************************
17459 + * TOE Queue Header Word 2
17460 + **********************************************************************/
17461 +typedef union
17462 +{
17463 +       unsigned int bits32;
17464 +       struct bit_qhdr2
17465 +       {
17466 +#if (BIG_ENDIAN==1)
17467 +
17468 +               unsigned int usd                        : 1;    // bit 31               0: if no data assembled yet
17469 +               unsigned int ctl                        : 1;    // bit 30               1: have control flag bits (except ack)
17470 +               unsigned int osq                        : 1;    // bit 29               1: out of sequence
17471 +               unsigned int sat                        : 1;    // bit 28               1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
17472 +               unsigned int ip_opt                     : 1;    // bit 27               1: have IPV4 option or IPV6 Extension header
17473 +               unsigned int tcp_opt            : 1;    // bit 26               1: Have TCP option
17474 +               unsigned int abn                        : 1;    // bit 25               1: Abnormal case Found
17475 +               unsigned int dack                       : 1;    // bit 24               1: Duplicated ACK
17476 +               unsigned int reserved           : 7;    // bit 23:17
17477 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
17478 +#else
17479 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
17480 +               unsigned int reserved           : 7;    // bit 23:17
17481 +               unsigned int dack                       : 1;    // bit 24               1: Duplicated ACK
17482 +               unsigned int abn                        : 1;    // bit 25               1: Abnormal case Found
17483 +               unsigned int tcp_opt            : 1;    // bit 26               1: Have TCP option
17484 +               unsigned int ip_opt                     : 1;    // bit 27               1: have IPV4 option or IPV6 Extension header
17485 +               unsigned int sat                        : 1;    // bit 28               1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
17486 +               unsigned int osq                        : 1;    // bit 29               1: out of sequence
17487 +               unsigned int ctl                        : 1;    // bit 30               1: have control flag bits (except ack)
17488 +               unsigned int usd                        : 1;    // bit 31               0: if no data assembled yet
17489 +#endif
17490 +       } bits;
17491 +} TOE_QHDR2_T;
17492 +
17493 +/**********************************************************************
17494 + * TOE Queue Header Word 3
17495 + **********************************************************************/
17496 +typedef union
17497 +{
17498 +       unsigned int bits32;
17499 +       unsigned int seq_num;
17500 +} TOE_QHDR3_T;
17501 +
17502 +/**********************************************************************
17503 + * TOE Queue Header Word 4
17504 + **********************************************************************/
17505 +typedef union
17506 +{
17507 +       unsigned int bits32;
17508 +       unsigned int ack_num;
17509 +} TOE_QHDR4_T;
17510 +
17511 +/**********************************************************************
17512 + * TOE Queue Header Word 5
17513 + **********************************************************************/
17514 +typedef union
17515 +{
17516 +       unsigned int bits32;
17517 +       struct bit_qhdr5
17518 +       {
17519 +#if (BIG_ENDIAN==1)
17520 +
17521 +               unsigned int SeqCnt             : 16;   // bit 31:16
17522 +               unsigned int AckCnt             : 16;   // bit 15:0
17523 +#else
17524 +               unsigned int AckCnt             : 16;   // bit 15:0
17525 +               unsigned int SeqCnt             : 16;   // bit 31:16
17526 +#endif
17527 +       } bits;
17528 +} TOE_QHDR5_T;
17529 +
17530 +/**********************************************************************
17531 + * TOE Queue Header Word 6
17532 + **********************************************************************/
17533 +typedef union
17534 +{
17535 +       unsigned int bits32;
17536 +       struct bit_qhdr6
17537 +       {
17538 +#if (BIG_ENDIAN==1)
17539 +
17540 +               unsigned int MaxPktSize : 14;   // bit 31:18
17541 +               unsigned int iq_num             : 2;    // bit 17:16
17542 +               unsigned int WinSize    : 16;   // bit 15:0
17543 +#else
17544 +               unsigned int WinSize    : 16;   // bit 15:0
17545 +               unsigned int iq_num             : 2;    // bit 17:16
17546 +               unsigned int MaxPktSize : 14;   // bit 31:18
17547 +#endif
17548 +       } bits;
17549 +} TOE_QHDR6_T;
17550 +
17551 +/**********************************************************************
17552 + * TOE Queue Header Word 7
17553 + **********************************************************************/
17554 +typedef union
17555 +{
17556 +       unsigned int bits32;
17557 +       struct bit_qhdr7
17558 +       {
17559 +#if (BIG_ENDIAN==1)
17560 +
17561 +               unsigned int SeqThreshold       : 16;   // bit 31:16
17562 +               unsigned int AckThreshold       : 16;   // bit 15:0
17563 +#else
17564 +               unsigned int AckThreshold       : 16;   // bit 15:0
17565 +               unsigned int SeqThreshold       : 16;   // bit 31:16
17566 +#endif
17567 +       } bits;
17568 +} TOE_QHDR7_T;
17569 +
17570 +/**********************************************************************
17571 + * TOE Queue Header
17572 + **********************************************************************/
17573 +typedef struct
17574 +{
17575 +       TOE_QHDR0_T             word0;
17576 +       TOE_QHDR1_T             word1;
17577 +       TOE_QHDR2_T             word2;
17578 +       TOE_QHDR3_T             word3;
17579 +       TOE_QHDR4_T             word4;
17580 +       TOE_QHDR5_T             word5;
17581 +       TOE_QHDR6_T             word6;
17582 +       TOE_QHDR7_T             word7;
17583 +} TOE_QHDR_T;
17584 +
17585 +/**********************************************************************
17586 + * NONTOE Queue Header Word 0
17587 + **********************************************************************/
17588 +typedef union
17589 +{
17590 +       unsigned int bits32;
17591 +       unsigned int base_size;
17592 +} NONTOE_QHDR0_T;
17593 +
17594 +#define NONTOE_QHDR0_BASE_MASK         (~0x0f)
17595 +
17596 +/**********************************************************************
17597 + * NONTOE Queue Header Word 1
17598 + **********************************************************************/
17599 +typedef union
17600 +{
17601 +       unsigned int bits32;
17602 +       struct bit_nonqhdr1
17603 +       {
17604 +#if (BIG_ENDIAN==1)
17605 +
17606 +               unsigned int wptr                       : 16;   // bit 31:16
17607 +               unsigned int rptr                       : 16;   // bit 15:0
17608 +#else
17609 +               unsigned int rptr                       : 16;   // bit 15:0
17610 +               unsigned int wptr                       : 16;   // bit 31:16
17611 +#endif
17612 +       } bits;
17613 +} NONTOE_QHDR1_T;
17614 +
17615 +/**********************************************************************
17616 + * Non-TOE Queue Header
17617 + **********************************************************************/
17618 +typedef struct
17619 +{
17620 +       NONTOE_QHDR0_T          word0;
17621 +       NONTOE_QHDR1_T          word1;
17622 +} NONTOE_QHDR_T;
17623 +
17624 +/**********************************************************************
17625 + * Interrupt Queue Header Word 0
17626 + **********************************************************************/
17627 +typedef union
17628 +{
17629 +       unsigned int bits32;
17630 +       struct bit_intrqhdr0
17631 +       {
17632 +#if (BIG_ENDIAN==1)
17633 +
17634 +               unsigned int wptr               : 16;   // bit 31:16    Write Pointer where hw stopped
17635 +               unsigned int win_size   : 16;   // bit 15:0     Descriptor Ring Size
17636 +#else
17637 +               unsigned int win_size   : 16;   // bit 15:0     Descriptor Ring Size
17638 +               unsigned int wptr               : 16;   // bit 31:16    Write Pointer where hw stopped
17639 +#endif
17640 +       } bits;
17641 +} INTR_QHDR0_T;
17642 +
17643 +/**********************************************************************
17644 + * Interrupt Queue Header Word 1
17645 + **********************************************************************/
17646 +typedef union
17647 +{
17648 +       unsigned int bits32;
17649 +       struct bit_intrqhdr1
17650 +       {
17651 +#if (BIG_ENDIAN==1)
17652 +
17653 +               unsigned int ctl                        : 1;    // bit 31               1: have control flag bits (except ack)
17654 +               unsigned int osq                        : 1;    // bit 30               1: out of sequence
17655 +               unsigned int sat                        : 1;    // bit 29               1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
17656 +               unsigned int ip_opt                     : 1;    // bit 28               1: have IPV4 option or IPV6 Extension header
17657 +               unsigned int tcp_opt            : 1;    // bit 27               1: Have TCP option
17658 +               unsigned int abn                        : 1;    // bit 26               1: Abnormal case Found
17659 +               unsigned int dack                       : 1;    // bit 25               1: Duplicated ACK
17660 +               unsigned int tcp_qid            : 8;    // bit 24:17    TCP Queue ID
17661 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
17662 +#else
17663 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
17664 +               unsigned int tcp_qid            : 8;    // bit 24:17    TCP Queue ID
17665 +               unsigned int dack                       : 1;    // bit 25               1: Duplicated ACK
17666 +               unsigned int abn                        : 1;    // bit 26               1: Abnormal case Found
17667 +               unsigned int tcp_opt            : 1;    // bit 27               1: Have TCP option
17668 +               unsigned int ip_opt                     : 1;    // bit 28               1: have IPV4 option or IPV6 Extension header
17669 +               unsigned int sat                        : 1;    // bit 29               1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
17670 +               unsigned int osq                        : 1;    // bit 30               1: out of sequence
17671 +               unsigned int ctl                        : 1;    // bit 31               1: have control flag bits (except ack)
17672 +#endif
17673 +       } bits;
17674 +} INTR_QHDR1_T;
17675 +
17676 +/**********************************************************************
17677 + * Interrupt Queue Header Word 2
17678 + **********************************************************************/
17679 +typedef union
17680 +{
17681 +       unsigned int bits32;
17682 +       unsigned int seq_num;
17683 +} INTR_QHDR2_T;
17684 +
17685 +/**********************************************************************
17686 + * Interrupt Queue Header Word 3
17687 + **********************************************************************/
17688 +typedef union
17689 +{
17690 +       unsigned int bits32;
17691 +       unsigned int ack_num;
17692 +} INTR_QHDR3_T;
17693 +
17694 +/**********************************************************************
17695 + * Interrupt Queue Header Word 4
17696 + **********************************************************************/
17697 +typedef union
17698 +{
17699 +       unsigned int bits32;
17700 +       struct bit_intrqhdr4
17701 +       {
17702 +#if (BIG_ENDIAN==1)
17703 +
17704 +               unsigned int SeqCnt             : 16;   // bit 31:16    Seq# change since last seq# intr.
17705 +               unsigned int AckCnt             : 16;   // bit 15:0     Ack# change since last ack# intr.
17706 +#else
17707 +               unsigned int AckCnt             : 16;   // bit 15:0             Ack# change since last ack# intr.
17708 +               unsigned int SeqCnt             : 16;   // bit 31:16    Seq# change since last seq# intr.
17709 +#endif
17710 +       } bits;
17711 +} INTR_QHDR4_T;
17712 +
17713 +/**********************************************************************
17714 + * Interrupt Queue Header
17715 + **********************************************************************/
17716 +typedef struct
17717 +{
17718 +       INTR_QHDR0_T            word0;
17719 +       INTR_QHDR1_T            word1;
17720 +       INTR_QHDR2_T            word2;
17721 +       INTR_QHDR3_T            word3;
17722 +       INTR_QHDR4_T            word4;
17723 +       unsigned int            word5;
17724 +       unsigned int            word6;
17725 +       unsigned int            word7;
17726 +} INTR_QHDR_T;
17727 +
17728 +/**********************************************************************
17729 + * GMAC Conf
17730 + **********************************************************************/
17731 +typedef struct gmac_conf {
17732 +       struct net_device *dev;
17733 +       int portmap;
17734 +       int vid;
17735 +       int flag;     /* 1: active  0: non-active */
17736 +} sys_gmac_conf;
17737 +
17738 +/**********************************************************************
17739 + * GMAC private data
17740 + **********************************************************************/
17741 +typedef struct {
17742 +       unsigned int            rwptr_reg;
17743 +       unsigned int            desc_base;
17744 +       unsigned int            total_desc_num;
17745 +       unsigned short          finished_idx;
17746 +       GMAC_TXDESC_T           *curr_tx_desc;
17747 +       GMAC_TXDESC_T           *curr_finished_desc;
17748 +       struct sk_buff          *tx_skb[TX_DESC_NUM];
17749 +       unsigned long           total_sent;
17750 +       unsigned long           total_finished;
17751 +       unsigned long           intr_cnt;
17752 +} GMAC_SWTXQ_T;
17753 +
17754 +typedef struct {
17755 +       unsigned int            desc_base;
17756 +       unsigned long           eof_cnt;
17757 +} GMAC_HWTXQ_T;
17758 +
17759 +typedef struct gmac_private{
17760 +       struct net_device       *dev;
17761 +       unsigned int            existed;
17762 +       unsigned int            port_id;        // 0 or 1
17763 +       unsigned int            base_addr;
17764 +       unsigned int            dma_base_addr;
17765 +       unsigned char           *mac_addr1;
17766 +       unsigned char           *mac_addr2;
17767 +       unsigned int            swtxq_desc_base;
17768 +       unsigned int            hwtxq_desc_base;
17769 +       GMAC_SWTXQ_T            swtxq[TOE_SW_TXQ_NUM];
17770 +       GMAC_HWTXQ_T            hwtxq[TOE_HW_TXQ_NUM];
17771 +       NONTOE_QHDR_T           *default_qhdr;
17772 +       unsigned int            default_desc_base;
17773 +       unsigned int            default_desc_num;
17774 +       unsigned int            rx_curr_desc;
17775 +       DMA_RWPTR_T                     rx_rwptr;
17776 +       struct sk_buff          *curr_rx_skb;
17777 +       dma_addr_t                      default_desc_base_dma;
17778 +       dma_addr_t                      swtxq_desc_base_dma;
17779 +       dma_addr_t                      hwtxq_desc_base_dma;
17780 +       unsigned int            irq;
17781 +       unsigned int            flow_control_enable     ;
17782 +       unsigned int            pre_phy_status;
17783 +       unsigned int            full_duplex_cfg;
17784 +       unsigned int            speed_cfg;
17785 +       unsigned int            auto_nego_cfg;
17786 +       unsigned int            full_duplex_status;
17787 +       unsigned int            speed_status;
17788 +       unsigned int            phy_mode;       /* 0->MII 1->GMII 2->RGMII(10/100) 3->RGMII(1000) */
17789 +       unsigned int            phy_addr;
17790 +       unsigned int            intr0_enabled;  // 1: enabled
17791 +       unsigned int            intr1_enabled;  // 1: enabled
17792 +       unsigned int            intr2_enabled;  // 1: enabled
17793 +       unsigned int            intr3_enabled;  // 1: enabled
17794 +       unsigned int            intr4_enabled;  // 1: enabled
17795 +//     unsigned int            intr4_enabled_1;        // 1: enabled
17796 +       unsigned int            intr0_selected; // 1: selected
17797 +       unsigned int            intr1_selected; // 1: selected
17798 +       unsigned int            intr2_selected; // 1: selected
17799 +       unsigned int            intr3_selected; // 1: selected
17800 +       unsigned int            intr4_selected; // 1: selected
17801 +       // void                                 (*gmac_rcv_handler)(struct sk_buff *, int);
17802 +       struct net_device_stats ifStatics;
17803 +       unsigned long           txDerr_cnt[GMAC_NUM];
17804 +       unsigned long           txPerr_cnt[GMAC_NUM];
17805 +       unsigned long           RxDerr_cnt[GMAC_NUM];
17806 +       unsigned long           RxPerr_cnt[GMAC_NUM];
17807 +       unsigned int            isr_rx_cnt;
17808 +       unsigned int            isr_tx_cnt;
17809 +       unsigned long           rx_discard;
17810 +       unsigned long           rx_error;
17811 +       unsigned long           rx_mcast;
17812 +       unsigned long           rx_bcast;
17813 +       unsigned long           rx_status_cnt[8];
17814 +       unsigned long           rx_chksum_cnt[8];
17815 +       unsigned long           rx_sta1_ucast;  // for STA 1 MAC Address
17816 +       unsigned long           rx_sta2_ucast;  // for STA 2 MAC Address
17817 +       unsigned long           mib_full_cnt;
17818 +       unsigned long           rx_pause_on_cnt;
17819 +       unsigned long           tx_pause_on_cnt;
17820 +       unsigned long           rx_pause_off_cnt;
17821 +       unsigned long           tx_pause_off_cnt;
17822 +       unsigned long           rx_overrun_cnt;
17823 +       unsigned long           status_changed_cnt;
17824 +       unsigned long           default_q_cnt;
17825 +       unsigned long           hw_fq_empty_cnt;
17826 +       unsigned long           sw_fq_empty_cnt;
17827 +       unsigned long           default_q_intr_cnt;
17828 +       pid_t               thr_pid;
17829 +       wait_queue_head_t   thr_wait;
17830 +       struct completion   thr_exited;
17831 +    spinlock_t          lock;
17832 +    int                 time_to_die;
17833 +    int                                        operation;
17834 +#ifdef SL351x_GMAC_WORKAROUND
17835 +    unsigned long              short_frames_cnt;
17836 +#endif
17837 +}GMAC_INFO_T ;
17838 +
17839 +typedef struct toe_private {
17840 +       unsigned int    swfq_desc_base;
17841 +       unsigned int    hwfq_desc_base;
17842 +       unsigned int    hwfq_buf_base;
17843 +//     unsigned int    toe_desc_base[TOE_TOE_QUEUE_NUM];
17844 +//     unsigned int    toe_desc_num;
17845 +//     unsigned int    class_desc_base;
17846 +//     unsigned int    class_desc_num;
17847 +//     unsigned int    intr_desc_base;
17848 +//     unsigned int    intr_desc_num;
17849 +//     unsigned int    intr_buf_base;
17850 +       DMA_RWPTR_T             fq_rx_rwptr;
17851 +       GMAC_INFO_T             gmac[GMAC_NUM];
17852 +       dma_addr_t              sw_freeq_desc_base_dma;
17853 +       dma_addr_t              hw_freeq_desc_base_dma;
17854 +       dma_addr_t              hwfq_buf_base_dma;
17855 +       dma_addr_t              hwfq_buf_end_dma;
17856 +//     dma_addr_t              toe_desc_base_dma[TOE_TOE_QUEUE_NUM];
17857 +//     dma_addr_t              class_desc_base_dma;
17858 +//     dma_addr_t              intr_desc_base_dma;
17859 +//     dma_addr_t              intr_buf_base_dma;
17860 +//     unsigned long   toe_iq_intr_full_cnt[TOE_INTR_QUEUE_NUM];
17861 +//     unsigned long   toe_iq_intr_cnt[TOE_INTR_QUEUE_NUM];
17862 +//     unsigned long   toe_q_intr_full_cnt[TOE_TOE_QUEUE_NUM];
17863 +//     unsigned long   class_q_intr_full_cnt[TOE_CLASS_QUEUE_NUM];
17864 +//     unsigned long   class_q_intr_cnt[TOE_CLASS_QUEUE_NUM];
17865 +} TOE_INFO_T;
17866 +
17867 +extern TOE_INFO_T toe_private_data;
17868 +
17869 +#define GMAC_PORT0     0
17870 +#define GMAC_PORT1     1
17871 +/**********************************************************************
17872 + * PHY Definition
17873 + **********************************************************************/
17874 +#define HPHY_ADDR                      0x01
17875 +#define GPHY_ADDR                      0x02
17876 +
17877 +enum phy_state
17878 +{
17879 +    LINK_DOWN   = 0,
17880 +    LINK_UP     = 1
17881 +};
17882 +
17883 +/* transmit timeout value */
17884 +
17885 +#endif //_GMAC_SL351x_H
17886 --- /dev/null
17887 +++ b/include/asm-arm/arch-sl2312/sl351x_hash_cfg.h
17888 @@ -0,0 +1,365 @@
17889 +/*-----------------------------------------------------------------------------------
17890 +*      sl351x_hash_cfg.h
17891 +*
17892 +*      Description:
17893 +*      
17894 +*      History:
17895 +*
17896 +*      9/14/2005       Gary Chen       Create
17897 +*
17898 +*-------------------------------------------------------------------------------------*/
17899 +#ifndef _SL351x_HASH_CFG_H_
17900 +#define _SL351x_HASH_CFG_H_    1
17901 +
17902 +// #define NAT_DEBUG_MSG       1
17903 +// #define DEBUG_NAT_MIXED_HW_SW_TX    1
17904 +#ifdef DEBUG_NAT_MIXED_HW_SW_TX
17905 +       // #define NAT_DEBUG_LAN_HASH_TIMEOUT   1
17906 +       // #define NAT_DEBUG_WAN_HASH_TIMEOUT   1
17907 +#endif
17908 +
17909 +#define IPIV(a,b,c,d)          ((a<<24)+(b<<16)+(c<<8)+d)
17910 +#define        IPIV1(a)                        ((a>>24)&0xff)
17911 +#define        IPIV2(a)                        ((a>>16)&0xff)
17912 +#define IPIV3(a)                       ((a>>8)&0xff)
17913 +#define IPIV4(a)                       ((a)&0xff)
17914 +
17915 +#define HASH_MAX_BYTES                 64      // 128
17916 +#define HASH_ACTION_DWORDS             9
17917 +#define HASH_MAX_DWORDS                        (HASH_MAX_BYTES / sizeof(u32))
17918 +#define HASH_MAX_KEY_DWORD             (HASH_MAX_DWORDS - HASH_ACTION_DWORDS)
17919 +#define HASH_INIT_KEY                  0x534C4F52
17920 +#define HASH_BITS                              12      // 12 : Normal, 7: Simulation
17921 +#define HASH_TOTAL_ENTRIES             (1 << HASH_BITS)
17922 +#define HASH_MAX_ENTRIES               (1 << 12)
17923 +#define HASH_TOE_ENTRIES               (HASH_TOTAL_ENTRIES >> 5)
17924 +#define HASH_BITS_MASK                 ((1 << HASH_BITS) - 1)
17925 +
17926 +#define hash_lock(lock)                        // spin_lock_bh(lock)
17927 +#define hash_unlock(lock)              // spin_unlock_bh(lock)
17928 +
17929 +/*----------------------------------------------------------------------
17930 + *  special macro
17931 + ----------------------------------------------------------------------*/
17932 +#define HASH_PUSH_WORD(cp, data)       {*cp++ = (((u16)(data))     ) & 0xff;   \
17933 +                                                                       *cp++ = (((u16)(data)) >> 8) & 0xff;} 
17934 +#define HASH_PUSH_DWORD(cp, data)      {*cp++ = (u8)(((u32)(data))      ) & 0xff;      \
17935 +                                                                       *cp++ = (u8)(((u32)(data)) >>  8) & 0xff;       \
17936 +                                                                       *cp++ = (u8)(((u32)(data)) >> 16) & 0xff;       \
17937 +                                                                       *cp++ = (u8)(((u32)(data)) >> 24) & 0xff;}
17938 +#define HASH_PUSH_BYTE(cp, data)       {*cp++ = ((u8)(data)) & 0xff;}
17939 +
17940 +/*----------------------------------------------------------------------
17941 + *  key
17942 + ----------------------------------------------------------------------*/
17943 +typedef struct {
17944 +       u8              port;
17945 +       u16             Ethertype;
17946 +       u8              da[6];
17947 +       u8              sa[6];
17948 +       u16             pppoe_sid;      
17949 +       u16             vlan_id;        
17950 +       u8              ipv4_hdrlen;    
17951 +       u8              ip_tos; 
17952 +       u8              ip_protocol;    
17953 +       u32             ipv6_flow_label;
17954 +       u8              sip[16];
17955 +       u8              dip[16];
17956 +       //__u32                 sip[4];
17957 +       //__u32                 dip[4];
17958 +       u8              l4_bytes[24];
17959 +       u8              l7_bytes[24];
17960 +       u8              ipv6;   // 1: IPv6, 0: IPV4
17961 +} ENTRY_KEY_T;
17962 +
17963 +/*----------------------------------------------------------------------
17964 + *  key for NAT
17965 + *     Note: packed
17966 + ----------------------------------------------------------------------*/
17967 +typedef struct {
17968 +       u16             Ethertype;              // not used
17969 +       u8              port_id;
17970 +       u8              rule_id;
17971 +       u8              ip_protocol;
17972 +       u8              reserved1;              // ip_tos, not used
17973 +       u16             reserved2;              // not used
17974 +       u32             sip;
17975 +       u32             dip;
17976 +       u16             sport;
17977 +       u16             dport;
17978 +} NAT_KEY_T;
17979 +
17980 +#define NAT_KEY_DWORD_SIZE     (sizeof(NAT_KEY_T)/sizeof(u32))
17981 +#define NAT_KEY_SIZE           (sizeof(NAT_KEY_T))
17982 +
17983 +/*----------------------------------------------------------------------
17984 + *  key for NAT
17985 + *     Note: packed
17986 + ----------------------------------------------------------------------*/
17987 +typedef struct {
17988 +       u16             Ethertype;              // not used
17989 +       u8              port_id;
17990 +       u8              rule_id;
17991 +       u8              ip_protocol;
17992 +       u8              reserved1;              // ip_tos, not used
17993 +       u16             reserved2;              // not used
17994 +       u32             sip;
17995 +       u32             dip;
17996 +       u16             reserved3;
17997 +       u16             protocol;
17998 +       u16             reserved4;
17999 +       u16             call_id;
18000 +} GRE_KEY_T;
18001 +
18002 +#define GRE_KEY_DWORD_SIZE     (sizeof(GRE_KEY_T)/sizeof(u32))
18003 +#define GRE_KEY_SIZE           (sizeof(GRE_KEY_T))
18004 +/*----------------------------------------------------------------------
18005 + *  key present or not
18006 + ----------------------------------------------------------------------*/
18007 +typedef struct {
18008 +       u32             port                    : 1;
18009 +       u32             Ethertype               : 1;
18010 +       u32             da                              : 1;
18011 +       u32             sa                              : 1;
18012 +       u32             pppoe_sid               : 1;    
18013 +       u32             vlan_id                 : 1;    
18014 +       u32             ipv4_hdrlen             : 1;    
18015 +       u32             ip_tos                  : 1;
18016 +       u32             ip_protocol             : 1;    
18017 +       u32             ipv6_flow_label : 1;
18018 +       u32             sip                             : 1;
18019 +       u32             dip                             : 1;
18020 +       u32             l4_bytes_0_3    : 1;
18021 +       u32             l4_bytes_4_7    : 1;
18022 +       u32             l4_bytes_8_11   : 1;
18023 +       u32             l4_bytes_12_15  : 1;
18024 +       u32             l4_bytes_16_19  : 1;
18025 +       u32             l4_bytes_20_23  : 1;
18026 +       u32             l7_bytes_0_3    : 1;
18027 +       u32             l7_bytes_4_7    : 1;
18028 +       u32             l7_bytes_8_11   : 1;
18029 +       u32             l7_bytes_12_15  : 1;
18030 +       u32             l7_bytes_16_19  : 1;
18031 +       u32             l7_bytes_20_23  : 1;
18032 +       u32             reserved                : 8;
18033 +} KEY_FIELD_T;
18034 +
18035 +/*----------------------------------------------------------------------
18036 + *  action
18037 + ----------------------------------------------------------------------*/
18038 +typedef struct {
18039 +       u32             reserved0       : 5;    // bit 0:4
18040 +       u32             pppoe           : 2;    // bit 5:6
18041 +       u32             vlan            : 2;    // bit 7:8
18042 +       u32             sa                      : 1;    // bit 9
18043 +       u32             da                      : 1;    // bit 10
18044 +       u32             Dport           : 1;    // bit 11
18045 +       u32             Sport           : 1;    // bit 12
18046 +       u32             Dip                     : 1;    // bit 13
18047 +       u32             Sip                     : 1;    // bit 14
18048 +       u32             sw_id           : 1;    // bit 15
18049 +       u32             frag            : 1;    // bit 16
18050 +       u32             option          : 1;    // bit 17
18051 +       u32             ttl_0           : 1;    // bit 18
18052 +       u32             ttl_1           : 1;    // bit 19
18053 +       u32             mtu                     : 1;    // bit 20
18054 +       u32             exception       : 1;    // bit 21
18055 +       u32             srce_qid        : 1;    // bit 22
18056 +       u32             discard         : 1;    // bit 23
18057 +       u32             dest_qid        : 8;    // bit 24:31
18058 +} ENTRY_ACTION_T;
18059 +
18060 +#define ACTION_DISCARD_BIT             BIT(23)
18061 +#define ACTION_SRCE_QID_BIT            BIT(22)
18062 +#define ACTION_EXCEPTION_BIT   BIT(21)
18063 +#define ACTION_MTU_BIT                 BIT(20)
18064 +#define ACTION_TTL_1_BIT               BIT(19)
18065 +#define ACTION_TTL_0_BIT               BIT(18)
18066 +#define ACTION_IP_OPTION               BIT(17)
18067 +#define ACTION_FRAG_BIT                        BIT(16)
18068 +#define ACTION_SWID_BIT                        BIT(15)
18069 +#define ACTION_SIP_BIT                 BIT(14)
18070 +#define ACTION_DIP_BIT                 BIT(13)
18071 +#define ACTION_SPORT_BIT               BIT(12)
18072 +#define ACTION_DPORT_BIT               BIT(11)
18073 +#define ACTION_DA_BIT                  BIT(10)
18074 +#define ACTION_SA_BIT                  BIT(9)
18075 +#define ACTION_VLAN_DEL_BIT            BIT(8)
18076 +#define ACTION_VLAN_INS_BIT            BIT(7)
18077 +#define ACTION_PPPOE_DEL_BIT   BIT(6)
18078 +#define ACTION_PPPOE_INS_BIT   BIT(5)
18079 +#define ACTION_L4_THIRD_BIT            BIT(4)
18080 +#define ACTION_L4_FOURTH_BIT   BIT(3)
18081 +
18082 +#define NAT_ACTION_BITS                        (ACTION_SRCE_QID_BIT  | ACTION_EXCEPTION_BIT |  \
18083 +                                                               ACTION_TTL_1_BIT | ACTION_TTL_0_BIT |                   \
18084 +                                                               ACTION_IP_OPTION | ACTION_FRAG_BIT |                    \
18085 +                                                               ACTION_DA_BIT | ACTION_SA_BIT)
18086 +#define NAT_LAN2WAN_ACTIONS            (NAT_ACTION_BITS | ACTION_SIP_BIT | ACTION_SPORT_BIT)
18087 +#define NAT_WAN2LAN_ACTIONS            (NAT_ACTION_BITS | ACTION_DIP_BIT | ACTION_DPORT_BIT)
18088 +#define NAT_PPPOE_LAN2WAN_ACTIONS      (NAT_LAN2WAN_ACTIONS | ACTION_PPPOE_INS_BIT)
18089 +#define NAT_PPPOE_WAN2LAN_ACTIONS      (NAT_WAN2LAN_ACTIONS | ACTION_PPPOE_DEL_BIT)
18090 +#define NAT_PPTP_LAN2WAN_ACTIONS       (NAT_ACTION_BITS | ACTION_SIP_BIT | ACTION_L4_FOURTH_BIT)
18091 +#define NAT_PPTP_WAN2LAN_ACTIONS       (NAT_ACTION_BITS | ACTION_DIP_BIT | ACTION_L4_FOURTH_BIT)
18092 +#define NAT_PPPOE_PPTP_LAN2WAN_ACTIONS (NAT_PPTP_LAN2WAN_ACTIONS | ACTION_PPPOE_INS_BIT)
18093 +#define NAT_PPPOE_PPTP_WAN2LAN_ACTIONS (NAT_PPTP_WAN2LAN_ACTIONS | ACTION_PPPOE_DEL_BIT)
18094 +                                                               
18095 +/*----------------------------------------------------------------------
18096 + *  parameter
18097 + ----------------------------------------------------------------------*/
18098 +typedef struct {
18099 +       u8              da[6];
18100 +       u8              sa[6];
18101 +       u16             vlan;   
18102 +       u16     pppoe;  
18103 +       u32             Sip;
18104 +       u32             Dip;
18105 +       u16     Sport;  
18106 +       u16     Dport;  
18107 +       u16     sw_id;  
18108 +       u16     mtu;    
18109 +} ENTRY_PARAM_T;
18110 +
18111 +/*----------------------------------------------------------------------
18112 + *  Hash Entry
18113 + ----------------------------------------------------------------------*/
18114 +typedef struct {
18115 +       char                    rule;
18116 +       ENTRY_KEY_T             key;
18117 +       KEY_FIELD_T             key_present;
18118 +       ENTRY_ACTION_T  action;
18119 +       ENTRY_PARAM_T   param;
18120 +       int                             index;
18121 +       int                             total_dwords;
18122 +} HASH_ENTRY_T;
18123 +
18124 +/*----------------------------------------------------------------------
18125 + *  NAT Hash Entry
18126 + ----------------------------------------------------------------------*/
18127 +typedef struct {
18128 +       short   counter;
18129 +       short   interval;
18130 +} HASH_TIMEOUT_T;
18131 +
18132 +/*----------------------------------------------------------------------
18133 + *  NAT Hash Entry for TCP/UDP protocol
18134 + ----------------------------------------------------------------------*/
18135 +typedef struct {
18136 +       NAT_KEY_T                       key;
18137 +       union {
18138 +               u32                             dword;
18139 +               ENTRY_ACTION_T  bits;
18140 +       } action;
18141 +       ENTRY_PARAM_T           param;
18142 +       HASH_TIMEOUT_T          tmo;    // used by software only, to use memory space efficiently
18143 +} NAT_HASH_ENTRY_T;
18144 +
18145 +#define NAT_HASH_ENTRY_SIZE            (sizeof(NAT_HASH_ENTRY_T))
18146 +
18147 +/*----------------------------------------------------------------------
18148 + *  GRE Hash Entry for PPTP/GRE protocol
18149 + ----------------------------------------------------------------------*/
18150 +typedef struct {
18151 +       GRE_KEY_T                       key;
18152 +       union {
18153 +               u32                             dword;
18154 +               ENTRY_ACTION_T  bits;
18155 +       } action;
18156 +       ENTRY_PARAM_T           param;
18157 +       HASH_TIMEOUT_T          tmo;    // used by software only, to use memory space efficiently
18158 +} GRE_HASH_ENTRY_T;
18159 +
18160 +#define GRE_HASH_ENTRY_SIZE            (sizeof(GRE_HASH_ENTRY_T))
18161 +
18162 +/*----------------------------------------------------------------------
18163 + *  External Variables
18164 + ----------------------------------------------------------------------*/
18165 +extern char                            hash_tables[HASH_TOTAL_ENTRIES][HASH_MAX_BYTES] __attribute__ ((aligned(16)));
18166 +extern u32                             hash_nat_owner_bits[HASH_TOTAL_ENTRIES/32];
18167 +/*----------------------------------------------------------------------
18168 +* hash_get_valid_flag
18169 +*----------------------------------------------------------------------*/
18170 +static inline int hash_get_valid_flag(int index)
18171 +{
18172 +       volatile u32 *hash_valid_bits_ptr = (volatile u32 *)TOE_V_BIT_BASE;
18173 +
18174 +#ifdef SL351x_GMAC_WORKAROUND
18175 +       if (index >= (0x80 * 8) && index < (0x8c * 8))
18176 +               return 1;
18177 +#endif 
18178 +       return (hash_valid_bits_ptr[index/32] & (1 << (index %32)));
18179 +}
18180 +
18181 +/*----------------------------------------------------------------------
18182 +* hash_get_nat_owner_flag
18183 +*----------------------------------------------------------------------*/
18184 +static inline int hash_get_nat_owner_flag(int index)
18185 +{
18186 +       return (hash_nat_owner_bits[index/32] & (1 << (index %32)));
18187 +}
18188 +
18189 +/*----------------------------------------------------------------------
18190 +* hash_validate_entry
18191 +*----------------------------------------------------------------------*/
18192 +static inline void hash_validate_entry(int index)
18193 +{
18194 +       volatile u32    *hash_valid_bits_ptr = (volatile u32 *)TOE_V_BIT_BASE;
18195 +       register int    ptr = index/32, bits = 1 << (index %32);
18196 +       
18197 +       hash_valid_bits_ptr[ptr] |= bits;
18198 +}
18199 +
18200 +/*----------------------------------------------------------------------
18201 +* hash_invalidate_entry
18202 +*----------------------------------------------------------------------*/
18203 +static inline void hash_invalidate_entry(int index)
18204 +{
18205 +       volatile u32 *hash_valid_bits_ptr = (volatile u32 *)TOE_V_BIT_BASE;
18206 +       register int    ptr = index/32, bits = 1 << (index %32);
18207 +       
18208 +       hash_valid_bits_ptr[ptr] &= ~(bits);
18209 +}
18210 +
18211 +/*----------------------------------------------------------------------
18212 +* hash_nat_enable_owner
18213 +*----------------------------------------------------------------------*/
18214 +static inline void hash_nat_enable_owner(int index)
18215 +{
18216 +       hash_nat_owner_bits[index/32] |= (1 << (index % 32));
18217 +}
18218 +
18219 +/*----------------------------------------------------------------------
18220 +* hash_nat_disable_owner
18221 +*----------------------------------------------------------------------*/
18222 +static inline void hash_nat_disable_owner(int index)
18223 +{
18224 +       hash_nat_owner_bits[index/32] &= ~(1 << (index % 32));
18225 +}
18226 +
18227 +/*----------------------------------------------------------------------
18228 +* hash_get_entry
18229 +*----------------------------------------------------------------------*/
18230 +static inline void *hash_get_entry(int index)
18231 +{
18232 +       return (void*) &hash_tables[index][0];
18233 +}
18234 +
18235 +/*----------------------------------------------------------------------
18236 +* Functions
18237 +*----------------------------------------------------------------------*/
18238 +extern int hash_add_entry(HASH_ENTRY_T *entry);
18239 +extern void sl351x_hash_init(void);
18240 +extern void hash_set_valid_flag(int index, int valid);
18241 +extern void hash_set_nat_owner_flag(int index, int valid);
18242 +extern void *hash_get_entry(int index);
18243 +extern int hash_build_keys(u32 *destp, HASH_ENTRY_T *entry);
18244 +extern void hash_build_nat_keys(u32 *destp, HASH_ENTRY_T *entry);
18245 +extern int hash_write_entry(HASH_ENTRY_T *entry, u8 *key);
18246 +extern int hash_add_entry(HASH_ENTRY_T *entry);
18247 +extern u16 hash_crc16(u16 crc, u8 *datap, u32 len);
18248 +extern u16 hash_gen_crc16(u8 *datap, u32 len);
18249 +
18250 +#endif // _SL351x_HASH_CFG_H_
18251 +
18252 +
18253 +
18254 --- /dev/null
18255 +++ b/include/asm-arm/arch-sl2312/sl351x_nat_cfg.h
18256 @@ -0,0 +1,211 @@
18257 +/**************************************************************************
18258 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.                
18259 +*--------------------------------------------------------------------------
18260 +*      sl_nat_cfg.h
18261 +*
18262 +*      Description:
18263 +*              - Define the Device Control Commands for NAT Configuration
18264 +*      
18265 +*      History:
18266 +*
18267 +*      4/28/2006       Gary Chen       Create
18268 +*
18269 +*-----------------------------------------------------------------------------*/
18270 +#ifndef _SL351x_NAT_CFG_H_
18271 +#define _SL351x_NAT_CFG_H_     1
18272 +
18273 +/*----------------------------------------------------------------------
18274 +* Confiuration
18275 +*----------------------------------------------------------------------*/
18276 +#ifdef CONFIG_NETFILTER
18277 +#define CONFIG_SL351x_NAT                      1
18278 +#undef CONFIG_SL351x_NAT
18279 +#undef CONFIG_SL351x_SYSCTL
18280 +#endif
18281 +#define CONFIG_NAT_MAX_IP_NUM          4       // per device (eth0 or eth1)
18282 +#define CONFIG_NAT_MAX_XPORT           64
18283 +#define CONFIG_NAT_MAX_WRULE           16      // per Queue
18284 +#define CONFIG_NAT_TXQ_NUM                     4
18285 +/*----------------------------------------------------------------------
18286 +* Command set
18287 +*----------------------------------------------------------------------*/
18288 +#define SIOCDEVSL351x  SIOCDEVPRIVATE  // 0x89F0
18289 +#define NATSSTATUS             0
18290 +#define NATGSTATUS             1
18291 +#define NATSETPORT             2
18292 +#define NATGETPORT             3
18293 +#define NATADDIP               4
18294 +#define NATDELIP               5
18295 +#define NATGETIP               6
18296 +#define NATAXPORT              7
18297 +#define NATDXPORT              8
18298 +#define NATGXPORT              9
18299 +#define NATSWEIGHT             10
18300 +#define NATGWEIGHT             11
18301 +#define NATAWRULE              12
18302 +#define NATDWRULE              13
18303 +#define NATGWRULE              14
18304 +#define NATSDEFQ               15
18305 +#define NATGDEFQ               16
18306 +#define NATRMIPCFG             17              // remove IP config
18307 +#define NATTESTENTRY   18
18308 +#define NATSETMEM              19
18309 +#define NATSHOWMEM             20
18310 +/*----------------------------------------------------------------------
18311 +* Command Structure
18312 +*----------------------------------------------------------------------*/
18313 +// Common Header
18314 +typedef struct {
18315 +       unsigned short          cmd;    // command ID
18316 +       unsigned short          len;    // data length, excluding this header
18317 +} NATCMD_HDR_T;
18318 +
18319 +// NATSSTATUS & NATGSTATUS commands
18320 +typedef struct {
18321 +       unsigned char           enable;
18322 +} NAT_STATUS_T;        
18323 +
18324 +// NATSETPORT & NATGETPORT commands
18325 +typedef struct {
18326 +       unsigned char           portmap;
18327 +} NAT_PORTCFG_T;
18328 +
18329 +typedef struct {
18330 +       unsigned int            ipaddr;
18331 +       unsigned int            netmask;
18332 +} NAT_IP_ENTRY_T;
18333 +
18334 +// NATADDIP & NATDELIP commands
18335 +typedef struct {
18336 +       NAT_IP_ENTRY_T  entry;
18337 +} NAT_IPCFG_T;
18338 +
18339 +// NATGETIP command
18340 +typedef struct {
18341 +       unsigned int    total;
18342 +       NAT_IP_ENTRY_T  entry[CONFIG_NAT_MAX_IP_NUM];
18343 +} NAT_IPCFG_ALL_T;
18344 +
18345 +typedef struct {
18346 +       unsigned int            protocol;
18347 +       unsigned short          sport_start;
18348 +       unsigned short          sport_end;
18349 +       unsigned short          dport_start;
18350 +       unsigned short          dport_end;
18351 +} NAT_XPORT_ENTRY_T;
18352 +
18353 +// NATAXPORT & NATDXPORT Commands
18354 +typedef struct {
18355 +       NAT_XPORT_ENTRY_T       entry;
18356 +} NAT_XPORT_T;
18357 +
18358 +// NATGXPORT Command
18359 +typedef struct {
18360 +       unsigned int            total;
18361 +       NAT_XPORT_ENTRY_T       entry[CONFIG_NAT_MAX_XPORT];
18362 +} NAT_XPORT_ALL_T;
18363 +
18364 +// NATSWEIGHT & NATGWEIGHT Commands
18365 +typedef struct {
18366 +       unsigned char           weight[CONFIG_NAT_TXQ_NUM];
18367 +} NAT_WEIGHT_T;
18368 +
18369 +typedef struct {
18370 +       unsigned int            protocol;
18371 +       unsigned int            sip_start;
18372 +       unsigned int            sip_end;
18373 +       unsigned int            dip_start;
18374 +       unsigned int            dip_end;
18375 +       unsigned short          sport_start;
18376 +       unsigned short          sport_end;
18377 +       unsigned short          dport_start;
18378 +       unsigned short          dport_end;
18379 +} NAT_WRULE_ENTRY_T;   
18380 +
18381 +// NATAWRULE & NATDWRULE Commands
18382 +typedef struct {
18383 +       unsigned int            qid;
18384 +       NAT_WRULE_ENTRY_T       entry;
18385 +} NAT_WRULE_T;
18386 +
18387 +// NATGWRULE Command
18388 +typedef struct {
18389 +       unsigned int            total;
18390 +       NAT_WRULE_ENTRY_T       entry[CONFIG_NAT_MAX_WRULE];
18391 +} NAT_WRULE_ALL_T;
18392 +
18393 +// NATSDEFQ & NATGDEFQ commands
18394 +typedef struct {
18395 +       unsigned int            qid;
18396 +} NAT_QUEUE_T; 
18397 +
18398 +// NATTESTENTRY 
18399 +typedef struct {
18400 +       u_int16_t               cmd;    // command ID
18401 +       u_int16_t               len;    // data length, excluding this header
18402 +       u_int8_t                init_enable;
18403 +} NAT_TESTENTRY_T;     
18404 +       
18405 +typedef union
18406 +{
18407 +       NAT_STATUS_T            status;
18408 +       NAT_PORTCFG_T           portcfg;
18409 +       NAT_IPCFG_T                     ipcfg;
18410 +       NAT_XPORT_T                     xport;
18411 +       NAT_WEIGHT_T            weight;
18412 +       NAT_WRULE_T                     wrule;
18413 +       NAT_QUEUE_T                     queue;
18414 +       NAT_TESTENTRY_T init_entry;
18415 +} NAT_REQ_E;
18416 +       
18417 +/*----------------------------------------------------------------------
18418 +* NAT Configuration
18419 +*      - Used by driver only
18420 +*----------------------------------------------------------------------*/
18421 +typedef struct {
18422 +       unsigned int            enabled;
18423 +       unsigned int            init_enabled;
18424 +       unsigned int            tcp_udp_rule_id;
18425 +       unsigned int            gre_rule_id;
18426 +       unsigned int            lan_port;
18427 +       unsigned int            wan_port;
18428 +       unsigned int            default_hw_txq;
18429 +       short                           tcp_tmo_interval;
18430 +       short                           udp_tmo_interval;
18431 +       short                           gre_tmo_interval;
18432 +       NAT_IPCFG_ALL_T         ipcfg[2];       // LAN/WAN port
18433 +       NAT_XPORT_ALL_T         xport;
18434 +       NAT_WEIGHT_T            weight;
18435 +       NAT_WRULE_ALL_T         wrule[CONFIG_NAT_TXQ_NUM];
18436 +} NAT_CFG_T;
18437 +
18438 +/*----------------------------------------------------------------------
18439 +* NAT Control Block
18440 +*      - Used by driver only
18441 +*      - Stores LAN-IN or WAN-IN information
18442 +*      - WAN-OUT and LAN-OUT driver use them to build up a hash entry
18443 +*      - NOTES: To update this data structure, MUST take care of alignment issue
18444 +*   -           MUST make sure that the size of skbuff structure must 
18445 +*            be larger than (40 + sizof(NAT_CB_T))
18446 +*----------------------------------------------------------------------*/
18447 +typedef struct {
18448 +       unsigned short          tag;
18449 +       unsigned char           sa[6];
18450 +       unsigned int            sip;
18451 +       unsigned int            dip;
18452 +       unsigned short          sport;
18453 +       unsigned short          dport;
18454 +       unsigned char           pppoe_frame;
18455 +       unsigned char           state;                  // same to enum tcp_conntrack
18456 +       unsigned char           reserved[2];
18457 +} NAT_CB_T;
18458 +
18459 +#define NAT_CB_TAG             0x4C53  // "SL"
18460 +#define NAT_CB_SIZE            sizeof(NAT_CB_T)
18461 +// #define NAT_SKB_CB(skb)     (NAT_CB_T *)(((unsigned int)&((skb)->cb[40]) + 3) & ~3)  // for align 4
18462 +#define NAT_SKB_CB(skb)        (NAT_CB_T *)&((skb)->cb[40])  // for align 4
18463 +
18464 +#endif // _SL351x_NAT_CFG_H_
18465 +
18466 +
18467 +
18468 --- /dev/null
18469 +++ b/include/asm-arm/arch-sl2312/sl351x_toe.h
18470 @@ -0,0 +1,88 @@
18471 +/**************************************************************************
18472 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
18473 +*--------------------------------------------------------------------------
18474 +* Name                 : sl351x_toe.h
18475 +* Description  :
18476 +*              Define for TOE driver of Storlink SL351x
18477 +*
18478 +* History
18479 +*
18480 +*      Date            Writer          Description
18481 +*----------------------------------------------------------------------------
18482 +*                              Xiaochong       Create
18483 +*
18484 +****************************************************************************/
18485 +#ifndef __SL351x_TOE_H
18486 +#define __SL351x_TOE_H 1
18487 +#include <net/sock.h>
18488 +#include <asm/arch/sl351x_gmac.h>
18489 +#include <linux/timer.h>
18490 +#include <linux/netdevice.h>
18491 +#include <linux/ip.h>
18492 +#include <linux/if_ether.h>
18493 +/*
18494 + * TOE_CONN_T is data structure of tcp connection info, used at both
18495 + * device layer and kernel tcp layer
18496 + * skb is the jumbo frame
18497 + */
18498 +
18499 +struct toe_conn{
18500 +       __u8    qid;            // connection qid 0~63.
18501 +       __u8    ip_ver;         // 0: not used; 4: ipv4; 6: ipv6.
18502 +       /* hash key of the connection */
18503 +       __u16   source;
18504 +       __u16   dest;
18505 +       __u32   saddr[4];
18506 +       __u32   daddr[4];
18507 +
18508 +       __u32   seq;
18509 +       __u32   ack_seq;
18510 +
18511 +       /* these fields are used to set TOE QHDR */
18512 +       __u32   ack_threshold;
18513 +       __u32   seq_threshold;
18514 +       __u16   max_pktsize;
18515 +
18516 +       /* used by sw toe, accumulated ack_seq of ack frames */
18517 +       __u16   ack_cnt;
18518 +       /* used by sw toe, accumulated data frames held at driver */
18519 +       __u16   cur_pktsize;
18520 +
18521 +       __u8    status;
18522 +#define        TCP_CONN_UNDEFINE               0X00
18523 +#define        TCP_CONN_CREATION               0X01
18524 +#define        TCP_CONN_CONNECTING             0X02
18525 +#define        TCP_CONN_ESTABLISHED    0X04
18526 +#define        TCP_CONN_RESET                  0X08    // this is used for out-of-order
18527 +                                               // or congestion window is small
18528 +#define        TCP_CONN_CLOSING                0X10
18529 +#define        TCP_CONN_CLOSED                 0x11
18530 +
18531 +       __u16   hash_entry_index;       /* associated hash entry */
18532 +
18533 +       // one timer per connection. Otherwise all connections should be scanned
18534 +       // in a timeout interrupt, and timeout interrupt is triggered no matter
18535 +       // a connection is actually timeout or not.
18536 +       struct timer_list       rx_timer;
18537 +       unsigned long           last_rx_jiffies;
18538 +       GMAC_INFO_T                     *gmac;
18539 +       struct net_device       *dev;
18540 +
18541 +       //      for generating pure ack frame.
18542 +       struct ethhdr           l2_hdr;
18543 +       struct iphdr            l3_hdr;
18544 +
18545 +       spinlock_t                      conn_lock;
18546 +       DMA_RWPTR_T                     toeq_rwptr;
18547 +       GMAC_RXDESC_T           *curr_desc;
18548 +       struct sk_buff          *curr_rx_skb;
18549 +};
18550 +
18551 +struct jumbo_frame {
18552 +       struct sk_buff  *skb0;          // the head of jumbo frame
18553 +       struct sk_buff  *tail;          // the tail of jumbo frame
18554 +       struct iphdr    *iphdr0;        // the ip hdr of skb0.
18555 +       struct tcphdr   *tcphdr0;       // the tcp hdr of skb0.
18556 +};
18557 +
18558 +#endif // __SL351x_TOE_H
18559 --- a/drivers/net/Kconfig
18560 +++ b/drivers/net/Kconfig
18561 @@ -2131,6 +2131,42 @@
18562  
18563           The safe and default value for this is N.
18564  
18565 +config NET_GMAC
18566 +       tristate "Storlink Gigabit Ethernet support"
18567 +       depends on ARCH_SL2312
18568 +       help
18569 +         This driver supports Storlink dual Gigabit Ethernet.
18570 +
18571 +config NET_SL2312
18572 +       tristate "Storlink Gigabit Ethernet support"
18573 +       depends on NET_GMAC
18574 +       help
18575 +         This driver supports Storlink dual Gigabit Ethernet.
18576 +
18577 +config NET_SL351X
18578 +       tristate "Storlink Lepus Gigabit Ethernet support"
18579 +       depends on NET_GMAC
18580 +       help
18581 +         This driver supports Storlink TOE and NAT dual Gigabit Ethernet.
18582 +
18583 +config SL2312_TSO
18584 +       bool "Tx Segmentation Enable"
18585 +       depends on NET_GMAC
18586 +       help
18587 +         TBD
18588 +
18589 +config SL2312_MPAGE
18590 +       bool "Tx Multipage Enable"
18591 +       depends on NET_GMAC
18592 +       help
18593 +         TBD
18594 +
18595 +config SL2312_RECVFILE
18596 +       bool "Rx Multipage Enable"
18597 +       depends on NET_GMAC
18598 +       help
18599 +         TBD
18600 +
18601  config DL2K
18602         tristate "D-Link DL2000-based Gigabit Ethernet support"
18603         depends on PCI
18604 --- a/drivers/net/Makefile
18605 +++ b/drivers/net/Makefile
18606 @@ -236,4 +236,8 @@
18607  
18608  obj-$(CONFIG_FS_ENET) += fs_enet/
18609  
18610 -obj-$(CONFIG_NETXEN_NIC) += netxen/
18611 +
18612 +obj-$(CONFIG_NET_SL351X)+= sl351x_gmac.o sl351x_nat.o sl351x_hash.o sl351x_crc16.o sl351x_proc.o sl_switch.o
18613 +obj-$(CONFIG_NET_SL2312)+= sl2312_emac.o
18614 +
18615 +