projects / librecmc / librecmc.git / blob
? search:


961b5dd4f3189582b7f341b1c4eedee9a1dcc84c
[librecmc/librecmc.git] / target / linux / storm / patches / 1002-gmac.patch
1 Index: linux-2.6.23.17/drivers/net/sl2312_emac.c
2 ===================================================================
3 --- /dev/null
4 +++ linux-2.6.23.17/drivers/net/sl2312_emac.c
5 @@ -0,0 +1,4604 @@
6 +#include <linux/module.h>
7 +#include <linux/kernel.h>
8 +#include <linux/compiler.h>
9 +#include <linux/pci.h>
10 +#include <linux/init.h>
11 +#include <linux/ioport.h>
12 +#include <linux/netdevice.h>
13 +#include <linux/etherdevice.h>
14 +#include <linux/rtnetlink.h>
15 +#include <linux/delay.h>
16 +#include <linux/ethtool.h>
17 +#include <linux/mii.h>
18 +#include <linux/completion.h>
19 +#include <asm/hardware.h>
20 +#include <asm/io.h>
21 +#include <asm/irq.h>
22 +#include <asm/semaphore.h>
23 +#include <asm/arch-sl2312/irqs.h>
24 +#include <asm/arch/it8712.h>
25 +#include <asm/arch/sl2312.h>
26 +#include <linux/mtd/kvctl.h>
27 +#include <linux/sysctl_storlink.h>
28 +
29 +#define BIG_ENDIAN     0
30 +
31 +#define GMAC_DEBUG      0
32 +
33 +#define GMAC_PHY_IF     2
34 +
35 +/* define PHY address */
36 +#define HPHY_ADDR   0x01
37 +#define GPHY_ADDR   0x02
38 +
39 +#define CONFIG_ADM_6999 1
40 +/* define chip information */
41 +#define DRV_NAME                       "SL2312"
42 +#define DRV_VERSION                    "0.1.1"
43 +#define SL2312_DRIVER_NAME  DRV_NAME " Fast Ethernet driver " DRV_VERSION
44 +
45 +/* define TX/RX descriptor parameter */
46 +#define MAX_ETH_FRAME_SIZE     1920
47 +#define TX_BUF_SIZE                    MAX_ETH_FRAME_SIZE
48 +#define TX_DESC_NUM                    128
49 +#define TX_BUF_TOT_LEN         (TX_BUF_SIZE * TX_DESC_NUM)
50 +#define RX_BUF_SIZE                    MAX_ETH_FRAME_SIZE
51 +#define RX_DESC_NUM                    256
52 +#define RX_BUF_TOT_LEN         (RX_BUF_SIZE * RX_DESC_NUM)
53 +#define MAX_ISR_WORK        20
54 +
55 +unsigned int int_status = 0;
56 +
57 +/* define GMAC base address */
58 +#define GMAC_PHYSICAL_BASE_ADDR            (SL2312_GMAC_BASE)
59 +#define GMAC_BASE_ADDR                     (IO_ADDRESS(GMAC_PHYSICAL_BASE_ADDR))
60 +#define GMAC_GLOBAL_BASE_ADDR       (IO_ADDRESS(SL2312_GLOBAL_BASE))
61 +
62 +#define GMAC0_BASE                  (IO_ADDRESS(SL2312_GMAC0_BASE))
63 +#define GMAC1_BASE                  (IO_ADDRESS(SL2312_GMAC1_BASE))
64 +
65 +/* memory management utility */
66 +#define DMA_MALLOC(size,handle)                pci_alloc_consistent(NULL,size,handle)
67 +#define DMA_MFREE(mem,size,handle)     pci_free_consistent(NULL,size,mem,handle)
68 +
69 +//#define gmac_read_reg(offset)       (readl(GMAC_BASE_ADDR + offset))
70 +//#define gmac_write_reg(offset,data,mask)  writel( (gmac_read_reg(offset)&~mask) |(data&mask),(GMAC_BASE_ADDR+offset))
71 +
72 +/* define owner bit */
73 +#define CPU            0
74 +#define DMA            1
75 +
76 +#define ACTIVE      1
77 +#define NONACTIVE   0
78 +
79 +#define CONFIG_SL_NAPI
80 +
81 +#ifndef CONFIG_SL2312_MPAGE
82 +#define CONFIG_SL2312_MPAGE
83 +#endif
84 +
85 +#ifdef CONFIG_SL2312_MPAGE
86 +#include <linux/skbuff.h>
87 +#include <linux/ip.h>
88 +#include <linux/tcp.h>
89 +#endif
90 +
91 +#ifndef CONFIG_TXINT_DISABLE
92 +//#define CONFIG_TXINT_DISABLE
93 +#endif
94 +
95 +enum phy_state
96 +{
97 +    LINK_DOWN   = 0,
98 +    LINK_UP     = 1
99 +};
100 +
101 +
102 +/* transmit timeout value */
103 +#define TX_TIMEOUT  (6*HZ)
104 +
105 +/***************************************/
106 +/* the offset address of GMAC register */
107 +/***************************************/
108 +enum GMAC_REGISTER {
109 +       GMAC_STA_ADD0   = 0x0000,
110 +       GMAC_STA_ADD1   = 0x0004,
111 +       GMAC_STA_ADD2   = 0x0008,
112 +       GMAC_RX_FLTR    = 0x000c,
113 +       GMAC_MCAST_FIL0 = 0x0010,
114 +       GMAC_MCAST_FIL1 = 0x0014,
115 +       GMAC_CONFIG0    = 0x0018,
116 +       GMAC_CONFIG1    = 0x001c,
117 +       GMAC_CONFIG2    = 0x0020,
118 +       GMAC_BNCR               = 0x0024,
119 +       GMAC_RBNR               = 0x0028,
120 +       GMAC_STATUS             = 0x002c,
121 +       GMAC_IN_DISCARDS= 0x0030,
122 +       GMAC_IN_ERRORS  = 0x0034,
123 +       GMAC_IN_MCAST   = 0x0038,
124 +       GMAC_IN_BCAST   = 0x003c,
125 +       GMAC_IN_MAC1    = 0x0040,
126 +       GMAC_IN_MAC2    = 0x0044
127 +};
128 +
129 +/*******************************************/
130 +/* the offset address of GMAC DMA register */
131 +/*******************************************/
132 +enum GMAC_DMA_REGISTER {
133 +       GMAC_DMA_DEVICE_ID              = 0xff00,
134 +       GMAC_DMA_STATUS                 = 0xff04,
135 +       GMAC_TXDMA_CTRL                 = 0xff08,
136 +       GMAC_TXDMA_FIRST_DESC   = 0xff0c,
137 +       GMAC_TXDMA_CURR_DESC    = 0xff10,
138 +       GMAC_RXDMA_CTRL                 = 0xff14,
139 +       GMAC_RXDMA_FIRST_DESC   = 0xff18,
140 +       GMAC_RXDMA_CURR_DESC    = 0xff1c,
141 +};
142 +
143 +/*******************************************/
144 +/* the register structure of GMAC          */
145 +/*******************************************/
146 +typedef union
147 +{
148 +       unsigned int bits32;
149 +       struct bit1_0004
150 +       {
151 +#if (BIG_ENDIAN==1)
152 +               unsigned int sta_add2_l16       : 16;   /* station MAC address2 bits 15 to 0 */
153 +               unsigned int sta_add1_h16       : 16;   /* station MAC address1 bits 47 to 32 */
154 +#else
155 +               unsigned int sta_add1_h16       : 16;   /* station MAC address1 bits 47 to 32 */
156 +               unsigned int sta_add2_l16       : 16;   /* station MAC address2 bits 15 to 0 */
157 +#endif
158 +       } bits;
159 +} GMAC_STA_ADD1_T;
160 +
161 +typedef union
162 +{
163 +       unsigned int bits32;
164 +       struct bit1_000c
165 +       {
166 +#if (BIG_ENDIAN==1)
167 +               unsigned int                            : 27;
168 +               unsigned int error                      :  1;   /* enable receive of all error frames */
169 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
170 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
171 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
172 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
173 +#else
174 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
175 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
176 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
177 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
178 +               unsigned int error                      :  1;   /* enable receive of all error frames */
179 +               unsigned int                            : 27;
180 +#endif
181 +       } bits;
182 +} GMAC_RX_FLTR_T;
183 +
184 +typedef union
185 +{
186 +       unsigned int bits32;
187 +       struct bit1_0018
188 +       {
189 +#if (BIG_ENDIAN==1)
190 +               unsigned int : 10;
191 +               unsigned int inv_rx_clk     : 1;        /* Inverse RX Clock */
192 +               unsigned int rising_latch   : 1;
193 +        unsigned int rx_tag_remove  :  1;   /* Remove Rx VLAN tag */
194 +        unsigned int ipv6_tss_rx_en :  1;   /* IPv6 TSS RX enable */
195 +        unsigned int ipv4_tss_rx_en :  1;   /* IPv4 TSS RX enable */
196 +        unsigned int rgmii_en       :  1;   /* RGMII in-band status enable */
197 +               unsigned int tx_fc_en           :  1;   /* TX flow control enable */
198 +               unsigned int rx_fc_en           :  1;   /* RX flow control enable */
199 +               unsigned int sim_test           :  1;   /* speed up timers in simulation */
200 +               unsigned int dis_col            :  1;   /* disable 16 collisions abort function */
201 +               unsigned int dis_bkoff          :  1;   /* disable back-off function */
202 +               unsigned int max_len            :  3;   /* maximum receive frame length allowed */
203 +               unsigned int adj_ifg            :  4;   /* adjust IFG from 96+/-56 */
204 +        unsigned int                :  1;   /* reserved */
205 +               unsigned int loop_back          :  1;   /* transmit data loopback enable */
206 +               unsigned int dis_rx                     :  1;   /* disable receive */
207 +               unsigned int dis_tx                     :  1;   /* disable transmit */
208 +#else
209 +               unsigned int dis_tx                     :  1;   /* disable transmit */
210 +               unsigned int dis_rx                     :  1;   /* disable receive */
211 +               unsigned int loop_back          :  1;   /* transmit data loopback enable */
212 +        unsigned int                :  1;   /* reserved */
213 +               unsigned int adj_ifg            :  4;   /* adjust IFG from 96+/-56 */
214 +               unsigned int max_len            :  3;   /* maximum receive frame length allowed */
215 +               unsigned int dis_bkoff          :  1;   /* disable back-off function */
216 +               unsigned int dis_col            :  1;   /* disable 16 collisions abort function */
217 +               unsigned int sim_test           :  1;   /* speed up timers in simulation */
218 +               unsigned int rx_fc_en           :  1;   /* RX flow control enable */
219 +               unsigned int tx_fc_en           :  1;   /* TX flow control enable */
220 +        unsigned int rgmii_en       :  1;   /* RGMII in-band status enable */
221 +        unsigned int ipv4_tss_rx_en :  1;   /* IPv4 TSS RX enable */
222 +        unsigned int ipv6_tss_rx_en :  1;   /* IPv6 TSS RX enable */
223 +        unsigned int rx_tag_remove  :  1;   /* Remove Rx VLAN tag */
224 +               unsigned int rising_latch   :  1;
225 +               unsigned int inv_rx_clk : 1;    /* Inverse RX Clock */
226 +               unsigned int : 10;
227 +#endif
228 +       } bits;
229 +} GMAC_CONFIG0_T;
230 +
231 +typedef union
232 +{
233 +       unsigned int bits32;
234 +       struct bit1_001c
235 +       {
236 +#if (BIG_ENDIAN==1)
237 +               unsigned int                            : 28;
238 +               unsigned int buf_size           :  4;   /* per packet buffer size */
239 +#else
240 +               unsigned int buf_size           :  4;   /* per packet buffer size */
241 +               unsigned int                            : 28;
242 +#endif
243 +       } bits;
244 +} GMAC_CONFIG1_T;
245 +
246 +typedef union
247 +{
248 +       unsigned int bits32;
249 +       struct bit1_0020
250 +       {
251 +#if (BIG_ENDIAN==1)
252 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
253 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
254 +#else
255 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
256 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
257 +#endif
258 +       } bits;
259 +} GMAC_CONFIG2_T;
260 +
261 +typedef union
262 +{
263 +       unsigned int bits32;
264 +       struct bit1_0024
265 +       {
266 +#if (BIG_ENDIAN==1)
267 +               unsigned int                            : 16;
268 +               unsigned int buf_num            : 16;   /* return buffer number from software */
269 +#else
270 +               unsigned int buf_num            : 16;   /* return buffer number from software */
271 +               unsigned int                            : 16;
272 +#endif
273 +       } bits;
274 +} GMAC_BNCR_T;
275 +
276 +typedef union
277 +{
278 +       unsigned int bits32;
279 +       struct bit1_0028
280 +       {
281 +#if (BIG_ENDIAN==1)
282 +               unsigned int                            : 16;
283 +               unsigned int buf_remain         : 16;   /* remaining buffer number */
284 +#else
285 +               unsigned int buf_remain         : 16;   /* remaining buffer number */
286 +               unsigned int                            : 16;
287 +#endif
288 +       } bits;
289 +} GMAC_RBNR_T;
290 +
291 +typedef union
292 +{
293 +       unsigned int bits32;
294 +       struct bit1_002c
295 +       {
296 +#if (BIG_ENDIAN==1)
297 +               unsigned int                            : 25;
298 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
299 +               unsigned int phy_mode           :  1;   /* PHY interface mode in 10M-bps */
300 +               unsigned int duplex                     :  1;   /* duplex mode */
301 +               unsigned int speed                      :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
302 +               unsigned int link                       :  1;   /* link status */
303 +#else
304 +               unsigned int link                       :  1;   /* link status */
305 +               unsigned int speed                      :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
306 +               unsigned int duplex                     :  1;   /* duplex mode */
307 +               unsigned int phy_mode           :  1;   /* PHY interface mode in 10M-bps */
308 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
309 +               unsigned int                            : 25;
310 +#endif
311 +       } bits;
312 +} GMAC_STATUS_T;
313 +
314 +
315 +typedef union
316 +{
317 +       unsigned int bits32;
318 +       struct bit1_009
319 +       {
320 +#if (BIG_ENDIAN==1)
321 +               unsigned int                            : 10;
322 +               unsigned int tx_fail            :  1;   /* Tx fail interrupt */
323 +               unsigned int cnt_full           :  1;   /* MIB counters half full interrupt */
324 +               unsigned int rx_pause_on        :  1;   /* received pause on frame interrupt */
325 +               unsigned int tx_pause_on        :  1;   /* transmit pause on frame interrupt */
326 +               unsigned int rx_pause_off   :  1;       /* received pause off frame interrupt */
327 +               unsigned int tx_pause_off       :  1;   /* received pause off frame interrupt */
328 +               unsigned int rx_overrun         :  1;   /* GMAC Rx FIFO overrun interrupt */
329 +               unsigned int tx_underrun        :  1;   /* GMAC Tx FIFO underrun interrupt */
330 +               unsigned int                            :  6;
331 +               unsigned int m_tx_fail          :  1;   /* Tx fail interrupt mask */
332 +               unsigned int m_cnt_full         :  1;   /* MIB counters half full interrupt mask */
333 +               unsigned int m_rx_pause_on      :  1;   /* received pause on frame interrupt mask */
334 +               unsigned int m_tx_pause_on  :  1;       /* transmit pause on frame interrupt mask */
335 +               unsigned int m_rx_pause_off :  1;       /* received pause off frame interrupt mask */
336 +               unsigned int m_tx_pause_off     :  1;   /* received pause off frame interrupt mask */
337 +               unsigned int m_rx_overrun       :  1;   /* GMAC Rx FIFO overrun interrupt mask */
338 +               unsigned int m_tx_underrun      :  1;   /* GMAC Tx FIFO underrun interrupt mask */
339 +#else
340 +               unsigned int m_tx_underrun      :  1;   /* GMAC Tx FIFO underrun interrupt mask */
341 +               unsigned int m_rx_overrun       :  1;   /* GMAC Rx FIFO overrun interrupt mask */
342 +               unsigned int m_tx_pause_off     :  1;   /* received pause off frame interrupt mask */
343 +               unsigned int m_rx_pause_off :  1;       /* received pause off frame interrupt mask */
344 +               unsigned int m_tx_pause_on  :  1;       /* transmit pause on frame interrupt mask */
345 +               unsigned int m_rx_pause_on      :  1;   /* received pause on frame interrupt mask */
346 +               unsigned int m_cnt_full         :  1;   /* MIB counters half full interrupt mask */
347 +               unsigned int m_tx_fail          :  1;   /* Tx fail interrupt mask */
348 +               unsigned int                            :  6;
349 +               unsigned int tx_underrun        :  1;   /* GMAC Tx FIFO underrun interrupt */
350 +               unsigned int rx_overrun         :  1;   /* GMAC Rx FIFO overrun interrupt */
351 +               unsigned int tx_pause_off       :  1;   /* received pause off frame interrupt */
352 +               unsigned int rx_pause_off   :  1;       /* received pause off frame interrupt */
353 +               unsigned int tx_pause_on        :  1;   /* transmit pause on frame interrupt */
354 +               unsigned int rx_pause_on        :  1;   /* received pause on frame interrupt */
355 +               unsigned int cnt_full           :  1;   /* MIB counters half full interrupt */
356 +               unsigned int tx_fail            :  1;   /* Tx fail interrupt */
357 +               unsigned int                            : 10;
358 +#endif
359 +       } bits;
360 +} GMAC_INT_MASK_T;
361 +
362 +
363 +/*******************************************/
364 +/* the register structure of GMAC DMA      */
365 +/*******************************************/
366 +typedef union
367 +{
368 +       unsigned int bits32;
369 +       struct bit2_ff00
370 +       {
371 +#if (BIG_ENDIAN==1)
372 +               unsigned int                :  7;   /* reserved */
373 +               unsigned int s_ahb_err          :  1;   /* Slave AHB bus error */
374 +               unsigned int tx_err_code    :  4;   /* TxDMA error code */
375 +               unsigned int rx_err_code        :  4;   /* RxDMA error code */
376 +               unsigned int device_id          : 12;
377 +               unsigned int revision_id        :  4;
378 +#else
379 +               unsigned int revision_id        :  4;
380 +               unsigned int device_id          : 12;
381 +               unsigned int rx_err_code        :  4;   /* RxDMA error code */
382 +               unsigned int tx_err_code    :  4;   /* TxDMA error code */
383 +               unsigned int s_ahb_err          :  1;   /* Slave AHB bus error */
384 +               unsigned int                :  7;   /* reserved */
385 +#endif
386 +       } bits;
387 +} GMAC_DMA_DEVICE_ID_T;
388 +
389 +typedef union
390 +{
391 +       unsigned int bits32;
392 +       struct bit2_ff04
393 +       {
394 +#if (BIG_ENDIAN==1)
395 +               unsigned int ts_finish          :  1;   /* finished tx interrupt */
396 +               unsigned int ts_derr            :  1;   /* AHB Bus Error while tx */
397 +               unsigned int ts_perr            :  1;   /* Tx Descriptor protocol error */
398 +               unsigned int ts_eodi            :  1;   /* TxDMA end of descriptor interrupt */
399 +               unsigned int ts_eofi            :  1;   /* TxDMA end of frame interrupt */
400 +               unsigned int rs_finish          :  1;   /* finished rx interrupt */
401 +               unsigned int rs_derr            :  1;   /* AHB Bus Error while rx */
402 +               unsigned int rs_perr            :  1;   /* Rx Descriptor protocol error */
403 +               unsigned int rs_eodi            :  1;   /* RxDMA end of descriptor interrupt */
404 +               unsigned int rs_eofi            :  1;   /* RxDMA end of frame interrupt */
405 +               unsigned int                    :  1;   /* Tx fail interrupt */
406 +               unsigned int cnt_full           :  1;   /* MIB counters half full interrupt */
407 +               unsigned int rx_pause_on        :  1;   /* received pause on frame interrupt */
408 +               unsigned int tx_pause_on        :  1;   /* transmit pause on frame interrupt */
409 +               unsigned int rx_pause_off   :  1;       /* received pause off frame interrupt */
410 +               unsigned int tx_pause_off       :  1;   /* received pause off frame interrupt */
411 +               unsigned int rx_overrun         :  1;   /* GMAC Rx FIFO overrun interrupt */
412 +               unsigned int link_change        :  1;   /* GMAC link changed Interrupt for RGMII mode */
413 +               unsigned int                    :  1;
414 +               unsigned int                    :  1;
415 +               unsigned int                            :  3;
416 +               unsigned int loop_back          :  1;   /* loopback TxDMA to RxDMA */
417 +               unsigned int                    :  1;   /* Tx fail interrupt mask */
418 +               unsigned int m_cnt_full         :  1;   /* MIB counters half full interrupt mask */
419 +               unsigned int m_rx_pause_on      :  1;   /* received pause on frame interrupt mask */
420 +               unsigned int m_tx_pause_on  :  1;       /* transmit pause on frame interrupt mask */
421 +               unsigned int m_rx_pause_off :  1;       /* received pause off frame interrupt mask */
422 +               unsigned int m_tx_pause_off     :  1;   /* received pause off frame interrupt mask */
423 +               unsigned int m_rx_overrun       :  1;   /* GMAC Rx FIFO overrun interrupt mask */
424 +               unsigned int m_link_change      :  1;   /* GMAC link changed Interrupt mask for RGMII mode */
425 +#else
426 +               unsigned int m_link_change      :  1;   /* GMAC link changed Interrupt mask for RGMII mode */
427 +               unsigned int m_rx_overrun       :  1;   /* GMAC Rx FIFO overrun interrupt mask */
428 +               unsigned int m_tx_pause_off     :  1;   /* received pause off frame interrupt mask */
429 +               unsigned int m_rx_pause_off :  1;       /* received pause off frame interrupt mask */
430 +               unsigned int m_tx_pause_on  :  1;       /* transmit pause on frame interrupt mask */
431 +               unsigned int m_rx_pause_on      :  1;   /* received pause on frame interrupt mask */
432 +               unsigned int m_cnt_full         :  1;   /* MIB counters half full interrupt mask */
433 +               unsigned int                    :  1;   /* Tx fail interrupt mask */
434 +               unsigned int loop_back          :  1;   /* loopback TxDMA to RxDMA */
435 +               unsigned int                            :  3;
436 +               unsigned int                    :  1;
437 +               unsigned int                    :  1;
438 +               unsigned int link_change        :  1;   /* GMAC link changed Interrupt for RGMII mode */
439 +               unsigned int rx_overrun         :  1;   /* GMAC Rx FIFO overrun interrupt */
440 +               unsigned int tx_pause_off       :  1;   /* received pause off frame interrupt */
441 +               unsigned int rx_pause_off   :  1;       /* received pause off frame interrupt */
442 +               unsigned int tx_pause_on        :  1;   /* transmit pause on frame interrupt */
443 +               unsigned int rx_pause_on        :  1;   /* received pause on frame interrupt */
444 +               unsigned int cnt_full           :  1;   /* MIB counters half full interrupt */
445 +               unsigned int                    :  1;   /* Tx fail interrupt */
446 +               unsigned int rs_eofi            :  1;   /* RxDMA end of frame interrupt */
447 +               unsigned int rs_eodi            :  1;   /* RxDMA end of descriptor interrupt */
448 +               unsigned int rs_perr            :  1;   /* Rx Descriptor protocol error */
449 +               unsigned int rs_derr            :  1;   /* AHB Bus Error while rx */
450 +               unsigned int rs_finish          :  1;   /* finished rx interrupt */
451 +               unsigned int ts_eofi            :  1;   /* TxDMA end of frame interrupt */
452 +               unsigned int ts_eodi            :  1;   /* TxDMA end of descriptor interrupt */
453 +               unsigned int ts_perr            :  1;   /* Tx Descriptor protocol error */
454 +               unsigned int ts_derr            :  1;   /* AHB Bus Error while tx */
455 +               unsigned int ts_finish          :  1;   /* finished tx interrupt */
456 +#endif
457 +       } bits;
458 +} GMAC_DMA_STATUS_T;
459 +
460 +typedef union
461 +{
462 +       unsigned int bits32;
463 +       struct bit2_ff08
464 +       {
465 +#if (BIG_ENDIAN==1)
466 +               unsigned int td_start           :  1;   /* Start DMA transfer */
467 +               unsigned int td_continue        :  1;   /* Continue DMA operation */
468 +               unsigned int td_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
469 +               unsigned int                            :  1;
470 +               unsigned int td_prot            :  4;   /* TxDMA protection control */
471 +               unsigned int td_burst_size  :  2;       /* TxDMA max burst size for every AHB request */
472 +               unsigned int td_bus                 :  2;       /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */
473 +               unsigned int td_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
474 +               unsigned int td_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
475 +               unsigned int td_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
476 +               unsigned int td_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
477 +               unsigned int td_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
478 +               unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
479 +               unsigned int                            : 14;
480 +#else
481 +               unsigned int                            : 14;
482 +               unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
483 +               unsigned int td_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
484 +               unsigned int td_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
485 +               unsigned int td_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
486 +               unsigned int td_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
487 +               unsigned int td_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
488 +               unsigned int td_bus                 :  2;       /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */
489 +               unsigned int td_burst_size  :  2;       /* TxDMA max burst size for every AHB request */
490 +               unsigned int td_prot            :  4;   /* TxDMA protection control */
491 +               unsigned int                            :  1;
492 +               unsigned int td_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
493 +               unsigned int td_continue        :  1;   /* Continue DMA operation */
494 +               unsigned int td_start           :  1;   /* Start DMA transfer */
495 +#endif
496 +       } bits;
497 +} GMAC_TXDMA_CTRL_T;
498 +
499 +
500 +typedef union
501 +{
502 +       unsigned int bits32;
503 +       struct bit2_ff0c
504 +       {
505 +#if (BIG_ENDIAN==1)
506 +               unsigned int td_first_des_ptr   : 28;/* first descriptor address */
507 +               unsigned int td_busy                    :  1;/* 1-TxDMA busy; 0-TxDMA idle */
508 +               unsigned int                                    :  3;
509 +#else
510 +               unsigned int                                    :  3;
511 +               unsigned int td_busy                    :  1;/* 1-TxDMA busy; 0-TxDMA idle */
512 +               unsigned int td_first_des_ptr   : 28;/* first descriptor address */
513 +#endif
514 +       } bits;
515 +} GMAC_TXDMA_FIRST_DESC_T;
516 +
517 +typedef union
518 +{
519 +       unsigned int bits32;
520 +       struct bit2_ff10
521 +       {
522 +#if (BIG_ENDIAN==1)
523 +               unsigned int ndar                       : 28;   /* next descriptor address */
524 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
525 +               unsigned int                            :  1;
526 +               unsigned int sof_eof            :  2;
527 +#else
528 +               unsigned int sof_eof            :  2;
529 +               unsigned int                            :  1;
530 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
531 +               unsigned int ndar                       : 28;   /* next descriptor address */
532 +#endif
533 +       } bits;
534 +} GMAC_TXDMA_CURR_DESC_T;
535 +
536 +
537 +typedef union
538 +{
539 +       unsigned int bits32;
540 +       struct bit2_ff14
541 +       {
542 +#if (BIG_ENDIAN==1)
543 +               unsigned int rd_start           :  1;   /* Start DMA transfer */
544 +               unsigned int rd_continue        :  1;   /* Continue DMA operation */
545 +               unsigned int rd_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
546 +               unsigned int                            :  1;
547 +               unsigned int rd_prot            :  4;   /* DMA protection control */
548 +               unsigned int rd_burst_size  :  2;       /* DMA max burst size for every AHB request */
549 +               unsigned int rd_bus                 :  2;       /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */
550 +               unsigned int rd_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
551 +               unsigned int rd_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
552 +               unsigned int rd_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
553 +               unsigned int rd_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
554 +               unsigned int rd_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
555 +               unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
556 +               unsigned int                            : 14;
557 +#else
558 +               unsigned int                            : 14;
559 +               unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
560 +               unsigned int rd_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
561 +               unsigned int rd_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
562 +               unsigned int rd_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
563 +               unsigned int rd_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
564 +               unsigned int rd_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
565 +               unsigned int rd_bus                 :  2;       /* peripheral bus width;0x->8 bits,10->16 bits,11->32 bits */
566 +               unsigned int rd_burst_size  :  2;       /* DMA max burst size for every AHB request */
567 +               unsigned int rd_prot            :  4;   /* DMA protection control */
568 +               unsigned int                            :  1;
569 +               unsigned int rd_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
570 +               unsigned int rd_continue        :  1;   /* Continue DMA operation */
571 +               unsigned int rd_start           :  1;   /* Start DMA transfer */
572 +#endif
573 +       } bits;
574 +} GMAC_RXDMA_CTRL_T;
575 +
576 +
577 +typedef union
578 +{
579 +       unsigned int bits32;
580 +       struct bit2_ff18
581 +       {
582 +#if (BIG_ENDIAN==1)
583 +               unsigned int rd_first_des_ptr   : 28;/* first descriptor address */
584 +               unsigned int rd_busy                    :  1;/* 1-RxDMA busy; 0-RxDMA idle */
585 +               unsigned int                                    :  3;
586 +#else
587 +               unsigned int                                    :  3;
588 +               unsigned int rd_busy                    :  1;/* 1-RxDMA busy; 0-RxDMA idle */
589 +               unsigned int rd_first_des_ptr   : 28;/* first descriptor address */
590 +#endif
591 +       } bits;
592 +} GMAC_RXDMA_FIRST_DESC_T;
593 +
594 +typedef union
595 +{
596 +       unsigned int bits32;
597 +       struct bit2_ff1c
598 +       {
599 +#if (BIG_ENDIAN==1)
600 +               unsigned int ndar                       : 28;   /* next descriptor address */
601 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
602 +               unsigned int                            :  1;
603 +               unsigned int sof_eof            :  2;
604 +#else
605 +               unsigned int sof_eof            :  2;
606 +               unsigned int                            :  1;
607 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
608 +               unsigned int ndar                       : 28;   /* next descriptor address */
609 +#endif
610 +       } bits;
611 +} GMAC_RXDMA_CURR_DESC_T;
612 +
613 +
614 +/********************************************/
615 +/*          Descriptor Format               */
616 +/********************************************/
617 +
618 +typedef struct descriptor_t
619 +{
620 +       union frame_control_t
621 +       {
622 +               unsigned int bits32;
623 +               struct bits_0000
624 +               {
625 +#if (BIG_ENDIAN==1)
626 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
627 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
628 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
629 +                       unsigned int csum_state : 3;    /* checksum error status */
630 +                       unsigned int vlan_tag   : 1;    /* 802.1q vlan tag packet */
631 +                       unsigned int frame_state: 3;    /* reference Rx Status1 */
632 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
633 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
634 +#else
635 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
636 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
637 +                       unsigned int frame_state: 3;    /* reference Rx Status1 */
638 +                       unsigned int vlan_tag   : 1;    /* 802.1q vlan tag packet */
639 +                       unsigned int csum_state : 3;    /* checksum error status */
640 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
641 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
642 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
643 +#endif
644 +               } bits_rx;
645 +
646 +               struct bits_0001
647 +               {
648 +#if (BIG_ENDIAN==1)
649 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
650 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
651 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
652 +                       unsigned int            : 6;
653 +                       unsigned int success_tx : 1;    /* successful transmitted */
654 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
655 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
656 +#else
657 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
658 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
659 +                       unsigned int success_tx : 1;    /* successful transmitted */
660 +                       unsigned int            : 6;
661 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
662 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
663 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
664 +#endif
665 +        } bits_tx_in;
666 +
667 +               struct bits_0002
668 +               {
669 +#if (BIG_ENDIAN==1)
670 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
671 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
672 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
673 +                       unsigned int            : 2;
674 +                       unsigned int udp_csum_en: 1;    /* TSS UDP checksum enable */
675 +                       unsigned int tcp_csum_en: 1;    /* TSS TCP checksum enable */
676 +                       unsigned int ipv6_tx_en : 1;    /* TSS IPv6 TX enable */
677 +                       unsigned int ip_csum_en : 1;    /* TSS IPv4 IP Header checksum enable */
678 +                       unsigned int vlan_enable: 1;    /* VLAN TIC insertion enable */
679 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
680 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
681 +#else
682 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
683 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
684 +                       unsigned int vlan_enable: 1;    /* VLAN TIC insertion enable */
685 +                       unsigned int ip_csum_en : 1;    /* TSS IPv4 IP Header checksum enable */
686 +                       unsigned int ipv6_tx_en : 1;    /* TSS IPv6 TX enable */
687 +                       unsigned int tcp_csum_en: 1;    /* TSS TCP checksum enable */
688 +                       unsigned int udp_csum_en: 1;    /* TSS UDP checksum enable */
689 +                       unsigned int            : 2;
690 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
691 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
692 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
693 +#endif
694 +        } bits_tx_out;
695 +
696 +       } frame_ctrl;
697 +
698 +       union flag_status_t
699 +       {
700 +               unsigned int bits32;
701 +               struct bits_0004
702 +               {
703 +#if (BIG_ENDIAN==1)
704 +            unsigned int priority   : 3;    /* user priority extracted from receiving frame*/
705 +            unsigned int cfi        : 1;       /* cfi extracted from receiving frame*/
706 +                       unsigned int vlan_id    :12;    /* VLAN ID extracted from receiving frame */
707 +                       unsigned int frame_count:16;    /* received frame byte count,include CRC,not include VLAN TIC */
708 +#else
709 +                       unsigned int frame_count:16;    /* received frame byte count,include CRC,not include VLAN TIC */
710 +                       unsigned int vlan_id    :12;    /* VLAN ID extracted from receiving frame */
711 +            unsigned int cfi        : 1;       /* cfi extracted from receiving frame*/
712 +            unsigned int priority   : 3;    /* user priority extracted from receiving frame*/
713 +#endif
714 +               } bits_rx_status;
715 +
716 +               struct bits_0005
717 +               {
718 +#if (BIG_ENDIAN==1)
719 +            unsigned int priority   : 3;    /* user priority to transmit*/
720 +            unsigned int cfi        : 1;       /* cfi to transmit*/
721 +                       unsigned int vlan_id    :12;    /* VLAN ID to transmit */
722 +                       unsigned int frame_count:16;    /* total tx frame byte count */
723 +#else
724 +                       unsigned int frame_count:16;    /* total tx frame byte count */
725 +                       unsigned int vlan_id    :12;    /* VLAN ID to transmit */
726 +            unsigned int cfi        : 1;       /* cfi to transmit*/
727 +            unsigned int priority   : 3;    /* user priority to transmit*/
728 +#endif
729 +               } bits_tx_flag;
730 +       } flag_status;
731 +
732 +       unsigned int buf_adr;   /* data buffer address */
733 +
734 +       union next_desc_t
735 +       {
736 +               unsigned int next_descriptor;
737 +               struct bits_000c
738 +               {
739 +#if (BIG_ENDIAN==1)
740 +                       unsigned int ndar               :28;    /* next descriptor address */
741 +                       unsigned int eofie              : 1;    /* end of frame interrupt enable */
742 +                       unsigned int                    : 1;
743 +                       unsigned int sof_eof    : 2;    /* 00-the linking descriptor   01-the last descriptor of a frame*/
744 +                                                       /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
745 +#else
746 +                       unsigned int sof_eof    : 2;    /* 00-the linking descriptor   01-the last descriptor of a frame*/
747 +                                                       /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
748 +                       unsigned int                    : 1;
749 +                       unsigned int eofie              : 1;    /* end of frame interrupt enable */
750 +                       unsigned int ndar               :28;    /* next descriptor address */
751 +#endif
752 +               } bits;
753 +       } next_desc;
754 +} GMAC_DESCRIPTOR_T;
755 +
756 +typedef struct gmac_conf {
757 +       struct net_device *dev;
758 +       int portmap;
759 +       int vid;
760 +       int flag;     /* 1: active  0: non-active */
761 +} sys_gmac_conf;
762 +
763 +struct gmac_private {
764 +       unsigned char       *tx_bufs;   /* Tx bounce buffer region. */
765 +       unsigned char       *rx_bufs;
766 +       GMAC_DESCRIPTOR_T       *tx_desc;       /* point to virtual TX descriptor address*/
767 +       GMAC_DESCRIPTOR_T       *rx_desc;       /* point to virtual RX descriptor address*/
768 +       GMAC_DESCRIPTOR_T       *tx_cur_desc;   /* point to current TX descriptor */
769 +       GMAC_DESCRIPTOR_T       *rx_cur_desc;   /* point to current RX descriptor */
770 +       GMAC_DESCRIPTOR_T   *tx_finished_desc;
771 +       GMAC_DESCRIPTOR_T   *rx_finished_desc;
772 +       unsigned long       cur_tx;
773 +       unsigned int        cur_rx;     /* Index into the Rx buffer of next Rx pkt. */
774 +       unsigned int        tx_flag;
775 +       unsigned long       dirty_tx;
776 +       unsigned char       *tx_buf[TX_DESC_NUM];       /* Tx bounce buffers */
777 +       dma_addr_t          tx_desc_dma; /* physical TX descriptor address */
778 +       dma_addr_t          rx_desc_dma;        /* physical RX descriptor address */
779 +       dma_addr_t          tx_bufs_dma; /* physical TX descriptor address */
780 +       dma_addr_t          rx_bufs_dma; /* physical RX descriptor address */
781 +    struct net_device_stats  stats;
782 +       pid_t               thr_pid;
783 +       wait_queue_head_t   thr_wait;
784 +       struct completion   thr_exited;
785 +    spinlock_t          lock;
786 +    int                 time_to_die;
787 +       unsigned int            tx_desc_hdr[GMAC_PHY_IF];       /* the descriptor which sw can fill */
788 +       unsigned int            tx_desc_tail[GMAC_PHY_IF];      /* the descriptor which is not cleaned yet */
789 +};
790 +
791 +
792 +struct reg_ioctl_data {
793 +    unsigned int    reg_addr;   /* the register address */
794 +    unsigned int    val_in;     /* data write to the register */
795 +    unsigned int    val_out;    /* data read from the register */
796 +};
797 +
798 +#ifdef CONFIG_SL2312_MPAGE
799 +typedef struct tx_data_t {
800 +       int     freeable; // 1 when it's skb. it can be freed in tx interrupt handler
801 +       struct sk_buff* skb; // skb
802 +       int     desc_in_use; // 1 when the desc is in use. 0 when desc is available.
803 +       long end_seq; // to find out packets are in seq.
804 +       // so this value is the seq of next packet.
805 +} tx_data;
806 +#endif
807 +
808 +/*************************************************************
809 + *         Global Variable
810 + *************************************************************/
811 +struct semaphore        sem_gmac;   /* semaphore for share pins issue */
812 +
813 +/*************************************************************
814 + *        Static Global Variable
815 + *************************************************************/
816 +// static unsigned int     MAC_BASE_ADDR = GMAC0_BASE;
817 +static unsigned int     gmac_base_addr[GMAC_PHY_IF] = {GMAC0_BASE,GMAC1_BASE};
818 +static unsigned int     gmac_irq[GMAC_PHY_IF] = {IRQ_GMAC0,IRQ_GMAC1};
819 +static struct net_device *gmac_dev[GMAC_PHY_IF];
820 +
821 +static unsigned int     FLAG_SWITCH=0; /* if 1-->switch chip presented. if 0-->switch chip unpresented */
822 +static unsigned int     flow_control_enable[GMAC_PHY_IF] = {1,1};
823 +static unsigned int     pre_phy_status[GMAC_PHY_IF] = {LINK_DOWN,LINK_DOWN};
824 +static unsigned int     tx_desc_virtual_base[GMAC_PHY_IF];
825 +static unsigned int     rx_desc_virtual_base[GMAC_PHY_IF];
826 +static unsigned int     full_duplex = 1;
827 +static unsigned int     speed = 1;
828 +#ifdef CONFIG_SL2312_MPAGE
829 +static tx_data             tx_skb[GMAC_PHY_IF][TX_DESC_NUM];
830 +#else
831 +static struct sk_buff   *tx_skb[GMAC_PHY_IF][TX_DESC_NUM];
832 +#endif
833 +static struct sk_buff   *rx_skb[GMAC_PHY_IF][RX_DESC_NUM];
834 +static unsigned int     tx_desc_start_adr[GMAC_PHY_IF];
835 +static unsigned int     rx_desc_start_adr[GMAC_PHY_IF];
836 +static unsigned char    eth0_mac[6]= {0x00,0x50,0xc2,0x2b,0xd3,0x25};
837 +static unsigned char    eth1_mac[6]= {0x00,0x50,0xc2,0x2b,0xdf,0xfe};
838 +static unsigned int     next_tick = 3 * HZ;
839 +
840 +static unsigned int     phy_addr[GMAC_PHY_IF] = {0x01,0x02};  /* define PHY address */
841 +
842 +DECLARE_WAIT_QUEUE_HEAD(gmac_queue);
843 +//static       wait_queue_t    wait;
844 +
845 +struct gmac_conf VLAN_conf[] = {
846 +#ifdef CONFIG_ADM_6999
847 +       { (struct net_device *)0,0x7F,1 },
848 +       { (struct net_device *)0,0x80,2 }
849 +#endif
850 +#ifdef CONFIG_ADM_6996
851 +       { (struct net_device *)0,0x0F,1 },
852 +       { (struct net_device *)0,0x10,2 }
853 +#endif
854 +};
855 +
856 +#define NUM_VLAN_IF    (sizeof(VLAN_conf)/sizeof(struct gmac_conf))
857 +
858 +
859 +/************************************************/
860 +/*            GMAC function declare             */
861 +/************************************************/
862 +
863 +unsigned int mii_read(unsigned char phyad,unsigned char regad);
864 +void mii_write(unsigned char phyad,unsigned char regad,unsigned int value);
865 +static void gmac_set_phy_status(struct net_device *dev);
866 +static void gmac_get_phy_status(struct net_device *dev);
867 +static int gmac_phy_thread (void *data);
868 +static int gmac_set_mac_address(struct net_device *dev, void *addr);
869 +static void gmac_tx_timeout(struct net_device *dev);
870 +static void gmac_tx_packet_complete(struct net_device *dev);
871 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev);
872 +static void gmac_set_rx_mode(struct net_device *dev);
873 +static void gmac_rx_packet(struct net_device *dev);
874 +static int gmac_open (struct net_device *dev);
875 +static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
876 +
877 +static unsigned int gmac_get_dev_index(struct net_device *dev);
878 +static unsigned int gmac_select_interface(struct net_device *dev);
879 +
880 +#ifdef CONFIG_SL2312_MPAGE
881 +int printk_all(int dev_index, struct gmac_private* tp);
882 +#endif
883 +
884 +/****************************************/
885 +/*     SPI Function Declare            */
886 +/****************************************/
887 +void SPI_write(unsigned char addr,unsigned int value);
888 +unsigned int SPI_read(unsigned char table,unsigned char addr);
889 +void SPI_write_bit(char bit_EEDO);
890 +unsigned int SPI_read_bit(void);
891 +void SPI_default(void);
892 +void SPI_reset(unsigned char rstype,unsigned char port_cnt);
893 +void SPI_pre_st(void);
894 +void SPI_CS_enable(unsigned char enable);
895 +void SPI_Set_VLAN(unsigned char LAN,unsigned int port_mask);
896 +void SPI_Set_tag(unsigned int port,unsigned tag);
897 +void SPI_Set_PVID(unsigned int PVID,unsigned int port_mask);
898 +unsigned int SPI_Get_PVID(unsigned int port);
899 +void SPI_mac_lock(unsigned int port, unsigned char lock);
900 +void SPI_get_port_state(unsigned int port);
901 +void SPI_port_enable(unsigned int port,unsigned char enable);
902 +unsigned int SPI_get_identifier(void);
903 +void SPI_get_status(unsigned int port);
904 +
905 +/****************************************/
906 +/*     VLAN Function Declare                   */
907 +/****************************************/
908 +int getVLANfromdev (struct net_device *dev );
909 +struct net_device * getdevfromVLAN( int VID);
910 +
911 +
912 +
913 +/************************************************/
914 +/*                 function body                */
915 +/************************************************/
916 +#if 0
917 +void hw_memcpy(void *to,const void *from,unsigned long n)
918 +{
919 +    writel(from,SL2312_DRAM_CTRL_BASE+0x20);  /* set source address */
920 +    writel(to,SL2312_DRAM_CTRL_BASE+0x24);    /* set destination address */
921 +    writel(n,SL2312_DRAM_CTRL_BASE+0x28);     /* set byte count */
922 +    writel(0x00000001,SL2312_DRAM_CTRL_BASE+0x2c);
923 +    while (readl(SL2312_DRAM_CTRL_BASE+0x2c));
924 +}
925 +#endif
926 +
927 +static unsigned int gmac_read_reg(unsigned int addr)
928 +{
929 +    unsigned int    reg_val;
930 +//    unsigned int    flags;
931 +//    spinlock_t     lock;
932 +
933 +//    spin_lock_irqsave(&lock, flags);
934 +    reg_val = readl(addr);     // Gary Chen
935 +//     spin_unlock_irqrestore(&lock, flags);
936 +       return (reg_val);
937 +}
938 +
939 +static void gmac_write_reg(unsigned int addr,unsigned int data,unsigned int bit_mask)
940 +{
941 +       unsigned int    reg_val;
942 +    //unsigned int    *addr;
943 +//    unsigned int    flags;
944 +//    spinlock_t     lock;
945 +
946 +//    spin_lock_irqsave(&lock, flags);
947 +       reg_val = ( gmac_read_reg(addr) & (~bit_mask) ) | (data & bit_mask);
948 +    writel(reg_val,addr);
949 +//     spin_unlock_irqrestore(&lock, flags);
950 +       return;
951 +}
952 +
953 +
954 +static void gmac_sw_reset(struct net_device *dev)
955 +{
956 +    unsigned int    index;
957 +    unsigned int    reg_val;
958 +
959 +    index = gmac_get_dev_index(dev);
960 +    if (index==0)
961 +        reg_val = readl(GMAC_GLOBAL_BASE_ADDR+0x0c) | 0x00000020;   /* GMAC0 S/W reset */
962 +    else
963 +        reg_val = readl(GMAC_GLOBAL_BASE_ADDR+0x0c) | 0x00000040;   /* GMAC1 S/W reset */
964 +
965 +    writel(reg_val,GMAC_GLOBAL_BASE_ADDR+0x0c);
966 +    return;
967 +}
968 +
969 +static void gmac_get_mac_address(void)
970 +{
971 +#ifdef CONFIG_MTD
972 +       extern int get_vlaninfo(vlaninfo* vlan);
973 +    static vlaninfo    vlan[2];
974 +
975 +    if (get_vlaninfo(&vlan[0]))
976 +    {
977 +        memcpy(eth0_mac,vlan[0].mac,6);
978 +        VLAN_conf[0].vid = vlan[0].vlanid;
979 +        VLAN_conf[0].portmap = vlan[0].vlanmap;
980 +        memcpy(eth1_mac,vlan[1].mac,6);
981 +        VLAN_conf[1].vid = vlan[1].vlanid;
982 +        VLAN_conf[1].portmap = vlan[1].vlanmap;
983 +    }
984 +#else
985 +    unsigned int reg_val;
986 +
987 +    reg_val = readl(IO_ADDRESS(SL2312_SECURITY_BASE)+0xac);
988 +    eth0_mac[4] = (reg_val & 0xff00) >> 8;
989 +    eth0_mac[5] = reg_val & 0x00ff;
990 +    reg_val = readl(IO_ADDRESS(SL2312_SECURITY_BASE)+0xac);
991 +    eth1_mac[4] = (reg_val & 0xff00) >> 8;
992 +    eth1_mac[5] = reg_val & 0x00ff;
993 +#endif
994 +    return;
995 +}
996 +
997 +static unsigned int gmac_get_dev_index(struct net_device *dev)
998 +{
999 +    unsigned int    i;
1000 +
1001 +    /* get device index number */
1002 +    for (i=0;i<GMAC_PHY_IF;i++)
1003 +    {
1004 +        if (gmac_dev[i]==dev)
1005 +        {
1006 +            return(i);
1007 +        }
1008 +    }
1009 +    return (0xff);
1010 +}
1011 +
1012 +static unsigned int gmac_select_interface(struct net_device *dev)
1013 +{
1014 +    unsigned int    index;
1015 +
1016 +    index = gmac_get_dev_index(dev);
1017 +    // MAC_BASE_ADDR = gmac_base_addr[index];  // Gary Chen
1018 +    return (index);
1019 +}
1020 +
1021 +
1022 +static void gmac_dump_register(struct net_device *dev)
1023 +{
1024 +#if 0
1025 +    unsigned int   i,val,index;
1026 +
1027 +    index = gmac_select_interface(dev);
1028 +
1029 +    printk("========== GMAC%d ==========\n",index);
1030 +    for (i=0;i<=0x7c;i=i+4)
1031 +    {
1032 +        val = gmac_read_reg(gmac_base_addr[index] + i);
1033 +        printk("offset = %08x   value = %08x\n",i,val);
1034 +    }
1035 +    for (i=0xff00;i<=0xff7c;i=i+4)
1036 +    {
1037 +        val = gmac_read_reg(gmac_base_addr[index] + i);
1038 +        printk("offset = %08x   value = %08x\n",i,val);
1039 +    }
1040 +#endif
1041 +}
1042 +
1043 +static int gmac_init_chip(struct net_device *dev)
1044 +{
1045 +       GMAC_RBNR_T             rbnr_val,rbnr_mask;
1046 +       GMAC_CONFIG2_T  config2_val;
1047 +       GMAC_CONFIG0_T  config0,config0_mask;
1048 +       GMAC_CONFIG1_T  config1;
1049 +       struct sockaddr sock;
1050 +       unsigned int    status;
1051 +       unsigned int    phy_mode;
1052 +       unsigned int    index;
1053 +
1054 +    index = gmac_get_dev_index(dev);
1055 +
1056 +    /* set GMAC RMII mode */
1057 +    if (index==0)
1058 +        phy_mode = 0;   /* 0->MII 1->GMII 2->RGMII(10/100) 3->RGMII(1000) */
1059 +    else
1060 +        phy_mode = 2;   /* 0->MII 1->GMII 2->RGMII(10/100) 3->RGMII(1000) */
1061 +
1062 +    /* set PHY operation mode */
1063 +    status = (phy_mode<<5) | 0x11 | (full_duplex<<3) | (speed<<1);
1064 +    gmac_write_reg(gmac_base_addr[index] + GMAC_STATUS,status ,0x0000007f);
1065 +
1066 +       /* set station MAC address1 and address2 */
1067 +       if (index==0)
1068 +           memcpy(&sock.sa_data[0],&eth0_mac[0],6);
1069 +    else
1070 +           memcpy(&sock.sa_data[0],&eth1_mac[0],6);
1071 +    gmac_set_mac_address(dev,(void *)&sock);
1072 +
1073 +    /* set RX_FLTR register to receive all multicast packet */
1074 +    gmac_write_reg(gmac_base_addr[index] + GMAC_RX_FLTR,0x0000001F,0x0000001f);
1075 +    //gmac_write_reg(gmac_base_addr[index] + GMAC_RX_FLTR,0x00000007,0x0000001f);
1076 +
1077 +       /* set per packet buffer size */
1078 +       config1.bits32 = 0;
1079 +    config1.bits.buf_size = 11; /* buffer size = 2048-byte */
1080 +    gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG1,config1.bits32,0x0000000f);
1081 +
1082 +       /* set flow control threshold */
1083 +       config2_val.bits32 = 0;
1084 +       config2_val.bits.set_threshold = RX_DESC_NUM/4;
1085 +       config2_val.bits.rel_threshold = RX_DESC_NUM*3/4;
1086 +       gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG2,config2_val.bits32,0xffffffff);
1087 +
1088 +       /* init remaining buffer number register */
1089 +       rbnr_val.bits32 = 0;
1090 +       rbnr_val.bits.buf_remain = RX_DESC_NUM;
1091 +       rbnr_mask.bits32 = 0;
1092 +       rbnr_mask.bits.buf_remain = 0xffff;
1093 +       gmac_write_reg(gmac_base_addr[index] + GMAC_RBNR,rbnr_val.bits32,rbnr_mask.bits32);
1094 +
1095 +    /* disable TX/RX and disable internal loop back */
1096 +    config0.bits32 = 0;
1097 +    config0_mask.bits32 = 0;
1098 +    config0.bits.max_len = 2;
1099 +    if (flow_control_enable[index]==1)
1100 +    {
1101 +        config0.bits.tx_fc_en = 1; /* enable tx flow control */
1102 +        config0.bits.rx_fc_en = 1; /* enable rx flow control */
1103 +        printk("Enable MAC Flow Control...\n");
1104 +    }
1105 +    else
1106 +    {
1107 +        config0.bits.tx_fc_en = 0; /* disable tx flow control */
1108 +        config0.bits.rx_fc_en = 0; /* disable rx flow control */
1109 +        printk("Disable MAC Flow Control...\n");
1110 +    }
1111 +    config0.bits.dis_rx = 1;  /* disable rx */
1112 +    config0.bits.dis_tx = 1;  /* disable tx */
1113 +    config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
1114 +       config0.bits.inv_rx_clk = 0;
1115 +       config0.bits.rising_latch = 1;
1116 +       config0.bits.ipv4_tss_rx_en = 1;  /* enable H/W to check ip checksum */
1117 +       config0.bits.ipv6_tss_rx_en = 1;  /* enable H/W to check ip checksum */
1118 +
1119 +    config0_mask.bits.max_len = 7;
1120 +    config0_mask.bits.tx_fc_en = 1;
1121 +    config0_mask.bits.rx_fc_en = 1;
1122 +    config0_mask.bits.dis_rx = 1;
1123 +    config0_mask.bits.dis_tx = 1;
1124 +    config0_mask.bits.loop_back = 1;
1125 +    config0_mask.bits.inv_rx_clk = 1;
1126 +       config0_mask.bits.rising_latch = 1;
1127 +       config0_mask.bits.ipv4_tss_rx_en = 1;
1128 +       config0_mask.bits.ipv6_tss_rx_en = 1;
1129 +    gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
1130 +
1131 +       return (0);
1132 +}
1133 +
1134 +static void gmac_enable_tx_rx(struct net_device *dev)
1135 +{
1136 +       GMAC_CONFIG0_T  config0,config0_mask;
1137 +       int                             dev_index;
1138 +
1139 +    dev_index = gmac_select_interface(dev);
1140 +
1141 +    /* enable TX/RX */
1142 +    config0.bits32 = 0;
1143 +    config0_mask.bits32 = 0;
1144 +    config0.bits.dis_rx = 0;  /* enable rx */
1145 +    config0.bits.dis_tx = 0;  /* enable tx */
1146 +    config0_mask.bits.dis_rx = 1;
1147 +    config0_mask.bits.dis_tx = 1;
1148 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
1149 +}
1150 +
1151 +static void gmac_disable_tx_rx(struct net_device *dev)
1152 +{
1153 +       GMAC_CONFIG0_T  config0,config0_mask;
1154 +       int                             dev_index;
1155 +
1156 +    dev_index = gmac_select_interface(dev);
1157 +
1158 +    /* enable TX/RX */
1159 +    config0.bits32 = 0;
1160 +    config0_mask.bits32 = 0;
1161 +    config0.bits.dis_rx = 1;  /* disable rx */
1162 +    config0.bits.dis_tx = 1;  /* disable tx */
1163 +    config0_mask.bits.dis_rx = 1;
1164 +    config0_mask.bits.dis_tx = 1;
1165 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
1166 +}
1167 +
1168 +#ifdef CONFIG_SL_NAPI
1169 +static int gmac_rx_poll_ga(struct net_device *dev, int *budget)
1170 +{
1171 +       struct gmac_private *tp = dev->priv;
1172 +       struct sk_buff          *skb;
1173 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1174 +       GMAC_RXDMA_FIRST_DESC_T rxdma_busy;
1175 +    GMAC_DESCRIPTOR_T   *rx_desc;
1176 +       unsigned int            pkt_size;
1177 +       unsigned int        desc_count;
1178 +    unsigned int        vid;
1179 +//    unsigned int        priority;
1180 +       unsigned int        own;
1181 +       unsigned int        good_frame = 0;
1182 +       unsigned int        index;
1183 +       unsigned int        dev_index;
1184 +       int                 work = 0;
1185 +       int                 work_done = 0;
1186 +       int                 quota = min(dev->quota, *budget);
1187 +
1188 +    dev_index = gmac_select_interface(dev);
1189 +
1190 +       for (;;)
1191 +       {
1192 +        own = tp->rx_cur_desc->frame_ctrl.bits32 >> 31;
1193 +        if (own == CPU) /* check owner bit */
1194 +        {
1195 +               rx_desc = tp->rx_cur_desc;
1196 +#if (GMAC_DEBUG==1)
1197 +               /* check error interrupt */
1198 +               if ( (rx_desc->frame_ctrl.bits_rx.derr==1)||(rx_desc->frame_ctrl.bits_rx.perr==1) )
1199 +               {
1200 +               printk("%s::Rx Descriptor Processing Error !!!\n",__func__);
1201 +           }
1202 +#endif
1203 +           /* get frame information from the first descriptor of the frame */
1204 +               pkt_size = rx_desc->flag_status.bits_rx_status.frame_count - 4;  /*total byte count in a frame*/
1205 +#if (GMAC_DEBUG==1)
1206 +            priority = rx_desc->flag_status.bits_rx_status.priority;    /* 802.1p priority */
1207 +#endif
1208 +            vid = rx_desc->flag_status.bits_rx_status.vlan_id;          /* 802.1q vlan id */
1209 +            if (vid == 0)
1210 +            {
1211 +                vid = 1;    /* default vlan */
1212 +            }
1213 +               desc_count = rx_desc->frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */
1214 +
1215 +               if (rx_desc->frame_ctrl.bits_rx.frame_state == 0x000) /* good frame */
1216 +               {
1217 +                       tp->stats.rx_bytes += pkt_size;
1218 +                       tp->stats.rx_packets++;
1219 +                       good_frame = 1;
1220 +               }
1221 +               else
1222 +               {
1223 +                       tp->stats.rx_errors++;
1224 +                       good_frame = 0;
1225 +                       printk("RX status: 0x%x\n",rx_desc->frame_ctrl.bits_rx.frame_state);
1226 +               }
1227 +       }
1228 +       else
1229 +       {
1230 +           work_done = 1;
1231 +           break;  /* Rx process is completed */
1232 +       }
1233 +
1234 +        if (good_frame == 1)
1235 +        {
1236 +            /* get rx skb buffer index */
1237 +            index = ((unsigned int)tp->rx_cur_desc - rx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1238 +            if (rx_skb[dev_index][index])
1239 +            {
1240 +                skb_reserve (rx_skb[dev_index][index], 2);     /* 16 byte align the IP fields. */
1241 +                rx_skb[dev_index][index]->dev = dev;
1242 +                rx_skb[dev_index][index]->ip_summed = CHECKSUM_UNNECESSARY;
1243 +                           skb_put(rx_skb[dev_index][index],pkt_size);
1244 +                           rx_skb[dev_index][index]->protocol = eth_type_trans(rx_skb[dev_index][index],dev); /* set skb protocol */
1245 +                           netif_rx(rx_skb[dev_index][index]);  /* socket rx */
1246 +                           dev->last_rx = jiffies;
1247 +
1248 +                           /* allocate rx skb buffer */
1249 +                if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
1250 +                {
1251 +                    printk("%s::skb buffer allocation fail !\n",__func__);
1252 +                }
1253 +                rx_skb[dev_index][index] = skb;
1254 +                tp->rx_cur_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
1255 +            }
1256 +            else
1257 +            {
1258 +                printk("%s::rx skb index error !\n",__func__);
1259 +            }
1260 +        }
1261 +
1262 +           tp->rx_cur_desc->frame_ctrl.bits_rx.own = DMA; /* release rx descriptor to DMA */
1263 +        /* point to next rx descriptor */
1264 +        tp->rx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->rx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+rx_desc_virtual_base[dev_index]);
1265 +
1266 +        /* release buffer to Remaining Buffer Number Register */
1267 +        if (flow_control_enable[dev_index] ==1)
1268 +        {
1269 +//            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_BNCR,desc_count,0x0000ffff);
1270 +            writel(desc_count,(unsigned int *)(gmac_base_addr[dev_index] + GMAC_BNCR));
1271 +        }
1272 +
1273 +               if (work++ >= quota )
1274 +               {
1275 +                       break;
1276 +               }
1277 +    }
1278 +
1279 +    /* if RX DMA process is stoped , restart it */
1280 +       rxdma_busy.bits.rd_first_des_ptr = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC);
1281 +       if (rxdma_busy.bits.rd_busy == 0)
1282 +       {
1283 +           rxdma_ctrl.bits32 = 0;
1284 +       rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1285 +           rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1286 +           rxdma_ctrl_mask.bits32 = 0;
1287 +       rxdma_ctrl_mask.bits.rd_start = 1;
1288 +           rxdma_ctrl_mask.bits.rd_continue = 1;
1289 +           gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1290 +    }
1291 +
1292 +       dev->quota -= work;
1293 +       *budget -= work;
1294 +       if (work_done==1)
1295 +       {
1296 +           /* Receive descriptor is empty now */
1297 +        netif_rx_complete(dev);
1298 +        /* enable receive interrupt */
1299 +        gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,0x0007c000,0x0007c000);   /* enable rx interrupt */
1300 +        return 0;
1301 +    }
1302 +    else
1303 +    {
1304 +        return -1;
1305 +    }
1306 +}
1307 +
1308 +static int gmac_rx_poll_gb(struct net_device *dev, int *budget)
1309 +{
1310 +       struct gmac_private *tp = dev->priv;
1311 +       struct sk_buff          *skb;
1312 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1313 +       GMAC_RXDMA_FIRST_DESC_T rxdma_busy;
1314 +    GMAC_DESCRIPTOR_T   *rx_desc;
1315 +       unsigned int            pkt_size;
1316 +       unsigned int        desc_count;
1317 +    unsigned int        vid;
1318 +//    unsigned int        priority;
1319 +       unsigned int        own;
1320 +       unsigned int        good_frame = 0;
1321 +       unsigned int        index;
1322 +       unsigned int        dev_index;
1323 +       int                 work = 0;
1324 +       int                 work_done = 0;
1325 +       int                 quota = min(dev->quota, *budget);
1326 +
1327 +    dev_index = gmac_select_interface(dev);
1328 +
1329 +       for (;;)
1330 +       {
1331 +        own = tp->rx_cur_desc->frame_ctrl.bits32 >> 31;
1332 +        if (own == CPU) /* check owner bit */
1333 +        {
1334 +               rx_desc = tp->rx_cur_desc;
1335 +#if (GMAC_DEBUG==1)
1336 +               /* check error interrupt */
1337 +               if ( (rx_desc->frame_ctrl.bits_rx.derr==1)||(rx_desc->frame_ctrl.bits_rx.perr==1) )
1338 +               {
1339 +               printk("%s::Rx Descriptor Processing Error !!!\n",__func__);
1340 +           }
1341 +#endif
1342 +           /* get frame information from the first descriptor of the frame */
1343 +               pkt_size = rx_desc->flag_status.bits_rx_status.frame_count - 4;  /*total byte count in a frame*/
1344 +#if (GMAC_DEBUG==1)
1345 +            priority = rx_desc->flag_status.bits_rx_status.priority;    /* 802.1p priority */
1346 +#endif
1347 +            vid = rx_desc->flag_status.bits_rx_status.vlan_id;          /* 802.1q vlan id */
1348 +            if (vid == 0)
1349 +            {
1350 +                vid = 1;    /* default vlan */
1351 +            }
1352 +               desc_count = rx_desc->frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */
1353 +
1354 +               if (rx_desc->frame_ctrl.bits_rx.frame_state == 0x000) /* good frame */
1355 +               {
1356 +                       tp->stats.rx_bytes += pkt_size;
1357 +                       tp->stats.rx_packets++;
1358 +                       good_frame = 1;
1359 +               }
1360 +               else
1361 +               {
1362 +                       tp->stats.rx_errors++;
1363 +                       good_frame = 0;
1364 +                       printk("RX status: 0x%x\n",rx_desc->frame_ctrl.bits_rx.frame_state);
1365 +               }
1366 +       }
1367 +       else
1368 +       {
1369 +           work_done = 1;
1370 +           break;  /* Rx process is completed */
1371 +       }
1372 +
1373 +        if (good_frame == 1)
1374 +        {
1375 +            /* get rx skb buffer index */
1376 +            index = ((unsigned int)tp->rx_cur_desc - rx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1377 +            if (rx_skb[dev_index][index])
1378 +            {
1379 +                skb_reserve (rx_skb[dev_index][index], 2);     /* 16 byte align the IP fields. */
1380 +                rx_skb[dev_index][index]->dev = dev;
1381 +                rx_skb[dev_index][index]->ip_summed = CHECKSUM_UNNECESSARY;
1382 +                           skb_put(rx_skb[dev_index][index],pkt_size);
1383 +                           rx_skb[dev_index][index]->protocol = eth_type_trans(rx_skb[dev_index][index],dev); /* set skb protocol */
1384 +                           netif_rx(rx_skb[dev_index][index]);  /* socket rx */
1385 +                           dev->last_rx = jiffies;
1386 +
1387 +                           /* allocate rx skb buffer */
1388 +                if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
1389 +                {
1390 +                    printk("%s::skb buffer allocation fail !\n",__func__);
1391 +                }
1392 +                rx_skb[dev_index][index] = skb;
1393 +                tp->rx_cur_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
1394 +            }
1395 +            else
1396 +            {
1397 +                printk("%s::rx skb index error !\n",__func__);
1398 +            }
1399 +        }
1400 +
1401 +           tp->rx_cur_desc->frame_ctrl.bits_rx.own = DMA; /* release rx descriptor to DMA */
1402 +        /* point to next rx descriptor */
1403 +        tp->rx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->rx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+rx_desc_virtual_base[dev_index]);
1404 +
1405 +        /* release buffer to Remaining Buffer Number Register */
1406 +        if (flow_control_enable[dev_index] ==1)
1407 +        {
1408 +//            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_BNCR,desc_count,0x0000ffff);
1409 +            writel(desc_count,(unsigned int *)(gmac_base_addr[dev_index] + GMAC_BNCR));
1410 +        }
1411 +
1412 +               if (work++ >= quota )
1413 +               {
1414 +                       break;
1415 +               }
1416 +    }
1417 +
1418 +    /* if RX DMA process is stoped , restart it */
1419 +       rxdma_busy.bits.rd_first_des_ptr = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC);
1420 +       if (rxdma_busy.bits.rd_busy == 0)
1421 +       {
1422 +           rxdma_ctrl.bits32 = 0;
1423 +       rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1424 +           rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1425 +           rxdma_ctrl_mask.bits32 = 0;
1426 +       rxdma_ctrl_mask.bits.rd_start = 1;
1427 +           rxdma_ctrl_mask.bits.rd_continue = 1;
1428 +           gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1429 +    }
1430 +
1431 +       dev->quota -= work;
1432 +       *budget -= work;
1433 +       if (work_done==1)
1434 +       {
1435 +           /* Receive descriptor is empty now */
1436 +        netif_rx_complete(dev);
1437 +        /* enable receive interrupt */
1438 +        gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,0x0007c000,0x0007c000);   /* enable rx interrupt */
1439 +        return 0;
1440 +    }
1441 +    else
1442 +    {
1443 +        return -1;
1444 +    }
1445 +}
1446 +
1447 +#endif
1448 +
1449 +static void gmac_rx_packet(struct net_device *dev)
1450 +{
1451 +       struct gmac_private *tp = dev->priv;
1452 +       struct sk_buff          *skb;
1453 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1454 +       GMAC_RXDMA_FIRST_DESC_T rxdma_busy;
1455 +    GMAC_DESCRIPTOR_T   *rx_desc;
1456 +       unsigned int            pkt_size;
1457 +       unsigned int        desc_count;
1458 +    unsigned int        vid;
1459 +//    unsigned int        priority;
1460 +       unsigned int        own;
1461 +       unsigned int        good_frame = 0;
1462 +       unsigned int        i,index;
1463 +       unsigned int        dev_index;
1464 +
1465 +    dev_index = gmac_select_interface(dev);
1466 +
1467 +       for (i=0;i<256;i++)
1468 +       {
1469 +        own = tp->rx_cur_desc->frame_ctrl.bits32 >> 31;
1470 +        if (own == CPU) /* check owner bit */
1471 +        {
1472 +               rx_desc = tp->rx_cur_desc;
1473 +#if (GMAC_DEBUG==1)
1474 +               /* check error interrupt */
1475 +               if ( (rx_desc->frame_ctrl.bits_rx.derr==1)||(rx_desc->frame_ctrl.bits_rx.perr==1) )
1476 +               {
1477 +               printk("%s::Rx Descriptor Processing Error !!!\n",__func__);
1478 +           }
1479 +#endif
1480 +           /* get frame information from the first descriptor of the frame */
1481 +               pkt_size = rx_desc->flag_status.bits_rx_status.frame_count - 4;  /*total byte count in a frame*/
1482 +#if (GMAC_DEBUG==1)
1483 +            priority = rx_desc->flag_status.bits_rx_status.priority;    /* 802.1p priority */
1484 +#endif
1485 +            vid = rx_desc->flag_status.bits_rx_status.vlan_id;          /* 802.1q vlan id */
1486 +            if (vid == 0)
1487 +            {
1488 +                vid = 1;    /* default vlan */
1489 +            }
1490 +               desc_count = rx_desc->frame_ctrl.bits_rx.desc_count; /* get descriptor count per frame */
1491 +
1492 +               if (rx_desc->frame_ctrl.bits_rx.frame_state == 0x000) /* good frame */
1493 +               {
1494 +                       tp->stats.rx_bytes += pkt_size;
1495 +                       tp->stats.rx_packets++;
1496 +                       good_frame = 1;
1497 +               }
1498 +               else
1499 +               {
1500 +                       tp->stats.rx_errors++;
1501 +                       good_frame = 0;
1502 +                       printk("RX status: 0x%x\n",rx_desc->frame_ctrl.bits_rx.frame_state);
1503 +               }
1504 +       }
1505 +       else
1506 +       {
1507 +           break;  /* Rx process is completed */
1508 +       }
1509 +
1510 +        if (good_frame == 1)
1511 +        {
1512 +            /* get rx skb buffer index */
1513 +            index = ((unsigned int)tp->rx_cur_desc - rx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1514 +            if (rx_skb[dev_index][index])
1515 +            {
1516 +                skb_reserve (rx_skb[dev_index][index], 2);     /* 16 byte align the IP fields. */
1517 +                rx_skb[dev_index][index]->dev = dev;
1518 +                rx_skb[dev_index][index]->ip_summed = CHECKSUM_UNNECESSARY;
1519 +                           skb_put(rx_skb[dev_index][index],pkt_size);
1520 +                           rx_skb[dev_index][index]->protocol = eth_type_trans(rx_skb[dev_index][index],dev); /* set skb protocol */
1521 +                           netif_rx(rx_skb[dev_index][index]);  /* socket rx */
1522 +                           dev->last_rx = jiffies;
1523 +
1524 +                           /* allocate rx skb buffer */
1525 +                if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
1526 +                {
1527 +                    printk("%s::skb buffer allocation fail !\n",__func__);
1528 +                }
1529 +                rx_skb[dev_index][index] = skb;
1530 +                tp->rx_cur_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
1531 +            }
1532 +            else
1533 +            {
1534 +                printk("%s::rx skb index error !\n",__func__);
1535 +            }
1536 +        }
1537 +
1538 +           tp->rx_cur_desc->frame_ctrl.bits_rx.own = DMA; /* release rx descriptor to DMA */
1539 +        /* point to next rx descriptor */
1540 +        tp->rx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->rx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+rx_desc_virtual_base[dev_index]);
1541 +
1542 +        /* release buffer to Remaining Buffer Number Register */
1543 +        if (flow_control_enable[dev_index] ==1)
1544 +        {
1545 +            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_BNCR,desc_count,0x0000ffff);
1546 +        }
1547 +    }
1548 +
1549 +    /* if RX DMA process is stoped , restart it */
1550 +       rxdma_busy.bits.rd_first_des_ptr = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC);
1551 +       if (rxdma_busy.bits.rd_busy == 0)
1552 +       {
1553 +           rxdma_ctrl.bits32 = 0;
1554 +       rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1555 +           rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1556 +           rxdma_ctrl_mask.bits32 = 0;
1557 +       rxdma_ctrl_mask.bits.rd_start = 1;
1558 +           rxdma_ctrl_mask.bits.rd_continue = 1;
1559 +           gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1560 +    }
1561 +}
1562 +
1563 +#ifdef CONFIG_SL2312_MPAGE
1564 +static inline void free_tx_buf(int dev_index, int desc_index)
1565 +{
1566 +       if (tx_skb[dev_index][desc_index].freeable &&
1567 +           tx_skb[dev_index][desc_index].skb) {
1568 +               struct sk_buff* skb = tx_skb[dev_index][desc_index].skb;
1569 +               //printk("free_skb %x, len %d\n", skb, skb->len);
1570 +#ifdef CONFIG_TXINT_DISABLE
1571 +               dev_kfree_skb(skb);
1572 +#else
1573 +               dev_kfree_skb_irq(skb);
1574 +#endif
1575 +               tx_skb[dev_index][desc_index].skb = 0;
1576 +       }
1577 +}
1578 +
1579 +#ifdef CONFIG_TXINT_DISABLE
1580 +static void gmac_tx_packet_complete(struct net_device *dev)
1581 +{
1582 +       struct gmac_private     *tp = dev->priv;
1583 +    GMAC_DESCRIPTOR_T      *tx_hw_complete_desc, *next_desc;
1584 +    unsigned int desc_cnt=0;
1585 +    unsigned int i,index,dev_index;
1586 +    unsigned int tx_current_descriptor = 0;
1587 +       // int own_dma = 0;
1588 +
1589 +    dev_index = gmac_select_interface(dev);
1590 +
1591 +       index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1592 +       if (tx_skb[dev_index][index].desc_in_use && tp->tx_finished_desc->frame_ctrl.bits_tx_in.own == CPU) {
1593 +               free_tx_buf(dev_index, index);
1594 +               tx_skb[dev_index][index].desc_in_use = 0;
1595 +       }
1596 +       next_desc = (GMAC_DESCRIPTOR_T*)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
1597 +
1598 +       for (;;) {
1599 +               tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0)+ tx_desc_virtual_base[dev_index]);
1600 +               if (next_desc == tx_hw_complete_desc)
1601 +                       break;
1602 +               if (next_desc->frame_ctrl.bits_tx_in.own == CPU) {
1603 +                       if (next_desc->frame_ctrl.bits_tx_in.success_tx == 1) {
1604 +                               tp->stats.tx_bytes += next_desc->flag_status.bits_tx_flag.frame_count;
1605 +                               tp->stats.tx_packets ++;
1606 +                       } else {
1607 +                               tp->stats.tx_errors++;
1608 +                       }
1609 +                       desc_cnt = next_desc->frame_ctrl.bits_tx_in.desc_count;
1610 +                       for (i=1; i<desc_cnt; i++) {
1611 +                               /* get tx skb buffer index */
1612 +                               index = ((unsigned int)next_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1613 +                               next_desc->frame_ctrl.bits_tx_in.own = CPU;
1614 +                               free_tx_buf(dev_index, index);
1615 +                               tx_skb[dev_index][index].desc_in_use = 0;
1616 +                               tp->tx_desc_tail[dev_index] = (tp->tx_desc_tail[dev_index] +1) & (TX_DESC_NUM-1);
1617 +                               /* release Tx descriptor to CPU */
1618 +                               next_desc = (GMAC_DESCRIPTOR_T *)((next_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1619 +                       }
1620 +                       /* get tx skb buffer index */
1621 +                       index = ((unsigned int)next_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1622 +                       /* free skb buffer */
1623 +                       next_desc->frame_ctrl.bits_tx_in.own = CPU;
1624 +                       free_tx_buf(dev_index, index);
1625 +                       tx_skb[dev_index][index].desc_in_use = 0;
1626 +                       tp->tx_desc_tail[dev_index] = (tp->tx_desc_tail[dev_index] +1) & (TX_DESC_NUM-1);
1627 +                       tp->tx_finished_desc = next_desc;
1628 +//                     printk("finish tx_desc index %d\n", index);
1629 +                       next_desc = (GMAC_DESCRIPTOR_T *)((next_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1630 +               }
1631 +               else
1632 +                       break;
1633 +       }
1634 +       if (netif_queue_stopped(dev))
1635 +       {
1636 +               netif_wake_queue(dev);
1637 +       }
1638 +
1639 +}
1640 +#else
1641 +static void gmac_tx_packet_complete(struct net_device *dev)
1642 +{
1643 +       struct gmac_private     *tp = dev->priv;
1644 +       GMAC_DESCRIPTOR_T           *tx_hw_complete_desc;
1645 +       unsigned int desc_cnt=0;
1646 +       unsigned int i,index,dev_index;
1647 +       unsigned int tx_current_descriptor = 0;
1648 +       // int own_dma = 0;
1649 +
1650 +       dev_index = gmac_select_interface(dev);
1651 +
1652 +       index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1653 +
1654 +       /* check tx status and accumulate tx statistics */
1655 +       for (;;)
1656 +       {
1657 +
1658 +        for (i=0;i<1000;i++)
1659 +        {
1660 +            tx_current_descriptor = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC);
1661 +            if ( ((tx_current_descriptor & 0x00000003)==0x00000003) ||  /* only one descriptor */
1662 +                 ((tx_current_descriptor & 0x00000003)==0x00000001) )   /* the last descriptor */
1663 +            {
1664 +                break;
1665 +            }
1666 +            udelay(1);
1667 +        }
1668 +        if (i==1000)
1669 +        {
1670 +//            gmac_dump_register(dev);
1671 +//            printk("%s: tx current descriptor = %x \n",__func__,tx_current_descriptor);
1672 +//            printk_all(dev_index, tp);
1673 +            continue;
1674 +        }
1675 +
1676 +           /* get tx H/W completed descriptor virtual address */
1677 +       tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((tx_current_descriptor & 0xfffffff0)+ tx_desc_virtual_base[dev_index]);
1678 +//     tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0)+ tx_desc_virtual_base[dev_index]);
1679 +           if (tp->tx_finished_desc == tx_hw_complete_desc ) // ||
1680 +                   //tx_skb[dev_index][index].desc_in_use )   /* complete tx processing */
1681 +               {
1682 +                       break;
1683 +               }
1684 +
1685 +        for (;;)
1686 +        {
1687 +               if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.own == CPU)
1688 +               {
1689 +    #if (GMAC_DEBUG==1)
1690 +                       if ( (tp->tx_finished_desc->frame_ctrl.bits_tx_in.derr) ||
1691 +                          (tp->tx_finished_desc->frame_ctrl.bits_tx_in.perr) )
1692 +                       {
1693 +                               printk("%s::Descriptor Processing Error !!!\n",__func__);
1694 +                       }
1695 +    #endif
1696 +                       if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.success_tx == 1)
1697 +                       {
1698 +                               tp->stats.tx_bytes += tp->tx_finished_desc->flag_status.bits_tx_flag.frame_count;
1699 +                               tp->stats.tx_packets ++;
1700 +                       }
1701 +                       else
1702 +                       {
1703 +                               tp->stats.tx_errors++;
1704 +                       }
1705 +                       desc_cnt = tp->tx_finished_desc->frame_ctrl.bits_tx_in.desc_count;
1706 +                       for (i=1; i<desc_cnt; i++)  /* multi-descriptor in one packet */
1707 +                       {
1708 +                               /* get tx skb buffer index */
1709 +                               index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1710 +                               tp->tx_finished_desc->frame_ctrl.bits_tx_in.own = CPU;
1711 +                               free_tx_buf(dev_index, index);
1712 +                               tx_skb[dev_index][index].desc_in_use = 0;
1713 +                               /* release Tx descriptor to CPU */
1714 +                               tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1715 +                       }
1716 +                       /* get tx skb buffer index */
1717 +                       index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1718 +                       /* free skb buffer */
1719 +                       tp->tx_finished_desc->frame_ctrl.bits_tx_in.own = CPU;
1720 +                       free_tx_buf(dev_index, index);
1721 +                       tx_skb[dev_index][index].desc_in_use = 0;
1722 +                       tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1723 +
1724 +                   if (tp->tx_finished_desc == tx_hw_complete_desc )
1725 +                       {
1726 +                               break;
1727 +                       }
1728 +            }
1729 +               else
1730 +               {
1731 +                       break;
1732 +                       }
1733 +               }
1734 +       }
1735 +
1736 +       if (netif_queue_stopped(dev))
1737 +       {
1738 +               netif_wake_queue(dev);
1739 +       }
1740 +
1741 +}
1742 +#endif
1743 +#else
1744 +
1745 +static void gmac_tx_packet_complete(struct net_device *dev)
1746 +{
1747 +       struct gmac_private     *tp = dev->priv;
1748 +    GMAC_DESCRIPTOR_T      *tx_hw_complete_desc;
1749 +    unsigned int desc_cnt=0;
1750 +    unsigned int i,index,dev_index;
1751 +
1752 +    dev_index = gmac_select_interface(dev);
1753 +
1754 +       /* get tx H/W completed descriptor virtual address */
1755 +       tx_hw_complete_desc = (GMAC_DESCRIPTOR_T *)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0)+ tx_desc_virtual_base[dev_index]);
1756 +       /* check tx status and accumulate tx statistics */
1757 +    for (;;)
1758 +    {
1759 +        if (tp->tx_finished_desc == tx_hw_complete_desc)   /* complete tx processing */
1760 +        {
1761 +            break;
1762 +        }
1763 +       if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.own == CPU)
1764 +       {
1765 +#if (GMAC_DEBUG==1)
1766 +           if ( (tp->tx_finished_desc->frame_ctrl.bits_tx_in.derr) ||
1767 +                (tp->tx_finished_desc->frame_ctrl.bits_tx_in.perr) )
1768 +           {
1769 +               printk("%s::Descriptor Processing Error !!!\n",__func__);
1770 +           }
1771 +#endif
1772 +            if (tp->tx_finished_desc->frame_ctrl.bits_tx_in.success_tx == 1)
1773 +            {
1774 +                tp->stats.tx_bytes += tp->tx_finished_desc->flag_status.bits_tx_flag.frame_count;
1775 +                tp->stats.tx_packets ++;
1776 +            }
1777 +            else
1778 +            {
1779 +                tp->stats.tx_errors++;
1780 +            }
1781 +            desc_cnt = tp->tx_finished_desc->frame_ctrl.bits_tx_in.desc_count;
1782 +               for (i=1; i<desc_cnt; i++)  /* multi-descriptor in one packet */
1783 +               {
1784 +                /* get tx skb buffer index */
1785 +                index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1786 +                /* free skb buffer */
1787 +                if (tx_skb[dev_index][index])
1788 +                {
1789 +                           dev_kfree_skb_irq(tx_skb[dev_index][index]);
1790 +                       }
1791 +                   /* release Tx descriptor to CPU */
1792 +                tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1793 +                tp->tx_finished_desc->frame_ctrl.bits_tx_in.own = CPU;
1794 +               }
1795 +            /* get tx skb buffer index */
1796 +            index = ((unsigned int)tp->tx_finished_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
1797 +            /* free skb buffer */
1798 +            if (tx_skb[dev_index][index])
1799 +            {
1800 +                   dev_kfree_skb_irq(tx_skb[dev_index][index]);
1801 +               }
1802 +            tp->tx_finished_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_finished_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
1803 +       }
1804 +    }
1805 +
1806 +       if (netif_queue_stopped(dev))
1807 +       {
1808 +           netif_wake_queue(dev);
1809 +       }
1810 +
1811 +}
1812 +
1813 +
1814 +#endif
1815 +
1816 +#if 0
1817 +static void gmac_weird_interrupt(struct net_device *dev)
1818 +{
1819 +    gmac_dump_register(dev);
1820 +}
1821 +#endif
1822 +
1823 +/* The interrupt handler does all of the Rx thread work and cleans up
1824 +   after the Tx thread. */
1825 +static irqreturn_t gmac_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
1826 +{
1827 +       struct net_device       *dev = (struct net_device *)dev_instance;
1828 +       GMAC_RXDMA_FIRST_DESC_T rxdma_busy;
1829 +//     GMAC_TXDMA_FIRST_DESC_T txdma_busy;
1830 +//    GMAC_TXDMA_CTRL_T       txdma_ctrl,txdma_ctrl_mask;
1831 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1832 +       GMAC_DMA_STATUS_T           status;
1833 +    unsigned int            i,dev_index;
1834 +       int                     handled = 0;
1835 +
1836 +    dev_index = gmac_select_interface(dev);
1837 +
1838 +       handled = 1;
1839 +
1840 +#ifdef CONFIG_SL_NAPI
1841 +       disable_irq(gmac_irq[dev_index]);   /* disable GMAC interrupt */
1842 +
1843 +    status.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS);         /* read DMA status */
1844 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS,status.bits32,status.bits32);    /* clear DMA status */
1845 +
1846 +    if (status.bits.rx_overrun == 1)
1847 +    {
1848 +               printk("%s::RX Overrun !!!%d\n",__func__,gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RBNR));
1849 +         gmac_dump_register(dev);
1850 +        /* if RX DMA process is stoped , restart it */
1851 +        rxdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC) ;
1852 +        if (rxdma_busy.bits.rd_busy == 0)
1853 +        {
1854 +            /* restart Rx DMA process */
1855 +               rxdma_ctrl.bits32 = 0;
1856 +               rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1857 +            rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1858 +            rxdma_ctrl_mask.bits32 = 0;
1859 +               rxdma_ctrl_mask.bits.rd_start = 1;
1860 +            rxdma_ctrl_mask.bits.rd_continue = 1;
1861 +            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1862 +        }
1863 +    }
1864 +
1865 +    /* process rx packet */
1866 +       if (netif_running(dev) && ((status.bits.rs_eofi==1)||(status.bits.rs_finish==1)))
1867 +       {
1868 +        if (likely(netif_rx_schedule_prep(dev)))
1869 +        {
1870 +            gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,0,0x0007c000);   /* disable rx interrupt */
1871 +            __netif_rx_schedule(dev);
1872 +        }
1873 +    }
1874 +#ifndef CONFIG_TXINT_DISABLE
1875 +    /* process tx packet */
1876 +       if (netif_running(dev) && ((status.bits.ts_eofi==1)||(status.bits.ts_finish==1)))
1877 +       {
1878 +               gmac_tx_packet_complete(dev);
1879 +       }
1880 +#endif
1881 +
1882 +       enable_irq(gmac_irq[dev_index]);    /* enable GMAC interrupt */
1883 +    return IRQ_RETVAL(handled);
1884 +#endif
1885 +
1886 +   /* disable GMAC interrupt */
1887 +       disable_irq(gmac_irq[dev_index]);
1888 +    for (i=0;i<MAX_ISR_WORK;i++)
1889 +    {
1890 +        /* read DMA status */
1891 +           status.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS);
1892 +int_status = status.bits32;
1893 +           /* clear DMA status */
1894 +        gmac_write_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS,status.bits32,status.bits32);
1895 +
1896 +        if ((status.bits32 & 0xffffc000)==0)
1897 +        {
1898 +            break;
1899 +        }
1900 +
1901 +           if (status.bits.rx_overrun == 1)
1902 +           {
1903 +                       printk("%s::RX Overrun !!!%d\n",__func__,gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RBNR));
1904 +               gmac_dump_register(dev);
1905 +            /* if RX DMA process is stoped , restart it */
1906 +               rxdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_FIRST_DESC) ;
1907 +               if (rxdma_busy.bits.rd_busy == 0)
1908 +               {
1909 +                   /* restart Rx DMA process */
1910 +               rxdma_ctrl.bits32 = 0;
1911 +               rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
1912 +                   rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
1913 +                   rxdma_ctrl_mask.bits32 = 0;
1914 +               rxdma_ctrl_mask.bits.rd_start = 1;
1915 +                   rxdma_ctrl_mask.bits.rd_continue = 1;
1916 +                   gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
1917 +            }
1918 +           }
1919 +
1920 +        /* receive rx interrupt */
1921 +       if (netif_running(dev) && ((status.bits.rs_eofi==1)||(status.bits.rs_finish==1)))
1922 +       {
1923 +               gmac_rx_packet(dev);
1924 +//             gmac_tx_packet_complete(dev);
1925 +        }
1926 +
1927 +        /* receive tx interrupt */
1928 +       // if (netif_running(dev) && (status.bits.ts_finish==1))
1929 +#ifndef CONFIG_TXINT_DISABLE
1930 +       if (netif_running(dev) && ((status.bits.ts_eofi==1)||
1931 +                          (status.bits.ts_finish==1)))
1932 +       {
1933 +               gmac_tx_packet_complete(dev);
1934 +       }
1935 +#endif
1936 +       /* check uncommon events */
1937 +/*        if ((status.bits32 & 0x632fc000)!=0)
1938 +        {
1939 +            printk("%s::DMA Status = %08x \n",__func__,status.bits32);
1940 +            gmac_weird_interrupt(dev);
1941 +        }
1942 +*/
1943 +       }
1944 +
1945 +    /* enable GMAC interrupt */
1946 +       enable_irq(gmac_irq[dev_index]);
1947 +       //printk("gmac_interrupt complete!\n\n");
1948 +       return IRQ_RETVAL(handled);
1949 +}
1950 +
1951 +static void gmac_hw_start(struct net_device *dev)
1952 +{
1953 +       struct gmac_private     *tp = dev->priv;
1954 +       GMAC_TXDMA_CURR_DESC_T  tx_desc;
1955 +       GMAC_RXDMA_CURR_DESC_T  rx_desc;
1956 +    GMAC_TXDMA_CTRL_T       txdma_ctrl,txdma_ctrl_mask;
1957 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
1958 +       GMAC_DMA_STATUS_T       dma_status,dma_status_mask;
1959 +       int                                             dev_index;
1960 +
1961 +    dev_index = gmac_select_interface(dev);
1962 +
1963 +       /* program TxDMA Current Descriptor Address register for first descriptor */
1964 +       tx_desc.bits32 = (unsigned int)(tp->tx_desc_dma);
1965 +       tx_desc.bits.eofie = 1;
1966 +       tx_desc.bits.sof_eof = 0x03;
1967 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC,tx_desc.bits32,0xffffffff);
1968 +       gmac_write_reg(gmac_base_addr[dev_index] + 0xff2c,tx_desc.bits32,0xffffffff);   /* tx next descriptor address */
1969 +
1970 +       /* program RxDMA Current Descriptor Address register for first descriptor */
1971 +       rx_desc.bits32 = (unsigned int)(tp->rx_desc_dma);
1972 +       rx_desc.bits.eofie = 1;
1973 +       rx_desc.bits.sof_eof = 0x03;
1974 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CURR_DESC,rx_desc.bits32,0xffffffff);
1975 +       gmac_write_reg(gmac_base_addr[dev_index] + 0xff3c,rx_desc.bits32,0xffffffff);   /* rx next descriptor address */
1976 +
1977 +       /* enable GMAC interrupt & disable loopback */
1978 +       dma_status.bits32 = 0;
1979 +       dma_status.bits.loop_back = 0;  /* disable DMA loop-back mode */
1980 +//     dma_status.bits.m_tx_fail = 1;
1981 +       dma_status.bits.m_cnt_full = 1;
1982 +       dma_status.bits.m_rx_pause_on = 1;
1983 +       dma_status.bits.m_tx_pause_on = 1;
1984 +       dma_status.bits.m_rx_pause_off = 1;
1985 +       dma_status.bits.m_tx_pause_off = 1;
1986 +       dma_status.bits.m_rx_overrun = 1;
1987 +       dma_status.bits.m_link_change = 1;
1988 +       dma_status_mask.bits32 = 0;
1989 +       dma_status_mask.bits.loop_back = 1;
1990 +//     dma_status_mask.bits.m_tx_fail = 1;
1991 +       dma_status_mask.bits.m_cnt_full = 1;
1992 +       dma_status_mask.bits.m_rx_pause_on = 1;
1993 +       dma_status_mask.bits.m_tx_pause_on = 1;
1994 +       dma_status_mask.bits.m_rx_pause_off = 1;
1995 +       dma_status_mask.bits.m_tx_pause_off = 1;
1996 +       dma_status_mask.bits.m_rx_overrun = 1;
1997 +       dma_status_mask.bits.m_link_change = 1;
1998 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_DMA_STATUS,dma_status.bits32,dma_status_mask.bits32);
1999 +
2000 +    /* program tx dma control register */
2001 +       txdma_ctrl.bits32 = 0;
2002 +       txdma_ctrl.bits.td_start = 0;    /* start TX DMA transfer */
2003 +       txdma_ctrl.bits.td_continue = 0; /* continue Tx DMA operation */
2004 +       txdma_ctrl.bits.td_chain_mode = 1;  /* chain mode */
2005 +       txdma_ctrl.bits.td_prot = 0;
2006 +       txdma_ctrl.bits.td_burst_size = 2;  /* DMA burst size for every AHB request */
2007 +       txdma_ctrl.bits.td_bus = 2;         /* peripheral bus width */
2008 +       txdma_ctrl.bits.td_endian = 0;      /* little endian */
2009 +#ifdef CONFIG_TXINT_DISABLE
2010 +       txdma_ctrl.bits.td_finish_en = 0;   /* DMA finish event interrupt disable */
2011 +#else
2012 +       txdma_ctrl.bits.td_finish_en = 1;   /* DMA finish event interrupt enable */
2013 +#endif
2014 +       txdma_ctrl.bits.td_fail_en = 1;     /* DMA fail interrupt enable */
2015 +       txdma_ctrl.bits.td_perr_en = 1;     /* protocol failure interrupt enable */
2016 +       txdma_ctrl.bits.td_eod_en = 0;      /* disable Tx End of Descriptor Interrupt */
2017 +       //txdma_ctrl.bits.td_eod_en = 0;      /* disable Tx End of Descriptor Interrupt */
2018 +#ifdef CONFIG_TXINT_DISABLE
2019 +       txdma_ctrl.bits.td_eof_en = 0;      /* end of frame interrupt disable */
2020 +#else
2021 +       txdma_ctrl.bits.td_eof_en = 1;      /* end of frame interrupt enable */
2022 +#endif
2023 +       txdma_ctrl_mask.bits32 = 0;
2024 +       txdma_ctrl_mask.bits.td_start = 1;
2025 +       txdma_ctrl_mask.bits.td_continue = 1;
2026 +       txdma_ctrl_mask.bits.td_chain_mode = 1;
2027 +       txdma_ctrl_mask.bits.td_prot = 15;
2028 +       txdma_ctrl_mask.bits.td_burst_size = 3;
2029 +       txdma_ctrl_mask.bits.td_bus = 3;
2030 +       txdma_ctrl_mask.bits.td_endian = 1;
2031 +       txdma_ctrl_mask.bits.td_finish_en = 1;
2032 +       txdma_ctrl_mask.bits.td_fail_en = 1;
2033 +       txdma_ctrl_mask.bits.td_perr_en = 1;
2034 +       txdma_ctrl_mask.bits.td_eod_en = 1;
2035 +       //txdma_ctrl_mask.bits.td_eod_en = 1;
2036 +       txdma_ctrl_mask.bits.td_eof_en = 1;
2037 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,txdma_ctrl.bits32,txdma_ctrl_mask.bits32);
2038 +
2039 +    /* program rx dma control register */
2040 +       rxdma_ctrl.bits32 = 0;
2041 +       rxdma_ctrl.bits.rd_start = 1;    /* start RX DMA transfer */
2042 +       rxdma_ctrl.bits.rd_continue = 1; /* continue RX DMA operation */
2043 +       rxdma_ctrl.bits.rd_chain_mode = 1;  /* chain mode */
2044 +       rxdma_ctrl.bits.rd_prot = 0;
2045 +       rxdma_ctrl.bits.rd_burst_size = 2;  /* DMA burst size for every AHB request */
2046 +       rxdma_ctrl.bits.rd_bus = 2;         /* peripheral bus width */
2047 +       rxdma_ctrl.bits.rd_endian = 0;      /* little endian */
2048 +       rxdma_ctrl.bits.rd_finish_en = 1;   /* DMA finish event interrupt enable */
2049 +       rxdma_ctrl.bits.rd_fail_en = 1;     /* DMA fail interrupt enable */
2050 +       rxdma_ctrl.bits.rd_perr_en = 1;     /* protocol failure interrupt enable */
2051 +       rxdma_ctrl.bits.rd_eod_en = 0;      /* disable Rx End of Descriptor Interrupt */
2052 +       rxdma_ctrl.bits.rd_eof_en = 1;      /* end of frame interrupt enable */
2053 +       rxdma_ctrl_mask.bits32 = 0;
2054 +       rxdma_ctrl_mask.bits.rd_start = 1;
2055 +       rxdma_ctrl_mask.bits.rd_continue = 1;
2056 +       rxdma_ctrl_mask.bits.rd_chain_mode = 1;
2057 +       rxdma_ctrl_mask.bits.rd_prot = 15;
2058 +       rxdma_ctrl_mask.bits.rd_burst_size = 3;
2059 +       rxdma_ctrl_mask.bits.rd_bus = 3;
2060 +       rxdma_ctrl_mask.bits.rd_endian = 1;
2061 +       rxdma_ctrl_mask.bits.rd_finish_en = 1;
2062 +       rxdma_ctrl_mask.bits.rd_fail_en = 1;
2063 +       rxdma_ctrl_mask.bits.rd_perr_en = 1;
2064 +       rxdma_ctrl_mask.bits.rd_eod_en = 1;
2065 +       rxdma_ctrl_mask.bits.rd_eof_en = 1;
2066 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
2067 +    return;
2068 +}
2069 +
2070 +static void gmac_hw_stop(struct net_device *dev)
2071 +{
2072 +    GMAC_TXDMA_CTRL_T       txdma_ctrl,txdma_ctrl_mask;
2073 +    GMAC_RXDMA_CTRL_T       rxdma_ctrl,rxdma_ctrl_mask;
2074 +       int                                     dev_index;
2075 +
2076 +    dev_index = gmac_select_interface(dev);
2077 +
2078 +    /* program tx dma control register */
2079 +       txdma_ctrl.bits32 = 0;
2080 +       txdma_ctrl.bits.td_start = 0;
2081 +       txdma_ctrl.bits.td_continue = 0;
2082 +       txdma_ctrl_mask.bits32 = 0;
2083 +       txdma_ctrl_mask.bits.td_start = 1;
2084 +       txdma_ctrl_mask.bits.td_continue = 1;
2085 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,txdma_ctrl.bits32,txdma_ctrl_mask.bits32);
2086 +    /* program rx dma control register */
2087 +       rxdma_ctrl.bits32 = 0;
2088 +       rxdma_ctrl.bits.rd_start = 0;    /* stop RX DMA transfer */
2089 +       rxdma_ctrl.bits.rd_continue = 0; /* stop continue RX DMA operation */
2090 +       rxdma_ctrl_mask.bits32 = 0;
2091 +       rxdma_ctrl_mask.bits.rd_start = 1;
2092 +       rxdma_ctrl_mask.bits.rd_continue = 1;
2093 +       gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RXDMA_CTRL,rxdma_ctrl.bits32,rxdma_ctrl_mask.bits32);
2094 +}
2095 +
2096 +static int gmac_init_desc_buf(struct net_device *dev)
2097 +{
2098 +       struct gmac_private *tp = dev->priv;
2099 +       struct sk_buff          *skb;
2100 +       dma_addr_t          tx_first_desc_dma=0;
2101 +       dma_addr_t          rx_first_desc_dma=0;
2102 +       dma_addr_t          rx_first_buf_dma=0;
2103 +       unsigned int        i,index;
2104 +
2105 +    printk("Descriptor buffer init......\n");
2106 +
2107 +    /* get device index number */
2108 +    index = gmac_get_dev_index(dev);
2109 +#ifdef CONFIG_SL2312_MPAGE
2110 +       for (i=0; i<TX_DESC_NUM; i++) {
2111 +               tx_skb[index][i].freeable = 0;
2112 +               tx_skb[index][i].skb = 0;
2113 +               tx_skb[index][i].desc_in_use = 0;
2114 +               tx_skb[index][i].end_seq = 0;
2115 +       }
2116 +#else
2117 +    for (i=0;i<TX_DESC_NUM;i++)
2118 +    {
2119 +        tx_skb[index][i] = NULL;
2120 +    }
2121 +#endif
2122 +    for (i=0;i<RX_DESC_NUM;i++)
2123 +    {
2124 +        rx_skb[index][i] = NULL;
2125 +    }
2126 +
2127 +       /* allocates TX/RX descriptors */
2128 +       tp->tx_desc = DMA_MALLOC(TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(dma_addr_t *)&tp->tx_desc_dma);
2129 +    tx_desc_virtual_base[index] = (unsigned int)tp->tx_desc - (unsigned int)tp->tx_desc_dma;
2130 +    memset(tp->tx_desc,0x00,TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T));
2131 +       tp->rx_desc = DMA_MALLOC(RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(dma_addr_t *)&tp->rx_desc_dma);
2132 +    rx_desc_virtual_base[index] = (unsigned int)tp->rx_desc - (unsigned int)tp->rx_desc_dma;
2133 +    memset(tp->rx_desc,0x00,RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T));
2134 +    tx_desc_start_adr[index] = (unsigned int)tp->tx_desc;   /* for tx skb index calculation */
2135 +    rx_desc_start_adr[index] = (unsigned int)tp->rx_desc;   /* for rx skb index calculation */
2136 +    printk("tx_desc = %08x\n",(unsigned int)tp->tx_desc);
2137 +    printk("rx_desc = %08x\n",(unsigned int)tp->rx_desc);
2138 +       printk("tx_desc_dma = %08x\n",tp->tx_desc_dma);
2139 +       printk("rx_desc_dma = %08x\n",tp->rx_desc_dma);
2140 +
2141 +       if (tp->tx_desc==0x00 || tp->rx_desc==0x00)
2142 +       {
2143 +               free_irq(dev->irq, dev);
2144 +
2145 +               if (tp->tx_desc)
2146 +                       DMA_MFREE(tp->tx_desc, TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),tp->tx_desc_dma);
2147 +               if (tp->rx_desc)
2148 +                       DMA_MFREE(tp->rx_desc, RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),tp->rx_desc_dma);
2149 +               return -ENOMEM;
2150 +       }
2151 +
2152 +       /* TX descriptors initial */
2153 +       tp->tx_cur_desc = tp->tx_desc;  /* virtual address */
2154 +       tp->tx_finished_desc = tp->tx_desc; /* virtual address */
2155 +       tx_first_desc_dma = tp->tx_desc_dma; /* physical address */
2156 +       for (i = 1; i < TX_DESC_NUM; i++)
2157 +       {
2158 +               tp->tx_desc->frame_ctrl.bits_tx_out.own = CPU; /* set owner to CPU */
2159 +               tp->tx_desc->frame_ctrl.bits_tx_out.buffer_size = TX_BUF_SIZE;  /* set tx buffer size for descriptor */
2160 +               tp->tx_desc_dma = tp->tx_desc_dma + sizeof(GMAC_DESCRIPTOR_T); /* next tx descriptor DMA address */
2161 +               tp->tx_desc->next_desc.next_descriptor = tp->tx_desc_dma | 0x0000000b;
2162 +               tp->tx_desc = &tp->tx_desc[1] ; /* next tx descriptor virtual address */
2163 +       }
2164 +       /* the last descriptor will point back to first descriptor */
2165 +       tp->tx_desc->frame_ctrl.bits_tx_out.own = CPU;
2166 +       tp->tx_desc->frame_ctrl.bits_tx_out.buffer_size = TX_BUF_SIZE;
2167 +       tp->tx_desc->next_desc.next_descriptor = tx_first_desc_dma | 0x0000000b;
2168 +       tp->tx_desc = tp->tx_cur_desc;
2169 +       tp->tx_desc_dma = tx_first_desc_dma;
2170 +
2171 +       /* RX descriptors initial */
2172 +       tp->rx_cur_desc = tp->rx_desc;  /* virtual address */
2173 +       rx_first_desc_dma = tp->rx_desc_dma; /* physical address */
2174 +       for (i = 1; i < RX_DESC_NUM; i++)
2175 +       {
2176 +        if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
2177 +        {
2178 +            printk("%s::skb buffer allocation fail !\n",__func__);
2179 +        }
2180 +        rx_skb[index][i-1] = skb;
2181 +        tp->rx_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
2182 +               tp->rx_desc->frame_ctrl.bits_rx.own = DMA;  /* set owner bit to DMA */
2183 +               tp->rx_desc->frame_ctrl.bits_rx.buffer_size = RX_BUF_SIZE; /* set rx buffer size for descriptor */
2184 +               tp->rx_bufs_dma = tp->rx_bufs_dma + RX_BUF_SIZE;    /* point to next buffer address */
2185 +               tp->rx_desc_dma = tp->rx_desc_dma + sizeof(GMAC_DESCRIPTOR_T); /* next rx descriptor DMA address */
2186 +               tp->rx_desc->next_desc.next_descriptor = tp->rx_desc_dma | 0x0000000b;
2187 +               tp->rx_desc = &tp->rx_desc[1]; /* next rx descriptor virtual address */
2188 +       }
2189 +       /* the last descriptor will point back to first descriptor */
2190 +    if ( (skb = dev_alloc_skb(RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
2191 +    {
2192 +        printk("%s::skb buffer allocation fail !\n",__func__);
2193 +    }
2194 +    rx_skb[index][i-1] = skb;
2195 +    tp->rx_desc->buf_adr = (unsigned int)__pa(skb->data) | 0x02;    /* insert two bytes in the beginning of rx data */
2196 +       tp->rx_desc->frame_ctrl.bits_rx.own = DMA;
2197 +       tp->rx_desc->frame_ctrl.bits_rx.buffer_size = RX_BUF_SIZE;
2198 +       tp->rx_desc->next_desc.next_descriptor = rx_first_desc_dma | 0x0000000b;
2199 +       tp->rx_desc = tp->rx_cur_desc;
2200 +       tp->rx_desc_dma = rx_first_desc_dma;
2201 +       tp->rx_bufs_dma = rx_first_buf_dma;
2202 +
2203 +       for (i=0; i<GMAC_PHY_IF; i++) {
2204 +               tp->tx_desc_hdr[i] = 0;
2205 +               tp->tx_desc_tail[i] = 0;
2206 +       }
2207 +       return (0);
2208 +}
2209 +
2210 +static int gmac_clear_counter (struct net_device *dev)
2211 +{
2212 +       struct gmac_private *tp = dev->priv;
2213 +       unsigned int    dev_index;
2214 +
2215 +    dev_index = gmac_select_interface(dev);
2216 +//     tp = gmac_dev[index]->priv;
2217 +    /* clear counter */
2218 +    gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_DISCARDS);
2219 +    gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_ERRORS);
2220 +    tp->stats.tx_bytes = 0;
2221 +    tp->stats.tx_packets = 0;
2222 +       tp->stats.tx_errors = 0;
2223 +    tp->stats.rx_bytes = 0;
2224 +       tp->stats.rx_packets = 0;
2225 +       tp->stats.rx_errors = 0;
2226 +    tp->stats.rx_dropped = 0;
2227 +       return (0);
2228 +}
2229 +
2230 +static int gmac_open (struct net_device *dev)
2231 +{
2232 +       struct gmac_private     *tp = dev->priv;
2233 +       int    retval;
2234 +
2235 +    gmac_select_interface(dev);
2236 +
2237 +       /* chip reset */
2238 +       gmac_sw_reset(dev);
2239 +
2240 +    /* allocates tx/rx descriptor and buffer memory */
2241 +    gmac_init_desc_buf(dev);
2242 +
2243 +    /* get mac address from FLASH */
2244 +    gmac_get_mac_address();
2245 +
2246 +    /* set PHY register to start autonegition process */
2247 +    gmac_set_phy_status(dev);
2248 +
2249 +       /* GMAC initialization */
2250 +       if (gmac_init_chip(dev))
2251 +       {
2252 +               printk (KERN_ERR "GMAC init fail\n");
2253 +       }
2254 +
2255 +    /* start DMA process */
2256 +       gmac_hw_start(dev);
2257 +
2258 +    /* enable tx/rx register */
2259 +    gmac_enable_tx_rx(dev);
2260 +
2261 +    /* clear statistic counter */
2262 +    gmac_clear_counter(dev);
2263 +
2264 +       netif_start_queue (dev);
2265 +
2266 +    /* hook ISR */
2267 +       retval = request_irq (dev->irq, gmac_interrupt, SA_INTERRUPT, dev->name, dev);
2268 +       if (retval)
2269 +               return retval;
2270 +
2271 +       if(!FLAG_SWITCH)
2272 +       {
2273 +       init_waitqueue_head (&tp->thr_wait);
2274 +       init_completion(&tp->thr_exited);
2275 +
2276 +       tp->time_to_die = 0;
2277 +       tp->thr_pid = kernel_thread (gmac_phy_thread, dev, CLONE_FS | CLONE_FILES);
2278 +       if (tp->thr_pid < 0)
2279 +       {
2280 +               printk (KERN_WARNING "%s: unable to start kernel thread\n",dev->name);
2281 +       }
2282 +    }
2283 +       return (0);
2284 +}
2285 +
2286 +static int gmac_close(struct net_device *dev)
2287 +{
2288 +    struct gmac_private *tp = dev->priv;
2289 +    unsigned int        i,dev_index;
2290 +    unsigned int        ret;
2291 +
2292 +    dev_index = gmac_get_dev_index(dev);
2293 +
2294 +    /* stop tx/rx packet */
2295 +    gmac_disable_tx_rx(dev);
2296 +
2297 +    /* stop the chip's Tx and Rx DMA processes */
2298 +       gmac_hw_stop(dev);
2299 +
2300 +    netif_stop_queue(dev);
2301 +
2302 +    /* disable interrupts by clearing the interrupt mask */
2303 +    synchronize_irq();
2304 +    free_irq(dev->irq,dev);
2305 +
2306 +       DMA_MFREE(tp->tx_desc, TX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(unsigned int)tp->tx_desc_dma);
2307 +       DMA_MFREE(tp->rx_desc, RX_DESC_NUM*sizeof(GMAC_DESCRIPTOR_T),(unsigned int)tp->rx_desc_dma);
2308 +
2309 +#ifdef CONFIG_SL2312_MPAGE
2310 +//     kfree(tx_skb);
2311 +#endif
2312 +
2313 +    for (i=0;i<RX_DESC_NUM;i++)
2314 +    {
2315 +        if (rx_skb[dev_index][i])
2316 +        {
2317 +            dev_kfree_skb(rx_skb[dev_index][i]);
2318 +        }
2319 +    }
2320 +       if(!FLAG_SWITCH)
2321 +       {
2322 +       if (tp->thr_pid >= 0)
2323 +       {
2324 +                   tp->time_to_die = 1;
2325 +               wmb();
2326 +               ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2327 +               if (ret)
2328 +               {
2329 +                       printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2330 +                       return ret;
2331 +               }
2332 +//             wait_for_completion (&tp->thr_exited);
2333 +       }
2334 +    }
2335 +
2336 +    return (0);
2337 +}
2338 +
2339 +#ifdef CONFIG_SL2312_MPAGE
2340 +int printk_all(int dev_index, struct gmac_private* tp)
2341 +{
2342 +       int i=0;
2343 +    unsigned int tx_current_descriptor = 0;
2344 +    int hw_index;
2345 +    int fi;
2346 +    GMAC_DESCRIPTOR_T* tmp_desc;
2347 +
2348 +       GMAC_DESCRIPTOR_T* cur_desc=tp->tx_cur_desc;
2349 +       fi = ((unsigned int)cur_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2350 +       printk("tmp_desc %x, id %d\n", (int)cur_desc, fi);
2351 +
2352 +       tmp_desc = (GMAC_DESCRIPTOR_T*)((gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC) & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2353 +       hw_index = ((unsigned int)tmp_desc - tx_desc_start_adr[dev_index])/ sizeof(GMAC_DESCRIPTOR_T);
2354 +       printk("hd_desc %x, ind %d, fin desc %x\n",(int)tmp_desc, hw_index, (int)tp->tx_finished_desc);
2355 +
2356 +       for (i=0; i<TX_DESC_NUM; i++) {
2357 +               printk("**id %4d, hw_index %4d ==> ", fi, hw_index);
2358 +               printk("fc %8x ", tmp_desc->frame_ctrl.bits32);
2359 +               printk("fs %8x ", tmp_desc->flag_status.bits32);
2360 +               printk("fb %8x ", tmp_desc->buf_adr);
2361 +               printk("fd %8x\n",  tmp_desc->next_desc.next_descriptor);
2362 +               tmp_desc = (GMAC_DESCRIPTOR_T*)((tmp_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2363 +               fi = ((unsigned int)tmp_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2364 +       }
2365 +    tx_current_descriptor = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CURR_DESC);
2366 +    printk("%s: tx current descriptor = %x \n",__func__,tx_current_descriptor);
2367 +    printk("%s: interrupt status = %x \n",__func__,int_status);
2368 +    return 0;
2369 +}
2370 +
2371 +int cleanup_desc(int dev_index, struct gmac_private* tp)
2372 +{
2373 +       int i=0;
2374 +       int index = ((unsigned int)tp->tx_cur_desc - tx_desc_start_adr[dev_index])/sizeof(GMAC_DESCRIPTOR_T);
2375 +       GMAC_DESCRIPTOR_T* fill_desc = tp->tx_cur_desc;
2376 +
2377 +       for (i=0; i< TX_DESC_NUM; i++)
2378 +       {
2379 +               fill_desc->frame_ctrl.bits_tx_out.own = CPU;
2380 +               fill_desc->frame_ctrl.bits_tx_out.buffer_size = TX_BUF_SIZE;
2381 +               tx_skb[dev_index][index].desc_in_use = 0;
2382 +               free_tx_buf(dev_index, index);
2383 +               printk("cleanup di %d\n", index);
2384 +               fill_desc = (GMAC_DESCRIPTOR_T*)((fill_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2385 +               index++;
2386 +               if (index > TX_DESC_NUM)
2387 +                       index = 0;
2388 +       }
2389 +       return 1;
2390 +}
2391 +
2392 +size_t get_available_tx_desc(struct net_device* dev, int dev_index)
2393 +{
2394 +       struct gmac_private *tp = dev->priv;
2395 +       unsigned int desc_hdr = tp->tx_desc_hdr[dev_index];
2396 +       unsigned int desc_tail = tp->tx_desc_tail[dev_index];
2397 +       int available_desc_num = (TX_DESC_NUM - desc_hdr + desc_tail) & (TX_DESC_NUM-1);
2398 +       if (!available_desc_num) {
2399 +               if (tx_skb[dev_index][desc_hdr].desc_in_use)
2400 +                       return 0;
2401 +               else
2402 +                       return TX_DESC_NUM;
2403 +       }
2404 +       return available_desc_num;
2405 +}
2406 +
2407 +int check_free_tx_desc(int dev_index, int n, GMAC_DESCRIPTOR_T* desc)
2408 +{
2409 +       int i,index;
2410 +       GMAC_DESCRIPTOR_T* tmp_desc = desc;
2411 +
2412 +       if (n > TX_DESC_NUM)
2413 +               return 0;
2414 +
2415 +       index = ((unsigned int)tmp_desc - tx_desc_start_adr[dev_index])/sizeof(GMAC_DESCRIPTOR_T);
2416 +       for (i=0; i<n; i++)
2417 +       {
2418 +               if (tx_skb[dev_index][index].desc_in_use)
2419 +               {
2420 +                       printk("sw desc %d is in use\n", index);
2421 +                       /* cleanup all the descriptors to check if DMA still running */
2422 +                       return 0;
2423 +               }
2424 +               index++;
2425 +               if (index == TX_DESC_NUM)
2426 +                       index = 0;
2427 +       }
2428 +       return 1;
2429 +}
2430 +
2431 +#define TCPHDRLEN(tcp_hdr)  ((ntohs(*((__u16 *)tcp_hdr + 6)) >> 12) & 0x000F)
2432 +
2433 +inline int fill_in_desc(int dev_index, GMAC_DESCRIPTOR_T *desc, char* data, int len, int total_len, int sof, int freeable, int ownership, struct sk_buff* skb)
2434 +{
2435 +       int index = ((unsigned int)desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2436 +
2437 +       if (desc->frame_ctrl.bits_tx_in.own == CPU)
2438 +       {
2439 +               tx_skb[dev_index][index].freeable = freeable;
2440 +               if ((sof & 0x01) && skb) {
2441 +                       tx_skb[dev_index][index].skb = skb;
2442 +               }
2443 +               else
2444 +                       tx_skb[dev_index][index].skb = 0;
2445 +
2446 +               if (sof != 2)
2447 +                       tx_skb[dev_index][index].desc_in_use = 1;
2448 +               else
2449 +                       tx_skb[dev_index][index].desc_in_use = 0;
2450 +
2451 +               consistent_sync(data, len, PCI_DMA_TODEVICE);
2452 +               desc->buf_adr = (unsigned int)__pa(data);
2453 +               desc->frame_ctrl.bits_tx_out.buffer_size = len;
2454 +               desc->flag_status.bits_tx_flag.frame_count = total_len;
2455 +               desc->next_desc.bits.eofie = 1;
2456 +               desc->next_desc.bits.sof_eof = sof;
2457 +               desc->frame_ctrl.bits_tx_out.vlan_enable = 0;
2458 +               desc->frame_ctrl.bits_tx_out.ip_csum_en = 1;     /* TSS IPv4 IP header checksum enable */
2459 +               desc->frame_ctrl.bits_tx_out.ipv6_tx_en = 1;    /* TSS IPv6 tx enable */
2460 +               desc->frame_ctrl.bits_tx_out.tcp_csum_en = 1;    /* TSS TCP checksum enable */
2461 +               desc->frame_ctrl.bits_tx_out.udp_csum_en = 1;    /* TSS UDP checksum enable */
2462 +        wmb();
2463 +               desc->frame_ctrl.bits_tx_out.own = ownership;
2464 +//             consistent_sync(desc, sizeof(GMAC_DESCRIPTOR_T), PCI_DMA_TODEVICE);
2465 +       }
2466 +       return 0;
2467 +}
2468 +#endif
2469 +
2470 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
2471 +{
2472 +       struct gmac_private     *tp = dev->priv;
2473 +       GMAC_TXDMA_CTRL_T               tx_ctrl,tx_ctrl_mask;
2474 +       GMAC_TXDMA_FIRST_DESC_T txdma_busy;
2475 +       unsigned int            len = skb->len;
2476 +       unsigned int            dev_index;
2477 +       static unsigned int     pcount = 0;
2478 +#ifdef CONFIG_SL2312_MPAGE
2479 +    GMAC_DESCRIPTOR_T *fill_desc;
2480 +       int snd_pages = skb_shinfo(skb)->nr_frags;  /* get number of descriptor */
2481 +       int desc_needed = 1; // for jumbo packet, one descriptor is enough.
2482 +       int header_len = skb->len;
2483 +    struct iphdr       *ip_hdr;
2484 +    struct tcphdr      *tcp_hdr;
2485 +    int             tcp_hdr_len;
2486 +    int             data_len;
2487 +    int             prv_index;
2488 +    long            seq_num;
2489 +    int             first_desc_index;
2490 +    int             ownership, freeable;
2491 +    int             eof;
2492 +       int             i=0;
2493 +#endif
2494 +#ifdef CONFIG_TXINT_DISABLE
2495 +       int                             available_desc_cnt = 0;
2496 +#endif
2497 +
2498 +    dev_index = gmac_select_interface(dev);
2499 +
2500 +#ifdef CONFIG_TXINT_DISABLE
2501 +       available_desc_cnt = get_available_tx_desc(dev, dev_index);
2502 +
2503 +       if (available_desc_cnt < (TX_DESC_NUM >> 2)) {
2504 +               gmac_tx_packet_complete(dev);
2505 +       }
2506 +#endif
2507 +
2508 +#ifdef CONFIG_SL2312_MPAGE
2509 +
2510 +       fill_desc = tp->tx_cur_desc;
2511 +       if(!fill_desc) {
2512 +               printk("cur_desc is NULL!\n");
2513 +               return -1;
2514 +       }
2515 +
2516 +       if (storlink_ctl.recvfile==2)
2517 +       {
2518 +           printk("snd_pages=%d skb->len=%d\n",snd_pages,skb->len);
2519 +       }
2520 +
2521 +       if (snd_pages)
2522 +               desc_needed += snd_pages;   /* decriptors needed for this large packet */
2523 +
2524 +       if (!check_free_tx_desc(dev_index, desc_needed, fill_desc)) {
2525 +               printk("no available desc!\n");
2526 +        gmac_dump_register(dev);
2527 +               printk_all(dev_index, tp);
2528 +               tp->stats.tx_dropped++;
2529 +               if (pcount++ > 10)
2530 +               {
2531 +                   for (;;);
2532 +               }
2533 +               return -1;
2534 +       }
2535 +
2536 +       first_desc_index = ((unsigned int)fill_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2537 +
2538 +       /* check if the tcp packet is in order*/
2539 +       ip_hdr = (struct iphdr*) &(skb->data[14]);
2540 +       tcp_hdr = (struct tcphdr*) &(skb->data[14+ip_hdr->ihl * 4]);
2541 +       tcp_hdr_len = TCPHDRLEN(tcp_hdr) * 4;
2542 +       data_len = skb->len - 14 - ip_hdr->ihl *4 - tcp_hdr_len;
2543 +
2544 +       prv_index = first_desc_index-1;
2545 +       if (prv_index <0)
2546 +           prv_index += TX_DESC_NUM;
2547 +       seq_num = ntohl(tcp_hdr->seq);
2548 +
2549 +       if (snd_pages)
2550 +       {
2551 +               // calculate header length
2552 +               // check fragment total length and header len = skb len - frag len
2553 +               // or parse the header.
2554 +               for (i=0; i<snd_pages; i++) {
2555 +                       skb_frag_t* frag = &skb_shinfo(skb)->frags[i];
2556 +                       header_len -= frag->size;
2557 +               }
2558 +               ownership = CPU;
2559 +               freeable = 0;
2560 +               /* fill header into first descriptor */
2561 +               fill_in_desc(dev_index, fill_desc, skb->data, header_len, len, 2, freeable, ownership, 0);
2562 +               fill_desc = (GMAC_DESCRIPTOR_T*)((fill_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2563 +               tx_skb[dev_index][first_desc_index].end_seq = seq_num + data_len;
2564 +
2565 +               eof = 0;
2566 +               ownership = DMA;
2567 +               for (i=0; i<snd_pages; i++)
2568 +               {
2569 +                       skb_frag_t* frag = &skb_shinfo(skb)->frags[i];
2570 +                       int start_pos = frag->page_offset;
2571 +                       char* data_buf = page_address(frag->page);
2572 +                       int data_size = frag->size;
2573 +                       int cur_index;
2574 +
2575 +                       if (i == snd_pages-1)
2576 +                       {
2577 +                               eof=1;
2578 +                               freeable = 1;
2579 +                       }
2580 +                       fill_in_desc(dev_index, fill_desc, data_buf+(start_pos), data_size,
2581 +                                    len, eof, freeable, ownership, skb);
2582 +                       cur_index = ((unsigned int)fill_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2583 +
2584 +                       fill_desc = (GMAC_DESCRIPTOR_T*)((fill_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2585 +               }
2586 +               /* pass the ownership of the first descriptor to hardware */
2587 +//         disable_irq(gmac_irq[dev_index]);
2588 +               tx_skb[dev_index][first_desc_index].desc_in_use = 1;
2589 +        wmb();
2590 +               tp->tx_cur_desc->frame_ctrl.bits_tx_out.own = DMA;
2591 +//             consistent_sync(tp->tx_cur_desc, sizeof(GMAC_DESCRIPTOR_T), PCI_DMA_TODEVICE);
2592 +               tp->tx_cur_desc = fill_desc;
2593 +               dev->trans_start = jiffies;
2594 +//         enable_irq(gmac_irq[dev_index]);
2595 +       }
2596 +       else if ( tp->tx_cur_desc->frame_ctrl.bits_tx_out.own == CPU )
2597 +       {
2598 +//             tx_skb[dev_index][first_desc_index].end_seq = seq_num + data_len;
2599 +//         disable_irq(gmac_irq[dev_index]);
2600 +               fill_in_desc(dev_index, tp->tx_cur_desc, skb->data, skb->len, skb->len, 3, 1, DMA, skb);
2601 +//         enable_irq(gmac_irq[dev_index]);
2602 +               //consistent_sync(tp->tx_cur_desc, sizeof(GMAC_DESCRIPTOR_T), PCI_DMA_TODEVICE);
2603 +               tp->tx_cur_desc = (GMAC_DESCRIPTOR_T*)((tp->tx_cur_desc->next_desc.next_descriptor & 0xfffffff0) + tx_desc_virtual_base[dev_index]);
2604 +               dev->trans_start = jiffies;
2605 +       }
2606 +       else
2607 +       {
2608 +               printk("gmac tx drop!\n");
2609 +               tp->stats.tx_dropped++;
2610 +               return -1;
2611 +       }
2612 +
2613 +#ifdef CONFIG_TXINT_DISABLE
2614 +       tp->tx_desc_hdr[dev_index] = (tp->tx_desc_hdr[dev_index] + desc_needed) & (TX_DESC_NUM-1);
2615 +#endif
2616 +
2617 +#else
2618 +    if ((tp->tx_cur_desc->frame_ctrl.bits_tx_out.own == CPU) && (len < TX_BUF_SIZE))
2619 +       {
2620 +        index = ((unsigned int)tp->tx_cur_desc - tx_desc_start_adr[dev_index]) / sizeof(GMAC_DESCRIPTOR_T);
2621 +        tx_skb[dev_index][index] = skb;
2622 +        consistent_sync(skb->data,skb->len,PCI_DMA_TODEVICE);
2623 +        tp->tx_cur_desc->buf_adr = (unsigned int)__pa(skb->data);
2624 +       tp->tx_cur_desc->flag_status.bits_tx_flag.frame_count = len;    /* total frame byte count */
2625 +       tp->tx_cur_desc->next_desc.bits.sof_eof = 0x03;                 /*only one descriptor*/
2626 +               tp->tx_cur_desc->frame_ctrl.bits_tx_out.buffer_size = len;      /* descriptor byte count */
2627 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.vlan_enable = 0;
2628 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.ip_csum_en = 0;     /* TSS IPv4 IP header checksum enable */
2629 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.ipv6_tx_en = 0 ;    /* TSS IPv6 tx enable */
2630 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.tcp_csum_en = 0;    /* TSS TCP checksum enable */
2631 +        tp->tx_cur_desc->frame_ctrl.bits_tx_out.udp_csum_en = 0;    /* TSS UDP checksum enable */
2632 +        wmb();
2633 +       tp->tx_cur_desc->frame_ctrl.bits_tx_out.own = DMA;              /* set owner bit */
2634 +       tp->tx_cur_desc = (GMAC_DESCRIPTOR_T *)((tp->tx_cur_desc->next_desc.next_descriptor & 0xfffffff0)+tx_desc_virtual_base[dev_index]);
2635 +       dev->trans_start = jiffies;
2636 +       }
2637 +       else
2638 +       {
2639 +               /* no free tx descriptor */
2640 +               dev_kfree_skb(skb);
2641 +           netif_stop_queue(dev);
2642 +               tp->stats.tx_dropped++;
2643 +               return (-1);
2644 +       }
2645 +#endif
2646 +       /* if TX DMA process is stoped , restart it */
2647 +       txdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_FIRST_DESC);
2648 +       if (txdma_busy.bits.td_busy == 0)
2649 +       {
2650 +               /* restart DMA process */
2651 +               tx_ctrl.bits32 = 0;
2652 +               tx_ctrl.bits.td_start = 1;
2653 +               tx_ctrl.bits.td_continue = 1;
2654 +               tx_ctrl_mask.bits32 = 0;
2655 +               tx_ctrl_mask.bits.td_start = 1;
2656 +               tx_ctrl_mask.bits.td_continue = 1;
2657 +               gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,tx_ctrl.bits32,tx_ctrl_mask.bits32);
2658 +       }
2659 +       return (0);
2660 +}
2661 +
2662 +
2663 +struct net_device_stats * gmac_get_stats(struct net_device *dev)
2664 +{
2665 +    struct gmac_private *tp = dev->priv;
2666 +    unsigned long       flags;
2667 +    unsigned int        pkt_drop;
2668 +    unsigned int        pkt_error;
2669 +    unsigned int        dev_index;
2670 +
2671 +    dev_index = gmac_select_interface(dev);
2672 +
2673 +//     if (storlink_ctl.recvfile==3)
2674 +//     {
2675 +//        printk("GMAC_GLOBAL_BASE_ADDR=%x\n", readl(GMAC_GLOBAL_BASE_ADDR+0x30));
2676 +//        gmac_dump_register(dev);
2677 +//        printk_all(0, dev);
2678 +//    }
2679 +
2680 +    if (netif_running(dev))
2681 +    {
2682 +        /* read H/W counter */
2683 +        spin_lock_irqsave(&tp->lock,flags);
2684 +        pkt_drop = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_DISCARDS);
2685 +        pkt_error = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_IN_ERRORS);
2686 +        tp->stats.rx_dropped = tp->stats.rx_dropped + pkt_drop;
2687 +        tp->stats.rx_errors = tp->stats.rx_errors + pkt_error;
2688 +        spin_unlock_irqrestore(&tp->lock,flags);
2689 +    }
2690 +    return &tp->stats;
2691 +}
2692 +
2693 +static unsigned const ethernet_polynomial = 0x04c11db7U;
2694 +static inline u32 ether_crc (int length, unsigned char *data)
2695 +{
2696 +       int crc = -1;
2697 +       unsigned int i;
2698 +       unsigned int crc_val=0;
2699 +
2700 +       while (--length >= 0) {
2701 +               unsigned char current_octet = *data++;
2702 +               int bit;
2703 +               for (bit = 0; bit < 8; bit++, current_octet >>= 1)
2704 +                       crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
2705 +                            ethernet_polynomial : 0);
2706 +       }
2707 +       crc = ~crc;
2708 +       for (i=0;i<32;i++)
2709 +       {
2710 +               crc_val = crc_val + (((crc << i) & 0x80000000) >> (31-i));
2711 +       }
2712 +       return crc_val;
2713 +}
2714 +
2715 +static void gmac_set_rx_mode(struct net_device *dev)
2716 +{
2717 +    GMAC_RX_FLTR_T      filter;
2718 +       unsigned int        mc_filter[2];       /* Multicast hash filter */
2719 +    int                 bit_nr;
2720 +       unsigned int        i, dev_index;
2721 +
2722 +    dev_index = gmac_select_interface(dev);
2723 +
2724 +//    printk("%s : dev->flags = %x \n",__func__,dev->flags);
2725 +//    dev->flags |= IFF_ALLMULTI;  /* temp */
2726 +    filter.bits32 = 0;
2727 +    filter.bits.error = 0;
2728 +       if (dev->flags & IFF_PROMISC)
2729 +       {
2730 +           filter.bits.error = 1;
2731 +        filter.bits.promiscuous = 1;
2732 +        filter.bits.broadcast = 1;
2733 +        filter.bits.multicast = 1;
2734 +        filter.bits.unicast = 1;
2735 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
2736 +       }
2737 +       else if (dev->flags & IFF_ALLMULTI)
2738 +       {
2739 +        filter.bits.promiscuous = 1;
2740 +        filter.bits.broadcast = 1;
2741 +        filter.bits.multicast = 1;
2742 +        filter.bits.unicast = 1;
2743 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
2744 +       }
2745 +       else
2746 +       {
2747 +               struct dev_mc_list *mclist;
2748 +
2749 +        filter.bits.promiscuous = 1;
2750 +        filter.bits.broadcast = 1;
2751 +        filter.bits.multicast = 1;
2752 +        filter.bits.unicast = 1;
2753 +               mc_filter[1] = mc_filter[0] = 0;
2754 +               for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;i++, mclist = mclist->next)
2755 +               {
2756 +            bit_nr = ether_crc(ETH_ALEN,mclist->dmi_addr) & 0x0000003f;
2757 +            if (bit_nr < 32)
2758 +            {
2759 +                mc_filter[0] = mc_filter[0] | (1<<bit_nr);
2760 +            }
2761 +            else
2762 +            {
2763 +                mc_filter[1] = mc_filter[1] | (1<<(bit_nr-32));
2764 +            }
2765 +               }
2766 +       }
2767 +    filter.bits32 = 0x1f;
2768 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_RX_FLTR,filter.bits32,0xffffffff);
2769 +
2770 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_MCAST_FIL0,mc_filter[0],0xffffffff);
2771 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_MCAST_FIL1,mc_filter[1],0xffffffff);
2772 +    return;
2773 +}
2774 +
2775 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
2776 +{
2777 +       struct sockaddr *sock;
2778 +       unsigned int    reg_val;
2779 +       unsigned int    dev_index;
2780 +    unsigned int    i;
2781 +
2782 +    dev_index = gmac_select_interface(dev);
2783 +
2784 +       sock = (struct sockaddr *) addr;
2785 +       for (i = 0; i < 6; i++)
2786 +       {
2787 +               dev->dev_addr[i] = sock->sa_data[i];
2788 +       }
2789 +
2790 +    reg_val = dev->dev_addr[0] + (dev->dev_addr[1]<<8) + (dev->dev_addr[2]<<16) + (dev->dev_addr[3]<<24);
2791 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_STA_ADD0,reg_val,0xffffffff);
2792 +    reg_val = dev->dev_addr[4] + (dev->dev_addr[5]<<8) ;
2793 +    gmac_write_reg(gmac_base_addr[dev_index] + GMAC_STA_ADD1,reg_val,0x0000ffff);
2794 +    memcpy(&eth0_mac[0],&dev->dev_addr[0],6);
2795 +    printk("Storlink %s address = ",dev->name);
2796 +    printk("%02x",dev->dev_addr[0]);
2797 +    printk("%02x",dev->dev_addr[1]);
2798 +    printk("%02x",dev->dev_addr[2]);
2799 +    printk("%02x",dev->dev_addr[3]);
2800 +    printk("%02x",dev->dev_addr[4]);
2801 +    printk("%02x\n",dev->dev_addr[5]);
2802 +
2803 +    return (0);
2804 +}
2805 +
2806 +static void gmac_tx_timeout(struct net_device *dev)
2807 +{
2808 +       GMAC_TXDMA_CTRL_T               tx_ctrl,tx_ctrl_mask;
2809 +    GMAC_TXDMA_FIRST_DESC_T     txdma_busy;
2810 +    int                                                        dev_index;
2811 +
2812 +    dev_index = gmac_select_interface(dev);
2813 +
2814 +    /* if TX DMA process is stoped , restart it */
2815 +       txdma_busy.bits32 = gmac_read_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_FIRST_DESC);
2816 +       if (txdma_busy.bits.td_busy == 0)
2817 +       {
2818 +               /* restart DMA process */
2819 +               tx_ctrl.bits32 = 0;
2820 +               tx_ctrl.bits.td_start = 1;
2821 +               tx_ctrl.bits.td_continue = 1;
2822 +               tx_ctrl_mask.bits32 = 0;
2823 +               tx_ctrl_mask.bits.td_start = 1;
2824 +               tx_ctrl_mask.bits.td_continue = 1;
2825 +               gmac_write_reg(gmac_base_addr[dev_index] + GMAC_TXDMA_CTRL,tx_ctrl.bits32,tx_ctrl_mask.bits32);
2826 +       }
2827 +       netif_wake_queue(dev);
2828 +    return;
2829 +}
2830 +
2831 +static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2832 +{
2833 +       int rc = 0;
2834 +    unsigned char *hwa = rq->ifr_ifru.ifru_hwaddr.sa_data;
2835 +
2836 +       if (!netif_running(dev))
2837 +       {
2838 +           printk("Before changing the H/W address,please down the device.\n");
2839 +               return -EINVAL;
2840 +    }
2841 +
2842 +       switch (cmd) {
2843 +       case SIOCETHTOOL:
2844 +        break;
2845 +
2846 +    case SIOCSIFHWADDR:
2847 +        gmac_set_mac_address(dev,hwa);
2848 +        break;
2849 +
2850 +       case SIOCGMIIPHY:       /* Get the address of the PHY in use. */
2851 +       case SIOCDEVPRIVATE:    /* binary compat, remove in 2.5 */
2852 +        break;
2853 +
2854 +       case SIOCGMIIREG:       /* Read the specified MII register. */
2855 +       case SIOCDEVPRIVATE+1:
2856 +               break;
2857 +
2858 +       case SIOCSMIIREG:       /* Write the specified MII register */
2859 +       case SIOCDEVPRIVATE+2:
2860 +               break;
2861 +
2862 +       default:
2863 +               rc = -EOPNOTSUPP;
2864 +               break;
2865 +       }
2866 +
2867 +       return rc;
2868 +}
2869 +
2870 +static void gmac_cleanup_module(void)
2871 +{
2872 +    int i;
2873 +
2874 +    for (i=0;i<GMAC_PHY_IF;i++)
2875 +    {
2876 +        unregister_netdev(gmac_dev[i]);
2877 +    }
2878 +       return ;
2879 +}
2880 +
2881 +static int __init gmac_init_module(void)
2882 +{
2883 +       struct gmac_private *tp;
2884 +       struct net_device *dev[GMAC_PHY_IF];
2885 +       unsigned int i;
2886 +
2887 +#ifdef MODULE
2888 +       printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2889 +#endif
2890 +//     init_waitqueue_entry(&wait, current);
2891 +
2892 +       printk("GMAC Init......\n");
2893 +       for(i = 0; i<GMAC_PHY_IF; i++)
2894 +       {
2895 +               dev[i] = alloc_etherdev(sizeof(struct gmac_private));
2896 +               if (dev[i] == NULL)
2897 +               {
2898 +                       printk (KERN_ERR "Can't allocate ethernet device #%d .\n",i);
2899 +                       return -ENOMEM;
2900 +               }
2901 +        gmac_dev[i] = dev[i];
2902 +
2903 +               SET_MODULE_OWNER(dev[i]);
2904 +
2905 +               tp = dev[i]->priv;
2906 +
2907 +               dev[i]->base_addr = gmac_base_addr[i];
2908 +               dev[i]->irq = gmac_irq[i];
2909 +           dev[i]->open = gmac_open;
2910 +           dev[i]->stop = gmac_close;
2911 +               dev[i]->hard_start_xmit = gmac_start_xmit;
2912 +               dev[i]->get_stats = gmac_get_stats;
2913 +               dev[i]->set_multicast_list = gmac_set_rx_mode;
2914 +               dev[i]->set_mac_address = gmac_set_mac_address;
2915 +               dev[i]->do_ioctl = gmac_netdev_ioctl;
2916 +               dev[i]->tx_timeout = gmac_tx_timeout;
2917 +               dev[i]->watchdog_timeo = TX_TIMEOUT;
2918 +               dev[i]->features |= NETIF_F_SG|NETIF_F_HW_CSUM|NETIF_F_TSO;
2919 +#ifdef CONFIG_SL_NAPI
2920 +        printk("NAPI driver is enabled.\n");
2921 +        if (i==0)
2922 +        {
2923 +               dev[i]->poll = gmac_rx_poll_ga;
2924 +               dev[i]->weight = 64;
2925 +           }
2926 +           else
2927 +           {
2928 +               dev[i]->poll = gmac_rx_poll_gb;
2929 +               dev[i]->weight = 64;
2930 +           }
2931 +#endif
2932 +
2933 +               if (register_netdev(dev[i]))
2934 +               {
2935 +                       gmac_cleanup_module();
2936 +                       return(-1);
2937 +               }
2938 +       }
2939 +
2940 +#ifdef CONFIG_SL3516_ASIC
2941 +{
2942 +    unsigned int    val;
2943 +
2944 +    /* set GMAC global register */
2945 +    val = readl(GMAC_GLOBAL_BASE_ADDR+0x10);
2946 +    val = val | 0x005a0000;
2947 +    writel(val,GMAC_GLOBAL_BASE_ADDR+0x10);
2948 +    writel(0x07f007f0,GMAC_GLOBAL_BASE_ADDR+0x1c);
2949 +    writel(0x77770000,GMAC_GLOBAL_BASE_ADDR+0x20);
2950 +    writel(0x77770000,GMAC_GLOBAL_BASE_ADDR+0x24);
2951 +       val = readl(GMAC_GLOBAL_BASE_ADDR+0x04);
2952 +       if((val&(1<<20))==0){           // GMAC1 enable
2953 +               val = readl(GMAC_GLOBAL_BASE_ADDR+0x30);
2954 +               val = (val & 0xe7ffffff) | 0x08000000;
2955 +               writel(val,GMAC_GLOBAL_BASE_ADDR+0x30);
2956 +       }
2957 +
2958 +}
2959 +#endif
2960 +
2961 +//     printk("%s: dev0=%x  dev1=%x \n",__func__,dev[0],dev[1]);
2962 +//     FLAG_SWITCH = 0 ;
2963 +//     FLAG_SWITCH = SPI_get_identifier();
2964 +//     if(FLAG_SWITCH)
2965 +//     {
2966 +//             printk("Configure ADM699X...\n");
2967 +//             SPI_default();  //Add by jason for ADM699X configuration
2968 +//     }
2969 +       return (0);
2970 +}
2971 +
2972 +
2973 +module_init(gmac_init_module);
2974 +module_exit(gmac_cleanup_module);
2975 +
2976 +static int gmac_phy_thread (void *data)
2977 +{
2978 +       struct net_device   *dev = data;
2979 +       struct gmac_private *tp = dev->priv;
2980 +       unsigned long       timeout;
2981 +
2982 +    daemonize("%s", dev->name);
2983 +       allow_signal(SIGTERM);
2984 +//     reparent_to_init();
2985 +//     spin_lock_irq(&current->sigmask_lock);
2986 +//     sigemptyset(&current->blocked);
2987 +//     recalc_sigpending(current);
2988 +//     spin_unlock_irq(&current->sigmask_lock);
2989 +//     strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
2990 +//     current->comm[sizeof(current->comm) - 1] = '\0';
2991 +
2992 +       while (1)
2993 +       {
2994 +           timeout = next_tick;
2995 +               do
2996 +               {
2997 +                       timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
2998 +               } while (!signal_pending (current) && (timeout > 0));
2999 +
3000 +               if (signal_pending (current))
3001 +               {
3002 +//                     spin_lock_irq(&current->sigmask_lock);
3003 +                       flush_signals(current);
3004 +//                     spin_unlock_irq(&current->sigmask_lock);
3005 +               }
3006 +
3007 +               if (tp->time_to_die)
3008 +                       break;
3009 +
3010 +//        printk("%s : Polling PHY Status...%x\n",__func__,dev);
3011 +               rtnl_lock ();
3012 +        gmac_get_phy_status(dev);
3013 +               rtnl_unlock ();
3014 +       }
3015 +       complete_and_exit (&tp->thr_exited, 0);
3016 +}
3017 +
3018 +static void gmac_set_phy_status(struct net_device *dev)
3019 +{
3020 +    GMAC_STATUS_T   status;
3021 +    unsigned int    reg_val;
3022 +    unsigned int    i = 0;
3023 +    unsigned int    index;
3024 +
3025 +    if (FLAG_SWITCH==1)
3026 +    {
3027 +        return; /* GMAC connects to a switch chip, not PHY */
3028 +    }
3029 +
3030 +    index = gmac_get_dev_index(dev);
3031 +
3032 +    if (index == 0)
3033 +    {
3034 +//     mii_write(phy_addr[index],0x04,0x0461); /* advertisement 10M full duplex, pause capable on */
3035 +//     mii_write(phy_addr[index],0x04,0x0421); /* advertisement 10M half duplex, pause capable on */
3036 +       mii_write(phy_addr[index],0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
3037 +//     mii_write(phy_addr[index],0x04,0x04a1); /* advertisement 100M half duplex, pause capable on */
3038 +#ifdef CONFIG_SL3516_ASIC
3039 +       mii_write(phy_addr[index],0x09,0x0300); /* advertisement 1000M full duplex, pause capable on */
3040 +//     mii_write(phy_addr[index],0x09,0x0000); /* advertisement 1000M full duplex, pause capable on */
3041 +#endif
3042 +    }
3043 +    else
3044 +    {
3045 +//     mii_write(phy_addr[index],0x04,0x0461); /* advertisement 10M full duplex, pause capable on */
3046 +//     mii_write(phy_addr[index],0x04,0x0421); /* advertisement 10M half duplex, pause capable on */
3047 +       mii_write(phy_addr[index],0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
3048 +//     mii_write(phy_addr[index],0x04,0x04a1); /* advertisement 100M half duplex, pause capable on */
3049 +#ifdef CONFIG_SL3516_ASIC
3050 +//     mii_write(phy_addr[index],0x09,0x0000); /* advertisement no 1000M */
3051 +       mii_write(phy_addr[index],0x09,0x0300); /* advertisement 1000M full duplex, pause capable on */
3052 +#endif
3053 +       }
3054 +
3055 +    mii_write(phy_addr[index],0x00,0x1200); /* Enable and Restart Auto-Negotiation */
3056 +    mii_write(phy_addr[index],0x18,0x0041); /* Enable Active led */
3057 +    while (((reg_val=mii_read(phy_addr[index],0x01)) & 0x00000004)!=0x04)
3058 +    {
3059 +        i++;
3060 +        if (i > 30)
3061 +        {
3062 +            break;
3063 +        }
3064 +       msleep(100);
3065 +    }
3066 +    if (i>30)
3067 +    {
3068 +        pre_phy_status[index] = LINK_DOWN;
3069 +               clear_bit(__LINK_STATE_START, &dev->state);
3070 +        netif_stop_queue(dev);
3071 +        storlink_ctl.link = 0;
3072 +        printk("Link Down (%04x) ",reg_val);
3073 +    }
3074 +    else
3075 +    {
3076 +        pre_phy_status[index] = LINK_UP;
3077 +               set_bit(__LINK_STATE_START, &dev->state);
3078 +        netif_wake_queue(dev);
3079 +        storlink_ctl.link = 1;
3080 +        printk("Link Up (%04x) ",reg_val);
3081 +    }
3082 +
3083 +    status.bits32 = 0;
3084 +    reg_val = mii_read(phy_addr[index],10);
3085 +    printk("reg_val0 = %x \n",reg_val);
3086 +    if ((reg_val & 0x0800) == 0x0800)
3087 +    {
3088 +        status.bits.duplex = 1;
3089 +        status.bits.speed = 2;
3090 +        printk(" 1000M/Full \n");
3091 +    }
3092 +    else if ((reg_val & 0x0400) == 0x0400)
3093 +    {
3094 +        status.bits.duplex = 0;
3095 +        status.bits.speed = 2;
3096 +        printk(" 1000M/Half \n");
3097 +    }
3098 +    else
3099 +    {
3100 +        reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5;
3101 +        printk("reg_val1 = %x \n",reg_val);
3102 +        if ((reg_val & 0x08)==0x08) /* 100M full duplex */
3103 +        {
3104 +                status.bits.duplex = 1;
3105 +                status.bits.speed = 1;
3106 +                printk(" 100M/Full \n");
3107 +        }
3108 +        else if ((reg_val & 0x04)==0x04) /* 100M half duplex */
3109 +        {
3110 +                status.bits.duplex = 0;
3111 +                status.bits.speed = 1;
3112 +                printk(" 100M/Half \n");
3113 +        }
3114 +        else if ((reg_val & 0x02)==0x02) /* 10M full duplex */
3115 +        {
3116 +                status.bits.duplex = 1;
3117 +                status.bits.speed = 0;
3118 +                printk(" 10M/Full \n");
3119 +        }
3120 +        else if ((reg_val & 0x01)==0x01) /* 10M half duplex */
3121 +        {
3122 +                status.bits.duplex = 0;
3123 +                status.bits.speed = 0;
3124 +                printk(" 100M/Half \n");
3125 +        }
3126 +    }
3127 +
3128 +    reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5;
3129 +    if ((reg_val & 0x20)==0x20)
3130 +    {
3131 +        flow_control_enable[index] = 1;
3132 +        printk("Flow Control Enable. \n");
3133 +    }
3134 +    else
3135 +    {
3136 +        flow_control_enable[index] = 0;
3137 +        printk("Flow Control Disable. \n");
3138 +    }
3139 +    full_duplex = status.bits.duplex;
3140 +    speed = status.bits.speed;
3141 +}
3142 +
3143 +static void gmac_get_phy_status(struct net_device *dev)
3144 +{
3145 +       GMAC_CONFIG0_T  config0,config0_mask;
3146 +    GMAC_STATUS_T   status;
3147 +    unsigned int    reg_val;
3148 +    unsigned int    index;
3149 +
3150 +    index = gmac_select_interface(dev);
3151 +
3152 +    status.bits32 = 0;
3153 +    status.bits.phy_mode = 1;
3154 +
3155 +#ifdef CONFIG_SL3516_ASIC
3156 +    status.bits.mii_rmii = 2;   /* default value for ASIC version */
3157 +//    status.bits.speed = 1;
3158 +#else
3159 +    if (index==0)
3160 +        status.bits.mii_rmii = 0;
3161 +    else
3162 +        status.bits.mii_rmii = 2;
3163 +#endif
3164 +
3165 +    /* read PHY status register */
3166 +    reg_val = mii_read(phy_addr[index],0x01);
3167 +    if ((reg_val & 0x0024) == 0x0024) /* link is established and auto_negotiate process completed */
3168 +    {
3169 +        /* read PHY Auto-Negotiation Link Partner Ability Register */
3170 +        reg_val = mii_read(phy_addr[index],10);
3171 +        if ((reg_val & 0x0800) == 0x0800)
3172 +        {
3173 +            status.bits.mii_rmii = 3;  /* RGMII 1000Mbps mode */
3174 +            status.bits.duplex = 1;
3175 +            status.bits.speed = 2;
3176 +        }
3177 +        else if ((reg_val & 0x0400) == 0x0400)
3178 +        {
3179 +            status.bits.mii_rmii = 3;  /* RGMII 1000Mbps mode */
3180 +            status.bits.duplex = 0;
3181 +            status.bits.speed = 2;
3182 +        }
3183 +        else
3184 +        {
3185 +            reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5;
3186 +            if ((reg_val & 0x08)==0x08) /* 100M full duplex */
3187 +            {
3188 +                    status.bits.mii_rmii = 2;  /* RGMII 10/100Mbps mode */
3189 +                    status.bits.duplex = 1;
3190 +                    status.bits.speed = 1;
3191 +            }
3192 +            else if ((reg_val & 0x04)==0x04) /* 100M half duplex */
3193 +            {
3194 +                    status.bits.mii_rmii = 2;  /* RGMII 10/100Mbps mode */
3195 +                    status.bits.duplex = 0;
3196 +                    status.bits.speed = 1;
3197 +            }
3198 +            else if ((reg_val & 0x02)==0x02) /* 10M full duplex */
3199 +            {
3200 +                    status.bits.mii_rmii = 2;  /* RGMII 10/100Mbps mode */
3201 +                    status.bits.duplex = 1;
3202 +                    status.bits.speed = 0;
3203 +            }
3204 +            else if ((reg_val & 0x01)==0x01) /* 10M half duplex */
3205 +            {
3206 +                    status.bits.mii_rmii = 2;  /* RGMII 10/100Mbps mode */
3207 +                    status.bits.duplex = 0;
3208 +                    status.bits.speed = 0;
3209 +            }
3210 +        }
3211 +        status.bits.link = LINK_UP; /* link up */
3212 +        netif_wake_queue(dev);
3213 +
3214 +        reg_val = (mii_read(phy_addr[index],0x05) & 0x05E0) >> 5;
3215 +        if ((reg_val & 0x20)==0x20)
3216 +        {
3217 +            if (flow_control_enable[index] == 0)
3218 +            {
3219 +                config0.bits32 = 0;
3220 +                config0_mask.bits32 = 0;
3221 +                config0.bits.tx_fc_en = 1; /* enable tx flow control */
3222 +                config0.bits.rx_fc_en = 1; /* enable rx flow control */
3223 +                config0_mask.bits.tx_fc_en = 1;
3224 +                config0_mask.bits.rx_fc_en = 1;
3225 +                gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
3226 +//                printk("eth%d Flow Control Enable. \n",index);
3227 +            }
3228 +            flow_control_enable[index] = 1;
3229 +        }
3230 +        else
3231 +        {
3232 +            if (flow_control_enable[index] == 1)
3233 +            {
3234 +                config0.bits32 = 0;
3235 +                config0_mask.bits32 = 0;
3236 +                config0.bits.tx_fc_en = 0; /* disable tx flow control */
3237 +                config0.bits.rx_fc_en = 0; /* disable rx flow control */
3238 +                config0_mask.bits.tx_fc_en = 1;
3239 +                config0_mask.bits.rx_fc_en = 1;
3240 +                gmac_write_reg(gmac_base_addr[index] + GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
3241 +//                printk("eth%d Flow Control Disable. \n",index);
3242 +            }
3243 +            flow_control_enable[index] = 0;
3244 +        }
3245 +
3246 +        if (pre_phy_status[index] == LINK_DOWN)
3247 +        {
3248 +            gmac_enable_tx_rx(dev);
3249 +            pre_phy_status[index] = LINK_UP;
3250 +                       set_bit(__LINK_STATE_START, &dev->state);
3251 +                       storlink_ctl.link = 1;
3252 +//                     printk("eth%d Link Up ...\n",index);
3253 +        }
3254 +    }
3255 +    else
3256 +    {
3257 +        status.bits.link = LINK_DOWN; /* link down */
3258 +        netif_stop_queue(dev);
3259 +        flow_control_enable[index] = 0;
3260 +        storlink_ctl.link = 0;
3261 +        if (pre_phy_status[index] == LINK_UP)
3262 +        {
3263 +            gmac_disable_tx_rx(dev);
3264 +            pre_phy_status[index] = LINK_DOWN;
3265 +                       clear_bit(__LINK_STATE_START, &dev->state);
3266 +//                     printk("eth%d Link Down ...\n",index);
3267 +       }
3268 +
3269 +    }
3270 +
3271 +    reg_val = gmac_read_reg(gmac_base_addr[index] + GMAC_STATUS);
3272 +    if (reg_val != status.bits32)
3273 +    {
3274 +        gmac_write_reg(gmac_base_addr[index] + GMAC_STATUS,status.bits32,0x0000007f);
3275 +    }
3276 +}
3277 +
3278 +/***************************************/
3279 +/* define GPIO module base address     */
3280 +/***************************************/
3281 +#define GPIO_BASE_ADDR  (IO_ADDRESS(SL2312_GPIO_BASE))
3282 +
3283 +/* define GPIO pin for MDC/MDIO */
3284 +
3285 +// for gemini ASIC
3286 +#ifdef CONFIG_SL3516_ASIC
3287 +#define H_MDC_PIN           22
3288 +#define H_MDIO_PIN          21
3289 +#define G_MDC_PIN           22
3290 +#define G_MDIO_PIN          21
3291 +#else
3292 +#define H_MDC_PIN           3
3293 +#define H_MDIO_PIN          2
3294 +#define G_MDC_PIN           0
3295 +#define G_MDIO_PIN          1
3296 +#endif
3297 +
3298 +//#define GPIO_MDC             0x80000000
3299 +//#define GPIO_MDIO            0x00400000
3300 +
3301 +static unsigned int GPIO_MDC = 0;
3302 +static unsigned int GPIO_MDIO = 0;
3303 +static unsigned int GPIO_MDC_PIN = 0;
3304 +static unsigned int GPIO_MDIO_PIN = 0;
3305 +
3306 +// For PHY test definition!!
3307 +#define LPC_EECK               0x02
3308 +#define LPC_EDIO               0x04
3309 +#define LPC_GPIO_SET           3
3310 +#define LPC_BASE_ADDR          IO_ADDRESS(IT8712_IO_BASE)
3311 +#define inb_gpio(x)            inb(LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
3312 +#define outb_gpio(x, y)                outb(y, LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
3313 +
3314 +enum GPIO_REG
3315 +{
3316 +    GPIO_DATA_OUT   = 0x00,
3317 +    GPIO_DATA_IN    = 0x04,
3318 +    GPIO_PIN_DIR    = 0x08,
3319 +    GPIO_BY_PASS    = 0x0c,
3320 +    GPIO_DATA_SET   = 0x10,
3321 +    GPIO_DATA_CLEAR = 0x14,
3322 +};
3323 +/***********************/
3324 +/*    MDC : GPIO[31]   */
3325 +/*    MDIO: GPIO[22]   */
3326 +/***********************/
3327 +
3328 +/***************************************************
3329 +* All the commands should have the frame structure:
3330 +*<PRE><ST><OP><PHYAD><REGAD><TA><DATA><IDLE>
3331 +****************************************************/
3332 +
3333 +/*****************************************************************
3334 +* Inject a bit to NWay register through CSR9_MDC,MDIO
3335 +*******************************************************************/
3336 +void mii_serial_write(char bit_MDO) // write data into mii PHY
3337 +{
3338 +#if 0 //def CONFIG_SL2312_LPC_IT8712
3339 +       unsigned char iomode,status;
3340 +
3341 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3342 +       iomode |= (LPC_EECK|LPC_EDIO) ;                         // Set EECK,EDIO,EECS output
3343 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
3344 +
3345 +       if(bit_MDO)
3346 +       {
3347 +               status = inb_gpio( LPC_GPIO_SET);
3348 +               status |= LPC_EDIO ;            //EDIO high
3349 +               outb_gpio(LPC_GPIO_SET, status);
3350 +       }
3351 +       else
3352 +       {
3353 +               status = inb_gpio( LPC_GPIO_SET);
3354 +               status &= ~(LPC_EDIO) ;         //EDIO low
3355 +               outb_gpio(LPC_GPIO_SET, status);
3356 +       }
3357 +
3358 +       status |= LPC_EECK ;            //EECK high
3359 +       outb_gpio(LPC_GPIO_SET, status);
3360 +
3361 +       status &= ~(LPC_EECK) ;         //EECK low
3362 +       outb_gpio(LPC_GPIO_SET, status);
3363 +
3364 +#else
3365 +    unsigned int addr;
3366 +    unsigned int value;
3367 +
3368 +    addr = GPIO_BASE_ADDR + GPIO_PIN_DIR;
3369 +    value = readl(addr) | GPIO_MDC | GPIO_MDIO; /* set MDC/MDIO Pin to output */
3370 +    writel(value,addr);
3371 +    if(bit_MDO)
3372 +    {
3373 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3374 +        writel(GPIO_MDIO,addr); /* set MDIO to 1 */
3375 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3376 +        writel(GPIO_MDC,addr); /* set MDC to 1 */
3377 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3378 +        writel(GPIO_MDC,addr); /* set MDC to 0 */
3379 +    }
3380 +    else
3381 +    {
3382 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3383 +        writel(GPIO_MDIO,addr); /* set MDIO to 0 */
3384 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3385 +        writel(GPIO_MDC,addr); /* set MDC to 1 */
3386 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3387 +        writel(GPIO_MDC,addr); /* set MDC to 0 */
3388 +    }
3389 +
3390 +#endif
3391 +}
3392 +
3393 +/**********************************************************************
3394 +* read a bit from NWay register through CSR9_MDC,MDIO
3395 +***********************************************************************/
3396 +unsigned int mii_serial_read(void) // read data from mii PHY
3397 +{
3398 +#if 0 //def CONFIG_SL2312_LPC_IT8712
3399 +       unsigned char iomode,status;
3400 +       unsigned int value ;
3401 +
3402 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3403 +       iomode &= ~(LPC_EDIO) ;         // Set EDIO input
3404 +       iomode |= (LPC_EECK) ;          // Set EECK,EECS output
3405 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
3406 +
3407 +       status = inb_gpio( LPC_GPIO_SET);
3408 +       status |= LPC_EECK ;            //EECK high
3409 +       outb_gpio(LPC_GPIO_SET, status);
3410 +
3411 +       status &= ~(LPC_EECK) ;         //EECK low
3412 +       outb_gpio(LPC_GPIO_SET, status);
3413 +
3414 +       value = inb_gpio( LPC_GPIO_SET);
3415 +
3416 +       value = value>>2 ;
3417 +       value &= 0x01;
3418 +
3419 +       return value ;
3420 +
3421 +#else
3422 +    unsigned int *addr;
3423 +    unsigned int value;
3424 +
3425 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_PIN_DIR);
3426 +    value = readl(addr) & ~GPIO_MDIO; //0xffbfffff;   /* set MDC to output and MDIO to input */
3427 +    writel(value,addr);
3428 +
3429 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_SET);
3430 +    writel(GPIO_MDC,addr); /* set MDC to 1 */
3431 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3432 +    writel(GPIO_MDC,addr); /* set MDC to 0 */
3433 +
3434 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_IN);
3435 +    value = readl(addr);
3436 +    value = (value & (1<<GPIO_MDIO_PIN)) >> GPIO_MDIO_PIN;
3437 +    return(value);
3438 +
3439 +#endif
3440 +}
3441 +
3442 +/***************************************
3443 +* preamble + ST
3444 +***************************************/
3445 +void mii_pre_st(void)
3446 +{
3447 +    unsigned char i;
3448 +
3449 +    for(i=0;i<32;i++) // PREAMBLE
3450 +        mii_serial_write(1);
3451 +    mii_serial_write(0); // ST
3452 +    mii_serial_write(1);
3453 +}
3454 +
3455 +
3456 +/******************************************
3457 +* Read MII register
3458 +* phyad -> physical address
3459 +* regad -> register address
3460 +***************************************** */
3461 +unsigned int mii_read(unsigned char phyad,unsigned char regad)
3462 +{
3463 +    unsigned int i,value;
3464 +    unsigned int bit;
3465 +
3466 +    if (phyad == GPHY_ADDR)
3467 +    {
3468 +        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
3469 +        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
3470 +    }
3471 +    else
3472 +    {
3473 +        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
3474 +        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
3475 +    }
3476 +    GPIO_MDC = (1<<GPIO_MDC_PIN);
3477 +    GPIO_MDIO = (1<<GPIO_MDIO_PIN);
3478 +
3479 +    mii_pre_st(); // PRE+ST
3480 +    mii_serial_write(1); // OP
3481 +    mii_serial_write(0);
3482 +
3483 +    for (i=0;i<5;i++) { // PHYAD
3484 +        bit= ((phyad>>(4-i)) & 0x01) ? 1 :0 ;
3485 +        mii_serial_write(bit);
3486 +    }
3487 +
3488 +    for (i=0;i<5;i++) { // REGAD
3489 +        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
3490 +        mii_serial_write(bit);
3491 +    }
3492 +
3493 +    mii_serial_read(); // TA_Z
3494 +//    if((bit=mii_serial_read()) !=0 ) // TA_0
3495 +//    {
3496 +//        return(0);
3497 +//    }
3498 +    value=0;
3499 +    for (i=0;i<16;i++) { // READ DATA
3500 +        bit=mii_serial_read();
3501 +        value += (bit<<(15-i)) ;
3502 +    }
3503 +
3504 +    mii_serial_write(0); // dumy clock
3505 +    mii_serial_write(0); // dumy clock
3506 +//printk("%s: phy_addr=%x reg_addr=%x value=%x \n",__func__,phyad,regad,value);
3507 +    return(value);
3508 +}
3509 +
3510 +/******************************************
3511 +* Write MII register
3512 +* phyad -> physical address
3513 +* regad -> register address
3514 +* value -> value to be write
3515 +***************************************** */
3516 +void mii_write(unsigned char phyad,unsigned char regad,unsigned int value)
3517 +{
3518 +    unsigned int i;
3519 +    char bit;
3520 +
3521 +printk("%s: phy_addr=%x reg_addr=%x value=%x \n",__func__,phyad,regad,value);
3522 +    if (phyad == GPHY_ADDR)
3523 +    {
3524 +        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
3525 +        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
3526 +    }
3527 +    else
3528 +    {
3529 +        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
3530 +        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
3531 +    }
3532 +    GPIO_MDC = (1<<GPIO_MDC_PIN);
3533 +    GPIO_MDIO = (1<<GPIO_MDIO_PIN);
3534 +
3535 +    mii_pre_st(); // PRE+ST
3536 +    mii_serial_write(0); // OP
3537 +    mii_serial_write(1);
3538 +    for (i=0;i<5;i++) { // PHYAD
3539 +        bit= ((phyad>>(4-i)) & 0x01) ? 1 :0 ;
3540 +        mii_serial_write(bit);
3541 +    }
3542 +
3543 +    for (i=0;i<5;i++) { // REGAD
3544 +        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
3545 +        mii_serial_write(bit);
3546 +    }
3547 +    mii_serial_write(1); // TA_1
3548 +    mii_serial_write(0); // TA_0
3549 +
3550 +    for (i=0;i<16;i++) { // OUT DATA
3551 +        bit= ((value>>(15-i)) & 0x01) ? 1 : 0 ;
3552 +        mii_serial_write(bit);
3553 +    }
3554 +    mii_serial_write(0); // dumy clock
3555 +    mii_serial_write(0); // dumy clock
3556 +}
3557 +
3558 +
3559 +
3560 +
3561 +
3562 +
3563 +
3564 +
3565 +
3566 +/*                             NOTES
3567 + *   The instruction set of the 93C66/56/46/26/06 chips are as follows:
3568 + *
3569 + *               Start  OP         *
3570 + *     Function   Bit  Code  Address**  Data     Description
3571 + *     -------------------------------------------------------------------
3572 + *     READ        1    10   A7 - A0             Reads data stored in memory,
3573 + *                                               starting at specified address
3574 + *     EWEN        1    00   11XXXXXX            Write enable must precede
3575 + *                                               all programming modes
3576 + *     ERASE       1    11   A7 - A0             Erase register A7A6A5A4A3A2A1A0
3577 + *     WRITE       1    01   A7 - A0   D15 - D0  Writes register
3578 + *     ERAL        1    00   10XXXXXX            Erase all registers
3579 + *     WRAL        1    00   01XXXXXX  D15 - D0  Writes to all registers
3580 + *     EWDS        1    00   00XXXXXX            Disables all programming
3581 + *                                               instructions
3582 + *    *Note: A value of X for address is a don't care condition.
3583 + *    **Note: There are 8 address bits for the 93C56/66 chips unlike
3584 + *           the 93C46/26/06 chips which have 6 address bits.
3585 + *
3586 + *   The 93Cx6 has a four wire interface: clock, chip select, data in, and
3587 + *   data out.While the ADM6996 uning three interface: clock, chip select,and data line.
3588 + *   The input and output are the same pin. ADM6996 can only recognize the write cmd.
3589 + *   In order to perform above functions, you need
3590 + *   1. to enable the chip select .
3591 + *   2. send one clock of dummy clock
3592 + *   3. send start bit and opcode
3593 + *   4. send 8 bits address and 16 bits data
3594 + *   5. to disable the chip select.
3595 + *                                                     Jason Lee 2003/07/30
3596 + */
3597 +
3598 +/***************************************/
3599 +/* define GPIO module base address     */
3600 +/***************************************/
3601 +#define GPIO_EECS           0x00400000         /*   EECS: GPIO[22]   */
3602 +//#define GPIO_MOSI         0x20000000         /*   EEDO: GPIO[29]   send to 6996*/
3603 +#define GPIO_MISO           0x40000000         /*   EEDI: GPIO[30]   receive from 6996*/
3604 +#define GPIO_EECK           0x80000000         /*   EECK: GPIO[31]   */
3605 +
3606 +#define ADM_EECS               0x01
3607 +#define ADM_EECK               0x02
3608 +#define ADM_EDIO               0x04
3609 +/*************************************************************
3610 +* SPI protocol for ADM6996 control
3611 +**************************************************************/
3612 +#define SPI_OP_LEN          0x03               // the length of start bit and opcode
3613 +#define SPI_OPWRITE         0X05               // write
3614 +#define SPI_OPREAD          0X06               // read
3615 +#define SPI_OPERASE         0X07               // erase
3616 +#define SPI_OPWTEN          0X04               // write enable
3617 +#define SPI_OPWTDIS         0X04               // write disable
3618 +#define SPI_OPERSALL        0X04               // erase all
3619 +#define SPI_OPWTALL         0X04               // write all
3620 +
3621 +#define SPI_ADD_LEN         8                  // bits of Address
3622 +#define SPI_DAT_LEN         16                 // bits of Data
3623 +#define ADM6996_PORT_NO             6                  // the port number of ADM6996
3624 +#define ADM6999_PORT_NO             9                  // the port number of ADM6999
3625 +#ifdef CONFIG_ADM_6996
3626 +       #define ADM699X_PORT_NO         ADM6996_PORT_NO
3627 +#endif
3628 +#ifdef CONFIG_ADM_6999
3629 +       #define ADM699X_PORT_NO         ADM6999_PORT_NO
3630 +#endif
3631 +#define LPC_GPIO_SET           3
3632 +#define LPC_BASE_ADDR                  IO_ADDRESS(IT8712_IO_BASE)
3633 +
3634 +extern int it8712_exist;
3635 +
3636 +#define inb_gpio(x)                    inb(LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
3637 +#define outb_gpio(x, y)                outb(y, LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
3638 +
3639 +/****************************************/
3640 +/*     Function Declare                */
3641 +/****************************************/
3642 +/*
3643 +void SPI_write(unsigned char addr,unsigned int value);
3644 +unsigned int SPI_read(unsigned char table,unsigned char addr);
3645 +void SPI_write_bit(char bit_EEDO);
3646 +unsigned int SPI_read_bit(void);
3647 +void SPI_default(void);
3648 +void SPI_reset(unsigned char rstype,unsigned char port_cnt);
3649 +void SPI_pre_st(void);
3650 +void SPI_CS_enable(unsigned char enable);
3651 +void SPI_Set_VLAN(unsigned char LAN,unsigned int port_mask);
3652 +void SPI_Set_tag(unsigned int port,unsigned tag);
3653 +void SPI_Set_PVID(unsigned int PVID,unsigned int port_mask);
3654 +void SPI_mac_lock(unsigned int port, unsigned char lock);
3655 +void SPI_get_port_state(unsigned int port);
3656 +void SPI_port_enable(unsigned int port,unsigned char enable);
3657 +
3658 +void SPI_get_status(unsigned int port);
3659 +*/
3660 +
3661 +struct PORT_CONFIG
3662 +{
3663 +       unsigned char auto_negotiation; // 0:Disable    1:Enable
3664 +       unsigned char speed;            // 0:10M        1:100M
3665 +       unsigned char duplex;           // 0:Half       1:Full duplex
3666 +       unsigned char Tag;              // 0:Untag      1:Tag
3667 +       unsigned char port_disable;     // 0:port enable        1:disable
3668 +       unsigned char pvid;             // port VLAN ID 0001
3669 +       unsigned char mdix;             // Crossover judgement. 0:Disable 1:Enable
3670 +       unsigned char mac_lock;         // MAC address Lock 0:Disable 1:Enable
3671 +};
3672 +
3673 +struct PORT_STATUS
3674 +{
3675 +       unsigned char link;             // 0:not link   1:link established
3676 +       unsigned char speed;            // 0:10M        1:100M
3677 +       unsigned char duplex;           // 0:Half       1:Full duplex
3678 +       unsigned char flow_ctl;         // 0:flow control disable 1:enable
3679 +       unsigned char mac_lock;         // MAC address Lock 0:Disable 1:Enable
3680 +       unsigned char port_disable;     // 0:port enable        1:disable
3681 +
3682 +       // Serial Management
3683 +       unsigned long rx_pac_count;             //receive packet count
3684 +       unsigned long rx_pac_byte;              //receive packet byte count
3685 +       unsigned long tx_pac_count;             //transmit packet count
3686 +       unsigned long tx_pac_byte;              //transmit packet byte count
3687 +       unsigned long collision_count;          //error count
3688 +       unsigned long error_count ;
3689 +
3690 +       unsigned long rx_pac_count_overflow;            //overflow flag
3691 +       unsigned long rx_pac_byte_overflow;
3692 +       unsigned long tx_pac_count_overflow;
3693 +       unsigned long tx_pac_byte_overflow;
3694 +       unsigned long collision_count_overflow;
3695 +       unsigned long error_count_overflow;
3696 +};
3697 +
3698 +struct PORT_CONFIG port_config[ADM699X_PORT_NO];       // 0~3:LAN , 4:WAN , 5:MII
3699 +static struct PORT_STATUS port_state[ADM699X_PORT_NO];
3700 +
3701 +/******************************************
3702 +* SPI_write
3703 +* addr -> Write Address
3704 +* value -> value to be write
3705 +***************************************** */
3706 +void SPI_write(unsigned char addr,unsigned int value)
3707 +{
3708 +       int     i;
3709 +       char    bit;
3710 +#ifdef CONFIG_IT8712_GPIO
3711 +       char    status;
3712 +#else
3713 +    int     ad1;
3714 +#endif
3715 +
3716 +#ifdef CONFIG_IT8712_GPIO
3717 +       status = inb_gpio(LPC_GPIO_SET);
3718 +       status &= ~(ADM_EDIO) ;         //EDIO low
3719 +       outb_gpio(LPC_GPIO_SET, status);
3720 +#else
3721 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3722 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
3723 +#endif
3724 +       SPI_CS_enable(1);
3725 +
3726 +       SPI_write_bit(0);       //dummy clock
3727 +
3728 +       //send write command (0x05)
3729 +       for(i=SPI_OP_LEN-1;i>=0;i--)
3730 +       {
3731 +               bit = (SPI_OPWRITE>>i)& 0x01;
3732 +               SPI_write_bit(bit);
3733 +       }
3734 +       // send 8 bits address (MSB first, LSB last)
3735 +       for(i=SPI_ADD_LEN-1;i>=0;i--)
3736 +       {
3737 +               bit = (addr>>i)& 0x01;
3738 +               SPI_write_bit(bit);
3739 +       }
3740 +       // send 16 bits data (MSB first, LSB last)
3741 +       for(i=SPI_DAT_LEN-1;i>=0;i--)
3742 +       {
3743 +               bit = (value>>i)& 0x01;
3744 +               SPI_write_bit(bit);
3745 +       }
3746 +
3747 +       SPI_CS_enable(0);       // CS low
3748 +
3749 +       for(i=0;i<0xFFF;i++) ;
3750 +#ifdef CONFIG_IT8712_GPIO
3751 +       status = inb_gpio(LPC_GPIO_SET);
3752 +       status &= ~(ADM_EDIO) ;         //EDIO low
3753 +       outb_gpio(LPC_GPIO_SET, status);
3754 +#else
3755 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3756 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
3757 +#endif
3758 +}
3759 +
3760 +
3761 +/************************************
3762 +* SPI_write_bit
3763 +* bit_EEDO -> 1 or 0 to be written
3764 +************************************/
3765 +void SPI_write_bit(char bit_EEDO)
3766 +{
3767 +#ifdef CONFIG_IT8712_GPIO
3768 +       unsigned char iomode,status;
3769 +
3770 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3771 +       iomode |= (ADM_EECK|ADM_EDIO|ADM_EECS) ;                                // Set EECK,EDIO,EECS output
3772 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
3773 +
3774 +       if(bit_EEDO)
3775 +       {
3776 +               status = inb_gpio( LPC_GPIO_SET);
3777 +               status |= ADM_EDIO ;            //EDIO high
3778 +               outb_gpio(LPC_GPIO_SET, status);
3779 +       }
3780 +       else
3781 +       {
3782 +               status = inb_gpio( LPC_GPIO_SET);
3783 +               status &= ~(ADM_EDIO) ;         //EDIO low
3784 +               outb_gpio(LPC_GPIO_SET, status);
3785 +       }
3786 +
3787 +       status |= ADM_EECK ;            //EECK high
3788 +       outb_gpio(LPC_GPIO_SET, status);
3789 +
3790 +       status &= ~(ADM_EECK) ;         //EECK low
3791 +       outb_gpio(LPC_GPIO_SET, status);
3792 +
3793 +#else
3794 +       unsigned int addr;
3795 +       unsigned int value;
3796 +
3797 +       addr = (GPIO_BASE_ADDR + GPIO_PIN_DIR);
3798 +       value = readl(addr) |GPIO_EECK |GPIO_MISO ;   /* set EECK/MISO Pin to output */
3799 +       writel(value,addr);
3800 +       if(bit_EEDO)
3801 +       {
3802 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3803 +               writel(GPIO_MISO,addr); /* set MISO to 1 */
3804 +               writel(GPIO_EECK,addr); /* set EECK to 1 */
3805 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3806 +               writel(GPIO_EECK,addr); /* set EECK to 0 */
3807 +       }
3808 +       else
3809 +       {
3810 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3811 +               writel(GPIO_MISO,addr); /* set MISO to 0 */
3812 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
3813 +               writel(GPIO_EECK,addr); /* set EECK to 1 */
3814 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3815 +               writel(GPIO_EECK,addr); /* set EECK to 0 */
3816 +       }
3817 +
3818 +       return ;
3819 +#endif
3820 +}
3821 +
3822 +/**********************************************************************
3823 +* read a bit from ADM6996 register
3824 +***********************************************************************/
3825 +unsigned int SPI_read_bit(void) // read data from
3826 +{
3827 +#ifdef CONFIG_IT8712_GPIO
3828 +       unsigned char iomode,status;
3829 +       unsigned int value ;
3830 +
3831 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3832 +       iomode &= ~(ADM_EDIO) ;         // Set EDIO input
3833 +       iomode |= (ADM_EECS|ADM_EECK) ;         // Set EECK,EECS output
3834 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
3835 +
3836 +       status = inb_gpio( LPC_GPIO_SET);
3837 +       status |= ADM_EECK ;            //EECK high
3838 +       outb_gpio(LPC_GPIO_SET, status);
3839 +
3840 +       status &= ~(ADM_EECK) ;         //EECK low
3841 +       outb_gpio(LPC_GPIO_SET, status);
3842 +
3843 +       value = inb_gpio( LPC_GPIO_SET);
3844 +
3845 +       value = value>>2 ;
3846 +       value &= 0x01;
3847 +
3848 +       return value ;
3849 +#else
3850 +       unsigned int addr;
3851 +       unsigned int value;
3852 +
3853 +       addr = (GPIO_BASE_ADDR + GPIO_PIN_DIR);
3854 +       value = readl(addr) & (~GPIO_MISO);   // set EECK to output and MISO to input
3855 +       writel(value,addr);
3856 +
3857 +       addr =(GPIO_BASE_ADDR + GPIO_DATA_SET);
3858 +       writel(GPIO_EECK,addr); // set EECK to 1
3859 +       addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3860 +       writel(GPIO_EECK,addr); // set EECK to 0
3861 +
3862 +       addr = (GPIO_BASE_ADDR + GPIO_DATA_IN);
3863 +       value = readl(addr) ;
3864 +       value = value >> 30;
3865 +       return value ;
3866 +#endif
3867 +}
3868 +
3869 +/******************************************
3870 +* SPI_default
3871 +* EEPROM content default value
3872 +*******************************************/
3873 +void SPI_default(void)
3874 +{
3875 +       int i;
3876 +#ifdef CONFIG_ADM_6999
3877 +       SPI_write(0x11,0xFF30);
3878 +       for(i=1;i<8;i++)
3879 +               SPI_write(i,0x840F);
3880 +
3881 +       SPI_write(0x08,0x880F);                 //port 8 Untag, PVID=2
3882 +       SPI_write(0x09,0x881D);                 //port 9 Tag, PVID=2 ,10M
3883 +       SPI_write(0x14,0x017F);                 //Group 0~6,8 as VLAN 1
3884 +       SPI_write(0x15,0x0180);                 //Group 7,8 as VLAN 2
3885 +#endif
3886 +
3887 +#ifdef CONFIG_ADM_6996
3888 +       SPI_write(0x11,0xFF30);
3889 +       SPI_write(0x01,0x840F);                 //port 0~3 Untag ,PVID=1 ,100M ,duplex
3890 +       SPI_write(0x03,0x840F);
3891 +       SPI_write(0x05,0x840F);
3892 +       SPI_write(0x07,0x840F);
3893 +       SPI_write(0x08,0x880F);                 //port 4 Untag, PVID=2
3894 +       SPI_write(0x09,0x881D);                 //port 5 Tag, PVID=2 ,10M
3895 +       SPI_write(0x14,0x0155);                 //Group 0~3,5 as VLAN 1
3896 +       SPI_write(0x15,0x0180);                 //Group 4,5 as VLAN 2
3897 +
3898 +#endif
3899 +
3900 +       for(i=0x16;i<=0x22;i++)
3901 +               SPI_write((unsigned char)i,0x0000);             // clean VLAN¡@map 3~15
3902 +
3903 +       for (i=0;i<NUM_VLAN_IF;i++)                             // Set VLAN ID map 1,2
3904 +               SPI_Set_PVID( VLAN_conf[i].vid,  VLAN_conf[i].portmap);
3905 +
3906 +       for(i=0;i<ADM699X_PORT_NO;i++)                          // reset count
3907 +               SPI_reset(0,i);
3908 +}
3909 +
3910 +/*************************************************
3911 +* SPI_reset
3912 +* rstype -> reset type
3913 +*          0:reset all count for 'port_cnt' port
3914 +*          1:reset specified count 'port_cnt'
3915 +* port_cnt   ->  port number or counter index
3916 +***************************************************/
3917 +void SPI_reset(unsigned char rstype,unsigned char port_cnt)
3918 +{
3919 +
3920 +       int i;
3921 +#ifdef CONFIG_IT8712_GPIO
3922 +    char status;
3923 +#else
3924 +       int ad1;
3925 +#endif
3926 +       char bit;
3927 +
3928 +#ifdef CONFIG_IT8712_GPIO
3929 +       status = inb_gpio(LPC_GPIO_SET);
3930 +       status &= ~(ADM_EDIO) ;         //EDIO low
3931 +       outb_gpio(LPC_GPIO_SET, status);
3932 +#else
3933 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3934 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
3935 +#endif
3936 +
3937 +       SPI_CS_enable(0);       // CS low
3938 +
3939 +       SPI_pre_st(); // PRE+ST
3940 +       SPI_write_bit(0); // OP
3941 +       SPI_write_bit(1);
3942 +
3943 +       SPI_write_bit(1);               // Table select, must be 1 -> reset Counter
3944 +
3945 +       SPI_write_bit(0);               // Device Address
3946 +       SPI_write_bit(0);
3947 +
3948 +       rstype &= 0x01;
3949 +       SPI_write_bit(rstype);          // Reset type 0:clear dedicate port's all counters 1:clear dedicate counter
3950 +
3951 +       for (i=5;i>=0;i--)              // port or cnt index
3952 +       {
3953 +               bit = port_cnt >> i ;
3954 +               bit &= 0x01 ;
3955 +               SPI_write_bit(bit);
3956 +       }
3957 +
3958 +       SPI_write_bit(0);               // dumy clock
3959 +       SPI_write_bit(0);               // dumy clock
3960 +
3961 +#ifdef CONFIG_IT8712_GPIO
3962 +       status = inb_gpio(LPC_GPIO_SET);
3963 +       status &= ~(ADM_EDIO) ;         //EDIO low
3964 +       outb_gpio(LPC_GPIO_SET, status);
3965 +#else
3966 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
3967 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
3968 +#endif
3969 +}
3970 +
3971 +/*****************************************************
3972 +* SPI_pre_st
3973 +* preambler: 32 bits '1'   start bit: '01'
3974 +*****************************************************/
3975 +void SPI_pre_st(void)
3976 +{
3977 +       int i;
3978 +
3979 +       for(i=0;i<32;i++) // PREAMBLE
3980 +               SPI_write_bit(1);
3981 +       SPI_write_bit(0); // ST
3982 +       SPI_write_bit(1);
3983 +}
3984 +
3985 +
3986 +/***********************************************************
3987 +* SPI_CS_enable
3988 +* before access ,you have to enable Chip Select. (pull high)
3989 +* When fisish, you should pull low !!
3990 +*************************************************************/
3991 +void SPI_CS_enable(unsigned char enable)
3992 +{
3993 +#ifdef CONFIG_IT8712_GPIO
3994 +
3995 +       unsigned char iomode,status;
3996 +
3997 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
3998 +       iomode |= (ADM_EECK|ADM_EDIO|ADM_EECS) ;                                // Set EECK,EDIO,EECS output
3999 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
4000 +
4001 +
4002 +       status = inb_gpio( LPC_GPIO_SET);
4003 +       if(enable)
4004 +               status |= ADM_EECS ;            //EECS high
4005 +       else
4006 +               status &= ~(ADM_EECS) ; //EECS low
4007 +
4008 +       outb_gpio(LPC_GPIO_SET, status);
4009 +
4010 +
4011 +       status |= ADM_EECK ;            //EECK high
4012 +       outb_gpio(LPC_GPIO_SET, status);
4013 +
4014 +       status &= ~(ADM_EECK) ;         //EECK low
4015 +       outb_gpio(LPC_GPIO_SET, status);
4016 +
4017 +#else
4018 +       unsigned int addr,value;
4019 +
4020 +       addr = (GPIO_BASE_ADDR + GPIO_PIN_DIR);
4021 +       value = readl(addr) |GPIO_EECS |GPIO_EECK;   /* set EECS/EECK Pin to output */
4022 +       writel(value,addr);
4023 +
4024 +       if(enable)
4025 +       {
4026 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
4027 +               writel(GPIO_EECS,addr); /* set EECS to 1 */
4028 +
4029 +       }
4030 +       else
4031 +       {
4032 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
4033 +               writel(GPIO_EECS,addr); /* set EECS to 0 */
4034 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
4035 +               writel(GPIO_EECK,addr); /* set EECK to 1 */     // at least one clock after CS low
4036 +               addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
4037 +               writel(GPIO_EECK,addr); /* set EECK to 0 */
4038 +       }
4039 +#endif
4040 +}
4041 +
4042 +/*********************************************************
4043 +* SPI_Set_VLAN: group ports as VLAN
4044 +* LAN  -> VLAN number : 0~16
4045 +* port_mask -> ports which would group as LAN
4046 +*             ex. 0x03 = 0000 0011
4047 +*                      port 0 and port 1
4048 +*********************************************************/
4049 +void SPI_Set_VLAN(unsigned char LAN,unsigned int port_mask)
4050 +{
4051 +       unsigned int i,value=0;
4052 +       unsigned reg_add = 0x13 + LAN ;
4053 +
4054 +       for(i=0;i<ADM6996_PORT_NO;i++)
4055 +       {       if(port_mask&0x01)
4056 +               {
4057 +                       switch(i)
4058 +                       {
4059 +                               case 0: value|=0x0001;  break;  //port0:bit[0]
4060 +                               case 1: value|=0x0004;  break;  //port1:bit[2]
4061 +                               case 2: value|=0x0010;  break;  //port2:bit[4]
4062 +                               case 3: value|=0x0040;  break;  //port3:bit[6]
4063 +                               case 4: value|=0x0080;  break;  //port4:bit[7]
4064 +                               case 5: value|=0x0100;  break;  //port5:bit[8]
4065 +                       }
4066 +               }
4067 +               port_mask >>= 1;
4068 +       }
4069 +
4070 +       SPI_write(reg_add,value);
4071 +}
4072 +
4073 +
4074 +/*******************************************
4075 +* SPI_Set_tag
4076 +* port -> port number to set tag or untag
4077 +* tag  -> 0/set untag,  1/set tag
4078 +* In general, tag is for MII port. LAN and
4079 +* WAN port is configed as untag!!
4080 +********************************************/
4081 +void SPI_Set_tag(unsigned int port,unsigned tag)
4082 +{
4083 +       unsigned int regadd,value;
4084 +
4085 +       // mapping port's register !! (0,1,2,3,4,5) ==> (1,3,5,7,8,9)
4086 +       if(port<=3)
4087 +               regadd=2*port+1;
4088 +       else if(port==4) regadd = 8 ;
4089 +       else regadd = 9 ;
4090 +
4091 +
4092 +       value = SPI_read(0,regadd);             //read original setting
4093 +
4094 +       if(tag)
4095 +               value |= 0x0010 ;               // set tag
4096 +       else
4097 +               value &= 0xFFEF ;               // set untag
4098 +
4099 +       SPI_write(regadd,value);                // write back!!
4100 +}
4101 +
4102 +/************************************************
4103 +* SPI_Set_PVID
4104 +* PVID -> PVID number :
4105 +* port_mask -> ports which would group as LAN
4106 +*             ex. 0x0F = 0000 1111 ==> port 0~3
4107 +************************************************/
4108 +void SPI_Set_PVID(unsigned int PVID,unsigned int port_mask)
4109 +{
4110 +       unsigned int i,value=0;
4111 +
4112 +       PVID &= 0x000F ;
4113 +
4114 +       for(i=0;i<ADM699X_PORT_NO;i++)
4115 +       {       if(port_mask&0x01)
4116 +               {
4117 +#ifdef CONFIG_ADM_6996
4118 +                       switch(i)
4119 +                       {
4120 +                               case 0:
4121 +                                       value = SPI_read(0,0x01);       // read original value
4122 +                                       value &= 0xC3FF ;                       //set PVIC column as 0 first
4123 +                                       value |= PVID << 10 ;           //Set PVID column as PVID
4124 +                                       SPI_write(0x01,value);          //write back
4125 +                                       break;
4126 +                               case 1:
4127 +                                       value = SPI_read(0,0x03);
4128 +                                       value &= 0xC3FF ;
4129 +                                       value |= PVID << 10 ;
4130 +                                       SPI_write(0x03,value);
4131 +                                       break;
4132 +                               case 2:
4133 +                                       value = SPI_read(0,0x05);
4134 +                                       value &= 0xC3FF ;
4135 +                                       value |= PVID << 10 ;
4136 +                                       SPI_write(0x05,value);
4137 +                                       break;
4138 +                               case 3:
4139 +                                       value = SPI_read(0,0x07);
4140 +                                       value &= 0xC3FF ;
4141 +                                       value |= PVID << 10 ;
4142 +                                       SPI_write(0x07,value);
4143 +                                       break;
4144 +                               case 4:
4145 +                                       value = SPI_read(0,0x08);
4146 +                                       value &= 0xC3FF ;
4147 +                                       value |= PVID << 10 ;
4148 +                                       SPI_write(0x08,value);
4149 +                                       break;
4150 +                               case 5:
4151 +                                       value = SPI_read(0,0x09);
4152 +                                       value &= 0xC3FF ;
4153 +                                       value |= PVID << 10 ;
4154 +                                       SPI_write(0x09,value);
4155 +                                       break;
4156 +                       }
4157 +#endif
4158 +#ifdef CONFIG_ADM_6999
4159 +                       value = SPI_read(0,(unsigned char)i+1);
4160 +                       value &= 0xC3FF ;
4161 +                       value |= PVID << 10 ;
4162 +                       SPI_write((unsigned char)i+1,value);
4163 +#endif
4164 +               }
4165 +               port_mask >>= 1;
4166 +       }
4167 +}
4168 +
4169 +
4170 +/************************************************
4171 +* SPI_get_PVID
4172 +* port -> which ports to VID
4173 +************************************************/
4174 +unsigned int SPI_Get_PVID(unsigned int port)
4175 +{
4176 +       unsigned int value=0;
4177 +
4178 +       if (port>=ADM6996_PORT_NO)
4179 +               return 0;
4180 +
4181 +       switch(port)
4182 +       {
4183 +               case 0:
4184 +                       value = SPI_read(0,0x01);       // read original value
4185 +                       value &= 0x3C00 ;               // get VID
4186 +                       value = value >> 10 ;           // Shift
4187 +                       break;
4188 +               case 1:
4189 +                       value = SPI_read(0,0x03);
4190 +                       value &= 0x3C00 ;
4191 +                       value = value >> 10 ;
4192 +                       break;
4193 +               case 2:
4194 +                       value = SPI_read(0,0x05);
4195 +                       value &= 0x3C00 ;
4196 +                       value = value >> 10 ;
4197 +                       break;
4198 +               case 3:
4199 +                       value = SPI_read(0,0x07);
4200 +                       value &= 0x3C00 ;
4201 +                       value = value >> 10 ;
4202 +                       break;
4203 +               case 4:
4204 +                       value = SPI_read(0,0x08);
4205 +                       value &= 0x3C00 ;
4206 +                       value = value >> 10 ;
4207 +                       break;
4208 +               case 5:
4209 +                       value = SPI_read(0,0x09);
4210 +                       value &= 0x3C00 ;
4211 +                       value = value >> 10 ;
4212 +                       break;
4213 +       }
4214 +       return value ;
4215 +}
4216 +
4217 +
4218 +/**********************************************
4219 +* SPI_mac_clone
4220 +* port -> the port which will lock or unlock
4221 +* lock -> 0/the port will be unlock
4222 +*        1/the port will be locked
4223 +**********************************************/
4224 +void SPI_mac_lock(unsigned int port, unsigned char lock)
4225 +{
4226 +       unsigned int i,value=0;
4227 +
4228 +       value = SPI_read(0,0x12);               // read original
4229 +
4230 +       for(i=0;i<ADM6996_PORT_NO;i++)
4231 +       {       if(lock)                                // lock port
4232 +               {
4233 +                       switch(port)
4234 +                       {
4235 +                               case 0: value|=0x0001;  break;  //port0:bit[0]
4236 +                               case 1: value|=0x0004;  break;  //port1:bit[2]
4237 +                               case 2: value|=0x0010;  break;  //port2:bit[4]
4238 +                               case 3: value|=0x0040;  break;  //port3:bit[6]
4239 +                               case 4: value|=0x0080;  break;  //port4:bit[7]
4240 +                               case 5: value|=0x0100;  break;  //port5:bit[8]
4241 +                       }
4242 +               }
4243 +               else
4244 +               {
4245 +                       switch(i)                       // unlock port
4246 +                       {
4247 +                               case 0: value&=0xFFFE;  break;
4248 +                               case 1: value&=0xFFFB;  break;
4249 +                               case 2: value&=0xFFEF;  break;
4250 +                               case 3: value&=0xFFBF;  break;
4251 +                               case 4: value&=0xFF7F;  break;
4252 +                               case 5: value&=0xFEFF;  break;
4253 +                       }
4254 +               }
4255 +       }
4256 +
4257 +       SPI_write(0x12,value);
4258 +}
4259 +
4260 +
4261 +/***************************************************
4262 +* SPI_learn_pause
4263 +* pause = 01-80-c2-00-00-01
4264 +* DA=distination address
4265 +* forward -> 0: if DA == pause then drop and stop mac learning
4266 +*           1: if DA == pause ,then forward it
4267 +***************************************************/
4268 +void SPI_pause_cmd_forward(unsigned char forward)
4269 +{
4270 +       unsigned int value=0;
4271 +
4272 +       value = SPI_read(0,0x2C);               // read original setting
4273 +       if(forward)
4274 +               value |= 0x2000;                // set bit[13] '1'
4275 +       else
4276 +               value &= 0xDFFF;                // set bit[13] '0'
4277 +
4278 +       SPI_write(0x2C,value);
4279 +
4280 +}
4281 +
4282 +
4283 +/************************************************
4284 +* SPI_read
4285 +* table -> which table to be read: 1/count  0/EEPROM
4286 +* addr  -> Address to be read
4287 +* return : Value of the register
4288 +*************************************************/
4289 +unsigned int SPI_read(unsigned char table,unsigned char addr)
4290 +{
4291 +       int i ;
4292 +       unsigned int value=0;
4293 +       unsigned int bit;
4294 +#ifdef CONFIG_IT8712_GPIO
4295 +       unsigned char status;
4296 +#else
4297 +    unsigned int ad1;
4298 +#endif
4299 +
4300 +#ifdef CONFIG_IT8712_GPIO
4301 +       status = inb_gpio(LPC_GPIO_SET);
4302 +       status &= ~(ADM_EDIO) ;         //EDIO low
4303 +       outb_gpio(LPC_GPIO_SET, status);
4304 +#else
4305 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
4306 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
4307 +#endif
4308 +
4309 +       SPI_CS_enable(0);
4310 +
4311 +       SPI_pre_st(); // PRE+ST
4312 +       SPI_write_bit(1); // OPCODE '10' for read
4313 +       SPI_write_bit(0);
4314 +
4315 +       (table==1) ? SPI_write_bit(1) : SPI_write_bit(0) ;      // table select
4316 +
4317 +       SPI_write_bit(0);               // Device Address
4318 +       SPI_write_bit(0);
4319 +
4320 +
4321 +       // send 7 bits address to be read
4322 +       for (i=6;i>=0;i--) {
4323 +               bit= ((addr>>i) & 0x01) ? 1 :0 ;
4324 +               SPI_write_bit(bit);
4325 +       }
4326 +
4327 +
4328 +       // turn around
4329 +       SPI_read_bit(); // TA_Z
4330 +
4331 +       value=0;
4332 +       for (i=31;i>=0;i--) { // READ DATA
4333 +               bit=SPI_read_bit();
4334 +               value |= bit << i ;
4335 +       }
4336 +
4337 +       SPI_read_bit(); // dumy clock
4338 +       SPI_read_bit(); // dumy clock
4339 +
4340 +       if(!table)                                      // EEPROM, only fetch 16 bits data
4341 +       {
4342 +           if(addr&0x01)                               // odd number content (register,register-1)
4343 +                   value >>= 16 ;                      // so we remove the rear 16bits
4344 +           else                                        // even number content (register+1,register),
4345 +                   value &= 0x0000FFFF ;               // so we keep the rear 16 bits
4346 +       }
4347 +
4348 +
4349 +       SPI_CS_enable(0);
4350 +
4351 +#ifdef CONFIG_IT8712_GPIO
4352 +       status = inb_gpio(LPC_GPIO_SET);
4353 +       status &= ~(ADM_EDIO) ;         //EDIO low
4354 +       outb_gpio(LPC_GPIO_SET, status);
4355 +#else
4356 +       ad1 = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
4357 +       writel(GPIO_MISO,ad1); /* set MISO to 0 */
4358 +#endif
4359 +
4360 +       return(value);
4361 +
4362 +}
4363 +
4364 +
4365 +
4366 +/**************************************************
4367 +* SPI_port_en
4368 +* port -> Number of port to config
4369 +* enable -> 1/ enable this port
4370 +*          0/ disable this port
4371 +**************************************************/
4372 +void SPI_port_enable(unsigned int port,unsigned char enable)
4373 +{
4374 +       unsigned int reg_val ;
4375 +       unsigned char reg_add ;
4376 +
4377 +       if(port<=3)
4378 +               reg_add=2*port+1;
4379 +       else if(port==4) reg_add = 8 ;
4380 +       else reg_add = 9 ;
4381 +
4382 +       reg_val = SPI_read(0,reg_add);
4383 +       if(enable)
4384 +       {
4385 +               reg_val &= 0xFFDF ;
4386 +               SPI_write(reg_add,reg_val);
4387 +       }
4388 +       else
4389 +       {
4390 +               reg_val |= 0x0020 ;
4391 +               SPI_write(reg_add,reg_val);
4392 +       }
4393 +}
4394 +
4395 +/********************************************************
4396 +* get port status
4397 +* port -> specify the port number to get configuration
4398 +*********************************************************/
4399 +void SPI_get_status(unsigned int port)
4400 +{
4401 +/*     unsigned int reg_val,add_offset[6];
4402 +       struct PORT_STATUS *status;
4403 +       status = &port_state[port];
4404 +
4405 +       if(port>(ADM6996_PORT_NO-1))
4406 +               return ;
4407 +
4408 +       // Link estabilish , speed, deplex, flow control ?
4409 +       if(port < 5 )
4410 +       {
4411 +               reg_val = SPI_read(1, 1) ;
4412 +               if(port < 4)
4413 +                       reg_val >>= port*8 ;
4414 +               else
4415 +                       reg_val >>=28 ;
4416 +               status->link = reg_val & 0x00000001 ;
4417 +               status->speed = reg_val  & 0x00000002 ;
4418 +               status->duplex = reg_val & 0x00000004 ;
4419 +               status->flow_ctl = reg_val & 0x00000008 ;
4420 +       }
4421 +       else if(port ==5 )
4422 +       {
4423 +               reg_val = SPI_read(1, 2) ;
4424 +               status->link = reg_val & 0x00000001 ;
4425 +               status->speed = reg_val  & 0x00000002 ;
4426 +               status->duplex = reg_val & 0x00000008 ;
4427 +               status->flow_ctl = reg_val & 0x00000010 ;
4428 +       }
4429 +
4430 +       //   Mac Lock ?
4431 +       reg_val = SPI_read(0,0x12);
4432 +       switch(port)
4433 +       {
4434 +               case 0: status->mac_lock = reg_val & 0x00000001;
4435 +               case 1: status->mac_lock = reg_val & 0x00000004;
4436 +               case 2: status->mac_lock = reg_val & 0x00000010;
4437 +               case 3: status->mac_lock = reg_val & 0x00000040;
4438 +               case 4: status->mac_lock = reg_val & 0x00000080;
4439 +               case 5: status->mac_lock = reg_val & 0x00000100;
4440 +       }
4441 +
4442 +       // port enable ?
4443 +       add_offset[0] = 0x01 ;          add_offset[1] = 0x03 ;
4444 +       add_offset[2] = 0x05 ;          add_offset[3] = 0x07 ;
4445 +       add_offset[4] = 0x08 ;          add_offset[5] = 0x09 ;
4446 +       reg_val = SPI_read(0,add_offset[port]);
4447 +       status->port_disable = reg_val & 0x0020;
4448 +
4449 +
4450 +       //  Packet Count ...
4451 +       add_offset[0] = 0x04 ;          add_offset[1] = 0x06 ;
4452 +       add_offset[2] = 0x08 ;          add_offset[3] = 0x0a ;
4453 +       add_offset[4] = 0x0b ;          add_offset[5] = 0x0c ;
4454 +
4455 +       reg_val = SPI_read(1,add_offset[port]);
4456 +       status->rx_pac_count = reg_val ;
4457 +       reg_val = SPI_read(1,add_offset[port]+9);
4458 +       status->rx_pac_byte = reg_val ;
4459 +       reg_val = SPI_read(1,add_offset[port]+18);
4460 +       status->tx_pac_count = reg_val ;
4461 +       reg_val = SPI_read(1,add_offset[port]+27);
4462 +       status->tx_pac_byte = reg_val ;
4463 +       reg_val = SPI_read(1,add_offset[port]+36);
4464 +       status->collision_count = reg_val ;
4465 +       reg_val = SPI_read(1,add_offset[port]+45);
4466 +       status->error_count = reg_val ;
4467 +       reg_val = SPI_read(1, 0x3A);
4468 +       switch(port)
4469 +       {
4470 +               case 0: status->rx_pac_count_overflow = reg_val & 0x00000001;
4471 +                       status->rx_pac_byte_overflow = reg_val & 0x00000200 ;
4472 +               case 1: status->rx_pac_count_overflow = reg_val & 0x00000004;
4473 +                       status->rx_pac_byte_overflow = reg_val & 0x00000800 ;
4474 +               case 2: status->rx_pac_count_overflow = reg_val & 0x00000010;
4475 +                       status->rx_pac_byte_overflow = reg_val & 0x00002000 ;
4476 +               case 3: status->rx_pac_count_overflow = reg_val & 0x00000040;;
4477 +                       status->rx_pac_byte_overflow = reg_val & 0x00008000 ;
4478 +               case 4: status->rx_pac_count_overflow = reg_val & 0x00000080;
4479 +                       status->rx_pac_byte_overflow = reg_val & 0x00010000 ;
4480 +               case 5: status->rx_pac_count_overflow = reg_val & 0x00000100;
4481 +                       status->rx_pac_byte_overflow = reg_val & 0x00020000 ;
4482 +       }
4483 +
4484 +       reg_val = SPI_read(1, 0x3B);
4485 +       switch(port)
4486 +       {
4487 +               case 0: status->tx_pac_count_overflow = reg_val & 0x00000001;
4488 +                       status->tx_pac_byte_overflow  = reg_val & 0x00000200 ;
4489 +               case 1: status->tx_pac_count_overflow  = reg_val & 0x00000004;
4490 +                       status->tx_pac_byte_overflow  = reg_val & 0x00000800 ;
4491 +               case 2: status->tx_pac_count_overflow  = reg_val & 0x00000010;
4492 +                       status->tx_pac_byte_overflow  = reg_val & 0x00002000 ;
4493 +               case 3: status->tx_pac_count_overflow  = reg_val & 0x00000040;;
4494 +                       status->tx_pac_byte_overflow  = reg_val & 0x00008000 ;
4495 +               case 4: status->tx_pac_count_overflow  = reg_val & 0x00000080;
4496 +                       status->tx_pac_byte_overflow  = reg_val & 0x00010000 ;
4497 +               case 5: status->tx_pac_count_overflow  = reg_val & 0x00000100;
4498 +                       status->tx_pac_byte_overflow  = reg_val & 0x00020000 ;
4499 +       }
4500 +*/
4501 +
4502 +       unsigned int reg_val;
4503 +       struct PORT_STATUS *status;
4504 +       status = &port_state[port];
4505 +
4506 +       if(port>=ADM6999_PORT_NO)
4507 +               return ;
4508 +
4509 +       // Link estabilish , speed, deplex, flow control ?
4510 +       if(port < ADM6999_PORT_NO-1 )
4511 +       {
4512 +               reg_val = SPI_read(1, 0x01) ;
4513 +               reg_val = reg_val >> port*4 ;
4514 +               status->link = reg_val & 0x00000001 ;
4515 +               status->speed = reg_val  & 0x00000002 ;
4516 +               status->duplex = reg_val & 0x00000004 ;
4517 +               status->flow_ctl = reg_val & 0x00000008 ;
4518 +       }
4519 +       else if(port == (ADM6999_PORT_NO-1) )
4520 +       {
4521 +               reg_val = SPI_read(1, 0x02) ;
4522 +               status->link = reg_val & 0x00000001 ;
4523 +               status->speed = reg_val  & 0x00000002 ;
4524 +               status->duplex = reg_val & 0x00000008 ;
4525 +               status->flow_ctl = reg_val & 0x00000010 ;
4526 +       }
4527 +
4528 +       // Mac Lock ?
4529 +       reg_val = SPI_read(0,0x12);
4530 +       reg_val = reg_val >> port ;
4531 +       reg_val = reg_val & 0x01 ;
4532 +       status->mac_lock = reg_val ? 0x01:0x00 ;
4533 +
4534 +       // port enable ?
4535 +       reg_val = SPI_read(0,(unsigned char)port+1);
4536 +       status->port_disable = reg_val & 0x0020;
4537 +
4538 +       //  Packet Count ...
4539 +       reg_val = SPI_read(1,(unsigned char)port+0x04);
4540 +       status->rx_pac_count = reg_val ;
4541 +       reg_val = SPI_read(1,(unsigned char)port+0x0D);
4542 +       status->rx_pac_byte = reg_val ;
4543 +       reg_val = SPI_read(1,(unsigned char)port+0x16);
4544 +       status->tx_pac_count = reg_val ;
4545 +       reg_val = SPI_read(1,(unsigned char)port+0x1F);
4546 +       status->tx_pac_byte = reg_val ;
4547 +       reg_val = SPI_read(1,(unsigned char)port+0x28);
4548 +       status->collision_count = reg_val ;
4549 +       reg_val = SPI_read(1,(unsigned char)port+0x31);
4550 +       status->error_count = reg_val ;
4551 +       reg_val = SPI_read(1, 0x3A);
4552 +       reg_val = reg_val >> port ;
4553 +       status->rx_pac_count_overflow = reg_val & 0x00000001;
4554 +       reg_val = reg_val >> 0x09 ;
4555 +       status->rx_pac_byte_overflow = reg_val & 0x00000001 ;
4556 +
4557 +       reg_val = SPI_read(1, 0x3B);
4558 +       reg_val = reg_val >> port ;
4559 +       status->tx_pac_count_overflow = reg_val & 0x00000001;
4560 +       reg_val = reg_val >> 0x09 ;
4561 +       status->tx_pac_byte_overflow  = reg_val & 0x00000001 ;
4562 +
4563 +       reg_val = SPI_read(1, 0x3C);
4564 +       reg_val = reg_val >> port ;
4565 +       status->collision_count_overflow = reg_val & 0x00000001;
4566 +       reg_val = reg_val >> 0x09 ;
4567 +       status->error_count_overflow  = reg_val & 0x00000001 ;
4568 +
4569 +}
4570 +
4571 +unsigned int SPI_get_identifier(void)
4572 +{
4573 +       unsigned int flag=0;
4574 +
4575 +#ifdef CONFIG_IT8712_GPIO
4576 +
4577 +       if (!it8712_exist) {
4578 +               return -ENODEV;
4579 +       }
4580 +       printk("it8712_gpio init\n");
4581 +
4582 +       /* initialize registers */
4583 +       // switch all multi-function pins to GPIO
4584 +       LPCSetConfig(LDN_GPIO, 0x28, 0xff);
4585 +
4586 +       // set simple I/O base address
4587 +       LPCSetConfig(LDN_GPIO, 0x62, IT8712_GPIO_BASE >> 8);
4588 +       LPCSetConfig(LDN_GPIO, 0x63, (unsigned char) IT8712_GPIO_BASE >> 8);
4589 +
4590 +       // select GPIO to simple I/O
4591 +       LPCSetConfig(LDN_GPIO, 0xc3, 0xff);
4592 +
4593 +       // enable internal pull-up
4594 +       LPCSetConfig(LDN_GPIO, 0xbb, 0xff);
4595 +
4596 +#endif
4597 +
4598 +       flag = SPI_read(1,0x00);
4599 +       printk("Get ADM identifier %6x\n",flag);
4600 +       if ((flag & 0xFFFF0) == 0x21120) {
4601 +               printk("ADM699X Found\n");
4602 +               return 1;
4603 +       }
4604 +       else {
4605 +               printk("ADM699X not Found\n");
4606 +               return 0;
4607 +       }
4608 +}
4609 +
4610 Index: linux-2.6.23.17/drivers/net/sl351x_crc16.c
4611 ===================================================================
4612 --- /dev/null
4613 +++ linux-2.6.23.17/drivers/net/sl351x_crc16.c
4614 @@ -0,0 +1,93 @@
4615 +/****************************************************************************
4616 +* Name                 : sl351x_crc16.c
4617 +* Description  :
4618 +*              Implement CRC16
4619 +*              refer to RFC1662
4620 +* History
4621 +*
4622 +*      Date            Writer          Description
4623 +*      -----------     -----------     -------------------------------------------------
4624 +*      09/14/2005      Gary Chen       Create
4625 +*
4626 +****************************************************************************/
4627 +
4628 +#define INITFCS16              0xffff  /* Initial FCS value */
4629 +#define GOODFCS16              0xf0b8  /* Good final FCS value */
4630 +#define SWAP_WORD(x)   (unsigned short)((((unsigned short)x & 0x00FF) << 8) |  \
4631 +                                                                                (((unsigned short)x & 0xFF00) >> 8))
4632 +
4633 +/*----------------------------------------------------------------------
4634 +*      x**0 + x**5 + x**12 + x**16
4635 +*----------------------------------------------------------------------*/
4636 +static const unsigned short crc16_tbl[256] = {
4637 +      0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
4638 +      0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
4639 +      0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
4640 +      0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
4641 +      0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
4642 +      0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
4643 +      0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
4644 +      0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
4645 +      0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
4646 +      0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
4647 +      0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
4648 +      0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
4649 +      0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
4650 +      0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
4651 +      0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
4652 +      0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
4653 +      0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
4654 +      0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
4655 +      0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
4656 +      0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
4657 +      0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
4658 +      0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
4659 +      0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
4660 +      0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
4661 +      0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
4662 +      0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
4663 +      0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
4664 +      0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
4665 +      0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
4666 +      0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
4667 +      0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
4668 +      0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
4669 +};
4670 +
4671 +/*----------------------------------------------------------------------
4672 +* hash_crc16
4673 +*----------------------------------------------------------------------*/
4674 +unsigned short hash_crc16(unsigned short crc, unsigned char *datap, unsigned long len)
4675 +{
4676 +    while (len--)
4677 +    {
4678 +        crc = (crc >> 8) ^ crc16_tbl[(crc ^ (*datap++)) & 0xff];
4679 +    }
4680 +
4681 +    return (crc);
4682 +
4683 +}
4684 +
4685 +/*----------------------------------------------------------------------
4686 +* hash_check_crc16
4687 +*----------------------------------------------------------------------*/
4688 +unsigned long hash_check_crc16(unsigned char *datap, unsigned long len)
4689 +{
4690 +    unsigned short crc;
4691 +
4692 +    crc = hash_crc16(INITFCS16, datap, len );
4693 +    return (crc == GOODFCS16) ?  0 : 1;
4694 +}
4695 +
4696 +/*----------------------------------------------------------------------
4697 +* hash_gen_crc16
4698 +*----------------------------------------------------------------------*/
4699 +unsigned short hash_gen_crc16(unsigned char *datap, unsigned long len)
4700 +{
4701 +    unsigned short crc;
4702 +
4703 +    crc = hash_crc16(INITFCS16, datap, len);
4704 +    crc ^= 0xffff;
4705 +
4706 +    return(SWAP_WORD(crc));
4707 +}
4708 Index: linux-2.6.23.17/drivers/net/sl351x_gmac.c
4709 ===================================================================
4710 --- /dev/null
4711 +++ linux-2.6.23.17/drivers/net/sl351x_gmac.c
4712 @@ -0,0 +1,5622 @@
4713 +/**************************************************************************
4714 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
4715 +*--------------------------------------------------------------------------
4716 +* Name                 : sl351x_gmac.c
4717 +* Description  :
4718 +*              Ethernet device driver for Storlink SL351x FPGA
4719 +*
4720 +* History
4721 +*
4722 +*      Date            Writer          Description
4723 +*      -----------     -----------     -------------------------------------------------
4724 +*      08/22/2005      Gary Chen       Create and implement
4725 +*   27/10/2005  CH Hsu      Porting to Linux
4726 +*
4727 +****************************************************************************/
4728 +#include <linux/module.h>
4729 +#include <linux/kernel.h>
4730 +#include <linux/slab.h>
4731 +#include <linux/mm.h>
4732 +#include <linux/compiler.h>
4733 +#include <linux/pci.h>
4734 +#include <linux/init.h>
4735 +#include <linux/ioport.h>
4736 +#include <linux/netdevice.h>
4737 +#include <linux/etherdevice.h>
4738 +#include <linux/rtnetlink.h>
4739 +#include <linux/delay.h>
4740 +#include <linux/ethtool.h>
4741 +#include <linux/mii.h>
4742 +#include <linux/completion.h>
4743 +#include <asm/hardware.h>
4744 +#include <asm/io.h>
4745 +#include <asm/irq.h>
4746 +#include <asm/semaphore.h>
4747 +#include <asm/arch/irqs.h>
4748 +#include <asm/arch/it8712.h>
4749 +#include <linux/mtd/kvctl.h>
4750 +#include <linux/skbuff.h>
4751 +#include <linux/in.h>
4752 +#include <linux/ip.h>
4753 +#include <linux/tcp.h>
4754 +#include <linux/udp.h>
4755 +
4756 +#include <linux/mtd/kvctl.h>
4757 +
4758 +#define         MIDWAY
4759 +#define         SL_LEPUS
4760 +#define VITESSE_G5SWITCH       1
4761 +
4762 +#ifndef CONFIG_SL351x_RXTOE
4763 +//#define CONFIG_SL351x_RXTOE  1
4764 +#endif
4765 +#undef CONFIG_SL351x_RXTOE
4766 +
4767 +#include <asm/arch/sl2312.h>
4768 +#include <asm/arch/sl351x_gmac.h>
4769 +#include <asm/arch/sl351x_hash_cfg.h>
4770 +#include <asm/arch/sl351x_nat_cfg.h>
4771 +
4772 +#ifdef CONFIG_SL351x_SYSCTL
4773 +#include <linux/sysctl_storlink.h>
4774 +#endif
4775 +
4776 +#ifdef CONFIG_SL351x_RXTOE
4777 +#include <asm/arch/sl351x_toe.h>
4778 +#include <net/tcp.h>
4779 +#include <linux/tcp.h>
4780 +#include <linux/ip.h>
4781 +#endif
4782 +
4783 +// #define SL351x_TEST_WORKAROUND
4784 +#ifdef CONFIG_SL351x_NAT
4785 +#define CONFIG_SL_NAPI                                 1
4786 +#endif
4787 +#define GMAX_TX_INTR_DISABLED                  1
4788 +#define DO_HW_CHKSUM                                   1
4789 +#define ENABLE_TSO                                             1
4790 +#define GMAC_USE_TXQ0                                  1
4791 +// #define NAT_WORKAROUND_BY_RESET_GMAC        1
4792 +// #define HW_RXBUF_BY_KMALLOC                 1
4793 +//#define _DUMP_TX_TCP_CONTENT 1
4794 +#define        br_if_ioctl                                             1
4795 +#define GMAC_LEN_1_2_ISSUE                             1
4796 +
4797 +#define GMAC_EXISTED_FLAG                      0x5566abcd
4798 +#define CONFIG_MAC_NUM                         GMAC_NUM
4799 +#define GMAC0_BASE                                     TOE_GMAC0_BASE
4800 +#define GMAC1_BASE                                     TOE_GMAC1_BASE
4801 +#define PAUSE_SET_HW_FREEQ                     (TOE_HW_FREEQ_DESC_NUM / 2)
4802 +#define PAUSE_REL_HW_FREEQ                     ((TOE_HW_FREEQ_DESC_NUM / 2) + 10)
4803 +#define DEFAULT_RXQ_MAX_CNT                    256
4804 +#ifdef L2_jumbo_frame
4805 +#define TCPHDRLEN(tcp_hdr)  ((ntohs(*((__u16 *)tcp_hdr + 6)) >> 12) & 0x000F)
4806 +#endif
4807 +
4808 +/* define chip information */
4809 +#define DRV_NAME                                       "SL351x"
4810 +#define DRV_VERSION                                    "0.1.4"
4811 +#define SL351x_DRIVER_NAME             DRV_NAME " Giga Ethernet driver " DRV_VERSION
4812 +
4813 +#define toe_gmac_enable_interrupt(irq) enable_irq(irq)
4814 +#define toe_gmac_disable_interrupt(irq)        disable_irq(irq)
4815 +
4816 +#ifdef SL351x_GMAC_WORKAROUND
4817 +#define GMAC_SHORT_FRAME_THRESHOLD             10
4818 +static struct timer_list gmac_workround_timer_obj;
4819 +void sl351x_poll_gmac_hanged_status(u32 data);
4820 +#ifdef CONFIG_SL351x_NAT
4821 +//#define IxscriptMate_1518                            1
4822 +       void sl351x_nat_workaround_init(void);
4823 +       #ifndef NAT_WORKAROUND_BY_RESET_GMAC
4824 +               static void sl351x_nat_workaround_handler(void);
4825 +       #endif
4826 +#endif
4827 +#endif
4828 +
4829 +#ifdef GMAC_LEN_1_2_ISSUE
4830 +       #define _DEBUG_PREFETCH_NUM     256
4831 +static int     _debug_prefetch_cnt;
4832 +static char _debug_prefetch_buf[_DEBUG_PREFETCH_NUM][4] __attribute__((aligned(4)));
4833 +#endif
4834 +/*************************************************************
4835 + *         Global Variable
4836 + *************************************************************/
4837 +static int     gmac_initialized = 0;
4838 +TOE_INFO_T toe_private_data;
4839 +//static int           do_again = 0;
4840 +spinlock_t gmac_fq_lock;
4841 +unsigned int FLAG_SWITCH;
4842 +
4843 +static unsigned int            next_tick = 3 * HZ;
4844 +static unsigned char           eth_mac[CONFIG_MAC_NUM][6]= {{0x00,0x11,0x11,0x87,0x87,0x87}, {0x00,0x22,0x22,0xab,0xab,0xab}};
4845 +
4846 +#undef CONFIG_SL351x_RXTOE
4847 +extern NAT_CFG_T nat_cfg;
4848 +
4849 +/************************************************/
4850 +/*                 function declare             */
4851 +/************************************************/
4852 +static int gmac_set_mac_address(struct net_device *dev, void *addr);
4853 +static unsigned int gmac_get_phy_vendor(int phy_addr);
4854 +static void gmac_set_phy_status(struct net_device *dev);
4855 +void gmac_get_phy_status(struct net_device *dev);
4856 +static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
4857 +static void gmac_tx_timeout(struct net_device *dev);
4858 +static int gmac_phy_thread (void *data);
4859 +struct net_device_stats * gmac_get_stats(struct net_device *dev);
4860 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev);
4861 +static void gmac_set_rx_mode(struct net_device *dev);
4862 +static irqreturn_t toe_gmac_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
4863 +static void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp);
4864 +unsigned int mii_read(unsigned char phyad,unsigned char regad);
4865 +void mii_write(unsigned char phyad,unsigned char regad,unsigned int value);
4866 +void mac_init_drv(void);
4867 +
4868 +static void toe_init_free_queue(void);
4869 +static void toe_init_swtx_queue(void);
4870 +static void toe_init_default_queue(void);
4871 +#ifdef CONFIG_SL351x_RXTOE
4872 +static void toe_init_interrupt_queue(void);
4873 +#endif
4874 +static void toe_init_interrupt_config(void);
4875 +static void toe_gmac_sw_reset(void);
4876 +static int toe_gmac_init_chip(struct net_device *dev);
4877 +static void toe_gmac_enable_tx_rx(struct net_device* dev);
4878 +static void toe_gmac_disable_tx_rx(struct net_device *dev);
4879 +static void toe_gmac_hw_start(struct net_device *dev);
4880 +static void toe_gmac_hw_stop(struct net_device *dev);
4881 +static int toe_gmac_clear_counter(struct net_device *dev);
4882 +static void toe_init_gmac(struct net_device *dev);
4883 +static  void toe_gmac_tx_complete(GMAC_INFO_T *tp, unsigned int tx_qid, struct net_device *dev, int interrupt);
4884 +#ifdef CONFIG_SL_NAPI
4885 +static int gmac_rx_poll(struct net_device *dev, int *budget);
4886 +// static void toe_gmac_disable_rx(struct net_device *dev);
4887 +// static void toe_gmac_enable_rx(struct net_device *dev);
4888 +#endif
4889 +
4890 +u32 mac_read_dma_reg(int mac, unsigned int offset);
4891 +void mac_write_dma_reg(int mac, unsigned int offset, u32 data);
4892 +void mac_stop_txdma(struct net_device *dev);
4893 +void mac_get_sw_tx_weight(struct net_device *dev, char *weight);
4894 +void mac_set_sw_tx_weight(struct net_device *dev, char *weight);
4895 +void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
4896 +void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
4897 +static inline void toe_gmac_fill_free_q(void);
4898 +
4899 +#ifdef VITESSE_G5SWITCH
4900 +extern int Get_Set_port_status(void);
4901 +extern int SPI_default(void);
4902 +extern unsigned int SPI_get_identifier(void);
4903 +void gmac_get_switch_status(struct net_device *dev);
4904 +unsigned int Giga_switch=0;
4905 +unsigned int switch_port_no=0;
4906 +unsigned int ever_dwon=0;
4907 +#endif
4908 +
4909 +/************************************************/
4910 +/*            GMAC function declare             */
4911 +/************************************************/
4912 +static int gmac_open (struct net_device *dev);
4913 +static int gmac_close (struct net_device *dev);
4914 +static void gmac_cleanup_module(void);
4915 +static void gmac_get_mac_address(void);
4916 +
4917 +#ifdef CONFIG_SL351x_NAT
4918 +static void toe_init_hwtx_queue(void);
4919 +extern void sl351x_nat_init(void);
4920 +extern void sl351x_nat_input(struct sk_buff *skb, int port, void *l3off, void *l4off);
4921 +extern int sl351x_nat_output(struct sk_buff *skb, int port);
4922 +extern int sl351x_nat_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
4923 +#endif
4924 +
4925 +#ifdef CONFIG_SL351x_RXTOE
4926 +extern void set_toeq_hdr(struct toe_conn* connection, TOE_INFO_T* toe, struct net_device *dev);
4927 +extern void sl351x_toe_init(void);
4928 +extern void toe_gmac_handle_toeq(struct net_device *dev, GMAC_INFO_T* tp, __u32 status);
4929 +extern struct toe_conn* init_toeq(int ipver, void* iph, struct tcphdr* tcp_hdr, TOE_INFO_T* toe, unsigned char* l2hdr);
4930 +#endif
4931 +
4932 +int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2);
4933 +void mac_set_rule_enable_bit(int mac, int rule, int data);
4934 +int mac_set_rule_action(int mac, int rule, int data);
4935 +int mac_get_MRxCRx(int mac, int rule, int ctrlreg);
4936 +void mac_set_MRxCRx(int mac, int rule, int ctrlreg, u32 data);
4937 +
4938 +/*----------------------------------------------------------------------
4939 +*      Ethernet Driver init
4940 +*----------------------------------------------------------------------*/
4941 +
4942 +static int __init gmac_init_module(void)
4943 +{
4944 +       GMAC_INFO_T             *tp;
4945 +       struct net_device       *dev;
4946 +       int             i,j;
4947 +       unsigned int    chip_id;
4948 +//     unsigned int chip_version;
4949 +
4950 +#ifdef CONFIG_SL3516_ASIC
4951 +{
4952 +    unsigned int    val;
4953 +    /* set GMAC global register */
4954 +    val = readl(GMAC_GLOBAL_BASE_ADDR+0x10);
4955 +    val = val | 0x005f0000;
4956 +    writel(val,GMAC_GLOBAL_BASE_ADDR+0x10);
4957 +//    writel(0xb737b737,GMAC_GLOBAL_BASE_ADDR+0x1c); //For Socket Board
4958 +    writel(0x77777777,GMAC_GLOBAL_BASE_ADDR+0x20);
4959 +//    writel(0xa737b747,GMAC_GLOBAL_BASE_ADDR+0x1c);//For Mounting Board
4960 +
4961 +       //debug_Aaron
4962 +    //writel(0xa7f0a7f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For Mounting Board
4963 +    writel(0xa7f0b7f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For Mounting Board
4964 +
4965 +    writel(0x77777777,GMAC_GLOBAL_BASE_ADDR+0x24);
4966 +       writel(0x09200030,GMAC_GLOBAL_BASE_ADDR+0x2C);
4967 +       val = readl(GMAC_GLOBAL_BASE_ADDR+0x04);
4968 +       if((val&(1<<20))==0){           // GMAC1 enable
4969 +               val = readl(GMAC_GLOBAL_BASE_ADDR+0x30);
4970 +               val = (val & 0xe7ffffff) | 0x08000000;
4971 +               writel(val,GMAC_GLOBAL_BASE_ADDR+0x30);
4972 +       }
4973 +}
4974 +#endif
4975 +
4976 +#ifdef VITESSE_G5SWITCH
4977 +       Giga_switch = SPI_get_identifier();
4978 +       if(Giga_switch)
4979 +               switch_port_no = SPI_default();
4980 +#endif
4981 +
4982 +       chip_id = readl(GMAC_GLOBAL_BASE_ADDR+0x0);
4983 +       if (chip_id == 0x3512C1)
4984 +       {
4985 +               writel(0x5787a5f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For 3512 Switch Board
4986 +               writel(0x55557777,GMAC_GLOBAL_BASE_ADDR+0x20);//For 3512 Switch Board
4987 +       }
4988 +//#endif
4989 +
4990 +       mac_init_drv();
4991 +
4992 +       printk (KERN_INFO SL351x_DRIVER_NAME " built at %s %s\n", __DATE__, __TIME__);
4993 +
4994 +//     init_waitqueue_entry(&wait, current);
4995 +
4996 +       // printk("GMAC Init......\n");
4997 +
4998 +       i = 0;
4999 +       for(j = 0; i<CONFIG_MAC_NUM; j++)
5000 +       {
5001 +               i=j;
5002 +               if(Giga_switch){                // if gswitch present, swap eth0/1
5003 +                       if(j==0)
5004 +                               i=1;
5005 +                       else if(j==1)
5006 +                               i=0;
5007 +               }
5008 +
5009 +               tp = (GMAC_INFO_T *)&toe_private_data.gmac[i];
5010 +               tp->dev = NULL;
5011 +               if (tp->existed != GMAC_EXISTED_FLAG) continue;
5012 +
5013 +               dev = alloc_etherdev(0);
5014 +               if (dev == NULL)
5015 +               {
5016 +                       printk (KERN_ERR "Can't allocate ethernet device #%d .\n",i);
5017 +                       return -ENOMEM;
5018 +               }
5019 +
5020 +               dev->priv=tp;
5021 +               tp->dev = dev;
5022 +
5023 +               SET_MODULE_OWNER(dev);
5024 +
5025 +               // spin_lock_init(&tp->lock);
5026 +               spin_lock_init(&gmac_fq_lock);
5027 +               dev->base_addr = tp->base_addr;
5028 +               dev->irq = tp->irq;
5029 +           dev->open = gmac_open;
5030 +           dev->stop = gmac_close;
5031 +               dev->hard_start_xmit = gmac_start_xmit;
5032 +               dev->get_stats = gmac_get_stats;
5033 +               dev->set_multicast_list = gmac_set_rx_mode;
5034 +               dev->set_mac_address = gmac_set_mac_address;
5035 +               dev->do_ioctl = gmac_netdev_ioctl;
5036 +               dev->tx_timeout = gmac_tx_timeout;
5037 +               dev->watchdog_timeo = GMAC_DEV_TX_TIMEOUT;
5038 +#ifdef L2_jumbo_frame
5039 +               dev->mtu = 2018; //2002  ,2018
5040 +#endif
5041 +               if (tp->port_id == 0)
5042 +                       dev->tx_queue_len = TOE_GMAC0_SWTXQ_DESC_NUM;
5043 +               else
5044 +                       dev->tx_queue_len = TOE_GMAC1_SWTXQ_DESC_NUM;
5045 +
5046 +#ifdef DO_HW_CHKSUM
5047 +               dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
5048 +#ifdef ENABLE_TSO
5049 +               dev->features |= NETIF_F_TSO;
5050 +#endif
5051 +#endif
5052 +#ifdef CONFIG_SL_NAPI
5053 +        dev->poll = gmac_rx_poll;
5054 +        dev->weight = 64;
5055 +#endif
5056 +
5057 +               if (register_netdev(dev))
5058 +               {
5059 +                       gmac_cleanup_module();
5060 +                       return(-1);
5061 +               }
5062 +       }
5063 +
5064 +
5065 +//     FLAG_SWITCH = 0 ;
5066 +//     FLAG_SWITCH = SPI_get_identifier();
5067 +//     if(FLAG_SWITCH)
5068 +//     {
5069 +//             printk("Configure ADM699X...\n");
5070 +//             SPI_default();  //Add by jason for ADM699X configuration
5071 +//     }
5072 +       return (0);
5073 +}
5074 +
5075 +/*----------------------------------------------------------------------
5076 +*      gmac_cleanup_module
5077 +*----------------------------------------------------------------------*/
5078 +
5079 +static void gmac_cleanup_module(void)
5080 +{
5081 +    int i;
5082 +
5083 +#ifdef SL351x_GMAC_WORKAROUND
5084 +       del_timer(&gmac_workround_timer_obj);
5085 +#endif
5086 +
5087 +    for (i=0;i<CONFIG_MAC_NUM;i++)
5088 +    {
5089 +       if (toe_private_data.gmac[i].dev)
5090 +       {
5091 +               unregister_netdev(toe_private_data.gmac[i].dev);
5092 +               toe_private_data.gmac[i].dev = NULL;
5093 +        }
5094 +    }
5095 +       return ;
5096 +}
5097 +
5098 +module_init(gmac_init_module);
5099 +module_exit(gmac_cleanup_module);
5100 +
5101 +
5102 +/*----------------------------------------------------------------------
5103 +*      gmac_read_reg
5104 +*----------------------------------------------------------------------*/
5105 +static inline unsigned int gmac_read_reg(unsigned int base, unsigned int offset)
5106 +//static unsigned int gmac_read_reg(unsigned int base, unsigned int offset)
5107 +{
5108 +    volatile unsigned int reg_val;
5109 +
5110 +    reg_val = readl(base + offset);
5111 +       return (reg_val);
5112 +}
5113 +
5114 +/*----------------------------------------------------------------------
5115 +*      gmac_write_reg
5116 +*----------------------------------------------------------------------*/
5117 +static inline void gmac_write_reg(unsigned int base, unsigned int offset,unsigned int data,unsigned int bit_mask)
5118 +//static void gmac_write_reg(unsigned int base, unsigned int offset,unsigned int data,unsigned int bit_mask)
5119 +{
5120 +       volatile unsigned int reg_val;
5121 +    unsigned int *addr;
5122 +
5123 +       reg_val = ( gmac_read_reg(base, offset) & (~bit_mask) ) | (data & bit_mask);
5124 +       addr = (unsigned int *)(base + offset);
5125 +    writel(reg_val,addr);
5126 +       return;
5127 +}
5128 +
5129 +/*----------------------------------------------------------------------
5130 +*      mac_init_drv
5131 +*----------------------------------------------------------------------*/
5132 +void mac_init_drv(void)
5133 +{
5134 +       TOE_INFO_T                      *toe;
5135 +       int                                     i;
5136 +       QUEUE_THRESHOLD_T       threshold;
5137 +       u32                                     *destp;
5138 +       unsigned int            chip_id,chip_version;
5139 +
5140 +       chip_id = readl(GMAC_GLOBAL_BASE_ADDR+0x0);
5141 +       chip_version = chip_id & 0x1 ;
5142 +
5143 +       if (!gmac_initialized)
5144 +       {
5145 +               gmac_initialized = 1;
5146 +
5147 +               // clear non TOE Queue Header Area
5148 +               destp = (u32 *)TOE_NONTOE_QUE_HDR_BASE;
5149 +               for (; destp < (u32 *)NONTOE_Q_HDR_AREA_END; destp++)
5150 +                       *destp = 0x00;
5151 +
5152 +               // clear TOE Queue Header Area
5153 +               destp = (u32 *)TOE_TOE_QUE_HDR_BASE;
5154 +               for (; destp < (u32 *)TOE_Q_HDR_AREA_END; destp++)
5155 +                       *destp = 0x00;
5156 +
5157 +               // init private data
5158 +               toe = (TOE_INFO_T *)&toe_private_data;
5159 +               memset((void *)toe, 0, sizeof(TOE_INFO_T));
5160 +               toe->gmac[0].base_addr = GMAC0_BASE;
5161 +               toe->gmac[1].base_addr = GMAC1_BASE;
5162 +               toe->gmac[0].dma_base_addr = TOE_GMAC0_DMA_BASE;
5163 +               toe->gmac[1].dma_base_addr = TOE_GMAC1_DMA_BASE;
5164 +        toe->gmac[0].auto_nego_cfg = 1;
5165 +        toe->gmac[1].auto_nego_cfg = 1;
5166 +#ifdef CONFIG_SL3516_ASIC
5167 +        toe->gmac[0].speed_cfg = GMAC_SPEED_1000;
5168 +        toe->gmac[1].speed_cfg = GMAC_SPEED_1000;
5169 +#else
5170 +               toe->gmac[0].speed_cfg = GMAC_SPEED_100;
5171 +        toe->gmac[1].speed_cfg = GMAC_SPEED_100;
5172 +#endif
5173 +        toe->gmac[0].full_duplex_cfg = 1;
5174 +        toe->gmac[1].full_duplex_cfg = 1;
5175 +#ifdef CONFIG_SL3516_ASIC
5176 +        toe->gmac[0].phy_mode = GMAC_PHY_RGMII_1000;
5177 +        toe->gmac[1].phy_mode = GMAC_PHY_RGMII_1000;
5178 +#else
5179 +               toe->gmac[0].phy_mode = GMAC_PHY_RGMII_100;
5180 +        toe->gmac[1].phy_mode = GMAC_PHY_RGMII_100;
5181 +#endif
5182 +        toe->gmac[0].port_id = GMAC_PORT0;
5183 +        toe->gmac[1].port_id = GMAC_PORT1;
5184 +        toe->gmac[0].phy_addr = 0x1;
5185 +        toe->gmac[1].phy_addr = 2;
5186 +//      toe->gmac[0].irq = SL2312_INTERRUPT_GMAC0;
5187 +               toe->gmac[0].irq =1;
5188 +//      toe->gmac[1].irq = SL2312_INTERRUPT_GMAC1;
5189 +               toe->gmac[1].irq =2;
5190 +        toe->gmac[0].mac_addr1 = &eth_mac[0][0];
5191 +        toe->gmac[1].mac_addr1 = &eth_mac[1][0];
5192 +
5193 +               for (i=0; i<CONFIG_MAC_NUM; i++)
5194 +               {
5195 +                       unsigned int data, phy_vendor;
5196 +                       gmac_write_reg(toe->gmac[i].base_addr, GMAC_STA_ADD2, 0x55aa55aa, 0xffffffff);
5197 +                       data = gmac_read_reg(toe->gmac[i].base_addr, GMAC_STA_ADD2);
5198 +                       if (data == 0x55aa55aa)
5199 +                       {
5200 +#ifdef VITESSE_G5SWITCH
5201 +                               if(Giga_switch && (i==1)){
5202 +                                       toe->gmac[i].existed = GMAC_EXISTED_FLAG;
5203 +                                       break;
5204 +                               }
5205 +#endif
5206 +                               phy_vendor = gmac_get_phy_vendor(toe->gmac[i].phy_addr);
5207 +                               if (phy_vendor != 0 && phy_vendor != 0xffffffff)
5208 +                                       toe->gmac[i].existed = GMAC_EXISTED_FLAG;
5209 +                       }
5210 +               }
5211 +
5212 +               // Write GLOBAL_QUEUE_THRESHOLD_REG
5213 +               threshold.bits32 = 0;
5214 +               threshold.bits.swfq_empty = (TOE_SW_FREEQ_DESC_NUM > 256) ? 255 :
5215 +                                                       TOE_SW_FREEQ_DESC_NUM/2;
5216 +               threshold.bits.hwfq_empty = (TOE_HW_FREEQ_DESC_NUM > 256) ? 256/4 :
5217 +                                                       TOE_HW_FREEQ_DESC_NUM/4;
5218 +               threshold.bits.toe_class = (TOE_TOE_DESC_NUM > 256) ? 256/4 :
5219 +                                                       TOE_TOE_DESC_NUM/4;
5220 +               threshold.bits.intrq = (TOE_INTR_DESC_NUM > 256) ? 256/4 :
5221 +                                                       TOE_INTR_DESC_NUM/4;
5222 +               writel(threshold.bits32, TOE_GLOBAL_BASE + GLOBAL_QUEUE_THRESHOLD_REG);
5223 +
5224 +               FLAG_SWITCH = 0;
5225 +               toe_gmac_sw_reset();
5226 +               toe_init_free_queue();
5227 +               toe_init_swtx_queue();
5228 +#ifdef CONFIG_SL351x_NAT
5229 +               toe_init_hwtx_queue();
5230 +#endif
5231 +               toe_init_default_queue();
5232 +#ifdef CONFIG_SL351x_RXTOE
5233 +               toe_init_interrupt_queue();
5234 +#endif
5235 +               toe_init_interrupt_config();
5236 +
5237 +#if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
5238 +               sl351x_hash_init();
5239 +#else
5240 +       {
5241 +               volatile u32 *dp1, *dp2, dword;
5242 +
5243 +               dp1 = (volatile u32 *) TOE_V_BIT_BASE;
5244 +               dp2 = (volatile u32 *) TOE_A_BIT_BASE;
5245 +
5246 +               for (i=0; i<HASH_TOTAL_ENTRIES/32; i++)
5247 +               {
5248 +                       *dp1++ = 0;
5249 +                       dword = *dp2++; // read-clear
5250 +               }
5251 +       }
5252 +#endif
5253 +       }
5254 +
5255 +#ifdef SL351x_GMAC_WORKAROUND
5256 +#ifdef CONFIG_SL351x_NAT
5257 +       sl351x_nat_workaround_init();
5258 +#endif
5259 +       init_timer(&gmac_workround_timer_obj);
5260 +       if (chip_version == 1)
5261 +       {
5262 +               gmac_workround_timer_obj.expires = jiffies * 50;
5263 +       }
5264 +       else
5265 +       {
5266 +               gmac_workround_timer_obj.expires = jiffies + 2;
5267 +       }
5268 +       gmac_workround_timer_obj.data = (unsigned long)&gmac_workround_timer_obj;
5269 +       gmac_workround_timer_obj.function = (void *)&sl351x_poll_gmac_hanged_status;
5270 +       add_timer(&gmac_workround_timer_obj);
5271 +#endif
5272 +}
5273 +
5274 +/*----------------------------------------------------------------------
5275 +*      toe_init_free_queue
5276 +*      (1) Initialize the Free Queue Descriptor Base Address & size
5277 +*              Register: TOE_GLOBAL_BASE + 0x0004
5278 +*      (2) Initialize DMA Read/Write pointer for
5279 +*              SW Free Queue and HW Free Queue
5280 +*      (3)     Initialize DMA Descriptors for
5281 +*              SW Free Queue and HW Free Queue,
5282 +*----------------------------------------------------------------------*/
5283 +static void toe_init_free_queue(void)
5284 +{
5285 +       int                             i;
5286 +       TOE_INFO_T                      *toe;
5287 +       DMA_RWPTR_T                     rwptr_reg;
5288 +//     unsigned int            rwptr_addr;
5289 +       unsigned int            desc_buf;
5290 +       GMAC_RXDESC_T           *sw_desc_ptr;
5291 +       struct sk_buff          *skb;
5292 +#ifdef CONFIG_SL351x_NAT
5293 +       GMAC_RXDESC_T           *desc_ptr;
5294 +       unsigned int            buf_ptr;
5295 +#endif
5296 +
5297 +       toe = (TOE_INFO_T *)&toe_private_data;
5298 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T)),
5299 +                                               (dma_addr_t *)&toe->sw_freeq_desc_base_dma) ;
5300 +       sw_desc_ptr = (GMAC_RXDESC_T *)desc_buf;
5301 +       if (!desc_buf)
5302 +       {
5303 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5304 +               return;
5305 +       }
5306 +       memset((void *)desc_buf, 0, TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
5307 +
5308 +       // DMA Queue Base & Size
5309 +       writel((toe->sw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_SW_FREEQ_DESC_POWER,
5310 +                       TOE_GLOBAL_BASE + GLOBAL_SW_FREEQ_BASE_SIZE_REG);
5311 +
5312 +       // init descriptor base
5313 +       toe->swfq_desc_base = desc_buf;
5314 +
5315 +       // SW Free Queue Read/Write Pointer
5316 +       rwptr_reg.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
5317 +       rwptr_reg.bits.rptr = 0;
5318 +       toe->fq_rx_rwptr.bits32 = rwptr_reg.bits32;
5319 +       writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
5320 +
5321 +       // SW Free Queue Descriptors
5322 +       for (i=0; i<TOE_SW_FREEQ_DESC_NUM; i++)
5323 +       {
5324 +               sw_desc_ptr->word0.bits.buffer_size = SW_RX_BUF_SIZE;
5325 +               sw_desc_ptr->word1.bits.sw_id = i;      // used to locate skb
5326 +               if ( (skb = dev_alloc_skb(SW_RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
5327 +               {
5328 +                       printk("%s::skb buffer allocation fail !\n",__func__); while(1);
5329 +               }
5330 +               REG32(skb->data) = (unsigned int)skb;
5331 +               skb_reserve(skb, SKB_RESERVE_BYTES);
5332 +               // toe->rx_skb[i] = skb;
5333 +               sw_desc_ptr->word2.buf_adr = (unsigned int)__pa(skb->data);
5334 +//             consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
5335 +               sw_desc_ptr++;
5336 +       }
5337 +
5338 +#ifdef CONFIG_SL351x_NAT
5339 +       if (sizeof(skb->cb) < 64)
5340 +       {
5341 +                       printk("==> %s:: sk structure is incorrect -->Change to cb[64] !\n",__func__); while(1);
5342 +       }
5343 +       // init hardware free queues
5344 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_HW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T)),
5345 +                                               (dma_addr_t *)&toe->hw_freeq_desc_base_dma) ;
5346 +       desc_ptr = (GMAC_RXDESC_T *)desc_buf;
5347 +       if (!desc_buf)
5348 +       {
5349 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5350 +               return;
5351 +       }
5352 +       memset((void *)desc_buf, 0, TOE_HW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T));
5353 +
5354 +       // DMA Queue Base & Size
5355 +       writel((toe->hw_freeq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_HW_FREEQ_DESC_POWER,
5356 +                       TOE_GLOBAL_BASE + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
5357 +
5358 +       // init descriptor base
5359 +       toe->hwfq_desc_base = desc_buf;
5360 +
5361 +       // HW Free Queue Read/Write Pointer
5362 +       rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
5363 +       rwptr_reg.bits.rptr = 0;
5364 +       writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
5365 +#ifndef HW_RXBUF_BY_KMALLOC
5366 +       buf_ptr = (unsigned int)DMA_MALLOC(TOE_HW_FREEQ_DESC_NUM * HW_RX_BUF_SIZE,
5367 +                                               (dma_addr_t *)&toe->hwfq_buf_base_dma);
5368 +#else
5369 +       buf_ptr = (unsigned int)kmalloc(TOE_HW_FREEQ_DESC_NUM * HW_RX_BUF_SIZE, GFP_KERNEL);
5370 +       toe->hwfq_buf_base_dma = __pa(buf_ptr);
5371 +#endif
5372 +       if (!buf_ptr)
5373 +       {
5374 +               printk("===> %s::Failed to allocate HW TxQ Buffers!\n",__func__);
5375 +               while(1);       // could not be happened, if happened, adjust the buffer descriptor number
5376 +               return;
5377 +       }
5378 +
5379 +       toe->hwfq_buf_base = buf_ptr;
5380 +       toe->hwfq_buf_end_dma = toe->hwfq_buf_base_dma + (TOE_HW_FREEQ_DESC_NUM * HW_RX_BUF_SIZE);
5381 +       buf_ptr = (unsigned int)toe->hwfq_buf_base_dma;
5382 +       for (i=0; i<TOE_HW_FREEQ_DESC_NUM; i++)
5383 +       {
5384 +               desc_ptr->word0.bits.buffer_size = HW_RX_BUF_SIZE;
5385 +               desc_ptr->word1.bits.sw_id = i;
5386 +               desc_ptr->word2.buf_adr = (unsigned int)buf_ptr;
5387 +//             consistent_sync((unsigned int)desc_ptr, sizeof(GMAC_RXDESC_T), PCI_DMA_TODEVICE);
5388 +               // consistent_sync((unsigned int)buf_ptr, HW_RX_BUF_SIZE, PCI_DMA_TODEVICE);
5389 +               desc_ptr++;
5390 +               buf_ptr += HW_RX_BUF_SIZE;
5391 +       }
5392 +#else
5393 +       // DMA Queue Base & Size
5394 +       writel((0) | TOE_SW_FREEQ_DESC_POWER,
5395 +                       TOE_GLOBAL_BASE + GLOBAL_HW_FREEQ_BASE_SIZE_REG);
5396 +       rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
5397 +       rwptr_reg.bits.rptr = 0;
5398 +       writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
5399 +
5400 +#endif
5401 +}
5402 +/*----------------------------------------------------------------------
5403 +*      toe_init_swtx_queue
5404 +*      (2) Initialize the GMAC 0/1 SW TXQ Queue Descriptor Base Address & sizeup
5405 +*              GMAC_SW_TX_QUEUE_BASE_REG(0x0050)
5406 +*      (2) Initialize DMA Read/Write pointer for
5407 +*              GMAC 0/1 SW TX Q0-5
5408 +*----------------------------------------------------------------------*/
5409 +static void toe_init_swtx_queue(void)
5410 +{
5411 +       int                             i;
5412 +       TOE_INFO_T                      *toe;
5413 +       DMA_RWPTR_T                     rwptr_reg;
5414 +       unsigned int            rwptr_addr;
5415 +       unsigned int            desc_buf;
5416 +
5417 +
5418 +       toe = (TOE_INFO_T *)&toe_private_data;
5419 +
5420 +       // GMAC-0, SW-TXQ
5421 +       // The GMAC-0 and GMAC-0 maybe have different descriptor number
5422 +       // so, not use for instruction
5423 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
5424 +                                               (dma_addr_t *)&toe->gmac[0].swtxq_desc_base_dma) ;
5425 +       toe->gmac[0].swtxq_desc_base = desc_buf;
5426 +       if (!desc_buf)
5427 +       {
5428 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5429 +               return  ;
5430 +       }
5431 +       memset((void *)desc_buf, 0,     TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
5432 +       writel((toe->gmac[0].swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC0_SWTXQ_DESC_POWER,
5433 +                       TOE_GMAC0_DMA_BASE+ GMAC_SW_TX_QUEUE_BASE_REG);
5434 +
5435 +       // GMAC0 SW TX Q0-Q5
5436 +       rwptr_reg.bits.wptr = 0;
5437 +       rwptr_reg.bits.rptr = 0;
5438 +       rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_SW_TX_QUEUE0_PTR_REG;
5439 +       for (i=0; i<TOE_SW_TXQ_NUM; i++)
5440 +       {
5441 +               toe->gmac[0].swtxq[i].rwptr_reg = rwptr_addr;
5442 +               toe->gmac[0].swtxq[i].desc_base = desc_buf;
5443 +               toe->gmac[0].swtxq[i].total_desc_num = TOE_GMAC0_SWTXQ_DESC_NUM;
5444 +               desc_buf += TOE_GMAC0_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
5445 +               writel(rwptr_reg.bits32, rwptr_addr);
5446 +               rwptr_addr+=4;
5447 +       }
5448 +
5449 +       // GMAC-1, SW-TXQ
5450 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC1_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
5451 +                                               (dma_addr_t *)&toe->gmac[1].swtxq_desc_base_dma) ;
5452 +       toe->gmac[1].swtxq_desc_base = desc_buf;
5453 +       if (!desc_buf)
5454 +       {
5455 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5456 +               return  ;
5457 +       }
5458 +       memset((void *)desc_buf, 0,     TOE_GMAC1_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
5459 +       writel((toe->gmac[1].swtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC1_SWTXQ_DESC_POWER,
5460 +                       TOE_GMAC1_DMA_BASE+ GMAC_SW_TX_QUEUE_BASE_REG);
5461 +
5462 +
5463 +       // GMAC1 SW TX Q0-Q5
5464 +       rwptr_reg.bits.wptr = 0;
5465 +       rwptr_reg.bits.rptr = 0;
5466 +       rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_SW_TX_QUEUE0_PTR_REG;
5467 +       for (i=0; i<TOE_SW_TXQ_NUM; i++)
5468 +       {
5469 +               toe->gmac[1].swtxq[i].rwptr_reg = rwptr_addr;
5470 +               toe->gmac[1].swtxq[i].desc_base = desc_buf;
5471 +               toe->gmac[1].swtxq[i].total_desc_num = TOE_GMAC1_SWTXQ_DESC_NUM;
5472 +               desc_buf += TOE_GMAC1_SWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
5473 +               writel(rwptr_reg.bits32, rwptr_addr);
5474 +               rwptr_addr+=4;
5475 +       }
5476 +}
5477 +
5478 +/*----------------------------------------------------------------------
5479 +*      toe_init_hwtx_queue
5480 +*      (2) Initialize the GMAC 0/1 HW TXQ Queue Descriptor Base Address & size
5481 +*              GMAC_HW_TX_QUEUE_BASE_REG(0x0054)
5482 +*      (2) Initialize DMA Read/Write pointer for
5483 +*              GMAC 0/1 HW TX Q0-5
5484 +*----------------------------------------------------------------------*/
5485 +#ifdef CONFIG_SL351x_NAT
5486 +static void toe_init_hwtx_queue(void)
5487 +{
5488 +       int                             i;
5489 +       TOE_INFO_T                      *toe;
5490 +       DMA_RWPTR_T                     rwptr_reg;
5491 +       unsigned int            rwptr_addr;
5492 +       unsigned int            desc_buf;
5493 +
5494 +       toe = (TOE_INFO_T *)&toe_private_data;
5495 +       // GMAC-0, HW-TXQ
5496 +       // The GMAC-0 and GMAC-0 maybe have different descriptor number
5497 +       // so, not use for instruction
5498 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC0_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
5499 +                                               (dma_addr_t *)&toe->gmac[0].hwtxq_desc_base_dma) ;
5500 +       toe->gmac[0].hwtxq_desc_base = desc_buf;
5501 +       if (!desc_buf)
5502 +       {
5503 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5504 +               return  ;
5505 +       }
5506 +       memset((void *)desc_buf, 0,     TOE_GMAC0_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
5507 +       writel((toe->gmac[0].hwtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC0_HWTXQ_DESC_POWER,
5508 +                       TOE_GMAC0_DMA_BASE+ GMAC_HW_TX_QUEUE_BASE_REG);
5509 +
5510 +       // GMAC0 HW TX Q0-Q5
5511 +       rwptr_reg.bits.wptr = 0;
5512 +       rwptr_reg.bits.rptr = 0;
5513 +       rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
5514 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
5515 +       {
5516 +               toe->gmac[0].hwtxq[i].desc_base = desc_buf;
5517 +               desc_buf += TOE_GMAC0_HWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
5518 +               writel(rwptr_reg.bits32, rwptr_addr);
5519 +               rwptr_addr+=4;
5520 +       }
5521 +
5522 +       // GMAC-1, HW-TXQ
5523 +       desc_buf = (unsigned int)DMA_MALLOC((TOE_GMAC1_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T)),
5524 +                                               (dma_addr_t *)&toe->gmac[1].hwtxq_desc_base_dma) ;
5525 +       toe->gmac[1].hwtxq_desc_base = desc_buf;
5526 +       if (!desc_buf)
5527 +       {
5528 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5529 +               return  ;
5530 +       }
5531 +       memset((void *)desc_buf, 0,     TOE_GMAC1_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T));
5532 +       writel((toe->gmac[1].hwtxq_desc_base_dma & DMA_Q_BASE_MASK) | TOE_GMAC1_HWTXQ_DESC_POWER,
5533 +                       TOE_GMAC1_DMA_BASE+ GMAC_HW_TX_QUEUE_BASE_REG);
5534 +
5535 +       // GMAC1 HW TX Q0-Q5
5536 +       rwptr_reg.bits.wptr = 0;
5537 +       rwptr_reg.bits.rptr = 0;
5538 +       rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
5539 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
5540 +       {
5541 +               toe->gmac[1].hwtxq[i].desc_base = desc_buf;
5542 +               desc_buf += TOE_GMAC1_HWTXQ_DESC_NUM * sizeof(GMAC_TXDESC_T);
5543 +               writel(rwptr_reg.bits32, rwptr_addr);
5544 +               rwptr_addr+=4;
5545 +       }
5546 +}
5547 +#endif
5548 +
5549 +/*----------------------------------------------------------------------
5550 +*      toe_init_default_queue
5551 +*      (1) Initialize the default 0/1 Queue Header
5552 +*              Register: TOE_DEFAULT_Q0_HDR_BASE (0x60002000)
5553 +*                                TOE_DEFAULT_Q1_HDR_BASE (0x60002008)
5554 +*      (2)     Initialize Descriptors of Default Queue 0/1
5555 +*----------------------------------------------------------------------*/
5556 +static void toe_init_default_queue(void)
5557 +{
5558 +       TOE_INFO_T                              *toe;
5559 +       volatile NONTOE_QHDR_T  *qhdr;
5560 +       GMAC_RXDESC_T                   *desc_ptr;
5561 +       DMA_SKB_SIZE_T                  skb_size;
5562 +
5563 +       toe = (TOE_INFO_T *)&toe_private_data;
5564 +       desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T)),
5565 +                                                                                       (dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
5566 +       if (!desc_ptr)
5567 +       {
5568 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5569 +               return  ;
5570 +       }
5571 +       memset((void *)desc_ptr, 0, TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_RXDESC_T));
5572 +       toe->gmac[0].default_desc_base = (unsigned int)desc_ptr;
5573 +       toe->gmac[0].default_desc_num = TOE_DEFAULT_Q0_DESC_NUM;
5574 +       qhdr = (volatile NONTOE_QHDR_T *)TOE_DEFAULT_Q0_HDR_BASE;
5575 +       qhdr->word0.base_size = ((unsigned int)toe->gmac[0].default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q0_DESC_POWER;
5576 +       qhdr->word1.bits32 = 0;
5577 +       toe->gmac[0].rx_rwptr.bits32 = 0;
5578 +       toe->gmac[0].default_qhdr = (NONTOE_QHDR_T *)qhdr;
5579 +       desc_ptr = (GMAC_RXDESC_T *)DMA_MALLOC((TOE_DEFAULT_Q1_DESC_NUM * sizeof(GMAC_RXDESC_T)),
5580 +                                                                                       (dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
5581 +       if (!desc_ptr)
5582 +       {
5583 +               printk("%s::DMA_MALLOC fail !\n",__func__);
5584 +               return  ;
5585 +       }
5586 +       memset((void *)desc_ptr, 0, TOE_DEFAULT_Q1_DESC_NUM * sizeof(GMAC_RXDESC_T));
5587 +       toe->gmac[1].default_desc_base = (unsigned int)desc_ptr;
5588 +       toe->gmac[1].default_desc_num = TOE_DEFAULT_Q1_DESC_NUM;
5589 +       qhdr = (volatile NONTOE_QHDR_T *)TOE_DEFAULT_Q1_HDR_BASE;
5590 +       qhdr->word0.base_size = ((unsigned int)toe->gmac[1].default_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_DEFAULT_Q1_DESC_POWER;
5591 +       qhdr->word1.bits32 = 0;
5592 +       toe->gmac[1].rx_rwptr.bits32 = 0;
5593 +       toe->gmac[1].default_qhdr = (NONTOE_QHDR_T *)qhdr;
5594 +
5595 +       skb_size.bits.hw_skb_size = HW_RX_BUF_SIZE;
5596 +       skb_size.bits.sw_skb_size = SW_RX_BUF_SIZE;
5597 +       writel(skb_size.bits32, TOE_GLOBAL_BASE + GLOBAL_DMA_SKB_SIZE_REG);
5598 +}
5599 +
5600 +/*----------------------------------------------------------------------
5601 +*      toe_init_interrupt_queue
5602 +*      (1) Initialize the Interrupt Queue Header
5603 +*              Register: TOE_INTR_Q_HDR_BASE (0x60002080)
5604 +*      (2)     Initialize Descriptors of Interrupt Queues
5605 +*----------------------------------------------------------------------*/
5606 +#ifdef CONFIG_SL351x_RXTOE
5607 +static void toe_init_interrupt_queue(void)
5608 +{
5609 +       TOE_INFO_T                              *toe;
5610 +       volatile NONTOE_QHDR_T  *qhdr;
5611 +       INTR_QHDR_T                             *desc_ptr;
5612 +       // unsigned int                 desc_buf_addr;
5613 +       int                                             i;
5614 +
5615 +       toe = (TOE_INFO_T *)&toe_private_data;
5616 +       desc_ptr = (INTR_QHDR_T *)DMA_MALLOC((TOE_INTR_QUEUE_NUM * TOE_INTR_DESC_NUM * sizeof(INTR_QHDR_T)),
5617 +                                                                                       (dma_addr_t *)&toe->intr_desc_base_dma);
5618 +       if (!desc_ptr)
5619 +       {
5620 +               printk("%s::DMA_MALLOC interrupt queue fail !\n",__func__);
5621 +               return  ;
5622 +       }
5623 +       /*
5624 +       desc_buf_addr = (unsigned int)DMA_MALLOC((TOE_INTR_DESC_NUM * sizeof(TOE_QHDR_T)),
5625 +                                                                                               (dma_addr_t *)&toe->intr_buf_base_dma);
5626 +       if (!desc_buf_addr)
5627 +       {
5628 +               printk("%s::DMA_MALLOC interrupt desc fail !\n",__func__);
5629 +               return  ;
5630 +       }*/
5631 +       printk("#### %s::Intr Q desc %x\n", __func__, (u32)desc_ptr);
5632 +
5633 +       memset((void *)desc_ptr, 0, TOE_INTR_QUEUE_NUM * TOE_INTR_DESC_NUM * sizeof(INTR_QHDR_T));
5634 +//     memset((void *)desc_buf_addr, 0, TOE_INTR_DESC_NUM * sizeof(TOE_QHDR_T));
5635 +       toe->intr_desc_base = (unsigned int)desc_ptr;
5636 +       toe->intr_desc_num = TOE_INTR_DESC_NUM;
5637 +
5638 +       qhdr = (volatile NONTOE_QHDR_T *)TOE_INTR_Q_HDR_BASE;
5639 +//     intrq = (INTRQ_INFO_T*) &toe->intrq[0];
5640 +       for (i=0; i<TOE_INTR_QUEUE_NUM; i++, qhdr++)
5641 +       {
5642 +               qhdr->word0.base_size = ((unsigned int)toe->intr_desc_base_dma & NONTOE_QHDR0_BASE_MASK) | TOE_INTR_DESC_POWER;
5643 +               qhdr->word1.bits32 = 0;
5644 +               desc_ptr += TOE_INTR_DESC_NUM;
5645 +       }
5646 +}
5647 +
5648 +#endif
5649 +
5650 +/*----------------------------------------------------------------------
5651 +*      toe_init_interrupt_config
5652 +*      Interrupt Select Registers are used to map interrupt to int0 or int1
5653 +*      Int0 and int1 are wired to CPU 0/1 GMAC 0/1
5654 +*      Interrupt Device Inteface data are used to pass device info to
5655 +*              upper device deiver or store status/statistics
5656 +*      ISR handler
5657 +*              (1) If status bit ON but masked, the prinf error message (bug issue)
5658 +*              (2) If select bits are for me, handle it, else skip to let
5659 +*                      the other ISR handles it.
5660 +*  Notes:
5661 +*              GMACx init routine (for eCOS) or open routine (for Linux)
5662 +*       enable the interrupt bits only which are selected for him.
5663 +*
5664 +*      Default Setting:
5665 +*              GMAC0 intr bits ------> int0 ----> eth0
5666 +*              GMAC1 intr bits ------> int1 ----> eth1
5667 +*              TOE intr -------------> int0 ----> eth0
5668 +*              Classification Intr --> int0 ----> eth0
5669 +*              Default Q0 -----------> int0 ----> eth0
5670 +*              Default Q1 -----------> int1 ----> eth1
5671 +*----------------------------------------------------------------------*/
5672 +static void toe_init_interrupt_config(void)
5673 +{
5674 +       // clear all status bits
5675 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
5676 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
5677 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
5678 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
5679 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
5680 +
5681 +       // Init select registers
5682 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
5683 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
5684 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
5685 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
5686 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
5687 +
5688 +       // disable all interrupt
5689 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_0_REG);
5690 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
5691 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_2_REG);
5692 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_3_REG);
5693 +       writel(0, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_4_REG);
5694 +}
5695 +
5696 +/*----------------------------------------------------------------------
5697 +*      toe_init_gmac
5698 +*----------------------------------------------------------------------*/
5699 +static void toe_init_gmac(struct net_device *dev)
5700 +{
5701 +       GMAC_INFO_T             *tp = dev->priv;
5702 +       TOE_INFO_T              *toe;
5703 +       u32                     data;
5704 +
5705 +       if (!gmac_initialized)
5706 +               return ;
5707 +
5708 +       if (!tp->existed)
5709 +               return;
5710 +
5711 +       tp->dev = dev;
5712 +       tp->flow_control_enable = 1;
5713 +       tp->pre_phy_status = LINK_DOWN;
5714 +       tp->full_duplex_status = tp->full_duplex_cfg;
5715 +       tp->speed_status = tp->speed_status;
5716 +
5717 +#if 0
5718 +   /* get mac address from FLASH */
5719 +    gmac_get_mac_address();
5720 +#endif
5721 +
5722 +    /* set PHY register to start autonegition process */
5723 +    gmac_set_phy_status(dev);
5724 +
5725 +       /* GMAC initialization */
5726 +       if ( toe_gmac_init_chip(dev) )
5727 +       {
5728 +               printk ("GMAC %d init fail\n", tp->port_id);
5729 +       }
5730 +
5731 +    /* clear statistic counter */
5732 +    toe_gmac_clear_counter(dev);
5733 +
5734 +       memset((void *)&tp->ifStatics, 0, sizeof(struct net_device_stats));
5735 +
5736 +       /* -----------------------------------------------------------
5737 +       Enable GMAC interrupt & disable loopback
5738 +       Notes:
5739 +               GMACx init routine (for eCOS) or open routine (for Linux)
5740 +               enable the interrupt bits only which are selected for him.
5741 +       --------------------------------------------------------------*/
5742 +       toe = (TOE_INFO_T *)&toe_private_data;
5743 +
5744 +       // Enable Interrupt Bits
5745 +       if (tp->port_id == 0)
5746 +       {
5747 +               tp->intr0_selected =    GMAC0_TXDERR_INT_BIT     | GMAC0_TXPERR_INT_BIT         |
5748 +                                       GMAC0_RXDERR_INT_BIT     | GMAC0_RXPERR_INT_BIT         |
5749 +                                   GMAC0_SWTQ05_FIN_INT_BIT | GMAC0_SWTQ05_EOF_INT_BIT |
5750 +                                   GMAC0_SWTQ04_FIN_INT_BIT | GMAC0_SWTQ04_EOF_INT_BIT |
5751 +                                   GMAC0_SWTQ03_FIN_INT_BIT | GMAC0_SWTQ03_EOF_INT_BIT |
5752 +                                   GMAC0_SWTQ02_FIN_INT_BIT | GMAC0_SWTQ02_EOF_INT_BIT |
5753 +                                   GMAC0_SWTQ01_FIN_INT_BIT | GMAC0_SWTQ01_EOF_INT_BIT |
5754 +                                   GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
5755 +
5756 +#ifdef GMAX_TX_INTR_DISABLED
5757 +           tp->intr0_enabled =         0;
5758 +#else
5759 +           tp->intr0_enabled =         GMAC0_SWTQ00_FIN_INT_BIT | GMAC0_SWTQ00_EOF_INT_BIT;
5760 +#endif
5761 +
5762 +           tp->intr1_selected =        TOE_IQ_ALL_BITS                  | TOE_CLASS_RX_INT_BITS        |
5763 +                                                       GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
5764 +                                                       GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT |
5765 +                                                       DEFAULT_Q0_INT_BIT;
5766 +           tp->intr1_enabled =         DEFAULT_Q0_INT_BIT | TOE_IQ_ALL_BITS;
5767 +           tp->intr2_selected =        0xffffffff;      // TOE Queue 32-63 FUUL Intr
5768 +           tp->intr2_enabled =         0xffffffff;
5769 +           tp->intr3_selected =        0xffffffff;      // TOE Queue 0-31 FUUL Intr
5770 +           tp->intr3_enabled =         0xffffffff;
5771 +           tp->intr4_selected =        GMAC0_INT_BITS | CLASS_RX_FULL_INT_BITS |
5772 +                                                       HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
5773 +           tp->intr4_enabled =         GMAC0_INT_BITS | SWFQ_EMPTY_INT_BIT;
5774 +
5775 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) & ~tp->intr0_selected;
5776 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
5777 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG) & ~tp->intr1_selected;
5778 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
5779 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG) & ~tp->intr2_selected;
5780 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
5781 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG) & ~tp->intr3_selected;
5782 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
5783 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) & ~tp->intr4_selected;
5784 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
5785 +       }
5786 +       else
5787 +       {
5788 +               tp->intr0_selected =    GMAC1_TXDERR_INT_BIT     | GMAC1_TXPERR_INT_BIT         |
5789 +                                       GMAC1_RXDERR_INT_BIT     | GMAC1_RXPERR_INT_BIT         |
5790 +                                   GMAC1_SWTQ15_FIN_INT_BIT | GMAC1_SWTQ15_EOF_INT_BIT |
5791 +                                   GMAC1_SWTQ14_FIN_INT_BIT | GMAC1_SWTQ14_EOF_INT_BIT |
5792 +                                   GMAC1_SWTQ13_FIN_INT_BIT | GMAC1_SWTQ13_EOF_INT_BIT |
5793 +                                   GMAC1_SWTQ12_FIN_INT_BIT | GMAC1_SWTQ12_EOF_INT_BIT |
5794 +                                   GMAC1_SWTQ11_FIN_INT_BIT | GMAC1_SWTQ11_EOF_INT_BIT |
5795 +                                   GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
5796 +#ifdef GMAX_TX_INTR_DISABLED
5797 +           tp->intr0_enabled =         0;
5798 +#else
5799 +           tp->intr0_enabled =         GMAC1_SWTQ10_FIN_INT_BIT | GMAC1_SWTQ10_EOF_INT_BIT;
5800 +#endif
5801 +
5802 +           tp->intr1_selected =        DEFAULT_Q1_INT_BIT;
5803 +           tp->intr1_enabled =         DEFAULT_Q1_INT_BIT | TOE_IQ_ALL_BITS;
5804 +           tp->intr2_selected =        0;       // TOE Queue 32-63 FUUL Intr
5805 +           tp->intr2_enabled =         0;
5806 +           tp->intr3_selected =        0;       // TOE Queue 0-31 FUUL Intr
5807 +           tp->intr3_enabled =         0;
5808 +           tp->intr4_selected =        GMAC1_INT_BITS;
5809 +           tp->intr4_enabled =         GMAC1_INT_BITS;
5810 +
5811 +           if (toe->gmac[0].existed != GMAC_EXISTED_FLAG)
5812 +           {
5813 +               tp->intr1_selected      |=      TOE_IQ_ALL_BITS | TOE_CLASS_RX_INT_BITS |
5814 +                                                               GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT |
5815 +                                                               GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT;
5816 +               tp->intr1_enabled       |=      TOE_IQ_ALL_BITS;
5817 +               tp->intr2_selected      |=      0xffffffff;      // TOE Queue 32-63 FUUL Intr
5818 +               tp->intr2_enabled       |=      0xffffffff;
5819 +               tp->intr3_selected      |=      0xffffffff;      // TOE Queue 0-31 FUUL Intr
5820 +               tp->intr3_enabled       |=      0xffffffff;
5821 +               tp->intr4_selected      |=      CLASS_RX_FULL_INT_BITS |
5822 +                                                               HWFQ_EMPTY_INT_BIT | SWFQ_EMPTY_INT_BIT;
5823 +               tp->intr4_enabled       |=      SWFQ_EMPTY_INT_BIT;
5824 +               }
5825 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG) | tp->intr0_selected;
5826 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_0_REG);
5827 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG) | tp->intr1_selected;
5828 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_1_REG);
5829 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG) | tp->intr2_selected;
5830 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_2_REG);
5831 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG) | tp->intr3_selected;
5832 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_3_REG);
5833 +           data = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG) | tp->intr4_selected;
5834 +           writel(data, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_SELECT_4_REG);
5835 +       }
5836 +
5837 +       // enable only selected bits
5838 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_0_REG,
5839 +                                       tp->intr0_enabled, tp->intr0_selected);
5840 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_1_REG,
5841 +                                       tp->intr1_enabled, tp->intr1_selected);
5842 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_2_REG,
5843 +                                       tp->intr2_enabled, tp->intr2_selected);
5844 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_3_REG,
5845 +                                       tp->intr3_enabled, tp->intr3_selected);
5846 +       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
5847 +                                       tp->intr4_enabled, tp->intr4_selected);
5848 +
5849 +    /* start DMA process */
5850 +       toe_gmac_hw_start(dev);
5851 +
5852 +    /* enable tx/rx register */
5853 +    toe_gmac_enable_tx_rx(dev);
5854 +
5855 +//     toe_gmac_enable_interrupt(tp->irq);
5856 +
5857 +    return ;
5858 +}
5859 +
5860 +
5861 +/*----------------------------------------------------------------------
5862 +* toe_gmac_sw_reset
5863 +*----------------------------------------------------------------------*/
5864 +static void toe_gmac_sw_reset(void)
5865 +{
5866 +       unsigned int    reg_val;
5867 +       reg_val = readl(GMAC_GLOBAL_BASE_ADDR+GLOBAL_RESET_REG) | 0x00000060;   /* GMAC0 S/W reset */
5868 +    writel(reg_val,GMAC_GLOBAL_BASE_ADDR+GLOBAL_RESET_REG);
5869 +    udelay(100);
5870 +    return;
5871 +}
5872 +
5873 +/*----------------------------------------------------------------------
5874 +*      toe_gmac_init_chip
5875 +*----------------------------------------------------------------------*/
5876 +static int toe_gmac_init_chip(struct net_device *dev)
5877 +{
5878 +       GMAC_INFO_T     *tp = dev->priv;
5879 +       GMAC_CONFIG2_T  config2_val;
5880 +       GMAC_CONFIG0_T  config0,config0_mask;
5881 +       GMAC_CONFIG1_T  config1;
5882 +       #ifdef CONFIG_SL351x_NAT
5883 +       GMAC_CONFIG3_T  config3_val;
5884 +       #endif
5885 +       GMAC_TX_WCR0_T  hw_weigh;
5886 +       GMAC_TX_WCR1_T  sw_weigh;
5887 +//     GMAC_HASH_ENABLE_REG0_T hash_ctrl;
5888 +//
5889 +#if 0 /* mac address will be set in late_initcall */
5890 +       struct sockaddr sock;
5891 +       // GMAC_AHB_WEIGHT_T    ahb_weight, ahb_weight_mask;
5892 +
5893 +
5894 +       /* set station MAC address1 and address2 */
5895 +       memcpy(&sock.sa_data[0],&eth_mac[tp->port_id][0],6);
5896 +       gmac_set_mac_address(dev,(void *)&sock);
5897 +#endif
5898 +
5899 +       /* set RX_FLTR register to receive all multicast packet */
5900 +       gmac_write_reg(tp->base_addr, GMAC_RX_FLTR, 0x00000007,0x0000001f);
5901 +       //    gmac_write_reg(tp->base_addr, GMAC_RX_FLTR, 0x00000007,0x0000001f);
5902 +       //gmac_write_reg(tp->base_addr, GMAC_RX_FLTR,0x00000007,0x0000001f);
5903 +
5904 +       /* set per packet buffer size */
5905 +       //      config1.bits32 = 0x002004;      //next version
5906 +       /* set flow control threshold */
5907 +       config1.bits32 = 0;
5908 +       config1.bits.set_threshold = 32 / 2;
5909 +       config1.bits.rel_threshold = 32 / 4 * 3;
5910 +       gmac_write_reg(tp->base_addr, GMAC_CONFIG1, config1.bits32, 0xffffffff);
5911 +
5912 +       /* set flow control threshold */
5913 +       config2_val.bits32 = 0;
5914 +       config2_val.bits.set_threshold = TOE_SW_FREEQ_DESC_NUM/2;
5915 +       config2_val.bits.rel_threshold = TOE_SW_FREEQ_DESC_NUM*3/4;
5916 +       gmac_write_reg(tp->base_addr, GMAC_CONFIG2, config2_val.bits32,0xffffffff);
5917 +
5918 +       #ifdef CONFIG_SL351x_NAT
5919 +       /* set HW free queue flow control threshold */
5920 +       config3_val.bits32 = 0;
5921 +       config3_val.bits.set_threshold = PAUSE_SET_HW_FREEQ;
5922 +       config3_val.bits.rel_threshold = PAUSE_REL_HW_FREEQ;
5923 +       gmac_write_reg(tp->base_addr, GMAC_CONFIG3, config3_val.bits32,0xffffffff);
5924 +       #endif
5925 +       /* set_mcast_filter mask*/
5926 +       //      gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,0x0,0xffffffff);
5927 +       //  gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,0x0,0xffffffff);
5928 +
5929 +       /* disable TX/RX and disable internal loop back */
5930 +       config0.bits32 = 0;
5931 +       config0_mask.bits32 = 0;
5932 +
5933 +       //debug_Aaron
5934 +#ifdef L2_jumbo_frame
5935 +       config0.bits.max_len = 5;
5936 +#else
5937 +       config0.bits.max_len = 2;
5938 +#endif
5939 +
5940 +       if (tp->flow_control_enable==1)
5941 +       {
5942 +               config0.bits.tx_fc_en = 1; /* enable tx flow control */
5943 +               config0.bits.rx_fc_en = 1; /* enable rx flow control */
5944 +               printk("Enable MAC Flow Control...\n");
5945 +       }
5946 +       else
5947 +       {
5948 +               config0.bits.tx_fc_en = 0; /* disable tx flow control */
5949 +               config0.bits.rx_fc_en = 0; /* disable rx flow control */
5950 +               printk("Disable MAC Flow Control...\n");
5951 +       }
5952 +       config0.bits.dis_rx = 1;  /* disable rx */
5953 +       config0.bits.dis_tx = 1;  /* disable tx */
5954 +       config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
5955 +       config0.bits.rx_err_detect = 1;
5956 +       config0.bits.rgmii_en = 0;
5957 +       config0.bits.rgmm_edge = 1;
5958 +       config0.bits.rxc_inv = 0;
5959 +       config0.bits.ipv4_rx_chksum = 1;  /* enable H/W to check ip checksum */
5960 +       config0.bits.ipv6_rx_chksum = 1;  /* enable H/W to check ip checksum */
5961 +       config0.bits.port0_chk_hwq = 1; // GaryChen 3/24/2006 2:26PM
5962 +       config0.bits.port1_chk_hwq = 1; // GaryChen 3/24/2006 2:26PM
5963 +       config0.bits.port0_chk_toeq = 1;
5964 +       config0.bits.port1_chk_toeq = 1;
5965 +       config0.bits.port0_chk_classq = 1;
5966 +       config0.bits.port1_chk_classq = 1;
5967 +
5968 +       config0_mask.bits.max_len = 7;
5969 +       config0_mask.bits.tx_fc_en = 1;
5970 +       config0_mask.bits.rx_fc_en = 1;
5971 +       config0_mask.bits.dis_rx = 1;
5972 +       config0_mask.bits.dis_tx = 1;
5973 +       config0_mask.bits.loop_back = 1;
5974 +       config0_mask.bits.rgmii_en = 1;
5975 +       config0_mask.bits.rgmm_edge = 1;
5976 +       config0_mask.bits.rxc_inv = 1;
5977 +       config0_mask.bits.ipv4_rx_chksum = 1;
5978 +       config0_mask.bits.ipv6_rx_chksum = 1;
5979 +       config0_mask.bits.port0_chk_hwq = 1;
5980 +       config0_mask.bits.port1_chk_hwq = 1;
5981 +       config0_mask.bits.port0_chk_toeq = 1;
5982 +       config0_mask.bits.port1_chk_toeq = 1;
5983 +       config0_mask.bits.port0_chk_classq = 1;
5984 +       config0_mask.bits.port1_chk_classq = 1;
5985 +       config0_mask.bits.rx_err_detect = 1;
5986 +
5987 +       #if 0
5988 +       config0.bits.dis_rx = 1;  /* disable rx */
5989 +       config0.bits.dis_tx = 1;  /* disable tx */
5990 +       config0.bits.loop_back = 0; /* enable/disable GMAC loopback */
5991 +       config0.bits.txc_inv = 0;
5992 +       config0.bits.rgmii_en = 0;
5993 +       config0.bits.rgmm_edge = 1;
5994 +       config0.bits.rxc_inv = 1;
5995 +       config0.bits.ipv4_tss_rx_en = 1;  /* enable H/W to check ip checksum */
5996 +       config0.bits.ipv6_tss_rx_en = 1;  /* enable H/W to check ip checksum */
5997 +
5998 +       config0_mask.bits.max_len = 3;
5999 +       config0_mask.bits.tx_fc_en = 1;
6000 +       config0_mask.bits.rx_fc_en = 1;
6001 +       config0_mask.bits.dis_rx = 1;
6002 +       config0_mask.bits.dis_tx = 1;
6003 +       config0_mask.bits.loop_back = 1;
6004 +       config0_mask.bits.rgmii_en = 1;
6005 +       config0_mask.bits.rgmm_edge = 1;
6006 +       config0_mask.bits.txc_inv = 1;
6007 +       config0_mask.bits.rxc_inv = 1;
6008 +       config0_mask.bits.ipv4_tss_rx_en = 1;
6009 +       config0_mask.bits.ipv6_tss_rx_en = 1;
6010 +       #endif
6011 +
6012 +       gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6013 +
6014 +       #if 1
6015 +       hw_weigh.bits32 = 0;
6016 +       hw_weigh.bits.hw_tq3 = 1;
6017 +       hw_weigh.bits.hw_tq2 = 1;
6018 +       hw_weigh.bits.hw_tq1 = 1;
6019 +       hw_weigh.bits.hw_tq0 = 1;
6020 +       gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_0_REG, hw_weigh.bits32, 0xffffffff);
6021 +
6022 +       sw_weigh.bits32 = 0;
6023 +       sw_weigh.bits.sw_tq5 = 1;
6024 +       sw_weigh.bits.sw_tq4 = 1;
6025 +       sw_weigh.bits.sw_tq3 = 1;
6026 +       sw_weigh.bits.sw_tq2 = 1;
6027 +       sw_weigh.bits.sw_tq1 = 1;
6028 +       sw_weigh.bits.sw_tq0 = 1;
6029 +       gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_1_REG, sw_weigh.bits32, 0xffffffff);
6030 +       #endif
6031 +
6032 +       #if 0
6033 +       ahb_weight.bits32 = 0;
6034 +       ahb_weight_mask.bits32 = 0;
6035 +       ahb_weight.bits.rx_weight = 1;
6036 +       ahb_weight.bits.tx_weight = 1;
6037 +       ahb_weight.bits.hash_weight = 1;
6038 +       ahb_weight.bits.pre_req = 0x1f;
6039 +       ahb_weight.bits.tqDV_threshold = 0;
6040 +       ahb_weight_mask.bits.rx_weight = 0x1f;
6041 +       ahb_weight_mask.bits.tx_weight = 0x1f;
6042 +       ahb_weight_mask.bits.hash_weight = 0x1f;
6043 +       ahb_weight_mask.bits.pre_req = 0x1f;
6044 +       ahb_weight_mask.bits.tqDV_threshold = 0x1f;
6045 +       gmac_write_reg(tp->dma_base_addr, GMAC_AHB_WEIGHT_REG, ahb_weight.bits32, ahb_weight_mask.bits32);
6046 +       #endif
6047 +
6048 +       #if defined(CONFIG_SL351x_NAT) || defined(CONFIG_SL351x_RXTOE)
6049 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR0, IPPROTO_TCP, 0xffffffff);
6050 +       #endif
6051 +       #ifdef CONFIG_SL351x_NAT
6052 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR1, IPPROTO_UDP, 0xffffffff);
6053 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR2, IPPROTO_GRE, 0xffffffff);
6054 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR3, 0xff, 0xffffffff);
6055 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR4, 0xff, 0xffffffff);
6056 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR5, 0xff, 0xffffffff);
6057 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR6, 0xff, 0xffffffff);
6058 +       gmac_write_reg(tp->dma_base_addr, GMAC_SPR7, 0xff, 0xffffffff);
6059 +
6060 +       sl351x_nat_init();
6061 +       #endif
6062 +
6063 +       #ifdef CONFIG_SL351x_RXTOE
6064 +       /* setup matching rule to TOE */
6065 +       sl351x_toe_init();
6066 +       #endif
6067 +
6068 +       // for A1 ASIC version
6069 +//     hash_ctrl.bits32 = 0;
6070 +//     hash_ctrl.bits.timing = 6;
6071 +//     gmac_write_reg(tp->dma_base_addr, GMAC_HASH_ENGINE_REG0, hash_ctrl.bits32, 0xffffffff);
6072 +
6073 +       return (0);
6074 +}
6075 +
6076 +/*----------------------------------------------------------------------
6077 +*      toe_gmac_enable_tx_rx
6078 +*----------------------------------------------------------------------*/
6079 +static void toe_gmac_enable_tx_rx(struct net_device *dev)
6080 +{
6081 +       GMAC_INFO_T             *tp = dev->priv;
6082 +       GMAC_CONFIG0_T  config0,config0_mask;
6083 +
6084 +    /* enable TX/RX */
6085 +    config0.bits32 = 0;
6086 +    config0_mask.bits32 = 0;
6087 +    config0.bits.dis_rx = 0;  /* enable rx */
6088 +    config0.bits.dis_tx = 0;  /* enable tx */
6089 +    config0_mask.bits.dis_rx = 1;
6090 +    config0_mask.bits.dis_tx = 1;
6091 +    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6092 +}
6093 +/*----------------------------------------------------------------------
6094 +*      toe_gmac_disable_rx
6095 +*----------------------------------------------------------------------*/
6096 +#if 0
6097 +static void toe_gmac_disable_rx(struct net_device *dev)
6098 +{
6099 +       GMAC_INFO_T             *tp = dev->priv;
6100 +       GMAC_CONFIG0_T  config0,config0_mask;
6101 +
6102 +    /* enable TX/RX */
6103 +    config0.bits32 = 0;
6104 +    config0_mask.bits32 = 0;
6105 +    config0.bits.dis_rx = 1;  /* disable rx */
6106 +//    config0.bits.dis_tx = 1;  /* disable tx */
6107 +    config0_mask.bits.dis_rx = 1;
6108 +//     config0_mask.bits.dis_tx = 1;
6109 +    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6110 +}
6111 +#endif
6112 +/*----------------------------------------------------------------------
6113 +*      toe_gmac_enable_rx
6114 +*----------------------------------------------------------------------*/
6115 +#if 0
6116 +static void toe_gmac_enable_rx(struct net_device *dev)
6117 +{
6118 +       GMAC_INFO_T             *tp = dev->priv;
6119 +       GMAC_CONFIG0_T  config0,config0_mask;
6120 +
6121 +    /* enable TX/RX */
6122 +    config0.bits32 = 0;
6123 +    config0_mask.bits32 = 0;
6124 +    config0.bits.dis_rx = 0;  /* enable rx */
6125 +//    config0.bits.dis_tx = 0;  /* enable tx */
6126 +    config0_mask.bits.dis_rx = 1;
6127 +//    config0_mask.bits.dis_tx = 1;
6128 +    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6129 +}
6130 +#endif
6131 +/*----------------------------------------------------------------------
6132 +*      toe_gmac_disable_tx_rx
6133 +*----------------------------------------------------------------------*/
6134 +static void toe_gmac_disable_tx_rx(struct net_device *dev)
6135 +{
6136 +       GMAC_INFO_T             *tp = dev->priv;
6137 +       GMAC_CONFIG0_T  config0,config0_mask;
6138 +
6139 +    /* enable TX/RX */
6140 +    config0.bits32 = 0;
6141 +    config0_mask.bits32 = 0;
6142 +    config0.bits.dis_rx = 1;  /* disable rx */
6143 +    config0.bits.dis_tx = 1;  /* disable tx */
6144 +    config0_mask.bits.dis_rx = 1;
6145 +    config0_mask.bits.dis_tx = 1;
6146 +    gmac_write_reg(tp->base_addr, GMAC_CONFIG0, config0.bits32,config0_mask.bits32);
6147 +}
6148 +
6149 +/*----------------------------------------------------------------------
6150 +*      toe_gmac_hw_start
6151 +*----------------------------------------------------------------------*/
6152 +static void toe_gmac_hw_start(struct net_device *dev)
6153 +{
6154 +       GMAC_INFO_T                             *tp = (GMAC_INFO_T *)dev->priv;
6155 +       GMAC_DMA_CTRL_T                 dma_ctrl, dma_ctrl_mask;
6156 +
6157 +
6158 +    /* program dma control register */
6159 +       dma_ctrl.bits32 = 0;
6160 +       dma_ctrl.bits.rd_enable = 1;
6161 +       dma_ctrl.bits.td_enable = 1;
6162 +       dma_ctrl.bits.loopback = 0;
6163 +       dma_ctrl.bits.drop_small_ack = 0;
6164 +       dma_ctrl.bits.rd_prot = 0;
6165 +       dma_ctrl.bits.rd_burst_size = 3;
6166 +       dma_ctrl.bits.rd_insert_bytes = RX_INSERT_BYTES;
6167 +       dma_ctrl.bits.rd_bus = 3;
6168 +       dma_ctrl.bits.td_prot = 0;
6169 +       dma_ctrl.bits.td_burst_size = 3;
6170 +       dma_ctrl.bits.td_bus = 3;
6171 +
6172 +       dma_ctrl_mask.bits32 = 0;
6173 +       dma_ctrl_mask.bits.rd_enable = 1;
6174 +       dma_ctrl_mask.bits.td_enable = 1;
6175 +       dma_ctrl_mask.bits.loopback = 1;
6176 +       dma_ctrl_mask.bits.drop_small_ack = 1;
6177 +       dma_ctrl_mask.bits.rd_prot = 3;
6178 +       dma_ctrl_mask.bits.rd_burst_size = 3;
6179 +       dma_ctrl_mask.bits.rd_insert_bytes = 3;
6180 +       dma_ctrl_mask.bits.rd_bus = 3;
6181 +       dma_ctrl_mask.bits.td_prot = 0x0f;
6182 +       dma_ctrl_mask.bits.td_burst_size = 3;
6183 +       dma_ctrl_mask.bits.td_bus = 3;
6184 +
6185 +       gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6186 +
6187 +    return;
6188 +}
6189 +
6190 +/*----------------------------------------------------------------------
6191 +*      toe_gmac_hw_stop
6192 +*----------------------------------------------------------------------*/
6193 +static void toe_gmac_hw_stop(struct net_device *dev)
6194 +{
6195 +       GMAC_INFO_T                     *tp = (GMAC_INFO_T *)dev->priv;
6196 +       GMAC_DMA_CTRL_T         dma_ctrl, dma_ctrl_mask;
6197 +
6198 +    /* program dma control register */
6199 +       dma_ctrl.bits32 = 0;
6200 +       dma_ctrl.bits.rd_enable = 0;
6201 +       dma_ctrl.bits.td_enable = 0;
6202 +
6203 +       dma_ctrl_mask.bits32 = 0;
6204 +       dma_ctrl_mask.bits.rd_enable = 1;
6205 +       dma_ctrl_mask.bits.td_enable = 1;
6206 +
6207 +       gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6208 +}
6209 +
6210 +/*----------------------------------------------------------------------
6211 +*      toe_gmac_clear_counter
6212 +*----------------------------------------------------------------------*/
6213 +static int toe_gmac_clear_counter (struct net_device *dev)
6214 +{
6215 +       GMAC_INFO_T     *tp = (GMAC_INFO_T *)dev->priv;
6216 +
6217 +    /* clear counter */
6218 +    gmac_read_reg(tp->base_addr, GMAC_IN_DISCARDS);
6219 +    gmac_read_reg(tp->base_addr, GMAC_IN_ERRORS);
6220 +    gmac_read_reg(tp->base_addr, GMAC_IN_MCAST);
6221 +    gmac_read_reg(tp->base_addr, GMAC_IN_BCAST);
6222 +    gmac_read_reg(tp->base_addr, GMAC_IN_MAC1);
6223 +    gmac_read_reg(tp->base_addr, GMAC_IN_MAC2);
6224 +               tp->ifStatics.tx_bytes = 0;
6225 +               tp->ifStatics.tx_packets = 0;
6226 +               tp->ifStatics.tx_errors = 0;
6227 +               tp->ifStatics.rx_bytes = 0;
6228 +               tp->ifStatics.rx_packets = 0;
6229 +               tp->ifStatics.rx_errors = 0;
6230 +               tp->ifStatics.rx_dropped = 0;
6231 +       return (0);
6232 +}
6233 +
6234 +
6235 +/*----------------------------------------------------------------------
6236 +*      toe_gmac_tx_complete
6237 +*----------------------------------------------------------------------*/
6238 +static  void toe_gmac_tx_complete(GMAC_INFO_T *tp, unsigned int tx_qid,
6239 +                                                                               struct net_device *dev, int interrupt)
6240 +{
6241 +       volatile GMAC_TXDESC_T  *curr_desc;
6242 +       GMAC_TXDESC_0_T                 word0;
6243 +       GMAC_TXDESC_1_T                 word1;
6244 +       unsigned int                    desc_count;
6245 +//     struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
6246 +       GMAC_SWTXQ_T                    *swtxq;
6247 +       DMA_RWPTR_T                             rwptr;
6248 +
6249 +       /* get tx H/W completed descriptor virtual address */
6250 +       /* check tx status and accumulate tx statistics */
6251 +       swtxq = &tp->swtxq[tx_qid];
6252 +       swtxq->intr_cnt++;
6253 +       for (;;)
6254 +       {
6255 +               rwptr.bits32 = readl(swtxq->rwptr_reg);
6256 +               if (rwptr.bits.rptr == swtxq->finished_idx)
6257 +                       break;
6258 +       curr_desc = (volatile GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
6259 +//             consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
6260 +               word0.bits32 = curr_desc->word0.bits32;
6261 +               word1.bits32 = curr_desc->word1.bits32;
6262 +
6263 +               if (word0.bits.status_tx_ok)
6264 +               {
6265 +                       tp->ifStatics.tx_bytes += word1.bits.byte_count;
6266 +                       desc_count = word0.bits.desc_count;
6267 +                       if (desc_count==0)
6268 +                       {
6269 +                               printk("%s::Desc 0x%x = 0x%x, desc_count=%d\n",__func__, (u32)curr_desc, word0.bits32, desc_count);
6270 +                               while(1);
6271 +                       }
6272 +                       while (--desc_count)
6273 +                       {
6274 +                               word0.bits.status_tx_ok = 0;
6275 +                               curr_desc->word0.bits32 = word0.bits32;
6276 +                               swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
6277 +                               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
6278 +                               word0.bits32 = curr_desc->word0.bits32;
6279 +#ifdef _DUMP_TX_TCP_CONTENT
6280 +                               if (curr_desc->word0.bits.buffer_size < 16)
6281 +                               {
6282 +                                       int a;
6283 +                                       char *datap;
6284 +                                       printk("\t Tx Finished Desc 0x%x Len %d Addr 0x%08x: ", (u32)curr_desc, curr_desc->word0.bits.buffer_size, curr_desc->word2.buf_adr);
6285 +                                       datap = (char *)__va(curr_desc->word2.buf_adr);
6286 +                                       for (a=0; a<8 && a<curr_desc->word0.bits.buffer_size; a++, datap++)
6287 +                                       {
6288 +                                               printk("0x%02x ", *datap);
6289 +                                       }
6290 +                                       printk("\n");
6291 +                               }
6292 +#endif
6293 +                       }
6294 +
6295 +                       word0.bits.status_tx_ok = 0;
6296 +                       if (swtxq->tx_skb[swtxq->finished_idx])
6297 +                       {
6298 +                               if (interrupt)
6299 +                                       dev_kfree_skb_irq(swtxq->tx_skb[swtxq->finished_idx]);
6300 +                               else
6301 +                                       dev_kfree_skb(swtxq->tx_skb[swtxq->finished_idx]);
6302 +                               swtxq->tx_skb[swtxq->finished_idx] = NULL;
6303 +                       }
6304 +                       curr_desc->word0.bits32 = word0.bits32;
6305 +                       swtxq->curr_finished_desc = (GMAC_TXDESC_T *)curr_desc;
6306 +                       swtxq->total_finished++;
6307 +                       tp->ifStatics.tx_packets++;
6308 +                       swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
6309 +               }
6310 +               else
6311 +               {
6312 +                       // tp->ifStatics.tx_errors++;
6313 +                       // printk("%s::Tx Descriptor is !!!\n",__func__);
6314 +                       // wait ready by breaking
6315 +                       break;
6316 +               }
6317 +       }
6318 +
6319 +       if (netif_queue_stopped(dev))
6320 +       {
6321 +               netif_wake_queue(dev);
6322 +       }
6323 +}
6324 +
6325 +/*----------------------------------------------------------------------
6326 +*      gmac_start_xmit
6327 +*----------------------------------------------------------------------*/
6328 +static int gmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
6329 +{
6330 +       GMAC_INFO_T                     *tp= dev->priv;
6331 +//     static unsigned int     pcount = 0;
6332 +//     unsigned int                    tx_qid;
6333 +    DMA_RWPTR_T                                rwptr;
6334 +       volatile GMAC_TXDESC_T  *curr_desc;
6335 +       int                                     snd_pages = skb_shinfo(skb)->nr_frags + 1;  /* get number of descriptor */
6336 +       int                                     frag_id = 0;
6337 +       int                                     len, total_len = skb->len;
6338 +       struct net_device_stats *isPtr;
6339 +       unsigned int                    free_desc;
6340 +       GMAC_SWTXQ_T                    *swtxq;
6341 +       register unsigned long  word0, word1, word2, word3;
6342 +       unsigned short                  wptr, rptr;
6343 +#ifdef L2_jumbo_frame
6344 +       int header_len = skb->len;
6345 +       struct iphdr    *ip_hdr;
6346 +    struct tcphdr      *tcp_hdr;
6347 +    int             tcp_hdr_len;
6348 +    unsigned char      *ptr;
6349 +    int             data_len,a;
6350 +    unsigned int    val;
6351 +#endif
6352 +
6353 +#ifdef GMAC_LEN_1_2_ISSUE
6354 +       int                                             total_pages;
6355 +       total_pages = snd_pages;
6356 +#endif
6357 +
6358 +       isPtr = (struct net_device_stats *)&tp->ifStatics;
6359 +#if 1
6360 +       if (skb->len >= 0x10000)
6361 +       {
6362 +//             spin_unlock(&tp->tx_mutex);
6363 +               isPtr->tx_dropped++;
6364 +               printk("%s::[GMAC %d] skb->len %d >= 64K\n", __func__, tp->port_id, skb->len);
6365 +               netif_stop_queue(dev);
6366 +               return 1;
6367 +    }
6368 +#endif
6369 +
6370 +#if 0
6371 +       if (storlink_ctl.recvfile==2)
6372 +       {
6373 +           printk("snd_pages=%d skb->len=%d\n",snd_pages,skb->len);
6374 +       }
6375 +#endif
6376 +
6377 +#ifdef GMAC_USE_TXQ0
6378 +       #define tx_qid  0
6379 +#endif
6380 +
6381 +       swtxq = &tp->swtxq[tx_qid];
6382 +
6383 +//     spin_lock(&tp->tx_mutex);
6384 +    rwptr.bits32 = readl(swtxq->rwptr_reg);
6385 +       wptr = rwptr.bits.wptr;
6386 +       rptr = rwptr.bits.rptr;
6387 +
6388 +       // check finished desc or empty BD
6389 +       // cannot check by read ptr of RW PTR register,
6390 +       // because the HW complete to send but the SW may NOT handle it
6391 +#ifndef        GMAX_TX_INTR_DISABLED
6392 +       if (wptr >= swtxq->finished_idx)
6393 +               free_desc = swtxq->total_desc_num - wptr - 1 + swtxq->finished_idx;
6394 +       else
6395 +               free_desc = swtxq->finished_idx - wptr - 1;
6396 +
6397 +       if (free_desc < snd_pages)
6398 +       {
6399 +//             spin_unlock(&tp->tx_mutex);
6400 +               isPtr->tx_dropped++;
6401 +//             printk("GMAC %d No available descriptor!\n", tp->port_id);
6402 +               netif_stop_queue(dev);
6403 +               return 1;
6404 +    }
6405 +#else
6406 +       toe_gmac_tx_complete(tp, tx_qid, dev, 0);
6407 +
6408 +       if (wptr >= swtxq->finished_idx)
6409 +               free_desc = swtxq->total_desc_num - wptr - 1 + swtxq->finished_idx;
6410 +       else
6411 +               free_desc = swtxq->finished_idx - wptr - 1;
6412 +       if (free_desc < snd_pages)
6413 +       {
6414 +//             spin_unlock(&tp->tx_mutex);
6415 +               isPtr->tx_dropped++;
6416 +//             printk("GMAC %d No available descriptor!\n", tp->port_id);
6417 +               netif_stop_queue(dev);
6418 +               return 1;
6419 +    }
6420 +
6421 +#if 0
6422 +       printk("1: free_desc=%d, wptr=%d, finished_idx=%d\n", free_desc, wptr, swtxq->finished_idx);
6423 +       if ((free_desc < (snd_pages << 2)) ||
6424 +           (free_desc < (swtxq->total_desc_num >> 2)))
6425 +       {
6426 +               printk("2: free_desc = %d\n", free_desc);
6427 +               toe_gmac_tx_complete(tp, tx_qid, dev, 0);
6428 +               rwptr.bits32 = readl(swtxq->rwptr_reg);
6429 +               wptr = rwptr.bits.wptr;
6430 +               if (wptr>= swtxq->finished_idx)
6431 +                       free_desc = swtxq->total_desc_num - wptr -1 + swtxq->finished_idx;
6432 +               else
6433 +                       free_desc = swtxq->finished_idx - wptr - 1;
6434 +       }
6435 +#endif
6436 +#endif
6437 +
6438 +#ifdef L2_jumbo_frame
6439 +//             data_len = skb->len - 14 - ip_hdr->ihl *4 - tcp_hdr_len;
6440 +//             if ((skb->nh.iph->protocol == __constant_htons(ETH_P_IP)) && ((skb->nh.iph->protocol & 0x00ff)  == IPPROTO_TCP))
6441 +//             if (skb->nh.iph->protocol == 0x006 && (skb->nh.iph->protocol == __constant_htons(ETH_P_IP)))
6442 +               if (((skb->nh.iph->protocol & 0x00ff)  == IPPROTO_TCP))
6443 +               {
6444 +                               ip_hdr = (struct iphdr*)(skb->nh.iph);
6445 +                               tcp_hdr = (struct tcphdr*)(skb->h.th);
6446 +                               tcp_hdr_len = TCPHDRLEN(tcp_hdr) * 4;
6447 +                               tcp_hdr_len = TCPHDRLEN(tcp_hdr) * 4;
6448 +
6449 +                               if ((skb->h.th->syn) && (tcp_hdr_len > 20))
6450 +                               {
6451 +                                       ptr = (unsigned char *)(tcp_hdr+1);
6452 +                                       if ((ptr[0] == 0x02) && (ptr[1] == 0x04) && (ptr[2] == 0x07) && (ptr[3] == 0xba)) // 0x07 aa=2016-54=1962  ,0x07ba=2032-54=1978
6453 +                                       {
6454 +                                               ptr[2]=0x20;    //23
6455 +                                               ptr[3]=0x00;    //00
6456 +                                               printk("-----> Change MSS to 8K \n" );
6457 +                                       }
6458 +                               }
6459 +               }
6460 +//             if ((ip_hdr->protocol & 0x00ff) != IPPROTO_TCP)
6461 +//             if ((tcp_hdr_len > 20) && (skb->h.th->syn))
6462 +#endif
6463 +
6464 +
6465 +#if 0
6466 +       if (snd_pages > 1)
6467 +               printk("-----> snd_pages=%d\n", snd_pages);
6468 +       if (total_len > 1514)
6469 +       {
6470 +               printk("-----> total_len=%d\n", total_len);
6471 +       }
6472 +#endif
6473 +
6474 +    while (snd_pages)
6475 +    {
6476 +       char *pkt_datap;
6477 +
6478 +       curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + wptr;
6479 +//             consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_FROMDEVICE);
6480 +#if 0
6481 +//#if (GMAC_DEBUG==1)
6482 +       // if curr_desc->word2.buf_adr !=0 means that the ISR does NOT handle it
6483 +       // if (curr_desc->word2.buf_adr)
6484 +       if (swtxq->tx_skb[wptr])
6485 +       {
6486 +               printk("Error! Stop due to TX descriptor's buffer is not freed!\n");
6487 +               while(1);
6488 +               dev_kfree_skb(swtxq->tx_skb[wptr]);
6489 +               swtxq->tx_skb[wptr] = NULL;
6490 +               }
6491 +#endif
6492 +
6493 +               if (frag_id == 0)
6494 +               {
6495 +#if 0
6496 +                       int i;
6497 +                       pkt_datap = skb->data;
6498 +                       len = total_len;
6499 +                       for (i=0; i<skb_shinfo(skb)->nr_frags; i++)
6500 +                       {
6501 +                               skb_frag_t* frag = &skb_shinfo(skb)->frags[i];
6502 +                               len -= frag->size;
6503 +                       }
6504 +#else
6505 +                       pkt_datap = skb->data;
6506 +                       len = total_len - skb->data_len;
6507 +#endif
6508 +               }
6509 +               else
6510 +               {
6511 +                       skb_frag_t* frag = &skb_shinfo(skb)->frags[frag_id-1];
6512 +                       pkt_datap = page_address(frag->page) + frag->page_offset;
6513 +                       len = frag->size;
6514 +                       if (len > total_len)
6515 +                       {
6516 +                               printk("===> Fatal Error! Send Frag size %d > Total Size %d!!!!!\n",
6517 +                                       len, total_len);
6518 +                       }
6519 +               }
6520 +
6521 +               /* set TX descriptor */
6522 +               /* copy packet to descriptor buffer address */
6523 +               // curr_desc->word0.bits32 = len;    /* total frame byte count */
6524 +               word0 = len;
6525 +#ifdef L2_jumbo_frame
6526 +               word3 = (dev->mtu+14) | EOFIE_BIT;  //2016 ,2032
6527 +#else
6528 +               word3 = 1514 | EOFIE_BIT;
6529 +#endif
6530 +
6531 +#ifdef DO_HW_CHKSUM
6532 +#ifdef L2_jumbo_frame
6533 +               if (total_len >= (dev->mtu+14) && (skb->nh.iph->protocol == 0x011) && skb->nh.iph && (skb->nh.iph->frag_off & __constant_htons(0x3fff)))
6534 +#else
6535 +               if (total_len <= 1514 && skb->nh.iph && (skb->nh.iph->frag_off & __constant_htons(0x3fff)))
6536 +#endif
6537 +                       word1  = total_len |
6538 +                                       TSS_IP_CHKSUM_BIT  |
6539 +                                       TSS_IPV6_ENABLE_BIT |
6540 +                                       TSS_MTU_ENABLE_BIT;
6541 +               else
6542 +                       word1 = total_len |
6543 +                                       TSS_UDP_CHKSUM_BIT |
6544 +                                       TSS_TCP_CHKSUM_BIT |
6545 +                                       TSS_IP_CHKSUM_BIT  |
6546 +                                       TSS_IPV6_ENABLE_BIT |
6547 +                                       TSS_MTU_ENABLE_BIT;
6548 +#else
6549 +               word1 = total_len | TSS_MTU_ENABLE_BIT;
6550 +#endif
6551 +               word2 = (unsigned long)__pa(pkt_datap);
6552 +
6553 +               if (frag_id == 0)
6554 +               {
6555 +                       word3 |= SOF_BIT;       // SOF
6556 +               }
6557 +
6558 +               if (snd_pages == 1)
6559 +               {
6560 +                       word3 |= EOF_BIT;       // EOF
6561 +                       swtxq->tx_skb[wptr] = skb;
6562 +#ifdef CONFIG_SL351x_NAT
6563 +                       if (nat_cfg.enabled && sl351x_nat_output(skb, tp->port_id))
6564 +                               word1 |= TSS_IP_FIXED_LEN_BIT;
6565 +#endif
6566 +               }
6567 +               else
6568 +                       swtxq->tx_skb[wptr] = NULL;
6569 +               // word1 |= TSS_IP_FIXED_LEN_BIT;
6570 +#if 1
6571 +#ifdef CONFIG_SL351x_RXTOE
6572 +               // check if this frame has the mission to enable toe hash entry..
6573 +               // if rx_max_pktsize ==0, do not enable RXTOE
6574 +               if (TCP_SKB_CB(skb)->connection && storlink_ctl.rx_max_pktsize) {
6575 +                       set_toeq_hdr(TCP_SKB_CB(skb)->connection, &toe_private_data, dev);
6576 +               }
6577 +#endif
6578 +#endif
6579 +#ifdef _DUMP_TX_TCP_CONTENT
6580 +               if (len < 16 && frag_id && skb->h.th && (skb->h.th->source == __constant_htons(445) || skb->h.th->source == __constant_htons(139)))
6581 +               {
6582 +                       int a;
6583 +                       char *datap;
6584 +                       printk("Tx Desc 0x%x Frag %d Len %d [IP-ID 0x%x] 0x%08x: ", (u32)curr_desc, frag_id, len, htons(skb->nh.iph->id), (u32)pkt_datap);
6585 +                       datap = (char *)pkt_datap;
6586 +                       for (a=0; a<8 && a<len; a++, datap++)
6587 +                       {
6588 +                               printk("0x%02x ", *datap);
6589 +                       }
6590 +                       printk("\n");
6591 +               }
6592 +#endif
6593 +
6594 +#ifdef GMAC_LEN_1_2_ISSUE
6595 +               if ((total_pages!=snd_pages) && (len == 1 || len == 2 ) && ((u32)pkt_datap & 0x03))
6596 +               {
6597 +                       memcpy((void *)&_debug_prefetch_buf[_debug_prefetch_cnt][0], pkt_datap, len);
6598 +                       pkt_datap = (char *)&_debug_prefetch_buf[_debug_prefetch_cnt][0];
6599 +                       word2 = (unsigned long)__pa(pkt_datap);
6600 +                       _debug_prefetch_cnt++;
6601 +                       if (_debug_prefetch_cnt >= _DEBUG_PREFETCH_NUM)
6602 +                               _debug_prefetch_cnt = 0;
6603 +               }
6604 +#endif
6605 +
6606 +               consistent_sync((void *)pkt_datap, len, PCI_DMA_TODEVICE);
6607 +               wmb();
6608 +               curr_desc->word0.bits32 = word0;
6609 +               curr_desc->word1.bits32 = word1;
6610 +               curr_desc->word2.bits32 = word2;
6611 +               curr_desc->word3.bits32 = word3;
6612 +               swtxq->curr_tx_desc = (GMAC_TXDESC_T *)curr_desc;
6613 +//             consistent_sync((void *)curr_desc, sizeof(GMAC_TXDESC_T), PCI_DMA_TODEVICE);
6614 +#ifdef _DUMP_TX_TCP_CONTENT
6615 +               if (len < 16 && frag_id && skb->h.th && (skb->h.th->source == __constant_htons(445) || skb->h.th->source == __constant_htons(139)))
6616 +               {
6617 +                       int a;
6618 +                       char *datap;
6619 +                       printk("\t 0x%08x: ", (u32)pkt_datap);
6620 +                       datap = (char *)pkt_datap;
6621 +                       for (a=0; a<8 && a<len; a++, datap++)
6622 +                       {
6623 +                               printk("0x%02x ", *datap);
6624 +                       }
6625 +                       printk("\n");
6626 +               }
6627 +#endif
6628 +               free_desc--;
6629 +               wmb();
6630 +               wptr = RWPTR_ADVANCE_ONE(wptr, swtxq->total_desc_num);
6631 +               frag_id++;
6632 +               snd_pages--;
6633 +       }
6634 +
6635 +    swtxq->total_sent++;
6636 +       SET_WPTR(swtxq->rwptr_reg, wptr);
6637 +       dev->trans_start = jiffies;
6638 +
6639 +
6640 +       // printk("MAC %d Qid %d rwptr = 0x%x, curr_desc=0x%x\n", skb->tx_port_id, tx_qid, rwptr.bits32, curr_desc);
6641 +//#ifdef       GMAX_TX_INTR_DISABLED
6642 +//             toe_gmac_tx_complete(tp, tx_qid, dev, 0);
6643 +//#endif
6644 +       return (0);
6645 +}
6646 +
6647 +/*----------------------------------------------------------------------
6648 +* gmac_set_mac_address
6649 +*----------------------------------------------------------------------*/
6650 +
6651 +static int gmac_set_mac_address(struct net_device *dev, void *addr)
6652 +{
6653 +       GMAC_INFO_T             *tp= dev->priv;
6654 +       struct sockaddr *sock;
6655 +       unsigned int    reg_val;
6656 +    unsigned int    i;
6657 +
6658 +       sock = (struct sockaddr *) addr;
6659 +       for (i = 0; i < 6; i++)
6660 +       {
6661 +               dev->dev_addr[i] = sock->sa_data[i];
6662 +       }
6663 +
6664 +    reg_val = dev->dev_addr[0] + (dev->dev_addr[1]<<8) + (dev->dev_addr[2]<<16) + (dev->dev_addr[3]<<24);
6665 +    gmac_write_reg(tp->base_addr,GMAC_STA_ADD0,reg_val,0xffffffff);
6666 +    reg_val = dev->dev_addr[4] + (dev->dev_addr[5]<<8);
6667 +    gmac_write_reg(tp->base_addr,GMAC_STA_ADD1,reg_val,0x0000ffff);
6668 +       memcpy(&eth_mac[tp->port_id][0],&dev->dev_addr[0],6);
6669 +
6670 +    printk("Storlink %s address = ",dev->name);
6671 +    printk("%02x",dev->dev_addr[0]);
6672 +    printk("%02x",dev->dev_addr[1]);
6673 +    printk("%02x",dev->dev_addr[2]);
6674 +    printk("%02x",dev->dev_addr[3]);
6675 +    printk("%02x",dev->dev_addr[4]);
6676 +    printk("%02x\n",dev->dev_addr[5]);
6677 +
6678 +    return (0);
6679 +}
6680 +
6681 +/*----------------------------------------------------------------------
6682 +* gmac_get_mac_address
6683 +*      get mac address from FLASH
6684 +*----------------------------------------------------------------------*/
6685 +static void gmac_get_mac_address(void)
6686 +{
6687 +#ifdef CONFIG_MTD
6688 +       extern int get_vlaninfo(vlaninfo* vlan);
6689 +    static vlaninfo    vlan[2];
6690 +
6691 +    if (get_vlaninfo(&vlan[0]))
6692 +    {
6693 +        memcpy((void *)&eth_mac[0][0],vlan[0].mac,6);
6694 +        // VLAN_conf[0].vid = vlan[0].vlanid;
6695 +        // VLAN_conf[0].portmap = vlan[0].vlanmap;
6696 +        memcpy((void *)&eth_mac[1][0],vlan[1].mac,6);
6697 +        // VLAN_conf[1].vid = vlan[1].vlanid;
6698 +        // VLAN_conf[1].portmap = vlan[1].vlanmap;
6699 +    }
6700 +#else
6701 +    unsigned int reg_val;
6702 +
6703 +    reg_val = readl(IO_ADDRESS(TOE_GMAC0_BASE)+0xac);
6704 +    eth_mac[0][4] = (reg_val & 0xff00) >> 8;
6705 +    eth_mac[0][5] = reg_val & 0x00ff;
6706 +    reg_val = readl(IO_ADDRESS(SL2312_SECURITY_BASE)+0xac);
6707 +    eth_mac[1][4] = (reg_val & 0xff00) >> 8;
6708 +    eth_mac[1][5] = reg_val & 0x00ff;
6709 +#endif
6710 +    return;
6711 +}
6712 +
6713 +
6714 +/*----------------------------------------------------------------------
6715 +* mac_stop_txdma
6716 +*----------------------------------------------------------------------*/
6717 +void mac_stop_txdma(struct net_device *dev)
6718 +{
6719 +       GMAC_INFO_T                             *tp = (GMAC_INFO_T *)dev->priv;
6720 +       GMAC_DMA_CTRL_T                 dma_ctrl, dma_ctrl_mask;
6721 +       GMAC_TXDMA_FIRST_DESC_T txdma_busy;
6722 +
6723 +       // wait idle
6724 +       do
6725 +       {
6726 +               txdma_busy.bits32 = gmac_read_reg(tp->dma_base_addr, GMAC_DMA_TX_FIRST_DESC_REG);
6727 +       } while (txdma_busy.bits.td_busy);
6728 +
6729 +    /* program dma control register */
6730 +       dma_ctrl.bits32 = 0;
6731 +       dma_ctrl.bits.rd_enable = 0;
6732 +       dma_ctrl.bits.td_enable = 0;
6733 +
6734 +       dma_ctrl_mask.bits32 = 0;
6735 +       dma_ctrl_mask.bits.rd_enable = 1;
6736 +       dma_ctrl_mask.bits.td_enable = 1;
6737 +
6738 +       gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6739 +}
6740 +
6741 +/*----------------------------------------------------------------------
6742 +* mac_start_txdma
6743 +*----------------------------------------------------------------------*/
6744 +void mac_start_txdma(struct net_device *dev)
6745 +{
6746 +       GMAC_INFO_T                     *tp = (GMAC_INFO_T *)dev->priv;
6747 +       GMAC_DMA_CTRL_T         dma_ctrl, dma_ctrl_mask;
6748 +
6749 +    /* program dma control register */
6750 +       dma_ctrl.bits32 = 0;
6751 +       dma_ctrl.bits.rd_enable = 1;
6752 +       dma_ctrl.bits.td_enable = 1;
6753 +
6754 +       dma_ctrl_mask.bits32 = 0;
6755 +       dma_ctrl_mask.bits.rd_enable = 1;
6756 +       dma_ctrl_mask.bits.td_enable = 1;
6757 +
6758 +       gmac_write_reg(tp->dma_base_addr, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6759 +}
6760 +
6761 +
6762 +/*----------------------------------------------------------------------
6763 +* gmac_get_stats
6764 +*----------------------------------------------------------------------*/
6765 +
6766 +struct net_device_stats * gmac_get_stats(struct net_device *dev)
6767 +{
6768 +    GMAC_INFO_T *tp = (GMAC_INFO_T *)dev->priv;
6769 +    // unsigned int        flags;
6770 +    unsigned int        pkt_drop;
6771 +    unsigned int        pkt_error;
6772 +
6773 +    if (netif_running(dev))
6774 +    {
6775 +        /* read H/W counter */
6776 +        // spin_lock_irqsave(&tp->lock,flags);
6777 +        pkt_drop = gmac_read_reg(tp->base_addr,GMAC_IN_DISCARDS);
6778 +        pkt_error = gmac_read_reg(tp->base_addr,GMAC_IN_ERRORS);
6779 +        tp->ifStatics.rx_dropped = tp->ifStatics.rx_dropped + pkt_drop;
6780 +        tp->ifStatics.rx_errors = tp->ifStatics.rx_errors + pkt_error;
6781 +        // spin_unlock_irqrestore(&tp->lock,flags);
6782 +    }
6783 +    return &tp->ifStatics;
6784 +}
6785 +
6786 +
6787 +
6788 +/*----------------------------------------------------------------------
6789 +* mac_get_sw_tx_weight
6790 +*----------------------------------------------------------------------*/
6791 +void mac_get_sw_tx_weight(struct net_device *dev, char *weight)
6792 +{
6793 +       GMAC_TX_WCR1_T  sw_weigh;
6794 +    GMAC_INFO_T                *tp = (GMAC_INFO_T *)dev->priv;
6795 +
6796 +       sw_weigh.bits32 = gmac_read_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_1_REG);
6797 +
6798 +       weight[0] = sw_weigh.bits.sw_tq0;
6799 +       weight[1] = sw_weigh.bits.sw_tq1;
6800 +       weight[2] = sw_weigh.bits.sw_tq2;
6801 +       weight[3] = sw_weigh.bits.sw_tq3;
6802 +       weight[4] = sw_weigh.bits.sw_tq4;
6803 +       weight[5] = sw_weigh.bits.sw_tq5;
6804 +}
6805 +
6806 +/*----------------------------------------------------------------------
6807 +* mac_set_sw_tx_weight
6808 +*----------------------------------------------------------------------*/
6809 +void mac_set_sw_tx_weight(struct net_device *dev, char *weight)
6810 +{
6811 +       GMAC_TX_WCR1_T  sw_weigh;
6812 +    GMAC_INFO_T                *tp = (GMAC_INFO_T *)dev->priv;
6813 +
6814 +       sw_weigh.bits32 = 0;
6815 +       sw_weigh.bits.sw_tq0 = weight[0];
6816 +       sw_weigh.bits.sw_tq1 = weight[1];
6817 +       sw_weigh.bits.sw_tq2 = weight[2];
6818 +       sw_weigh.bits.sw_tq3 = weight[3];
6819 +       sw_weigh.bits.sw_tq4 = weight[4];
6820 +       sw_weigh.bits.sw_tq5 = weight[5];
6821 +
6822 +       gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_1_REG, sw_weigh.bits32, 0xffffffff);
6823 +}
6824 +
6825 +/*----------------------------------------------------------------------
6826 +* mac_get_hw_tx_weight
6827 +*----------------------------------------------------------------------*/
6828 +void mac_get_hw_tx_weight(struct net_device *dev, char *weight)
6829 +{
6830 +       GMAC_TX_WCR0_T  hw_weigh;
6831 +    GMAC_INFO_T                *tp = (GMAC_INFO_T *)dev->priv;
6832 +
6833 +       hw_weigh.bits32 = gmac_read_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_0_REG);
6834 +
6835 +       weight[0] = hw_weigh.bits.hw_tq0;
6836 +       weight[1] = hw_weigh.bits.hw_tq1;
6837 +       weight[2] = hw_weigh.bits.hw_tq2;
6838 +       weight[3] = hw_weigh.bits.hw_tq3;
6839 +}
6840 +
6841 +/*----------------------------------------------------------------------
6842 +* mac_set_hw_tx_weight
6843 +*----------------------------------------------------------------------*/
6844 +void mac_set_hw_tx_weight(struct net_device *dev, char *weight)
6845 +{
6846 +       GMAC_TX_WCR0_T  hw_weigh;
6847 +    GMAC_INFO_T                *tp = (GMAC_INFO_T *)dev->priv;
6848 +
6849 +       hw_weigh.bits32 = 0;
6850 +       hw_weigh.bits.hw_tq0 = weight[0];
6851 +       hw_weigh.bits.hw_tq1 = weight[1];
6852 +       hw_weigh.bits.hw_tq2 = weight[2];
6853 +       hw_weigh.bits.hw_tq3 = weight[3];
6854 +
6855 +       gmac_write_reg(tp->dma_base_addr, GMAC_TX_WEIGHTING_CTRL_0_REG, hw_weigh.bits32, 0xffffffff);
6856 +}
6857 +
6858 +/*----------------------------------------------------------------------
6859 +* mac_start_tx_dma
6860 +*----------------------------------------------------------------------*/
6861 +int mac_start_tx_dma(int mac)
6862 +{
6863 +       GMAC_DMA_CTRL_T dma_ctrl, dma_ctrl_mask;
6864 +
6865 +       dma_ctrl.bits32 = 0;
6866 +       dma_ctrl.bits.td_enable = 1;
6867 +
6868 +       dma_ctrl_mask.bits32 = 0;
6869 +       dma_ctrl_mask.bits.td_enable = 1;
6870 +
6871 +       if (mac == 0)
6872 +       gmac_write_reg(TOE_GMAC0_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6873 +       else
6874 +       gmac_write_reg(TOE_GMAC1_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6875 +       return  1;
6876 +}
6877 +
6878 +/*----------------------------------------------------------------------
6879 +* mac_stop_tx_dma
6880 +*----------------------------------------------------------------------*/
6881 +int mac_stop_tx_dma(int mac)
6882 +{
6883 +       GMAC_DMA_CTRL_T dma_ctrl, dma_ctrl_mask;
6884 +
6885 +       dma_ctrl.bits32 = 0;
6886 +       dma_ctrl.bits.td_enable = 0;
6887 +
6888 +       dma_ctrl_mask.bits32 = 0;
6889 +       dma_ctrl_mask.bits.td_enable = 1;
6890 +
6891 +       if (mac == 0)
6892 +       gmac_write_reg(TOE_GMAC0_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6893 +       else
6894 +       gmac_write_reg(TOE_GMAC1_DMA_BASE, GMAC_DMA_CTRL_REG, dma_ctrl.bits32, dma_ctrl_mask.bits32);
6895 +       return  1;
6896 +}
6897 +
6898 +/*----------------------------------------------------------------------
6899 +* mac_read_reg(int mac, unsigned int offset)
6900 +*----------------------------------------------------------------------*/
6901 +unsigned int mac_read_reg(int mac, unsigned int offset)
6902 +{
6903 +       switch (mac)
6904 +       {
6905 +               case 0:
6906 +                       return gmac_read_reg(TOE_GMAC0_BASE, offset);
6907 +               case 1:
6908 +                       return gmac_read_reg(TOE_GMAC1_BASE, offset);
6909 +               default:
6910 +                       return 0;
6911 +       }
6912 +}
6913 +
6914 +/*----------------------------------------------------------------------
6915 +* mac_write_reg
6916 +*----------------------------------------------------------------------*/
6917 +void mac_write_reg(int mac, unsigned int offset, unsigned data)
6918 +{
6919 +       switch (mac)
6920 +       {
6921 +               case 0:
6922 +                       gmac_write_reg(GMAC0_BASE, offset, data, 0xffffffff);
6923 +                       break;
6924 +               case 1:
6925 +                       gmac_write_reg(GMAC1_BASE, offset, data, 0xffffffff);
6926 +                       break;
6927 +       }
6928 +}
6929 +
6930 +/*----------------------------------------------------------------------
6931 +* mac_read_dma_reg(int mac, unsigned int offset)
6932 +*----------------------------------------------------------------------*/
6933 +u32 mac_read_dma_reg(int mac, unsigned int offset)
6934 +{
6935 +       switch (mac)
6936 +       {
6937 +               case 0:
6938 +                       return gmac_read_reg(TOE_GMAC0_DMA_BASE, offset);
6939 +               case 1:
6940 +                       return gmac_read_reg(TOE_GMAC1_DMA_BASE, offset);
6941 +               default:
6942 +                       return 0;
6943 +       }
6944 +}
6945 +
6946 +/*----------------------------------------------------------------------
6947 +* mac_write_dma_reg
6948 +*----------------------------------------------------------------------*/
6949 +void mac_write_dma_reg(int mac, unsigned int offset, u32 data)
6950 +{
6951 +       switch (mac)
6952 +       {
6953 +               case 0:
6954 +                       gmac_write_reg(TOE_GMAC0_DMA_BASE, offset, data, 0xffffffff);
6955 +                       break;
6956 +               case 1:
6957 +                       gmac_write_reg(TOE_GMAC1_DMA_BASE, offset, data, 0xffffffff);
6958 +                       break;
6959 +       }
6960 +}
6961 +
6962 +/*----------------------------------------------------------------------
6963 +* ether_crc
6964 +*----------------------------------------------------------------------*/
6965 +static unsigned const ethernet_polynomial = 0x04c11db7U;
6966 +static unsigned int ether_crc (int length, unsigned char *data)
6967 +{
6968 +       int crc = -1;
6969 +       unsigned int i;
6970 +       unsigned int crc_val=0;
6971 +
6972 +       while (--length >= 0) {
6973 +               unsigned char current_octet = *data++;
6974 +               int bit;
6975 +               for (bit = 0; bit < 8; bit++, current_octet >>= 1)
6976 +                       crc = (crc << 1) ^ ((crc < 0) ^ (current_octet & 1) ?
6977 +                            ethernet_polynomial : 0);
6978 +       }
6979 +       crc = ~crc;
6980 +       for (i=0;i<32;i++)
6981 +       {
6982 +               crc_val = crc_val + (((crc << i) & 0x80000000) >> (31-i));
6983 +       }
6984 +       return crc_val;
6985 +}
6986 +
6987 +
6988 +
6989 +/*----------------------------------------------------------------------
6990 +* mac_set_rx_mode
6991 +*----------------------------------------------------------------------*/
6992 +void mac_set_rx_mode(int pid, unsigned int data)
6993 +{
6994 +       unsigned int    base;
6995 +
6996 +       base = (pid == 0) ? GMAC0_BASE : GMAC1_BASE;
6997 +
6998 +    gmac_write_reg(base, GMAC_RX_FLTR, data, 0x0000001f);
6999 +    return;
7000 +}
7001 +
7002 +
7003 +/*----------------------------------------------------------------------
7004 +* gmac_open
7005 +*----------------------------------------------------------------------*/
7006 +
7007 +static int gmac_open (struct net_device *dev)
7008 +{
7009 +       GMAC_INFO_T  *tp = (GMAC_INFO_T *)dev->priv;
7010 +       int                                     retval;
7011 +       TOE_INFO_T                              *toe;
7012 +       toe = (TOE_INFO_T *)&toe_private_data;
7013 +
7014 +    /* hook ISR */
7015 +       retval = request_irq (dev->irq, toe_gmac_interrupt, SA_INTERRUPT, dev->name, dev);
7016 +       if (retval)
7017 +               return retval;
7018 +
7019 +       toe_init_gmac(dev);
7020 +
7021 +       if(!FLAG_SWITCH)
7022 +       {
7023 +       init_waitqueue_head (&tp->thr_wait);
7024 +       init_completion(&tp->thr_exited);
7025 +
7026 +       tp->time_to_die = 0;
7027 +       tp->thr_pid = kernel_thread (gmac_phy_thread, dev, CLONE_FS | CLONE_FILES);
7028 +       if (tp->thr_pid < 0)
7029 +       {
7030 +               printk (KERN_WARNING "%s: unable to start kernel thread\n",dev->name);
7031 +       }
7032 +    }
7033 +
7034 +       tp->operation = 1;
7035 +
7036 +       netif_start_queue (dev);
7037 +
7038 +       return (0);
7039 +}
7040 +
7041 +/*----------------------------------------------------------------------
7042 +* gmac_close
7043 +*----------------------------------------------------------------------*/
7044 +static int gmac_close(struct net_device *dev)
7045 +{
7046 +    TOE_INFO_T                 *toe;
7047 +//     GMAC_RXDESC_T           *sw_desc_ptr,*desc_ptr;
7048 +//     unsigned int            buf_ptr;
7049 +       GMAC_INFO_T     *tp = dev->priv;
7050 +       unsigned int            ret;
7051 +
7052 +       toe = (TOE_INFO_T *)&toe_private_data;
7053 +
7054 +       tp->operation = 0;
7055 +
7056 +    netif_stop_queue(dev);
7057 +    mdelay(20);
7058 +
7059 +    /* stop tx/rx packet */
7060 +    toe_gmac_disable_tx_rx(dev);
7061 +    mdelay(20);
7062 +
7063 +    /* stop the chip's Tx and Rx DMA processes */
7064 +       toe_gmac_hw_stop(dev);
7065 +
7066 +       toe_gmac_disable_interrupt(tp->irq);
7067 +
7068 +    /* disable interrupts by clearing the interrupt mask */
7069 +    synchronize_irq();
7070 +    free_irq(dev->irq,dev);
7071 +
7072 +//     DMA_MFREE(sw_desc_ptr, (TOE_SW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),(dma_addr_t *)&toe->sw_freeq_desc_base_dma);
7073 +//     DMA_MFREE(desc_ptr, TOE_HW_FREEQ_DESC_NUM * sizeof(GMAC_RXDESC_T),(dma_addr_t *)&toe->hw_freeq_desc_base_dma);
7074 +//     DMA_MFREE(buf_ptr, TOE_HW_FREEQ_DESC_NUM) * HW_RX_BUF_SIZE),(dma_addr_t *)&toe->hwfq_buf_base_dma);
7075 +//     DMA_MFREE(toe->gmac[0].swtxq_desc_base , TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[0].swtxq_desc_base_dma);
7076 +//     DMA_MFREE(toe->gmac[1].swtxq_desc_base , TOE_GMAC0_SWTXQ_DESC_NUM * TOE_SW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[1].swtxq_desc_base_dma);
7077 +//     DMA_MFREE(toe->gmac[0].hwtxq_desc_base_dma , TOE_GMAC0_HWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[0].hwtxq_desc_base_dma);
7078 +//     DMA_MFREE(toe->gmac[1].hwtxq_desc_base_dma , TOE_GMAC0_SWTXQ_DESC_NUM * TOE_HW_TXQ_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[1].hwtxq_desc_base_dma);
7079 +//     DMA_MFREE(toe->gmac[0].default_desc_base_dma ,TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[0].default_desc_base_dma);
7080 +//     DMA_MFREE(toe->gmac[1].default_desc_base_dma , TOE_DEFAULT_Q0_DESC_NUM * sizeof(GMAC_TXDESC_T),(dma_addr_t *)&toe->gmac[1].default_desc_base_dma);
7081 +//     DMA_MFREE(toe->intr_desc_base_dma , TOE_INTR_QUEUE_NUM * TOE_INTR_DESC_NUM * sizeof(GMAC_RXDESC_T),(dma_addr_t *)&toe->intr_desc_base_dma);
7082 +//     DMA_MFREE(toe->intr_buf_base_dma , TOE_INTR_DESC_NUM * sizeof(TOE_QHDR_T),(dma_addr_t *)&toe->intr_buf_base_dma);
7083 +
7084 +       if(!FLAG_SWITCH)
7085 +       {
7086 +       if (tp->thr_pid >= 0)
7087 +       {
7088 +                   tp->time_to_die = 1;
7089 +               wmb();
7090 +               ret = kill_proc (tp->thr_pid, SIGTERM, 1);
7091 +               if (ret)
7092 +               {
7093 +                       printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
7094 +                       return ret;
7095 +               }
7096 +//             wait_for_completion (&tp->thr_exited);
7097 +       }
7098 +    }
7099 +
7100 +    return (0);
7101 +}
7102 +
7103 +/*----------------------------------------------------------------------
7104 +* toe_gmac_fill_free_q
7105 +* allocate buffers for free queue.
7106 +*----------------------------------------------------------------------*/
7107 +static inline void toe_gmac_fill_free_q(void)
7108 +{
7109 +       struct sk_buff  *skb;
7110 +       volatile DMA_RWPTR_T    fq_rwptr;
7111 +       volatile GMAC_RXDESC_T  *fq_desc;
7112 +       unsigned long   flags;
7113 +       // unsigned short max_cnt=TOE_SW_FREEQ_DESC_NUM>>1;
7114 +
7115 +       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7116 +       spin_lock_irqsave(&gmac_fq_lock, flags);
7117 +       //while ((max_cnt--) && (unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
7118 +       //                              TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
7119 +       while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
7120 +                                       TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr) {
7121 +               if ((skb = dev_alloc_skb(SW_RX_BUF_SIZE)) == NULL) {
7122 +                       printk("%s::skb allocation fail!\n", __func__);
7123 +                       //while(1);
7124 +                       break;
7125 +               }
7126 +               REG32(skb->data) = (unsigned int)skb;
7127 +               skb_reserve(skb, SKB_RESERVE_BYTES);
7128 +               // fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7129 +               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr,
7130 +                       TOE_SW_FREEQ_DESC_NUM);
7131 +               fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base+fq_rwptr.bits.wptr;
7132 +               fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
7133 +               SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
7134 +               toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
7135 +       }
7136 +       spin_unlock_irqrestore(&gmac_fq_lock, flags);
7137 +}
7138 +// EXPORT_SYMBOL(toe_gmac_fill_free_q);
7139 +
7140 +/*----------------------------------------------------------------------
7141 +* toe_gmac_interrupt
7142 +*----------------------------------------------------------------------*/
7143 +static irqreturn_t toe_gmac_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
7144 +{
7145 +       struct net_device   *dev = (struct net_device *)dev_instance;
7146 +       TOE_INFO_T                      *toe;
7147 +       GMAC_INFO_T             *tp = (GMAC_INFO_T *)dev->priv;
7148 +       unsigned int            status0;
7149 +       unsigned int            status1;
7150 +       unsigned int            status2;
7151 +       unsigned int            status3;
7152 +       unsigned int            status4;
7153 +
7154 +//     struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
7155 +       toe = (TOE_INFO_T *)&toe_private_data;
7156 +//     handle NAPI
7157 +#ifdef CONFIG_SL_NAPI
7158 +if (storlink_ctl.pauseoff == 1)
7159 +{
7160 +/* disable GMAC interrupt */
7161 +    //toe_gmac_disable_interrupt(tp->irq);
7162 +
7163 +//     isPtr->interrupts++;
7164 +       /* read Interrupt status */
7165 +       status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
7166 +       status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
7167 +       status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
7168 +       status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
7169 +       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
7170 +       // prompt warning if status bit ON but not enabled
7171 +#if 0
7172 +       if (status0 & ~tp->intr0_enabled)
7173 +               printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
7174 +                               status0, tp->intr0_enabled);
7175 +       if (status1 & ~tp->intr1_enabled)
7176 +               printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
7177 +                               status1, tp->intr1_enabled);
7178 +       if (status2 & ~tp->intr2_enabled)
7179 +               printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
7180 +                               status2, tp->intr2_enabled);
7181 +       if (status3 & ~tp->intr3_enabled)
7182 +               printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
7183 +                               status3, tp->intr3_enabled);
7184 +       if (status4 & ~tp->intr4_enabled)
7185 +               printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
7186 +                               status4, tp->intr4_enabled);
7187 +#endif
7188 +
7189 +       if (status0)
7190 +               writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
7191 +       if (status1)
7192 +               writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
7193 +       if (status2)
7194 +               writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
7195 +       if (status3)
7196 +               writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
7197 +       if (status4)
7198 +               writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
7199 +#if 0
7200 +       /* handle freeq interrupt first */
7201 +       if (status4 & tp->intr4_enabled) {
7202 +               if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
7203 +               {
7204 +                       // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7205 +                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
7206 +                       //      tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7207 +
7208 +                       if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
7209 +                               toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
7210 +                       if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
7211 +                               toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
7212 +                       printk("\nfreeq int\n");
7213 +                       toe_gmac_fill_free_q();
7214 +                       tp->sw_fq_empty_cnt++;
7215 +
7216 +               }
7217 +       }
7218 +#endif
7219 +       // Interrupt Status 1
7220 +       if (status1 & tp->intr1_enabled)
7221 +       {
7222 +               #define G1_INTR0_BITS   (GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
7223 +               #define G0_INTR0_BITS   (GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
7224 +               // Handle GMAC 0/1 HW Tx queue 0-3 EOF events
7225 +               // Only count
7226 +               // TOE, Classification, and default queues interrupts are handled by ISR
7227 +               // because they should pass packets to upper layer
7228 +               if (tp->port_id == 0)
7229 +               {
7230 +                       if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
7231 +                       {
7232 +                               if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
7233 +                                       tp->hwtxq[3].eof_cnt++;
7234 +                               if (status1 & GMAC0_HWTQ02_EOF_INT_BIT)
7235 +                                       tp->hwtxq[2].eof_cnt++;
7236 +                               if (status1 & GMAC0_HWTQ01_EOF_INT_BIT)
7237 +                                       tp->hwtxq[1].eof_cnt++;
7238 +                               if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
7239 +                                       tp->hwtxq[0].eof_cnt++;
7240 +                       }
7241 +                               if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
7242 +                               {
7243 +                                       if (likely(netif_rx_schedule_prep(dev)))
7244 +                               {
7245 +                                       unsigned int data32;
7246 +                                       // disable GMAC-0 rx interrupt
7247 +                                       // class-Q & TOE-Q are implemented in future
7248 +                                       //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
7249 +                                       //data32 &= ~DEFAULT_Q0_INT_BIT;
7250 +                                               //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
7251 +                                               //printk("\%s: DEFAULT_Q0_INT_BIT===================>>>>>>>>>>>>\n",__func__);
7252 +                                               writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
7253 +                                               //tp->total_q_cnt_napi=0;
7254 +                                               //rx_time = jiffies;
7255 +                                               //rx_old_bytes = isPtr->rx_bytes;
7256 +                               __netif_rx_schedule(dev);
7257 +                               }
7258 +                       }
7259 +               }
7260 +               else if (tp->port_id == 1)
7261 +               {
7262 +                       if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
7263 +                       {
7264 +                               if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
7265 +                                       tp->hwtxq[3].eof_cnt++;
7266 +                               if (status1 & GMAC1_HWTQ12_EOF_INT_BIT)
7267 +                                       tp->hwtxq[2].eof_cnt++;
7268 +                               if (status1 & GMAC1_HWTQ11_EOF_INT_BIT)
7269 +                                       tp->hwtxq[1].eof_cnt++;
7270 +                               if (status1 & GMAC1_HWTQ10_EOF_INT_BIT)
7271 +                                       tp->hwtxq[0].eof_cnt++;
7272 +                       }
7273 +
7274 +                       if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
7275 +                       {
7276 +                               if (likely(netif_rx_schedule_prep(dev)))
7277 +                       {
7278 +                               unsigned int data32;
7279 +                               // disable GMAC-0 rx interrupt
7280 +                               // class-Q & TOE-Q are implemented in future
7281 +                               //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
7282 +                               //data32 &= ~DEFAULT_Q1_INT_BIT;
7283 +                                       //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
7284 +                                       //printk("\%s: 1111111111--->DEFAULT_Q1_INT_BIT===================>>>>>>>>>>>>\n",__func__);
7285 +                                       writel(0x0, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
7286 +                                       //tp->total_q_cnt_napi=0;
7287 +                                       //rx_time = jiffies;
7288 +                                       //rx_old_bytes = isPtr->rx_bytes;
7289 +                               __netif_rx_schedule(dev);
7290 +                       }
7291 +                       }
7292 +               }
7293 +       }
7294 +
7295 +       // Interrupt Status 0
7296 +       if (status0 & tp->intr0_enabled)
7297 +       {
7298 +               #define ERR_INTR_BITS   (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |  \
7299 +                                                                GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |  \
7300 +                                                                GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |  \
7301 +                                                                GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT)
7302 +
7303 +               if (status0 &  ERR_INTR_BITS)
7304 +               {
7305 +                       if ((status0 & GMAC0_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXDERR_INT_BIT))
7306 +                       {
7307 +                               tp->txDerr_cnt[0]++;
7308 +                               printk("GMAC0 TX AHB Bus Error!\n");
7309 +                       }
7310 +                       if ((status0 & GMAC0_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXPERR_INT_BIT))
7311 +                       {
7312 +                               tp->txPerr_cnt[0]++;
7313 +                               printk("GMAC0 Tx Descriptor Protocol Error!\n");
7314 +                       }
7315 +                       if ((status0 & GMAC1_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXDERR_INT_BIT))
7316 +                       {
7317 +                               tp->txDerr_cnt[1]++;
7318 +                               printk("GMAC1 Tx AHB Bus Error!\n");
7319 +                       }
7320 +                       if ((status0 & GMAC1_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXPERR_INT_BIT))
7321 +                       {
7322 +                               tp->txPerr_cnt[1]++;
7323 +                               printk("GMAC1 Tx Descriptor Protocol Error!\n");
7324 +                       }
7325 +
7326 +                       if ((status0 & GMAC0_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXDERR_INT_BIT))
7327 +                       {
7328 +                               tp->RxDerr_cnt[0]++;
7329 +                               printk("GMAC0 Rx AHB Bus Error!\n");
7330 +                       }
7331 +                       if ((status0 & GMAC0_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXPERR_INT_BIT))
7332 +                       {
7333 +                               tp->RxPerr_cnt[0]++;
7334 +                               printk("GMAC0 Rx Descriptor Protocol Error!\n");
7335 +                       }
7336 +                       if ((status0 & GMAC1_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXDERR_INT_BIT))
7337 +                       {
7338 +                               tp->RxDerr_cnt[1]++;
7339 +                               printk("GMAC1 Rx AHB Bus Error!\n");
7340 +                       }
7341 +                       if ((status0 & GMAC1_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXPERR_INT_BIT))
7342 +                       {
7343 +                               tp->RxPerr_cnt[1]++;
7344 +                               printk("GMAC1 Rx Descriptor Protocol Error!\n");
7345 +                       }
7346 +               }
7347 +
7348 +#ifndef        GMAX_TX_INTR_DISABLED
7349 +               if (tp->port_id == 1 && netif_running(dev) &&
7350 +                       (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
7351 +                       ||
7352 +                       ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT))))
7353 +               {
7354 +                       toe_gmac_tx_complete(&toe_private_data.gmac[1], 0, dev, 1);
7355 +               }
7356 +
7357 +               if (tp->port_id == 0 && netif_running(dev) &&
7358 +                       (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
7359 +                       ||
7360 +                       ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT))))
7361 +               {
7362 +                       toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
7363 +               }
7364 +#endif
7365 +       }
7366 +       // Interrupt Status 4
7367 +       if (status4 & tp->intr4_enabled)
7368 +       {
7369 +               #define G1_INTR4_BITS           (0xff000000)
7370 +               #define G0_INTR4_BITS           (0x00ff0000)
7371 +
7372 +               if (tp->port_id == 0)
7373 +               {
7374 +                       if ((status4 & G0_INTR4_BITS) && (tp->intr4_enabled & G0_INTR4_BITS))
7375 +                       {
7376 +                               if (status4 & GMAC0_RESERVED_INT_BIT)
7377 +                                       printk("GMAC0_RESERVED_INT_BIT is ON\n");
7378 +                               if (status4 & GMAC0_MIB_INT_BIT)
7379 +                                       tp->mib_full_cnt++;
7380 +                               if (status4 & GMAC0_RX_PAUSE_ON_INT_BIT)
7381 +                                       tp->rx_pause_on_cnt++;
7382 +                               if (status4 & GMAC0_TX_PAUSE_ON_INT_BIT)
7383 +                                       tp->tx_pause_on_cnt++;
7384 +                               if (status4 & GMAC0_RX_PAUSE_OFF_INT_BIT)
7385 +                                       tp->rx_pause_off_cnt++;
7386 +                               if (status4 & GMAC0_TX_PAUSE_OFF_INT_BIT)
7387 +                                       tp->rx_pause_off_cnt++;
7388 +                               if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
7389 +                                       tp->rx_overrun_cnt++;
7390 +                               if (status4 & GMAC0_STATUS_CHANGE_INT_BIT)
7391 +                                       tp->status_changed_cnt++;
7392 +                       }
7393 +               }
7394 +               else if (tp->port_id == 1)
7395 +               {
7396 +                       if ((status4 & G1_INTR4_BITS) && (tp->intr4_enabled & G1_INTR4_BITS))
7397 +                       {
7398 +                               if (status4 & GMAC1_RESERVED_INT_BIT)
7399 +                                       printk("GMAC1_RESERVED_INT_BIT is ON\n");
7400 +                               if (status4 & GMAC1_MIB_INT_BIT)
7401 +                                       tp->mib_full_cnt++;
7402 +                               if (status4 & GMAC1_RX_PAUSE_ON_INT_BIT)
7403 +                               {
7404 +                                       printk("Gmac pause on\n");
7405 +                                       tp->rx_pause_on_cnt++;
7406 +                               }
7407 +                               if (status4 & GMAC1_TX_PAUSE_ON_INT_BIT)
7408 +                               {
7409 +                                       printk("Gmac pause on\n");
7410 +                                       tp->tx_pause_on_cnt++;
7411 +                               }
7412 +                               if (status4 & GMAC1_RX_PAUSE_OFF_INT_BIT)
7413 +                               {
7414 +                                       printk("Gmac pause off\n");
7415 +                                       tp->rx_pause_off_cnt++;
7416 +                               }
7417 +                               if (status4 & GMAC1_TX_PAUSE_OFF_INT_BIT)
7418 +                               {
7419 +                                       printk("Gmac pause off\n");
7420 +                                       tp->rx_pause_off_cnt++;
7421 +                               }
7422 +                               if (status4 & GMAC1_RX_OVERRUN_INT_BIT)
7423 +                               {
7424 +                                       //printk("Gmac Rx Overrun \n");
7425 +                                       tp->rx_overrun_cnt++;
7426 +                               }
7427 +                               if (status4 & GMAC1_STATUS_CHANGE_INT_BIT)
7428 +                                       tp->status_changed_cnt++;
7429 +                       }
7430 +               }
7431 +       }
7432 +
7433 +       //toe_gmac_enable_interrupt(tp->irq);
7434 +#ifdef IxscriptMate_1518
7435 +       if (storlink_ctl.pauseoff == 1)
7436 +       {
7437 +               GMAC_CONFIG0_T config0;
7438 +               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7439 +               config0.bits.dis_rx = 0;
7440 +               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7441 +               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7442 +               config0.bits.dis_rx = 0;
7443 +               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7444 +       }
7445 +#endif
7446 +//      enable_irq(gmac_irq[dev_index]);
7447 +       //printk("gmac_interrupt complete!\n\n");
7448 +//     return IRQ_RETVAL(handled);
7449 +       return  IRQ_RETVAL(1);
7450 +}
7451 +else
7452 +{
7453 +#endif //endif NAPI
7454 +
7455 +
7456 +       /* disable GMAC interrupt */
7457 +    toe_gmac_disable_interrupt(tp->irq);
7458 +
7459 +//     isPtr->interrupts++;
7460 +       /* read Interrupt status */
7461 +       status0 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
7462 +       status1 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
7463 +       status2 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
7464 +       status3 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
7465 +       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
7466 +       // prompt warning if status bit ON but not enabled
7467 +#if 0
7468 +       if (status0 & ~tp->intr0_enabled)
7469 +               printk("Intr 0 Status error. status = 0x%X, enable = 0x%X\n",
7470 +                               status0, tp->intr0_enabled);
7471 +       if (status1 & ~tp->intr1_enabled)
7472 +               printk("Intr 1 Status error. status = 0x%X, enable = 0x%X\n",
7473 +                               status1, tp->intr1_enabled);
7474 +       if (status2 & ~tp->intr2_enabled)
7475 +               printk("Intr 2 Status error. status = 0x%X, enable = 0x%X\n",
7476 +                               status2, tp->intr2_enabled);
7477 +       if (status3 & ~tp->intr3_enabled)
7478 +               printk("Intr 3 Status error. status = 0x%X, enable = 0x%X\n",
7479 +                               status3, tp->intr3_enabled);
7480 +       if (status4 & ~tp->intr4_enabled)
7481 +               printk("Intr 4 Status error. status = 0x%X, enable = 0x%X\n",
7482 +                               status4, tp->intr4_enabled);
7483 +#endif
7484 +#define        INTERRUPT_SELECT                        1
7485 +       if (status0)
7486 +               writel(status0 & tp->intr0_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_0_REG);
7487 +       if (status1)
7488 +               writel(status1 & tp->intr1_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_1_REG);
7489 +       if (status2)
7490 +               writel(status2 & tp->intr2_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_2_REG);
7491 +       if (status3)
7492 +               writel(status3 & tp->intr3_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_3_REG);
7493 +       if (status4)
7494 +               writel(status4 & tp->intr4_enabled, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_STATUS_4_REG);
7495 +
7496 +       /* handle freeq interrupt first */
7497 +       if (status4 & tp->intr4_enabled) {
7498 +               if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
7499 +               {
7500 +                       // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7501 +                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
7502 +                       //      tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7503 +
7504 +                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
7505 +                       //      SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7506 +                       if (toe->gmac[0].dev && netif_running(toe->gmac[0].dev))
7507 +                               toe_gmac_handle_default_rxq(toe->gmac[0].dev,&toe->gmac[0]);
7508 +                       if (toe->gmac[1].dev && netif_running(toe->gmac[1].dev))
7509 +                               toe_gmac_handle_default_rxq(toe->gmac[1].dev,&toe->gmac[1]);
7510 +                       printk("\nfreeq int\n");
7511 +                       toe_gmac_fill_free_q();
7512 +                       tp->sw_fq_empty_cnt++;
7513 +
7514 +                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
7515 +                               SWFQ_EMPTY_INT_BIT);
7516 +               }
7517 +       }
7518 +
7519 +       // Interrupt Status 1
7520 +       if (status1 & tp->intr1_enabled)
7521 +       {
7522 +               #define G1_INTR0_BITS   (GMAC1_HWTQ13_EOF_INT_BIT | GMAC1_HWTQ12_EOF_INT_BIT | GMAC1_HWTQ11_EOF_INT_BIT | GMAC1_HWTQ10_EOF_INT_BIT)
7523 +               #define G0_INTR0_BITS   (GMAC0_HWTQ03_EOF_INT_BIT | GMAC0_HWTQ02_EOF_INT_BIT | GMAC0_HWTQ01_EOF_INT_BIT | GMAC0_HWTQ00_EOF_INT_BIT)
7524 +               // Handle GMAC 0/1 HW Tx queue 0-3 EOF events
7525 +               // Only count
7526 +               // TOE, Classification, and default queues interrupts are handled by ISR
7527 +               // because they should pass packets to upper layer
7528 +               if (tp->port_id == 0)
7529 +               {
7530 +#ifndef        INTERRUPT_SELECT
7531 +                       if (netif_running(dev) && (status1 & G0_INTR0_BITS) && (tp->intr1_enabled & G0_INTR0_BITS))
7532 +                       {
7533 +                               if (status1 & GMAC0_HWTQ03_EOF_INT_BIT)
7534 +                                       tp->hwtxq[3].eof_cnt++;
7535 +                               if (status1 & GMAC0_HWTQ02_EOF_INT_BIT)
7536 +                                       tp->hwtxq[2].eof_cnt++;
7537 +                               if (status1 & GMAC0_HWTQ01_EOF_INT_BIT)
7538 +                                       tp->hwtxq[1].eof_cnt++;
7539 +                               if (status1 & GMAC0_HWTQ00_EOF_INT_BIT)
7540 +                                       tp->hwtxq[0].eof_cnt++;
7541 +#endif //INTERRUPT_SELECT
7542 +#ifndef        INTERRUPT_SELECT
7543 +                       }
7544 +#endif //INTERRUPT_SELECT
7545 +                       if (netif_running(dev) && (status1 & DEFAULT_Q0_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q0_INT_BIT))
7546 +                       {
7547 +                               tp->default_q_intr_cnt++;
7548 +                               toe_gmac_handle_default_rxq(dev, tp);
7549 +                       }
7550 +#ifdef CONFIG_SL351x_RXTOE
7551 +                       if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
7552 +                           (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
7553 +                               //printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
7554 +                               toe_gmac_handle_toeq(dev, tp, status1);
7555 +                               //toe_gmac_handle_toeq(dev, toe, tp, status1);
7556 +                       }
7557 +#endif
7558 +               }
7559 +               else if (tp->port_id == 1)
7560 +               {
7561 +#ifndef        INTERRUPT_SELECT
7562 +                       if (netif_running(dev) && (status1 & G1_INTR0_BITS) && (tp->intr1_enabled & G1_INTR0_BITS))
7563 +                       {
7564 +                               if (status1 & GMAC1_HWTQ13_EOF_INT_BIT)
7565 +                                       tp->hwtxq[3].eof_cnt++;
7566 +                               if (status1 & GMAC1_HWTQ12_EOF_INT_BIT)
7567 +                                       tp->hwtxq[2].eof_cnt++;
7568 +                               if (status1 & GMAC1_HWTQ11_EOF_INT_BIT)
7569 +                                       tp->hwtxq[1].eof_cnt++;
7570 +                               if (status1 & GMAC1_HWTQ10_EOF_INT_BIT)
7571 +                                       tp->hwtxq[0].eof_cnt++;
7572 +#endif //INTERRUPT_SELECT
7573 +#ifndef        INTERRUPT_SELECT
7574 +                       }
7575 +#endif //INTERRUPT_SELECT
7576 +                       if (netif_running(dev) && (status1 & DEFAULT_Q1_INT_BIT) && (tp->intr1_enabled & DEFAULT_Q1_INT_BIT))
7577 +                       {
7578 +                               tp->default_q_intr_cnt++;
7579 +                               toe_gmac_handle_default_rxq(dev, tp);
7580 +                       }
7581 +#ifdef CONFIG_SL351x_RXTOE
7582 +                       if (netif_running(dev) && (status1 & TOE_IQ_ALL_BITS) &&
7583 +                           (tp->intr1_enabled & TOE_IQ_ALL_BITS)) {
7584 +                               //printk("status %x, bits %x, slct %x\n", status1, TOE_IQ_ALL_BITS, tp->intr1_selected);
7585 +                               toe_gmac_handle_toeq(dev, tp, status1);
7586 +                               //toe_gmac_handle_toeq(dev, toe, tp, status1);
7587 +                       }
7588 +#endif
7589 +               }
7590 +       }
7591 +
7592 +
7593 +       // Interrupt Status 0
7594 +       if (status0 & tp->intr0_enabled)
7595 +       {
7596 +
7597 +               #define ERR_INTR_BITS   (GMAC0_TXDERR_INT_BIT | GMAC0_TXPERR_INT_BIT |  \
7598 +                                                                GMAC1_TXDERR_INT_BIT | GMAC1_TXPERR_INT_BIT |  \
7599 +                                                                GMAC0_RXDERR_INT_BIT | GMAC0_RXPERR_INT_BIT |  \
7600 +                                                                GMAC1_RXDERR_INT_BIT | GMAC1_RXPERR_INT_BIT)
7601 +#ifndef        INTERRUPT_SELECT
7602 +               if (status0 &  ERR_INTR_BITS)
7603 +               {
7604 +                       if ((status0 & GMAC0_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXDERR_INT_BIT))
7605 +                       {
7606 +                               tp->txDerr_cnt[0]++;
7607 +                               printk("GMAC0 TX AHB Bus Error!\n");
7608 +                       }
7609 +                       if ((status0 & GMAC0_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_TXPERR_INT_BIT))
7610 +                       {
7611 +                               tp->txPerr_cnt[0]++;
7612 +                               printk("GMAC0 Tx Descriptor Protocol Error!\n");
7613 +                       }
7614 +                       if ((status0 & GMAC1_TXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXDERR_INT_BIT))
7615 +                       {
7616 +                               tp->txDerr_cnt[1]++;
7617 +                               printk("GMAC1 Tx AHB Bus Error!\n");
7618 +                       }
7619 +                       if ((status0 & GMAC1_TXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_TXPERR_INT_BIT))
7620 +                       {
7621 +                               tp->txPerr_cnt[1]++;
7622 +                               printk("GMAC1 Tx Descriptor Protocol Error!\n");
7623 +                       }
7624 +
7625 +                       if ((status0 & GMAC0_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXDERR_INT_BIT))
7626 +                       {
7627 +                               tp->RxDerr_cnt[0]++;
7628 +                               printk("GMAC0 Rx AHB Bus Error!\n");
7629 +                       }
7630 +                       if ((status0 & GMAC0_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC0_RXPERR_INT_BIT))
7631 +                       {
7632 +                               tp->RxPerr_cnt[0]++;
7633 +                               printk("GMAC0 Rx Descriptor Protocol Error!\n");
7634 +                       }
7635 +                       if ((status0 & GMAC1_RXDERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXDERR_INT_BIT))
7636 +                       {
7637 +                               tp->RxDerr_cnt[1]++;
7638 +                               printk("GMAC1 Rx AHB Bus Error!\n");
7639 +                       }
7640 +                       if ((status0 & GMAC1_RXPERR_INT_BIT) && (tp->intr0_enabled & GMAC1_RXPERR_INT_BIT))
7641 +                       {
7642 +                               tp->RxPerr_cnt[1]++;
7643 +                               printk("GMAC1 Rx Descriptor Protocol Error!\n");
7644 +                       }
7645 +               }
7646 +#endif //INTERRUPT_SELECT
7647 +#ifndef        GMAX_TX_INTR_DISABLED
7648 +               if (tp->port_id == 1 && netif_running(dev) &&
7649 +                       (((status0 & GMAC1_SWTQ10_FIN_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_FIN_INT_BIT))
7650 +                       ||
7651 +                       ((status0 & GMAC1_SWTQ10_EOF_INT_BIT) && (tp->intr0_enabled & GMAC1_SWTQ10_EOF_INT_BIT))))
7652 +               {
7653 +                       toe_gmac_tx_complete(&toe_private_data.gmac[1], 0, dev, 1);
7654 +               }
7655 +
7656 +               if (tp->port_id == 0 && netif_running(dev) &&
7657 +                       (((status0 & GMAC0_SWTQ00_FIN_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_FIN_INT_BIT))
7658 +                       ||
7659 +                       ((status0 & GMAC0_SWTQ00_EOF_INT_BIT) && (tp->intr0_enabled & GMAC0_SWTQ00_EOF_INT_BIT))))
7660 +               {
7661 +                       toe_gmac_tx_complete(&toe_private_data.gmac[0], 0, dev, 1);
7662 +               }
7663 +#endif
7664 +               // clear enabled status bits
7665 +       }
7666 +       // Interrupt Status 4
7667 +#ifndef        INTERRUPT_SELECT
7668 +       if (status4 & tp->intr4_enabled)
7669 +       {
7670 +               #define G1_INTR4_BITS           (0xff000000)
7671 +               #define G0_INTR4_BITS           (0x00ff0000)
7672 +
7673 +               if (tp->port_id == 0)
7674 +               {
7675 +                       if ((status4 & G0_INTR4_BITS) && (tp->intr4_enabled & G0_INTR4_BITS))
7676 +                       {
7677 +                               if (status4 & GMAC0_RESERVED_INT_BIT)
7678 +                                       printk("GMAC0_RESERVED_INT_BIT is ON\n");
7679 +                               if (status4 & GMAC0_MIB_INT_BIT)
7680 +                                       tp->mib_full_cnt++;
7681 +                               if (status4 & GMAC0_RX_PAUSE_ON_INT_BIT)
7682 +                                       tp->rx_pause_on_cnt++;
7683 +                               if (status4 & GMAC0_TX_PAUSE_ON_INT_BIT)
7684 +                                       tp->tx_pause_on_cnt++;
7685 +                               if (status4 & GMAC0_RX_PAUSE_OFF_INT_BIT)
7686 +                                       tp->rx_pause_off_cnt++;
7687 +                               if (status4 & GMAC0_TX_PAUSE_OFF_INT_BIT)
7688 +                                       tp->rx_pause_off_cnt++;
7689 +                               if (status4 & GMAC0_RX_OVERRUN_INT_BIT)
7690 +                                       tp->rx_overrun_cnt++;
7691 +                               if (status4 & GMAC0_STATUS_CHANGE_INT_BIT)
7692 +                                       tp->status_changed_cnt++;
7693 +                       }
7694 +               }
7695 +               else if (tp->port_id == 1)
7696 +               {
7697 +                       if ((status4 & G1_INTR4_BITS) && (tp->intr4_enabled & G1_INTR4_BITS))
7698 +                       {
7699 +                               if (status4 & GMAC1_RESERVED_INT_BIT)
7700 +                                       printk("GMAC1_RESERVED_INT_BIT is ON\n");
7701 +                               if (status4 & GMAC1_MIB_INT_BIT)
7702 +                                       tp->mib_full_cnt++;
7703 +                               if (status4 & GMAC1_RX_PAUSE_ON_INT_BIT)
7704 +                               {
7705 +                                       //printk("Gmac pause on\n");
7706 +                                       tp->rx_pause_on_cnt++;
7707 +                               }
7708 +                               if (status4 & GMAC1_TX_PAUSE_ON_INT_BIT)
7709 +                               {
7710 +                                       //printk("Gmac pause on\n");
7711 +                                       tp->tx_pause_on_cnt++;
7712 +                               }
7713 +                               if (status4 & GMAC1_RX_PAUSE_OFF_INT_BIT)
7714 +                               {
7715 +                                       //printk("Gmac pause off\n");
7716 +                                       tp->rx_pause_off_cnt++;
7717 +                               }
7718 +                               if (status4 & GMAC1_TX_PAUSE_OFF_INT_BIT)
7719 +                               {
7720 +                                       //printk("Gmac pause off\n");
7721 +                                       tp->rx_pause_off_cnt++;
7722 +                               }
7723 +                               if (status4 & GMAC1_RX_OVERRUN_INT_BIT)
7724 +                               {
7725 +                                       //printk("Gmac Rx Overrun \n");
7726 +                                       tp->rx_overrun_cnt++;
7727 +                               }
7728 +                               if (status4 & GMAC1_STATUS_CHANGE_INT_BIT)
7729 +                                       tp->status_changed_cnt++;
7730 +                       }
7731 +               }
7732 +#if 0
7733 +               if ((status4 & SWFQ_EMPTY_INT_BIT) && (tp->intr4_enabled & SWFQ_EMPTY_INT_BIT))
7734 +               {
7735 +                       // unsigned long data = REG32(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
7736 +//                     mac_stop_rxdma(tp->sc);
7737 +                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_ENABLE_4_REG,
7738 +                               tp->intr4_enabled & ~SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7739 +
7740 +                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG,
7741 +                               SWFQ_EMPTY_INT_BIT, SWFQ_EMPTY_INT_BIT);
7742 +                       toe_gmac_fill_free_q();
7743 +                       tp->sw_fq_empty_cnt++;
7744 +
7745 +                       gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
7746 +                               SWFQ_EMPTY_INT_BIT);
7747 +//#if 0
7748 +/*                     if (netif_running(dev))
7749 +                               toe_gmac_handle_default_rxq(dev, tp);
7750 +                       printk("SWFQ_EMPTY_INT_BIT is ON!\n");  // should not be happened */
7751 +//#endif
7752 +               }
7753 +#endif
7754 +       }
7755 +#endif //INTERRUPT_SELECT
7756 +       toe_gmac_enable_interrupt(tp->irq);
7757 +//enable gmac rx function when do RFC 2544
7758 +#ifdef IxscriptMate_1518
7759 +       if (storlink_ctl.pauseoff == 1)
7760 +       {
7761 +               GMAC_CONFIG0_T config0;
7762 +               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7763 +               config0.bits.dis_rx = 0;
7764 +               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7765 +               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7766 +               config0.bits.dis_rx = 0;
7767 +               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7768 +       }
7769 +#endif
7770 +       //printk("gmac_interrupt complete!\n\n");
7771 +//     return IRQ_RETVAL(handled);
7772 +       return  IRQ_RETVAL(1);
7773 +#ifdef CONFIG_SL_NAPI
7774 +}
7775 +#endif
7776 +}
7777 +
7778 +/*----------------------------------------------------------------------
7779 +*      toe_gmac_handle_default_rxq
7780 +*      (1) Get rx Buffer for default Rx queue
7781 +*      (2) notify or call upper-routine to handle it
7782 +*      (3) get a new buffer and insert it into SW free queue
7783 +*      (4) Note: The SW free queue Read-Write Pointer should be locked when accessing
7784 +*----------------------------------------------------------------------*/
7785 +//static inline void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
7786 +static void toe_gmac_handle_default_rxq(struct net_device *dev, GMAC_INFO_T *tp)
7787 +{
7788 +       TOE_INFO_T                      *toe;
7789 +    GMAC_RXDESC_T      *curr_desc;
7790 +       struct sk_buff          *skb;
7791 +    DMA_RWPTR_T                        rwptr;
7792 +       unsigned int            pkt_size;
7793 +       int                                     max_cnt;
7794 +       unsigned int        desc_count;
7795 +       unsigned int        good_frame, chksum_status, rx_status;
7796 +       struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
7797 +
7798 +//when do ixia RFC 2544 test and packet size is select 1518 bytes,disable gmace rx function immediately after one interrupt come in.
7799 +#ifdef IxscriptMate_1518
7800 +       if (storlink_ctl.pauseoff == 1)
7801 +       {
7802 +               GMAC_CONFIG0_T config0;
7803 +               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7804 +               config0.bits.dis_rx = 1;
7805 +               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7806 +               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7807 +               config0.bits.dis_rx = 1;
7808 +               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7809 +       }
7810 +#endif
7811 +       rwptr.bits32 = readl(&tp->default_qhdr->word1);
7812 +#if 0
7813 +       if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
7814 +       {
7815 +               mac_stop_txdma((struct net_device *)tp->dev);
7816 +               printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
7817 +                               rwptr.bits32, tp->rx_rwptr.bits.rptr);
7818 +               while(1);
7819 +       }
7820 +#endif
7821 +       toe = (TOE_INFO_T *)&toe_private_data;
7822 +       max_cnt = DEFAULT_RXQ_MAX_CNT;
7823 +       while ((--max_cnt) && rwptr.bits.rptr != rwptr.bits.wptr)
7824 +//     while (rwptr.bits.rptr != rwptr.bits.wptr)
7825 +       {
7826 +//if packet size is not 1518 for RFC 2544,enable gmac rx function.The other packet size have RX workaround.
7827 +#ifdef IxscriptMate_1518
7828 +       if (storlink_ctl.pauseoff == 1)
7829 +               {
7830 +                       if (pkt_size != 1514)
7831 +                       {
7832 +                                               GMAC_CONFIG0_T config0;
7833 +                                               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7834 +                                               config0.bits.dis_rx = 0;
7835 +                                               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7836 +                                               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7837 +                                               config0.bits.dis_rx = 0;
7838 +                                               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7839 +                       }
7840 +               }
7841 +#endif
7842 +       curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
7843 +//             consistent_sync(curr_desc, sizeof(GMAC_RXDESC_T), PCI_DMA_FROMDEVICE);
7844 +               tp->default_q_cnt++;
7845 +       tp->rx_curr_desc = (unsigned int)curr_desc;
7846 +       rx_status = curr_desc->word0.bits.status;
7847 +       chksum_status = curr_desc->word0.bits.chksum_status;
7848 +       tp->rx_status_cnt[rx_status]++;
7849 +       tp->rx_chksum_cnt[chksum_status]++;
7850 +        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
7851 +               desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
7852 +               good_frame=1;
7853 +               if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
7854 +                       || (pkt_size < 60)
7855 +                   || (chksum_status & 0x4)
7856 +                       || rx_status)
7857 +               {
7858 +                       good_frame = 0;
7859 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
7860 +                               printk("%s::derr (GMAC-%d)!!!\n", __func__, tp->port_id);
7861 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
7862 +                               printk("%s::perr (GMAC-%d)!!!\n", __func__, tp->port_id);
7863 +                       if (rx_status)
7864 +                       {
7865 +                               if (rx_status == 4 || rx_status == 7)
7866 +                                       isPtr->rx_crc_errors++;
7867 +//                             printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
7868 +                       }
7869 +#ifdef SL351x_GMAC_WORKAROUND
7870 +                       else if (pkt_size < 60)
7871 +                       {
7872 +                               if (tp->short_frames_cnt < GMAC_SHORT_FRAME_THRESHOLD)
7873 +                                       tp->short_frames_cnt++;
7874 +                               if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
7875 +                               {
7876 +                                       GMAC_CONFIG0_T config0;
7877 +                                       config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7878 +                                       config0.bits.dis_rx = 1;
7879 +                                       writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7880 +                                       config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7881 +                                       config0.bits.dis_rx = 1;
7882 +                                       writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7883 +                               }
7884 +                       }
7885 +#endif
7886 +//                     if (chksum_status)
7887 +//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
7888 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
7889 +                       dev_kfree_skb_irq(skb);
7890 +               }
7891 +               if (good_frame)
7892 +               {
7893 +                       if (curr_desc->word0.bits.drop)
7894 +                               printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
7895 +//                     if (chksum_status)
7896 +//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
7897 +
7898 +               /* get frame information from the first descriptor of the frame */
7899 +#ifdef SL351x_GMAC_WORKAROUND
7900 +                       if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
7901 +                       {
7902 +                               GMAC_CONFIG0_T config0;
7903 +                               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
7904 +                               config0.bits.dis_rx = 0;
7905 +                               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
7906 +                               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
7907 +                               config0.bits.dis_rx = 0;
7908 +                               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
7909 +                       }
7910 +                       tp->short_frames_cnt = 0;
7911 +#endif
7912 +                       isPtr->rx_packets++;
7913 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr - SKB_RESERVE_BYTES)));
7914 +                       if (!skb)
7915 +                       {
7916 +                               printk("Fatal Error!!skb==NULL\n");
7917 +                               goto next_rx;
7918 +                       }
7919 +                       tp->curr_rx_skb = skb;
7920 +                       // consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
7921 +
7922 +       //              curr_desc->word2.buf_adr = 0;
7923 +
7924 +                       skb_reserve (skb, RX_INSERT_BYTES);     /* 16 byte align the IP fields. */
7925 +                       skb_put(skb, pkt_size);
7926 +                       skb->dev = dev;
7927 +                       if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
7928 +                       {
7929 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
7930 +#ifdef CONFIG_SL351x_NAT
7931 +                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
7932 +                               {
7933 +                                       struct iphdr    *ip_hdr;
7934 +                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
7935 +                                       sl351x_nat_input(skb,
7936 +                                                                       tp->port_id,
7937 +                                                                       (void *)curr_desc->word3.bits.l3_offset,
7938 +                                                                       (void *)curr_desc->word3.bits.l4_offset);
7939 +                               }
7940 +#endif
7941 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
7942 +#if 0
7943 +#ifdef CONFIG_SL351x_RXTOE
7944 +                               if (storlink_ctl.rx_max_pktsize) {
7945 +                                       struct iphdr    *ip_hdr;
7946 +                                       struct tcphdr   *tcp_hdr;
7947 +                                       int ip_hdrlen;
7948 +
7949 +                                       ip_hdr = (struct iphdr*)&(skb->data[0]);
7950 +                                       if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
7951 +                                          ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
7952 +                                               ip_hdrlen = ip_hdr->ihl << 2;
7953 +                                               tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
7954 +                                               if (tcp_hdr->syn) {
7955 +                                                       struct toe_conn* connection = init_toeq(ip_hdr->version,
7956 +                                                                       ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
7957 +                                                       TCP_SKB_CB(skb)->connection = connection;
7958 +                                                       //      hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
7959 +                                                       //              printk("%s::skb data %x, conn %x, mode %x\n",
7960 +                                                       //                      __func__, skb->data, connection, connection->mode);
7961 +                                               }
7962 +                                       }
7963 +                               }
7964 +#endif
7965 +#endif
7966 +                       }
7967 +                       else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
7968 +                       {
7969 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
7970 +#ifdef CONFIG_SL351x_NAT
7971 +                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
7972 +                               {
7973 +                                       struct iphdr            *ip_hdr;
7974 +                                       //struct tcphdr         *tcp_hdr;
7975 +                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
7976 +                                       //tcp_hdr = (struct tcphdr *)&(skb->data[curr_desc->word3.bits.l4_offset]);
7977 +                                       if (ip_hdr->protocol == IPPROTO_UDP)
7978 +                                       {
7979 +                                               sl351x_nat_input(skb,
7980 +                                                                               tp->port_id,
7981 +                                                                               (void *)curr_desc->word3.bits.l3_offset,
7982 +                                                                               (void *)curr_desc->word3.bits.l4_offset);
7983 +                                       }
7984 +                                       else if (ip_hdr->protocol == IPPROTO_GRE)
7985 +                                       {
7986 +                                               sl351x_nat_input(skb,
7987 +                                                                       tp->port_id,
7988 +                                                                       (void *)curr_desc->word3.bits.l3_offset,
7989 +                                                                       (void *)curr_desc->word3.bits.l4_offset);
7990 +                                       }
7991 +                               }
7992 +#endif
7993 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
7994 +                       }
7995 +                       else
7996 +                       {
7997 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
7998 +                       }
7999 +
8000 +                       netif_rx(skb);  /* socket rx */
8001 +                       dev->last_rx = jiffies;
8002 +
8003 +                       isPtr->rx_bytes += pkt_size;
8004 +
8005 +        }
8006 +
8007 +next_rx:
8008 +               // advance one for Rx default Q 0/1
8009 +               rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
8010 +               SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
8011 +       tp->rx_rwptr.bits32 = rwptr.bits32;
8012 +
8013 +               toe_gmac_fill_free_q();
8014 +       }
8015 +}
8016 +
8017 +/*----------------------------------------------------------------------
8018 +* gmac_get_phy_vendor
8019 +*----------------------------------------------------------------------*/
8020 +static unsigned int gmac_get_phy_vendor(int phy_addr)
8021 +{
8022 +    unsigned int       reg_val;
8023 +    reg_val=(mii_read(phy_addr,0x02) << 16) + mii_read(phy_addr,0x03);
8024 +    return reg_val;
8025 +}
8026 +
8027 +/*----------------------------------------------------------------------
8028 +* gmac_set_phy_status
8029 +*----------------------------------------------------------------------*/
8030 +void gmac_set_phy_status(struct net_device *dev)
8031 +{
8032 +       GMAC_INFO_T *tp = dev->priv;
8033 +       GMAC_STATUS_T   status;
8034 +       unsigned int    reg_val, ability,wan_port_id;
8035 +       unsigned int    i = 0;
8036 +
8037 +#ifdef VITESSE_G5SWITCH
8038 +       if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1)){
8039 +#if 0
8040 +               rcv_mask = SPI_read(2,0,0x10);                  // Receive mask
8041 +               rcv_mask |= 0x4F;
8042 +               for(i=0;i<4;i++){
8043 +                       reg_val = BIT(26)|(i<<21)|(10<<16);
8044 +                       SPI_write(3,0,1,reg_val);
8045 +                       msleep(10);
8046 +                       reg_val = SPI_read(3,0,2);
8047 +                       if(reg_val & 0x0c00){
8048 +                               printk("Port%d:Giga mode\n",i);
8049 +                               SPI_write(1,i,0x00,0x300701B1);
8050 +                               SPI_write(1,i,0x00,0x10070181);
8051 +                               switch_pre_link[i]=LINK_UP;
8052 +                               switch_pre_speed[i]=GMAC_SPEED_1000;
8053 +                       }
8054 +                       else{
8055 +                               reg_val = BIT(26)|(i<<21)|(5<<16);
8056 +                               SPI_write(3,0,1,reg_val);
8057 +                               msleep(10);
8058 +                               ability = (reg_val = SPI_read(3,0,2)&0x5e0) >>5;
8059 +                               if ((ability & 0x0C)) /* 100M full duplex */
8060 +                               {
8061 +                                       SPI_write(1,i,0x00,0x30050472);
8062 +                                       SPI_write(1,i,0x00,0x10050442);
8063 +                                       printk("Port%d:100M\n",i);
8064 +                                       switch_pre_link[i]=LINK_UP;
8065 +                               switch_pre_speed[i]=GMAC_SPEED_100;
8066 +                               }
8067 +                               else if((ability & 0x03)) /* 10M full duplex */
8068 +                               {
8069 +                                       SPI_write(1,i,0x00,0x30050473);
8070 +                                       SPI_write(1,i,0x00,0x10050443);
8071 +                                       printk("Port%d:10M\n",i);
8072 +                                       switch_pre_link[i]=LINK_UP;
8073 +                                       switch_pre_speed[i]=GMAC_SPEED_10;
8074 +                               }
8075 +                               else{
8076 +                                       SPI_write(1,i,0x00,BIT(16));                    // disable RX
8077 +                                       SPI_write(5,0,0x0E,BIT(i));                     // dicard packet
8078 +                                       while((SPI_read(5,0,0x0C)&BIT(i))==0)           // wait to be empty
8079 +                                               msleep(1);
8080 +
8081 +                                       SPI_write(1,i,0x00,0x20000030);                 // PORT_RST
8082 +                                       switch_pre_link[i]=LINK_DOWN;
8083 +                                       switch_pre_speed[i]=GMAC_SPEED_10;
8084 +                                       rcv_mask &= ~BIT(i);
8085 +                                       SPI_write(2,0,0x10,rcv_mask);                   // Disable Receive
8086 +                               }
8087 +                       }
8088 +               }
8089 +#endif
8090 +               gmac_get_switch_status(dev);
8091 +               gmac_write_reg(tp->base_addr, GMAC_STATUS, 0x7d, 0x0000007f);
8092 +//             SPI_write(2,0,0x10,rcv_mask);                   // Enable Receive
8093 +               return ;
8094 +       }
8095 +#endif
8096 +
8097 +       reg_val = gmac_get_phy_vendor(tp->phy_addr);
8098 +       printk("GMAC-%d Addr %d Vendor ID: 0x%08x\n", tp->port_id, tp->phy_addr, reg_val);
8099 +
8100 +       switch (tp->phy_mode)
8101 +       {
8102 +               case GMAC_PHY_GMII:
8103 +               mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
8104 +               #ifdef CONFIG_SL3516_ASIC
8105 +               mii_write(tp->phy_addr,0x09,0x0300); /* advertise 1000M full/half duplex */
8106 +               #else
8107 +               mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M full/half duplex */
8108 +               #endif
8109 +               break;
8110 +               case GMAC_PHY_RGMII_100:
8111 +               mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
8112 +               mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M */
8113 +               break;
8114 +               case GMAC_PHY_RGMII_1000:
8115 +               mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
8116 +               #ifdef CONFIG_SL3516_ASIC
8117 +               mii_write(tp->phy_addr,0x09,0x0300); /* advertise 1000M full/half duplex */
8118 +               #else
8119 +               mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M full/half duplex */
8120 +               #endif
8121 +               break;
8122 +               case GMAC_PHY_MII:
8123 +               default:
8124 +               mii_write(tp->phy_addr,0x04,0x05e1); /* advertisement 100M full duplex, pause capable on */
8125 +               mii_write(tp->phy_addr,0x09,0x0000); /* advertise no 1000M */
8126 +               break;
8127 +       }
8128 +
8129 +       mii_write(tp->phy_addr,0x18,0x0041);    // Phy active led
8130 +       if (tp->auto_nego_cfg)
8131 +       {
8132 +               reg_val = 0x1200 | (1 << 15);
8133 +               mii_write(tp->phy_addr,0x00,reg_val); /* Enable and Restart Auto-Negotiation */
8134 +               mdelay(500);
8135 +               reg_val &= ~(1 << 15);
8136 +               mii_write(tp->phy_addr, 0x00, reg_val);
8137 +       }
8138 +       else
8139 +       {
8140 +               reg_val = 0;
8141 +               reg_val |= (tp->full_duplex_cfg) ? (1 << 8) : 0;
8142 +               reg_val |= (tp->speed_cfg == GMAC_SPEED_1000) ? (1 << 6) : 0;
8143 +               reg_val |= (tp->speed_cfg == GMAC_SPEED_100) ? (1 << 13) : 0;
8144 +               mii_write(tp->phy_addr, 0x00, reg_val);
8145 +               mdelay(100);
8146 +
8147 +               reg_val |= (1 << 15);   // Reset PHY;
8148 +               mii_write(tp->phy_addr, 0x00, reg_val);
8149 +       }
8150 +
8151 +       status.bits32 = 0;
8152 +       /* set PHY operation mode */
8153 +       status.bits.mii_rmii = tp->phy_mode;
8154 +       status.bits.reserved = 1;
8155 +       mdelay(100);
8156 +       while (((reg_val=mii_read(tp->phy_addr,0x01)) & 0x00000004)!=0x04)
8157 +       {
8158 +               msleep(100);
8159 +               i++;
8160 +               if (i > 30)
8161 +               break;
8162 +       }
8163 +       if (i>30)
8164 +       {
8165 +               tp->pre_phy_status = LINK_DOWN;
8166 +               status.bits.link = LINK_DOWN;
8167 +               //              clear_bit(__LINK_STATE_START, &dev->state);
8168 +               printk("Link Down (0x%04x) ", reg_val);
8169 +               if(Giga_switch == 1)
8170 +               {
8171 +                               wan_port_id = 1;
8172 +#ifdef CONFIG_SL351x_SYSCTL
8173 +                               storlink_ctl.link[ wan_port_id] = 0;
8174 +#endif
8175 +               }
8176 +               else
8177 +               {
8178 +#ifdef CONFIG_SL351x_SYSCTL
8179 +                               storlink_ctl.link[ tp->port_id] = 0;
8180 +#endif
8181 +               }
8182 +       }
8183 +       else
8184 +       {
8185 +               tp->pre_phy_status = LINK_UP;
8186 +               status.bits.link = LINK_UP;
8187 +               //              set_bit(__LINK_STATE_START, &dev->state);
8188 +               printk("Link Up (0x%04x) ",reg_val);
8189 +               if(Giga_switch == 1)
8190 +               {
8191 +                               wan_port_id = 1;
8192 +#ifdef CONFIG_SL351x_SYSCTL
8193 +                               storlink_ctl.link[ wan_port_id] = 1;
8194 +#endif
8195 +               }
8196 +               else
8197 +               {
8198 +#ifdef CONFIG_SL351x_SYSCTL
8199 +                               storlink_ctl.link[ tp->port_id] = 1;
8200 +#endif
8201 +               }
8202 +       }
8203 +       //    value = mii_read(PHY_ADDR,0x05);
8204 +
8205 +       ability = (mii_read(tp->phy_addr,0x05) & 0x05E0) >> 5;
8206 +
8207 +       //#ifdef CONFIG_SL3516_ASIC
8208 +       reg_val = mii_read(tp->phy_addr,10);
8209 +       printk("MII REG 10 = 0x%x\n",reg_val);
8210 +
8211 +       if ((reg_val & 0x0800) == 0x0800)
8212 +       {
8213 +               status.bits.duplex = 1;
8214 +               status.bits.speed = 2;
8215 +               if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
8216 +               status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
8217 +
8218 +               printk(" 1000M/Full \n");
8219 +       }
8220 +       else if ((reg_val & 0x0400) == 0x0400)
8221 +       {
8222 +               status.bits.duplex = 0;
8223 +               status.bits.speed = 2;
8224 +               if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
8225 +               status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
8226 +
8227 +               printk(" 1000M/Half \n");
8228 +       }
8229 +       //#endif
8230 +       else
8231 +       {
8232 +               #ifdef CONFIG_SL3516_ASIC
8233 +               if (status.bits.mii_rmii == GMAC_PHY_RGMII_1000)
8234 +               status.bits.mii_rmii = GMAC_PHY_RGMII_100;
8235 +               #endif
8236 +               printk("MII REG 5 (bit 5:15) = 0x%x\n", ability);
8237 +               if ((ability & 0x08)==0x08) /* 100M full duplex */
8238 +               {
8239 +                       status.bits.duplex = 1;
8240 +                       status.bits.speed = 1;
8241 +                       printk(" 100M/Full\n");
8242 +
8243 +               }
8244 +               else if ((ability & 0x04)==0x04) /* 100M half duplex */
8245 +               {
8246 +                       status.bits.duplex = 0;
8247 +                       status.bits.speed = 1;
8248 +                       printk(" 100M/Half\n");
8249 +
8250 +               }
8251 +               else if ((ability & 0x02)==0x02) /* 10M full duplex */
8252 +               {
8253 +                       status.bits.duplex = 1;
8254 +                       status.bits.speed = 0;
8255 +                       printk(" 10M/Full\n");
8256 +
8257 +               }
8258 +               else if ((ability & 0x01)==0x01) /* 10M half duplex */
8259 +               {
8260 +                       status.bits.duplex = 0;
8261 +                       status.bits.speed = 0;
8262 +                       printk(" 10M/Half\n");
8263 +
8264 +               }
8265 +       }
8266 +       if ((ability & 0x20)==0x20)
8267 +       {
8268 +               tp->flow_control_enable = 1;
8269 +               printk("Flow Control Enable.\n");
8270 +       }
8271 +       else
8272 +       {
8273 +               tp->flow_control_enable = 0;
8274 +               printk("Flow Control Disable.\n");
8275 +       }
8276 +       tp->full_duplex_status = status.bits.duplex;
8277 +       tp->speed_status = status.bits.speed;
8278 +       if (!tp->auto_nego_cfg)
8279 +       {
8280 +               status.bits.duplex = tp->full_duplex_cfg;
8281 +               status.bits.speed = tp->speed_cfg;
8282 +       }
8283 +       toe_gmac_disable_tx_rx(dev);
8284 +       mdelay(10);
8285 +       gmac_write_reg(tp->base_addr, GMAC_STATUS, status.bits32, 0x0000007f);
8286 +       toe_gmac_enable_tx_rx(dev);
8287 +}
8288 +
8289 +/*----------------------------------------------------------------------
8290 +* gmac_phy_thread
8291 +*----------------------------------------------------------------------*/
8292 +static int gmac_phy_thread (void *data)
8293 +{
8294 +       struct net_device   *dev = data;
8295 +       GMAC_INFO_T *tp = dev->priv;
8296 +       unsigned long       timeout;
8297 +
8298 +    daemonize("%s", dev->name);
8299 +       allow_signal(SIGTERM);
8300 +//     reparent_to_init();
8301 +//     spin_lock_irq(&current->sigmask_lock);
8302 +//     sigemptyset(&current->blocked);
8303 +//     recalc_sigpending(current);
8304 +//     spin_unlock_irq(&current->sigmask_lock);
8305 +//     strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
8306 +//     current->comm[sizeof(current->comm) - 1] = '\0';
8307 +
8308 +       while (1)
8309 +       {
8310 +           timeout = next_tick;
8311 +               do
8312 +               {
8313 +                       timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
8314 +               } while (!signal_pending (current) && (timeout > 0));
8315 +
8316 +               if (signal_pending (current))
8317 +               {
8318 +//                     spin_lock_irq(&current->sigmask_lock);
8319 +                       flush_signals(current);
8320 +//                     spin_unlock_irq(&current->sigmask_lock);
8321 +               }
8322 +
8323 +               if (tp->time_to_die)
8324 +                       break;
8325 +
8326 +               // printk("%s : Polling MAC %d PHY Status...\n",__func__, tp->port_id);
8327 +               rtnl_lock ();
8328 +               if (tp->auto_nego_cfg){
8329 +#ifdef VITESSE_G5SWITCH
8330 +                       if((tp->port_id == GMAC_PORT1)&&(Giga_switch==1))
8331 +                               gmac_get_switch_status(dev);
8332 +                       else
8333 +#endif
8334 +                               gmac_get_phy_status(dev); //temp remove
8335 +               }
8336 +               rtnl_unlock ();
8337 +       }
8338 +       complete_and_exit (&tp->thr_exited, 0);
8339 +}
8340 +
8341 +/*----------------------------------------------------------------------
8342 +* gmac_get_switch_status
8343 +*----------------------------------------------------------------------*/
8344 +#ifdef VITESSE_G5SWITCH
8345 +void gmac_get_switch_status(struct net_device *dev)
8346 +{
8347 +       GMAC_INFO_T *tp = dev->priv;
8348 +       GMAC_CONFIG0_T  config0,config0_mask;
8349 +       unsigned int    switch_port_id;
8350 +       int get_link=0;
8351 +
8352 +       get_link = Get_Set_port_status();
8353 +       if(get_link){                           // link
8354 +               if(ever_dwon){
8355 +                       ever_dwon = 0;
8356 +                       toe_gmac_enable_tx_rx(dev);
8357 +                       netif_wake_queue(dev);
8358 +                       set_bit(__LINK_STATE_START, &dev->state);
8359 +               }
8360 +       }
8361 +       else{                                   // all down
8362 +               //printk("All link down\n");
8363 +               ever_dwon=1;
8364 +               netif_stop_queue(dev);
8365 +               toe_gmac_disable_tx_rx(dev);
8366 +               clear_bit(__LINK_STATE_START, &dev->state);
8367 +       }
8368 +
8369 +       if ( tp->port_id == 1 )
8370 +               switch_port_id = 0;
8371 +#ifdef CONFIG_SL351x_SYSCTL
8372 +       if (get_link)
8373 +       {
8374 +               storlink_ctl.link[switch_port_id] = 1;
8375 +       }
8376 +       else
8377 +       {
8378 +               storlink_ctl.link[switch_port_id] = 0;
8379 +       }
8380 +       if (storlink_ctl.pauseoff == 1)
8381 +               {
8382 +                       if (tp->flow_control_enable == 1)
8383 +                       {
8384 +                               config0.bits32 = 0;
8385 +                               config0_mask.bits32 = 0;
8386 +                               config0.bits.tx_fc_en = 0; /* disable tx flow control */
8387 +                               config0.bits.rx_fc_en = 0; /* disable rx flow control */
8388 +                               config0_mask.bits.tx_fc_en = 1;
8389 +                               config0_mask.bits.rx_fc_en = 1;
8390 +                               gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
8391 +                               printk("Disable SWITCH Flow Control...\n");
8392 +                       }
8393 +                               tp->flow_control_enable = 0;
8394 +               }
8395 +               else
8396 +#endif
8397 +               {
8398 +                       if (tp->flow_control_enable == 0)
8399 +                       {
8400 +                               config0.bits32 = 0;
8401 +                               config0_mask.bits32 = 0;
8402 +                               config0.bits.tx_fc_en = 1; /* enable tx flow control */
8403 +                               config0.bits.rx_fc_en = 1; /* enable rx flow control */
8404 +                               config0_mask.bits.tx_fc_en = 1;
8405 +                               config0_mask.bits.rx_fc_en = 1;
8406 +                               gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
8407 +                               printk("Enable SWITCH Flow Control...\n");
8408 +                       }
8409 +                       tp->flow_control_enable = 1;
8410 +               }
8411 +       return ;
8412 +
8413 +}
8414 +#endif
8415 +
8416 +/*----------------------------------------------------------------------
8417 +* gmac_get_phy_status
8418 +*----------------------------------------------------------------------*/
8419 +void gmac_get_phy_status(struct net_device *dev)
8420 +{
8421 +       GMAC_INFO_T *tp = dev->priv;
8422 +       GMAC_CONFIG0_T  config0,config0_mask;
8423 +       GMAC_STATUS_T   status, old_status;
8424 +       unsigned int    reg_val,ability,wan_port_id;
8425 +
8426 +       old_status.bits32 = status.bits32 = gmac_read_reg(tp->base_addr, GMAC_STATUS);
8427 +
8428 +
8429 +       /* read PHY status register */
8430 +       reg_val = mii_read(tp->phy_addr,0x01);
8431 +       if ((reg_val & 0x0024) == 0x0024) /* link is established and auto_negotiate process completed */
8432 +       {
8433 +               ability = (mii_read(tp->phy_addr,0x05) & 0x05E0) >> 5;
8434 +               /* read PHY Auto-Negotiation Link Partner Ability Register */
8435 +               #ifdef CONFIG_SL3516_ASIC
8436 +               reg_val = mii_read(tp->phy_addr,10);
8437 +               if ((reg_val & 0x0800) == 0x0800)
8438 +               {
8439 +                       status.bits.duplex = 1;
8440 +                       status.bits.speed = 2;
8441 +                       if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
8442 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
8443 +               }
8444 +               else if ((reg_val & 0x0400) == 0x0400)
8445 +               {
8446 +                       status.bits.duplex = 0;
8447 +                       status.bits.speed = 2;
8448 +                       if (status.bits.mii_rmii == GMAC_PHY_RGMII_100)
8449 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_1000;
8450 +               }
8451 +               else
8452 +               #endif
8453 +               {
8454 +                       #ifdef CONFIG_SL3516_ASIC
8455 +                       if (status.bits.mii_rmii == GMAC_PHY_RGMII_1000)
8456 +                       status.bits.mii_rmii = GMAC_PHY_RGMII_100;
8457 +                       #endif
8458 +                       if ((ability & 0x08)==0x08) /* 100M full duplex */
8459 +                       {
8460 +                               status.bits.duplex = 1;
8461 +                               status.bits.speed = 1;
8462 +                       }
8463 +                       else if ((ability & 0x04)==0x04) /* 100M half duplex */
8464 +                       {
8465 +                               status.bits.duplex = 0;
8466 +                               status.bits.speed = 1;
8467 +                       }
8468 +                       else if ((ability & 0x02)==0x02) /* 10M full duplex */
8469 +                       {
8470 +                               status.bits.duplex = 1;
8471 +                               status.bits.speed = 0;
8472 +                       }
8473 +                       else if ((ability & 0x01)==0x01) /* 10M half duplex */
8474 +                       {
8475 +                               status.bits.duplex = 0;
8476 +                               status.bits.speed = 0;
8477 +                       }
8478 +               }
8479 +               status.bits.link = LINK_UP; /* link up */
8480 +               if(Giga_switch==1)
8481 +               {
8482 +                               wan_port_id = 1;
8483 +#ifdef CONFIG_SL351x_SYSCTL
8484 +                               storlink_ctl.link[ wan_port_id] = 1;
8485 +               }
8486 +               else
8487 +               {
8488 +                               storlink_ctl.link[ tp->port_id] = 1;
8489 +#endif
8490 +               }
8491 +               if ((ability & 0x20)==0x20)
8492 +               {
8493 +                       if (tp->flow_control_enable == 0)
8494 +                       {
8495 +                               config0.bits32 = 0;
8496 +                               config0_mask.bits32 = 0;
8497 +                               config0.bits.tx_fc_en = 1; /* enable tx flow control */
8498 +                               config0.bits.rx_fc_en = 1; /* enable rx flow control */
8499 +                               config0_mask.bits.tx_fc_en = 1;
8500 +                               config0_mask.bits.rx_fc_en = 1;
8501 +                               gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
8502 +                               printk("GMAC-%d Flow Control Enable.\n", tp->port_id);
8503 +                       }
8504 +                       tp->flow_control_enable = 1;
8505 +               }
8506 +               else
8507 +               {
8508 +                       if (tp->flow_control_enable == 1)
8509 +                       {
8510 +                               config0.bits32 = 0;
8511 +                               config0_mask.bits32 = 0;
8512 +                               config0.bits.tx_fc_en = 0; /* disable tx flow control */
8513 +                               config0.bits.rx_fc_en = 0; /* disable rx flow control */
8514 +                               config0_mask.bits.tx_fc_en = 1;
8515 +                               config0_mask.bits.rx_fc_en = 1;
8516 +                               gmac_write_reg(tp->base_addr, GMAC_CONFIG0,config0.bits32,config0_mask.bits32);
8517 +                               printk("GMAC-%d Flow Control Disable.\n", tp->port_id);
8518 +                       }
8519 +                       tp->flow_control_enable = 0;
8520 +               }
8521 +
8522 +               if (tp->pre_phy_status == LINK_DOWN)
8523 +               {
8524 +                       printk("GMAC-%d LINK_UP......\n",tp->port_id);
8525 +                       tp->pre_phy_status = LINK_UP;
8526 +               }
8527 +       }
8528 +       else
8529 +       {
8530 +               status.bits.link = LINK_DOWN; /* link down */
8531 +               if(Giga_switch == 1)
8532 +               {
8533 +                               wan_port_id = 1;
8534 +#ifdef CONFIG_SL351x_SYSCTL
8535 +                               storlink_ctl.link[ wan_port_id] = 0;
8536 +               }
8537 +               else
8538 +               {
8539 +                               storlink_ctl.link[ tp->port_id] = 0;
8540 +#endif
8541 +               }
8542 +               if (tp->pre_phy_status == LINK_UP)
8543 +               {
8544 +                       printk("GMAC-%d LINK_Down......\n",tp->port_id);
8545 +                       tp->pre_phy_status = LINK_DOWN;
8546 +               }
8547 +       }
8548 +
8549 +       tp->full_duplex_status = status.bits.duplex;
8550 +       tp->speed_status = status.bits.speed;
8551 +       if (!tp->auto_nego_cfg)
8552 +       {
8553 +               status.bits.duplex = tp->full_duplex_cfg;
8554 +               status.bits.speed = tp->speed_cfg;
8555 +       }
8556 +
8557 +       if (old_status.bits32 != status.bits32)
8558 +       {
8559 +               netif_stop_queue(dev);
8560 +               toe_gmac_disable_tx_rx(dev);
8561 +               clear_bit(__LINK_STATE_START, &dev->state);
8562 +               printk("GMAC-%d Change Status Bits 0x%x-->0x%x\n",tp->port_id, old_status.bits32, status.bits32);
8563 +               mdelay(10); // let GMAC consume packet
8564 +               gmac_write_reg(tp->base_addr, GMAC_STATUS, status.bits32, 0x0000007f);
8565 +               if (status.bits.link == LINK_UP)
8566 +               {
8567 +                       toe_gmac_enable_tx_rx(dev);
8568 +                       netif_wake_queue(dev);
8569 +                       set_bit(__LINK_STATE_START, &dev->state);
8570 +               }
8571 +       }
8572 +}
8573 +
8574 +/***************************************/
8575 +/* define GPIO module base address     */
8576 +/***************************************/
8577 +#define GPIO_BASE_ADDR  (IO_ADDRESS(SL2312_GPIO_BASE))
8578 +#define GPIO_BASE_ADDR1  (IO_ADDRESS(SL2312_GPIO_BASE1))
8579 +
8580 +/* define GPIO pin for MDC/MDIO */
8581 +#ifdef CONFIG_SL3516_ASIC
8582 +#define H_MDC_PIN           22
8583 +#define H_MDIO_PIN          21
8584 +#define G_MDC_PIN           22
8585 +#define G_MDIO_PIN          21
8586 +#else
8587 +#define H_MDC_PIN           3
8588 +#define H_MDIO_PIN          2
8589 +#define G_MDC_PIN           0
8590 +#define G_MDIO_PIN          1
8591 +#endif
8592 +
8593 +//#define GPIO_MDC             0x80000000
8594 +//#define GPIO_MDIO            0x00400000
8595 +
8596 +static unsigned int GPIO_MDC = 0;
8597 +static unsigned int GPIO_MDIO = 0;
8598 +static unsigned int GPIO_MDC_PIN = 0;
8599 +static unsigned int GPIO_MDIO_PIN = 0;
8600 +
8601 +// For PHY test definition!!
8602 +#define LPC_EECK               0x02
8603 +#define LPC_EDIO               0x04
8604 +#define LPC_GPIO_SET           3
8605 +#define LPC_BASE_ADDR          IO_ADDRESS(IT8712_IO_BASE)
8606 +#define inb_gpio(x)            inb(LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
8607 +#define outb_gpio(x, y)                outb(y, LPC_BASE_ADDR + IT8712_GPIO_BASE + x)
8608 +
8609 +enum GPIO_REG
8610 +{
8611 +    GPIO_DATA_OUT   = 0x00,
8612 +    GPIO_DATA_IN    = 0x04,
8613 +    GPIO_PIN_DIR    = 0x08,
8614 +    GPIO_BY_PASS    = 0x0c,
8615 +    GPIO_DATA_SET   = 0x10,
8616 +    GPIO_DATA_CLEAR = 0x14,
8617 +};
8618 +/***********************/
8619 +/*    MDC : GPIO[31]   */
8620 +/*    MDIO: GPIO[22]   */
8621 +/***********************/
8622 +
8623 +/***************************************************
8624 +* All the commands should have the frame structure:
8625 +*<PRE><ST><OP><PHYAD><REGAD><TA><DATA><IDLE>
8626 +****************************************************/
8627 +
8628 +/*****************************************************************
8629 +* Inject a bit to NWay register through CSR9_MDC,MDIO
8630 +*******************************************************************/
8631 +void mii_serial_write(char bit_MDO) // write data into mii PHY
8632 +{
8633 +#ifdef CONFIG_SL2312_LPC_IT8712
8634 +       unsigned char iomode,status;
8635 +
8636 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
8637 +       iomode |= (LPC_EECK|LPC_EDIO) ;                         // Set EECK,EDIO,EECS output
8638 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
8639 +
8640 +       if(bit_MDO)
8641 +       {
8642 +               status = inb_gpio( LPC_GPIO_SET);
8643 +               status |= LPC_EDIO ;            //EDIO high
8644 +               outb_gpio(LPC_GPIO_SET, status);
8645 +       }
8646 +       else
8647 +       {
8648 +               status = inb_gpio( LPC_GPIO_SET);
8649 +               status &= ~(LPC_EDIO) ;         //EDIO low
8650 +               outb_gpio(LPC_GPIO_SET, status);
8651 +       }
8652 +
8653 +       status |= LPC_EECK ;            //EECK high
8654 +       outb_gpio(LPC_GPIO_SET, status);
8655 +
8656 +       status &= ~(LPC_EECK) ;         //EECK low
8657 +       outb_gpio(LPC_GPIO_SET, status);
8658 +
8659 +#else
8660 +    unsigned int addr;
8661 +    unsigned int value;
8662 +
8663 +    addr = GPIO_BASE_ADDR + GPIO_PIN_DIR;
8664 +    value = readl(addr) | GPIO_MDC | GPIO_MDIO; /* set MDC/MDIO Pin to output */
8665 +    writel(value,addr);
8666 +    if(bit_MDO)
8667 +    {
8668 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
8669 +        writel(GPIO_MDIO,addr); /* set MDIO to 1 */
8670 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
8671 +        writel(GPIO_MDC,addr); /* set MDC to 1 */
8672 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
8673 +        writel(GPIO_MDC,addr); /* set MDC to 0 */
8674 +    }
8675 +    else
8676 +    {
8677 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
8678 +        writel(GPIO_MDIO,addr); /* set MDIO to 0 */
8679 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_SET);
8680 +        writel(GPIO_MDC,addr); /* set MDC to 1 */
8681 +        addr = (GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
8682 +        writel(GPIO_MDC,addr); /* set MDC to 0 */
8683 +    }
8684 +
8685 +#endif
8686 +}
8687 +
8688 +/**********************************************************************
8689 +* read a bit from NWay register through CSR9_MDC,MDIO
8690 +***********************************************************************/
8691 +unsigned int mii_serial_read(void) // read data from mii PHY
8692 +{
8693 +#ifdef CONFIG_SL2312_LPC_IT8712
8694 +       unsigned char iomode,status;
8695 +       unsigned int value ;
8696 +
8697 +       iomode = LPCGetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET);
8698 +       iomode &= ~(LPC_EDIO) ;         // Set EDIO input
8699 +       iomode |= (LPC_EECK) ;          // Set EECK,EECS output
8700 +       LPCSetConfig(LDN_GPIO, 0xc8 + LPC_GPIO_SET, iomode);
8701 +
8702 +       status = inb_gpio( LPC_GPIO_SET);
8703 +       status |= LPC_EECK ;            //EECK high
8704 +       outb_gpio(LPC_GPIO_SET, status);
8705 +
8706 +       status &= ~(LPC_EECK) ;         //EECK low
8707 +       outb_gpio(LPC_GPIO_SET, status);
8708 +
8709 +       value = inb_gpio( LPC_GPIO_SET);
8710 +
8711 +       value = value>>2 ;
8712 +       value &= 0x01;
8713 +
8714 +       return value ;
8715 +
8716 +#else
8717 +    unsigned int *addr;
8718 +    unsigned int value;
8719 +
8720 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_PIN_DIR);
8721 +    value = readl(addr) & ~GPIO_MDIO; //0xffbfffff;   /* set MDC to output and MDIO to input */
8722 +    writel(value,addr);
8723 +
8724 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_SET);
8725 +    writel(GPIO_MDC,addr); /* set MDC to 1 */
8726 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_CLEAR);
8727 +    writel(GPIO_MDC,addr); /* set MDC to 0 */
8728 +
8729 +    addr = (unsigned int *)(GPIO_BASE_ADDR + GPIO_DATA_IN);
8730 +    value = readl(addr);
8731 +    value = (value & (1<<GPIO_MDIO_PIN)) >> GPIO_MDIO_PIN;
8732 +    return(value);
8733 +
8734 +#endif
8735 +}
8736 +
8737 +/***************************************
8738 +* preamble + ST
8739 +***************************************/
8740 +void mii_pre_st(void)
8741 +{
8742 +    unsigned char i;
8743 +
8744 +    for(i=0;i<32;i++) // PREAMBLE
8745 +        mii_serial_write(1);
8746 +    mii_serial_write(0); // ST
8747 +    mii_serial_write(1);
8748 +}
8749 +
8750 +
8751 +/******************************************
8752 +* Read MII register
8753 +* phyad -> physical address
8754 +* regad -> register address
8755 +***************************************** */
8756 +unsigned int mii_read(unsigned char phyad,unsigned char regad)
8757 +{
8758 +    unsigned int i,value;
8759 +    unsigned int bit;
8760 +
8761 +    if (phyad == GPHY_ADDR)
8762 +    {
8763 +        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
8764 +        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
8765 +    }
8766 +    else
8767 +    {
8768 +        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
8769 +        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
8770 +    }
8771 +    GPIO_MDC = (1<<GPIO_MDC_PIN);
8772 +    GPIO_MDIO = (1<<GPIO_MDIO_PIN);
8773 +
8774 +    mii_pre_st(); // PRE+ST
8775 +    mii_serial_write(1); // OP
8776 +    mii_serial_write(0);
8777 +
8778 +    for (i=0;i<5;i++) { // PHYAD
8779 +        bit= ((phyad>>(4-i)) & 0x01) ? 1 :0 ;
8780 +        mii_serial_write(bit);
8781 +    }
8782 +
8783 +    for (i=0;i<5;i++) { // REGAD
8784 +        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
8785 +        mii_serial_write(bit);
8786 +    }
8787 +
8788 +    mii_serial_read(); // TA_Z
8789 +//    if((bit=mii_serial_read()) !=0 ) // TA_0
8790 +//    {
8791 +//        return(0);
8792 +//    }
8793 +    value=0;
8794 +    for (i=0;i<16;i++) { // READ DATA
8795 +        bit=mii_serial_read();
8796 +        value += (bit<<(15-i)) ;
8797 +    }
8798 +
8799 +    mii_serial_write(0); // dumy clock
8800 +    mii_serial_write(0); // dumy clock
8801 +
8802 +       //printk("%s: phy_addr=0x%x reg_addr=0x%x value=0x%x \n",__func__,phyad,regad,value);
8803 +    return(value);
8804 +}
8805 +
8806 +/******************************************
8807 +* Write MII register
8808 +* phyad -> physical address
8809 +* regad -> register address
8810 +* value -> value to be write
8811 +***************************************** */
8812 +void mii_write(unsigned char phyad,unsigned char regad,unsigned int value)
8813 +{
8814 +    unsigned int i;
8815 +    char bit;
8816 +
8817 +       printk("%s: phy_addr=0x%x reg_addr=0x%x value=0x%x \n",__func__,phyad,regad,value);
8818 +    if (phyad == GPHY_ADDR)
8819 +    {
8820 +        GPIO_MDC_PIN = G_MDC_PIN;   /* assigned MDC pin for giga PHY */
8821 +        GPIO_MDIO_PIN = G_MDIO_PIN; /* assigned MDIO pin for giga PHY */
8822 +    }
8823 +    else
8824 +    {
8825 +        GPIO_MDC_PIN = H_MDC_PIN;   /* assigned MDC pin for 10/100 PHY */
8826 +        GPIO_MDIO_PIN = H_MDIO_PIN; /* assigned MDIO pin for 10/100 PHY */
8827 +    }
8828 +    GPIO_MDC = (1<<GPIO_MDC_PIN);
8829 +    GPIO_MDIO = (1<<GPIO_MDIO_PIN);
8830 +
8831 +    mii_pre_st(); // PRE+ST
8832 +    mii_serial_write(0); // OP
8833 +    mii_serial_write(1);
8834 +    for (i=0;i<5;i++) { // PHYAD
8835 +        bit= ((phyad>>(4-i)) & 0x01) ? 1 :0 ;
8836 +        mii_serial_write(bit);
8837 +    }
8838 +
8839 +    for (i=0;i<5;i++) { // REGAD
8840 +        bit= ((regad>>(4-i)) & 0x01) ? 1 :0 ;
8841 +        mii_serial_write(bit);
8842 +    }
8843 +    mii_serial_write(1); // TA_1
8844 +    mii_serial_write(0); // TA_0
8845 +
8846 +    for (i=0;i<16;i++) { // OUT DATA
8847 +        bit= ((value>>(15-i)) & 0x01) ? 1 : 0 ;
8848 +        mii_serial_write(bit);
8849 +    }
8850 +    mii_serial_write(0); // dumy clock
8851 +    mii_serial_write(0); // dumy clock
8852 +}
8853 +
8854 +/*----------------------------------------------------------------------
8855 +* gmac_set_rx_mode
8856 +*----------------------------------------------------------------------*/
8857 +static void gmac_set_rx_mode(struct net_device *dev)
8858 +{
8859 +    GMAC_RX_FLTR_T      filter;
8860 +       unsigned int        mc_filter[2];       /* Multicast hash filter */
8861 +    int                 bit_nr;
8862 +       unsigned int        i;
8863 +       GMAC_INFO_T             *tp = dev->priv;
8864 +
8865 +//    printk("%s : dev->flags = %x \n",__func__,dev->flags);
8866 +//    dev->flags |= IFF_ALLMULTI;  /* temp */
8867 +    filter.bits32 = 0;
8868 +    filter.bits.error = 0;
8869 +       if (dev->flags & IFF_PROMISC)
8870 +       {
8871 +           filter.bits.error = 1;
8872 +        filter.bits.promiscuous = 1;
8873 +        filter.bits.broadcast = 1;
8874 +        filter.bits.multicast = 1;
8875 +        filter.bits.unicast = 1;
8876 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
8877 +       }
8878 +       else if (dev->flags & IFF_ALLMULTI)
8879 +       {
8880 +//        filter.bits.promiscuous = 1;
8881 +        filter.bits.broadcast = 1;
8882 +        filter.bits.multicast = 1;
8883 +        filter.bits.unicast = 1;
8884 +               mc_filter[1] = mc_filter[0] = 0xffffffff;
8885 +       }
8886 +       else
8887 +       {
8888 +               struct dev_mc_list *mclist;
8889 +
8890 +//        filter.bits.promiscuous = 1;
8891 +        filter.bits.broadcast = 1;
8892 +        filter.bits.multicast = 1;
8893 +        filter.bits.unicast = 1;
8894 +               mc_filter[1] = mc_filter[0] = 0;
8895 +               for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;i++, mclist = mclist->next)
8896 +               {
8897 +            bit_nr = ether_crc(ETH_ALEN,mclist->dmi_addr) & 0x0000003f;
8898 +            if (bit_nr < 32)
8899 +            {
8900 +                mc_filter[0] = mc_filter[0] | (1<<bit_nr);
8901 +            }
8902 +            else
8903 +            {
8904 +                mc_filter[1] = mc_filter[1] | (1<<(bit_nr-32));
8905 +            }
8906 +               }
8907 +       }
8908 +    gmac_write_reg(tp->base_addr,GMAC_RX_FLTR,filter.bits32,0xffffffff);  //chech base address!!!
8909 +    gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL0,mc_filter[0],0xffffffff);
8910 +    gmac_write_reg(tp->base_addr,GMAC_MCAST_FIL1,mc_filter[1],0xffffffff);
8911 +    return;
8912 +}
8913 +
8914 +#ifdef CONFIG_SL_NAPI
8915 +/*----------------------------------------------------------------------
8916 +* gmac_rx_poll
8917 +*----------------------------------------------------------------------*/
8918 +static int gmac_rx_poll(struct net_device *dev, int *budget)
8919 +{
8920 +       TOE_INFO_T                      *toe;
8921 +    GMAC_RXDESC_T      *curr_desc;
8922 +       struct sk_buff          *skb;
8923 +    DMA_RWPTR_T                        rwptr;
8924 +       unsigned int            pkt_size;
8925 +       unsigned int        desc_count;
8926 +       unsigned int        good_frame, chksum_status, rx_status;
8927 +       int                 rx_pkts_num = 0;
8928 +       int                 quota = min(dev->quota, *budget);
8929 +       GMAC_INFO_T                     *tp = (GMAC_INFO_T *)dev->priv;
8930 +       unsigned int            status4;
8931 +       volatile DMA_RWPTR_T    fq_rwptr;
8932 +       int                                     max_cnt = TOE_SW_FREEQ_DESC_NUM;//TOE_SW_FREEQ_DESC_NUM = 64
8933 +       //unsigned long         rx_old_bytes;
8934 +       struct net_device_stats *isPtr = (struct net_device_stats *)&tp->ifStatics;
8935 +       //unsigned long long    rx_time;
8936 +
8937 +
8938 +
8939 +#if 1
8940 +       if (do_again)
8941 +       {
8942 +                       toe_gmac_fill_free_q();
8943 +                       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
8944 +                       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
8945 +                       //printk("\n%s:: do_again toe_gmac_fill_free_q =======>status4=0x%x =====fq_rwptr =0x%8x======>JKJKJKJKJKJKJKJKJ \n", __func__,status4,fq_rwptr.bits32);
8946 +                       if (fq_rwptr.bits.wptr != fq_rwptr.bits.rptr)
8947 +                       {
8948 +                                               //status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
8949 +                                               do_again =0;
8950 +                                               //netif_rx_complete(dev);
8951 +                                               gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4, 0x1);
8952 +                                               fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
8953 +                                               rwptr.bits32 = readl(&tp->default_qhdr->word1);
8954 +                       }
8955 +                       else
8956 +                               return 1;
8957 +       }
8958 +#endif
8959 +       rwptr.bits32 = readl(&tp->default_qhdr->word1);
8960 +#if 0
8961 +       if (rwptr.bits.rptr != tp->rx_rwptr.bits.rptr)
8962 +       {
8963 +               mac_stop_txdma((struct net_device *)tp->dev);
8964 +               printk("Default Queue HW RD ptr (0x%x) != SW RD Ptr (0x%x)\n",
8965 +                               rwptr.bits32, tp->rx_rwptr.bits.rptr);
8966 +               while(1);
8967 +       }
8968 +#endif
8969 +       toe = (TOE_INFO_T *)&toe_private_data;
8970 +
8971 +       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
8972 +       //printk("%s:---Before-------------->Default Queue HW RW ptr (0x%8x),   fq_rwptr =0x%8x \n",__func__,rwptr.bits32,fq_rwptr.bits32 );
8973 +       //printk("%s:---Before while   rx_pkts_num=%d------rx_finished_idx=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rx_finished_idx,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
8974 +//     while ((--max_cnt) && (rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
8975 +
8976 +       while ((rwptr.bits.rptr != rwptr.bits.wptr) && (rx_pkts_num < quota))
8977 +       {
8978 +
8979 +       curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
8980 +               tp->default_q_cnt++;
8981 +       tp->rx_curr_desc = (unsigned int)curr_desc;
8982 +       rx_status = curr_desc->word0.bits.status;
8983 +       chksum_status = curr_desc->word0.bits.chksum_status;
8984 +       tp->rx_status_cnt[rx_status]++;
8985 +       tp->rx_chksum_cnt[chksum_status]++;
8986 +        pkt_size = curr_desc->word1.bits.byte_count;  /*total byte count in a frame*/
8987 +               desc_count = curr_desc->word0.bits.desc_count; /* get descriptor count per frame */
8988 +               good_frame=1;
8989 +               if ((curr_desc->word0.bits32 & (GMAC_RXDESC_0_T_derr | GMAC_RXDESC_0_T_perr))
8990 +                       || (pkt_size < 60)
8991 +                   || (chksum_status & 0x4)
8992 +                   || rx_status )
8993 +//                     || rx_status || (rwptr.bits.rptr > rwptr.bits.wptr ))
8994 +               {
8995 +                       good_frame = 0;
8996 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_derr)
8997 +                               printk("%s::derr (GMAC-%d)!!!\n", __func__, tp->port_id);
8998 +                       if (curr_desc->word0.bits32 & GMAC_RXDESC_0_T_perr)
8999 +                               printk("%s::perr (GMAC-%d)!!!\n", __func__, tp->port_id);
9000 +                       if (rx_status)
9001 +                       {
9002 +                               if (rx_status == 4 || rx_status == 7)
9003 +                                       isPtr->rx_crc_errors++;
9004 +//                             printk("%s::Status=%d (GMAC-%d)!!!\n", __func__, rx_status, tp->port_id);
9005 +                       }
9006 +#ifdef SL351x_GMAC_WORKAROUND
9007 +                       else if (pkt_size < 60)
9008 +                       {
9009 +                               if (tp->short_frames_cnt < GMAC_SHORT_FRAME_THRESHOLD)
9010 +                                       tp->short_frames_cnt++;
9011 +                               if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
9012 +                               {
9013 +                                       GMAC_CONFIG0_T config0;
9014 +                                       config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
9015 +                                       config0.bits.dis_rx = 1;
9016 +                                       writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
9017 +                                       config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
9018 +                                       config0.bits.dis_rx = 1;
9019 +                                       writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
9020 +                               }
9021 +                       }
9022 +#endif
9023 +//                     if (chksum_status)
9024 +//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
9025 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
9026 +                       dev_kfree_skb_irq(skb);
9027 +               }
9028 +               if (good_frame)
9029 +               {
9030 +                       if (curr_desc->word0.bits.drop)
9031 +                               printk("%s::Drop (GMAC-%d)!!!\n", __func__, tp->port_id);
9032 +//                     if (chksum_status)
9033 +//                             printk("%s::Checksum Status=%d (GMAC-%d)!!!\n", __func__, chksum_status, tp->port_id);
9034 +
9035 +#ifdef SL351x_GMAC_WORKAROUND
9036 +                       if (tp->short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
9037 +                       {
9038 +                               GMAC_CONFIG0_T config0;
9039 +                               config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
9040 +                               config0.bits.dis_rx = 0;
9041 +                               writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
9042 +                               config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
9043 +                               config0.bits.dis_rx = 0;
9044 +                               writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
9045 +                       }
9046 +                       tp->short_frames_cnt = 0;
9047 +#endif
9048 +               /* get frame information from the first descriptor of the frame */
9049 +                       isPtr->rx_packets++;
9050 +                       //consistent_sync((void *)__va(curr_desc->word2.buf_adr), pkt_size, PCI_DMA_FROMDEVICE);
9051 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
9052 +                       tp->curr_rx_skb = skb;
9053 +       //              curr_desc->word2.buf_adr = 0;
9054 +
9055 +                   //skb_reserve (skb, SKB_RESERVE_BYTES);
9056 +                       skb_reserve (skb, RX_INSERT_BYTES);     /* 2 byte align the IP fields. */
9057 +                       //if ((skb->tail+pkt_size) > skb->end )
9058 +                       //printk("%s::------------->Here skb->len=%d,pkt_size= %d,skb->head=0x%x,skb->tail= 0x%x, skb->end= 0x%x\n", __func__, skb->len, pkt_size,skb->head,skb->tail,skb->end);
9059 +                       skb_put(skb, pkt_size);
9060 +
9061 +
9062 +                       skb->dev = dev;
9063 +                       if (chksum_status == RX_CHKSUM_IP_UDP_TCP_OK)
9064 +                       {
9065 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
9066 +#ifdef CONFIG_SL351x_NAT
9067 +                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
9068 +                               {
9069 +                                       struct iphdr    *ip_hdr;
9070 +                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
9071 +                                       sl351x_nat_input(skb,
9072 +                                                                       tp->port_id,
9073 +                                                                       (void *)curr_desc->word3.bits.l3_offset,
9074 +                                                                       (void *)curr_desc->word3.bits.l4_offset);
9075 +                               }
9076 +#endif
9077 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
9078 +#if 0
9079 +#ifdef CONFIG_SL351x_RXTOE
9080 +                               if (storlink_ctl.rx_max_pktsize) {
9081 +                                       struct iphdr    *ip_hdr;
9082 +                                       struct tcphdr   *tcp_hdr;
9083 +                                       int ip_hdrlen;
9084 +
9085 +                                       ip_hdr = (struct iphdr*)&(skb->data[0]);
9086 +                                       if ((skb->protocol == __constant_htons(ETH_P_IP)) &&
9087 +                                          ((ip_hdr->protocol & 0x00ff) == IPPROTO_TCP)) {
9088 +                                               ip_hdrlen = ip_hdr->ihl << 2;
9089 +                                               tcp_hdr = (struct tcphdr*)&(skb->data[ip_hdrlen]);
9090 +                                               if (tcp_hdr->syn) {
9091 +                                                       struct toe_conn* connection = init_toeq(ip_hdr->version,
9092 +                                                                       ip_hdr, tcp_hdr, toe, &(skb->data[0]) - 14);
9093 +                                                       TCP_SKB_CB(skb)->connection = connection;
9094 +                                                       //      hash_dump_entry(TCP_SKB_CB(skb)->connection->hash_entry_index);
9095 +                                                       //              printk("%s::skb data %x, conn %x, mode %x\n",
9096 +                                                       //                      __func__, skb->data, connection, connection->mode);
9097 +                                               }
9098 +                                       }
9099 +                               }
9100 +#endif
9101 +#endif
9102 +                       }
9103 +                       else if (chksum_status == RX_CHKSUM_IP_OK_ONLY)
9104 +                       {
9105 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
9106 +#ifdef CONFIG_SL351x_NAT
9107 +                               if (nat_cfg.enabled && curr_desc->word3.bits.l3_offset && curr_desc->word3.bits.l4_offset)
9108 +                               {
9109 +                                       struct iphdr    *ip_hdr;
9110 +                                       ip_hdr = (struct iphdr *)&(skb->data[curr_desc->word3.bits.l3_offset]);
9111 +                                       if (ip_hdr->protocol == IPPROTO_UDP)
9112 +                                       {
9113 +                                               sl351x_nat_input(skb,
9114 +                                                                               tp->port_id,
9115 +                                                                               (void *)curr_desc->word3.bits.l3_offset,
9116 +                                                                               (void *)curr_desc->word3.bits.l4_offset);
9117 +                                       }
9118 +                                       else if (ip_hdr->protocol == IPPROTO_GRE)
9119 +                                       {
9120 +                                               sl351x_nat_input(skb,
9121 +                                                                       tp->port_id,
9122 +                                                                       (void *)curr_desc->word3.bits.l3_offset,
9123 +                                                                       (void *)curr_desc->word3.bits.l4_offset);
9124 +                                       }
9125 +                               }
9126 +#endif
9127 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
9128 +                       }
9129 +                       else
9130 +                       {
9131 +                               skb->protocol = eth_type_trans(skb,dev); /* set skb protocol */
9132 +                       }
9133 +                       //netif_rx(skb);  /* socket rx */
9134 +                       netif_receive_skb(skb); //For NAPI
9135 +                       dev->last_rx = jiffies;
9136 +
9137 +                       isPtr->rx_bytes += pkt_size;
9138 +                       //printk("------------------->isPtr->rx_bytes = %d\n",isPtr->rx_bytes);
9139 +
9140 +
9141 +        }
9142 +               // advance one for Rx default Q 0/1
9143 +               rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
9144 +               SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
9145 +       tp->rx_rwptr.bits32 = rwptr.bits32;
9146 +               rx_pkts_num++;
9147 +               //rwptr.bits32 = readl(&tp->default_qhdr->word1);//try read default_qhdr again
9148 +               //fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
9149 +               //printk("%s:---Loop  -------->rx_pkts_num=%d------------>Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits32,fq_rwptr.bits32 );
9150 +#if 0
9151 +               if ((status4 & 0x1) == 0)
9152 +               {
9153 +                       //if (!((dev->last_rx <= (rx_time + 2)) &&  (isPtr->rx_bytes > (rx_old_bytes + 1000000 ))))
9154 +                       if (tp->total_q_cnt_napi < 1024)
9155 +                       {
9156 +                               tp->total_q_cnt_napi++;
9157 +                               toe_gmac_fill_free_q();  //for iperf test disable
9158 +                       }
9159 +                       //else
9160 +                               //printk("%s:---isPtr->rx_bytes =%u , rx_old_bytes =%u\n",__func__,isPtr->rx_bytes,rx_old_bytes );
9161 +
9162 +               }
9163 +#endif
9164 +               //rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
9165 +               //printk("%s:---Loop  -------->rx_pkts_num=%d----rwptr.bits.rptr=0x%x-------->Default Queue HW RW ptr = (0x%8x),   fq_rwptr =0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits32,fq_rwptr.bits32 );
9166 +               //printk("%s:---Loop  rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
9167 +       }
9168 +       // advance one for Rx default Q 0/1
9169 +
9170 +               //rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
9171 +               //SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
9172 +       //tp->rx_rwptr.bits32 = rwptr.bits32;
9173 +       //rwptr.bits.rptr = rwptr.bits.rptr;
9174 +
9175 +       dev->quota -= rx_pkts_num;
9176 +       *budget -= rx_pkts_num;
9177 +
9178 +       status4 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);//try read SWFQ empty again
9179 +       //fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
9180 +       rwptr.bits32 = readl(&tp->default_qhdr->word1); //try read default_qhdr again
9181 +       //printk("%s:---After    rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
9182 +//     if (rwptr.bits.rptr > rwptr.bits.wptr )
9183 +//                     {
9184 +                               //toe_gmac_disable_rx(dev);
9185 +                               //wait_event_interruptible_timeout(freeq_wait,
9186 +                                       //(rx_pkts_num == 100), CMTP_INTEROP_TIMEOUT);
9187 +                               //printk("\n%s:: return 22222=======> rx_pkts_num =%d,   rwptr.bits.rptr=%d,   rwptr.bits.wptr = %d ====---------=======>JKJKJKJKJK\n",
9188 +                                       //__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
9189 +//                             return 1;
9190 +//                     }
9191 +
9192 +       if (rwptr.bits.rptr == rwptr.bits.wptr)
9193 +       {
9194 +               unsigned int data32;
9195 +                       //printk("%s:---[rwptr.bits.rptr == rwptr.bits.wptr]   rx_pkts_num=%d------rwptr.bits.rptr=0x%x------->Default_Q [rwptr.bits.rptr(SW)=0x%x,   rwptr.bits.wptr(HW) = 0x%x ]---->Free_Q(SW_HW) = 0x%8x \n",__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.rptr,rwptr.bits.wptr,fq_rwptr.bits32 );
9196 +
9197 +           /* Receive descriptor is empty now */
9198 +#if 1
9199 +     if (status4 & 0x1)
9200 +                       {
9201 +                               do_again =1;
9202 +                               //writel(0x40400000, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_4_REG); //disable SWFQ empty interrupt
9203 +                               //toe_gmac_disable_interrupt(tp->irq);
9204 +                               tp->sw_fq_empty_cnt++;
9205 +                               //toe_gmac_disable_rx(dev);
9206 +                               writel(0x07960202, TOE_GMAC0_BASE+GMAC_CONFIG0);
9207 +                               writel(0x07960202, TOE_GMAC1_BASE+GMAC_CONFIG0);
9208 +                               //printk("\n%s ::  freeq int-----tp->sw_fq_empty_cnt  =%d---------====================----------------->\n",__func__,tp->sw_fq_empty_cnt);
9209 +                               //while ((fq_rwptr.bits.wptr >= (fq_rwptr.bits.rptr+256)) || (fq_rwptr.bits.wptr <= (fq_rwptr.bits.rptr+256)))
9210 +                               //{
9211 +                                       //gmac_write_reg(TOE_GLOBAL_BASE, GLOBAL_INTERRUPT_STATUS_4_REG, status4,
9212 +                                       //0x1);
9213 +                               //printk("\n%s::fq_rwptr.wrptr = %x =======> ===========>here \n", __func__,fq_rwptr.bits32);
9214 +                               //if ((status4 & 0x1) == 0)
9215 +                                       //break;
9216 +                                return 1;
9217 +                               //}
9218 +
9219 +                       }
9220 +#endif
9221 +        //toe_gmac_fill_free_q();
9222 +        netif_rx_complete(dev);
9223 +        // enable GMAC-0 rx interrupt
9224 +        // class-Q & TOE-Q are implemented in future
9225 +        //data32 = readl(TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
9226 +        //if (tp->port_id == 0)
9227 +               //data32 |= DEFAULT_Q0_INT_BIT;
9228 +        //else
9229 +               //data32 |= DEFAULT_Q1_INT_BIT;
9230 +        //writel(data32, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_ENABLE_1_REG);
9231 +               writel(0x3, TOE_GLOBAL_BASE+GLOBAL_INTERRUPT_ENABLE_1_REG);
9232 +               //printk("\n%s::netif_rx_complete-->  rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x ====---------=======>JKJKJKJKJK\n",
9233 +               //__func__,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
9234 +        writel(0x07960200, TOE_GMAC0_BASE+GMAC_CONFIG0);
9235 +               writel(0x07960200, TOE_GMAC1_BASE+GMAC_CONFIG0);
9236 +        return 0;
9237 +    }
9238 +    else
9239 +    {
9240 +        //printk("\n%s:: return 1 -->status4= 0x%x,rx_pkts_num =%d,   rwptr.bits.rptr=0x%x,   rwptr.bits.wptr = 0x%x  ======> \n", __func__,status4,rx_pkts_num,rwptr.bits.rptr,rwptr.bits.wptr);
9241 +        return 1;
9242 +    }
9243 +}
9244 +#endif
9245 +
9246 +/*----------------------------------------------------------------------
9247 +* gmac_tx_timeout
9248 +*----------------------------------------------------------------------*/
9249 +void gmac_tx_timeout(struct net_device *dev)
9250 +{
9251 +       GMAC_INFO_T                             *tp = (GMAC_INFO_T *)dev->priv;
9252 +
9253 +#ifdef CONFIG_SL351x_SYSCTL
9254 +       if (tp->operation && storlink_ctl.link[tp->port_id])
9255 +#else
9256 +       if (tp->operation)
9257 +#endif
9258 +       {
9259 +               netif_wake_queue(dev);
9260 +       }
9261 +}
9262 +
9263 +
9264 +
9265 +/*----------------------------------------------------------------------
9266 +* mac_set_rule_reg
9267 +*----------------------------------------------------------------------*/
9268 +int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2)
9269 +{
9270 +       int             total_key_dwords;
9271 +
9272 +       total_key_dwords = 1;
9273 +
9274 +       if (reg0 & MR_L2_BIT)
9275 +       {
9276 +               if (reg0 & MR_DA_BIT) total_key_dwords += 2;
9277 +               if (reg0 & MR_SA_BIT) total_key_dwords += 2;
9278 +               if ((reg0 & MR_DA_BIT) && ( reg0 & MR_SA_BIT)) total_key_dwords--;
9279 +               if (reg0 & (MR_PPPOE_BIT | MR_VLAN_BIT)) total_key_dwords++;
9280 +       }
9281 +       if (reg0 & MR_L3_BIT)
9282 +       {
9283 +               if (reg0 & (MR_IP_HDR_LEN_BIT | MR_TOS_TRAFFIC_BIT | MR_SPR_BITS))
9284 +                       total_key_dwords++;
9285 +               if (reg0 & MR_FLOW_LABLE_BIT) total_key_dwords++;
9286 +               if ((reg0 & MR_IP_VER_BIT) == 0) // IPv4
9287 +               {
9288 +                       if (reg1 & 0xff000000) total_key_dwords += 1;
9289 +                       if (reg1 & 0x00ff0000) total_key_dwords += 1;
9290 +               }
9291 +               else
9292 +               {
9293 +                       if (reg1 & 0xff000000) total_key_dwords += 4;
9294 +                       if (reg1 & 0x00ff0000) total_key_dwords += 4;
9295 +               }
9296 +       }
9297 +       if (reg0 & MR_L4_BIT)
9298 +       {
9299 +               if (reg1 & 0x0000f000) total_key_dwords += 1;
9300 +               if (reg1 & 0x00000f00) total_key_dwords += 1;
9301 +               if (reg1 & 0x000000f0) total_key_dwords += 1;
9302 +               if (reg1 & 0x0000000f) total_key_dwords += 1;
9303 +               if (reg2 & 0xf0000000) total_key_dwords += 1;
9304 +               if (reg2 & 0x0f000000) total_key_dwords += 1;
9305 +       }
9306 +       if (reg0 & MR_L7_BIT)
9307 +       {
9308 +               if (reg2 & 0x00f00000) total_key_dwords += 1;
9309 +               if (reg2 & 0x000f0000) total_key_dwords += 1;
9310 +               if (reg2 & 0x0000f000) total_key_dwords += 1;
9311 +               if (reg2 & 0x00000f00) total_key_dwords += 1;
9312 +               if (reg2 & 0x000000f0) total_key_dwords += 1;
9313 +               if (reg2 & 0x0000000f) total_key_dwords += 1;
9314 +       }
9315 +
9316 +       if (total_key_dwords > HASH_MAX_KEY_DWORD)
9317 +               return -1;
9318 +
9319 +       if (total_key_dwords == 0 && enabled)
9320 +               return -2;
9321 +
9322 +       mac_set_rule_enable_bit(mac, rule, 0);
9323 +       if (enabled)
9324 +       {
9325 +               mac_set_MRxCRx(mac, rule, 0, reg0);
9326 +               mac_set_MRxCRx(mac, rule, 1, reg1);
9327 +               mac_set_MRxCRx(mac, rule, 2, reg2);
9328 +               mac_set_rule_action(mac, rule, total_key_dwords);
9329 +               mac_set_rule_enable_bit(mac, rule, enabled);
9330 +       }
9331 +       else
9332 +       {
9333 +               mac_set_rule_action(mac, rule, 0);
9334 +       }
9335 +       return total_key_dwords;
9336 +}
9337 +
9338 +/*----------------------------------------------------------------------
9339 +* mac_get_rule_enable_bit
9340 +*----------------------------------------------------------------------*/
9341 +int mac_get_rule_enable_bit(int mac, int rule)
9342 +{
9343 +       switch (rule)
9344 +       {
9345 +               case 0: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) >> 15) & 1);
9346 +               case 1: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) >> 31) & 1);
9347 +               case 2: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) >> 15) & 1);
9348 +               case 3: return ((mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) >> 31) & 1);
9349 +               default: return 0;
9350 +       }
9351 +}
9352 +
9353 +/*----------------------------------------------------------------------
9354 +* mac_set_rule_enable_bit
9355 +*----------------------------------------------------------------------*/
9356 +void mac_set_rule_enable_bit(int mac, int rule, int data)
9357 +{
9358 +       u32 reg;
9359 +
9360 +       if (data & ~1)
9361 +               return;
9362 +
9363 +       switch (rule)
9364 +       {
9365 +               case 0:
9366 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(1<<15)) | (data << 15);
9367 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg);
9368 +                       break;
9369 +               case 1:
9370 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(1<<31)) | (data << 31);
9371 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg);
9372 +                       break;
9373 +               case 2:
9374 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(1<<15)) | (data << 15);
9375 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1, reg);
9376 +                       break;
9377 +               case 3:
9378 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(1<<31)) | (data << 31);
9379 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1, reg);
9380 +       }
9381 +}
9382 +
9383 +/*----------------------------------------------------------------------
9384 +* mac_set_rule_action
9385 +*----------------------------------------------------------------------*/
9386 +int mac_set_rule_action(int mac, int rule, int data)
9387 +{
9388 +       u32 reg;
9389 +
9390 +       if (data > 32)
9391 +               return -1;
9392 +
9393 +       if (data)
9394 +               data = (data << 6) | (data + HASH_ACTION_DWORDS);
9395 +       switch (rule)
9396 +       {
9397 +               case 0:
9398 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(0x7ff));
9399 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg | data);
9400 +                       break;
9401 +               case 1:
9402 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG0) & ~(0x7ff<<16));
9403 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG0, reg | (data << 16));
9404 +                       break;
9405 +               case 2:
9406 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(0x7ff));
9407 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1,  reg | data);
9408 +                       break;
9409 +               case 3:
9410 +                       reg = (mac_read_dma_reg(mac, GMAC_HASH_ENGINE_REG1) & ~(0x7ff<<16));
9411 +                       mac_write_dma_reg(mac, GMAC_HASH_ENGINE_REG1, reg | (data << 16));
9412 +                       break;
9413 +               default:
9414 +                       return -1;
9415 +       }
9416 +
9417 +       return 0;
9418 +}
9419 +/*----------------------------------------------------------------------
9420 +* mac_get_MRxCRx
9421 +*----------------------------------------------------------------------*/
9422 +int mac_get_MRxCRx(int mac, int rule, int ctrlreg)
9423 +{
9424 +       int reg;
9425 +
9426 +       switch (rule)
9427 +       {
9428 +               case 0: reg = GMAC_MR0CR0 + ctrlreg * 4; break;
9429 +               case 1: reg = GMAC_MR1CR0 + ctrlreg * 4; break;
9430 +               case 2: reg = GMAC_MR2CR0 + ctrlreg * 4; break;
9431 +               case 3: reg = GMAC_MR3CR0 + ctrlreg * 4; break;
9432 +               default: return 0;
9433 +       }
9434 +       return mac_read_dma_reg(mac, reg);
9435 +}
9436 +
9437 +/*----------------------------------------------------------------------
9438 +* mac_set_MRxCRx
9439 +*----------------------------------------------------------------------*/
9440 +void mac_set_MRxCRx(int mac, int rule, int ctrlreg, u32 data)
9441 +{
9442 +       int reg;
9443 +
9444 +       switch (rule)
9445 +       {
9446 +               case 0: reg = GMAC_MR0CR0 + ctrlreg * 4; break;
9447 +               case 1: reg = GMAC_MR1CR0 + ctrlreg * 4; break;
9448 +               case 2: reg = GMAC_MR2CR0 + ctrlreg * 4; break;
9449 +               case 3: reg = GMAC_MR3CR0 + ctrlreg * 4; break;
9450 +               default: return;
9451 +       }
9452 +       mac_write_dma_reg(mac, reg, data);
9453 +}
9454 +
9455 +/*----------------------------------------------------------------------
9456 +* mac_set_rule_priority
9457 +*----------------------------------------------------------------------*/
9458 +void mac_set_rule_priority(int mac, int p0, int p1, int p2, int p3)
9459 +{
9460 +       int                     i;
9461 +       GMAC_MRxCR0_T   reg[4];
9462 +
9463 +       for (i=0; i<4; i++)
9464 +               reg[i].bits32 = mac_get_MRxCRx(mac, i, 0);
9465 +
9466 +       reg[0].bits.priority = p0;
9467 +       reg[1].bits.priority = p1;
9468 +       reg[2].bits.priority = p2;
9469 +       reg[3].bits.priority = p3;
9470 +
9471 +       for (i=0; i<4; i++)
9472 +               mac_set_MRxCRx(mac, i, 0, reg[i].bits32);
9473 +}
9474 +
9475 +/*----------------------------------------------------------------------
9476 +* gmac_netdev_ioctl
9477 +*----------------------------------------------------------------------*/
9478 +static int gmac_netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
9479 +{
9480 +       int                             rc = 0;
9481 +    unsigned char              *hwa = rq->ifr_ifru.ifru_hwaddr.sa_data;
9482 +
9483 +#ifdef br_if_ioctl
9484 +    struct                             ethtool_cmd ecmd;       //br_if.c will call this ioctl
9485 +       GMAC_INFO_T             *tp = dev->priv;
9486 +#endif
9487 +
9488 +#ifdef         CONFIG_SL351x_NAT
9489 +       if (cmd == SIOCDEVPRIVATE)
9490 +               return sl351x_nat_ioctl(dev, rq, cmd);
9491 +#endif
9492 +
9493 +       switch (cmd) {
9494 +       case SIOCETHTOOL:
9495 +#ifdef br_if_ioctl     //br_if.c will call this ioctl
9496 +               if (!netif_running(dev))
9497 +               {
9498 +                       printk("Before changing the H/W address,please down the device.\n");
9499 +                       return -EINVAL;
9500 +               }
9501 +               memset((void *) &ecmd, 0, sizeof (ecmd));
9502 +                   ecmd.supported =
9503 +                       SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII |
9504 +                    SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
9505 +                    SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
9506 +                           ecmd.port = PORT_TP;
9507 +                   ecmd.transceiver = XCVR_EXTERNAL;
9508 +                   ecmd.phy_address = tp->phy_addr;
9509 +                   switch (tp->speed_status)
9510 +                   {
9511 +                   case GMAC_SPEED_10: ecmd.speed = SPEED_10; break;
9512 +                   case GMAC_SPEED_100: ecmd.speed = SPEED_100; break;
9513 +                   case GMAC_SPEED_1000: ecmd.speed = SPEED_1000; break;
9514 +                   default: ecmd.speed = SPEED_10; break;
9515 +                  }
9516 +                   ecmd.duplex = tp->full_duplex_status ? DUPLEX_FULL : DUPLEX_HALF;
9517 +                   ecmd.advertising = ADVERTISED_TP;
9518 +                   ecmd.advertising |= ADVERTISED_Autoneg;
9519 +                   ecmd.autoneg = AUTONEG_ENABLE;
9520 +                    if (copy_to_user(rq->ifr_data, &ecmd, sizeof (ecmd)))
9521 +                       return -EFAULT;
9522 +#endif
9523 +
9524 +        break;
9525 +
9526 +    case SIOCSIFHWADDR:
9527 +               if (!netif_running(dev))
9528 +               {
9529 +                       printk("Before changing the H/W address,please down the device.\n");
9530 +                       return -EINVAL;
9531 +               }
9532 +        gmac_set_mac_address(dev,hwa);
9533 +        break;
9534 +
9535 +       case SIOCGMIIPHY:       /* Get the address of the PHY in use. */
9536 +        break;
9537 +
9538 +       case SIOCGMIIREG:       /* Read the specified MII register. */
9539 +               break;
9540 +
9541 +       case SIOCSMIIREG:       /* Write the specified MII register */
9542 +               break;
9543 +
9544 +       default:
9545 +               rc = -EOPNOTSUPP;
9546 +               break;
9547 +       }
9548 +
9549 +       return rc;
9550 +}
9551 +
9552 +#ifdef SL351x_GMAC_WORKAROUND
9553 +
9554 +#define GMAC_TX_STATE_OFFSET   0x60
9555 +#define GMAC_RX_STATE_OFFSET   0x64
9556 +#define GMAC_POLL_HANGED_NUM   200
9557 +#define GMAC_RX_HANGED_STATE   0x4b2000
9558 +#define GMAC_RX_HANGED_MASK            0xdff000
9559 +#define GMAC_TX_HANGED_STATE   0x34012
9560 +#define GMAC_TX_HANGED_MASK            0xfffff
9561 +#define TOE_GLOBAL_REG_SIZE            (0x78/sizeof(u32))
9562 +#define TOE_DMA_REG_SIZE               (0xd0/sizeof(u32))
9563 +#define TOE_GMAC_REG_SIZE              (0x30/sizeof(u32))
9564 +#define GMAC0_RX_HANG_BIT              (1 << 0)
9565 +#define GMAC0_TX_HANG_BIT              (1 << 1)
9566 +#define GMAC1_RX_HANG_BIT              (1 << 2)
9567 +#define GMAC1_TX_HANG_BIT              (1 << 3)
9568 +
9569 +int            gmac_in_do_workaround;
9570 +#if 0
9571 +int            debug_cnt, poll_max_cnt;
9572 +#endif
9573 +u32            gmac_workaround_cnt[4];
9574 +u32            toe_global_reg[TOE_GLOBAL_REG_SIZE];
9575 +u32            toe_dma_reg[GMAC_NUM][TOE_DMA_REG_SIZE];
9576 +u32            toe_gmac_reg[GMAC_NUM][TOE_GMAC_REG_SIZE];
9577 +u32            gmac_short_frame_workaround_cnt[2];
9578 +
9579 +static void sl351x_gmac_release_buffers(void);
9580 +static void sl351x_gmac_release_swtx_q(void);
9581 +static void sl351x_gmac_release_rx_q(void);
9582 +#ifdef _TOEQ_CLASSQ_READY_
9583 +static void sl351x_gmac_release_class_q(void);
9584 +static void sl351x_gmac_release_toe_q(void);
9585 +static void sl351x_gmac_release_intr_q(void);
9586 +#endif
9587 +static void sl351x_gmac_release_sw_free_q(void);
9588 +static void sl351x_gmac_release_hw_free_q(void);
9589 +#ifdef CONFIG_SL351x_NAT
9590 +static int get_free_desc_cnt(unsigned long rwptr, int total);
9591 +static void sl351x_gmac_release_hwtx_q(void);
9592 +u32     sl351x_nat_workaround_cnt;
9593 +#endif
9594 +void sl351x_gmac_save_reg(void);
9595 +void sl351x_gmac_restore_reg(void);
9596 +
9597 +
9598 +/*----------------------------------------------------------------------
9599 +*      sl351x_poll_gmac_hanged_status
9600 +*      - Called by timer routine, period 10ms
9601 +*      - If (state != 0 && state == prev state && )
9602 +*----------------------------------------------------------------------*/
9603 +void sl351x_poll_gmac_hanged_status(u32 data)
9604 +{
9605 +       int                     i;
9606 +       u32                     state;
9607 +       TOE_INFO_T              *toe;
9608 +       GMAC_INFO_T             *tp;
9609 +       u32                             hanged_state;
9610 +       // int                          old_operation[GMAC_NUM];
9611 +#ifdef CONFIG_SL351x_NAT
9612 +       u32                             hw_free_cnt;
9613 +#endif
9614 +
9615 +       if (gmac_in_do_workaround)
9616 +               return;
9617 +
9618 +       gmac_in_do_workaround = 1;
9619 +
9620 +       toe = (TOE_INFO_T *)&toe_private_data;
9621 +       hanged_state = 0;
9622 +
9623 +#ifdef SL351x_TEST_WORKAROUND
9624 +       if (toe->gmac[0].operation || toe->gmac[1].operation)
9625 +       {
9626 +               debug_cnt++;
9627 +               if (debug_cnt == (30 * HZ))
9628 +               {
9629 +                       debug_cnt = 0;
9630 +                       hanged_state = GMAC0_RX_HANG_BIT;
9631 +                       goto do_workaround;
9632 +               }
9633 +       }
9634 +#endif
9635 +       if (toe->gmac[0].operation)
9636 +               hanged_state |= GMAC0_RX_HANG_BIT | GMAC0_TX_HANG_BIT;
9637 +
9638 +#if (GMAC_NUM > 1)
9639 +       if (toe->gmac[1].operation)
9640 +               hanged_state |= GMAC1_RX_HANG_BIT | GMAC1_TX_HANG_BIT;
9641 +#endif
9642 +
9643 +       for (i=0; i<GMAC_POLL_HANGED_NUM; i++)
9644 +       {
9645 +               if (hanged_state & GMAC0_RX_HANG_BIT)
9646 +               {
9647 +                       state = readl(TOE_GMAC0_BASE + GMAC_RX_STATE_OFFSET) & GMAC_RX_HANGED_MASK;
9648 +                       if (state != GMAC_RX_HANGED_STATE)
9649 +                               hanged_state &= ~GMAC0_RX_HANG_BIT;
9650 +               }
9651 +               if (hanged_state & GMAC0_TX_HANG_BIT)
9652 +               {
9653 +                       state = readl(TOE_GMAC0_BASE + GMAC_TX_STATE_OFFSET) & GMAC_TX_HANGED_MASK;
9654 +                       if (state != GMAC_TX_HANGED_STATE)
9655 +                               hanged_state &= ~GMAC0_TX_HANG_BIT;
9656 +               }
9657 +#if (GMAC_NUM > 1)
9658 +               if (hanged_state & GMAC1_RX_HANG_BIT)
9659 +               {
9660 +                       state = readl(TOE_GMAC1_BASE + GMAC_RX_STATE_OFFSET) & GMAC_RX_HANGED_MASK;
9661 +                       if (state != GMAC_RX_HANGED_STATE)
9662 +                               hanged_state &= ~GMAC1_RX_HANG_BIT;
9663 +               }
9664 +               if (hanged_state & GMAC1_TX_HANG_BIT)
9665 +               {
9666 +                       state = readl(TOE_GMAC1_BASE + GMAC_TX_STATE_OFFSET) & GMAC_TX_HANGED_MASK;
9667 +                       if (state != GMAC_TX_HANGED_STATE)
9668 +                               hanged_state &= ~GMAC1_TX_HANG_BIT;
9669 +               }
9670 +#endif
9671 +               if (!hanged_state)
9672 +               {
9673 +#if 0
9674 +                       if (i < poll_max_cnt)
9675 +                               poll_max_cnt = i;
9676 +#endif
9677 +                       if (toe->gmac[0].short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
9678 +                       {
9679 +                               gmac_short_frame_workaround_cnt[0]++;
9680 +                               toe->gmac[0].short_frames_cnt = 0;
9681 +                               goto do_workaround;
9682 +                       }
9683 +#if (GMAC_NUM > 1)
9684 +                       if (toe->gmac[1].short_frames_cnt >= GMAC_SHORT_FRAME_THRESHOLD)
9685 +                       {
9686 +                               gmac_short_frame_workaround_cnt[1]++;
9687 +                               toe->gmac[1].short_frames_cnt = 0;
9688 +                               goto do_workaround;
9689 +                       }
9690 +#endif
9691 +
9692 +#ifdef CONFIG_SL351x_NAT
9693 +                       hw_free_cnt = readl(TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
9694 +                       hw_free_cnt = get_free_desc_cnt(hw_free_cnt, TOE_HW_FREEQ_DESC_NUM);
9695 +#ifdef NAT_WORKAROUND_BY_RESET_GMAC
9696 +                       if (readl(TOE_GLOBAL_BASE + 0x4084) && (hw_free_cnt <= PAUSE_SET_HW_FREEQ))
9697 +                       {
9698 +                               sl351x_nat_workaround_cnt++;
9699 +                               goto do_workaround;
9700 +                       }
9701 +#else
9702 +                       if (readl(TOE_GLOBAL_BASE + 0x4084) && (hw_free_cnt <= (PAUSE_SET_HW_FREEQ*2)))
9703 +                       {
9704 +                               sl351x_nat_workaround_cnt++;
9705 +                               sl351x_nat_workaround_handler();
9706 +                       }
9707 +#endif
9708 +#endif
9709 +                       gmac_in_do_workaround = 0;
9710 +                       add_timer(&gmac_workround_timer_obj);
9711 +                       return;
9712 +               }
9713 +       }
9714 +
9715 +do_workaround:
9716 +
9717 +       gmac_initialized = 0;
9718 +       if (hanged_state)
9719 +       {
9720 +               if (hanged_state & GMAC0_RX_HANG_BIT) gmac_workaround_cnt[0]++;
9721 +               if (hanged_state & GMAC0_TX_HANG_BIT) gmac_workaround_cnt[1]++;
9722 +               if (hanged_state & GMAC1_RX_HANG_BIT) gmac_workaround_cnt[2]++;
9723 +               if (hanged_state & GMAC1_TX_HANG_BIT) gmac_workaround_cnt[3]++;
9724 +       }
9725 +
9726 +       for (i=0; i<GMAC_NUM; i++)
9727 +       {
9728 +               tp=(GMAC_INFO_T *)&toe->gmac[i];
9729 +               // old_operation[i] = tp->operation;
9730 +               if (tp->operation)
9731 +               {
9732 +                       netif_stop_queue(tp->dev);
9733 +                       clear_bit(__LINK_STATE_START, &tp->dev->state);
9734 +                       toe_gmac_disable_interrupt(tp->irq);
9735 +                       toe_gmac_disable_tx_rx(tp->dev);
9736 +                       toe_gmac_hw_stop(tp->dev);
9737 +               }
9738 +       }
9739 +
9740 +       // clear all status bits
9741 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_0_REG);
9742 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_1_REG);
9743 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_2_REG);
9744 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_3_REG);
9745 +       writel(0xffffffff, TOE_GLOBAL_BASE + GLOBAL_INTERRUPT_STATUS_4_REG);
9746 +
9747 +#if 0
9748 +       if ((hanged_state & GMAC0_RX_HANG_BIT) &&
9749 +               (readl(TOE_GMAC0_DMA_BASE + 0xdc) & 0xf0))
9750 +       {
9751 +               struct sk_buff *skb;
9752 +               unsigned int buf;
9753 +               buf = readl(TOE_GMAC0_DMA_BASE + 0x68) & ~3;
9754 +#ifdef CONFIG_SL351x_NAT
9755 +               if (buf < toe->hwfq_buf_base_dma || buf > toe->hwfq_buf_end_dma)
9756 +#endif
9757 +               {
9758 +                       skb = (struct sk_buff *)(REG32(buf - SKB_RESERVE_BYTES));
9759 +                       printk("GMAC-0 free a loss SKB 0x%x\n", (u32)skb);
9760 +                       dev_kfree_skb(skb);
9761 +               }
9762 +       }
9763 +       if ((hanged_state & GMAC1_RX_HANG_BIT)  &&
9764 +               (readl(TOE_GMAC1_DMA_BASE + 0xdc) & 0xf0))
9765 +       {
9766 +               struct sk_buff *skb;
9767 +               unsigned int buf;
9768 +               buf = readl(TOE_GMAC1_DMA_BASE + 0x68) & ~3;
9769 +#ifdef CONFIG_SL351x_NAT
9770 +               if (buf < toe->hwfq_buf_base_dma || buf > toe->hwfq_buf_end_dma)
9771 +#endif
9772 +               {
9773 +                       skb = (struct sk_buff *)(REG32(buf - SKB_RESERVE_BYTES));
9774 +                       printk("GMAC-1 free a loss SKB 0x%x\n", (u32)skb);
9775 +                       dev_kfree_skb(skb);
9776 +               }
9777 +       }
9778 +#endif
9779 +
9780 +       sl351x_gmac_release_buffers();
9781 +       sl351x_gmac_save_reg();
9782 +       toe_gmac_sw_reset();
9783 +       sl351x_gmac_restore_reg();
9784 +
9785 +       if (toe->gmac[0].default_qhdr->word1.bits32)
9786 +       {
9787 +               // printk("===> toe->gmac[0].default_qhdr->word1 = 0x%x\n", toe->gmac[0].default_qhdr->word1);
9788 +               sl351x_gmac_release_rx_q();
9789 +               writel(0, &toe->gmac[0].default_qhdr->word1);
9790 +       }
9791 +       if (toe->gmac[1].default_qhdr->word1.bits32)
9792 +       {
9793 +               // printk("===> toe->gmac[1].default_qhdr->word1 = 0x%x\n", toe->gmac[1].default_qhdr->word1);
9794 +               sl351x_gmac_release_rx_q();
9795 +               writel(0, &toe->gmac[1].default_qhdr->word1);
9796 +       }
9797 +
9798 +       gmac_initialized = 1;
9799 +
9800 +#ifdef         CONFIG_SL351x_NAT
9801 +       writel(0, TOE_GLOBAL_BASE + 0x4084);
9802 +#endif
9803 +
9804 +       for (i=0; i<GMAC_NUM; i++)
9805 +       {
9806 +               tp=(GMAC_INFO_T *)&toe->gmac[i];
9807 +               if (tp->operation)
9808 +               {
9809 +                       toe_gmac_enable_interrupt(tp->irq);
9810 +                       toe_gmac_hw_start(tp->dev);
9811 +                       toe_gmac_enable_tx_rx(tp->dev);
9812 +                       netif_wake_queue(tp->dev);
9813 +                       set_bit(__LINK_STATE_START, &tp->dev->state);
9814 +               }
9815 +       }
9816 +
9817 +       gmac_in_do_workaround = 0;
9818 +       add_timer(&gmac_workround_timer_obj);
9819 +}
9820 +
9821 +/*----------------------------------------------------------------------
9822 +*      get_free_desc_cnt
9823 +*----------------------------------------------------------------------*/
9824 +#ifdef CONFIG_SL351x_NAT
9825 +static int get_free_desc_cnt(unsigned long rwptr, int total)
9826 +{
9827 +       unsigned short wptr = rwptr & 0xffff;
9828 +       unsigned short rptr = rwptr >> 16;
9829 +
9830 +       if (wptr >= rptr)
9831 +               return (total - wptr + rptr);
9832 +       else
9833 +               return (rptr - wptr);
9834 +}
9835 +#endif
9836 +/*----------------------------------------------------------------------
9837 +*      sl351x_gmac_release_buffers
9838 +*----------------------------------------------------------------------*/
9839 +static void sl351x_gmac_release_buffers(void)
9840 +{
9841 +       // Free buffers & Descriptors in all SW Tx Queues
9842 +       sl351x_gmac_release_swtx_q();
9843 +
9844 +       // Free buffers in Default Rx Queues
9845 +       sl351x_gmac_release_rx_q();
9846 +
9847 +#ifdef _TOEQ_CLASSQ_READY_
9848 +       // Free buffers in Classification Queues
9849 +       sl351x_gmac_release_class_q();
9850 +
9851 +       // Free buffers in TOE Queues
9852 +       sl351x_gmac_release_toe_q();
9853 +
9854 +       // Free buffers in Interrupt Queues
9855 +       sl351x_gmac_release_intr_q();
9856 +#endif
9857 +
9858 +       // Free buffers & descriptors in SW free queue
9859 +       sl351x_gmac_release_sw_free_q();
9860 +
9861 +       // Free buffers & descriptors in HW free queue
9862 +       sl351x_gmac_release_hw_free_q();
9863 +
9864 +#ifdef CONFIG_SL351x_NAT
9865 +       // Free buffers & descriptors in HW free queue
9866 +       sl351x_gmac_release_hwtx_q();
9867 +#endif
9868 +}
9869 +/*----------------------------------------------------------------------
9870 +*      sl351x_gmac_release_swtx_q
9871 +*----------------------------------------------------------------------*/
9872 +static void sl351x_gmac_release_swtx_q(void)
9873 +{
9874 +       int                             i, j;
9875 +       GMAC_TXDESC_T   *curr_desc;
9876 +       unsigned int    desc_count;
9877 +       TOE_INFO_T              *toe;
9878 +       GMAC_INFO_T             *tp;
9879 +       GMAC_SWTXQ_T    *swtxq;
9880 +       DMA_RWPTR_T             rwptr;
9881 +
9882 +       toe = (TOE_INFO_T *)&toe_private_data;
9883 +       tp = (GMAC_INFO_T *)&toe->gmac[0];
9884 +       for (i=0; i<GMAC_NUM; i++, tp++)
9885 +       {
9886 +               if (!tp->existed) continue;
9887 +               swtxq = (GMAC_SWTXQ_T *)&tp->swtxq[0];
9888 +               for (j=0; j<TOE_SW_TXQ_NUM; j++, swtxq++)
9889 +               {
9890 +                       for (;;)
9891 +                       {
9892 +                               rwptr.bits32 = readl(swtxq->rwptr_reg);
9893 +                               if (rwptr.bits.rptr == swtxq->finished_idx)
9894 +                               break;
9895 +                               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
9896 +                               // if (curr_desc->word0.bits.status_tx_ok)
9897 +                               {
9898 +                                       desc_count = curr_desc->word0.bits.desc_count;
9899 +                                       while (--desc_count)
9900 +                                       {
9901 +                                               curr_desc->word0.bits.status_tx_ok = 0;
9902 +                                               swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
9903 +                                               curr_desc = (GMAC_TXDESC_T *)swtxq->desc_base + swtxq->finished_idx;
9904 +                                       }
9905 +
9906 +                                       curr_desc->word0.bits.status_tx_ok = 0;
9907 +                                       if (swtxq->tx_skb[swtxq->finished_idx])
9908 +                                       {
9909 +                                               dev_kfree_skb_irq(swtxq->tx_skb[swtxq->finished_idx]);
9910 +                                               swtxq->tx_skb[swtxq->finished_idx] = NULL;
9911 +                                       }
9912 +                               }
9913 +                               swtxq->finished_idx = RWPTR_ADVANCE_ONE(swtxq->finished_idx, swtxq->total_desc_num);
9914 +                       }
9915 +                       writel(0, swtxq->rwptr_reg);
9916 +                       swtxq->finished_idx = 0;
9917 +               }
9918 +       }
9919 +
9920 +}
9921 +/*----------------------------------------------------------------------
9922 +*      sl351x_gmac_release_rx_q
9923 +*----------------------------------------------------------------------*/
9924 +static void sl351x_gmac_release_rx_q(void)
9925 +{
9926 +       int                             i;
9927 +       TOE_INFO_T              *toe;
9928 +       GMAC_INFO_T             *tp;
9929 +       DMA_RWPTR_T             rwptr;
9930 +       volatile GMAC_RXDESC_T  *curr_desc;
9931 +       struct sk_buff                  *skb;
9932 +
9933 +       toe = (TOE_INFO_T *)&toe_private_data;
9934 +       tp = (GMAC_INFO_T *)&toe->gmac[0];
9935 +       for (i=0; i<GMAC_NUM; i++, tp++)
9936 +       {
9937 +               if (!tp->existed) continue;
9938 +               rwptr.bits32 = readl(&tp->default_qhdr->word1);
9939 +               while (rwptr.bits.rptr != rwptr.bits.wptr)
9940 +               {
9941 +                       curr_desc = (GMAC_RXDESC_T *)tp->default_desc_base + rwptr.bits.rptr;
9942 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
9943 +                       dev_kfree_skb_irq(skb);
9944 +                       rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, tp->default_desc_num);
9945 +                       SET_RPTR(&tp->default_qhdr->word1, rwptr.bits.rptr);
9946 +                       rwptr.bits32 = readl(&tp->default_qhdr->word1);
9947 +               }  // while
9948 +               writel(0, &tp->default_qhdr->word1);
9949 +               tp->rx_rwptr.bits32 = 0;
9950 +       } // for
9951 +
9952 +}
9953 +/*----------------------------------------------------------------------
9954 +*      sl351x_gmac_release_class_q
9955 +*----------------------------------------------------------------------*/
9956 +#ifdef _TOEQ_CLASSQ_READY_
9957 +static void sl351x_gmac_release_class_q(void)
9958 +{
9959 +       int                             i;
9960 +       TOE_INFO_T              *toe;
9961 +       CLASSQ_INFO_T   *classq;
9962 +       DMA_RWPTR_T             rwptr;
9963 +       volatile GMAC_RXDESC_T  *curr_desc;
9964 +       struct sk_buff                  *skb;
9965 +
9966 +       toe = (TOE_INFO_T *)&toe_private_data;
9967 +       classq = (CLASSQ_INFO_T *)&toe->classq[0];
9968 +       for (i=0; i<TOE_CLASS_QUEUE_NUM; i++, classq++)
9969 +       {
9970 +               rwptr.bits32 = readl(&classq->qhdr->word1);
9971 +               while (rwptr.bits.rptr != rwptr.bits.wptr)
9972 +               {
9973 +                       curr_desc = (GMAC_RXDESC_T *)classq->desc_base + rwptr.bits.rptr;
9974 +                       skb = (struct sk_buff *)(REG32(__va(curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
9975 +                       dev_kfree_skb_irq(skb);
9976 +                       rwptr.bits.rptr = RWPTR_ADVANCE_ONE(rwptr.bits.rptr, classq->desc_num);
9977 +                       SET_RPTR(&classq->qhdr->word1, rwptr.bits.rptr);
9978 +                       rwptr.bits32 = readl(&classq->qhdr->word1);
9979 +               }  // while
9980 +               writel(0, &classq->qhdr->word1);
9981 +               classq->rwptr.bits32 = 0;
9982 +       } // for
9983 +
9984 +}
9985 +#endif
9986 +/*----------------------------------------------------------------------
9987 +*      sl351x_gmac_release_toe_q
9988 +*----------------------------------------------------------------------*/
9989 +#ifdef _TOEQ_CLASSQ_READY_
9990 +static void sl351x_gmac_release_toe_q(void)
9991 +{
9992 +       int                             i;
9993 +       TOE_INFO_T              *toe;
9994 +       TOEQ_INFO_T             *toeq_info;
9995 +       TOE_QHDR_T              *toe_qhdr;
9996 +       DMA_RWPTR_T             rwptr;
9997 +       volatile GMAC_RXDESC_T  *curr_desc;
9998 +       unsigned int    rptr, wptr;
9999 +       GMAC_RXDESC_T   *toe_curr_desc;
10000 +       struct sk_buff                  *skb;
10001 +
10002 +       toe = (TOE_INFO_T *)&toe_private_data;
10003 +       toe_qhdr = (TOE_QHDR_T *)TOE_TOE_QUE_HDR_BASE;
10004 +       for (i=0; i<TOE_TOE_QUEUE_NUM; i++, toe_qhdr++)
10005 +       {
10006 +               toeq_info = (TOEQ_INFO_T *)&toe->toeq[i];
10007 +               wptr = toe_qhdr->word1.bits.wptr;
10008 +               rptr = toe_qhdr->word1.bits.rptr;
10009 +               while (rptr != wptr)
10010 +               {
10011 +                       toe_curr_desc = (GMAC_RXDESC_T *)toeq_info->desc_base + rptr;
10012 +                       skb = (struct sk_buff *)(REG32(__va(toe_curr_desc->word2.buf_adr) - SKB_RESERVE_BYTES));
10013 +                       dev_kfree_skb_irq(skb);
10014 +                       rptr = RWPTR_ADVANCE_ONE(rptr, toeq_info->desc_num);
10015 +                       SET_RPTR(&toe_qhdr->word1.bits32, rptr);
10016 +                       wptr = toe_qhdr->word1.bits.wptr;
10017 +                       rptr = toe_qhdr->word1.bits.rptr;
10018 +               }
10019 +               toe_qhdr->word1.bits32 = 0;
10020 +               toeq_info->rwptr.bits32 = 0;
10021 +       }
10022 +}
10023 +#endif
10024 +/*----------------------------------------------------------------------
10025 +*      sl351x_gmac_release_intr_q
10026 +*----------------------------------------------------------------------*/
10027 +#ifdef _TOEQ_CLASSQ_READY_
10028 +static void sl351x_gmac_release_intr_q(void)
10029 +{
10030 +}
10031 +#endif
10032 +/*----------------------------------------------------------------------
10033 +*      sl351x_gmac_release_sw_free_q
10034 +*----------------------------------------------------------------------*/
10035 +static void sl351x_gmac_release_sw_free_q(void)
10036 +{
10037 +       TOE_INFO_T                              *toe;
10038 +       volatile DMA_RWPTR_T    fq_rwptr;
10039 +       volatile GMAC_RXDESC_T  *fq_desc;
10040 +
10041 +       toe = (TOE_INFO_T *)&toe_private_data;
10042 +       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
10043 +
10044 +       while ((unsigned short)RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM) != fq_rwptr.bits.rptr)
10045 +       {
10046 +               struct sk_buff *skb;
10047 +               if ((skb = dev_alloc_skb(SW_RX_BUF_SIZE))==NULL)  /* allocate socket buffer */
10048 +               {
10049 +                       printk("%s::skb buffer allocation fail !\n",__func__); while(1);
10050 +               }
10051 +               // *(unsigned int *)(skb->data) = (unsigned int)skb;
10052 +               REG32(skb->data) = (unsigned long)skb;
10053 +               skb_reserve(skb, SKB_RESERVE_BYTES);
10054 +
10055 +               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
10056 +               fq_desc = (volatile GMAC_RXDESC_T *)toe->swfq_desc_base + fq_rwptr.bits.wptr;
10057 +               fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
10058 +               SET_WPTR(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
10059 +               fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
10060 +       }
10061 +
10062 +       toe->fq_rx_rwptr.bits.wptr = TOE_SW_FREEQ_DESC_NUM - 1;
10063 +       toe->fq_rx_rwptr.bits.rptr = 0;
10064 +       writel(toe->fq_rx_rwptr.bits32, TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
10065 +
10066 +}
10067 +/*----------------------------------------------------------------------
10068 +*      sl351x_gmac_release_hw_free_q
10069 +*----------------------------------------------------------------------*/
10070 +static void sl351x_gmac_release_hw_free_q(void)
10071 +{
10072 +       DMA_RWPTR_T                     rwptr_reg;
10073 +
10074 +#ifdef CONFIG_SL351x_NAT
10075 +       int                                     i;
10076 +       TOE_INFO_T                      *toe;
10077 +       GMAC_RXDESC_T           *desc_ptr;
10078 +       unsigned int            buf_ptr;
10079 +
10080 +       toe = (TOE_INFO_T *)&toe_private_data;
10081 +       desc_ptr = (GMAC_RXDESC_T *)toe->hwfq_desc_base;
10082 +       buf_ptr = (unsigned int)toe->hwfq_buf_base_dma;
10083 +       for (i=0; i<TOE_HW_FREEQ_DESC_NUM; i++)
10084 +       {
10085 +               desc_ptr->word0.bits.buffer_size = HW_RX_BUF_SIZE;
10086 +               desc_ptr->word1.bits.sw_id = i;
10087 +               desc_ptr->word2.buf_adr = (unsigned int)buf_ptr;
10088 +               desc_ptr++;
10089 +               buf_ptr += HW_RX_BUF_SIZE;
10090 +       }
10091 +#endif
10092 +       rwptr_reg.bits.wptr = TOE_HW_FREEQ_DESC_NUM - 1;
10093 +       rwptr_reg.bits.rptr = 0;
10094 +       writel(rwptr_reg.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
10095 +}
10096 +
10097 +/*----------------------------------------------------------------------
10098 +*      sl351x_gmac_release_hw_free_q
10099 +*----------------------------------------------------------------------*/
10100 +#ifdef CONFIG_SL351x_NAT
10101 +static void sl351x_gmac_release_hwtx_q(void)
10102 +{
10103 +       int                             i;
10104 +       unsigned int    rwptr_addr;
10105 +
10106 +       rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
10107 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
10108 +       {
10109 +               writel(0, rwptr_addr);
10110 +               rwptr_addr+=4;
10111 +       }
10112 +       rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
10113 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
10114 +       {
10115 +               writel(0, rwptr_addr);
10116 +               rwptr_addr+=4;
10117 +       }
10118 +}
10119 +#endif
10120 +
10121 +/*----------------------------------------------------------------------
10122 +*      sl351x_gmac_save_reg
10123 +*----------------------------------------------------------------------*/
10124 +void sl351x_gmac_save_reg(void)
10125 +{
10126 +       int     i;
10127 +       volatile u32    *destp;
10128 +       unsigned int    srce_addr;
10129 +
10130 +       srce_addr = TOE_GLOBAL_BASE;
10131 +       destp = (volatile u32 *)toe_global_reg;
10132 +       for (i=0; i<TOE_GLOBAL_REG_SIZE; i++, destp++, srce_addr+=4)
10133 +               *destp = readl(srce_addr);
10134 +
10135 +       srce_addr = TOE_GMAC0_DMA_BASE;
10136 +       destp = (volatile u32 *)&toe_dma_reg[0][0];
10137 +       for (i=0; i<TOE_DMA_REG_SIZE; i++, destp++, srce_addr+=4)
10138 +       {
10139 +               if (srce_addr ==  (TOE_GMAC0_DMA_BASE+0x38))
10140 +                       srce_addr = (TOE_GMAC0_DMA_BASE+0x50);
10141 +               if (srce_addr ==  (TOE_GMAC0_DMA_BASE+0x58))
10142 +                       srce_addr = (TOE_GMAC0_DMA_BASE+0x70);
10143 +
10144 +               *destp = readl(srce_addr);
10145 +       }
10146 +       srce_addr = TOE_GMAC1_DMA_BASE;
10147 +       destp = (volatile u32 *)&toe_dma_reg[1][0];
10148 +       for (i=0; i<TOE_DMA_REG_SIZE; i++, destp++, srce_addr+=4)
10149 +       {
10150 +               if (srce_addr ==  (TOE_GMAC0_DMA_BASE+0x38))
10151 +                       srce_addr = (TOE_GMAC0_DMA_BASE+0x50);
10152 +               if (srce_addr ==  (TOE_GMAC0_DMA_BASE+0x58))
10153 +                       srce_addr = (TOE_GMAC0_DMA_BASE+0x70);
10154 +
10155 +               *destp = readl(srce_addr);
10156 +       }
10157 +
10158 +       srce_addr = TOE_GMAC0_BASE;
10159 +       destp = (volatile u32 *)&toe_gmac_reg[0][0];
10160 +       for (i=0; i<TOE_GMAC_REG_SIZE; i++, destp++, srce_addr+=4)
10161 +               *destp = readl(srce_addr);
10162 +
10163 +       srce_addr = TOE_GMAC1_BASE;
10164 +       destp = (volatile u32 *)&toe_gmac_reg[1][0];
10165 +       for (i=0; i<TOE_GMAC_REG_SIZE; i++, destp++, srce_addr+=4)
10166 +               *destp = readl(srce_addr);
10167 +}
10168 +
10169 +/*----------------------------------------------------------------------
10170 +*      sl351x_gmac_restore_reg
10171 +*----------------------------------------------------------------------*/
10172 +void sl351x_gmac_restore_reg(void)
10173 +{
10174 +       int     i;
10175 +       volatile u32    *srcep;
10176 +       unsigned int    dest_addr;
10177 +
10178 +       srcep = (volatile u32 *)&toe_dma_reg[0][0];
10179 +       dest_addr = TOE_GMAC0_DMA_BASE;
10180 +       for (i=0; i<TOE_DMA_REG_SIZE; i++, dest_addr+=4, srcep++)
10181 +       {
10182 +               if (dest_addr == (TOE_GMAC0_DMA_BASE+0x38))
10183 +                       dest_addr = (TOE_GMAC0_DMA_BASE+0x50);
10184 +               if (dest_addr == (TOE_GMAC0_DMA_BASE+0x58))
10185 +                       dest_addr = (TOE_GMAC0_DMA_BASE+0x70);
10186 +
10187 +               writel(*srcep, dest_addr);
10188 +               // gmac_write_reg(dest_addr, 0, *srcep, 0xffffffff);
10189 +       }
10190 +       srcep = (volatile u32 *)&toe_dma_reg[1][0];
10191 +       dest_addr = TOE_GMAC1_DMA_BASE;
10192 +       for (i=0; i<TOE_DMA_REG_SIZE; i++, dest_addr+=4, srcep++)
10193 +       {
10194 +               if (dest_addr == (TOE_GMAC0_DMA_BASE+0x38))
10195 +                       dest_addr = (TOE_GMAC0_DMA_BASE+0x50);
10196 +               if (dest_addr == (TOE_GMAC0_DMA_BASE+0x58))
10197 +                       dest_addr = (TOE_GMAC0_DMA_BASE+0x70);
10198 +
10199 +               writel(*srcep, dest_addr);
10200 +               // gmac_write_reg(dest_addr, 0, *srcep, 0xffffffff);
10201 +       }
10202 +
10203 +       srcep = (volatile u32 *)&toe_gmac_reg[0][0];
10204 +       dest_addr = TOE_GMAC0_BASE;
10205 +       for (i=0; i<TOE_GMAC_REG_SIZE; i++, dest_addr+=4, srcep++)
10206 +               writel(*srcep, dest_addr);
10207 +
10208 +       srcep = (volatile u32 *)&toe_gmac_reg[1][0];
10209 +       dest_addr = TOE_GMAC1_BASE;
10210 +       for (i=0; i<TOE_GMAC_REG_SIZE; i++, dest_addr+=4, srcep++)
10211 +               writel(*srcep, dest_addr);
10212 +
10213 +       srcep = (volatile u32 *)toe_global_reg;
10214 +       dest_addr = TOE_GLOBAL_BASE;
10215 +       for (i=0; i<TOE_GLOBAL_REG_SIZE; i++, dest_addr+=4, srcep++)
10216 +               writel(*srcep, dest_addr);
10217 +
10218 +}
10219 +
10220 +#ifdef CONFIG_SL351x_NAT
10221 +/*----------------------------------------------------------------------
10222 +*      sl351x_nat_workaround_init
10223 +*----------------------------------------------------------------------*/
10224 +#define NAT_WORAROUND_DESC_POWER       (6)
10225 +#define NAT_WORAROUND_DESC_NUM         (2 << NAT_WORAROUND_DESC_POWER)
10226 +dma_addr_t sl351x_nat_workaround_desc_dma;
10227 +void sl351x_nat_workaround_init(void)
10228 +{
10229 +       unsigned int    desc_buf;
10230 +
10231 +       desc_buf = (unsigned int)DMA_MALLOC((NAT_WORAROUND_DESC_NUM * sizeof(GMAC_RXDESC_T)),
10232 +                                               (dma_addr_t *)&sl351x_nat_workaround_desc_dma) ;
10233 +       memset((void *)desc_buf, 0, NAT_WORAROUND_DESC_NUM * sizeof(GMAC_RXDESC_T));
10234 +
10235 +       // DMA Queue Base & Size
10236 +       writel((sl351x_nat_workaround_desc_dma & DMA_Q_BASE_MASK) | NAT_WORAROUND_DESC_POWER,
10237 +                       TOE_GLOBAL_BASE + 0x4080);
10238 +       writel(0, TOE_GLOBAL_BASE + 0x4084);
10239 +}
10240 +
10241 +/*----------------------------------------------------------------------
10242 +*      sl351x_nat_workaround_handler
10243 +*----------------------------------------------------------------------*/
10244 +#ifndef NAT_WORKAROUND_BY_RESET_GMAC
10245 +static void sl351x_nat_workaround_handler(void)
10246 +{
10247 +       int                                     i;
10248 +       DMA_RWPTR_T                     rwptr;
10249 +       GMAC_RXDESC_T           *desc_ptr;
10250 +       unsigned int            buf_ptr;
10251 +       TOE_INFO_T                      *toe;
10252 +       GMAC_CONFIG0_T          config0;
10253 +       unsigned int            rwptr_addr;
10254 +
10255 +       toe = (TOE_INFO_T *)&toe_private_data;
10256 +
10257 +       // disable Rx of GMAC-0 & 1
10258 +       config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
10259 +       config0.bits.dis_rx = 1;
10260 +       writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
10261 +       config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
10262 +       config0.bits.dis_rx = 1;
10263 +       writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
10264 +
10265 +       // wait GMAC-0 HW Tx finished
10266 +       rwptr_addr = TOE_GMAC0_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
10267 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
10268 +       {
10269 +               rwptr.bits32 = readl(rwptr_addr);
10270 +               if (rwptr.bits.rptr != rwptr.bits.wptr)
10271 +                       return; // wait the HW to send packets and release buffers
10272 +               rwptr_addr+=4;
10273 +       }
10274 +       rwptr_addr = TOE_GMAC1_DMA_BASE + GMAC_HW_TX_QUEUE0_PTR_REG;
10275 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
10276 +       {
10277 +               rwptr.bits32 = readl(rwptr_addr);
10278 +               if (rwptr.bits.rptr != rwptr.bits.wptr)
10279 +                       return; // wait the HW to send packets and release buffers
10280 +               rwptr_addr+=4;
10281 +       }
10282 +
10283 +       // printk("sl351x_nat_workaround_handler %d\n", sl351x_nat_workaround_cnt);
10284 +       desc_ptr = (GMAC_RXDESC_T *)toe->hwfq_desc_base;
10285 +       buf_ptr = (unsigned int)toe->hwfq_buf_base_dma;
10286 +       for (i=0; i<TOE_HW_FREEQ_DESC_NUM; i++)
10287 +       {
10288 +               desc_ptr->word0.bits.buffer_size = HW_RX_BUF_SIZE;
10289 +               desc_ptr->word1.bits.sw_id = i;
10290 +               desc_ptr->word2.buf_adr = (unsigned int)buf_ptr;
10291 +               desc_ptr++;
10292 +               buf_ptr += HW_RX_BUF_SIZE;
10293 +       }
10294 +       rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
10295 +       rwptr.bits.wptr = RWPTR_RECEDE_ONE(rwptr.bits.rptr, TOE_HW_FREEQ_DESC_NUM);
10296 +       writel(rwptr.bits32, TOE_GLOBAL_BASE + GLOBAL_HWFQ_RWPTR_REG);
10297 +       writel(0, TOE_GLOBAL_BASE + 0x4084);
10298 +
10299 +       // Enable Rx of GMAC-0 & 1
10300 +       config0.bits32 = readl(TOE_GMAC0_BASE+GMAC_CONFIG0);
10301 +       config0.bits.dis_rx = 0;
10302 +       writel(config0.bits32, TOE_GMAC0_BASE+GMAC_CONFIG0);
10303 +       config0.bits32 = readl(TOE_GMAC1_BASE+GMAC_CONFIG0);
10304 +       config0.bits.dis_rx = 0;
10305 +       writel(config0.bits32, TOE_GMAC1_BASE+GMAC_CONFIG0);
10306 +}
10307 +#endif
10308 +#endif // CONFIG_SL351x_NAT
10309 +
10310 +#endif // SL351x_GMAC_WORKAROUND
10311 +
10312 +/* get the mac addresses from flash
10313 + *can't do this in module_init because mtd driver is initialized after ethernet
10314 + */
10315 +static __init int sl351x_mac_address_init(void)
10316 +{
10317 +       GMAC_INFO_T             *tp;
10318 +       struct sockaddr sock;
10319 +       int i;
10320 +
10321 +       /* get mac address from FLASH */
10322 +       gmac_get_mac_address();
10323 +
10324 +       for (i = 0; i < GMAC_NUM; i++) {
10325 +               tp = (GMAC_INFO_T *)&toe_private_data.gmac[i];
10326 +               memcpy(&sock.sa_data[0],&eth_mac[tp->port_id][0],6);
10327 +               gmac_set_mac_address(tp->dev,(void *)&sock);
10328 +       }
10329 +
10330 +        return 0;
10331 +}
10332 +late_initcall(sl351x_mac_address_init);
10333 +
10334 +
10335 Index: linux-2.6.23.17/drivers/net/sl351x_hash.c
10336 ===================================================================
10337 --- /dev/null
10338 +++ linux-2.6.23.17/drivers/net/sl351x_hash.c
10339 @@ -0,0 +1,713 @@
10340 +/**************************************************************************
10341 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
10342 +*--------------------------------------------------------------------------
10343 +* Name                 : sl351x_hash.c
10344 +* Description  :
10345 +*              Handle Storlink SL351x Hash Functions
10346 +*
10347 +* History
10348 +*
10349 +*      Date            Writer          Description
10350 +*----------------------------------------------------------------------------
10351 +*      03/13/2006      Gary Chen       Create and implement
10352 +*
10353 +****************************************************************************/
10354 +#include <linux/module.h>
10355 +#include <linux/kernel.h>
10356 +#include <linux/compiler.h>
10357 +#include <linux/pci.h>
10358 +#include <linux/init.h>
10359 +#include <linux/ioport.h>
10360 +#include <linux/netdevice.h>
10361 +#include <linux/etherdevice.h>
10362 +#include <linux/rtnetlink.h>
10363 +#include <linux/delay.h>
10364 +#include <linux/ethtool.h>
10365 +#include <linux/mii.h>
10366 +#include <linux/completion.h>
10367 +#include <asm/hardware.h>
10368 +#include <asm/io.h>
10369 +#include <asm/irq.h>
10370 +#include <asm/semaphore.h>
10371 +#include <asm/arch/irqs.h>
10372 +#include <asm/arch/it8712.h>
10373 +#include <linux/mtd/kvctl.h>
10374 +#include <linux/skbuff.h>
10375 +#include <linux/in.h>
10376 +#include <linux/ip.h>
10377 +#include <linux/tcp.h>
10378 +#include <linux/list.h>
10379 +#define         MIDWAY
10380 +#define         SL_LEPUS
10381 +
10382 +#include <asm/arch/sl2312.h>
10383 +#include <asm/arch/sl351x_gmac.h>
10384 +#include <asm/arch/sl351x_hash_cfg.h>
10385 +
10386 +#ifndef RXTOE_DEBUG
10387 +#define RXTOE_DEBUG
10388 +#endif
10389 +#undef RXTOE_DEBUG
10390 +
10391 +/*----------------------------------------------------------------------
10392 +* Definition
10393 +*----------------------------------------------------------------------*/
10394 +#define        hash_printf                             printk
10395 +
10396 +#define HASH_TIMER_PERIOD              (30)    // seconds
10397 +#define HASH_ILLEGAL_INDEX             0xffff
10398 +
10399 +/*----------------------------------------------------------------------
10400 +* Variables
10401 +*----------------------------------------------------------------------*/
10402 +u32                                    hash_nat_owner_bits[HASH_TOTAL_ENTRIES/32];
10403 +char                           hash_tables[HASH_TOTAL_ENTRIES][HASH_MAX_BYTES] __attribute__ ((aligned(16)));
10404 +static struct timer_list hash_timer_obj;
10405 +LIST_HEAD(hash_timeout_list);
10406 +
10407 +/*----------------------------------------------------------------------
10408 +* Functions
10409 +*----------------------------------------------------------------------*/
10410 +void dm_long(u32 location, int length);
10411 +static void hash_timer_func(u32 data);
10412 +
10413 +/*----------------------------------------------------------------------
10414 +* hash_init
10415 +*----------------------------------------------------------------------*/
10416 +void sl351x_hash_init(void)
10417 +{
10418 +       int i;
10419 +       volatile u32 *dp1, *dp2, dword;
10420 +
10421 +       dp1 = (volatile u32 *) TOE_V_BIT_BASE;
10422 +       dp2 = (volatile u32 *) TOE_A_BIT_BASE;
10423 +
10424 +       for (i=0; i<HASH_TOTAL_ENTRIES/32; i++)
10425 +       {
10426 +               *dp1++ = 0;
10427 +               dword = *dp2++; // read-clear
10428 +       }
10429 +       memset((void *)&hash_nat_owner_bits, 0, sizeof(hash_nat_owner_bits));
10430 +       memset((void *)&hash_tables, 0, sizeof(hash_tables));
10431 +
10432 +       init_timer(&hash_timer_obj);
10433 +       hash_timer_obj.expires = jiffies + (HASH_TIMER_PERIOD * HZ);
10434 +       hash_timer_obj.data = (unsigned long)&hash_timer_obj;
10435 +       hash_timer_obj.function = (void *)&hash_timer_func;
10436 +       add_timer(&hash_timer_obj);
10437 +
10438 +#if (HASH_MAX_BYTES == 128)
10439 +       writel((unsigned long)__pa(&hash_tables) | 3,   // 32 words
10440 +                       TOE_GLOBAL_BASE + GLOBAL_HASH_TABLE_BASE_REG);
10441 +#elif (HASH_MAX_BYTES == 64)
10442 +       writel((unsigned long)__pa(&hash_tables) | 2,   // 16 words
10443 +                       TOE_GLOBAL_BASE + GLOBAL_HASH_TABLE_BASE_REG);
10444 +#else
10445 +       #error Incorrect setting for HASH_MAX_BYTES
10446 +#endif
10447 +
10448 +}
10449 +/*----------------------------------------------------------------------
10450 +* hash_add_entry
10451 +*----------------------------------------------------------------------*/
10452 +int hash_add_entry(HASH_ENTRY_T *entry)
10453 +{
10454 +       int     rc;
10455 +       u32     key[HASH_MAX_DWORDS];
10456 +       rc = hash_build_keys((u32 *)&key, entry);
10457 +       if (rc < 0)
10458 +               return -1;
10459 +       hash_write_entry(entry, (unsigned char*) &key[0]);
10460 +//     hash_set_valid_flag(entry->index, 1);
10461 +//     printk("Dump hash key!\n");
10462 +//     dump_hash_key(entry);
10463 +       return entry->index;
10464 +}
10465 +
10466 +/*----------------------------------------------------------------------
10467 +* hash_set_valid_flag
10468 +*----------------------------------------------------------------------*/
10469 +void hash_set_valid_flag(int index, int valid)
10470 +{
10471 +       register u32 reg32;
10472 +
10473 +       reg32 = TOE_V_BIT_BASE + (index/32) * 4;
10474 +
10475 +       if (valid)
10476 +       {
10477 +               writel(readl(reg32) | (1 << (index%32)), reg32);
10478 +       }
10479 +       else
10480 +       {
10481 +               writel(readl(reg32) & ~(1 << (index%32)), reg32);
10482 +       }
10483 +}
10484 +
10485 +/*----------------------------------------------------------------------
10486 +* hash_set_nat_owner_flag
10487 +*----------------------------------------------------------------------*/
10488 +void hash_set_nat_owner_flag(int index, int valid)
10489 +{
10490 +       if (valid)
10491 +       {
10492 +               hash_nat_owner_bits[index/32] |= (1 << (index % 32));
10493 +       }
10494 +       else
10495 +       {
10496 +               hash_nat_owner_bits[index/32] &= ~(1 << (index % 32));
10497 +       }
10498 +}
10499 +
10500 +
10501 +/*----------------------------------------------------------------------
10502 +* hash_build_keys
10503 +*----------------------------------------------------------------------*/
10504 +int hash_build_keys(u32 *destp, HASH_ENTRY_T *entry)
10505 +{
10506 +       u32     data;
10507 +       unsigned char   *cp;
10508 +       int                             i, j;
10509 +       unsigned short  index;
10510 +       int                     total;
10511 +
10512 +       memset((void *)destp, 0, HASH_MAX_BYTES);
10513 +       cp = (unsigned char *)destp;
10514 +
10515 +       if (entry->key_present.port || entry->key_present.Ethertype)
10516 +       {
10517 +               HASH_PUSH_WORD(cp, entry->key.Ethertype);               // word 0
10518 +               HASH_PUSH_BYTE(cp, entry->key.port);                    // Byte 2
10519 +               HASH_PUSH_BYTE(cp, 0);                                                  // Byte 3
10520 +       }
10521 +       else
10522 +       {
10523 +               HASH_PUSH_DWORD(cp, 0);
10524 +       }
10525 +
10526 +       if (entry->key_present.da || entry->key_present.sa)
10527 +       {
10528 +               unsigned char mac[4];
10529 +               if (entry->key_present.da)
10530 +               {
10531 +                       for (i=0; i<4; i++)
10532 +                               HASH_PUSH_BYTE(cp, entry->key.da[i]);
10533 +               }
10534 +               mac[0] = (entry->key_present.da) ? entry->key.da[4] : 0;
10535 +               mac[1] = (entry->key_present.da) ? entry->key.da[5] : 0;
10536 +               mac[2] = (entry->key_present.sa) ? entry->key.sa[0] : 0;
10537 +               mac[3] = (entry->key_present.sa) ? entry->key.sa[1] : 0;
10538 +               data = mac[0] + (mac[1]<<8) + (mac[2]<<16) + (mac[3]<<24);
10539 +               HASH_PUSH_DWORD(cp, data);
10540 +               if (entry->key_present.sa)
10541 +               {
10542 +                       for (i=2; i<6; i++)
10543 +                               HASH_PUSH_BYTE(cp, entry->key.sa[i]);
10544 +               }
10545 +       }
10546 +
10547 +       if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
10548 +       {
10549 +               HASH_PUSH_WORD(cp, entry->key.vlan_id);         // low word
10550 +               HASH_PUSH_WORD(cp, entry->key.pppoe_sid);       // high word
10551 +       }
10552 +       if (entry->key_present.ipv4_hdrlen || entry->key_present.ip_tos || entry->key_present.ip_protocol)
10553 +       {
10554 +               HASH_PUSH_BYTE(cp, entry->key.ip_protocol);             // Byte 0
10555 +               HASH_PUSH_BYTE(cp, entry->key.ip_tos);                  // Byte 1
10556 +               HASH_PUSH_BYTE(cp, entry->key.ipv4_hdrlen);             // Byte 2
10557 +               HASH_PUSH_BYTE(cp, 0);                                                  // Byte 3
10558 +       }
10559 +
10560 +       if (entry->key_present.ipv6_flow_label)
10561 +       {
10562 +               HASH_PUSH_DWORD(cp, entry->key.ipv6_flow_label);        // low word
10563 +       }
10564 +       if (entry->key_present.sip)
10565 +       {
10566 +               // input (entry->key.sip[i]) is network-oriented
10567 +               // output (hash key) is host-oriented
10568 +               for (i=3; i>=0; i--)
10569 +                       HASH_PUSH_BYTE(cp, entry->key.sip[i]);
10570 +               if (entry->key.ipv6)
10571 +               {
10572 +                       for (i=4; i<16; i+=4)
10573 +                       {
10574 +                               for (j=i+3; j>=i; j--)
10575 +                                       HASH_PUSH_BYTE(cp, entry->key.sip[j]);
10576 +                       }
10577 +               }
10578 +       }
10579 +       if (entry->key_present.dip)
10580 +       {
10581 +               // input (entry->key.sip[i]) is network-oriented
10582 +               // output (hash key) is host-oriented
10583 +               for (i=3; i>=0; i--)
10584 +                       HASH_PUSH_BYTE(cp, entry->key.dip[i]);
10585 +               if (entry->key.ipv6)
10586 +               {
10587 +                       for (i=4; i<16; i+=4)
10588 +                       {
10589 +                               for (j=i+3; j>=i; j--)
10590 +                                       HASH_PUSH_BYTE(cp, entry->key.dip[j]);
10591 +                       }
10592 +               }
10593 +       }
10594 +
10595 +       if (entry->key_present.l4_bytes_0_3)
10596 +       {
10597 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
10598 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
10599 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
10600 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
10601 +       }
10602 +       if (entry->key_present.l4_bytes_4_7)
10603 +       {
10604 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[4]);
10605 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[5]);
10606 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[6]);
10607 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[7]);
10608 +       }
10609 +       if (entry->key_present.l4_bytes_8_11)
10610 +       {
10611 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[8]);
10612 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[9]);
10613 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[10]);
10614 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[11]);
10615 +       }
10616 +       if (entry->key_present.l4_bytes_12_15)
10617 +       {
10618 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[12]);
10619 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[13]);
10620 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[14]);
10621 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[15]);
10622 +       }
10623 +       if (entry->key_present.l4_bytes_16_19)
10624 +       {
10625 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[16]);
10626 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[17]);
10627 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[18]);
10628 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[19]);
10629 +       }
10630 +       if (entry->key_present.l4_bytes_20_23)
10631 +       {
10632 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[20]);
10633 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[21]);
10634 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[22]);
10635 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[23]);
10636 +       }
10637 +       if (entry->key_present.l7_bytes_0_3)
10638 +       {
10639 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[0]);
10640 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[1]);
10641 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[2]);
10642 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[3]);
10643 +       }
10644 +       if (entry->key_present.l7_bytes_4_7)
10645 +       {
10646 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[4]);
10647 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[5]);
10648 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[6]);
10649 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[7]);
10650 +       }
10651 +       if (entry->key_present.l7_bytes_8_11)
10652 +       {
10653 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[8]);
10654 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[9]);
10655 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[10]);
10656 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[11]);
10657 +       }
10658 +       if (entry->key_present.l7_bytes_12_15)
10659 +       {
10660 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[12]);
10661 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[13]);
10662 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[14]);
10663 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[15]);
10664 +       }
10665 +       if (entry->key_present.l7_bytes_16_19)
10666 +       {
10667 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[16]);
10668 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[17]);
10669 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[18]);
10670 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[19]);
10671 +       }
10672 +       if (entry->key_present.l7_bytes_20_23)
10673 +       {
10674 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[20]);
10675 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[21]);
10676 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[22]);
10677 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[23]);
10678 +       }
10679 +
10680 +       // get hash index
10681 +       total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
10682 +
10683 +       if (total > HASH_MAX_KEY_DWORD)
10684 +       {
10685 +               //hash_printf("Total key words (%d) is too large (> %d)!\n",
10686 +               //                              total, HASH_MAX_KEY_DWORD);
10687 +               return -1;
10688 +       }
10689 +
10690 +       if (entry->key_present.port || entry->key_present.Ethertype)
10691 +               index = hash_gen_crc16((unsigned char *)destp, total * 4);
10692 +       else
10693 +       {
10694 +               if (total == 1)
10695 +               {
10696 +                       hash_printf("No key is assigned!\n");
10697 +                       return -1;
10698 +               }
10699 +
10700 +               index = hash_gen_crc16((unsigned char *)(destp+1), (total-1) * 4);
10701 +       }
10702 +
10703 +       entry->index = index & HASH_BITS_MASK;
10704 +
10705 +       //hash_printf("Total key words = %d, Hash Index= %d\n",
10706 +       //                              total, entry->index);
10707 +
10708 +       cp = (unsigned char *)destp;
10709 +       cp+=3;
10710 +       HASH_PUSH_BYTE(cp, entry->rule);        // rule
10711 +
10712 +       entry->total_dwords = total;
10713 +
10714 +       return total;
10715 +}
10716 +
10717 +/*----------------------------------------------------------------------
10718 +* hash_build_nat_keys
10719 +*----------------------------------------------------------------------*/
10720 +void hash_build_nat_keys(u32 *destp, HASH_ENTRY_T *entry)
10721 +{
10722 +       unsigned char   *cp;
10723 +       int                             i;
10724 +       unsigned short  index;
10725 +       int                     total;
10726 +
10727 +       memset((void *)destp, 0, HASH_MAX_BYTES);
10728 +
10729 +       cp = (unsigned char *)destp + 2;
10730 +       HASH_PUSH_BYTE(cp, entry->key.port);
10731 +       cp++;
10732 +
10733 +       if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
10734 +       {
10735 +               HASH_PUSH_WORD(cp, entry->key.vlan_id);         // low word
10736 +               HASH_PUSH_WORD(cp, entry->key.pppoe_sid);       // high word
10737 +       }
10738 +
10739 +       HASH_PUSH_BYTE(cp, entry->key.ip_protocol);
10740 +       cp+=3;
10741 +
10742 +       // input (entry->key.sip[i]) is network-oriented
10743 +       // output (hash key) is host-oriented
10744 +       for (i=3; i>=0; i--)
10745 +               HASH_PUSH_BYTE(cp, entry->key.sip[i]);
10746 +
10747 +       // input (entry->key.sip[i]) is network-oriented
10748 +       // output (hash key) is host-oriented
10749 +       for (i=3; i>=0; i--)
10750 +               HASH_PUSH_BYTE(cp, entry->key.dip[i]);
10751 +
10752 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
10753 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
10754 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
10755 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
10756 +
10757 +       // get hash index
10758 +       total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
10759 +
10760 +       index = hash_gen_crc16((unsigned char *)destp, total * 4);
10761 +       entry->index = index & ((1 << HASH_BITS) - 1);
10762 +
10763 +       cp = (unsigned char *)destp;
10764 +       cp+=3;
10765 +       HASH_PUSH_BYTE(cp, entry->rule);        // rule
10766 +
10767 +       entry->total_dwords = total;
10768 +}
10769 +
10770 +/*----------------------------------------------------------------------
10771 +* hash_build_toe_keys
10772 +*----------------------------------------------------------------------*/
10773 +int hash_build_toe_keys(u32 *destp, HASH_ENTRY_T *entry)
10774 +{
10775 +       unsigned long   data;
10776 +       unsigned char   *cp;
10777 +       unsigned short  index;
10778 +       int     i;
10779 +       int total;
10780 +       //printk("%s\n", __func__);
10781 +       memset((void*)destp, 0, HASH_MAX_BYTES);
10782 +       cp = (unsigned char*)destp;
10783 +
10784 +       if(entry->key_present.port || entry->key_present.Ethertype) {
10785 +               data = (entry->key.port << 16) + entry->key.Ethertype;
10786 +               HASH_PUSH_DWORD(cp, data);
10787 +       } else
10788 +               HASH_PUSH_DWORD(cp, 0);
10789 +
10790 +       if (entry->key_present.da || entry->key_present.sa) {
10791 +               unsigned char   mac[4];
10792 +               if (entry->key_present.da) {
10793 +                       data = (entry->key.da[0]) + (entry->key.da[1] << 8) +
10794 +                                  (entry->key.da[2] << 16) + (entry->key.da[3] <<24);
10795 +                       HASH_PUSH_DWORD(cp, data);
10796 +               }
10797 +               mac[0] = (entry->key_present.da) ? entry->key.da[4] : 0;
10798 +               mac[1] = (entry->key_present.da) ? entry->key.da[5] : 0;
10799 +               mac[2] = (entry->key_present.sa) ? entry->key.sa[0] : 0;
10800 +               mac[3] = (entry->key_present.sa) ? entry->key.sa[1] : 0;
10801 +               data = mac[0] + (mac[1]<<8) + (mac[2]<<16) + (mac[3]<<24);
10802 +               HASH_PUSH_DWORD(cp, data);
10803 +               if (entry->key_present.sa) {
10804 +                       data = (entry->key.sa[2]) + (entry->key.sa[3] << 8) +
10805 +                                  (entry->key.sa[4] << 16) + (entry->key.sa[5] <<24);
10806 +                       HASH_PUSH_DWORD(cp, data);
10807 +               }
10808 +       }
10809 +
10810 +       if (entry->key_present.ip_protocol) {
10811 +               unsigned char ip_protocol;
10812 +               ip_protocol = entry->key.ip_protocol;
10813 +               data = ip_protocol;
10814 +               HASH_PUSH_DWORD(cp, data);
10815 +       }
10816 +
10817 +       if (entry->key_present.ipv6_flow_label) {
10818 +               unsigned long flow_label;
10819 +               flow_label  = entry->key.ipv6_flow_label;
10820 +               data = flow_label & 0xfffff;
10821 +               HASH_PUSH_DWORD(cp, data);
10822 +       }
10823 +
10824 +       if (entry->key_present.sip)     {
10825 +               {
10826 +                       data = IPIV(entry->key.sip[0], entry->key.sip[1],
10827 +                                       entry->key.sip[2], entry->key.sip[3]);
10828 +                       HASH_PUSH_DWORD(cp, data);
10829 +                       if (entry->key.ipv6) {
10830 +                               for (i=4; i<16; i+=4) {
10831 +                                       data = IPIV(entry->key.sip[i+0], entry->key.sip[i+1],
10832 +                                                       entry->key.sip[i+2], entry->key.sip[i+3]);
10833 +                                       HASH_PUSH_DWORD(cp, data);
10834 +                               }
10835 +                       }
10836 +               }
10837 +       }
10838 +
10839 +       if (entry->key_present.dip)     {
10840 +               {
10841 +                       data = IPIV(entry->key.dip[0], entry->key.dip[1],
10842 +                                               entry->key.dip[2], entry->key.dip[3]);
10843 +                       HASH_PUSH_DWORD(cp, data);
10844 +                       if (entry->key.ipv6) {
10845 +                               for (i=4; i<16; i+=4) {
10846 +                                       data = IPIV(entry->key.dip[i+0], entry->key.dip[i+1],
10847 +                                                               entry->key.dip[i+2], entry->key.dip[i+3]);
10848 +                                       HASH_PUSH_DWORD(cp, data);
10849 +                               }
10850 +                       }
10851 +               }
10852 +       }
10853 +       if (entry->key_present.l4_bytes_0_3)
10854 +       {
10855 +               unsigned char *datap;
10856 +               datap = &entry->key.l4_bytes[0];
10857 +               data =  datap[0] +      (datap[1] << 8) + (datap[2] << 16) + (datap[3] << 24);
10858 +               HASH_PUSH_DWORD(cp, data);
10859 +       }
10860 +       if (entry->key_present.l7_bytes_0_3)
10861 +       {
10862 +               unsigned char *datap;
10863 +               datap = &entry->key.l7_bytes[0];
10864 +               data =  datap[0] +      (datap[1] << 8) + (datap[2] << 16) + (datap[3] << 24);
10865 +               HASH_PUSH_DWORD(cp, data);
10866 +       }
10867 +       if (entry->key_present.l7_bytes_4_7)
10868 +       {
10869 +               unsigned char *datap;
10870 +               datap = &entry->key.l7_bytes[4];
10871 +               data =  datap[0] +      (datap[1] << 8) + (datap[2] << 16) + (datap[3] << 24);
10872 +               HASH_PUSH_DWORD(cp, data);
10873 +       }
10874 +
10875 +       total = (unsigned long)((unsigned long)cp - (unsigned long)destp) / (sizeof(u32));
10876 +       if (total > HASH_MAX_KEY_DWORD) {
10877 +               //printf("Total key words (%d) is too large (> %d)!\n",
10878 +               //              total, HASH_MAX_KEY_DWORD);
10879 +               return -1;
10880 +       }
10881 +       index = hash_gen_crc16((unsigned char*)(destp + 1), (total-1)*4);
10882 +       entry->index = index & ((1 << HASH_BITS)-1);
10883 +
10884 +       cp = (unsigned char*) destp;
10885 +       cp += 3;
10886 +       HASH_PUSH_BYTE(cp, entry->rule);
10887 +       entry->total_dwords = total;
10888 +       return total;
10889 +}
10890 +
10891 +/*----------------------------------------------------------------------
10892 +* hash_add_toe_entry
10893 +*----------------------------------------------------------------------*/
10894 +int hash_add_toe_entry(HASH_ENTRY_T *entry)
10895 +{
10896 +       int     rc;
10897 +       u32     key[HASH_MAX_DWORDS];
10898 +
10899 +       rc = hash_build_toe_keys((u32 *)&key, entry);
10900 +       if (rc < 0)
10901 +               return -1;
10902 +       hash_write_entry(entry, (unsigned char*) &key[0]);
10903 +       //hash_dump_entry(entry->index);
10904 +//     hash_set_valid_flag(entry->index, 1);
10905 +//     printk("Dump hash key!\n");
10906 +//     dump_hash_key(entry);
10907 +       return entry->index;
10908 +}
10909 +
10910 +
10911 +/*----------------------------------------------------------------------
10912 +* hash_write_entry
10913 +*----------------------------------------------------------------------*/
10914 +int hash_write_entry(HASH_ENTRY_T *entry, unsigned char *key)
10915 +{
10916 +       int             i;
10917 +       u32             *srcep, *destp, *destp2;
10918 +
10919 +       srcep = (u32 *)key;
10920 +       destp2 = destp = (u32 *)&hash_tables[entry->index][0];
10921 +
10922 +       for (i=0; i<(entry->total_dwords); i++, srcep++, destp++)
10923 +               *destp = *srcep;
10924 +
10925 +       srcep = (u32 *)&entry->action;
10926 +       *destp++ = *srcep;
10927 +
10928 +       srcep = (u32 *)&entry->param;
10929 +       for (i=0; i<(sizeof(ENTRY_PARAM_T)/sizeof(*destp)); i++, srcep++, destp++)
10930 +               *destp = *srcep;
10931 +
10932 +       memset(destp, 0, (HASH_MAX_DWORDS-entry->total_dwords-HASH_ACTION_DWORDS) * sizeof(u32));
10933 +
10934 +       consistent_sync(destp2, (entry->total_dwords+HASH_ACTION_DWORDS) * 4, PCI_DMA_TODEVICE);
10935 +       return 0;
10936 +}
10937 +
10938 +/*----------------------------------------------------------------------
10939 +* hash_timer_func
10940 +*----------------------------------------------------------------------*/
10941 +static void hash_timer_func(u32 data)
10942 +{
10943 +       int                                     i, j, idx;
10944 +       volatile u32            *own_p, *valid_p;
10945 +       u32                                     own_bits, a_bits;
10946 +       int                                     period = HASH_TIMER_PERIOD;
10947 +
10948 +       valid_p = (volatile u32 *)TOE_V_BIT_BASE;
10949 +       own_p = (volatile u32 *)hash_nat_owner_bits;
10950 +       for (i=0, idx=0; i<(HASH_TOTAL_ENTRIES/32); i++, own_p++, valid_p++, idx+=32)
10951 +       {
10952 +               a_bits = readl(TOE_A_BIT_BASE + (i*4));
10953 +               own_bits = *own_p;
10954 +               if (own_bits)
10955 +               {
10956 +                       for (j=0; own_bits && j<32; j++)
10957 +                       {
10958 +                               if (own_bits & 1)
10959 +                               {
10960 +                                       short *counter_p, *interval_p;
10961 +                                       NAT_HASH_ENTRY_T        *nat_entry;
10962 +                                       GRE_HASH_ENTRY_T        *gre_entry;
10963 +                                       nat_entry = (NAT_HASH_ENTRY_T *)hash_get_entry(idx+j);
10964 +                                       gre_entry = (GRE_HASH_ENTRY_T *)nat_entry;
10965 +                                       if (nat_entry->key.ip_protocol == IPPROTO_GRE)
10966 +                                       {
10967 +                                               counter_p = (short *)&gre_entry->tmo.counter;
10968 +                                               interval_p = (short *)&gre_entry->tmo.interval;
10969 +                                       }
10970 +                                       else
10971 +                                       {
10972 +                                               counter_p = (short *)&nat_entry->tmo.counter;
10973 +                                               interval_p = (short *)&nat_entry->tmo.interval;
10974 +                                       }
10975 +                                       if (a_bits & 1)
10976 +                                       {
10977 +                                               *counter_p = *interval_p;
10978 +                                       }
10979 +                                       else
10980 +                                       {
10981 +                                               *counter_p -= HASH_TIMER_PERIOD;
10982 +                                               if (*counter_p <= 0)
10983 +                                               {
10984 +                                                       *valid_p &= ~(1 << j);          // invalidate it
10985 +                                                       *own_p &= ~(1 << j);            // release ownership for NAT
10986 +                                                       *counter_p = 0;
10987 +                                                       // hash_printf("%lu %s: Clear hash index: %d\n", jiffies/HZ, __func__, i*32+j);
10988 +                                               }
10989 +                                               else if (period > *counter_p)
10990 +                                               {
10991 +                                                       period = *counter_p;
10992 +                                               }
10993 +                                       }
10994 +                               }
10995 +                               a_bits >>= 1;
10996 +                               own_bits >>=1;
10997 +                       }
10998 +               }
10999 +       }
11000 +
11001 +       hash_timer_obj.expires = jiffies + (period * HZ);
11002 +       add_timer((struct timer_list *)data);
11003 +}
11004 +
11005 +/*----------------------------------------------------------------------
11006 +* dm_long
11007 +*----------------------------------------------------------------------*/
11008 +void dm_long(u32 location, int length)
11009 +{
11010 +       u32             *start_p, *curr_p, *end_p;
11011 +       u32             *datap, data;
11012 +       int             i;
11013 +
11014 +       //if (length > 1024)
11015 +       //      length = 1024;
11016 +
11017 +       start_p = (u32 *)location;
11018 +       end_p = (u32 *)location + length;
11019 +       curr_p = (u32 *)((u32)location & 0xfffffff0);
11020 +       datap = (u32 *)location;
11021 +       while (curr_p < end_p)
11022 +       {
11023 +               hash_printf("0x%08x: ",(u32)curr_p & 0xfffffff0);
11024 +               for (i=0; i<4; i++)
11025 +               {
11026 +                       if (curr_p < start_p || curr_p >= end_p)
11027 +               hash_printf("         ");
11028 +                       else
11029 +                       {
11030 +                               data = *datap;
11031 +                               hash_printf("%08X ", data);
11032 +                       }
11033 +                       if (i==1)
11034 +              hash_printf("- ");
11035 +
11036 +                       curr_p++;
11037 +                       datap++;
11038 +               }
11039 +        hash_printf("\n");
11040 +       }
11041 +}
11042 +
11043 +/*----------------------------------------------------------------------
11044 +* hash_dump_entry
11045 +*----------------------------------------------------------------------*/
11046 +void hash_dump_entry(int index)
11047 +{
11048 +       hash_printf("Hash Index %d:\n", index);
11049 +       dm_long((u32)&hash_tables[index][0], HASH_MAX_DWORDS);
11050 +}
11051 +
11052 +
11053 Index: linux-2.6.23.17/drivers/net/sl351x_nat.c
11054 ===================================================================
11055 --- /dev/null
11056 +++ linux-2.6.23.17/drivers/net/sl351x_nat.c
11057 @@ -0,0 +1,1736 @@
11058 +/****************************************************************************
11059 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
11060 +*----------------------------------------------------------------------------
11061 +* Name                 : sl351x_nat.c
11062 +* Description  :
11063 +*              Handle Storlink SL351x NAT Functions
11064 +*
11065 +*
11066 +* Packet Flow:
11067 +*
11068 +*            (xmit)+<--- SW NAT -->+(xmit)
11069 +*                  |       ^^      |
11070 +*                  |       ||      |
11071 +*                  |       ||      |
11072 +*   Client <---> GMAC-x  HW-NAT  GMAC-y  <---> Server
11073 +*
11074 +*
11075 +* History
11076 +*
11077 +*      Date            Writer          Description
11078 +*----------------------------------------------------------------------------
11079 +*      03/13/2006      Gary Chen       Create and implement
11080 +*
11081 +*
11082 +****************************************************************************/
11083 +#include <linux/module.h>
11084 +#include <linux/kernel.h>
11085 +#include <linux/compiler.h>
11086 +#include <linux/pci.h>
11087 +#include <linux/init.h>
11088 +#include <linux/ioport.h>
11089 +#include <linux/netdevice.h>
11090 +#include <linux/etherdevice.h>
11091 +#include <linux/rtnetlink.h>
11092 +#include <linux/delay.h>
11093 +#include <linux/ethtool.h>
11094 +#include <linux/mii.h>
11095 +#include <linux/completion.h>
11096 +#include <asm/hardware.h>
11097 +#include <asm/io.h>
11098 +#include <asm/irq.h>
11099 +#include <asm/semaphore.h>
11100 +#include <asm/arch/irqs.h>
11101 +#include <asm/arch/it8712.h>
11102 +#include <linux/mtd/kvctl.h>
11103 +#include <linux/skbuff.h>
11104 +#include <linux/if_ether.h>
11105 +#include <linux/if_pppox.h>
11106 +#include <linux/in.h>
11107 +#include <linux/ip.h>
11108 +#include <linux/tcp.h>
11109 +#include <linux/udp.h>
11110 +#include <linux/ppp_defs.h>
11111 +
11112 +#define         MIDWAY
11113 +#define         SL_LEPUS
11114 +
11115 +#include <asm/arch/sl2312.h>
11116 +#include <asm/arch/sl351x_gmac.h>
11117 +#include <asm/arch/sl351x_hash_cfg.h>
11118 +#include <asm/arch/sl351x_nat_cfg.h>
11119 +#ifdef CONFIG_NETFILTER
11120 +#include <linux/netfilter_ipv4/ip_conntrack.h>
11121 +#include <linux/netfilter_ipv4/ip_conntrack_tcp.h>
11122 +#endif
11123 +
11124 +//#define NAT_DEBUG_MSG                1
11125 +#define _NOT_CHECK_SIP_DIP
11126 +//#define      SL351x_NAT_TEST_BY_SMARTBITS            1       // Initialize 32 hash entries and test by SmartBITS
11127 +#define VITESSE_G5SWITCH       1
11128 +
11129 +#ifdef CONFIG_SL351x_NAT
11130 +
11131 +/*----------------------------------------------------------------------
11132 +* Definition
11133 +*----------------------------------------------------------------------*/
11134 +#ifdef CONFIG_SL3516_ASIC
11135 +#define CONFIG_SL351x_NAT_TCP_UDP
11136 +#define CONFIG_SL351x_NAT_GRE
11137 +#define CONFIG_SL351x_TCP_UDP_RULE_ID  0
11138 +#define CONFIG_SL351x_GRE_RULE_ID              1
11139 +#else
11140 +#define CONFIG_SL351x_NAT_TCP_UDP
11141 +//#define CONFIG_SL351x_NAT_GRE
11142 +#define CONFIG_SL351x_TCP_UDP_RULE_ID  0
11143 +#define CONFIG_SL351x_GRE_RULE_ID              0
11144 +#endif
11145 +
11146 +#define        nat_printf                                      printk
11147 +#define NAT_FTP_CTRL_PORT                      (21)    // TCP
11148 +#define NAT_H323_PORT                          (1720)  // TCP
11149 +#define NAT_T120_PORT                          (1503)  // TCP
11150 +#define NAT_PPTP_PORT                          (1723)  // TCP
11151 +#define NAT_TFTP_PORT                          (69)    // UDP
11152 +#define NAT_DNS_PORT                           (53)    // UDP
11153 +#define NAT_NTP_PORT                           (123)   // UDP
11154 +#define NAT_RAS_PORT                           (1719)  // UDP
11155 +#define NAT_BOOTP67_PORT                       (67)    // UDP
11156 +#define NAT_BOOTP68_PORT                       (68)    // UDP
11157 +
11158 +#define NAT_TCP_PORT_MAX                       64
11159 +#define NAT_UDP_PORT_MAX                       64
11160 +
11161 +#define GRE_PROTOCOL                           (0x880b)
11162 +#define GRE_PROTOCOL_SWAP                      __constant_htons(0x880b)
11163 +
11164 +#ifdef VITESSE_G5SWITCH
11165 +extern int Giga_switch;
11166 +#endif
11167 +
11168 +typedef struct
11169 +{
11170 +       u16             flags_ver;
11171 +       u16             protocol;
11172 +       u16             payload_length;
11173 +       u16             call_id;
11174 +       u32             seq;
11175 +       u32             ack;
11176 +} GRE_PKTHDR_T;
11177 +
11178 +/*----------------------------------------------------------------------
11179 +* NAT Configuration
11180 +*
11181 +* Note: Any change for network setting, the NAT configuration should
11182 +*       be changed also.
11183 +*      cfg->lan_port   0 if GMAC-0, 1: if GMAC-1
11184 +*      cfg->wan_port   0 if GMAC-0, 1: if GMAC-1
11185 +*      cfg->lan_ipaddr, cfg->lan_gateway, cfg->lan_netmask
11186 +*      cfg->wan_ipaddr, cfg->wan_gateway, cfg->wan_netmask
11187 +*
11188 +*----------------------------------------------------------------------*/
11189 +NAT_CFG_T              nat_cfg;
11190 +static int             nat_initialized;
11191 +u32                    nat_collision;
11192 +
11193 +#ifdef CONFIG_SL351x_NAT_TCP_UDP
11194 +static u16             fixed_tcp_port_list[]={NAT_FTP_CTRL_PORT,
11195 +                                                                               NAT_H323_PORT,
11196 +                                                                               // NAT_T120_PORT,
11197 +                                                                               NAT_PPTP_PORT,
11198 +                                                                               0};
11199 +static u16             fixed_udp_port_list[]={NAT_DNS_PORT,
11200 +                                                                               NAT_NTP_PORT,
11201 +                                                                               NAT_TFTP_PORT,
11202 +                                                                               NAT_RAS_PORT,
11203 +                                                                               NAT_BOOTP67_PORT,
11204 +                                                                               NAT_BOOTP68_PORT,
11205 +                                                                               0};
11206 +#endif
11207 +
11208 +// #define _HAVE_DYNAMIC_PORT_LIST
11209 +#ifdef _HAVE_DYNAMIC_PORT_LIST
11210 +static u16             dynamic_tcp_port_list[NAT_TCP_PORT_MAX+1];
11211 +static u16             dynamic_udp_port_list[NAT_UDP_PORT_MAX+1]};
11212 +#endif
11213 +
11214 +/*----------------------------------------------------------------------
11215 +* Functions
11216 +*----------------------------------------------------------------------*/
11217 +int sl351x_nat_tcp_udp_output(struct sk_buff *skb, int port);
11218 +int sl351x_nat_udp_output(struct sk_buff *skb, int port);
11219 +int sl351x_nat_gre_output(struct sk_buff *skb, int port);
11220 +
11221 +extern int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2);
11222 +extern void hash_dump_entry(int index);
11223 +extern void mac_get_hw_tx_weight(struct net_device *dev, char *weight);
11224 +extern void mac_set_hw_tx_weight(struct net_device *dev, char *weight);
11225 +
11226 +#ifdef SL351x_NAT_TEST_BY_SMARTBITS
11227 +static void nat_init_test_entry(void);
11228 +#endif
11229 +/*----------------------------------------------------------------------
11230 +* sl351x_nat_init
11231 +*      initialize a NAT matching rule
11232 +*      Called by SL351x Driver
11233 +*              key             : port, protocol, Sip, Dip, Sport, Dport
11234 +*              Action  : Srce Q: HW Free Queue,
11235 +*                                Dest Q: HW TxQ
11236 +*                                Change DA
11237 +*                                Change SA
11238 +*                 Change Sip or Dip
11239 +*                        Change Sport or Dport
11240 +*----------------------------------------------------------------------*/
11241 +void sl351x_nat_init(void)
11242 +{
11243 +       int                                     rc;
11244 +       GMAC_MRxCR0_T           mrxcr0;
11245 +       GMAC_MRxCR1_T           mrxcr1;
11246 +       GMAC_MRxCR2_T           mrxcr2;
11247 +       NAT_CFG_T                       *cfg;
11248 +
11249 +       if (nat_initialized)
11250 +               return;
11251 +
11252 +       nat_initialized = 1;
11253 +
11254 +       if ((sizeof(NAT_HASH_ENTRY_T) > HASH_MAX_BYTES) ||
11255 +               (sizeof(GRE_HASH_ENTRY_T) > HASH_MAX_BYTES))
11256 +       {
11257 +               nat_printf("NAT_HASH_ENTRY_T structure Size is too larger!\n");
11258 +               while(1);
11259 +       }
11260 +
11261 +       cfg = (NAT_CFG_T *)&nat_cfg;
11262 +       memset((void *)cfg, 0, sizeof(NAT_CFG_T));
11263 +#ifdef _HAVE_DYNAMIC_PORT_LIST
11264 +       memset((void *)dynamic_tcp_port_list, 0, sizeof(dynamic_tcp_port_list));
11265 +       memset((void *)dynamic_udp_port_list, 0, sizeof(dynamic_udp_port_list));
11266 +#endif
11267 +
11268 +#ifdef VITESSE_G5SWITCH
11269 +       if(Giga_switch)
11270 +       {
11271 +               cfg->enabled                    = 1;
11272 +               cfg->tcp_udp_rule_id    = CONFIG_SL351x_TCP_UDP_RULE_ID;
11273 +               cfg->gre_rule_id                = CONFIG_SL351x_GRE_RULE_ID;
11274 +               cfg->lan_port                   = 1;
11275 +               cfg->wan_port                   = 0;
11276 +               cfg->default_hw_txq     = 3;
11277 +               cfg->tcp_tmo_interval   = 60;
11278 +               cfg->udp_tmo_interval   = 180;
11279 +               cfg->gre_tmo_interval   = 60;
11280 +       }
11281 +       else
11282 +       {
11283 +               cfg->enabled                    = 1;
11284 +               cfg->tcp_udp_rule_id    = CONFIG_SL351x_TCP_UDP_RULE_ID;
11285 +               cfg->gre_rule_id                = CONFIG_SL351x_GRE_RULE_ID;
11286 +               cfg->lan_port                   = 0;
11287 +               cfg->wan_port                   = 1;
11288 +               cfg->default_hw_txq     = 3;
11289 +               cfg->tcp_tmo_interval   = 60;
11290 +               cfg->udp_tmo_interval   = 180;
11291 +               cfg->gre_tmo_interval   = 60;
11292 +
11293 +       }
11294 +#endif
11295 +
11296 +#if 1  //      debug purpose
11297 +       cfg->ipcfg[0].total                             = 1;
11298 +       cfg->ipcfg[0].entry[0].ipaddr   = IPIV(192,168,2,92);
11299 +       cfg->ipcfg[0].entry[0].netmask  = IPIV(255,255,255,0);
11300 +       cfg->ipcfg[1].total                             = 1;
11301 +       cfg->ipcfg[1].entry[0].ipaddr   = IPIV(192,168,1,200);
11302 +       cfg->ipcfg[1].entry[0].netmask  = IPIV(255,255,255,0);
11303 +#endif
11304 +
11305 +#if 1
11306 +       cfg->xport.total = 0;
11307 +#else
11308 +       cfg->xport.total = 4;
11309 +
11310 +       // H.323/H.225 Call setup
11311 +       cfg->xport.entry[0].protocol = IPPROTO_TCP;
11312 +       cfg->xport.entry[0].sport_start = 0;
11313 +       cfg->xport.entry[0].sport_end = 0;
11314 +       cfg->xport.entry[0].dport_start = 1720;
11315 +       cfg->xport.entry[0].dport_end = 1720;
11316 +       cfg->xport.entry[1].protocol = IPPROTO_TCP;
11317 +       cfg->xport.entry[1].sport_start = 1720;
11318 +       cfg->xport.entry[1].sport_end = 1720;
11319 +       cfg->xport.entry[1].dport_start = 0;
11320 +       cfg->xport.entry[1].dport_end = 0;
11321 +
11322 +       // RAS Setup
11323 +       cfg->xport.entry[2].protocol = IPPROTO_UDP;
11324 +       cfg->xport.entry[2].sport_start = 0;
11325 +       cfg->xport.entry[2].sport_end = 0;
11326 +       cfg->xport.entry[2].dport_start = 1719;
11327 +       cfg->xport.entry[2].dport_end = 1719;
11328 +       cfg->xport.entry[3].protocol = IPPROTO_UDP;
11329 +       cfg->xport.entry[3].sport_start = 1719;
11330 +       cfg->xport.entry[3].sport_end = 1719;
11331 +       cfg->xport.entry[3].dport_start = 0;
11332 +       cfg->xport.entry[3].dport_end = 0;
11333 +#endif
11334 +
11335 +#ifdef CONFIG_SL351x_NAT_TCP_UDP
11336 +       mrxcr0.bits32 = 0;
11337 +       mrxcr1.bits32 = 0;
11338 +       mrxcr2.bits32 = 0;
11339 +       mrxcr0.bits.port = 1;
11340 +       mrxcr0.bits.l3 = 1;
11341 +       mrxcr0.bits.l4 = 1;
11342 +       mrxcr1.bits.sip = 1;
11343 +       mrxcr1.bits.dip = 1;
11344 +       mrxcr1.bits.l4_byte0_15 = 0x0f; // Byte 0-3
11345 +       mrxcr0.bits.sprx = 3;
11346 +
11347 +       rc = mac_set_rule_reg(cfg->lan_port, cfg->tcp_udp_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
11348 +       if (rc < 0)
11349 +       {
11350 +               nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->lan_port, cfg->tcp_udp_rule_id);
11351 +       }
11352 +
11353 +       if (cfg->lan_port != cfg->wan_port)
11354 +       {
11355 +               rc = mac_set_rule_reg(cfg->wan_port, cfg->tcp_udp_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
11356 +               if (rc < 0)
11357 +               {
11358 +                       nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->wan_port, cfg->tcp_udp_rule_id);
11359 +               }
11360 +       }
11361 +#endif
11362 +
11363 +#ifdef CONFIG_SL351x_NAT_GRE
11364 +       mrxcr0.bits32 = 0;
11365 +       mrxcr1.bits32 = 0;
11366 +       mrxcr2.bits32 = 0;
11367 +       mrxcr0.bits.port = 1;
11368 +       mrxcr0.bits.l3 = 1;
11369 +       mrxcr0.bits.l4 = 1;
11370 +       mrxcr1.bits.sip = 1;
11371 +       mrxcr1.bits.dip = 1;
11372 +       mrxcr1.bits.l4_byte0_15 = 0xcc; // Byte 2, 3, 6, 7
11373 +       mrxcr0.bits.sprx = 4;                   // see GMAC driver about SPR
11374 +
11375 +       rc = mac_set_rule_reg(cfg->lan_port, cfg->gre_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
11376 +       if (rc < 0)
11377 +       {
11378 +               nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->lan_port, cfg->gre_rule_id);
11379 +       }
11380 +
11381 +       if (cfg->lan_port != cfg->wan_port)
11382 +       {
11383 +               rc = mac_set_rule_reg(cfg->wan_port, cfg->gre_rule_id, 1, mrxcr0.bits32, mrxcr1.bits32, mrxcr2.bits32);
11384 +               if (rc < 0)
11385 +               {
11386 +                       nat_printf("NAT Failed to set MAC-%d Rule %d!\n", cfg->wan_port, cfg->gre_rule_id);
11387 +               }
11388 +       }
11389 +#endif
11390 +
11391 +#ifdef SL351x_NAT_TEST_BY_SMARTBITS
11392 +       nat_init_test_entry();
11393 +#endif
11394 +}
11395 +
11396 +/*----------------------------------------------------------------------
11397 +* nat_build_keys
11398 +*      Note: To call this routine, the key->rule_id MUST be zero
11399 +*----------------------------------------------------------------------*/
11400 +static inline int nat_build_keys(NAT_KEY_T *key)
11401 +{
11402 +       return hash_gen_crc16((unsigned char *)key, NAT_KEY_SIZE) & HASH_BITS_MASK;
11403 +}
11404 +
11405 +/*----------------------------------------------------------------------
11406 +* gre_build_keys
11407 +*      Note: To call this routine, the key->rule_id MUST be zero
11408 +*----------------------------------------------------------------------*/
11409 +static inline int gre_build_keys(GRE_KEY_T *key)
11410 +{
11411 +       return hash_gen_crc16((unsigned char *)key, GRE_KEY_SIZE) & HASH_BITS_MASK;
11412 +}
11413 +
11414 +/*----------------------------------------------------------------------
11415 +* nat_write_hash_entry
11416 +*----------------------------------------------------------------------*/
11417 +static inline int nat_write_hash_entry(int index, void *hash_entry)
11418 +{
11419 +       int             i;
11420 +       u32             *srcep, *destp, *destp2;
11421 +
11422 +       srcep = (u32 *)hash_entry;
11423 +       destp = destp2 = (u32 *)&hash_tables[index][0];
11424 +
11425 +       for (i=0; i<(NAT_HASH_ENTRY_SIZE/sizeof(u32)); i++)
11426 +               *destp++ = *srcep++;
11427 +
11428 +       consistent_sync(destp2, NAT_HASH_ENTRY_SIZE, PCI_DMA_TODEVICE);
11429 +       return 0;
11430 +}
11431 +
11432 +/*----------------------------------------------------------------------
11433 +* gre_write_hash_entry
11434 +*----------------------------------------------------------------------*/
11435 +static inline int gre_write_hash_entry(int index, void *hash_entry)
11436 +{
11437 +       int             i;
11438 +       u32             *srcep, *destp, *destp2;
11439 +
11440 +       srcep = (u32 *)hash_entry;
11441 +       destp = destp2 = (u32 *)&hash_tables[index][0];
11442 +
11443 +       for (i=0; i<(GRE_HASH_ENTRY_SIZE/sizeof(u32)); i++)
11444 +               *destp++ = *srcep++;
11445 +
11446 +       consistent_sync(destp2, GRE_HASH_ENTRY_SIZE, PCI_DMA_TODEVICE);
11447 +       return 0;
11448 +}
11449 +
11450 +/*----------------------------------------------------------------------
11451 +* sl351x_nat_find_ipcfg
11452 +*      return NULL if not found
11453 +*----------------------------------------------------------------------*/
11454 +static NAT_IP_ENTRY_T *sl351x_nat_find_ipcfg(u32 ipaddr, int port)
11455 +{
11456 +       int                             i;
11457 +       NAT_IP_ENTRY_T  *ipcfg;
11458 +
11459 +       ipcfg = (NAT_IP_ENTRY_T *)&nat_cfg.ipcfg[port].entry[0];
11460 +       for (i=0; i<nat_cfg.ipcfg[port].total; i++, ipcfg++)
11461 +       {
11462 +               if (ipaddr == ipcfg->ipaddr)
11463 +               {
11464 +                       return ipcfg;
11465 +               }
11466 +       }
11467 +       return NULL;
11468 +}
11469 +
11470 +/*----------------------------------------------------------------------
11471 +* sl351x_nat_assign_qid
11472 +*----------------------------------------------------------------------*/
11473 +static int sl351x_nat_assign_qid(u8 proto, u32 sip, u32 dip, u16 sport, u16 dport)
11474 +{
11475 +       int                             i, total, qid;
11476 +       NAT_WRULE_ENTRY_T       *entry;
11477 +
11478 +       for (qid = 0; qid<CONFIG_NAT_TXQ_NUM; qid++)
11479 +       {
11480 +               if (qid == nat_cfg.default_hw_txq)
11481 +                       continue;
11482 +
11483 +               entry = (NAT_WRULE_ENTRY_T *)&nat_cfg.wrule[qid].entry[0];
11484 +               total = nat_cfg.wrule[qid].total;
11485 +               for (i=0; i<total; i++, entry++)
11486 +               {
11487 +                       if (!entry->protocol || entry->protocol==proto)
11488 +                       {
11489 +                               //if (!entry->sip_start && !entry->dip_start && !entry->sport_start && !entry->dport_start)
11490 +                               //      continue; // UI take care
11491 +                               if (entry->sip_start && !((sip >= entry->sip_start) &&
11492 +                                                                          (sip <= entry->sip_end)))
11493 +                                       continue;
11494 +                               if (entry->dip_start && !((dip >= entry->dip_start) &&
11495 +                                                                          (dip <= entry->dip_end)))
11496 +                                       continue;
11497 +                               if (entry->sport_start && !((sport >= entry->sport_start) &&
11498 +                                                                          (sport <= entry->sport_end)))
11499 +                                       continue;
11500 +                               if (entry->dport_start && !((dport >= entry->dport_start)
11501 +                                                                      && (dport <= entry->dport_end)))
11502 +                                       continue;
11503 +                               return qid;
11504 +                       }
11505 +               }
11506 +       }
11507 +       return nat_cfg.default_hw_txq;
11508 +}
11509 +
11510 +/*----------------------------------------------------------------------
11511 +* sl351x_nat_input
11512 +*      Handle NAT input frames
11513 +*      Called by SL351x Driver - Handle Default Rx Queue
11514 +*      Notes: The caller must make sure that the l3off & l4offset should not be zero.
11515 +*      SL351x NAT Frames should meet the following conditions:
11516 +*      1. TCP or UDP frame
11517 +*      2. Cannot be special ALGs ports which TCP/UDP data is updated
11518 +*      3. LAN-IN Frames:
11519 +*              Source IP is in the LAN subnet and Destination is not in the LAN subnet
11520 +*      4. WAN-IN Frames
11521 +*              Destination IP is in the WAN port IP
11522 +*
11523 +*      Example Ports
11524 +*      1. TCP/UDP data is updated
11525 +*              (a) FTP Control Packet
11526 +*              (b) VoIP Packets
11527 +*              (c) etc. (add in future)
11528 +*      2. UDP Low packet rate, not worth
11529 +*              (b) TFTP Destination Port is 69
11530 +*              (b) DNS  53
11531 +*              (c) NTP  123
11532 +*              (d) etc. (add in future)
11533 +*----------------------------------------------------------------------*/
11534 +void sl351x_nat_input(struct sk_buff *skb, int port, void *l3off, void *l4off)
11535 +{
11536 +       int                             i, found;
11537 +       u32                                     sip, dip;
11538 +       u16                                     sport, dport;
11539 +       struct ethhdr           *ether_hdr;
11540 +       struct iphdr            *ip_hdr;
11541 +       struct tcphdr           *tcp_hdr;
11542 +       struct pppoe_hdr        *pppoe_hdr;
11543 +       NAT_CB_T                        *nat_cb;
11544 +       u8                                      proto, pppoe_frame=0;
11545 +       NAT_CFG_T                       *cfg;
11546 +       u16                                     ppp_proto;
11547 +       NAT_IP_ENTRY_T          *ipcfg;
11548 +       NAT_XPORT_ENTRY_T       *xentry;
11549 +       GRE_PKTHDR_T            *gre_hdr;
11550 +#ifdef CONFIG_SL351x_NAT_TCP_UDP
11551 +       u16                             *port_ptr;
11552 +#endif
11553 +
11554 +       cfg = (NAT_CFG_T *)&nat_cfg;
11555 +       if (!cfg->enabled || !cfg->ipcfg[port].total)
11556 +               return;
11557 +
11558 +       ip_hdr = (struct iphdr *)&(skb->data[(u32)l3off]);
11559 +       proto = ip_hdr->protocol;
11560 +
11561 +       tcp_hdr = (struct tcphdr *)&(skb->data[(u32)l4off]);
11562 +       gre_hdr = (GRE_PKTHDR_T *)tcp_hdr;
11563 +       sport = ntohs(tcp_hdr->source);
11564 +       dport = ntohs(tcp_hdr->dest);
11565 +
11566 +       sip = ntohl(ip_hdr->saddr);
11567 +       dip = ntohl(ip_hdr->daddr);
11568 +
11569 +       if (dip == IPIV(255,255,255,255))
11570 +               return;
11571 +
11572 +       if (port == cfg->lan_port)
11573 +       {
11574 +               ipcfg = (NAT_IP_ENTRY_T *)&cfg->ipcfg[port].entry[0];
11575 +               for (i=0, found=0; i<cfg->ipcfg[port].total; i++, ipcfg++)
11576 +               {
11577 +                       u32 subnet = ipcfg->ipaddr & ipcfg->netmask;
11578 +                       if (((sip & ipcfg->netmask) == subnet) &&
11579 +                               ((dip & ipcfg->netmask) != subnet))
11580 +                       {
11581 +                               found = 1;
11582 +                               break;
11583 +                       }
11584 +               }
11585 +               if (!found)
11586 +                       return;
11587 +       }
11588 +       else
11589 +       {
11590 +#ifndef _NOT_CHECK_SIP_DIP     // enable it if know and get the wan ip address
11591 +               if (!sl351x_nat_find_ipcfg(dip, port))
11592 +               {
11593 +                       printk("WAN->LAN Incorrect Dip %d.%d.%d.%d\n", HIPQUAD(dip));
11594 +                       return;
11595 +               }
11596 +#endif
11597 +               ether_hdr = (struct ethhdr *)skb->data;
11598 +               pppoe_hdr = (struct pppoe_hdr *)(ether_hdr + 1);
11599 +               ppp_proto = *(u16 *)&pppoe_hdr->tag[0];
11600 +               if (ether_hdr->h_proto == __constant_htons(ETH_P_PPP_SES)       // 0x8864
11601 +                       && ppp_proto == __constant_htons(PPP_IP) )                              // 0x21
11602 +               {
11603 +                       pppoe_frame = 1;
11604 +               }
11605 +       }
11606 +
11607 +#ifdef CONFIG_SL351x_NAT_TCP_UDP
11608 +       if (proto == IPPROTO_TCP)
11609 +       {
11610 +#ifdef NAT_DEBUG_MSG
11611 +               nat_printf("From   GMAC-%d: 0x%-4X TCP %d.%d.%d.%d [%d] --> %d.%d.%d.%d [%d]",
11612 +                               port, ntohs(ip_hdr->id),
11613 +                               NIPQUAD(ip_hdr->saddr), sport,
11614 +                               NIPQUAD(ip_hdr->daddr), dport);
11615 +               if (tcp_flag_word(tcp_hdr) & TCP_FLAG_SYN) nat_printf(" SYN");
11616 +               if (tcp_flag_word(tcp_hdr) & TCP_FLAG_FIN) nat_printf(" FIN");
11617 +               if (tcp_flag_word(tcp_hdr) & TCP_FLAG_RST) nat_printf(" RST");
11618 +               if (tcp_flag_word(tcp_hdr) & TCP_FLAG_ACK) nat_printf(" ACK");
11619 +               nat_printf("\n");
11620 +#endif
11621 +               // if (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN | TCP_FLAG_FIN | TCP_FLAG_RST))
11622 +               if (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN))
11623 +               {
11624 +                       return;
11625 +               }
11626 +               port_ptr = fixed_tcp_port_list;
11627 +               for (i=0; *port_ptr; i++, port_ptr++)
11628 +               {
11629 +                       if (sport == *port_ptr || dport == *port_ptr)
11630 +                               return;
11631 +               }
11632 +#ifdef _HAVE_DYNAMIC_PORT_LIST
11633 +               port_ptr = dynamic_tcp_port_list;
11634 +               for (i=0; *port_ptr; i++, port_ptr++)
11635 +               {
11636 +                       if (sport == *port_ptr || dport == *port_ptr)
11637 +                               return;
11638 +               }
11639 +#endif
11640 +       }
11641 +       else if (proto == IPPROTO_UDP)
11642 +       {
11643 +#ifdef NAT_DEBUG_MSG
11644 +               nat_printf("From   GMAC-%d: 0x%-4X UDP %d.%d.%d.%d [%d] --> %d.%d.%d.%d [%d]",
11645 +                               port, ntohs(ip_hdr->id),
11646 +                               NIPQUAD(ip_hdr->saddr), sport,
11647 +                               NIPQUAD(ip_hdr->daddr), dport);
11648 +               nat_printf("\n");
11649 +#endif
11650 +               port_ptr = fixed_udp_port_list;
11651 +               for (i=0; *port_ptr; i++, port_ptr++)
11652 +               {
11653 +                       if (sport == *port_ptr || dport == *port_ptr)
11654 +                               return;
11655 +               }
11656 +#ifdef _HAVE_DYNAMIC_PORT_LIST
11657 +               port_ptr = dynamic_udp_port_list;
11658 +               for (i=0; *port_ptr; i++, port_ptr++)
11659 +               {
11660 +                       if (sport == *port_ptr || dport == *port_ptr)
11661 +                               return;
11662 +               }
11663 +#endif
11664 +       }
11665 +       else
11666 +#endif // CONFIG_SL351x_NAT_TCP_UDP
11667 +#ifdef CONFIG_SL351x_NAT_GRE
11668 +       if (proto == IPPROTO_GRE)
11669 +       {
11670 +               if (gre_hdr->protocol != GRE_PROTOCOL_SWAP)
11671 +                       return;
11672 +#ifdef NAT_DEBUG_MSG
11673 +               nat_printf("From   GMAC-%d: 0x%-4X GRE %d.%d.%d.%d [%d] --> %d.%d.%d.%d",
11674 +                               port, ntohs(ip_hdr->id),
11675 +                               NIPQUAD(ip_hdr->saddr), ntohs(gre_hdr->call_id),
11676 +                               NIPQUAD(ip_hdr->daddr));
11677 +               nat_printf("\n");
11678 +#endif
11679 +       }
11680 +       else
11681 +#endif
11682 +               return;
11683 +
11684 +
11685 +       // check xport list
11686 +       xentry = (NAT_XPORT_ENTRY_T *)&cfg->xport.entry[0];
11687 +       for (i=0; i<cfg->xport.total; i++, xentry++)
11688 +       {
11689 +               if (!xentry->protocol || xentry->protocol == proto)
11690 +               {
11691 +                       //if (!xentry->sport_start && !xentry->dport_start) // UI take care
11692 +                       //      continue;
11693 +                       if (xentry->sport_start && !((sport >= xentry->sport_start) &&
11694 +                                                                          (sport <= xentry->sport_end)))
11695 +                               continue;
11696 +                       if (xentry->dport_start && !((dport >= xentry->dport_start)
11697 +                                                                      && (dport <= xentry->dport_end)))
11698 +                               continue;
11699 +                       return;
11700 +               }
11701 +       }
11702 +
11703 +       nat_cb = NAT_SKB_CB(skb);
11704 +       if (((u32)nat_cb & 3))
11705 +       {
11706 +               nat_printf("%s ERROR! nat_cb is not alignment!!!!!!\n", __func__);
11707 +               return;
11708 +       }
11709 +       nat_cb->tag = NAT_CB_TAG;
11710 +       memcpy(nat_cb->sa, skb->data+6, 6);
11711 +       nat_cb->sip = ip_hdr->saddr;
11712 +       nat_cb->dip = ip_hdr->daddr;
11713 +       if (proto == IPPROTO_GRE)
11714 +       {
11715 +               nat_cb->sport = gre_hdr->protocol;
11716 +               nat_cb->dport = gre_hdr->call_id;
11717 +       }
11718 +       else
11719 +       {
11720 +               nat_cb->sport = tcp_hdr->source;
11721 +               nat_cb->dport = tcp_hdr->dest;
11722 +       }
11723 +       nat_cb->pppoe_frame = pppoe_frame;
11724 +}
11725 +
11726 +/*----------------------------------------------------------------------
11727 +* sl351x_nat_output
11728 +*      Handle NAT output frames
11729 +*      Called by SL351x Driver - Transmit
11730 +*
11731 +*      1. If not SL351x NAT frames, return FALSE
11732 +*      2. LAN-to-WAN frames
11733 +*              (1) Sip must be WAN IP
11734 +*      3. If TCP SY/RST/FIN frame, return
11735 +*      4. Build the hash key and get the hash index
11736 +*      5. If V-Bit is ON, return.
11737 +*      6. Write hash entry and validate it
11738 +*
11739 +*----------------------------------------------------------------------*/
11740 +int sl351x_nat_output(struct sk_buff *skb, int port)
11741 +{
11742 +       struct iphdr            *ip_hdr;
11743 +       u8                                      proto;
11744 +       NAT_CB_T                        *nat_cb;
11745 +
11746 +       nat_cb = NAT_SKB_CB(skb);
11747 +       if (nat_cb->tag != NAT_CB_TAG)
11748 +               return 0;
11749 +
11750 +       if (((u32)nat_cb & 3))
11751 +       {
11752 +               nat_printf("%s ERROR! nat_cb is not alignment!!!!!!\n", __func__);
11753 +               return 0;
11754 +       }
11755 +       ip_hdr = (struct iphdr *)skb->h.ipiph;
11756 +       proto = ip_hdr->protocol;
11757 +
11758 +       switch (proto)
11759 +       {
11760 +               case IPPROTO_TCP:
11761 +               case IPPROTO_UDP:
11762 +                       return sl351x_nat_tcp_udp_output(skb, port);
11763 +               case IPPROTO_GRE:
11764 +                       return sl351x_nat_gre_output(skb, port);
11765 +       }
11766 +       return 0;
11767 +}
11768 +
11769 +/*----------------------------------------------------------------------
11770 +* sl351x_nat_tcp_udp_output
11771 +*      Handle NAT TCP/UDP output frames
11772 +*----------------------------------------------------------------------*/
11773 +int sl351x_nat_tcp_udp_output(struct sk_buff *skb, int port)
11774 +{
11775 +       u32                                     sip, dip;
11776 +       struct ethhdr           *ether_hdr;
11777 +       struct iphdr            *ip_hdr;
11778 +       struct tcphdr           *tcp_hdr;
11779 +       struct pppoe_hdr        *pppoe_hdr;
11780 +       NAT_CB_T                        *nat_cb;
11781 +       NAT_CFG_T                       *cfg;
11782 +       u8                                      proto;
11783 +       u16                                     sport, dport, ppp_proto;
11784 +       u32                                     hash_data[HASH_MAX_DWORDS];
11785 +       NAT_HASH_ENTRY_T        *hash_entry;
11786 +       int                                     hash_index;
11787 +       struct ip_conntrack *nat_ip_conntrack;
11788 +       enum ip_conntrack_info ctinfo;
11789 +
11790 +       nat_cb = NAT_SKB_CB(skb);
11791 +       cfg = (NAT_CFG_T *)&nat_cfg;
11792 +
11793 +       ether_hdr = (struct ethhdr *)skb->data;
11794 +       ip_hdr = (struct iphdr *)skb->h.ipiph;
11795 +       tcp_hdr = (struct tcphdr *)((u32)ip_hdr + (ip_hdr->ihl<<2));
11796 +       sip = ntohl(ip_hdr->saddr);
11797 +       dip = ntohl(ip_hdr->daddr);
11798 +       proto = ip_hdr->protocol;
11799 +       sport = ntohs(tcp_hdr->source);
11800 +       dport = ntohs(tcp_hdr->dest);
11801 +
11802 +#ifdef NAT_DEBUG_MSG
11803 +       {
11804 +               nat_printf("To   GMAC-%d: 0x%-4X [%d] %d.%d.%d.%d [%d] --> %d.%d.%d.%d [%d]",
11805 +                               port, ntohs(ip_hdr->id), proto,
11806 +                               NIPQUAD(ip_hdr->saddr), sport,
11807 +                               NIPQUAD(ip_hdr->daddr), dport);
11808 +               if (proto == IPPROTO_TCP)
11809 +               {
11810 +                       if (tcp_flag_word(tcp_hdr) & TCP_FLAG_SYN) nat_printf(" SYN");
11811 +                       if (tcp_flag_word(tcp_hdr) & TCP_FLAG_FIN) nat_printf(" FIN");
11812 +                       if (tcp_flag_word(tcp_hdr) & TCP_FLAG_RST) nat_printf(" RST");
11813 +                       if (tcp_flag_word(tcp_hdr) & TCP_FLAG_ACK) nat_printf(" ACK");
11814 +               }
11815 +               nat_printf("\n");
11816 +       }
11817 +#endif
11818 +       nat_ip_conntrack = ip_conntrack_get(skb, &ctinfo);
11819 +       if (!nat_ip_conntrack)
11820 +       {
11821 +               nat_printf("IP conntrack info is not found!\n");
11822 +               return 0;
11823 +       }
11824 +       // nat_printf("nat_ip_conntrack = 0x%x, status=0x%lx, ctinfo=%d\n", (u32)nat_ip_conntrack, nat_ip_conntrack->status, ctinfo);
11825 +       // if (nat_ip_conntrack->master || nat_ip_conntrack->helper)
11826 +       if (nat_ip_conntrack->helper)
11827 +       {
11828 +               nat_printf("Sport=%d Dport=%d master=0x%x, helper=0x%x\n", sport, dport, (u32)nat_ip_conntrack->master, (u32)nat_ip_conntrack->helper);
11829 +               return 0;
11830 +       }
11831 +
11832 +       //if (proto == IPPROTO_TCP && !(nat_ip_conntrack->status & IPS_ASSURED))
11833 +       //      return 0;
11834 +
11835 +#ifdef NAT_DEBUG_MSG
11836 +       nat_printf("nat_ip_conntrack=0x%x, nat_cb->state=%d\n", (u32)nat_ip_conntrack, nat_cb->state);
11837 +       nat_printf("lan2wan_hash_index=%d,  wan2lan_hash_index=%d\n", nat_ip_conntrack->lan2wan_hash_index, nat_ip_conntrack->wan2lan_hash_index);
11838 +       nat_printf("lan2wan_collision=%d, wan2lan_collision=%d\n", nat_ip_conntrack->lan2wan_collision, nat_ip_conntrack->wan2lan_collision);
11839 +#endif
11840 +       if (proto == IPPROTO_TCP)
11841 +       {
11842 +               if (nat_cb->state >= TCP_CONNTRACK_FIN_WAIT && nat_cb->state <= TCP_CONNTRACK_CLOSE)
11843 +               {
11844 +                       if      (nat_ip_conntrack->lan2wan_hash_index)
11845 +                       {
11846 +#ifdef NAT_DEBUG_MSG
11847 +                               nat_printf("Invalidate LAN->WAN hash entry %d\n", nat_ip_conntrack->lan2wan_hash_index - 1);
11848 +#endif
11849 +                               hash_nat_disable_owner(nat_ip_conntrack->lan2wan_hash_index - 1);
11850 +                               hash_invalidate_entry(nat_ip_conntrack->lan2wan_hash_index - 1);
11851 +                               nat_ip_conntrack->lan2wan_hash_index = 0;
11852 +                       }
11853 +                       if      (nat_ip_conntrack->wan2lan_hash_index)
11854 +                       {
11855 +#ifdef NAT_DEBUG_MSG
11856 +                               nat_printf("Invalidate WAN->LAN hash entry %d\n", nat_ip_conntrack->wan2lan_hash_index - 1);
11857 +#endif
11858 +                               hash_nat_disable_owner(nat_ip_conntrack->wan2lan_hash_index - 1);
11859 +                               hash_invalidate_entry(nat_ip_conntrack->wan2lan_hash_index - 1);
11860 +                               nat_ip_conntrack->wan2lan_hash_index = 0;
11861 +                       }
11862 +                       return 0;
11863 +
11864 +               }
11865 +               else if (nat_cb->state != TCP_CONNTRACK_ESTABLISHED)
11866 +               {
11867 +                       return 0;
11868 +               }
11869 +       }
11870 +       if (proto == IPPROTO_TCP && (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN | TCP_FLAG_FIN | TCP_FLAG_RST)))
11871 +       // if (proto == IPPROTO_TCP &&  (tcp_flag_word(tcp_hdr) & (TCP_FLAG_SYN)))
11872 +               return 0;
11873 +
11874 +       hash_entry = (NAT_HASH_ENTRY_T *)&hash_data;
11875 +       if (port == cfg->wan_port)      // LAN-to-WAN
11876 +       {
11877 +               if (nat_ip_conntrack->lan2wan_hash_index || nat_ip_conntrack->lan2wan_collision)
11878 +                       return 0;
11879 +#ifndef _NOT_CHECK_SIP_DIP     // enable it if know and get the wan ip address
11880 +               if (!sl351x_nat_find_ipcfg(sip, port))
11881 +               {
11882 +                       printk("LAN->WAN Incorrect Sip %d.%d.%d.%d\n", HIPQUAD(sip));
11883 +                       return 0;
11884 +               }
11885 +#endif
11886 +               // Note: unused fields (including rule_id) MUST be zero
11887 +               hash_entry->key.Ethertype       = 0;
11888 +               hash_entry->key.port_id         = cfg->lan_port;
11889 +               hash_entry->key.rule_id         = 0;
11890 +               hash_entry->key.ip_protocol = proto;
11891 +               hash_entry->key.reserved1       = 0;
11892 +               hash_entry->key.reserved2       = 0;
11893 +               hash_entry->key.sip             = ntohl(nat_cb->sip);
11894 +               hash_entry->key.dip             = ntohl(nat_cb->dip);
11895 +               hash_entry->key.sport           = nat_cb->sport;
11896 +               hash_entry->key.dport           = nat_cb->dport;
11897 +
11898 +               hash_index = nat_build_keys(&hash_entry->key);
11899 +
11900 +#ifdef NAT_DEBUG_LAN_HASH_TIMEOUT
11901 +               if (hash_get_nat_owner_flag(hash_index))
11902 +                       return 0;
11903 +#endif
11904 +               if (hash_get_valid_flag(hash_index))
11905 +               {
11906 +                       nat_ip_conntrack->lan2wan_collision = 1;
11907 +                       nat_collision++;
11908 +#if 0
11909 +                       if (proto == IPPROTO_TCP && (tcp_flag_word(tcp_hdr) & (TCP_FLAG_FIN | TCP_FLAG_RST)))
11910 +                       {
11911 +                               if (memcmp((void *)&hash_entry->key, hash_get_entry(hash_index), sizeof(NAT_KEY_T)) == 0)
11912 +                               {
11913 +                                       hash_nat_disable_owner(hash_index);
11914 +                                       hash_invalidate_entry(hash_index); // Must last one, else HW Tx fast SW
11915 +                                       // nat_printf("Invalidate nat hash entry %d\n", hash_index);
11916 +                               }
11917 +                       }
11918 +#endif
11919 +                       return 0;
11920 +               }
11921 +
11922 +               // write hash entry
11923 +               hash_entry->key.rule_id = cfg->tcp_udp_rule_id;
11924 +               memcpy(hash_entry->param.da, skb->data, 6);
11925 +               memcpy(hash_entry->param.sa, skb->data+6, 6);
11926 +               hash_entry->param.Sip = sip;
11927 +               hash_entry->param.Dip = dip;
11928 +               hash_entry->param.Sport = sport;
11929 +               hash_entry->param.Dport = dport;
11930 +               hash_entry->param.vlan = 0;
11931 +               hash_entry->param.sw_id = 0;
11932 +               hash_entry->param.mtu = 0;
11933 +               // check PPPoE
11934 +               pppoe_hdr = (struct pppoe_hdr *)(ether_hdr + 1);
11935 +               ppp_proto = *(u16 *)&pppoe_hdr->tag[0];
11936 +               if (ether_hdr->h_proto == __constant_htons(ETH_P_PPP_SES)       // 0x8864
11937 +                       && ppp_proto == __constant_htons(PPP_IP) )                              // 0x21
11938 +               {
11939 +                       hash_entry->action.dword = NAT_PPPOE_LAN2WAN_ACTIONS;
11940 +                       hash_entry->param.pppoe = htons(pppoe_hdr->sid);
11941 +               }
11942 +               else
11943 +               {
11944 +                       hash_entry->action.dword = NAT_LAN2WAN_ACTIONS;
11945 +                       hash_entry->param.pppoe = 0;
11946 +               }
11947 +               hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(proto, sip, dip, sport, dport);
11948 +               hash_entry->action.bits.dest_qid +=     (cfg->wan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
11949 +               hash_entry->tmo.counter = hash_entry->tmo.interval =
11950 +                                               (proto == IPPROTO_TCP) ? cfg->tcp_tmo_interval : cfg->udp_tmo_interval;
11951 +               nat_write_hash_entry(hash_index, hash_entry);
11952 +               // nat_printf("%lu Validate a LAN hash entry %d\n", jiffies/HZ, hash_index);
11953 +               // hash_dump_entry(hash_index);
11954 +               hash_nat_enable_owner(hash_index);
11955 +               hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
11956 +               nat_ip_conntrack->lan2wan_hash_index = hash_index + 1;
11957 +               nat_ip_conntrack->hw_nat |= 1;
11958 +               return 0;
11959 +       }
11960 +       else // WAN-to-LAN
11961 +       {
11962 +               if (nat_ip_conntrack->wan2lan_hash_index || nat_ip_conntrack->wan2lan_collision)
11963 +                       return 0;
11964 +
11965 +               // Note: unused fields (including rule_id) MUST be zero
11966 +               hash_entry->key.Ethertype       = 0;
11967 +               hash_entry->key.port_id         = cfg->wan_port;
11968 +               hash_entry->key.rule_id         = 0;
11969 +               hash_entry->key.ip_protocol = proto;
11970 +               hash_entry->key.reserved1       = 0;
11971 +               hash_entry->key.reserved2       = 0;
11972 +               hash_entry->key.sip             = ntohl(nat_cb->sip);
11973 +               hash_entry->key.dip             = ntohl(nat_cb->dip);
11974 +               hash_entry->key.sport           = nat_cb->sport;
11975 +               hash_entry->key.dport           = nat_cb->dport;
11976 +
11977 +               hash_index = nat_build_keys(&hash_entry->key);
11978 +
11979 +#ifdef NAT_DEBUG_WAN_HASH_TIMEOUT
11980 +               if (hash_get_nat_owner_flag(hash_index))
11981 +                       return 0;
11982 +#endif
11983 +               if (hash_get_valid_flag(hash_index))
11984 +               {
11985 +                       nat_ip_conntrack->wan2lan_collision = 1;
11986 +                       nat_collision++;
11987 +#if 0
11988 +                       if (proto == IPPROTO_TCP && (tcp_flag_word(tcp_hdr) & (TCP_FLAG_FIN | TCP_FLAG_RST)))
11989 +                       {
11990 +                               if (memcmp((void *)&hash_entry->key, hash_get_entry(hash_index), sizeof(NAT_KEY_T)) == 0)
11991 +                               {
11992 +                                       hash_nat_disable_owner(hash_index);
11993 +                                       hash_invalidate_entry(hash_index); // Must last one, else HW Tx fast SW
11994 +                                       // nat_printf("Invalidate nat hash entry %d\n", hash_index);
11995 +                               }
11996 +                       }
11997 +#endif
11998 +                       return 0;
11999 +               }
12000 +
12001 +               // write hash entry
12002 +               hash_entry->key.rule_id = cfg->tcp_udp_rule_id;
12003 +               memcpy(hash_entry->param.da, skb->data, 6);
12004 +               memcpy(hash_entry->param.sa, skb->data+6, 6);
12005 +               hash_entry->param.Sip = sip;
12006 +               hash_entry->param.Dip = dip;
12007 +               hash_entry->param.Sport = sport;
12008 +               hash_entry->param.Dport = dport;
12009 +               hash_entry->param.vlan = 0;
12010 +               hash_entry->param.pppoe = 0;
12011 +               hash_entry->param.sw_id = 0;
12012 +               hash_entry->param.mtu = 0;
12013 +               hash_entry->action.dword = (nat_cb->pppoe_frame) ? NAT_PPPOE_WAN2LAN_ACTIONS : NAT_WAN2LAN_ACTIONS;
12014 +               hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(proto, sip, dip, sport, dport);
12015 +               hash_entry->action.bits.dest_qid += (cfg->lan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;;
12016 +               hash_entry->tmo.counter = hash_entry->tmo.interval =
12017 +                                               (proto == IPPROTO_TCP) ? cfg->tcp_tmo_interval : cfg->udp_tmo_interval;
12018 +               nat_write_hash_entry(hash_index, hash_entry);
12019 +
12020 +               // nat_printf("%lu Validate a WAN hash entry %d\n", jiffies/HZ, hash_index);
12021 +               // hash_dump_entry(hash_index);
12022 +               hash_nat_enable_owner(hash_index);
12023 +               hash_validate_entry(hash_index); // Must last one, else HW Tx fast SW
12024 +               nat_ip_conntrack->wan2lan_hash_index = hash_index + 1;
12025 +               nat_ip_conntrack->hw_nat |= 2;
12026 +               return 0;
12027 +       }
12028 +       return 0;
12029 +}
12030 +
12031 +/*----------------------------------------------------------------------
12032 +* sl351x_nat_gre_output
12033 +*      Handle NAT GRE output frames
12034 +*----------------------------------------------------------------------*/
12035 +int sl351x_nat_gre_output(struct sk_buff *skb, int port)
12036 +{
12037 +       u32                                     sip, dip;
12038 +       struct ethhdr           *ether_hdr;
12039 +       struct iphdr            *ip_hdr;
12040 +       struct pppoe_hdr        *pppoe_hdr;
12041 +       GRE_PKTHDR_T            *gre_hdr;
12042 +       NAT_CB_T                        *nat_cb;
12043 +       NAT_CFG_T                       *cfg;
12044 +       u16                                     ppp_proto;
12045 +       u32                                     hash_data[HASH_MAX_DWORDS];
12046 +       GRE_HASH_ENTRY_T        *hash_entry;
12047 +       int                                     hash_index;
12048 +       struct ip_conntrack *nat_ip_conntrack;
12049 +       enum ip_conntrack_info ctinfo;
12050 +
12051 +       nat_cb = NAT_SKB_CB(skb);
12052 +       cfg = (NAT_CFG_T *)&nat_cfg;
12053 +
12054 +       ether_hdr = (struct ethhdr *)skb->data;
12055 +       ip_hdr = (struct iphdr *)skb->h.ipiph;
12056 +       gre_hdr = (GRE_PKTHDR_T *)((u32)ip_hdr + (ip_hdr->ihl<<2));
12057 +       sip = ntohl(ip_hdr->saddr);
12058 +       dip = ntohl(ip_hdr->daddr);
12059 +
12060 +#ifdef NAT_DEBUG_MSG
12061 +       {
12062 +               nat_printf("To   GMAC-%d: 0x%-4X GRE %d.%d.%d.%d [%d] --> %d.%d.%d.%d",
12063 +                               port, ntohs(ip_hdr->id),
12064 +                               NIPQUAD(ip_hdr->saddr), ntohs(gre_hdr->call_id),
12065 +                               NIPQUAD(ip_hdr->daddr));
12066 +               nat_printf("\n");
12067 +       }
12068 +#endif
12069 +       nat_ip_conntrack = ip_conntrack_get(skb, &ctinfo);
12070 +       if (nat_ip_conntrack)
12071 +       {
12072 +               // if (nat_ip_conntrack->master || nat_ip_conntrack->helper)
12073 +               if (nat_ip_conntrack->helper)
12074 +               {
12075 +                       nat_printf("GRE Call-ID=%d, master=0x%x, helper=0x%x\n", ntohs(gre_hdr->call_id), (u32)nat_ip_conntrack->master, (u32)nat_ip_conntrack->helper);
12076 +                       return 0;
12077 +               }
12078 +               if (!(nat_ip_conntrack->status & IPS_ASSURED))
12079 +                       return 0;
12080 +       }
12081 +
12082 +       hash_entry = (GRE_HASH_ENTRY_T *)&hash_data;
12083 +       if (port == cfg->wan_port)      // LAN-to-WAN
12084 +       {
12085 +#ifdef _NOT_CHECK_SIP_DIP      // enable it if know and get the wan ip address
12086 +               if (!sl351x_nat_find_ipcfg(sip, port))
12087 +               {
12088 +                       printk("LAN->WAN Incorrect Sip %d.%d.%d.%d\n", HIPQUAD(sip));
12089 +                       return 0;
12090 +               }
12091 +#endif
12092 +               // Note: unused fields (including rule_id) MUST be zero
12093 +               hash_entry->key.Ethertype       = 0;
12094 +               hash_entry->key.port_id         = cfg->lan_port;
12095 +               hash_entry->key.rule_id         = 0;
12096 +               hash_entry->key.ip_protocol = IPPROTO_GRE;
12097 +               hash_entry->key.reserved1       = 0;
12098 +               hash_entry->key.reserved2       = 0;
12099 +               hash_entry->key.reserved3       = 0;
12100 +               hash_entry->key.reserved4       = 0;
12101 +               hash_entry->key.sip             = ntohl(nat_cb->sip);
12102 +               hash_entry->key.dip             = ntohl(nat_cb->dip);
12103 +               hash_entry->key.protocol        = nat_cb->sport;
12104 +               hash_entry->key.call_id         = nat_cb->dport;
12105 +
12106 +               hash_index = gre_build_keys(&hash_entry->key);
12107 +
12108 +#ifdef NAT_DEBUG_LAN_HASH_TIMEOUT
12109 +               if (hash_get_nat_owner_flag(hash_index))
12110 +                       return 0;
12111 +#endif
12112 +               if (hash_get_valid_flag(hash_index))
12113 +               {
12114 +                       return 0;
12115 +               }
12116 +
12117 +               // write hash entry
12118 +               hash_entry->key.rule_id = cfg->gre_rule_id;
12119 +               memcpy(hash_entry->param.da, skb->data, 6);
12120 +               memcpy(hash_entry->param.sa, skb->data+6, 6);
12121 +               hash_entry->param.Sip = sip;
12122 +               hash_entry->param.Dip = dip;
12123 +               hash_entry->param.Sport = 0;
12124 +               hash_entry->param.Dport = ntohs(gre_hdr->call_id);
12125 +               hash_entry->param.vlan = 0;
12126 +               hash_entry->param.sw_id = 0;
12127 +               hash_entry->param.mtu = 0;
12128 +               // check PPPoE
12129 +               pppoe_hdr = (struct pppoe_hdr *)(ether_hdr + 1);
12130 +               ppp_proto = *(u16 *)&pppoe_hdr->tag[0];
12131 +               if (ether_hdr->h_proto == __constant_htons(ETH_P_PPP_SES)       // 0x8864
12132 +                       && ppp_proto == __constant_htons(PPP_IP) )                              // 0x21
12133 +               {
12134 +                       hash_entry->action.dword = NAT_PPPOE_PPTP_LAN2WAN_ACTIONS;
12135 +                       hash_entry->param.pppoe = htons(pppoe_hdr->sid);
12136 +               }
12137 +               else
12138 +               {
12139 +                       hash_entry->action.dword = NAT_PPTP_LAN2WAN_ACTIONS;
12140 +                       hash_entry->param.pppoe = 0;
12141 +               }
12142 +               hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(IPPROTO_GRE, sip, dip, 0, ntohs(gre_hdr->call_id));
12143 +               hash_entry->action.bits.dest_qid +=     (cfg->wan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
12144 +               hash_entry->tmo.counter = hash_entry->tmo.interval = cfg->gre_tmo_interval;
12145 +               gre_write_hash_entry(hash_index, hash_entry);
12146 +               // nat_printf("%lu Validate a LAN hash entry %d\n", jiffies/HZ, hash_index);
12147 +               // hash_dump_entry(hash_index);
12148 +               hash_nat_enable_owner(hash_index);
12149 +               hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
12150 +               return 0;
12151 +       }
12152 +       else // WAN-to-LAN
12153 +       {
12154 +               // Note: unused fields (including rule_id) MUST be zero
12155 +               hash_entry->key.Ethertype       = 0;
12156 +               hash_entry->key.port_id         = cfg->wan_port;
12157 +               hash_entry->key.rule_id         = 0;
12158 +               hash_entry->key.ip_protocol = IPPROTO_GRE;
12159 +               hash_entry->key.reserved1       = 0;
12160 +               hash_entry->key.reserved2       = 0;
12161 +               hash_entry->key.reserved3       = 0;
12162 +               hash_entry->key.reserved4       = 0;
12163 +               hash_entry->key.sip             = ntohl(nat_cb->sip);
12164 +               hash_entry->key.dip             = ntohl(nat_cb->dip);
12165 +               hash_entry->key.protocol        = nat_cb->sport;
12166 +               hash_entry->key.call_id         = nat_cb->dport;
12167 +
12168 +               hash_index = gre_build_keys(&hash_entry->key);
12169 +
12170 +#ifdef NAT_DEBUG_WAN_HASH_TIMEOUT
12171 +               if (hash_get_nat_owner_flag(hash_index))
12172 +                       return 0;
12173 +#endif
12174 +               if (hash_get_valid_flag(hash_index))
12175 +               {
12176 +                       return 0;
12177 +               }
12178 +
12179 +               // write hash entry
12180 +               hash_entry->key.rule_id = cfg->gre_rule_id;
12181 +               memcpy(hash_entry->param.da, skb->data, 6);
12182 +               memcpy(hash_entry->param.sa, skb->data+6, 6);
12183 +               hash_entry->param.Sip = sip;
12184 +               hash_entry->param.Dip = dip;
12185 +               hash_entry->param.Sport = 0;
12186 +               hash_entry->param.Dport = ntohs(gre_hdr->call_id);
12187 +               hash_entry->param.vlan = 0;
12188 +               hash_entry->param.pppoe = 0;
12189 +               hash_entry->param.sw_id = 0;
12190 +               hash_entry->param.mtu = 0;
12191 +               hash_entry->action.dword = (nat_cb->pppoe_frame) ? NAT_PPPOE_PPTP_WAN2LAN_ACTIONS : NAT_PPTP_WAN2LAN_ACTIONS;
12192 +               hash_entry->action.bits.dest_qid = sl351x_nat_assign_qid(IPPROTO_GRE, sip, dip, 0, ntohs(gre_hdr->call_id));
12193 +               hash_entry->action.bits.dest_qid += (cfg->lan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;;
12194 +               hash_entry->tmo.counter = hash_entry->tmo.interval = cfg->gre_tmo_interval;
12195 +               gre_write_hash_entry(hash_index, hash_entry);
12196 +
12197 +               // nat_printf("%lu Validate a WAN hash entry %d\n", jiffies/HZ, hash_index);
12198 +               // hash_dump_entry(hash_index);
12199 +               hash_nat_enable_owner(hash_index);
12200 +               hash_validate_entry(hash_index); // Must last one, else HW Tx fast SW
12201 +               return 0;
12202 +       }
12203 +       return 0;
12204 +}
12205 +
12206 +
12207 +#ifdef _HAVE_DYNAMIC_PORT_LIST
12208 +/*----------------------------------------------------------------------
12209 +* sl_nat_add_port
12210 +*----------------------------------------------------------------------*/
12211 +void sl_nat_add_port(u8 protocol, u16 port)
12212 +{
12213 +       int     i;
12214 +       u16             *port_ptr;
12215 +
12216 +       if (protocol == IPPROTO_TCP)
12217 +               port_ptr = dynamic_tcp_port_list;
12218 +       else if (protocol == IPPROTO_UDP)
12219 +               port_ptr = dynamic_udp_port_list;
12220 +       else
12221 +               return;
12222 +
12223 +       for (i=0; *port_ptr; i++)
12224 +       {
12225 +               if (port == *port_ptr)
12226 +                       return;
12227 +               port_ptr++;
12228 +       }
12229 +       port_ptr++;
12230 +       *port_ptr = port;
12231 +}
12232 +
12233 +/*----------------------------------------------------------------------
12234 +* sl_nat_remove_port
12235 +*----------------------------------------------------------------------*/
12236 +void sl_nat_remove_port(u8 protocol, u16 port)
12237 +{
12238 +       int     i, j;
12239 +       u16             *port_ptr, *next;
12240 +
12241 +       if (protocol == IPPROTO_TCP)
12242 +               port_ptr = dynamic_tcp_port_list;
12243 +       else if (protocol == IPPROTO_UDP)
12244 +               port_ptr = dynamic_udp_port_list;
12245 +       else
12246 +               return;
12247 +
12248 +       for (i=0; *port_ptr; i++, port_ptr++)
12249 +       {
12250 +               if (port == *port_ptr)
12251 +               {
12252 +                       port_next = port_ptr + 1;
12253 +                       for (j=i+1; *port_next; i++, j++)
12254 +                               *port_ptr++ = *port_next++;
12255 +                       *port_ptr = 0;
12256 +                       return;
12257 +               }
12258 +       }
12259 +}
12260 +#endif
12261 +
12262 +/*----------------------------------------------------------------------
12263 +* sl351x_nat_ioctl
12264 +*----------------------------------------------------------------------*/
12265 +int sl351x_nat_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
12266 +{
12267 +       GMAC_INFO_T             *tp = (GMAC_INFO_T *)dev->priv;
12268 +       int                             i, j, port_id;
12269 +    NATCMD_HDR_T               nat_hdr;
12270 +    NAT_REQ_E                  ctrl;
12271 +       unsigned char           *req_datap;
12272 +       NAT_IP_ENTRY_T          *ipcfg;
12273 +       NAT_XPORT_ENTRY_T       *xport_entry;
12274 +       NAT_WRULE_ENTRY_T       *wrule_entry;
12275 +       unsigned int            qid;
12276 +
12277 +       if (copy_from_user((void *)&nat_hdr, rq->ifr_data, sizeof(nat_hdr)))
12278 +               return -EFAULT;
12279 +       req_datap = (unsigned char *)rq->ifr_data + sizeof(nat_hdr);
12280 +       port_id = tp->port_id;
12281 +       switch (nat_hdr.cmd) {
12282 +       case NATSSTATUS:
12283 +               if (!capable(CAP_NET_ADMIN))
12284 +                       return -EPERM;
12285 +               if (nat_hdr.len != sizeof(NAT_STATUS_T))
12286 +                       return -EPERM;
12287 +               if (copy_from_user((void *)&ctrl.status, req_datap, sizeof(ctrl.status)))
12288 +                       return -EFAULT;
12289 +               if (ctrl.status.enable != 0 && ctrl.status.enable != 1)
12290 +                       return -EPERM;
12291 +               // sl351x_nat_set_enabled_flag(ctrl.status.enable);
12292 +               if (nat_cfg.enabled && (ctrl.status.enable == 0))
12293 +               {
12294 +                       for (i=0; i<HASH_TOTAL_ENTRIES; i++)
12295 +                       {
12296 +                               if (hash_get_nat_owner_flag(i))
12297 +                               {
12298 +                                       hash_nat_disable_owner(i);
12299 +                                       hash_invalidate_entry(i);
12300 +                               }
12301 +                       }
12302 +               }
12303 +               nat_cfg.enabled = ctrl.status.enable;
12304 +               break;
12305 +       case NATGSTATUS:
12306 +               if (nat_hdr.len != sizeof(NAT_STATUS_T))
12307 +                       return -EPERM;
12308 +               ctrl.status.enable = nat_cfg.enabled;
12309 +               if (copy_to_user(req_datap, (void *)&ctrl.status, sizeof(ctrl.status)))
12310 +                       return -EFAULT;
12311 +               break;
12312 +       case NATSETPORT:
12313 +               if (!capable(CAP_NET_ADMIN))
12314 +                       return -EPERM;
12315 +               if (nat_hdr.len != sizeof(NAT_PORTCFG_T))
12316 +                       return -EPERM;
12317 +               if (copy_from_user((void *)&ctrl.portcfg, req_datap, sizeof(ctrl.portcfg)))
12318 +                       return -EFAULT;
12319 +               if (ctrl.portcfg.portmap == 0)
12320 +                       nat_cfg.lan_port = port_id;
12321 +               else if (ctrl.portcfg.portmap == 1)
12322 +                       nat_cfg.wan_port = port_id;
12323 +               else
12324 +                       return -EPERM;
12325 +               break;
12326 +       case NATGETPORT:
12327 +               if (nat_hdr.len != sizeof(NAT_PORTCFG_T))
12328 +                       return -EPERM;
12329 +               if (nat_cfg.lan_port == port_id)
12330 +                       ctrl.portcfg.portmap = 0;
12331 +               else if (nat_cfg.wan_port == port_id)
12332 +                       ctrl.portcfg.portmap = 1;
12333 +               else
12334 +                       return -EPERM;
12335 +               if (copy_to_user(req_datap, (void *)&ctrl.portcfg, sizeof(ctrl.portcfg)))
12336 +                       return -EFAULT;
12337 +               break;
12338 +       case NATADDIP:
12339 +               if (!capable(CAP_NET_ADMIN))
12340 +                       return -EPERM;
12341 +               if (nat_hdr.len != sizeof(NAT_IPCFG_T))
12342 +                       return -EPERM;
12343 +               i = nat_cfg.ipcfg[port_id].total;
12344 +               if (i >= CONFIG_NAT_MAX_IP_NUM)
12345 +                       return -E2BIG;
12346 +               if (copy_from_user((void *)&nat_cfg.ipcfg[port_id].entry[i], req_datap, sizeof(NAT_IPCFG_T)))
12347 +                       return -EFAULT;
12348 +               nat_cfg.ipcfg[port_id].total++;
12349 +               break;
12350 +       case NATDELIP:
12351 +               if (!capable(CAP_NET_ADMIN))
12352 +                       return -EPERM;
12353 +               if (nat_hdr.len != sizeof(NAT_IPCFG_T))
12354 +                       return -EPERM;
12355 +               if (copy_from_user((void *)&ctrl.ipcfg, req_datap, sizeof(ctrl.ipcfg)))
12356 +                       return -EFAULT;
12357 +               ipcfg = (NAT_IP_ENTRY_T *)&nat_cfg.ipcfg[port_id].entry[0];
12358 +               for (i=0; i<nat_cfg.ipcfg[port_id].total; i++, ipcfg++)
12359 +               {
12360 +                       if (ipcfg->ipaddr == ctrl.ipcfg.entry.ipaddr)
12361 +                       {
12362 +                               NAT_IP_ENTRY_T *ipcfg_next;
12363 +                               ipcfg_next = ipcfg + 1;
12364 +                               for (j=i+1; j < nat_cfg.ipcfg[port_id].total; i++, j++)
12365 +                               {
12366 +                                       memcpy((void *)ipcfg, (void *)ipcfg_next, sizeof(NAT_IP_ENTRY_T));
12367 +                                       ipcfg++;
12368 +                                       ipcfg_next++;
12369 +                               }
12370 +                               ipcfg->ipaddr = 0;
12371 +                               ipcfg->netmask = 0;
12372 +                               nat_cfg.ipcfg[port_id].total--;
12373 +                               return 0;
12374 +                       }
12375 +               }
12376 +               return -ENOENT;
12377 +       case NATGETIP:
12378 +               if (nat_hdr.len != sizeof(NAT_IPCFG_ALL_T))
12379 +                       return -EPERM;
12380 +               if (copy_to_user(req_datap, (void *)&nat_cfg.ipcfg[port_id], sizeof(NAT_IPCFG_ALL_T)))
12381 +                       return -EFAULT;
12382 +               break;
12383 +       case NATAXPORT:
12384 +               if (!capable(CAP_NET_ADMIN))
12385 +                       return -EPERM;
12386 +               if (nat_hdr.len != sizeof(NAT_XPORT_T))
12387 +                       return -EPERM;
12388 +               i = nat_cfg.xport.total;
12389 +               if (i >= CONFIG_NAT_MAX_XPORT)
12390 +                       return -E2BIG;
12391 +               if (copy_from_user((void *)&nat_cfg.xport.entry[i], req_datap, sizeof(NAT_XPORT_T)))
12392 +                       return -EFAULT;
12393 +               nat_cfg.xport.total++;
12394 +               break;
12395 +       case NATDXPORT:
12396 +               if (!capable(CAP_NET_ADMIN))
12397 +                       return -EPERM;
12398 +               if (nat_hdr.len != sizeof(NAT_XPORT_T))
12399 +                       return -EPERM;
12400 +               if (copy_from_user((void *)&ctrl.xport, req_datap, sizeof(NAT_XPORT_T)))
12401 +                       return -EFAULT;
12402 +               xport_entry = (NAT_XPORT_ENTRY_T *)&nat_cfg.xport.entry[0];
12403 +               for (i=0; i<nat_cfg.xport.total; i++, xport_entry++)
12404 +               {
12405 +                       if (memcmp((void *)xport_entry, (void *)&ctrl.xport, sizeof(NAT_XPORT_ENTRY_T)) == 0)
12406 +                       {
12407 +                               NAT_XPORT_ENTRY_T *xport_next;
12408 +                               xport_next = xport_entry + 1;
12409 +                               for (j=i+1; j < nat_cfg.xport.total; i++, j++)
12410 +                               {
12411 +                                       memcpy((void *)xport_entry, (void *)xport_next, sizeof(NAT_XPORT_ENTRY_T));
12412 +                                       xport_entry++;
12413 +                                       xport_next++;
12414 +                               }
12415 +                               memset((void *)xport_entry, 0, sizeof(NAT_XPORT_ENTRY_T));
12416 +                               nat_cfg.xport.total--;
12417 +                               return 0;
12418 +                       }
12419 +               }
12420 +               return -ENOENT;
12421 +       case NATGXPORT:
12422 +               if (nat_hdr.len != sizeof(NAT_XPORT_ALL_T))
12423 +                       return -EPERM;
12424 +               if (copy_to_user(req_datap, (void *)&nat_cfg.xport, sizeof(NAT_XPORT_ALL_T)))
12425 +                       return -EFAULT;
12426 +               break;
12427 +       case NATSWEIGHT:
12428 +               if (!capable(CAP_NET_ADMIN))
12429 +                       return -EPERM;
12430 +               if (nat_hdr.len != sizeof(NAT_WEIGHT_T))
12431 +                       return -EPERM;
12432 +               if (copy_from_user((void *)&nat_cfg.weight, req_datap, sizeof(NAT_WEIGHT_T)))
12433 +                       return -EFAULT;
12434 +               mac_set_hw_tx_weight(dev, (char *)&nat_cfg.weight);
12435 +               break;
12436 +       case NATGWEIGHT:
12437 +               if (nat_hdr.len != sizeof(NAT_WEIGHT_T))
12438 +                       return -EPERM;
12439 +               mac_get_hw_tx_weight(dev, (char *)&nat_cfg.weight);
12440 +               if (copy_to_user(req_datap, (void *)&nat_cfg.weight, sizeof(NAT_WEIGHT_T)))
12441 +                       return -EFAULT;
12442 +               break;
12443 +       case NATAWRULE:
12444 +               if (!capable(CAP_NET_ADMIN))
12445 +                       return -EPERM;
12446 +               if (nat_hdr.len != sizeof(NAT_WRULE_T))
12447 +                       return -EPERM;
12448 +               if (copy_from_user((void *)&qid, req_datap, sizeof(qid)))
12449 +                       return -EFAULT;
12450 +               if (qid > CONFIG_NAT_TXQ_NUM)
12451 +                       return -EPERM;
12452 +               i = nat_cfg.wrule[qid].total;
12453 +               if (i >= CONFIG_NAT_MAX_WRULE)
12454 +                       return -E2BIG;
12455 +               if (copy_from_user((void *)&nat_cfg.wrule[qid].entry[i], req_datap+sizeof(qid), sizeof(NAT_WRULE_T)))
12456 +                       return -EFAULT;
12457 +               nat_cfg.wrule[qid].total++;
12458 +               break;
12459 +       case NATDWRULE:
12460 +               if (!capable(CAP_NET_ADMIN))
12461 +                       return -EPERM;
12462 +               if (nat_hdr.len != sizeof(NAT_WRULE_T))
12463 +                       return -EPERM;
12464 +               if (copy_from_user((void *)&ctrl.wrule, req_datap, sizeof(NAT_WRULE_T)))
12465 +                       return -EFAULT;
12466 +               qid = ctrl.wrule.qid;
12467 +               if (qid >= CONFIG_NAT_TXQ_NUM)
12468 +                       return -EPERM;
12469 +               wrule_entry = (NAT_WRULE_ENTRY_T *)&nat_cfg.wrule[qid].entry[0];
12470 +               for (i=0; i<nat_cfg.wrule[qid].total; i++, wrule_entry++)
12471 +               {
12472 +                       if (memcmp((void *)wrule_entry, (void *)&ctrl.wrule.entry, sizeof(NAT_WRULE_ENTRY_T)) == 0)
12473 +                       {
12474 +                               NAT_WRULE_ENTRY_T *wrule_next;
12475 +                               wrule_next = wrule_entry + 1;
12476 +                               for (j=i+1; j < nat_cfg.wrule[qid].total; i++, j++)
12477 +                               {
12478 +                                       memcpy((void *)wrule_entry, (void *)wrule_next, sizeof(NAT_WRULE_ENTRY_T));
12479 +                                       wrule_entry++;
12480 +                                       wrule_next++;
12481 +                               }
12482 +                               memset((void *)wrule_entry, 0, sizeof(NAT_WRULE_ENTRY_T));
12483 +                               nat_cfg.wrule[qid].total--;
12484 +                               return 0;
12485 +                       }
12486 +               }
12487 +               return -ENOENT;
12488 +       case NATGWRULE:
12489 +               if (nat_hdr.len != sizeof(NAT_WRULE_ALL_T))
12490 +                       return -EPERM;
12491 +               if (copy_from_user((void *)&qid, req_datap, sizeof(qid)))
12492 +                       return -EFAULT;
12493 +               if (qid >= CONFIG_NAT_TXQ_NUM)
12494 +                       return -EPERM;
12495 +               if (copy_to_user(req_datap, (void *)&nat_cfg.wrule[qid], sizeof(NAT_WRULE_ALL_T)))
12496 +                       return -EFAULT;
12497 +               break;
12498 +       case NATSDEFQ:
12499 +               if (!capable(CAP_NET_ADMIN))
12500 +                       return -EPERM;
12501 +               if (nat_hdr.len != sizeof(NAT_QUEUE_T))
12502 +                       return -EPERM;
12503 +               if (copy_from_user((void *)&nat_cfg.default_hw_txq, req_datap, sizeof(u32)))
12504 +                       return -EFAULT;
12505 +               break;
12506 +       case NATGDEFQ:
12507 +               if (nat_hdr.len != sizeof(NAT_QUEUE_T))
12508 +                       return -EPERM;
12509 +               if (copy_to_user(req_datap, (void *)&nat_cfg.default_hw_txq, sizeof(u32)))
12510 +                       return -EFAULT;
12511 +       case NATRMIPCFG:
12512 +               nat_cfg.ipcfg[port_id].total = 0;
12513 +               break;
12514 +       case NATTESTENTRY:
12515 +               if (!capable(CAP_NET_ADMIN))
12516 +                       return -EPERM;
12517 +               if (nat_hdr.len != sizeof(NAT_TESTENTRY_T))
12518 +                       return -EPERM;
12519 +               if (copy_from_user((void *)&ctrl.init_entry, req_datap, sizeof(ctrl.init_entry)))
12520 +                       return -EFAULT;
12521 +               if (ctrl.init_entry.init_enable != 0 && ctrl.init_entry.init_enable != 1)
12522 +                       return -EPERM;
12523 +               nat_cfg.init_enabled = ctrl.init_entry.init_enable;
12524 +               break;
12525 +
12526 +       default:
12527 +               return -EPERM;
12528 +       }
12529 +
12530 +       return 0;
12531 +}
12532 +
12533 +/*----------------------------------------------------------------------
12534 +*      nat_init_test_entry
12535 +*      Initialize NAT test hash entries
12536 +*
12537 +*      SmartBits P1  -----> Lepus GMAC 0 --------------+
12538 +*                                                                                                      |
12539 +*                                                                                                      |
12540 +*             P3  <----- Lepus GMAC 1 -- HW TxQ0 <--+
12541 +*                                                                        -- HW TxQ1 <--+
12542 +*                                                                        -- HW TxQ2 <--+
12543 +*                                                                        -- HW TxQ3 <--+
12544 +*
12545 +*      SmartBits P1  <----- Lepus GMAC 0 -- HW TxQ0 <--+
12546 +*                                                                        -- HW TxQ1 <--+
12547 +*                                     -- HW TxQ2 <--+
12548 +*                                                                        -- HW TxQ3 <--+
12549 +*                                                                                                      |
12550 +*                                                                                                      |
12551 +*             P3  -----> Lepus GMAC 1 --------------+
12552 +*
12553 +*   LAN GMAC0 <--------------------------------------------> GMAC1 WAN
12554 +*      192.168.[x].[y]:50 --> 168.95.[x].[y]:80 ---TXQ[y-1]---> 192.168.2.254:200[y] --> 168.95.[x].[y]:80
12555 +*      192.168.[x].[y]:50 <-- 168.95.[x].[y]:80 <--TXQ[y-1]---- 192.168.2.254:200[y] <-- 168.95.[x].[y]:80
12556 +*   where:
12557 +*              [x] : Packet Type
12558 +*              [y] : Tx Queue, 1 for TxQ0, 2 for TxQ1, 3 for TxQ2, 4 for TxQ3,
12559 +*
12560 +*
12561 +* Packet Type:
12562 +* 1. TCP Frames <---> TCP Frames
12563 +*   LAN GMAC0 <--------------------------------> GMAC1 WAN
12564 +*      192.168.1.1:50 --> 168.95.1.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.1.1:80
12565 +*      192.168.1.1:50 <-- 168.95.1.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.1.1:80
12566 +*
12567 +*      192.168.1.2:50 --> 168.95.1.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.1.2:80
12568 +*      192.168.1.2:50 <-- 168.95.1.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.1.2:80
12569 +*
12570 +*      192.168.1.3:50 --> 168.95.1.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.1.3:80
12571 +*      192.168.1.3:50 <-- 168.95.1.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.1.3:80
12572 +*
12573 +*      192.168.1.4:50 --> 168.95.1.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.1.4:80
12574 +*      192.168.1.4:50 <-- 168.95.1.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.1.4:80
12575 +*
12576 +* 2 TCP Frames <----> PPPoE + TCP Frames
12577 +*   LAN GMAC0 <--------------------------------> GMAC1 WAN
12578 +*      192.168.2.1:50 --> 168.95.2.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.2.1:80
12579 +*      192.168.2.1:50 <-- 168.95.2.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.2.1:80
12580 +*
12581 +*      192.168.2.2:50 --> 168.95.2.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.2.2:80
12582 +*      192.168.2.2:50 <-- 168.95.2.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.2.2:80
12583 +*
12584 +*      192.168.2.3:50 --> 168.95.2.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.2.3:80
12585 +*      192.168.2.3:50 <-- 168.95.2.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.2.3:80
12586 +*
12587 +*      192.168.2.4:50 --> 168.95.2.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.2.4:80
12588 +*      192.168.2.4:50 <-- 168.95.2.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.2.4:80
12589 +*
12590 +* 3 TCP Frames <----> VLAN + PPPoE + TCP Frames
12591 +*   LAN GMAC0 <--------------------------------> GMAC1 WAN
12592 +*      192.168.3.1:50 --> 168.95.3.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.3.1:80
12593 +*      192.168.3.1:50 <-- 168.95.3.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.3.1:80
12594 +*
12595 +*      192.168.3.2:50 --> 168.95.3.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.3.2:80
12596 +*      192.168.3.2:50 <-- 168.95.3.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.3.2:80
12597 +*
12598 +*      192.168.3.3:50 --> 168.95.3.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.3.3:80
12599 +*      192.168.3.3:50 <-- 168.95.3.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.3.3:80
12600 +*
12601 +*      192.168.3.4:50 --> 168.95.3.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.3.4:80
12602 +*      192.168.3.4:50 <-- 168.95.3.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.3.4:80
12603 +*
12604 +* 4 VLAN-A + TCP Frames <----> VLAN-B + PPPoE + TCP Frames
12605 +*   LAN GMAC0 <--------------------------------> GMAC1 WAN
12606 +*      192.168.4.1:50 --> 168.95.4.1:80 ---TXQ0---> 192.168.2.254:2001 --> 168.95.4.1:80
12607 +*      192.168.4.1:50 <-- 168.95.4.1:80 <--TXQ0---- 192.168.2.254:2001 <-- 168.95.4.1:80
12608 +*
12609 +*      192.168.4.2:50 --> 168.95.4.2:80 ---TXQ1---> 192.168.2.254:2002 --> 168.95.4.2:80
12610 +*      192.168.4.2:50 <-- 168.95.4.2:80 <--TXQ1---- 192.168.2.254:2002 <-- 168.95.4.2:80
12611 +*
12612 +*      192.168.4.3:50 --> 168.95.4.3:80 ---TXQ2---> 192.168.2.254:2003 --> 168.95.4.3:80
12613 +*      192.168.4.3:50 <-- 168.95.4.3:80 <--TXQ2---- 192.168.2.254:2003 <-- 168.95.4.3:80
12614 +*
12615 +*      192.168.4.4:50 --> 168.95.4.4:80 ---TXQ3---> 192.168.2.254:2004 --> 168.95.4.4:80
12616 +*      192.168.4.4:50 <-- 168.95.4.4:80 <--TXQ3---- 192.168.2.254:2004 <-- 168.95.4.4:80
12617 +*
12618 +*
12619 +*
12620 +*----------------------------------------------------------------------*/
12621 +#ifdef SL351x_NAT_TEST_BY_SMARTBITS
12622 +#define        NAT_IPIV(a,b,c,d)                       ((a<<24)+(b<<16)+(c<<8)+d)
12623 +#define     NAT_TEST_CLIENT_IP                         NAT_IPIV(192,168,1,1)
12624 +#define     NAT_TEST_SERVER_IP                         NAT_IPIV(168,95,1,1)
12625 +#define                NAT_TEST_LAN_IP                         NAT_IPIV(192,168,1,254)
12626 +#define                NAT_TEST_WAN_IP                         NAT_IPIV(192,168,2,254)
12627 +#define     NAT_TEST_MAP_PORT_BASE             2001
12628 +#define     NAT_TEST_SPORT                             50
12629 +#define     NAT_TEST_DPORT                             80
12630 +#define     NAT_TEST_PROTOCOL                  6
12631 +u8                     nat_test_lan_target_da[6]={0x00,0x11,0x22,0x33,0x44,0x55};
12632 +u8                     nat_test_wan_target_da[6]={0x00,0xaa,0xbb,0xcc,0xdd,0xee};
12633 +u8                     nat_test_lan_my_da[6]={0x00,0x11,0x11,0x11,0x11,0x11};
12634 +u8                     nat_test_wan_my_da[6]={0x00,0x22,0x22,0x22,0x22,0x22};
12635 +static void nat_init_test_entry(void)
12636 +{
12637 +       int                             i, j ;
12638 +       NAT_HASH_ENTRY_T        *hash_entry;
12639 +       u32                                     sip, dip;
12640 +       u32                                     hash_data[HASH_MAX_DWORDS];
12641 +       NAT_CFG_T                       *cfg;
12642 +       int                                     hash_index;
12643 +
12644 +       cfg = (NAT_CFG_T *)&nat_cfg;
12645 +       hash_entry = (NAT_HASH_ENTRY_T *)&hash_data;
12646 +       hash_entry->key.Ethertype       = 0;
12647 +       hash_entry->key.rule_id         = 0;
12648 +       hash_entry->key.ip_protocol = IPPROTO_TCP;
12649 +       hash_entry->key.reserved1       = 0;
12650 +       hash_entry->key.reserved2       = 0;
12651 +       // hash_entry->key.sip          = NAT_TEST_CLIENT_IP;
12652 +       // hash_entry->key.dip          = NAT_TEST_SERVER_IP;
12653 +       hash_entry->key.sport           = htons(NAT_TEST_SPORT);
12654 +       hash_entry->key.dport           = htons(NAT_TEST_DPORT);
12655 +       hash_entry->key.rule_id = cfg->tcp_udp_rule_id;
12656 +       hash_entry->action.dword = NAT_LAN2WAN_ACTIONS;
12657 +
12658 +       sip = NAT_TEST_CLIENT_IP;
12659 +       dip = NAT_TEST_SERVER_IP;
12660 +
12661 +       // Init TCP <------> TCP hash entries
12662 +       // LAN --> WAN
12663 +       // (1) TCP --> TCP
12664 +       // (2) TCP --> PPPoE + TCP
12665 +       // (3) TCP --> VLAN-B + PPPoE + TCP
12666 +       // (4) TCP + VLAN-A --> VLAN-B + PPPoE + TCP
12667 +       memcpy(hash_entry->param.da, nat_test_wan_target_da, 6);
12668 +       memcpy(hash_entry->param.sa, nat_test_wan_my_da, 6);
12669 +       hash_entry->key.port_id = cfg->lan_port;
12670 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
12671 +       {
12672 +               if (i < 2)
12673 +               {
12674 +                       hash_entry->action.bits.dest_qid = i+2;
12675 +               }
12676 +               else
12677 +               {
12678 +                       hash_entry->action.bits.dest_qid = i;
12679 +               }
12680 +               hash_entry->action.bits.dest_qid += (cfg->wan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
12681 +               hash_entry->param.Sport = NAT_TEST_MAP_PORT_BASE+i;
12682 +               hash_entry->param.Dport = NAT_TEST_DPORT;
12683 +               for (j=0; j<4; j++)
12684 +               {
12685 +                       hash_entry->key.sip = sip + i + j*0x100;
12686 +                       hash_entry->key.dip = dip + i + j*0x100;
12687 +                       hash_entry->param.Dip = hash_entry->key.dip;
12688 +                       hash_entry->param.Sip = NAT_TEST_WAN_IP;
12689 +                       switch (j)
12690 +                       {
12691 +                       case 0:
12692 +                               hash_entry->action.bits.pppoe = 0;
12693 +                               hash_entry->param.pppoe = 0;
12694 +                               hash_entry->action.bits.vlan = 0;
12695 +                               hash_entry->param.vlan = 0;
12696 +                               break;
12697 +                       case 1:
12698 +                               hash_entry->action.bits.pppoe = 1;
12699 +                               hash_entry->param.pppoe = i+1;
12700 +                               hash_entry->action.bits.vlan = 0;
12701 +                               hash_entry->param.vlan = 0;
12702 +                               break;
12703 +                       case 2:
12704 +                               hash_entry->action.bits.pppoe = 1;
12705 +                               hash_entry->param.pppoe = i+1;
12706 +                               hash_entry->action.bits.vlan = 1;
12707 +                               hash_entry->param.vlan = i+10;
12708 +                               break;
12709 +                       case 3:
12710 +                               hash_entry->action.bits.pppoe = 1;
12711 +                               hash_entry->param.pppoe = i+1;
12712 +                               hash_entry->action.bits.vlan = 1;
12713 +                               hash_entry->param.vlan = i+10;
12714 +                               break;
12715 +                       }
12716 +                       hash_entry->tmo.counter = hash_entry->tmo.interval = 0x7fff;
12717 +                       hash_index = nat_build_keys(&hash_entry->key);
12718 +                       nat_write_hash_entry(hash_index, hash_entry);
12719 +                       hash_nat_enable_owner(hash_index);
12720 +                       hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
12721 +               }
12722 +       }
12723 +
12724 +
12725 +       // WAN --> LAN
12726 +       hash_entry->key.port_id         = cfg->wan_port;
12727 +       hash_entry->key.sport           = htons(NAT_TEST_DPORT);
12728 +       hash_entry->key.dport           = htons(NAT_TEST_DPORT);
12729 +       hash_entry->key.rule_id         = cfg->tcp_udp_rule_id;
12730 +       hash_entry->action.dword        = NAT_WAN2LAN_ACTIONS;
12731 +       hash_entry->key.sport           = htons(NAT_TEST_DPORT);
12732 +       memcpy(hash_entry->param.da, nat_test_lan_target_da, 6);
12733 +       memcpy(hash_entry->param.sa, nat_test_lan_my_da, 6);
12734 +       for (i=0; i<TOE_HW_TXQ_NUM; i++)
12735 +       {
12736 +               hash_entry->key.dport = htons(NAT_TEST_MAP_PORT_BASE + i);
12737 +               if (i < 2)
12738 +               {
12739 +                       hash_entry->action.bits.dest_qid = i+2;
12740 +               }
12741 +               else
12742 +               {
12743 +                       hash_entry->action.bits.dest_qid = i;
12744 +               }
12745 +               hash_entry->action.bits.dest_qid += (cfg->lan_port==0) ? TOE_GMAC0_HW_TXQ0_QID : TOE_GMAC1_HW_TXQ0_QID;
12746 +               hash_entry->param.Dport = NAT_TEST_SPORT;
12747 +               hash_entry->param.Sport = NAT_TEST_DPORT;
12748 +               hash_entry->param.da[5] = i;
12749 +               for (j=0; j<4; j++)
12750 +               {
12751 +                       hash_entry->key.sip = (dip + i + j*0x100);
12752 +                       hash_entry->key.dip = (NAT_TEST_WAN_IP);
12753 +                       hash_entry->param.Sip = hash_entry->key.sip;
12754 +                       hash_entry->param.Dip = sip + i + j*0x100;
12755 +                       switch (j)
12756 +                       {
12757 +                       case 0:
12758 +                               hash_entry->action.bits.pppoe = 0;
12759 +                               hash_entry->param.pppoe = 0;
12760 +                               hash_entry->action.bits.vlan = 0;
12761 +                               hash_entry->param.vlan = 0;
12762 +                               break;
12763 +                       case 1:
12764 +                               hash_entry->action.bits.pppoe = 2;
12765 +                               hash_entry->param.pppoe = i+1;
12766 +                               hash_entry->action.bits.vlan = 0;
12767 +                               hash_entry->param.vlan = 0;
12768 +                               break;
12769 +                       case 2:
12770 +                               hash_entry->action.bits.pppoe = 2;
12771 +                               hash_entry->param.pppoe = i+1;
12772 +                               hash_entry->action.bits.vlan = 2;
12773 +                               hash_entry->param.vlan = i+5;
12774 +                               break;
12775 +                       case 3:
12776 +                               hash_entry->action.bits.pppoe = 1;
12777 +                               hash_entry->param.pppoe = i+1;
12778 +                               hash_entry->action.bits.vlan = 1;
12779 +                               hash_entry->param.vlan = i+5;
12780 +                               break;
12781 +                       }
12782 +                       hash_entry->tmo.counter = hash_entry->tmo.interval = 0x7fff;
12783 +                       hash_index = nat_build_keys(&hash_entry->key);
12784 +                       nat_write_hash_entry(hash_index, hash_entry);
12785 +                       hash_nat_enable_owner(hash_index);
12786 +                       hash_validate_entry(hash_index); // Must last one, else HW Tx fast than SW
12787 +               }
12788 +       }
12789 +}
12790 +#endif // SL351x_NAT_TEST_BY_SMARTBITS
12791 +
12792 +#endif // CONFIG_SL351x_NAT
12793 +
12794 Index: linux-2.6.23.17/drivers/net/sl351x_proc.c
12795 ===================================================================
12796 --- /dev/null
12797 +++ linux-2.6.23.17/drivers/net/sl351x_proc.c
12798 @@ -0,0 +1,578 @@
12799 +/****************************************************************************
12800 +* Copyright 2006 Storlink Corp.  All rights reserved.
12801 +*----------------------------------------------------------------------------
12802 +* Name                 : sl351x_proc.c
12803 +* Description  :
12804 +*              Handle Proc Routines for Storlink SL351x Platform
12805 +*
12806 +* History
12807 +*
12808 +*      Date            Writer          Description
12809 +*----------------------------------------------------------------------------
12810 +*      04/13/2006      Gary Chen       Create and implement
12811 +*
12812 +*
12813 +****************************************************************************/
12814 +#include <linux/module.h>
12815 +#include <linux/kernel.h>
12816 +#include <linux/compiler.h>
12817 +#include <linux/pci.h>
12818 +#include <linux/init.h>
12819 +#include <linux/ioport.h>
12820 +#include <linux/netdevice.h>
12821 +#include <linux/etherdevice.h>
12822 +#include <linux/rtnetlink.h>
12823 +#include <linux/delay.h>
12824 +#include <linux/ethtool.h>
12825 +#include <linux/mii.h>
12826 +#include <linux/completion.h>
12827 +#include <asm/hardware.h>
12828 +#include <asm/io.h>
12829 +#include <asm/irq.h>
12830 +#include <asm/semaphore.h>
12831 +#include <asm/arch/irqs.h>
12832 +#include <asm/arch/it8712.h>
12833 +#include <linux/mtd/kvctl.h>
12834 +#include <linux/skbuff.h>
12835 +#include <linux/if_ether.h>
12836 +#include <linux/if_pppox.h>
12837 +#include <linux/in.h>
12838 +#include <linux/ip.h>
12839 +#include <linux/tcp.h>
12840 +#include <linux/ppp_defs.h>
12841 +#ifdef CONFIG_NETFILTER
12842 +#include <linux/netfilter_ipv4/ip_conntrack.h>
12843 +#endif
12844 +#include <linux/proc_fs.h>
12845 +#include <linux/seq_file.h>
12846 +#include <linux/percpu.h>
12847 +#ifdef CONFIG_SYSCTL
12848 +#include <linux/sysctl.h>
12849 +#endif
12850 +
12851 +#define         MIDWAY
12852 +#define         SL_LEPUS
12853 +
12854 +// #define PROC_DEBUG_MSG      1
12855 +
12856 +#include <asm/arch/sl2312.h>
12857 +#include <asm/arch/sl351x_gmac.h>
12858 +#include <asm/arch/sl351x_hash_cfg.h>
12859 +#include <asm/arch/sl351x_nat_cfg.h>
12860 +#include <asm/arch/sl351x_toe.h>
12861 +
12862 +#ifdef CONFIG_PROC_FS
12863 +/*----------------------------------------------------------------------
12864 +* Definition
12865 +*----------------------------------------------------------------------*/
12866 +#define        proc_printf                                     printk
12867 +#define SL351x_GMAC_PROC_NAME          "sl351x_gmac"
12868 +#define SL351x_NAT_PROC_NAME           "sl351x_nat"
12869 +#define SL351x_TOE_PROC_NAME           "sl351x_toe"
12870 +
12871 +/*----------------------------------------------------------------------
12872 +* Function Definition
12873 +*----------------------------------------------------------------------*/
12874 +#ifdef CONFIG_SL351x_NAT
12875 +static int nat_ct_open(struct inode *inode, struct file *file);
12876 +static void *nat_ct_seq_start(struct seq_file *s, loff_t *pos);
12877 +static void nat_ct_seq_stop(struct seq_file *s, void *v);
12878 +static void *nat_ct_seq_next(struct seq_file *s, void *v, loff_t *pos);
12879 +static int nat_ct_seq_show(struct seq_file *s, void *v);
12880 +#endif
12881 +
12882 +#ifdef CONFIG_SL351x_RXTOE
12883 +static int toe_ct_open(struct inode *inode, struct file *file);
12884 +static void *toe_ct_seq_start(struct seq_file *s, loff_t *pos);
12885 +static void toe_ct_seq_stop(struct seq_file *s, void *v);
12886 +static void *toe_ct_seq_next(struct seq_file *s, void *v, loff_t *pos);
12887 +static int toe_ct_seq_show(struct seq_file *s, void *v);
12888 +extern int sl351x_get_toe_conn_flag(int index);
12889 +extern struct toe_conn * sl351x_get_toe_conn_info(int index);
12890 +#endif
12891 +
12892 +static int gmac_ct_open(struct inode *inode, struct file *file);
12893 +static void *gmac_ct_seq_start(struct seq_file *s, loff_t *pos);
12894 +static void gmac_ct_seq_stop(struct seq_file *s, void *v);
12895 +static void *gmac_ct_seq_next(struct seq_file *s, void *v, loff_t *pos);
12896 +static int gmac_ct_seq_show(struct seq_file *s, void *v);
12897 +
12898 +
12899 +/*----------------------------------------------------------------------
12900 +* Data
12901 +*----------------------------------------------------------------------*/
12902 +#ifdef CONFIG_SYSCTL
12903 +// static struct ctl_table_header *nat_ct_sysctl_header;
12904 +#endif
12905 +
12906 +#ifdef CONFIG_SL351x_NAT
12907 +static struct seq_operations nat_ct_seq_ops = {
12908 +       .start = nat_ct_seq_start,
12909 +       .next  = nat_ct_seq_next,
12910 +       .stop  = nat_ct_seq_stop,
12911 +       .show  = nat_ct_seq_show
12912 +};
12913 +
12914 +static struct file_operations nat_file_ops= {
12915 +       .owner   = THIS_MODULE,
12916 +       .open    = nat_ct_open,
12917 +       .read    = seq_read,
12918 +       .llseek  = seq_lseek,
12919 +       .release = seq_release
12920 +};
12921 +#endif // CONFIG_SL351x_NAT
12922 +
12923 +#ifdef CONFIG_SL351x_RXTOE
12924 +static struct seq_operations toe_ct_seq_ops = {
12925 +       .start = toe_ct_seq_start,
12926 +       .next  = toe_ct_seq_next,
12927 +       .stop  = toe_ct_seq_stop,
12928 +       .show  = toe_ct_seq_show
12929 +};
12930 +
12931 +static struct file_operations toe_file_ops= {
12932 +       .owner   = THIS_MODULE,
12933 +       .open    = toe_ct_open,
12934 +       .read    = seq_read,
12935 +       .llseek  = seq_lseek,
12936 +       .release = seq_release
12937 +};
12938 +#endif
12939 +
12940 +static struct seq_operations gmac_ct_seq_ops = {
12941 +       .start = gmac_ct_seq_start,
12942 +       .next  = gmac_ct_seq_next,
12943 +       .stop  = gmac_ct_seq_stop,
12944 +       .show  = gmac_ct_seq_show
12945 +};
12946 +
12947 +static struct file_operations gmac_file_ops= {
12948 +       .owner   = THIS_MODULE,
12949 +       .open    = gmac_ct_open,
12950 +       .read    = seq_read,
12951 +       .llseek  = seq_lseek,
12952 +       .release = seq_release
12953 +};
12954 +
12955 +#ifdef SL351x_GMAC_WORKAROUND
12956 +extern u32 gmac_workaround_cnt[4];
12957 +extern u32 gmac_short_frame_workaround_cnt[2];
12958 +#ifdef CONFIG_SL351x_NAT
12959 +       extern u32 sl351x_nat_workaround_cnt;
12960 +#endif
12961 +#endif
12962 +/*----------------------------------------------------------------------
12963 +* nat_ct_open
12964 +*----------------------------------------------------------------------*/
12965 +#ifdef CONFIG_SL351x_NAT
12966 +static int nat_ct_open(struct inode *inode, struct file *file)
12967 +{
12968 +       return seq_open(file, &nat_ct_seq_ops);
12969 +}
12970 +#endif // CONFIG_SL351x_NAT
12971 +/*----------------------------------------------------------------------
12972 +* nat_ct_seq_start
12973 +* find the first
12974 +*----------------------------------------------------------------------*/
12975 +#ifdef CONFIG_SL351x_NAT
12976 +static void *nat_ct_seq_start(struct seq_file *s, loff_t *pos)
12977 +{
12978 +       int i;
12979 +
12980 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
12981 +       for (i=*pos; i<HASH_TOTAL_ENTRIES; i++)
12982 +       {
12983 +               if (hash_get_nat_owner_flag(i))
12984 +               {
12985 +                       *pos = i;
12986 +                       return (void *)(i+1);
12987 +               }
12988 +       }
12989 +       return NULL;
12990 +}
12991 +#endif // CONFIG_SL351x_NAT
12992 +/*----------------------------------------------------------------------
12993 +* nat_ct_seq_stop
12994 +*----------------------------------------------------------------------*/
12995 +#ifdef CONFIG_SL351x_NAT
12996 +static void nat_ct_seq_stop(struct seq_file *s, void *v)
12997 +{
12998 +}
12999 +#endif // CONFIG_SL351x_NAT
13000 +/*----------------------------------------------------------------------
13001 +* nat_ct_seq_next
13002 +*----------------------------------------------------------------------*/
13003 +#ifdef CONFIG_SL351x_NAT
13004 +static void *nat_ct_seq_next(struct seq_file *s, void *v, loff_t *pos)
13005 +{
13006 +       int i;
13007 +
13008 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
13009 +       (*pos)++;
13010 +       for (i=*pos; i<HASH_TOTAL_ENTRIES; i++)
13011 +       {
13012 +               if (hash_get_nat_owner_flag(i))
13013 +               {
13014 +                       *pos = i;
13015 +                       return (void *)(i+1);
13016 +               }
13017 +       }
13018 +       return NULL;
13019 +}
13020 +#endif // CONFIG_SL351x_NAT
13021 +/*----------------------------------------------------------------------
13022 +* nat_ct_seq_show
13023 +*----------------------------------------------------------------------*/
13024 +#ifdef CONFIG_SL351x_NAT
13025 +static int nat_ct_seq_show(struct seq_file *s, void *v)
13026 +{
13027 +       int                             idx;
13028 +       NAT_HASH_ENTRY_T        *nat_entry;
13029 +       GRE_HASH_ENTRY_T        *gre_entry;
13030 +
13031 +       idx = (int)v;
13032 +       if (idx<=0 || idx >HASH_TOTAL_ENTRIES)
13033 +               return -ENOSPC;
13034 +
13035 +       idx--;
13036 +       nat_entry = (NAT_HASH_ENTRY_T *)&hash_tables[idx];
13037 +       gre_entry = (GRE_HASH_ENTRY_T *)nat_entry;
13038 +       if (nat_entry->key.ip_protocol == IPPROTO_GRE)
13039 +       {
13040 +               if (seq_printf(s, "%4d: KEY MAC-%d [%d] %u.%u.%u.%u [%u]-->%u.%u.%u.%u\n",
13041 +                                       idx, gre_entry->key.port_id, gre_entry->key.ip_protocol,
13042 +                                       HIPQUAD(gre_entry->key.sip), ntohs(gre_entry->key.call_id),
13043 +                                       HIPQUAD(gre_entry->key.dip)))
13044 +                       return -ENOSPC;
13045 +               if (seq_printf(s, "      PARAMETER: %u.%u.%u.%u -->%u.%u.%u.%u [%u] Timeout:%ds\n",
13046 +                                       HIPQUAD(gre_entry->param.Sip),
13047 +                                       HIPQUAD(gre_entry->param.Dip), gre_entry->param.Dport,
13048 +                                       gre_entry->tmo.counter))
13049 +                       return -ENOSPC;
13050 +       }
13051 +       else
13052 +       {
13053 +               if (seq_printf(s, "%4d: KEY MAC-%d [%d] %u.%u.%u.%u [%u]-->%u.%u.%u.%u [%u]\n",
13054 +                                       idx, nat_entry->key.port_id, nat_entry->key.ip_protocol,
13055 +                                       HIPQUAD(nat_entry->key.sip), ntohs(nat_entry->key.sport),
13056 +                                       HIPQUAD(nat_entry->key.dip), ntohs(nat_entry->key.dport)))
13057 +                       return -ENOSPC;
13058 +               if (seq_printf(s, "      PARAMETER: %u.%u.%u.%u [%u]-->%u.%u.%u.%u [%u] Timeout:%ds\n",
13059 +                                       HIPQUAD(nat_entry->param.Sip), nat_entry->param.Sport,
13060 +                                       HIPQUAD(nat_entry->param.Dip), nat_entry->param.Dport,
13061 +                                       nat_entry->tmo.counter))
13062 +                       return -ENOSPC;
13063 +       }
13064 +       return 0;
13065 +}
13066 +#endif // CONFIG_SL351x_NAT
13067 +
13068 +/*----------------------------------------------------------------------
13069 +* toe_ct_open
13070 +*----------------------------------------------------------------------*/
13071 +#ifdef CONFIG_SL351x_RXTOE
13072 +static int toe_ct_open(struct inode *inode, struct file *file)
13073 +{
13074 +       return seq_open(file, &toe_ct_seq_ops);
13075 +}
13076 +#endif
13077 +/*----------------------------------------------------------------------
13078 +* toe_ct_seq_start
13079 +* find the first
13080 +*----------------------------------------------------------------------*/
13081 +#ifdef CONFIG_SL351x_RXTOE
13082 +static void *toe_ct_seq_start(struct seq_file *s, loff_t *pos)
13083 +{
13084 +       int i;
13085 +
13086 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
13087 +       for (i=*pos; i<TOE_TOE_QUEUE_NUM; i++)
13088 +       {
13089 +               if (sl351x_get_toe_conn_flag(i))
13090 +               {
13091 +                       *pos = i;
13092 +                       return (void *)(i+1);
13093 +               }
13094 +       }
13095 +       return NULL;
13096 +}
13097 +#endif
13098 +/*----------------------------------------------------------------------
13099 +* toe_ct_seq_stop
13100 +*----------------------------------------------------------------------*/
13101 +#ifdef CONFIG_SL351x_RXTOE
13102 +static void toe_ct_seq_stop(struct seq_file *s, void *v)
13103 +{
13104 +}
13105 +#endif
13106 +/*----------------------------------------------------------------------
13107 +* toe_ct_seq_next
13108 +*----------------------------------------------------------------------*/
13109 +#ifdef CONFIG_SL351x_RXTOE
13110 +static void *toe_ct_seq_next(struct seq_file *s, void *v, loff_t *pos)
13111 +{
13112 +       int i;
13113 +
13114 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
13115 +       (*pos)++;
13116 +       for (i=*pos; i<TOE_TOE_QUEUE_NUM; i++)
13117 +       {
13118 +               if (sl351x_get_toe_conn_flag(i))
13119 +               {
13120 +                       *pos = i;
13121 +                       return (void *)(i+1);
13122 +               }
13123 +       }
13124 +       return NULL;
13125 +}
13126 +#endif
13127 +/*----------------------------------------------------------------------
13128 +* toe_ct_seq_show
13129 +*----------------------------------------------------------------------*/
13130 +#ifdef CONFIG_SL351x_RXTOE
13131 +static int toe_ct_seq_show(struct seq_file *s, void *v)
13132 +{
13133 +       int                             idx;
13134 +       struct toe_conn         *toe_entry;
13135 +
13136 +       idx = (int)v;
13137 +       if (idx<=0 || idx >TOE_TOE_QUEUE_NUM)
13138 +               return -ENOSPC;
13139 +
13140 +       idx--;
13141 +       toe_entry = (struct toe_conn *)sl351x_get_toe_conn_info(idx);
13142 +       if (!toe_entry)
13143 +               return -ENOSPC;
13144 +
13145 +       if (seq_printf(s, "%4d: Qid %d MAC-%d TCP %u.%u.%u.%u [%u]-->%u.%u.%u.%u [%u]\n",
13146 +                               idx, toe_entry->qid, toe_entry->gmac->port_id,
13147 +                               NIPQUAD(toe_entry->saddr[0]), ntohs(toe_entry->source),
13148 +                               NIPQUAD(toe_entry->daddr[0]), ntohs(toe_entry->dest)))
13149 +                       return -ENOSPC;
13150 +       return 0;
13151 +}
13152 +#endif
13153 +/*----------------------------------------------------------------------
13154 +* gmac_ct_open
13155 +*----------------------------------------------------------------------*/
13156 +static int gmac_ct_open(struct inode *inode, struct file *file)
13157 +{
13158 +       return seq_open(file, &gmac_ct_seq_ops);
13159 +}
13160 +
13161 +/*----------------------------------------------------------------------
13162 +* gmac_ct_seq_start
13163 +* find the first
13164 +*----------------------------------------------------------------------*/
13165 +static void *gmac_ct_seq_start(struct seq_file *s, loff_t *pos)
13166 +{
13167 +       int i;
13168 +       i = (int)*pos + 1;;
13169 +
13170 +       if (i > 9)
13171 +               return NULL;
13172 +       else
13173 +               return (void *)i;
13174 +}
13175 +
13176 +/*----------------------------------------------------------------------
13177 +* gmac_ct_seq_stop
13178 +*----------------------------------------------------------------------*/
13179 +static void gmac_ct_seq_stop(struct seq_file *s, void *v)
13180 +{
13181 +}
13182 +
13183 +/*----------------------------------------------------------------------
13184 +* gmac_ct_seq_next
13185 +*----------------------------------------------------------------------*/
13186 +static void *gmac_ct_seq_next(struct seq_file *s, void *v, loff_t *pos)
13187 +{
13188 +       int i;
13189 +
13190 +       // proc_printf("%s: *pos=%d\n", __func__, (int)*pos);
13191 +
13192 +       (*pos)++;
13193 +       i = (int)*pos + 1;;
13194 +
13195 +       if (i > 9)
13196 +               return NULL;
13197 +       else
13198 +               return (void *)i;
13199 +}
13200 +
13201 +/*----------------------------------------------------------------------
13202 +* seq_dm_long
13203 +*----------------------------------------------------------------------*/
13204 +static void seq_dm_long(struct seq_file *s, u32 location, int length)
13205 +{
13206 +       u32             *start_p, *curr_p, *end_p;
13207 +       u32             *datap, data;
13208 +       int             i;
13209 +
13210 +       //if (length > 1024)
13211 +       //      length = 1024;
13212 +
13213 +       start_p = (u32 *)location;
13214 +       end_p = (u32 *)location + length;
13215 +       curr_p = (u32 *)((u32)location & 0xfffffff0);
13216 +       datap = (u32 *)location;
13217 +       while (curr_p < end_p)
13218 +       {
13219 +               cond_resched();
13220 +               seq_printf(s, "0x%08x: ",(u32)curr_p & 0xfffffff0);
13221 +               for (i=0; i<4; i++)
13222 +               {
13223 +                       if (curr_p < start_p || curr_p >= end_p)
13224 +               seq_printf(s, "         ");
13225 +                       else
13226 +                       {
13227 +                               data = *datap;
13228 +                               seq_printf(s, "%08X ", data);
13229 +                       }
13230 +                       if (i==1)
13231 +              seq_printf(s, "- ");
13232 +
13233 +                       curr_p++;
13234 +                       datap++;
13235 +               }
13236 +        seq_printf(s, "\n");
13237 +       }
13238 +}
13239 +
13240 +/*----------------------------------------------------------------------
13241 +* gmac_ct_seq_show
13242 +*----------------------------------------------------------------------*/
13243 +static int gmac_ct_seq_show(struct seq_file *s, void *v)
13244 +{
13245 +       switch ((int)v)
13246 +       {
13247 +               case 1:
13248 +                       seq_printf(s, "\nGMAC Global Registers\n");
13249 +                       seq_dm_long(s, TOE_GLOBAL_BASE, 32);
13250 +                       break;
13251 +               case 2:
13252 +                       seq_printf(s, "\nGMAC Non-TOE Queue Header\n");
13253 +                       seq_dm_long(s, TOE_NONTOE_QUE_HDR_BASE, 12);
13254 +                       break;
13255 +               case 3:
13256 +                       seq_printf(s, "\nGMAC TOE Queue Header\n");
13257 +                       seq_dm_long(s, TOE_TOE_QUE_HDR_BASE, 12);
13258 +                       break;
13259 +               case 4:
13260 +                       seq_printf(s, "\nGMAC-0 DMA Registers\n");
13261 +                       seq_dm_long(s, TOE_GMAC0_DMA_BASE, 52);
13262 +                       break;
13263 +               case 5:
13264 +                       seq_printf(s, "\nGMAC-0 Registers\n");
13265 +                       seq_dm_long(s, TOE_GMAC0_BASE, 32);
13266 +                       break;
13267 +               case 6:
13268 +                       seq_printf(s, "\nGMAC-1 DMA Registers\n");
13269 +                       seq_dm_long(s, TOE_GMAC1_DMA_BASE, 52);
13270 +                       break;
13271 +               case 7:
13272 +                       seq_printf(s, "\nGMAC-1 Registers\n");
13273 +                       seq_dm_long(s, TOE_GMAC1_BASE, 32);
13274 +                       break;
13275 +               case 8:
13276 +                       seq_printf(s, "\nGLOBAL Registers\n");
13277 +                       seq_dm_long(s, GMAC_GLOBAL_BASE_ADDR, 16);
13278 +                       break;
13279 +               case 9:
13280 +#ifdef SL351x_GMAC_WORKAROUND
13281 +                       seq_printf(s, "\nGMAC-0 Rx/Tx/Short Workaround: %u, %u, %u\n", gmac_workaround_cnt[0], gmac_workaround_cnt[1], gmac_short_frame_workaround_cnt[0]);
13282 +                       seq_printf(s, "GMAC-1 Rx/Tx/Short Workaround: %u, %u, %u\n", gmac_workaround_cnt[2], gmac_workaround_cnt[3], gmac_short_frame_workaround_cnt[1]);
13283 +#ifdef CONFIG_SL351x_NAT
13284 +                       seq_printf(s, "NAT Workaround: %u\n", sl351x_nat_workaround_cnt);
13285 +#endif
13286 +#endif
13287 +                       break;
13288 +               default:
13289 +                       return -ENOSPC;
13290 +       }
13291 +       return 0;
13292 +}
13293 +
13294 +/*----------------------------------------------------------------------
13295 +* init
13296 +*----------------------------------------------------------------------*/
13297 +static int __init init(void)
13298 +{
13299 +       struct proc_dir_entry *proc_gmac=NULL;
13300 +
13301 +#ifdef CONFIG_SL351x_NAT
13302 +       struct proc_dir_entry *proc_nat=NULL;
13303 +#endif
13304 +
13305 +#ifdef CONFIG_SL351x_RXTOE
13306 +       struct proc_dir_entry *proc_toe=NULL;
13307 +#endif
13308 +
13309 +#ifdef CONFIG_SYSCTL
13310 +       // nat_ct_sysctl_header = NULL;
13311 +#endif
13312 +       proc_gmac = proc_net_fops_create(SL351x_GMAC_PROC_NAME, 0440, &gmac_file_ops);
13313 +       if (!proc_gmac) goto init_bad;
13314 +
13315 +#ifdef CONFIG_SL351x_NAT
13316 +       proc_nat = proc_net_fops_create(SL351x_NAT_PROC_NAME, 0440, &nat_file_ops);
13317 +       if (!proc_nat) goto init_bad;
13318 +#endif // CONFIG_SL351x_NAT
13319 +
13320 +#ifdef CONFIG_SL351x_RXTOE
13321 +       proc_toe = proc_net_fops_create(SL351x_TOE_PROC_NAME, 0440, &toe_file_ops);
13322 +       if (!proc_toe) goto init_bad;
13323 +#endif
13324 +
13325 +#ifdef CONFIG_SYSCTL
13326 +       // nat_ct_sysctl_header = register_sysctl_table(nat_ct_net_table, 0);
13327 +       // if (!nat_ct_sysctl_header) goto init_bad;
13328 +#endif
13329 +
13330 +       return 0;
13331 +
13332 +init_bad:
13333 +       if (proc_gmac) proc_net_remove(SL351x_GMAC_PROC_NAME);
13334 +
13335 +#ifdef CONFIG_SL351x_NAT
13336 +       if (proc_nat) proc_net_remove(SL351x_NAT_PROC_NAME);
13337 +#endif
13338 +
13339 +#ifdef CONFIG_SL351x_RXTOE
13340 +       if (proc_toe) proc_net_remove(SL351x_NAT_PROC_NAME);
13341 +#endif
13342 +
13343 +#ifdef CONFIG_SYSCTL
13344 +       // if (nat_ct_sysctl_header) unregister_sysctl_table(nat_ct_sysctl_header);
13345 +#endif
13346 +       proc_printf("SL351x NAT Proc: can't create proc or register sysctl.\n");
13347 +       return -ENOMEM;
13348 +}
13349 +
13350 +/*----------------------------------------------------------------------
13351 +* fini
13352 +*----------------------------------------------------------------------*/
13353 +static void __exit fini(void)
13354 +{
13355 +       proc_net_remove(SL351x_GMAC_PROC_NAME);
13356 +
13357 +#ifdef CONFIG_SL351x_NAT
13358 +       proc_net_remove(SL351x_NAT_PROC_NAME);
13359 +#endif
13360 +
13361 +#ifdef CONFIG_SL351x_RXTOE
13362 +       proc_net_remove(SL351x_TOE_PROC_NAME);
13363 +#endif
13364 +
13365 +#ifdef CONFIG_SYSCTL
13366 +       // unregister_sysctl_table(nat_ct_sysctl_header);
13367 +#endif
13368 +}
13369 +
13370 +/*----------------------------------------------------------------------
13371 +* module
13372 +*----------------------------------------------------------------------*/
13373 +module_init(init);
13374 +module_exit(fini);
13375 +
13376 +#endif // CONFIG_PROC_FS
13377 Index: linux-2.6.23.17/drivers/net/sl351x_toe.c
13378 ===================================================================
13379 --- /dev/null
13380 +++ linux-2.6.23.17/drivers/net/sl351x_toe.c
13381 @@ -0,0 +1,1083 @@
13382 +/**************************************************************************
13383 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
13384 +*--------------------------------------------------------------------------
13385 +* Name                 : sl351x_toe.c
13386 +* Description  :
13387 +*              Provide TOE routines for SL351x
13388 +*
13389 +* History
13390 +*
13391 +*      Date            Writer          Description
13392 +*----------------------------------------------------------------------------
13393 +*                              Xiaochong
13394 +*
13395 +****************************************************************************/
13396 +
13397 +#include <linux/pci.h>
13398 +#include <linux/ip.h>
13399 +#include <linux/ipv6.h>
13400 +#include <linux/tcp.h>
13401 +#include <linux/slab.h>
13402 +#include <linux/etherdevice.h>
13403 +#include <asm/io.h>
13404 +#include <linux/sysctl_storlink.h>
13405 +#include <net/tcp.h>
13406 +#include <linux/if_ether.h>
13407 +#include <asm/arch/sl351x_gmac.h>
13408 +#include <asm/arch/sl351x_toe.h>
13409 +#include <asm/arch/sl351x_hash_cfg.h>
13410 +#include <asm/arch/sl351x_nat_cfg.h>
13411 +
13412 +static int in_toe_isr;
13413 +static int toe_initialized=0;
13414 +
13415 +static struct toe_conn toe_connections[TOE_TOE_QUEUE_NUM];
13416 +EXPORT_SYMBOL(toe_connections);
13417 +static __u32 toe_connection_bits[TOE_TOE_QUEUE_NUM/32] __attribute__ ((aligned(16)));
13418 +struct sk_buff* gen_pure_ack(struct toe_conn* connection, TOE_QHDR_T* toe_qhdr, INTR_QHDR_T *intr_curr_desc);
13419 +
13420 +extern struct storlink_sysctl  storlink_ctl;
13421 +extern TOE_INFO_T toe_private_data;
13422 +extern spinlock_t gmac_fq_lock;
13423 +extern void mac_write_dma_reg(int mac, unsigned int offset, u32 data);
13424 +extern int mac_set_rule_reg(int mac, int rule, int enabled, u32 reg0, u32 reg1, u32 reg2);
13425 +extern int hash_add_toe_entry(HASH_ENTRY_T *entry);
13426 +extern void toe_gmac_fill_free_q(void);
13427 +
13428 +#define _DEBUG_SKB_            1
13429 +#ifdef _DEBUG_SKB_
13430 +/*---------------------------------------------------------------------------
13431 + * _debug_skb
13432 + *-------------------------------------------------------------------------*/
13433 +static inline void _debug_skb(struct sk_buff *skb, GMAC_RXDESC_T *toe_curr_desc, u32 data)
13434 +{
13435 +       if ((u32)skb < 0x1000)
13436 +       {
13437 +               printk("%s skb=%x\n", __func__, (u32)skb);
13438 +               while(1);
13439 +       }
13440 +       REG32(__va(toe_curr_desc->word2.buf_adr)-SKB_RESERVE_BYTES) = data;
13441 +}
13442 +#else
13443 +#define _debug_skb(x, y, z)
13444 +#endif
13445 +
13446 +/*---------------------------------------------------------------------------
13447 + * get_connection_seq_num
13448 + *-------------------------------------------------------------------------*/
13449 +u32 get_connection_seq_num(unsigned short qid)
13450 +{
13451 +       TOE_QHDR_T      *toe_qhdr;
13452 +
13453 +       toe_qhdr = (TOE_QHDR_T*)TOE_TOE_QUE_HDR_BASE;
13454 +       toe_qhdr += qid;
13455 +       return (u32)toe_qhdr->word3.seq_num;
13456 +}
13457 +EXPORT_SYMBOL(get_connection_seq_num);
13458 +
13459 +/*---------------------------------------------------------------------------
13460 + * get_connection_ack_num
13461 + *-------------------------------------------------------------------------*/
13462 +u32 get_connection_ack_num(unsigned short qid)
13463 +{
13464 +       TOE_QHDR_T      *toe_qhdr;
13465 +
13466 +       toe_qhdr = (TOE_QHDR_T*)TOE_TOE_QUE_HDR_BASE;
13467 +       toe_qhdr += qid;
13468 +       return (u32)toe_qhdr->word4.ack_num;
13469 +}
13470 +EXPORT_SYMBOL(get_connection_ack_num);
13471 +
13472 +/*---------------------------------------------------------------------------
13473 + * dump_toe_qhdr
13474 + *-------------------------------------------------------------------------*/
13475 +void dump_toe_qhdr(TOE_QHDR_T *toe_qhdr)
13476 +{
13477 +       printk("TOE w1 %x, w2 %x, w3 %x\n", toe_qhdr->word1.bits32,
13478 +               toe_qhdr->word2.bits32, toe_qhdr->word3.bits32);
13479 +       printk("w4 %x, w5 %x, w6 %x\n", toe_qhdr->word4.bits32,
13480 +               toe_qhdr->word5.bits32, toe_qhdr->word6.bits32);
13481 +}
13482 +
13483 +/*---------------------------------------------------------------------------
13484 + * dump_intrq_desc
13485 + *-------------------------------------------------------------------------*/
13486 +void dump_intrq_desc(INTR_QHDR_T *intr_curr_desc)
13487 +{
13488 +       printk("INTR w0 %x, w1 %x, seq %x\n", intr_curr_desc->word0.bits32,
13489 +               intr_curr_desc->word1.bits32, intr_curr_desc->word2.bits32);
13490 +       printk("ack %x, w4 %x\n", intr_curr_desc->word3.bits32,
13491 +               intr_curr_desc->word4.bits32);
13492 +}
13493 +
13494 +/*---------------------------------------------------------------------------
13495 + * This routine will initialize a TOE matching rule
13496 + * called by SL351x GMAC driver.
13497 + *-------------------------------------------------------------------------*/
13498 +void sl351x_toe_init(void)
13499 +{
13500 +       GMAC_MRxCR0_T   mrxcr0;
13501 +       GMAC_MRxCR1_T   mrxcr1;
13502 +       GMAC_MRxCR2_T   mrxcr2;
13503 +       int     rule, rc;
13504 +
13505 +       if (toe_initialized)
13506 +               return;
13507 +
13508 +       toe_initialized = 1;
13509 +
13510 +#ifndef CONFIG_SL351x_NAT
13511 +       mrxcr0.bits32 = 0;
13512 +       mrxcr1.bits32 = 0;
13513 +       mrxcr2.bits32 = 0;
13514 +       mrxcr0.bits.l3 = 1;
13515 +       mrxcr0.bits.l4 = 1;
13516 +       mrxcr1.bits.sip = 1;
13517 +       mrxcr1.bits.dip = 1;
13518 +       mrxcr1.bits.l4_byte0_15 = 0x0f;
13519 +       mrxcr0.bits.sprx = 1;
13520 +       rule = 0;
13521 +       rc = mac_set_rule_reg(0, rule, 1, mrxcr0.bits32, mrxcr1.bits32,
13522 +                                               mrxcr2.bits32);
13523 +       if (rc<0) {
13524 +               printk("%s::Set MAC 0 rule fail!\n", __func__);
13525 +       }
13526 +       rc = mac_set_rule_reg(1, rule, 1, mrxcr0.bits32, mrxcr1.bits32,
13527 +                                               mrxcr2.bits32);
13528 +       if (rc<0) {
13529 +               printk("%s::Set MAC 1 rule fail!\n", __func__);
13530 +       }
13531 +#endif // CONFIG_SL351x_NAT
13532 +}
13533 +
13534 +/*---------------------------------------------------------------------------
13535 + * dump_intrq_desc
13536 + * assign an interrupt queue number to a give tcp queue
13537 + *-------------------------------------------------------------------------*/
13538 +int get_interrupt_queue_id(int tcp_qid)
13539 +{
13540 +       return (int)(tcp_qid & 0x0003);
13541 +}
13542 +
13543 +/*---------------------------------------------------------------------------
13544 + * reset_connection_index
13545 + * reset the connection bit by given index
13546 + *-------------------------------------------------------------------------*/
13547 +void reset_connection_index(__u8 index)
13548 +{
13549 +       __u32 mask = ~(0xffffffff & (1<< (index&0x1f)));
13550 +       toe_connection_bits[index>>5] = toe_connection_bits[index>>5] & mask;
13551 +}
13552 +
13553 +/*---------------------------------------------------------------------------
13554 + * update_timer
13555 + *-------------------------------------------------------------------------*/
13556 +void update_timer(struct toe_conn* connection)
13557 +{
13558 +//     if (time_before(jiffies, connection->last_rx_jiffies+3))
13559 +//     if ((jiffies + 0xffffffff - connection->last_rx_jiffies) & 0x3)
13560 +//     if (connection->last_rx_jiffies > jiffies)
13561 +//             printk("%s::jif %g, last_rx_jif %g\n", __func__, jiffies, connection->last_rx_jiffies);
13562 +/*     if ((long)(jiffies + 2)< 3) { // overflow...
13563 +               printk("%s::jiffies %x\n", __func__, jiffies);
13564 +       } */
13565 +//     if ((long)(jiffies - connection->last_rx_jiffies)< 2)
13566 +//             return;
13567 +       connection->last_rx_jiffies = jiffies;
13568 +       // gary chen mod_timer(&connection->rx_timer, jiffies+2);
13569 +       connection->rx_timer.expires = jiffies + 2;
13570 +       add_timer(&connection->rx_timer);
13571 +//     printk("%s::nt %x, lj %x\n", __func__, (jiffies+2), connection->last_rx_jiffies);
13572 +}
13573 +
13574 +/*---------------------------------------------------------------------------
13575 + * gen_pure_ack
13576 + *-------------------------------------------------------------------------*/
13577 +struct sk_buff* gen_pure_ack(struct toe_conn* connection, TOE_QHDR_T* toe_qhdr,
13578 +INTR_QHDR_T *intr_curr_desc)
13579 +{
13580 +       struct sk_buff  *skb;
13581 +       struct iphdr    *ip_hdr;
13582 +       struct tcphdr   *tcp_hdr;
13583 +       struct ethhdr   *eth_hdr;
13584 +
13585 +       if ((skb= dev_alloc_skb(RX_BUF_SIZE))==NULL) {
13586 +               printk("%s::alloc pure ack fail!\n", __func__);
13587 +               return NULL;
13588 +       }
13589 +       skb_reserve(skb, RX_INSERT_BYTES);
13590 +       memset(skb->data, 0, 60);
13591 +
13592 +       eth_hdr = (struct ethhdr*)&(skb->data[0]);
13593 +       memcpy(eth_hdr, &connection->l2_hdr, sizeof(struct ethhdr));
13594 +
13595 +       ip_hdr = (struct iphdr*)&(skb->data[14]);
13596 +       ip_hdr->version = connection->ip_ver;
13597 +       ip_hdr->ihl = 20>>2;
13598 +       ip_hdr->tot_len = ntohs(40);
13599 +       ip_hdr->frag_off = htons(IP_DF);
13600 +       ip_hdr->ttl = 128;
13601 +       ip_hdr->protocol = 0x06;
13602 +       ip_hdr->saddr = connection->saddr[0];
13603 +       ip_hdr->daddr = connection->daddr[0];
13604 +//     printk("%s ip sa %x, da %x\n",
13605 +//             __func__, ntohl(ip_hdr->saddr), ntohl(ip_hdr->daddr));
13606 +
13607 +       tcp_hdr = (struct tcphdr*)&(skb->data[34]);
13608 +       tcp_hdr->source = connection->source;
13609 +       tcp_hdr->dest = connection->dest;
13610 +       if (intr_curr_desc) {
13611 +               tcp_hdr->seq = htonl(intr_curr_desc->word2.seq_num);
13612 +               tcp_hdr->ack_seq = htonl(intr_curr_desc->word3.ack_num);
13613 +               tcp_hdr->window = htons(intr_curr_desc->word0.bits.win_size);
13614 +       } else {
13615 +               tcp_hdr->seq = htonl(toe_qhdr->word3.seq_num);
13616 +               tcp_hdr->ack_seq = htonl(toe_qhdr->word4.ack_num);
13617 +               tcp_hdr->window = htons(toe_qhdr->word6.bits.WinSize);
13618 +       }
13619 +       tcp_hdr->ack = 1;
13620 +       tcp_hdr->doff = 20 >> 2;
13621 +#if 0
13622 +       if (!intr_curr_desc) {
13623 +               unsigned char byte;
13624 +               for (i=0; i<20; i++) {
13625 +                       byte = skb->data[34+i];
13626 +                       printk("%x ", byte);
13627 +               }
13628 +               printk("\n");
13629 +       }
13630 +#endif
13631 +       TCP_SKB_CB(skb)->connection = connection;
13632 +       return skb;
13633 +}
13634 +
13635 +/*---------------------------------------------------------------------------
13636 + * connection_rx_timer
13637 + *-------------------------------------------------------------------------*/
13638 +void connection_rx_timer(unsigned long *data)
13639 +{
13640 +       struct toe_conn *connection = (struct toe_conn*)data;
13641 +       unsigned int    tcp_qid, toeq_wptr;
13642 +       unsigned int    pkt_size, desc_count;
13643 +       struct sk_buff  *skb;
13644 +       GMAC_RXDESC_T   *toe_curr_desc;
13645 +       TOE_QHDR_T      *toe_qhdr;
13646 +       struct net_device       *dev;
13647 +       unsigned long   conn_flags;
13648 +       DMA_RWPTR_T             toeq_rwptr;
13649 +       unsigned short  timeout_descs;
13650 +
13651 +       if (in_toe_isr)
13652 +               printk("%s::in_toe_isr=%d!\n", __func__, in_toe_isr);
13653 +
13654 +       if (connection) {
13655 +               /* should we disable gmac interrupt first? */
13656 +               if (!connection->gmac)
13657 +                       printk("%s::conn gmac %x!\n", __func__, (u32)connection->gmac);
13658 +               local_irq_save(conn_flags);
13659 +               if (!spin_trylock(&connection->conn_lock)) {
13660 +                       local_irq_restore(conn_flags);
13661 +                       // timer should be updated by the toeq isr. So no need to update here.
13662 +                       printk("%s::conn_lock is held by ISR!\n", __func__);
13663 +                       return;
13664 +               }
13665 +               disable_irq(connection->gmac->irq);
13666 +
13667 +               /* disable hash entry and get toeq desc. */
13668 +               hash_set_valid_flag(connection->hash_entry_index, 0);
13669 +               do{} while(0);  /* wait until HW finish */
13670 +
13671 +               dev = connection->dev;
13672 +               if (!dev)
13673 +                       printk("%s::conn dev NULL!\n", __func__);
13674 +               tcp_qid = connection->qid;
13675 +               toe_qhdr = (TOE_QHDR_T *)(TOE_TOE_QUE_HDR_BASE +
13676 +                             tcp_qid * sizeof(TOE_QHDR_T));
13677 +               toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
13678 +               toeq_wptr = toe_qhdr->word1.bits.wptr;
13679 +               timeout_descs = toeq_wptr - toeq_rwptr.bits.rptr;
13680 +
13681 +               if (toeq_rwptr.bits.rptr == toeq_wptr) {
13682 +                       if (toe_qhdr->word5.bits32) {
13683 +                               // shall we check toe_qhdr->word2.bits?
13684 +                               skb = gen_pure_ack(connection, toe_qhdr, (INTR_QHDR_T *)NULL);
13685 +                               skb_put(skb, 54);
13686 +                               skb->dev = connection->dev;
13687 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
13688 +                               skb->protocol = eth_type_trans(skb, connection->dev);
13689 +                               netif_rx(skb);
13690 +                               connection->dev->last_rx = jiffies;
13691 +                       }
13692 +               } else {
13693 +                       while (toeq_rwptr.bits.rptr != toeq_rwptr.bits.wptr) {
13694 +                               /* we just simply send those packets to tcp? */
13695 +                               toe_curr_desc = (GMAC_RXDESC_T*)(toe_private_data.toe_desc_base[tcp_qid]
13696 +                                       + toeq_rwptr.bits.rptr * sizeof(GMAC_RXDESC_T));
13697 +                               connection->curr_desc = toe_curr_desc;
13698 +                               if (toe_curr_desc->word3.bits.ctrl_flag) {
13699 +                                       printk("%s::ctrl flag! %x, conn rptr %d, to %d, jif %x, conn_jif %x\n",
13700 +                                               __func__, toe_curr_desc->word3.bits32,
13701 +                                               connection->toeq_rwptr.bits.rptr, timeout_descs,
13702 +                                               (u32)jiffies, (u32)connection->last_rx_jiffies);
13703 +                               }
13704 +                               desc_count = toe_curr_desc->word0.bits.desc_count;
13705 +                               pkt_size = toe_curr_desc->word1.bits.byte_count;
13706 +                               consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
13707 +                                       PCI_DMA_FROMDEVICE);
13708 +                               skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr)-
13709 +                                       SKB_RESERVE_BYTES));
13710 +                               _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x02);
13711 +                               connection->curr_rx_skb = skb;
13712 +                               skb_reserve(skb, RX_INSERT_BYTES);
13713 +                               skb_put(skb, pkt_size);
13714 +                               skb->dev = dev;
13715 +                               skb->protocol = eth_type_trans(skb, dev);
13716 +                               {
13717 +                                       struct iphdr* ip_hdr = (struct iphdr*)&(skb->data[0]);
13718 +                                       if (toe_curr_desc->word3.bits.ctrl_flag)
13719 +                                               printk("%s::ip id %x\n", __func__, ntohs(ip_hdr->id));
13720 +                               }
13721 +                               skb->ip_summed = CHECKSUM_UNNECESSARY;
13722 +
13723 +                               netif_rx(skb);
13724 +                               dev->last_rx = jiffies;
13725 +#if 0
13726 +                               if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
13727 +                                       printk("%s::alloc buf fail!\n", __func__);
13728 +                               }
13729 +                               *(unsigned int*)(skb->data) = (unsigned int)skb;
13730 +                               connection->curr_rx_skb = skb;
13731 +                               skb_reserve(skb, SKB_RESERVE_BYTES);
13732 +                               spin_lock_irqsave(&connection->gmac->rx_mutex, flags);
13733 +                               fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
13734 +                               if (toe_private_data.fq_rx_rwptr.bits.wptr != fq_rwptr.bits.wptr) {
13735 +                                       mac_stop_txdma((struct net_device*)connection->dev);
13736 +                                       spin_unlock_irqrestore(&connection->gmac->rx_mutex, flags);
13737 +                                       while(1);
13738 +                               }
13739 +                               fq_desc = (GMAC_RXDESC_T*)toe_private_data.swfq_desc_base + fq_rwptr.bits.wptr;
13740 +                               fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
13741 +                               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
13742 +                               SET_WPTR(TOE_GLOBAL_BASE+GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
13743 +                               toe_private_data.fq_rx_rwptr.bits32 = fq_rwptr.bits32;
13744 +                               spin_unlock_irqrestore(&connection->gmac->rx_mutex, flags);
13745 +#endif
13746 +//                             spin_lock_irqsave(&connection->gmac->rx_mutex, flags);
13747 +                               toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
13748 +                               SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
13749 +//                             spin_unlock_irqrestore(&connection->gmac->rx_mutex, flags);
13750 +                               connection->toeq_rwptr.bits32 = toeq_rwptr.bits32;
13751 +                       }
13752 +                       toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
13753 +//                     toe_gmac_fill_free_q();
13754 +               }
13755 +               connection->last_rx_jiffies = jiffies;
13756 +               if (connection->status != TCP_CONN_CLOSED)
13757 +                       mod_timer(&connection->rx_timer, jiffies+2);
13758 +               if (connection->status != TCP_CONN_ESTABLISHED)
13759 +                       printk("%s::conn status %x\n", __func__, connection->status);
13760 +               hash_set_valid_flag(connection->hash_entry_index, 1);
13761 +               enable_irq(connection->gmac->irq);
13762 +               // Gary Chen spin_unlock_irqrestore(&connection->conn_lock, conn_flags);
13763 +       }
13764 +}
13765 +
13766 +/*---------------------------------------------------------------------------
13767 + * free_toeq_descs
13768 + *-------------------------------------------------------------------------*/
13769 +void free_toeq_descs(int qid, TOE_INFO_T *toe)
13770 +{
13771 +       void    *desc_ptr;
13772 +
13773 +       desc_ptr = (void*)toe->toe_desc_base[qid];
13774 +       pci_free_consistent(NULL, TOE_TOE_DESC_NUM*sizeof(GMAC_RXDESC_T), desc_ptr,
13775 +          (dma_addr_t)toe->toe_desc_base_dma[qid]);
13776 +       toe->toe_desc_base[qid] = 0;
13777 +}
13778 +
13779 +/*---------------------------------------------------------------------------
13780 + * set_toeq_hdr
13781 + *-------------------------------------------------------------------------*/
13782 +void set_toeq_hdr(struct toe_conn*     connection, TOE_INFO_T* toe, struct net_device *dev)
13783 +{
13784 +       volatile TOE_QHDR_T     *toe_qhdr;
13785 +       volatile unsigned int   toeq_wptr; // toeq_rptr
13786 +       volatile GMAC_RXDESC_T  *toe_curr_desc;
13787 +       struct sk_buff  *skb;
13788 +       unsigned int    pkt_size;
13789 +       DMA_RWPTR_T     toeq_rwptr;
13790 +
13791 +       if (connection->status == TCP_CONN_CLOSING) {
13792 +               connection->status = TCP_CONN_CLOSED;
13793 +               hash_set_valid_flag(connection->hash_entry_index, 0);
13794 +               // remove timer first.
13795 +               // del_timer_sync(&(connection->rx_timer));
13796 +               // check if any queued frames last time.
13797 +               toe_qhdr = (volatile TOE_QHDR_T*)TOE_TOE_QUE_HDR_BASE;
13798 +               toe_qhdr += connection->qid;
13799 +               toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
13800 +
13801 +               //toeq_rptr = toe_qhdr->word1.bits.rptr;
13802 +               toeq_wptr = toe_qhdr->word1.bits.wptr;
13803 +               while (toeq_rwptr.bits.rptr != toeq_wptr) {
13804 +                       printk("%s::pending frames in TOE Queue before closing!\n", __func__);
13805 +                       toe_curr_desc = (GMAC_RXDESC_T*)(toe->toe_desc_base[connection->qid] +
13806 +                               toe_qhdr->word1.bits.rptr*sizeof(GMAC_RXDESC_T));
13807 +                       connection->curr_desc = (GMAC_RXDESC_T *)toe_curr_desc;
13808 +                       pkt_size = toe_curr_desc->word1.bits.byte_count;
13809 +                       consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
13810 +                               PCI_DMA_FROMDEVICE);
13811 +                       skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr) -
13812 +                               SKB_RESERVE_BYTES));
13813 +                       _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x03);
13814 +                       connection->curr_rx_skb = skb;
13815 +                       skb_reserve(skb, RX_INSERT_BYTES);
13816 +                       skb_put(skb, pkt_size);
13817 +                       skb->dev = connection->dev;
13818 +                       skb->protocol = eth_type_trans(skb, connection->dev);
13819 +                       skb->ip_summed = CHECKSUM_UNNECESSARY;
13820 +                       netif_rx(skb);
13821 +                       connection->dev->last_rx = jiffies;
13822 +
13823 +                       toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
13824 +                       SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
13825 +               }
13826 +               free_toeq_descs(connection->qid, toe);
13827 +               // shall we re-fill free queue?
13828 +
13829 +               reset_connection_index(connection->qid);
13830 +               //memset(connection, 0, sizeof(struct toe_conn));
13831 +               printk(" del timer and close connection %x, qid %d\n", (u32)connection, connection->qid);
13832 +               return;
13833 +       }
13834 +       /* enable or setup toe queue header */
13835 +       if (connection->status == TCP_CONN_CONNECTING && storlink_ctl.rx_max_pktsize) {
13836 +               volatile TOE_QHDR_T     *qhdr;
13837 +               int iq_id;
13838 +               connection->status = TCP_CONN_ESTABLISHED;
13839 +               qhdr = (volatile TOE_QHDR_T*)((unsigned int)TOE_TOE_QUE_HDR_BASE +
13840 +                              connection->qid * sizeof(TOE_QHDR_T));
13841 +
13842 +               iq_id = get_interrupt_queue_id(connection->qid);
13843 +               connection->dev = dev;
13844 +               connection->gmac = dev->priv;
13845 +               connection->toeq_rwptr.bits32 = 0;
13846 +
13847 +//             qhdr->word6.bits.iq_num = iq_id;
13848 +               qhdr->word6.bits.MaxPktSize = (connection->max_pktsize)>>2; // in word.
13849 +               qhdr->word7.bits.AckThreshold = connection->ack_threshold;
13850 +               qhdr->word7.bits.SeqThreshold = connection->seq_threshold;
13851 +
13852 +               // init timer.
13853 +#if 1
13854 +               init_timer(&connection->rx_timer);
13855 +               connection->rx_timer.expires = jiffies + 5;
13856 +               connection->rx_timer.data = (unsigned long)connection;
13857 +               connection->rx_timer.function = (void *)&connection_rx_timer;
13858 +               add_timer(&connection->rx_timer);
13859 +               connection->last_rx_jiffies = jiffies;
13860 +               printk("init_timer %x\n", (u32)jiffies);
13861 +#endif
13862 +               hash_set_valid_flag(connection->hash_entry_index, 1);
13863 +               return;
13864 +       } else {
13865 +               printk("%s::conn status %x, rx_pktsize %d\n",
13866 +                       __func__, connection->status, storlink_ctl.rx_max_pktsize);
13867 +       }
13868 +}
13869 +
13870 +/*---------------------------------------------------------------------------
13871 + * get_connection_index
13872 + * get_connection_index will find an available index for the connection,
13873 + * when allocate a new connection is needed.
13874 + * we find available Qid from AV bits and write to hash_table, so that when RxTOE
13875 + * packet is received, sw_id from ToeQ descriptor is also the Qid of conneciton Q.
13876 + *-------------------------------------------------------------------------*/
13877 +int get_connection_index(void)
13878 +{
13879 +       int i=0, j=0, index=-1;
13880 +       __u32   connection_bits;
13881 +
13882 +       for (i = 0; i< TOE_TOE_QUEUE_NUM/32; i++) {
13883 +               connection_bits = ~(toe_connection_bits[i]);
13884 +               if (connection_bits == 0)
13885 +                       // all 32 bits are used.
13886 +                       continue;
13887 +
13888 +               for (j=0; j<32; j++) {
13889 +                       if (connection_bits & 0x01) {
13890 +                               index = i*32 + j;
13891 +                               return index;
13892 +                       }
13893 +                       connection_bits = connection_bits >> 1;
13894 +               }
13895 +       }
13896 +       return index;
13897 +}
13898 +
13899 +/*---------------------------------------------------------------------------
13900 + * set_toe_connection
13901 + *-------------------------------------------------------------------------*/
13902 +void set_toe_connection(int index, int val)
13903 +{
13904 +       if (val) {
13905 +               toe_connection_bits[index/32] |= (1<<(index%32));
13906 +       } else {
13907 +               toe_connection_bits[index/32] &= (~(1<<(index%32)));
13908 +       }
13909 +}
13910 +
13911 +/*---------------------------------------------------------------------------
13912 + * sl351x_get_toe_conn_flag
13913 + *-------------------------------------------------------------------------*/
13914 +int sl351x_get_toe_conn_flag(int index)
13915 +{
13916 +       if (index < TOE_TOE_QUEUE_NUM)
13917 +               return (toe_connection_bits[index/32] & (1 << (index %32)));
13918 +       else
13919 +               return 0;
13920 +}
13921 +
13922 +/*---------------------------------------------------------------------------
13923 + * sl351x_get_toe_conn_info
13924 + *-------------------------------------------------------------------------*/
13925 +struct toe_conn * sl351x_get_toe_conn_info(int index)
13926 +{
13927 +       if (index < TOE_TOE_QUEUE_NUM)
13928 +               return (struct toe_conn *)&toe_connections[index];
13929 +       else
13930 +               return NULL;
13931 +}
13932 +
13933 +/*---------------------------------------------------------------------------
13934 + * create_sw_toe_connection
13935 + *-------------------------------------------------------------------------*/
13936 +struct toe_conn* create_sw_toe_connection(int qid, int ip_ver, void* ip_hdr,
13937 +       struct tcphdr* tcp_hdr)
13938 +{
13939 +       struct toe_conn*        connection =  &(toe_connections[qid]);
13940 +
13941 +       connection->ip_ver = (__u8)ip_ver;
13942 +       connection->qid = (__u8)qid;
13943 +       connection->source = (__u16)tcp_hdr->source;
13944 +       connection->dest = (__u16)tcp_hdr->dest;
13945 +       if (ip_ver == 4) {
13946 +               struct iphdr* iph = (struct iphdr*) ip_hdr;
13947 +               connection->saddr[0] = (__u32)iph->saddr;
13948 +               connection->daddr[0] = (__u32)iph->daddr;
13949 +//             printk("%s::saddr %x, daddr %x\n", __func__,
13950 +//                     ntohl(connection->saddr[0]), ntohl(connection->daddr[0]));
13951 +       } else if (ip_ver == 6) {
13952 +               struct ipv6hdr *iph = (struct ipv6hdr*)ip_hdr;
13953 +               int i=0;
13954 +               for (i=0; i<4; i++) {
13955 +                       connection->saddr[i] = (__u32)iph->saddr.in6_u.u6_addr32[i];
13956 +                       connection->daddr[i] = (__u32)iph->daddr.in6_u.u6_addr32[i];
13957 +               }
13958 +       }
13959 +       connection->status = TCP_CONN_CREATION;
13960 +       return connection;
13961 +}
13962 +
13963 +/*---------------------------------------------------------------------------
13964 + * fill_toeq_buf
13965 + *-------------------------------------------------------------------------*/
13966 +int fill_toeq_buf(int index, TOE_INFO_T* toe)
13967 +{
13968 +       volatile TOE_QHDR_T     *qhdr;
13969 +       //struct toe_conn* connection;
13970 +       GMAC_RXDESC_T   *desc_ptr;
13971 +
13972 +       if (!toe->toe_desc_base[index]) {
13973 +               // first time. init.
13974 +               desc_ptr = (GMAC_RXDESC_T*)(pci_alloc_consistent(NULL, TOE_TOE_DESC_NUM
13975 +                           *sizeof(GMAC_RXDESC_T), (dma_addr_t*)&toe->toe_desc_base_dma[index]));
13976 +
13977 +               toe->toe_desc_num = TOE_TOE_DESC_NUM;
13978 +               toe->toe_desc_base[index] = (unsigned int)desc_ptr;
13979 +       }
13980 +       qhdr = (volatile TOE_QHDR_T*)((unsigned int)TOE_TOE_QUE_HDR_BASE +
13981 +                                                                       index*sizeof(TOE_QHDR_T));
13982 +       //connection = (struct toe_conn*)&(toe_connections[index]);
13983 +
13984 +       qhdr->word0.base_size = ((unsigned int)toe->toe_desc_base_dma[index]&TOE_QHDR0_BASE_MASK)
13985 +                                       | TOE_TOE_DESC_POWER;
13986 +       qhdr->word1.bits32 = 0;
13987 +       qhdr->word2.bits32 = 0;
13988 +       qhdr->word3.bits32 = 0;
13989 +       qhdr->word4.bits32 = 0;
13990 +       qhdr->word5.bits32 = 0;
13991 +       return 1;
13992 +}
13993 +
13994 +/*---------------------------------------------------------------------------
13995 + * create_toe_hash_entry_smb
13996 + * add SMB header in hash entry.
13997 + *-------------------------------------------------------------------------*/
13998 +int create_toe_hash_entry_smb(int ip_ver, void* ip_hdr, struct tcphdr* tcp_hdr,
13999 +       int sw_id)
14000 +{
14001 +       HASH_ENTRY_T    hash_entry, *entry;
14002 +       int     hash_entry_index;
14003 +       int i;
14004 +
14005 +       entry = (HASH_ENTRY_T*)&hash_entry;
14006 +       memset((void*)entry, 0, sizeof(HASH_ENTRY_T));
14007 +       entry->rule = 0;
14008 +
14009 +       /* enable fields of hash key */
14010 +       entry->key_present.ip_protocol = 1;
14011 +       entry->key_present.sip = 1;
14012 +       entry->key_present.dip = 1;
14013 +       entry->key_present.l4_bytes_0_3 = 1;    // src port and dest port
14014 +       entry->key_present.l7_bytes_0_3 = 0;    // do we need to enable NETBIOS? how?
14015 +       entry->key_present.l7_bytes_4_7 = 1;    // "SMB" header
14016 +
14017 +       /* hash key */
14018 +       entry->key.ip_protocol = IPPROTO_TCP;
14019 +       if (ip_ver == 4) {
14020 +               struct iphdr *iph = (struct iphdr*)ip_hdr;
14021 +               memcpy(entry->key.sip, &iph->saddr, 4);
14022 +               memcpy(entry->key.dip, &iph->daddr, 4);
14023 +       } else if (ip_ver == 6) {
14024 +               struct ipv6hdr *iph = (struct ipv6hdr*)ip_hdr;
14025 +               for (i=0; i<4; i++) {
14026 +                       memcpy(&(entry->key.sip[i*4]), &(iph->saddr.in6_u.u6_addr32[i]), 4);
14027 +                       memcpy(&(entry->key.dip[i*4]), &(iph->daddr.in6_u.u6_addr32[i]), 4);
14028 +               }
14029 +       }
14030 +       *(__u16*)&entry->key.l4_bytes[0] = tcp_hdr->source;
14031 +       *(__u16*)&entry->key.l4_bytes[2] = tcp_hdr->dest;
14032 +
14033 +       entry->key.l7_bytes[4] = 0xff;
14034 +       entry->key.l7_bytes[5] = 0x53;
14035 +       entry->key.l7_bytes[6] = 0x4d;
14036 +       entry->key.l7_bytes[7] = 0x42;
14037 +
14038 +       /* action of hash entry match */
14039 +       entry->action.sw_id = 1;
14040 +       entry->action.dest_qid = (__u8)TOE_TOE_QID(sw_id);
14041 +       entry->action.srce_qid = 0;
14042 +       hash_entry_index = hash_add_toe_entry(entry);
14043 +
14044 +       return hash_entry_index;
14045 +}
14046 +
14047 +// best performance of tcp streaming.
14048 +/*---------------------------------------------------------------------------
14049 + * create_toe_hash_entry_smb
14050 + * add SMB header in hash entry.
14051 + *-------------------------------------------------------------------------*/
14052 +int create_toe_hash_entry_ftp(int ip_ver, void* ip_hdr, struct tcphdr* tcphdr)
14053 +{
14054 +       return 0;
14055 +}
14056 +
14057 +// is hash entry for nfs needed?
14058 +
14059 +/*
14060 + * Create a TOE hash entry by given ip addresses and tcp port numbers.
14061 + * hash entry index will be saved in sw connection.
14062 + */
14063 +/*---------------------------------------------------------------------------
14064 + * create_toe_hash_entry
14065 + *-------------------------------------------------------------------------*/
14066 +int create_toe_hash_entry(int ip_ver, void* ip_hdr, struct tcphdr* tcp_hdr, int sw_id)
14067 +{
14068 +       HASH_ENTRY_T    hash_entry, *entry;
14069 +//     unsigned long   hash_key[HASH_MAX_DWORDS];
14070 +       int     hash_entry_index;
14071 +
14072 +       entry = (HASH_ENTRY_T*) &hash_entry;
14073 +       memset((void*)entry, 0, sizeof(HASH_ENTRY_T));
14074 +       entry->rule = 0;
14075 +       /* enable fields of hash key */
14076 +       entry->key_present.ip_protocol = 1;
14077 +       entry->key_present.sip = 1;
14078 +       entry->key_present.dip = 1;
14079 +       entry->key_present.l4_bytes_0_3 = 1;    // src port and dest port
14080 +
14081 +       /* hash key */
14082 +       entry->key.ip_protocol = IPPROTO_TCP;
14083 +       if (ip_ver == 4) {
14084 +               // key of ipv4
14085 +               struct iphdr* iph = (struct iphdr*)ip_hdr;
14086 +               memcpy(entry->key.sip, &iph->saddr, 4);
14087 +               memcpy(entry->key.dip, &iph->daddr, 4);
14088 +       } else if (ip_ver == 6) {
14089 +               // key of ipv6
14090 +               int i=0;
14091 +               struct ipv6hdr *iph = (struct ipv6hdr*)ip_hdr;
14092 +               for (i=0; i<4; i++) {
14093 +                       memcpy(&(entry->key.sip[i*4]), &(iph->saddr.in6_u.u6_addr32[i]), 4);
14094 +                       memcpy(&(entry->key.dip[i*4]), &(iph->daddr.in6_u.u6_addr32[i]), 4);
14095 +               }
14096 +       }
14097 +       *(__u16*)&entry->key.l4_bytes[0] = tcp_hdr->source;
14098 +       *(__u16*)&entry->key.l4_bytes[2] = tcp_hdr->dest;
14099 +       // is it necessary to write ip version to hash key?
14100 +
14101 +       /* action of hash entry match */
14102 +       entry->action.sw_id = 1;
14103 +       entry->action.dest_qid = (__u8)TOE_TOE_QID(sw_id);
14104 +       entry->action.srce_qid = 0;     // 0 for SW FreeQ. 1 for HW FreeQ.
14105 +       hash_entry_index = hash_add_toe_entry(entry);
14106 +//     printk("\n%s. sw_id %d, hash_entry index %x\n",
14107 +//             __func__, TOE_TOE_QID(sw_id), hash_entry_index);
14108 +       return hash_entry_index;
14109 +}
14110 +
14111 +/*---------------------------------------------------------------------------
14112 + * init_toeq
14113 + * 1. Reserve a TOE Queue id first, to get the sw toe_connection.
14114 + * 2. Setup the hash entry with given iphdr and tcphdr, save hash entry index
14115 + *    in sw toe_connection.
14116 + * 3. Prepare sw toe_connection and allocate buffers.
14117 + * 4. Validate hash entry.
14118 + *-------------------------------------------------------------------------*/
14119 +struct toe_conn* init_toeq(int ipver, void* iph, struct tcphdr* tcp_hdr,
14120 +       TOE_INFO_T* toe, unsigned char* l2hdr)
14121 +{
14122 +//     printk("\t*** %s, ipver %d\n", __func__, ipver);
14123 +       int qid=-1;
14124 +       struct toe_conn* connection;
14125 +       int hash_entry_index;
14126 +       // int i=0;
14127 +       unsigned short  dest_port = ntohs(tcp_hdr->dest);
14128 +
14129 +       if (dest_port == 445) {
14130 +               printk("%s::SMB/CIFS connection\n", __func__);
14131 +       } else if (dest_port == 20) {
14132 +               printk("%s::ftp-data connection\n", __func__);
14133 +       } else if (dest_port == 2049) {
14134 +               printk("%s::nfs daemon connection\n", __func__);
14135 +       }
14136 +       qid = get_connection_index();
14137 +       if (qid<0)
14138 +               return 0;       // setup toeq failure
14139 +       set_toe_connection(qid, 1); // reserve this sw toeq.
14140 +
14141 +       //connection = (struct toe_conn*)&(toe_connections[qid]);
14142 +       hash_entry_index = create_toe_hash_entry(ipver, iph, tcp_hdr, qid);
14143 +       if (hash_entry_index <0) {
14144 +               printk("%s::release toe hash entry!\n", __func__);
14145 +               set_toe_connection(qid, 0); // release this sw toeq.
14146 +               return 0;
14147 +       }
14148 +       connection = create_sw_toe_connection(qid, ipver, iph, tcp_hdr);
14149 +       connection->hash_entry_index = (__u16) hash_entry_index;
14150 +
14151 +       fill_toeq_buf(qid, toe);
14152 +       memcpy(&connection->l2_hdr, l2hdr, sizeof(struct ethhdr));
14153 +       spin_lock_init(&connection->conn_lock);
14154 +
14155 +       return connection;
14156 +}
14157 +
14158 +#if 0
14159 +/*----------------------------------------------------------------------
14160 +*   toe_init_toe_queue
14161 +*   (1) Initialize the TOE Queue Header
14162 +*       Register: TOE_TOE_QUE_HDR_BASE (0x60003000)
14163 +*   (2) Initialize Descriptors of TOE Queues
14164 +*----------------------------------------------------------------------*/
14165 +void toe_init_toe_queue(TOE_INFO_T* toe)
14166 +{
14167 +}
14168 +EXPORT_SYMBOL(toe_init_toe_queue);
14169 +#endif
14170 +
14171 +/*---------------------------------------------------------------------------
14172 + * dump_jumbo_skb
14173 + *-------------------------------------------------------------------------*/
14174 +void dump_jumbo_skb(struct jumbo_frame *jumbo_skb)
14175 +{
14176 +       if (jumbo_skb->skb0) {
14177 +//             printk("%s. jumbo skb %x, len %d\n",
14178 +//                     __func__, jumbo_skb->skb0->data, jumbo_skb->skb0->len);
14179 +               netif_rx(jumbo_skb->skb0);
14180 +       }
14181 +       jumbo_skb->skb0 = 0;
14182 +       jumbo_skb->tail = 0;
14183 +       jumbo_skb->iphdr0 = 0;
14184 +       jumbo_skb->tcphdr0 = 0;
14185 +}
14186 +
14187 +/* ---------------------------------------------------------------------
14188 + * Append skb to skb0. skb0 is the jumbo frame that will be passed to
14189 + * kernel tcp.
14190 + * --------------------------------------------------------------------*/
14191 +void rx_append_skb(struct jumbo_frame *jumbo_skb, struct sk_buff* skb, int payload_len)
14192 +{
14193 +       struct iphdr* iphdr0 = (struct iphdr*)&(skb->data[0]);
14194 +       int ip_hdrlen = iphdr0->ihl << 2;
14195 +       struct tcphdr* tcphdr0 = (struct tcphdr*)&(skb->data[ip_hdrlen]);
14196 +
14197 +       if (!jumbo_skb->skb0) {
14198 +               // head of the jumbo frame.
14199 +               jumbo_skb->skb0 = skb;
14200 +               jumbo_skb->tail = 0;
14201 +               jumbo_skb->iphdr0 = iphdr0;
14202 +               jumbo_skb->tcphdr0 = tcphdr0;
14203 +       } else {
14204 +               if (!jumbo_skb->tail)
14205 +                       skb_shinfo(jumbo_skb->skb0)->frag_list = skb;
14206 +               else
14207 +                       (jumbo_skb->tail)->next = skb;
14208 +               jumbo_skb->tail = skb;
14209 +
14210 +               // do we need to change truesize as well?
14211 +               jumbo_skb->skb0->len += payload_len;
14212 +               jumbo_skb->skb0->data_len += payload_len;
14213 +
14214 +               jumbo_skb->iphdr0->tot_len = htons(ntohs(jumbo_skb->iphdr0->tot_len)+payload_len);
14215 +               jumbo_skb->tcphdr0->ack_seq = tcphdr0->ack_seq;
14216 +               jumbo_skb->tcphdr0->window = tcphdr0->window;
14217 +
14218 +               skb->len += payload_len;
14219 +               skb->data_len = 0;
14220 +               skb->data += ntohs(iphdr0->tot_len) - payload_len;
14221 +       }
14222 +}
14223 +
14224 +/*----------------------------------------------------------------------
14225 +* toe_gmac_handle_toeq
14226 +* (1) read interrupt Queue to get TOE Q.
14227 +* (2) get packet fro TOE Q and send to upper layer handler.
14228 +* (3) allocate new buffers and put to TOE Q. Intr Q buffer is recycled.
14229 +*----------------------------------------------------------------------*/
14230 +void toe_gmac_handle_toeq(struct net_device *dev, GMAC_INFO_T* tp, __u32 status)
14231 +{
14232 +       //volatile INTRQ_INFO_T *intrq_info;
14233 +       //TOEQ_INFO_T           *toeq_info;
14234 +       volatile NONTOE_QHDR_T  *intr_qhdr;
14235 +       volatile TOE_QHDR_T             *toe_qhdr;
14236 +       volatile INTR_QHDR_T    *intr_curr_desc;
14237 +       TOE_INFO_T      *toe = &toe_private_data;
14238 +
14239 +       volatile GMAC_RXDESC_T  *toe_curr_desc; // , *fq_desc;// *tmp_desc;
14240 +       volatile DMA_RWPTR_T    intr_rwptr, toeq_rwptr;  // fq_rwptr;
14241 +
14242 +       unsigned int    pkt_size, desc_count, tcp_qid;
14243 +       volatile unsigned int   toeq_wptr;
14244 +       struct toe_conn*                connection;
14245 +       int             i, frag_id = 0;
14246 +       // unsigned long        toeq_flags;
14247 +       struct jumbo_frame      jumbo_skb;
14248 +       struct sk_buff  *skb;
14249 +       __u32   interrupt_status;
14250 +
14251 +       in_toe_isr++;
14252 +
14253 +       interrupt_status = status >> 24;
14254 +       // get interrupt queue header
14255 +       intr_qhdr = (volatile NONTOE_QHDR_T*)TOE_INTR_Q_HDR_BASE;
14256 +       memset(&jumbo_skb, 0, sizeof(struct jumbo_frame));
14257 +
14258 +       for (i=0; i<TOE_INTR_QUEUE_NUM; i++, intr_qhdr++) {
14259 +               if (!(interrupt_status & 0x0001)) {
14260 +                       // no interrupt of this IntQ
14261 +                       interrupt_status = interrupt_status >> 1;
14262 +                       continue;
14263 +               }
14264 +               interrupt_status = interrupt_status >> 1;
14265 +               intr_rwptr.bits32 = readl(&intr_qhdr->word1);
14266 +
14267 +               while ( intr_rwptr.bits.rptr != intr_rwptr.bits.wptr) {
14268 +                       int max_pktsize = 1;
14269 +                       // get interrupt queue descriptor.
14270 +                       intr_curr_desc = (INTR_QHDR_T*)toe->intr_desc_base +
14271 +                               i* TOE_INTR_DESC_NUM + intr_rwptr.bits.rptr;
14272 +//                     printk("%s::int %x\n", __func__, intr_curr_desc->word1.bits32);
14273 +                       // get toeq id
14274 +                       tcp_qid = (u8)intr_curr_desc->word1.bits.tcp_qid - (u8)TOE_TOE_QID(0);
14275 +                       // get toeq queue header
14276 +                       toe_qhdr = (volatile TOE_QHDR_T*) TOE_TOE_QUE_HDR_BASE;
14277 +                       toe_qhdr += tcp_qid;
14278 +                       connection = &toe_connections[tcp_qid];
14279 +                       del_timer(&connection->rx_timer);
14280 +                       // Gary Chen spin_lock_irqsave(&connection->conn_lock, toeq_flags);
14281 +                       // handling interrupts of this TOE Q.
14282 +                       if (intr_curr_desc->word1.bits.ctl || intr_curr_desc->word1.bits.osq ||
14283 +                               intr_curr_desc->word1.bits.abn)
14284 +                               max_pktsize = 0;
14285 +                       if (!max_pktsize || intr_curr_desc->word1.bits.TotalPktSize) {
14286 +                               desc_count=0;
14287 +                               // wptr in intl queue is where this TOE interrupt should stop.
14288 +                               toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
14289 +                               toeq_wptr = intr_curr_desc->word0.bits.wptr;
14290 +                               if (connection->toeq_rwptr.bits.rptr != toeq_rwptr.bits.rptr)
14291 +                                       printk("conn rptr %d, hw rptr %d\n",
14292 +                                               connection->toeq_rwptr.bits.rptr, toeq_rwptr.bits.rptr);
14293 +
14294 +                               if (intr_curr_desc->word1.bits.ctl &&
14295 +                                       (toeq_rwptr.bits.rptr == toeq_wptr)) {
14296 +                                       printk("\nctrl frame, but not in TOE queue! conn rptr %d, hw wptr %d\n",
14297 +                                               connection->toeq_rwptr.bits.rptr, toeq_wptr);
14298 +//                                     dump_toe_qhdr(toe_qhdr);
14299 +//                                     dump_intrq_desc(intr_curr_desc);
14300 +                               }
14301 +                               // while (toeq_rwptr.bits.rptr != intr_curr_desc->word0.bits.wptr) {
14302 +                               while (toe_qhdr->word1.bits.rptr != intr_curr_desc->word0.bits.wptr) {
14303 +                                       frag_id++;
14304 +                                       toe_curr_desc = (volatile GMAC_RXDESC_T *)(toe->toe_desc_base[tcp_qid]
14305 +                                               + toe_qhdr->word1.bits.rptr *sizeof(GMAC_RXDESC_T));
14306 +                                       connection->curr_desc = (GMAC_RXDESC_T *)toe_curr_desc;
14307 +                                       desc_count = toe_curr_desc->word0.bits.desc_count;
14308 +                                       pkt_size = toe_curr_desc->word1.bits.byte_count;
14309 +                                       consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
14310 +                                               PCI_DMA_FROMDEVICE);
14311 +                                       skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr)-
14312 +                                               SKB_RESERVE_BYTES));
14313 +                                       _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x01);
14314 +                                       connection->curr_rx_skb = skb;
14315 +                                       skb_reserve(skb, RX_INSERT_BYTES);
14316 +                                       if ((skb->len + pkt_size) > (1514+16))
14317 +                                       {
14318 +                                               printk("skb->len=%d, pkt_size=%d\n",skb->len, pkt_size);
14319 +                                               while(1);
14320 +                                       }
14321 +
14322 +                                       skb_put(skb, pkt_size);
14323 +                                       skb->dev = dev;
14324 +                                       skb->protocol = eth_type_trans(skb, dev);
14325 +                                       skb->ip_summed = CHECKSUM_UNNECESSARY;
14326 +
14327 +                                       if (toe_curr_desc->word3.bits32 & 0x1b000000)
14328 +                                               dump_jumbo_skb(&jumbo_skb);
14329 +
14330 +                                       rx_append_skb(&jumbo_skb, skb, pkt_size-toe_curr_desc->word3.bits.l7_offset);
14331 +//                                     spin_lock_irqsave(&gmac_fq_lock, flags);
14332 +                                       toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
14333 +                                       SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
14334 +//                                     spin_unlock_irqrestore(&gmac_fq_lock, flags);
14335 +                                       if (storlink_ctl.fqint_threshold)
14336 +                                               continue;
14337 +#if 0
14338 +//#if (HANDLE_FREEQ_METHOD == HANDLE_FREEQ_INDIVIDUAL)
14339 +                                       if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
14340 +                                               printk("%s::toe queue alloc buffer ", __func__);
14341 +                                       }
14342 +                                       *(unsigned int*)(skb->data) = (unsigned int)skb;
14343 +                                       connection->curr_rx_skb = skb;
14344 +                                       skb_reserve(skb, SKB_RESERVE_BYTES);
14345 +
14346 +                                       spin_lock_irqsave(&gmac_fq_lock, flags);
14347 +                                       fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
14348 +                                       if (toe->fq_rx_rwptr.bits.wptr != fq_rwptr.bits.wptr) {
14349 +                                               printk("%s::fq_rx_rwptr %x\n", __func__, toe->fq_rx_rwptr.bits32);
14350 +                                               mac_stop_txdma((struct net_device*) tp->dev);
14351 +                                               spin_unlock_irqrestore(&gmac_fq_lock, flags);
14352 +                                               while(1);
14353 +                                       }
14354 +                                       fq_desc = (GMAC_RXDESC_T*)toe->swfq_desc_base + fq_rwptr.bits.wptr;
14355 +                                       fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
14356 +
14357 +                                       fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
14358 +                                       SET_WPTR(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
14359 +                                       toe->fq_rx_rwptr.bits32 = fq_rwptr.bits32;
14360 +                                       spin_unlock_irqrestore(&gmac_fq_lock, flags);
14361 +#endif
14362 +                               } // end of this multi-desc.
14363 +                               dump_jumbo_skb(&jumbo_skb);
14364 +                               dev->last_rx = jiffies;
14365 +                               connection->toeq_rwptr.bits32 = toeq_rwptr.bits32;
14366 +                       } else if (intr_curr_desc->word1.bits.sat) {
14367 +                               toeq_rwptr.bits32 = readl(&toe_qhdr->word1);
14368 +                               toeq_wptr = intr_curr_desc->word0.bits.wptr;
14369 +                               if (connection->toeq_rwptr.bits.rptr != toeq_rwptr.bits.rptr)
14370 +                                       printk("SAT. conn rptr %d, hw rptr %d\n",
14371 +                                               connection->toeq_rwptr.bits.rptr, toeq_rwptr.bits.rptr);
14372 +/*
14373 +                                       printk("%s::SAT int!, ackcnt %x, seqcnt %x, rptr %d, wptr %d, ack %x, qhack %x\n",
14374 +                                               __func__, intr_curr_desc->word4.bits.AckCnt, intr_curr_desc->word4.bits.SeqCnt,
14375 +                                               toeq_rptr, toeq_wptr, intr_curr_desc->word3.ack_num, toe_qhdr->word4.ack_num);*/
14376 +                               /* pure ack */
14377 +                               if (toeq_rwptr.bits.rptr == toeq_wptr) {
14378 +                                       if (intr_curr_desc->word4.bits32) {
14379 +                                               skb = gen_pure_ack(connection, (TOE_QHDR_T *)toe_qhdr, (INTR_QHDR_T *)intr_curr_desc);
14380 +                                               skb_put(skb, 60);
14381 +                                               skb->dev = connection->dev;
14382 +                                               skb->ip_summed = CHECKSUM_UNNECESSARY;
14383 +                                               skb->protocol = eth_type_trans(skb, connection->dev);
14384 +                                               netif_rx(skb);
14385 +                                       } else
14386 +                                               printk("%s::SAT Interrupt!. But cnt is 0!\n", __func__);
14387 +                               } else {
14388 +                                       // while (toeq_rwptr.bits.rptr != toeq_wptr) {
14389 +                                       while (toe_qhdr->word1.bits.rptr != intr_curr_desc->word0.bits.wptr) {
14390 +                                               toe_curr_desc = (volatile GMAC_RXDESC_T*)(toe->toe_desc_base[tcp_qid]
14391 +                                                       + toe_qhdr->word1.bits.rptr * sizeof(GMAC_RXDESC_T));
14392 +                                               connection->curr_desc = (GMAC_RXDESC_T *)toe_curr_desc;
14393 +                                               desc_count = toe_curr_desc->word0.bits.desc_count;
14394 +                                               pkt_size = toe_curr_desc->word1.bits.byte_count;
14395 +                                               consistent_sync((void*)__va(toe_curr_desc->word2.buf_adr), pkt_size,
14396 +                                                       PCI_DMA_FROMDEVICE);
14397 +                                               // if ( ((toeq_rwptr.bits.rptr +1)&(TOE_TOE_DESC_NUM-1)) == toeq_wptr) {
14398 +                                               if ( RWPTR_ADVANCE_ONE(toe_qhdr->word1.bits.rptr, TOE_TOE_DESC_NUM) == toeq_wptr) {
14399 +                                                       skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr) -
14400 +                                                               SKB_RESERVE_BYTES));
14401 +                                                       _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x04);
14402 +                                                       connection->curr_rx_skb = skb;
14403 +                                                       skb_reserve(skb, RX_INSERT_BYTES);
14404 +                                                       skb_put(skb, pkt_size);
14405 +                                                       skb->dev = dev;
14406 +                                                       skb->protocol = eth_type_trans(skb, dev);
14407 +                                                       skb->ip_summed = CHECKSUM_UNNECESSARY;
14408 +                                                       // printk("toeq_rptr %d, wptr %d\n", toeq_rptr, toeq_wptr);
14409 +                                                       netif_rx(skb);
14410 +                                                       dev->last_rx = jiffies;
14411 +/*
14412 +                                                       if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
14413 +
14414 +                                                       }
14415 +                                                       *(unsigned int*)(skb->data) = (unsigned int) skb;
14416 +                                                       skb_reserve(skb, SKB_RESERVE_BYTES); */
14417 +                                               } else {
14418 +                                                       // reuse this skb, append to free queue..
14419 +                                                       skb = (struct sk_buff*)(REG32(__va(toe_curr_desc->word2.buf_adr)-
14420 +                                                               SKB_RESERVE_BYTES));
14421 +                                                       _debug_skb(skb, (GMAC_RXDESC_T *)toe_curr_desc, 0x05);
14422 +                                                       connection->curr_rx_skb = skb;
14423 +                                                       dev_kfree_skb_irq(skb);
14424 +                                               }
14425 +#if 0
14426 +                                               spin_lock_irqsave(&gmac_fq_lock, flags);
14427 +                                               fq_rwptr.bits32 = readl(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG);
14428 +/*                                             if (toe->fq_rx_rwptr.bits.wptr != fq_rwptr.bits.wptr) {
14429 +                                                       printk("%s::fq_rx_rwptr %x\n", __func__, toe->fq_rx_rwptr.bits32);
14430 +                                                       mac_stop_txdma((struct net_device*) tp->dev);
14431 +                                                       spin_unlock_irqrestore(&gmac_fq_lock, flags);
14432 +                                                       while(1);
14433 +                                               } */
14434 +                                               fq_desc = (GMAC_RXDESC_T*)toe->swfq_desc_base + fq_rwptr.bits.wptr;
14435 +                                               fq_desc->word2.buf_adr = (unsigned int)__pa(skb->data);
14436 +
14437 +                                               fq_rwptr.bits.wptr = RWPTR_ADVANCE_ONE(fq_rwptr.bits.wptr, TOE_SW_FREEQ_DESC_NUM);
14438 +                                               SET_WPTR(TOE_GLOBAL_BASE + GLOBAL_SWFQ_RWPTR_REG, fq_rwptr.bits.wptr);
14439 +                                               toe->fq_rx_rwptr.bits32 = fq_rwptr.bits32;
14440 +       //                                      spin_unlock_irqrestore(&gmac_fq_lock, flags);
14441 +#endif
14442 +//                                             spin_lock_irqsave(&gmac_fq_lock, flags);
14443 +                                               toeq_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(toeq_rwptr.bits.rptr, TOE_TOE_DESC_NUM);
14444 +                                               SET_RPTR(&toe_qhdr->word1, toeq_rwptr.bits.rptr);
14445 +//                                             spin_unlock_irqrestore(&gmac_fq_lock, flags);
14446 +                                       }
14447 +                               } // end of ACK with options.
14448 +                               connection->toeq_rwptr.bits32 = toeq_rwptr.bits32;
14449 +                               // Gary Chen spin_unlock_irqrestore(&connection->conn_lock, toeq_flags);
14450 +//                             }
14451 +                       };
14452 +                       update_timer(connection);
14453 +                       // any protection against interrupt queue header?
14454 +                       intr_rwptr.bits.rptr = RWPTR_ADVANCE_ONE(intr_rwptr.bits.rptr, TOE_INTR_DESC_NUM);
14455 +                       SET_RPTR(&intr_qhdr->word1, intr_rwptr.bits.rptr);
14456 +                       intr_rwptr.bits32 = readl(&intr_qhdr->word1);
14457 +                       toe_gmac_fill_free_q();
14458 +               } // end of this interrupt Queue processing.
14459 +       } // end of all interrupt Queues.
14460 +
14461 +       in_toe_isr = 0;
14462 +}
14463 +
14464 +
14465 Index: linux-2.6.23.17/drivers/net/sl_lepus_hash.c
14466 ===================================================================
14467 --- /dev/null
14468 +++ linux-2.6.23.17/drivers/net/sl_lepus_hash.c
14469 @@ -0,0 +1,553 @@
14470 +/**************************************************************************
14471 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
14472 +*--------------------------------------------------------------------------
14473 +* Name                 : sl_lepus_hash.c
14474 +* Description  :
14475 +*              Handle Storlink Lepus Hash Functions
14476 +*
14477 +* History
14478 +*
14479 +*      Date            Writer          Description
14480 +*----------------------------------------------------------------------------
14481 +*      03/13/2006      Gary Chen       Create and implement
14482 +*
14483 +****************************************************************************/
14484 +#include <linux/module.h>
14485 +#include <linux/kernel.h>
14486 +#include <linux/compiler.h>
14487 +#include <linux/pci.h>
14488 +#include <linux/init.h>
14489 +#include <linux/ioport.h>
14490 +#include <linux/netdevice.h>
14491 +#include <linux/etherdevice.h>
14492 +#include <linux/rtnetlink.h>
14493 +#include <linux/delay.h>
14494 +#include <linux/ethtool.h>
14495 +#include <linux/mii.h>
14496 +#include <linux/completion.h>
14497 +#include <asm/hardware.h>
14498 +#include <asm/io.h>
14499 +#include <asm/irq.h>
14500 +#include <asm/semaphore.h>
14501 +#include <asm/arch/irqs.h>
14502 +#include <asm/arch/it8712.h>
14503 +#include <linux/mtd/kvctl.h>
14504 +#include <linux/skbuff.h>
14505 +#include <linux/ip.h>
14506 +#include <linux/tcp.h>
14507 +#include <linux/list.h>
14508 +#define         MIDWAY
14509 +#define         SL_LEPUS
14510 +
14511 +#include <asm/arch/sl2312.h>
14512 +#include <asm/arch/sl_lepus_gmac.h>
14513 +#include <asm/arch/sl_hash_cfg.h>
14514 +
14515 +#ifndef RXTOE_DEBUG
14516 +#define RXTOE_DEBUG
14517 +#endif
14518 +#undef RXTOE_DEBUG
14519 +
14520 +/*----------------------------------------------------------------------
14521 +* Definition
14522 +*----------------------------------------------------------------------*/
14523 +#define        hash_printf                             printk
14524 +
14525 +#define HASH_TIMER_PERIOD              (60*HZ) // seconds
14526 +#define HASH_ILLEGAL_INDEX             0xffff
14527 +
14528 +/*----------------------------------------------------------------------
14529 +* Variables
14530 +*----------------------------------------------------------------------*/
14531 +u32                                    hash_activate_bits[HASH_TOTAL_ENTRIES/32];
14532 +u32                                    hash_nat_owner_bits[HASH_TOTAL_ENTRIES/32];
14533 +char                           hash_tables[HASH_TOTAL_ENTRIES][HASH_MAX_BYTES] __attribute__ ((aligned(16)));
14534 +static struct timer_list hash_timer_obj;
14535 +LIST_HEAD(hash_timeout_list);
14536 +
14537 +/*----------------------------------------------------------------------
14538 +* Functions
14539 +*----------------------------------------------------------------------*/
14540 +void dm_long(u32 location, int length);
14541 +static void hash_timer_func(u32 data);
14542 +
14543 +/*----------------------------------------------------------------------
14544 +* hash_init
14545 +*----------------------------------------------------------------------*/
14546 +void hash_init(void)
14547 +{
14548 +       int i;
14549 +       volatile u32 *dp1, *dp2, dword;
14550 +
14551 +       dp1 = (volatile u32 *) TOE_V_BIT_BASE;
14552 +       dp2 = (volatile u32 *) TOE_A_BIT_BASE;
14553 +
14554 +       for (i=0; i<HASH_TOTAL_ENTRIES/32; i++)
14555 +       {
14556 +               *dp1++ = 0;
14557 +               dword = *dp2++; // read-clear
14558 +       }
14559 +       memset((void *)&hash_nat_owner_bits, 0, sizeof(hash_nat_owner_bits));
14560 +       memset((void *)&hash_tables, 0, sizeof(hash_tables));
14561 +
14562 +       init_timer(&hash_timer_obj);
14563 +       hash_timer_obj.expires = jiffies + HASH_TIMER_PERIOD;
14564 +       hash_timer_obj.data = (unsigned long)&hash_timer_obj;
14565 +       hash_timer_obj.function = (void *)&hash_timer_func;
14566 +       add_timer(&hash_timer_obj);
14567 +
14568 +#if (HASH_MAX_BYTES == 128)
14569 +       writel((unsigned long)__pa(&hash_tables) | 3,   // 32 words
14570 +                       TOE_GLOBAL_BASE + GLOBAL_HASH_TABLE_BASE_REG);
14571 +#elif (HASH_MAX_BYTES == 64)
14572 +       writel((unsigned long)__pa(&hash_tables) | 2,   // 16 words
14573 +                       TOE_GLOBAL_BASE + GLOBAL_HASH_TABLE_BASE_REG);
14574 +#else
14575 +       #error Incorrect setting for HASH_MAX_BYTES
14576 +#endif
14577 +
14578 +}
14579 +/*----------------------------------------------------------------------
14580 +* hash_add_entry
14581 +*----------------------------------------------------------------------*/
14582 +int hash_add_entry(HASH_ENTRY_T *entry)
14583 +{
14584 +       int     rc;
14585 +       u32     key[HASH_MAX_DWORDS];
14586 +       rc = hash_build_keys((u32 *)&key, entry);
14587 +       if (rc < 0)
14588 +               return -1;
14589 +       hash_write_entry(entry, (unsigned char*) &key[0]);
14590 +//     hash_set_valid_flag(entry->index, 1);
14591 +//     printk("Dump hash key!\n");
14592 +//     dump_hash_key(entry);
14593 +       return entry->index;
14594 +}
14595 +
14596 +/*----------------------------------------------------------------------
14597 +* hash_set_valid_flag
14598 +*----------------------------------------------------------------------*/
14599 +void hash_set_valid_flag(int index, int valid)
14600 +{
14601 +       register u32 reg32;
14602 +
14603 +       reg32 = TOE_V_BIT_BASE + (index/32) * 4;
14604 +
14605 +       if (valid)
14606 +       {
14607 +               writel(readl(reg32) | (1 << (index%32)), reg32);
14608 +       }
14609 +       else
14610 +       {
14611 +               writel(readl(reg32) & ~(1 << (index%32)), reg32);
14612 +       }
14613 +}
14614 +
14615 +/*----------------------------------------------------------------------
14616 +* hash_set_nat_owner_flag
14617 +*----------------------------------------------------------------------*/
14618 +void hash_set_nat_owner_flag(int index, int valid)
14619 +{
14620 +       if (valid)
14621 +       {
14622 +               hash_nat_owner_bits[index/32] |= (1 << (index % 32));
14623 +       }
14624 +       else
14625 +       {
14626 +               hash_nat_owner_bits[index/32] &= ~(1 << (index % 32));
14627 +       }
14628 +}
14629 +
14630 +
14631 +/*----------------------------------------------------------------------
14632 +* hash_build_keys
14633 +*----------------------------------------------------------------------*/
14634 +int hash_build_keys(u32 *destp, HASH_ENTRY_T *entry)
14635 +{
14636 +       u32     data;
14637 +       unsigned char   *cp;
14638 +       int                             i, j;
14639 +       unsigned short  index;
14640 +       int                     total;
14641 +
14642 +       memset((void *)destp, 0, HASH_MAX_BYTES);
14643 +       cp = (unsigned char *)destp;
14644 +
14645 +       if (entry->key_present.port || entry->key_present.Ethertype)
14646 +       {
14647 +               HASH_PUSH_WORD(cp, entry->key.Ethertype);               // word 0
14648 +               HASH_PUSH_BYTE(cp, entry->key.port);                    // Byte 2
14649 +               HASH_PUSH_BYTE(cp, 0);                                                  // Byte 3
14650 +       }
14651 +       else
14652 +       {
14653 +               HASH_PUSH_DWORD(cp, 0);
14654 +       }
14655 +
14656 +       if (entry->key_present.da || entry->key_present.sa)
14657 +       {
14658 +               unsigned char mac[4];
14659 +               if (entry->key_present.da)
14660 +               {
14661 +                       for (i=0; i<4; i++)
14662 +                               HASH_PUSH_BYTE(cp, entry->key.da[i]);
14663 +               }
14664 +               mac[0] = (entry->key_present.da) ? entry->key.da[4] : 0;
14665 +               mac[1] = (entry->key_present.da) ? entry->key.da[5] : 0;
14666 +               mac[2] = (entry->key_present.sa) ? entry->key.sa[0] : 0;
14667 +               mac[3] = (entry->key_present.sa) ? entry->key.sa[1] : 0;
14668 +               data = mac[0] + (mac[1]<<8) + (mac[2]<<16) + (mac[3]<<24);
14669 +               HASH_PUSH_DWORD(cp, data);
14670 +               if (entry->key_present.sa)
14671 +               {
14672 +                       for (i=2; i<6; i++)
14673 +                               HASH_PUSH_BYTE(cp, entry->key.sa[i]);
14674 +               }
14675 +       }
14676 +
14677 +       if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
14678 +       {
14679 +               HASH_PUSH_WORD(cp, entry->key.vlan_id);         // low word
14680 +               HASH_PUSH_WORD(cp, entry->key.pppoe_sid);       // high word
14681 +       }
14682 +       if (entry->key_present.ipv4_hdrlen || entry->key_present.ip_tos || entry->key_present.ip_protocol)
14683 +       {
14684 +               HASH_PUSH_BYTE(cp, entry->key.ip_protocol);             // Byte 0
14685 +               HASH_PUSH_BYTE(cp, entry->key.ip_tos);                  // Byte 1
14686 +               HASH_PUSH_BYTE(cp, entry->key.ipv4_hdrlen);             // Byte 2
14687 +               HASH_PUSH_BYTE(cp, 0);                                                  // Byte 3
14688 +       }
14689 +
14690 +       if (entry->key_present.ipv6_flow_label)
14691 +       {
14692 +               HASH_PUSH_DWORD(cp, entry->key.ipv6_flow_label);        // low word
14693 +       }
14694 +       if (entry->key_present.sip)
14695 +       {
14696 +               // input (entry->key.sip[i]) is network-oriented
14697 +               // output (hash key) is host-oriented
14698 +               for (i=3; i>=0; i--)
14699 +                       HASH_PUSH_BYTE(cp, entry->key.sip[i]);
14700 +               if (entry->key.ipv6)
14701 +               {
14702 +                       for (i=4; i<16; i+=4)
14703 +                       {
14704 +                               for (j=i+3; j>=i; j--)
14705 +                                       HASH_PUSH_BYTE(cp, entry->key.sip[j]);
14706 +                       }
14707 +               }
14708 +       }
14709 +       if (entry->key_present.dip)
14710 +       {
14711 +               // input (entry->key.sip[i]) is network-oriented
14712 +               // output (hash key) is host-oriented
14713 +               for (i=3; i>=0; i--)
14714 +                       HASH_PUSH_BYTE(cp, entry->key.dip[i]);
14715 +               if (entry->key.ipv6)
14716 +               {
14717 +                       for (i=4; i<16; i+=4)
14718 +                       {
14719 +                               for (j=i+3; j>=i; j--)
14720 +                                       HASH_PUSH_BYTE(cp, entry->key.dip[j]);
14721 +                       }
14722 +               }
14723 +       }
14724 +
14725 +       if (entry->key_present.l4_bytes_0_3)
14726 +       {
14727 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
14728 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
14729 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
14730 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
14731 +       }
14732 +       if (entry->key_present.l4_bytes_4_7)
14733 +       {
14734 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[4]);
14735 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[5]);
14736 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[6]);
14737 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[7]);
14738 +       }
14739 +       if (entry->key_present.l4_bytes_8_11)
14740 +       {
14741 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[8]);
14742 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[9]);
14743 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[10]);
14744 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[11]);
14745 +       }
14746 +       if (entry->key_present.l4_bytes_12_15)
14747 +       {
14748 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[12]);
14749 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[13]);
14750 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[14]);
14751 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[15]);
14752 +       }
14753 +       if (entry->key_present.l4_bytes_16_19)
14754 +       {
14755 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[16]);
14756 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[17]);
14757 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[18]);
14758 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[19]);
14759 +       }
14760 +       if (entry->key_present.l4_bytes_20_23)
14761 +       {
14762 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[20]);
14763 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[21]);
14764 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[22]);
14765 +               HASH_PUSH_BYTE(cp, entry->key.l4_bytes[23]);
14766 +       }
14767 +       if (entry->key_present.l7_bytes_0_3)
14768 +       {
14769 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[0]);
14770 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[1]);
14771 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[2]);
14772 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[3]);
14773 +       }
14774 +       if (entry->key_present.l7_bytes_4_7)
14775 +       {
14776 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[4]);
14777 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[5]);
14778 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[6]);
14779 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[7]);
14780 +       }
14781 +       if (entry->key_present.l7_bytes_8_11)
14782 +       {
14783 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[8]);
14784 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[9]);
14785 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[10]);
14786 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[11]);
14787 +       }
14788 +       if (entry->key_present.l7_bytes_12_15)
14789 +       {
14790 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[12]);
14791 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[13]);
14792 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[14]);
14793 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[15]);
14794 +       }
14795 +       if (entry->key_present.l7_bytes_16_19)
14796 +       {
14797 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[16]);
14798 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[17]);
14799 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[18]);
14800 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[19]);
14801 +       }
14802 +       if (entry->key_present.l7_bytes_20_23)
14803 +       {
14804 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[20]);
14805 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[21]);
14806 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[22]);
14807 +               HASH_PUSH_BYTE(cp, entry->key.l7_bytes[23]);
14808 +       }
14809 +
14810 +       // get hash index
14811 +       total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
14812 +
14813 +       if (total > HASH_MAX_KEY_DWORD)
14814 +       {
14815 +               //hash_printf("Total key words (%d) is too large (> %d)!\n",
14816 +               //                              total, HASH_MAX_KEY_DWORD);
14817 +               return -1;
14818 +       }
14819 +
14820 +       if (entry->key_present.port || entry->key_present.Ethertype)
14821 +               index = hash_gen_crc16((unsigned char *)destp, total * 4);
14822 +       else
14823 +       {
14824 +               if (total == 1)
14825 +               {
14826 +                       hash_printf("No key is assigned!\n");
14827 +                       return -1;
14828 +               }
14829 +
14830 +               index = hash_gen_crc16((unsigned char *)(destp+1), (total-1) * 4);
14831 +       }
14832 +
14833 +       entry->index = index & HASH_BITS_MASK;
14834 +
14835 +       //hash_printf("Total key words = %d, Hash Index= %d\n",
14836 +       //                              total, entry->index);
14837 +
14838 +       cp = (unsigned char *)destp;
14839 +       cp+=3;
14840 +       HASH_PUSH_BYTE(cp, entry->rule);        // rule
14841 +
14842 +       entry->total_dwords = total;
14843 +
14844 +       return total;
14845 +}
14846 +
14847 +/*----------------------------------------------------------------------
14848 +* hash_build_nat_keys
14849 +*----------------------------------------------------------------------*/
14850 +void hash_build_nat_keys(u32 *destp, HASH_ENTRY_T *entry)
14851 +{
14852 +       unsigned char   *cp;
14853 +       int                             i;
14854 +       unsigned short  index;
14855 +       int                     total;
14856 +
14857 +       memset((void *)destp, 0, HASH_MAX_BYTES);
14858 +
14859 +       cp = (unsigned char *)destp + 2;
14860 +       HASH_PUSH_BYTE(cp, entry->key.port);
14861 +       cp++;
14862 +
14863 +       if (entry->key_present.pppoe_sid || entry->key_present.vlan_id)
14864 +       {
14865 +               HASH_PUSH_WORD(cp, entry->key.vlan_id);         // low word
14866 +               HASH_PUSH_WORD(cp, entry->key.pppoe_sid);       // high word
14867 +       }
14868 +
14869 +       HASH_PUSH_BYTE(cp, entry->key.ip_protocol);
14870 +       cp+=3;
14871 +
14872 +       // input (entry->key.sip[i]) is network-oriented
14873 +       // output (hash key) is host-oriented
14874 +       for (i=3; i>=0; i--)
14875 +               HASH_PUSH_BYTE(cp, entry->key.sip[i]);
14876 +
14877 +       // input (entry->key.sip[i]) is network-oriented
14878 +       // output (hash key) is host-oriented
14879 +       for (i=3; i>=0; i--)
14880 +               HASH_PUSH_BYTE(cp, entry->key.dip[i]);
14881 +
14882 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[0]);
14883 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[1]);
14884 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[2]);
14885 +       HASH_PUSH_BYTE(cp, entry->key.l4_bytes[3]);
14886 +
14887 +       // get hash index
14888 +       total = (u32)((u32)cp - (u32)destp) / (sizeof(u32));
14889 +
14890 +       index = hash_gen_crc16((unsigned char *)destp, total * 4);
14891 +       entry->index = index & ((1 << HASH_BITS) - 1);
14892 +
14893 +       cp = (unsigned char *)destp;
14894 +       cp+=3;
14895 +       HASH_PUSH_BYTE(cp, entry->rule);        // rule
14896 +
14897 +       entry->total_dwords = total;
14898 +}
14899 +
14900 +
14901 +/*----------------------------------------------------------------------
14902 +* hash_write_entry
14903 +*----------------------------------------------------------------------*/
14904 +int hash_write_entry(HASH_ENTRY_T *entry, unsigned char *key)
14905 +{
14906 +       int             i;
14907 +       u32             *srcep, *destp, *destp2;
14908 +
14909 +       srcep = (u32 *)key;
14910 +       destp2 = destp = (u32 *)&hash_tables[entry->index][0];
14911 +
14912 +       for (i=0; i<(entry->total_dwords); i++, srcep++, destp++)
14913 +               *destp = *srcep;
14914 +
14915 +       srcep = (u32 *)&entry->action;
14916 +       *destp++ = *srcep;
14917 +
14918 +       srcep = (u32 *)&entry->param;
14919 +       for (i=0; i<(sizeof(ENTRY_PARAM_T)/sizeof(*destp)); i++, srcep++, destp++)
14920 +               *destp = *srcep;
14921 +
14922 +       memset(destp, 0, (HASH_MAX_DWORDS-entry->total_dwords-HASH_ACTION_DWORDS) * sizeof(u32));
14923 +
14924 +       consistent_sync(destp2, (entry->total_dwords+HASH_ACTION_DWORDS) * 4, PCI_DMA_TODEVICE);
14925 +       return 0;
14926 +}
14927 +
14928 +/*----------------------------------------------------------------------
14929 +* hash_timer_func
14930 +*----------------------------------------------------------------------*/
14931 +static void hash_timer_func(u32 data)
14932 +{
14933 +       int                             i, j;
14934 +       volatile u32    *active_p, *own_p, *valid_p;
14935 +       u32                             a_bits, own_bits;
14936 +
14937 +       valid_p = (volatile u32 *)TOE_V_BIT_BASE;
14938 +       active_p = (volatile u32 *)hash_activate_bits;
14939 +       own_p = (volatile u32 *)hash_nat_owner_bits;
14940 +       for (i=0; i<(HASH_TOTAL_ENTRIES/32); i++, own_p++, active_p++, valid_p++)
14941 +       {
14942 +               *active_p |= readl(TOE_A_BIT_BASE + (i*4));
14943 +               a_bits = *active_p;
14944 +               own_bits = *own_p;
14945 +               if (own_bits)
14946 +               {
14947 +#ifndef DEBUG_NAT_MIXED_HW_SW_TX
14948 +                       a_bits = own_bits & ~a_bits;
14949 +#else
14950 +                       a_bits = own_bits & a_bits;
14951 +#endif
14952 +                       for (j=0; a_bits && j<32; j++)
14953 +                       {
14954 +                               if (a_bits & 1)
14955 +                               {
14956 +                                       *valid_p &= ~(1 << j);          // invalidate it
14957 +#if !(defined(NAT_DEBUG_LAN_HASH_TIMEOUT) || defined(NAT_DEBUG_WAN_HASH_TIMEOUT))
14958 +                                       *own_p &= ~(1 << j);            // release ownership for NAT
14959 +#endif
14960 +// #ifdef DEBUG_NAT_MIXED_HW_SW_TX
14961 +#if 0
14962 +                                       hash_printf("%lu %s: Clear hash index: %d\n", jiffies/HZ, __func__, i*32+j);
14963 +#endif
14964 +                               }
14965 +                               a_bits >>= 1;
14966 +                       }
14967 +                       *active_p &= ~own_bits;         // deactivate it for next polling
14968 +               }
14969 +       }
14970 +
14971 +       hash_timer_obj.expires = jiffies + HASH_TIMER_PERIOD;
14972 +       add_timer((struct timer_list *)data);
14973 +}
14974 +
14975 +/*----------------------------------------------------------------------
14976 +* dm_long
14977 +*----------------------------------------------------------------------*/
14978 +void dm_long(u32 location, int length)
14979 +{
14980 +       u32             *start_p, *curr_p, *end_p;
14981 +       u32             *datap, data;
14982 +       int             i;
14983 +
14984 +       //if (length > 1024)
14985 +       //      length = 1024;
14986 +
14987 +       start_p = (u32 *)location;
14988 +       end_p = (u32 *)location + length;
14989 +       curr_p = (u32 *)((u32)location & 0xfffffff0);
14990 +       datap = (u32 *)location;
14991 +       while (curr_p < end_p)
14992 +       {
14993 +               hash_printf("0x%08x: ",(u32)curr_p & 0xfffffff0);
14994 +               for (i=0; i<4; i++)
14995 +               {
14996 +                       if (curr_p < start_p || curr_p >= end_p)
14997 +               hash_printf("         ");
14998 +                       else
14999 +                       {
15000 +                               data = *datap;
15001 +                               hash_printf("%08X ", data);
15002 +                       }
15003 +                       if (i==1)
15004 +              hash_printf("- ");
15005 +
15006 +                       curr_p++;
15007 +                       datap++;
15008 +               }
15009 +        hash_printf("\n");
15010 +       }
15011 +}
15012 +
15013 +/*----------------------------------------------------------------------
15014 +* hash_dump_entry
15015 +*----------------------------------------------------------------------*/
15016 +void hash_dump_entry(int index)
15017 +{
15018 +       hash_printf("Hash Index %d:\n", index);
15019 +       dm_long((u32)&hash_tables[index][0], HASH_MAX_DWORDS);
15020 +}
15021 +
15022 +
15023 Index: linux-2.6.23.17/drivers/net/sl_switch.c
15024 ===================================================================
15025 --- /dev/null
15026 +++ linux-2.6.23.17/drivers/net/sl_switch.c
15027 @@ -0,0 +1,650 @@
15028 +#include <linux/module.h>
15029 +#include <linux/kernel.h>
15030 +#include <linux/init.h>
15031 +#include <linux/ioport.h>
15032 +#include <linux/delay.h>
15033 +#include <asm/hardware.h>
15034 +#include <asm/io.h>
15035 +
15036 +#define GMAC_GLOBAL_BASE_ADDR       (IO_ADDRESS(SL2312_GLOBAL_BASE))
15037 +#define GPIO_BASE_ADDR1  (IO_ADDRESS(SL2312_GPIO_BASE1))
15038 +enum GPIO_REG
15039 +{
15040 +    GPIO_DATA_OUT   = 0x00,
15041 +    GPIO_DATA_IN    = 0x04,
15042 +    GPIO_PIN_DIR    = 0x08,
15043 +    GPIO_BY_PASS    = 0x0c,
15044 +    GPIO_DATA_SET   = 0x10,
15045 +    GPIO_DATA_CLEAR = 0x14,
15046 +};
15047 +
15048 +#define GMAC_SPEED_10                  0
15049 +#define GMAC_SPEED_100                 1
15050 +#define GMAC_SPEED_1000                        2
15051 +
15052 +enum phy_state
15053 +{
15054 +    LINK_DOWN   = 0,
15055 +    LINK_UP     = 1
15056 +};
15057 +
15058 +#ifndef BIT
15059 +#define BIT(x)                                         (1 << (x))
15060 +#endif
15061 +
15062 +//int Get_Set_port_status();
15063 +unsigned int SPI_read_bit(void);
15064 +void SPI_write_bit(char bit_EEDO);
15065 +void SPI_write(unsigned char block,unsigned char subblock,unsigned char addr,unsigned int value);
15066 +unsigned int SPI_read(unsigned char block,unsigned char subblock,unsigned char addr);
15067 +int SPI_default(void);
15068 +void SPI_CS_enable(unsigned char enable);
15069 +unsigned int SPI_get_identifier(void);
15070 +void phy_write(unsigned char port_no,unsigned char reg,unsigned int val);
15071 +unsigned int phy_read(unsigned char port_no,unsigned char reg);
15072 +void phy_write_masked(unsigned char port_no,unsigned char reg,unsigned int val,unsigned int mask);
15073 +void init_seq_7385(unsigned char port_no) ;
15074 +void phy_receiver_init (unsigned char port_no);
15075 +
15076 +#define PORT_NO                4
15077 +int switch_pre_speed[PORT_NO]={0,0,0,0};
15078 +int switch_pre_link[PORT_NO]={0,0,0,0};
15079 +
15080 +
15081 +
15082 +
15083 +
15084 +/*                             NOTES
15085 + *   The Protocol of the SPI are as follows:
15086 + *
15087 + *                        Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
15088 + *     byte0     |   Block id  | r/w | sub-block        |
15089 + *     byte1     |             Address                  |
15090 + *     byte2     |             Data                     |
15091 + *     byte3     |             Data                     |
15092 + *     byte4     |             Data                     |
15093 + *     byte5     |             Data                     |
15094 + */
15095 +
15096 +
15097 +
15098 +
15099 +/***************************************/
15100 +/* define GPIO module base address     */
15101 +/***************************************/
15102 +#define GPIO_EECS           0x80000000         /*   EECS: GPIO[22]   */
15103 +#define GPIO_MOSI           0x20000000         /*   EEDO: GPIO[29]   send to 6996*/
15104 +#define GPIO_MISO           0x40000000         /*   EEDI: GPIO[30]   receive from 6996*/
15105 +#define GPIO_EECK           0x10000000         /*   EECK: GPIO[31]   */
15106 +
15107 +/*************************************************************
15108 +* SPI protocol for ADM6996 control
15109 +**************************************************************/
15110 +#define SPI_OP_LEN          0x08               // the length of start bit and opcode
15111 +#define SPI_OPWRITE         0X05               // write
15112 +#define SPI_OPREAD          0X06               // read
15113 +#define SPI_OPERASE         0X07               // erase
15114 +#define SPI_OPWTEN          0X04               // write enable
15115 +#define SPI_OPWTDIS         0X04               // write disable
15116 +#define SPI_OPERSALL        0X04               // erase all
15117 +#define SPI_OPWTALL         0X04               // write all
15118 +
15119 +#define SPI_ADD_LEN         8                  // bits of Address
15120 +#define SPI_DAT_LEN         32                 // bits of Data
15121 +
15122 +
15123 +/****************************************/
15124 +/*     Function Declare                */
15125 +/****************************************/
15126 +
15127 +//unsigned int SPI_read_bit(void);
15128 +//void SPI_write_bit(char bit_EEDO);
15129 +//unsigned int SPI_read_bit(void);
15130 +/******************************************
15131 +* SPI_write
15132 +* addr -> Write Address
15133 +* value -> value to be write
15134 +***************************************** */
15135 +void phy_receiver_init (unsigned char port_no)
15136 +{
15137 +    phy_write(port_no,31,0x2a30);
15138 +    phy_write_masked(port_no, 12, 0x0200, 0x0300);
15139 +    phy_write(port_no,31,0);
15140 +}
15141 +
15142 +void phy_write(unsigned char port_no,unsigned char reg,unsigned int val)
15143 +{
15144 +       unsigned int cmd;
15145 +
15146 +       cmd = (port_no<<21)|(reg<<16)|val;
15147 +       SPI_write(3,0,1,cmd);
15148 +}
15149 +
15150 +unsigned int phy_read(unsigned char port_no,unsigned char reg)
15151 +{
15152 +       unsigned int cmd,reg_val;
15153 +
15154 +       cmd = BIT(26)|(port_no<<21)|(reg<<16);
15155 +       SPI_write(3,0,1,cmd);
15156 +       msleep(2);
15157 +       reg_val = SPI_read(3,0,2);
15158 +       return reg_val;
15159 +}
15160 +
15161 +void phy_write_masked(unsigned char port_no,unsigned char reg,unsigned int val,unsigned int mask)
15162 +{
15163 +       unsigned int cmd,reg_val;
15164 +
15165 +       cmd = BIT(26)|(port_no<<21)|(reg<<16);  // Read reg_val
15166 +       SPI_write(3,0,1,cmd);
15167 +       mdelay(2);
15168 +       reg_val = SPI_read(3,0,2);
15169 +       reg_val &= ~mask;                       // Clear masked bit
15170 +       reg_val |= (val&mask) ;                 // set masked bit ,if true
15171 +       cmd = (port_no<<21)|(reg<<16)|reg_val;
15172 +       SPI_write(3,0,1,cmd);
15173 +}
15174 +
15175 +void init_seq_7385(unsigned char port_no)
15176 +{
15177 +       unsigned char rev;
15178 +
15179 +       phy_write(port_no, 31, 0x2a30);
15180 +       phy_write_masked(port_no, 8, 0x0200, 0x0200);
15181 +       phy_write(port_no, 31, 0x52b5);
15182 +       phy_write(port_no, 16, 0xb68a);
15183 +       phy_write_masked(port_no, 18, 0x0003, 0xff07);
15184 +       phy_write_masked(port_no, 17, 0x00a2, 0x00ff);
15185 +       phy_write(port_no, 16, 0x968a);
15186 +       phy_write(port_no, 31, 0x2a30);
15187 +       phy_write_masked(port_no, 8, 0x0000, 0x0200);
15188 +       phy_write(port_no, 31, 0x0000); /* Read revision */
15189 +       rev = phy_read(port_no, 3) & 0x000f;
15190 +       if (rev == 0)
15191 +       {
15192 +               phy_write(port_no, 31, 0x2a30);
15193 +               phy_write_masked(port_no, 8, 0x0200, 0x0200);
15194 +               phy_write(port_no, 31, 0x52b5);
15195 +               phy_write(port_no, 18, 0x0000);
15196 +               phy_write(port_no, 17, 0x0689);
15197 +               phy_write(port_no, 16, 0x8f92);
15198 +               phy_write(port_no, 31, 0x52B5);
15199 +               phy_write(port_no, 18, 0x0000);
15200 +               phy_write(port_no, 17, 0x0E35);
15201 +               phy_write(port_no, 16, 0x9786);
15202 +               phy_write(port_no, 31, 0x2a30);
15203 +               phy_write_masked(port_no, 8, 0x0000, 0x0200);
15204 +               phy_write(port_no, 23, 0xFF80);
15205 +               phy_write(port_no, 23, 0x0000);
15206 +       }
15207 +       phy_write(port_no, 31, 0x0000);
15208 +       phy_write(port_no, 18, 0x0048);
15209 +       if (rev == 0)
15210 +       {
15211 +               phy_write(port_no, 31, 0x2a30);
15212 +               phy_write(port_no, 20, 0x6600);
15213 +               phy_write(port_no, 31, 0x0000);
15214 +               phy_write(port_no, 24, 0xa24e);
15215 +       }
15216 +       else
15217 +       {
15218 +               phy_write(port_no, 31, 0x2a30);
15219 +               phy_write_masked(port_no, 22, 0x0240, 0x0fc0);
15220 +               phy_write_masked(port_no, 20, 0x4000, 0x6000);
15221 +               phy_write(port_no, 31, 1);
15222 +               phy_write_masked(port_no, 20, 0x6000, 0xe000);
15223 +               phy_write(port_no, 31, 0x0000);
15224 +       }
15225 +}
15226 +
15227 +int Get_Set_port_status()
15228 +{
15229 +       unsigned int    reg_val,ability,rcv_mask,mac_config;
15230 +       int is_link=0;
15231 +       int i;
15232 +
15233 +       rcv_mask = SPI_read(2,0,0x10);                  // Receive mask
15234 +
15235 +       for(i=0;i<4;i++){
15236 +               reg_val = phy_read(i,1);
15237 +               if ((reg_val & 0x0024) == 0x0024) /* link is established and auto_negotiate process completed */
15238 +               {
15239 +                       is_link=1;
15240 +                       if(switch_pre_link[i]==LINK_DOWN){              // Link Down ==> Link up
15241 +
15242 +                               rcv_mask |= BIT(i);                     // Enable receive
15243 +
15244 +                               reg_val = phy_read(i,10);
15245 +                               if(reg_val & 0x0c00){
15246 +                                       printk("Port%d:Giga mode\n",i);
15247 +//                                     SPI_write(1,i,0x00,0x300701B1);
15248 +                                       mac_config = 0x00060004|(6<<6);
15249 +
15250 +                                       SPI_write(1,i,0x00,((mac_config & 0xfffffff8) | 1) | 0x20000030);       // reset port
15251 +                                       mac_config |= (( BIT(i) << 19) | 0x08000000);
15252 +                                       SPI_write(1,i,0x00,mac_config);
15253 +                                       SPI_write(1,i,0x04,0x000300ff);         // flow control
15254 +
15255 +                                       reg_val = SPI_read(5,0,0x12);
15256 +                                       reg_val &= ~BIT(i);
15257 +                                       SPI_write(5,0,0x12,reg_val);
15258 +
15259 +                                       reg_val = SPI_read(1,i,0x00);
15260 +                                       reg_val |= 0x10010000;
15261 +                                       SPI_write(1,i,0x00,reg_val);
15262 +//                                     SPI_write(1,i,0x00,0x10070181);
15263 +                                       switch_pre_link[i]=LINK_UP;
15264 +                                       switch_pre_speed[i]=GMAC_SPEED_1000;
15265 +                               }
15266 +                               else{
15267 +                                       reg_val = phy_read(i,5);
15268 +                                       ability = (reg_val&0x5e0) >>5;
15269 +                                       if ((ability & 0x0C)) /* 100M */
15270 +                                       {
15271 +//                                             SPI_write(1,i,0x00,0x30050472);
15272 +                                               if((ability&0x08)==0)           // Half
15273 +                                                       mac_config = 0x00040004 |(17<<6);
15274 +                                               else                            // Full
15275 +                                                       mac_config = 0x00040004 |(17<<6);
15276 +
15277 +                                               SPI_write(1,i,0x00,((mac_config & 0xfffffff8) | 1) | 0x20000030);       // reset port
15278 +                                               mac_config |= (( BIT(i) << 19) | 0x08000000);
15279 +                                               SPI_write(1,i,0x00,mac_config);
15280 +                                               SPI_write(1,i,0x04,0x000300ff);         // flow control
15281 +
15282 +                                               reg_val = SPI_read(5,0,0x12);
15283 +                                               reg_val &= ~BIT(i);
15284 +                                               SPI_write(5,0,0x12,reg_val);
15285 +
15286 +                                               reg_val = SPI_read(1,i,0x00);
15287 +                                               reg_val &= ~0x08000000;
15288 +                                               reg_val |= 0x10010000;
15289 +                                               SPI_write(1,i,0x00,reg_val);
15290 +//                                             SPI_write(1,i,0x00,0x10050442);
15291 +                                               printk("Port%d:100M\n",i);
15292 +                                               switch_pre_link[i]=LINK_UP;
15293 +                                               switch_pre_speed[i]=GMAC_SPEED_100;
15294 +                                       }
15295 +                                       else if((ability & 0x03)) /* 10M */
15296 +                                       {
15297 +//                                             SPI_write(1,i,0x00,0x30050473);
15298 +                                               if((ability&0x2)==0)            // Half
15299 +                                                       mac_config = 0x00040004 |(17<<6);
15300 +                                               else                            // Full
15301 +                                                       mac_config = 0x00040004 |(17<<6);
15302 +
15303 +                                               SPI_write(1,i,0x00,((mac_config & 0xfffffff8) | 1) | 0x20000030);       // reset port
15304 +                                               mac_config |= (( BIT(i) << 19) | 0x08000000);
15305 +                                               SPI_write(1,i,0x00,mac_config);
15306 +                                               SPI_write(1,i,0x04,0x000300ff);         // flow control
15307 +
15308 +                                               reg_val = SPI_read(5,0,0x12);
15309 +                                               reg_val &= ~BIT(i);
15310 +                                               SPI_write(5,0,0x12,reg_val);
15311 +
15312 +                                               reg_val = SPI_read(1,i,0x00);
15313 +                                               reg_val &= ~0x08000000;
15314 +                                               reg_val |= 0x10010000;
15315 +                                               SPI_write(1,i,0x00,reg_val);
15316 +//                                             SPI_write(1,i,0x00,0x10050443);
15317 +                                               printk("Port%d:10M\n",i);
15318 +                                               switch_pre_link[i]=LINK_UP;
15319 +                                               switch_pre_speed[i]=GMAC_SPEED_10;
15320 +                                       }
15321 +                                       else{
15322 +                                               SPI_write(1,i,0x00,0x20000030);
15323 +                                               printk("Port%d:Unknown mode\n",i);
15324 +                                               switch_pre_link[i]=LINK_DOWN;
15325 +                                               switch_pre_speed[i]=GMAC_SPEED_10;
15326 +                                       }
15327 +                               }
15328 +                       }
15329 +                       else{                                           // Link up ==> Link UP
15330 +
15331 +                       }
15332 +               }
15333 +               else{                                                   // Link Down
15334 +                       if(switch_pre_link[i]==LINK_UP){
15335 +                               printk("Port%d:Link Down\n",i);
15336 +                               //phy_receiver_init(i);
15337 +                               reg_val = SPI_read(1,i,0);
15338 +                               reg_val &= ~BIT(16);
15339 +                               SPI_write(1,i,0x00,reg_val);                    // disable RX
15340 +                               SPI_write(5,0,0x0E,BIT(i));                     // dicard packet
15341 +                               while((SPI_read(5,0,0x0C)&BIT(i))==0)           // wait to be empty
15342 +                                       msleep(1);
15343 +                               SPI_write(1,i,0x00,0x20000030);                 // PORT_RST
15344 +                               SPI_write(5,0,0x0E,SPI_read(5,0,0x0E) & ~BIT(i));// accept packet
15345 +
15346 +                               reg_val = SPI_read(5,0,0x12);
15347 +                               reg_val |= BIT(i);
15348 +                               SPI_write(5,0,0x12,reg_val);
15349 +                       }
15350 +                       switch_pre_link[i]=LINK_DOWN;
15351 +                       rcv_mask &= ~BIT(i);                    // disable receive
15352 +               }
15353 +       }
15354 +
15355 +       SPI_write(2,0,0x10,rcv_mask);                   // Receive mask
15356 +       return is_link;
15357 +
15358 +}
15359 +EXPORT_SYMBOL(Get_Set_port_status);
15360 +
15361 +void SPI_write(unsigned char block,unsigned char subblock,unsigned char addr,unsigned int value)
15362 +{
15363 +       int     i;
15364 +       char    bit;
15365 +       unsigned int data;
15366 +
15367 +       SPI_CS_enable(1);
15368 +
15369 +       data = (block<<5) | 0x10 | subblock;
15370 +
15371 +       //send write command
15372 +       for(i=SPI_OP_LEN-1;i>=0;i--)
15373 +       {
15374 +               bit = (data>>i)& 0x01;
15375 +               SPI_write_bit(bit);
15376 +       }
15377 +
15378 +       // send 8 bits address (MSB first, LSB last)
15379 +       for(i=SPI_ADD_LEN-1;i>=0;i--)
15380 +       {
15381 +               bit = (addr>>i)& 0x01;
15382 +               SPI_write_bit(bit);
15383 +       }
15384 +       // send 32 bits data (MSB first, LSB last)
15385 +       for(i=SPI_DAT_LEN-1;i>=0;i--)
15386 +       {
15387 +               bit = (value>>i)& 0x01;
15388 +               SPI_write_bit(bit);
15389 +       }
15390 +
15391 +       SPI_CS_enable(0);       // CS low
15392 +
15393 +}
15394 +
15395 +
15396 +/************************************
15397 +* SPI_write_bit
15398 +* bit_EEDO -> 1 or 0 to be written
15399 +************************************/
15400 +void SPI_write_bit(char bit_EEDO)
15401 +{
15402 +       unsigned int addr;
15403 +       unsigned int value;
15404 +
15405 +       addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
15406 +       value = readl(addr) |GPIO_EECK |GPIO_MOSI ;   /* set EECK/MISO Pin to output */
15407 +       writel(value,addr);
15408 +       if(bit_EEDO)
15409 +       {
15410 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_SET);
15411 +               writel(GPIO_MOSI,addr); /* set MISO to 1 */
15412 +
15413 +       }
15414 +       else
15415 +       {
15416 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15417 +               writel(GPIO_MOSI,addr); /* set MISO to 0 */
15418 +       }
15419 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_SET);
15420 +       writel(GPIO_EECK,addr); /* set EECK to 1 */
15421 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15422 +       writel(GPIO_EECK,addr); /* set EECK to 0 */
15423 +
15424 +       //return ;
15425 +}
15426 +
15427 +/**********************************************************************
15428 +* read a bit from ADM6996 register
15429 +***********************************************************************/
15430 +unsigned int SPI_read_bit(void) // read data from
15431 +{
15432 +       unsigned int addr;
15433 +       unsigned int value;
15434 +
15435 +       addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
15436 +       value = readl(addr) & (~GPIO_MISO);   // set EECK to output and MISO to input
15437 +       writel(value,addr);
15438 +
15439 +       addr =(GPIO_BASE_ADDR1 + GPIO_DATA_SET);
15440 +       writel(GPIO_EECK,addr); // set EECK to 1
15441 +
15442 +
15443 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_IN);
15444 +       value = readl(addr) ;
15445 +
15446 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15447 +       writel(GPIO_EECK,addr); // set EECK to 0
15448 +
15449 +
15450 +       value = value >> 30;
15451 +       return value ;
15452 +}
15453 +
15454 +/******************************************
15455 +* SPI_default
15456 +* EEPROM content default value
15457 +*******************************************/
15458 +int SPI_default(void)
15459 +{
15460 +       int i;
15461 +       unsigned reg_val,cmd;
15462 +
15463 +#if 0
15464 +       SPI_write(7,0,0x1C,0x01);                               // map code space to 0
15465 +
15466 +       reg_val = SPI_read(7,0,0x10);
15467 +       reg_val |= 0x0146;
15468 +       reg_val &= ~0x0001;
15469 +       SPI_write(7,0,0x10,reg_val);                            // reset iCPU and enable ext_access
15470 +       SPI_write(7,0,0x11,0x0000);                             // start address
15471 +       for(i=0;i<sizeof(vts_img);i++){
15472 +               SPI_write(7,0,0x12,vts_img[i]);                 // fill in ROM data
15473 +       }
15474 +       reg_val |= BIT(0)|BIT(3);
15475 +       SPI_write(7,0,0x10,reg_val);                            // release iCPU
15476 +       SPI_write(7,0,0x10,SPI_read(7,0,0x10)&~BIT(7));                         // release iCPU
15477 +       return ;
15478 +#endif
15479 +
15480 +
15481 +       for(i=0;i<15;i++){
15482 +               if(i!=6 && i!=7)
15483 +                       SPI_write(3,2,0,0x1010400+i);           // Initial memory
15484 +               mdelay(1);
15485 +       }
15486 +
15487 +       mdelay(30);
15488 +
15489 +       SPI_write(2,0,0xB0,0x05);                       // Clear MAC table
15490 +       SPI_write(2,0,0xD0,0x03);                       // Clear VLAN
15491 +
15492 +       //for(i=0;i<5;i++)
15493 +       SPI_write(1,6,0x19,0x2C);                       // Double Data rate
15494 +
15495 +       for(i=0;i<4;i++){
15496 +               SPI_write(1,i,0x00,0x30050472);         // MAC configure
15497 +               SPI_write(1,i,0x00,0x10050442);         // MAC configure
15498 +               SPI_write(1,i,0x10,0x5F4);              // Max length
15499 +               SPI_write(1,i,0x04,0x00030000);         // Flow control
15500 +               SPI_write(1,i,0xDF,0x00000001);         // Flow control
15501 +               SPI_write(1,i,0x08,0x000050c2);         // Flow control mac high
15502 +               SPI_write(1,i,0x0C,0x002b00f1);         // Flow control mac low
15503 +               SPI_write(1,i,0x6E,BIT(3));             // forward pause frame
15504 +       }
15505 +       SPI_write(1,i,0x00,0x20000030);                 // set port 4 as reset
15506 +
15507 +       SPI_write(1,6,0x00,0x300701B1);                 // MAC configure
15508 +       SPI_write(1,6,0x00,0x10070181);                 // MAC configure
15509 +       SPI_write(1,6,0x10,0x5F4);                      // Max length
15510 +       SPI_write(1,6,0x04,0x00030000);         // Flow control
15511 +       SPI_write(1,6,0xDF,0x00000002);         // Flow control
15512 +       SPI_write(1,6,0x08,0x000050c2);         // Flow control mac high
15513 +       SPI_write(1,6,0x0C,0x002b00f1);         // Flow control mac low
15514 +       SPI_write(1,6,0x6E,BIT(3));             // forward pause frame
15515 +
15516 +
15517 +       //SPI_write(7,0,0x05,0x31);                     // MII delay for loader
15518 +       //SPI_write(7,0,0x05,0x01);                     // MII delay for kernel
15519 +       SPI_write(7,0,0x05,0x33);
15520 +
15521 +       SPI_write(2,0,0x10,0x4F);                       // Receive mask
15522 +
15523 +       mdelay(50);
15524 +
15525 +       SPI_write(7,0,0x14,0x02);                       // Release Reset
15526 +
15527 +       mdelay(3);
15528 +
15529 +       for(i=0;i<4;i++){
15530 +               init_seq_7385(i);
15531 +               phy_receiver_init(i);
15532 +               cmd = BIT(26)|(i<<21)|(0x1B<<16);       // Config LED
15533 +               SPI_write(3,0,1,cmd);
15534 +               mdelay(10);
15535 +               reg_val = SPI_read(3,0,2);
15536 +               reg_val &= 0xFF00;
15537 +               reg_val |= 0x61;
15538 +               cmd = (i<<21)|(0x1B<<16)|reg_val;
15539 +               SPI_write(3,0,1,cmd);
15540 +
15541 +               cmd = BIT(26)|(i<<21)|(0x04<<16);       // Pause enable
15542 +               SPI_write(3,0,1,cmd);
15543 +               mdelay(10);
15544 +               reg_val = SPI_read(3,0,2);
15545 +               reg_val |= BIT(10)|BIT(11);
15546 +               cmd = (i<<21)|(0x04<<16)|reg_val;
15547 +               SPI_write(3,0,1,cmd);
15548 +
15549 +               cmd = BIT(26)|(i<<21)|(0x0<<16);        // collision test and re-negotiation
15550 +               SPI_write(3,0,1,cmd);
15551 +               mdelay(10);
15552 +               reg_val = SPI_read(3,0,2);
15553 +               reg_val |= BIT(7)|BIT(8)|BIT(9);
15554 +               cmd = (i<<21)|(0x0<<16)|reg_val;
15555 +               SPI_write(3,0,1,cmd);
15556 +       }
15557 +       init_seq_7385(i);
15558 +       writel(0x5787a7f0,GMAC_GLOBAL_BASE_ADDR+0x1c);//For switch timing
15559 +       return 4;               // return port_no
15560 +}
15561 +EXPORT_SYMBOL(SPI_default);
15562 +
15563 +/***********************************************************
15564 +* SPI_CS_enable
15565 +* before access ,you have to enable Chip Select. (pull high)
15566 +* When fisish, you should pull low !!
15567 +*************************************************************/
15568 +void SPI_CS_enable(unsigned char enable)
15569 +{
15570 +
15571 +       unsigned int addr,value;
15572 +
15573 +       addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
15574 +       value = readl(addr) |GPIO_EECS |GPIO_EECK;   /* set EECS/EECK Pin to output */
15575 +       writel(value,addr);
15576 +
15577 +       if(enable)
15578 +       {
15579 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15580 +               writel(GPIO_EECK,addr); /* set EECK to 0 */     // pull low clk first
15581 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15582 +               writel(GPIO_EECS,addr); /* set EECS to 0 */
15583 +
15584 +       }
15585 +       else
15586 +       {
15587 +               addr = (GPIO_BASE_ADDR1 + GPIO_DATA_SET);
15588 +               writel(GPIO_EECK,addr); /* set EECK to 1 */     // pull high clk before disable
15589 +               writel(GPIO_EECS,addr); /* set EECS to 1 */
15590 +       }
15591 +}
15592 +
15593 +
15594 +/************************************************
15595 +* SPI_read
15596 +* table -> which table to be read: 1/count  0/EEPROM
15597 +* addr  -> Address to be read
15598 +* return : Value of the register
15599 +*************************************************/
15600 +unsigned int SPI_read(unsigned char block,unsigned char subblock,unsigned char addr)
15601 +{
15602 +       int     i;
15603 +       char    bit;
15604 +       unsigned int data,value=0;
15605 +
15606 +       SPI_CS_enable(1);
15607 +
15608 +       data = (block<<5) | subblock;
15609 +
15610 +       //send write command
15611 +       for(i=SPI_OP_LEN-1;i>=0;i--)
15612 +       {
15613 +               bit = (data>>i)& 0x01;
15614 +               SPI_write_bit(bit);
15615 +       }
15616 +
15617 +       // send 8 bits address (MSB first, LSB last)
15618 +       for(i=SPI_ADD_LEN-1;i>=0;i--)
15619 +       {
15620 +               bit = (addr>>i)& 0x01;
15621 +               SPI_write_bit(bit);
15622 +       }
15623 +
15624 +       // dummy read for chip ready
15625 +       for(i=0;i<8;i++)
15626 +               SPI_read_bit();
15627 +
15628 +
15629 +       // read 32 bits data (MSB first, LSB last)
15630 +       for(i=SPI_DAT_LEN-1;i>=0;i--)
15631 +       {
15632 +               bit = SPI_read_bit();
15633 +               value |= bit<<i;
15634 +       }
15635 +
15636 +       SPI_CS_enable(0);       // CS low
15637 +       return(value);
15638 +
15639 +}
15640 +
15641 +void pull_low_gpio(unsigned int val)
15642 +{
15643 +
15644 +       unsigned int addr,value;
15645 +
15646 +       addr = (GPIO_BASE_ADDR1 + GPIO_DATA_CLEAR);
15647 +       writel(val,addr); /* set pin low to save power*/
15648 +
15649 +       addr = (GPIO_BASE_ADDR1 + GPIO_PIN_DIR);
15650 +       value = readl(addr) & ~ val;   /* set Pin to input */
15651 +       writel(value,addr);
15652 +
15653 +//     value = readl(GMAC_GLOBAL_BASE_ADDR+0x0C);      // reset GPIO1 module(self clear)
15654 +//     value |= BIT(21);
15655 +//     writel(value,GMAC_GLOBAL_BASE_ADDR+0x0C);
15656 +}
15657 +
15658 +unsigned int SPI_get_identifier(void)
15659 +{
15660 +       unsigned int flag=0;
15661 +
15662 +       SPI_write(7,0,0x01,0x01);
15663 +       flag = SPI_read(7,0,0x18);  // chip id
15664 +       if((flag & 0x0ffff000)==0x07385000){
15665 +               printk("Get VSC-switch ID 0x%08x\n",flag);
15666 +               //Giga_switch = 1;;
15667 +               return 1;
15668 +       }
15669 +       else{
15670 +               printk("VSC-switch not found\n");
15671 +               //Giga_switch = 0;
15672 +               pull_low_gpio(GPIO_EECK|GPIO_MOSI|GPIO_MISO|GPIO_EECS); // reduce power consume
15673 +               return 0;
15674 +       }
15675 +}
15676 +EXPORT_SYMBOL(SPI_get_identifier);
15677 +
15678 Index: linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_gmac.h
15679 ===================================================================
15680 --- /dev/null
15681 +++ linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_gmac.h
15682 @@ -0,0 +1,2223 @@
15683 +/****************************************************************************
15684 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
15685 +*--------------------------------------------------------------------------
15686 +* Name                 : sl351x_gmac.h
15687 +* Description  :
15688 +*              Define for device driver of Storlink SL351x network Engine
15689 +*
15690 +* Historych
15691 +*
15692 +*      Date            Writer          Description
15693 +*      -----------     -----------     -------------------------------------------------
15694 +*      08/22/2005      Gary Chen       Create and implement
15695 +*
15696 +****************************************************************************/
15697 +#ifndef _GMAC_SL351x_H
15698 +#define _GMAC_SL351x_H
15699 +#include <linux/skbuff.h>
15700 +
15701 +#define SL351x_GMAC_WORKAROUND         1
15702 +
15703 +#undef BIG_ENDIAN
15704 +#define BIG_ENDIAN                             0
15705 +#define GMAC_DEBUG                             1
15706 +#define GMAC_NUM                                       2
15707 +//#define      L2_jumbo_frame                          1
15708 +
15709 +#define _PACKED_                                       __attribute__ ((aligned(1), packed))
15710 +
15711 +#ifndef BIT
15712 +#define BIT(x)                                         (1 << (x))
15713 +#endif
15714 +
15715 +#define REG32(addr)                            (*(volatile unsigned long  * const)(addr))
15716 +
15717 +#define DMA_MALLOC(size,handle)                pci_alloc_consistent(NULL,size,handle)
15718 +#define DMA_MFREE(mem,size,handle)     pci_free_consistent(NULL,size,mem,handle)
15719 +
15720 +// Define frame size
15721 +#define ETHER_ADDR_LEN                         6
15722 +#define GMAC_MAX_ETH_FRAME_SIZE                1514
15723 +#define GMAC_TX_BUF_SIZE                       ((GMAC_MAX_ETH_FRAME_SIZE + 31) & (~31))
15724 +#define MAX_ISR_WORK                   20
15725 +
15726 +#ifdef L2_jumbo_frame
15727 +#define SW_RX_BUF_SIZE                         9234    // 2048 ,9234
15728 +#else
15729 +#define SW_RX_BUF_SIZE                         1536    // 2048
15730 +#endif
15731 +
15732 +#define HW_RX_BUF_SIZE                         1536    // 2048
15733 +
15734 +#define GMAC_DEV_TX_TIMEOUT            (10*HZ)                 //add by CH
15735 +#define        SKB_RESERVE_BYTES                       16
15736 +
15737 +/**********************************************************************
15738 + * Base Register
15739 + **********************************************************************/
15740 +#define TOE_BASE                                       (IO_ADDRESS(SL2312_TOE_BASE))
15741 +#define GMAC_GLOBAL_BASE_ADDR       (IO_ADDRESS(SL2312_GLOBAL_BASE))
15742 +
15743 +#define TOE_GLOBAL_BASE                                (TOE_BASE + 0x0000)
15744 +#define TOE_NONTOE_QUE_HDR_BASE                (TOE_BASE + 0x2000)
15745 +#define TOE_TOE_QUE_HDR_BASE           (TOE_BASE + 0x3000)
15746 +#define TOE_V_BIT_BASE                         (TOE_BASE + 0x4000)
15747 +#define TOE_A_BIT_BASE                         (TOE_BASE + 0x6000)
15748 +#define TOE_GMAC0_DMA_BASE                     (TOE_BASE + 0x8000)
15749 +#define TOE_GMAC0_BASE                         (TOE_BASE + 0xA000)
15750 +#define TOE_GMAC1_DMA_BASE                     (TOE_BASE + 0xC000)
15751 +#define TOE_GMAC1_BASE                         (TOE_BASE + 0xE000)
15752 +
15753 +/**********************************************************************
15754 + * Queue ID
15755 + **********************************************************************/
15756 +#define TOE_SW_FREE_QID                                0x00
15757 +#define TOE_HW_FREE_QID                                0x01
15758 +#define TOE_GMAC0_SW_TXQ0_QID          0x02
15759 +#define TOE_GMAC0_SW_TXQ1_QID          0x03
15760 +#define TOE_GMAC0_SW_TXQ2_QID          0x04
15761 +#define TOE_GMAC0_SW_TXQ3_QID          0x05
15762 +#define TOE_GMAC0_SW_TXQ4_QID          0x06
15763 +#define TOE_GMAC0_SW_TXQ5_QID          0x07
15764 +#define TOE_GMAC0_HW_TXQ0_QID          0x08
15765 +#define TOE_GMAC0_HW_TXQ1_QID          0x09
15766 +#define TOE_GMAC0_HW_TXQ2_QID          0x0A
15767 +#define TOE_GMAC0_HW_TXQ3_QID          0x0B
15768 +#define TOE_GMAC1_SW_TXQ0_QID          0x12
15769 +#define TOE_GMAC1_SW_TXQ1_QID          0x13
15770 +#define TOE_GMAC1_SW_TXQ2_QID          0x14
15771 +#define TOE_GMAC1_SW_TXQ3_QID          0x15
15772 +#define TOE_GMAC1_SW_TXQ4_QID          0x16
15773 +#define TOE_GMAC1_SW_TXQ5_QID          0x17
15774 +#define TOE_GMAC1_HW_TXQ0_QID          0x18
15775 +#define TOE_GMAC1_HW_TXQ1_QID          0x19
15776 +#define TOE_GMAC1_HW_TXQ2_QID          0x1A
15777 +#define TOE_GMAC1_HW_TXQ3_QID          0x1B
15778 +#define TOE_GMAC0_DEFAULT_QID          0x20
15779 +#define TOE_GMAC1_DEFAULT_QID          0x21
15780 +#define TOE_CLASSIFICATION_QID(x)      (0x22 + x)      // 0x22 ~ 0x2F
15781 +#define TOE_TOE_QID(x)                         (0x40 + x)      // 0x40 ~ 0x7F
15782 +
15783 +/**********************************************************************
15784 + * TOE DMA Queue Number should be 2^n, n = 6...12
15785 + * TOE DMA Queues are the following queue types:
15786 + *             SW Free Queue, HW Free Queue,
15787 + *             GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
15788 + * They have same descriptor numbers.
15789 + * The base address and descriptor number are configured at
15790 + * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
15791 + **********************************************************************/
15792 +#define TOE_SW_FREEQ_DESC_POWER                10
15793 +#define TOE_SW_FREEQ_DESC_NUM          (1<<TOE_SW_FREEQ_DESC_POWER)
15794 +#define TOE_HW_FREEQ_DESC_POWER                8
15795 +#define TOE_HW_FREEQ_DESC_NUM          (1<<TOE_HW_FREEQ_DESC_POWER)
15796 +#define TOE_GMAC0_SWTXQ_DESC_POWER     8
15797 +#define TOE_GMAC0_SWTXQ_DESC_NUM       (1<<TOE_GMAC0_SWTXQ_DESC_POWER)
15798 +#define TOE_GMAC0_HWTXQ_DESC_POWER     8
15799 +#define TOE_GMAC0_HWTXQ_DESC_NUM       (1<<TOE_GMAC0_HWTXQ_DESC_POWER)
15800 +#define TOE_GMAC1_SWTXQ_DESC_POWER     8
15801 +#define TOE_GMAC1_SWTXQ_DESC_NUM       (1<<TOE_GMAC1_SWTXQ_DESC_POWER)
15802 +#define TOE_GMAC1_HWTXQ_DESC_POWER     8
15803 +#define TOE_GMAC1_HWTXQ_DESC_NUM       (1<<TOE_GMAC1_HWTXQ_DESC_POWER)
15804 +#define TOE_DEFAULT_Q0_DESC_POWER      8
15805 +#define TOE_DEFAULT_Q0_DESC_NUM                (1<<TOE_DEFAULT_Q0_DESC_POWER)
15806 +#define TOE_DEFAULT_Q1_DESC_POWER      8
15807 +#define TOE_DEFAULT_Q1_DESC_NUM                (1<<TOE_DEFAULT_Q1_DESC_POWER)
15808 +#define TOE_TOE_DESC_POWER                     8
15809 +#define TOE_TOE_DESC_NUM                       (1<<TOE_TOE_DESC_POWER)
15810 +#define TOE_CLASS_DESC_POWER           8
15811 +#define TOE_CLASS_DESC_NUM                     (1<<TOE_CLASS_DESC_POWER)
15812 +#define TOE_INTR_DESC_POWER                    8
15813 +#define TOE_INTR_DESC_NUM                      (1<<TOE_INTR_DESC_POWER)
15814 +
15815 +#define TOE_TOE_QUEUE_MAX                      64
15816 +#define TOE_TOE_QUEUE_NUM                      64
15817 +#define TOE_CLASS_QUEUE_MAX                    14
15818 +#define TOE_CLASS_QUEUE_NUM                    14
15819 +#define TOE_INTR_QUEUE_MAX                     4
15820 +#define TOE_INTR_QUEUE_NUM                     4
15821 +#define TOE_SW_TXQ_MAX                         6
15822 +#define TOE_SW_TXQ_NUM                         1
15823 +#define TOE_HW_TXQ_MAX                         4
15824 +#define TOE_HW_TXQ_NUM                         4
15825 +#define _max(x,y)                                      ((x>y) ? x :y)
15826 +#define TX_DESC_NUM                                    _max(TOE_GMAC0_SWTXQ_DESC_NUM, TOE_GMAC1_SWTXQ_DESC_NUM)
15827 +
15828 +#define RWPTR_ADVANCE_ONE(x, max)      ((x == (max -1)) ? 0 : x+1)
15829 +#define RWPTR_RECEDE_ONE(x, max)       ((x == 0) ? (max -1) : x-1)
15830 +#define SET_WPTR(addr, data)           (*(volatile u16 * const)((u32)(addr)+2) = (u16)data)
15831 +#define SET_RPTR(addr, data)           (*(volatile u16 * const)((u32)(addr)) = (u16)data)
15832 +
15833 +/**********************************************************************
15834 + * Global registers
15835 + * #define TOE_GLOBAL_BASE                     (TOE_BASE + 0x0000)
15836 + * Base 0x60000000
15837 + **********************************************************************/
15838 +#define GLOBAL_TOE_VERSION_REG                 0x0000
15839 +#define GLOBAL_SW_FREEQ_BASE_SIZE_REG  0x0004
15840 +#define GLOBAL_HW_FREEQ_BASE_SIZE_REG  0x0008
15841 +#define GLOBAL_DMA_SKB_SIZE_REG                        0x0010
15842 +#define GLOBAL_SWFQ_RWPTR_REG                  0x0014
15843 +#define GLOBAL_HWFQ_RWPTR_REG                  0x0018
15844 +#define GLOBAL_INTERRUPT_STATUS_0_REG  0x0020
15845 +#define GLOBAL_INTERRUPT_ENABLE_0_REG  0x0024
15846 +#define GLOBAL_INTERRUPT_SELECT_0_REG  0x0028
15847 +#define GLOBAL_INTERRUPT_STATUS_1_REG  0x0030
15848 +#define GLOBAL_INTERRUPT_ENABLE_1_REG  0x0034
15849 +#define GLOBAL_INTERRUPT_SELECT_1_REG  0x0038
15850 +#define GLOBAL_INTERRUPT_STATUS_2_REG  0x0040
15851 +#define GLOBAL_INTERRUPT_ENABLE_2_REG  0x0044
15852 +#define GLOBAL_INTERRUPT_SELECT_2_REG  0x0048
15853 +#define GLOBAL_INTERRUPT_STATUS_3_REG  0x0050
15854 +#define GLOBAL_INTERRUPT_ENABLE_3_REG  0x0054
15855 +#define GLOBAL_INTERRUPT_SELECT_3_REG  0x0058
15856 +#define GLOBAL_INTERRUPT_STATUS_4_REG  0x0060
15857 +#define GLOBAL_INTERRUPT_ENABLE_4_REG  0x0064
15858 +#define GLOBAL_INTERRUPT_SELECT_4_REG  0x0068
15859 +#define GLOBAL_HASH_TABLE_BASE_REG             0x006C
15860 +#define GLOBAL_QUEUE_THRESHOLD_REG             0x0070
15861 +
15862 +/**********************************************************************
15863 + * GMAC 0/1 DMA/TOE register
15864 + * #define TOE_GMAC0_DMA_BASE          (TOE_BASE + 0x8000)
15865 + * #define TOE_GMAC1_DMA_BASE          (TOE_BASE + 0xC000)
15866 + * Base 0x60008000 or 0x6000C000
15867 + **********************************************************************/
15868 +#define GMAC_DMA_CTRL_REG                              0x0000
15869 +#define GMAC_TX_WEIGHTING_CTRL_0_REG   0x0004
15870 +#define GMAC_TX_WEIGHTING_CTRL_1_REG   0x0008
15871 +#define GMAC_SW_TX_QUEUE0_PTR_REG              0x000C
15872 +#define GMAC_SW_TX_QUEUE1_PTR_REG              0x0010
15873 +#define GMAC_SW_TX_QUEUE2_PTR_REG              0x0014
15874 +#define GMAC_SW_TX_QUEUE3_PTR_REG              0x0018
15875 +#define GMAC_SW_TX_QUEUE4_PTR_REG              0x001C
15876 +#define GMAC_SW_TX_QUEUE5_PTR_REG              0x0020
15877 +#define GMAC_HW_TX_QUEUE0_PTR_REG              0x0024
15878 +#define GMAC_HW_TX_QUEUE1_PTR_REG              0x0028
15879 +#define GMAC_HW_TX_QUEUE2_PTR_REG              0x002C
15880 +#define GMAC_HW_TX_QUEUE3_PTR_REG              0x0030
15881 +#define GMAC_DMA_TX_FIRST_DESC_REG             0x0038
15882 +#define GMAC_DMA_TX_CURR_DESC_REG              0x003C
15883 +#define GMAC_DMA_TX_DESC_WORD0_REG             0x0040
15884 +#define GMAC_DMA_TX_DESC_WORD1_REG             0x0044
15885 +#define GMAC_DMA_TX_DESC_WORD2_REG             0x0048
15886 +#define GMAC_DMA_TX_DESC_WORD3_REG             0x004C
15887 +#define GMAC_SW_TX_QUEUE_BASE_REG              0x0050
15888 +#define GMAC_HW_TX_QUEUE_BASE_REG              0x0054
15889 +#define GMAC_DMA_RX_FIRST_DESC_REG             0x0058
15890 +#define GMAC_DMA_RX_CURR_DESC_REG              0x005C
15891 +#define GMAC_DMA_RX_DESC_WORD0_REG             0x0060
15892 +#define GMAC_DMA_RX_DESC_WORD1_REG             0x0064
15893 +#define GMAC_DMA_RX_DESC_WORD2_REG             0x0068
15894 +#define GMAC_DMA_RX_DESC_WORD3_REG             0x006C
15895 +#define GMAC_HASH_ENGINE_REG0                  0x0070
15896 +#define GMAC_HASH_ENGINE_REG1                  0x0074
15897 +#define GMAC_MR0CR0                                            0x0078  // matching rule 0 Control register 0
15898 +#define GMAC_MR0CR1                                            0x007C  // matching rule 0 Control register 1
15899 +#define GMAC_MR0CR2                                            0x0080  // matching rule 0 Control register 2
15900 +#define GMAC_MR1CR0                                            0x0084  // matching rule 1 Control register 0
15901 +#define GMAC_MR1CR1                                            0x0088  // matching rule 1 Control register 1
15902 +#define GMAC_MR1CR2                                            0x008C  // matching rule 1 Control register 2
15903 +#define GMAC_MR2CR0                                            0x0090  // matching rule 2 Control register 0
15904 +#define GMAC_MR2CR1                                            0x0094  // matching rule 2 Control register 1
15905 +#define GMAC_MR2CR2                                            0x0098  // matching rule 2 Control register 2
15906 +#define GMAC_MR3CR0                                            0x009C  // matching rule 3 Control register 0
15907 +#define GMAC_MR3CR1                                            0x00A0  // matching rule 3 Control register 1
15908 +#define GMAC_MR3CR2                                            0x00A4  // matching rule 3 Control register 2
15909 +#define GMAC_SPR0                                              0x00A8  // Support Protocol Regsister 0
15910 +#define GMAC_SPR1                                              0x00AC  // Support Protocol Regsister 1
15911 +#define GMAC_SPR2                                              0x00B0  // Support Protocol Regsister 2
15912 +#define GMAC_SPR3                                              0x00B4  // Support Protocol Regsister 3
15913 +#define GMAC_SPR4                                              0x00B8  // Support Protocol Regsister 4
15914 +#define GMAC_SPR5                                              0x00BC  // Support Protocol Regsister 5
15915 +#define GMAC_SPR6                                              0x00C0  // Support Protocol Regsister 6
15916 +#define GMAC_SPR7                                              0x00C4  // Support Protocol Regsister 7
15917 +#define GMAC_AHB_WEIGHT_REG                            0x00C8  // GMAC Hash/Rx/Tx AHB Weighting register
15918 +
15919 +/**********************************************************************
15920 + * TOE GMAC 0/1 register
15921 + * #define TOE_GMAC0_BASE                              (TOE_BASE + 0xA000)
15922 + * #define TOE_GMAC1_BASE                              (TOE_BASE + 0xE000)
15923 + * Base 0x6000A000 or 0x6000E000
15924 + **********************************************************************/
15925 +enum GMAC_REGISTER {
15926 +       GMAC_STA_ADD0   = 0x0000,
15927 +       GMAC_STA_ADD1   = 0x0004,
15928 +       GMAC_STA_ADD2   = 0x0008,
15929 +       GMAC_RX_FLTR    = 0x000c,
15930 +       GMAC_MCAST_FIL0 = 0x0010,
15931 +       GMAC_MCAST_FIL1 = 0x0014,
15932 +       GMAC_CONFIG0    = 0x0018,
15933 +       GMAC_CONFIG1    = 0x001c,
15934 +       GMAC_CONFIG2    = 0x0020,
15935 +       GMAC_CONFIG3    = 0x0024,
15936 +       GMAC_RESERVED   = 0x0028,
15937 +       GMAC_STATUS             = 0x002c,
15938 +       GMAC_IN_DISCARDS= 0x0030,
15939 +       GMAC_IN_ERRORS  = 0x0034,
15940 +       GMAC_IN_MCAST   = 0x0038,
15941 +       GMAC_IN_BCAST   = 0x003c,
15942 +       GMAC_IN_MAC1    = 0x0040,       // for STA 1 MAC Address
15943 +       GMAC_IN_MAC2    = 0x0044        // for STA 2 MAC Address
15944 +};
15945 +/**********************************************************************
15946 + * TOE version Register (offset 0x0000)
15947 + **********************************************************************/
15948 +typedef union
15949 +{
15950 +       unsigned int bits32;
15951 +       struct bit
15952 +       {
15953 +#if (BIG_ENDIAN==1)
15954 +
15955 +               unsigned int reserved           : 15;   // bit 31:17
15956 +               unsigned int v_bit_mode         : 1;    // bit 16               1: 128-entry
15957 +               unsigned int device_id          : 12;   // bit 15:4     Device ID
15958 +               unsigned int revision_id        : 4;    // bit  3:0     Revision ID
15959 +#else
15960 +               unsigned int revision_id        : 4;    // bit  3:0     Revision ID
15961 +               unsigned int device_id          : 12;   // bit 15:4     Device ID
15962 +               unsigned int v_bit_mode         : 1;    // bit 16               1: 128-entry
15963 +               unsigned int reserved           : 15;   // bit 31:17
15964 +#endif
15965 +       } bits;
15966 +} TOE_VERSION_T;
15967 +
15968 +
15969 +/**********************************************************************
15970 + * DMA Queues description Ring Base Address/Size Register (offset 0x0004)
15971 + **********************************************************************/
15972 +typedef union
15973 +{
15974 +       unsigned int bits32;
15975 +       unsigned int base_size;
15976 +} DMA_Q_BASE_SIZE_T;
15977 +#define DMA_Q_BASE_MASK        (~0x0f)
15978 +
15979 +/**********************************************************************
15980 + * DMA SKB Buffer register (offset 0x0008)
15981 + **********************************************************************/
15982 +typedef union
15983 +{
15984 +       unsigned int bits32;
15985 +       struct bit_0008
15986 +       {
15987 +#if (BIG_ENDIAN==1)
15988 +
15989 +               unsigned int hw_skb_size        : 16;   // bit 31:16    HW Free poll SKB Size
15990 +               unsigned int sw_skb_size        : 16;   // bit 15:0     SW Free poll SKB Size
15991 +#else
15992 +               unsigned int sw_skb_size        : 16;   // bit 15:0     SW Free poll SKB Size
15993 +               unsigned int hw_skb_size        : 16;   // bit 31:16    HW Free poll SKB Size
15994 +#endif
15995 +       } bits;
15996 +} DMA_SKB_SIZE_T;
15997 +
15998 +/**********************************************************************
15999 + * DMA SW Free Queue Read/Write Pointer Register (offset 0x000C)
16000 + **********************************************************************/
16001 +typedef union
16002 +{
16003 +       unsigned int bits32;
16004 +       struct bit_000c
16005 +       {
16006 +#if (BIG_ENDIAN==1)
16007 +
16008 +               unsigned int wptr                       : 16;   // bit 31:16    Write Ptr, RW
16009 +               unsigned int rptr                       : 16;   // bit 15:0             Read Ptr, RO
16010 +#else
16011 +               unsigned int rptr                       : 16;   // bit 15:0             Read Ptr, RO
16012 +               unsigned int wptr                       : 16;   // bit 31:16    Write Ptr, RW
16013 +#endif
16014 +       } bits;
16015 +} DMA_RWPTR_T;
16016 +
16017 +/**********************************************************************
16018 + * DMA HW Free Queue Read/Write Pointer Register (offset 0x0010)
16019 + **********************************************************************/
16020 +// see DMA_RWPTR_T structure
16021 +
16022 +/**********************************************************************
16023 + * Interrupt Status Register 0         (offset 0x0020)
16024 + * Interrupt Mask Register 0   (offset 0x0024)
16025 + * Interrupt Select Register 0         (offset 0x0028)
16026 + **********************************************************************/
16027 +typedef union
16028 +{
16029 +       unsigned int bits32;
16030 +       struct bit_0020
16031 +       {
16032 +#if (BIG_ENDIAN==1)
16033 +               unsigned int txDerr1            : 1;    // bit 31       GMAC1 AHB Bus Error while Tx
16034 +               unsigned int txPerr1            : 1;    // bit 30       GMAC1 Tx Descriptor Protocol Error
16035 +               unsigned int txDerr0            : 1;    // bit 29       GMAC0 AHB Bus Error while Tx
16036 +               unsigned int txPerr0            : 1;    // bit 28       GMAC0 Tx Descriptor Protocol Error
16037 +               unsigned int rxDerr1            : 1;    // bit 27       GMAC1 AHB Bus Error while Rx
16038 +               unsigned int rxPerr1            : 1;    // bit 26       GMAC1 Rx Descriptor Protocol Error
16039 +               unsigned int rxDerr0            : 1;    // bit 25       GMAC0 AHB Bus Error while Rx
16040 +               unsigned int rxPerr0            : 1;    // bit 24       GMAC0 Rx Descriptor Protocol Error
16041 +               unsigned int swtq15_fin         : 1;    // bit 23       GMAC1 SW Tx Queue 5 Finish Interrupt
16042 +               unsigned int swtq14_fin         : 1;    // bit 22       GMAC1 SW Tx Queue 4 Finish Interrupt
16043 +               unsigned int swtq13_fin         : 1;    // bit 21       GMAC1 SW Tx Queue 3 Finish Interrupt
16044 +               unsigned int swtq12_fin         : 1;    // bit 20       GMAC1 SW Tx Queue 2 Finish Interrupt
16045 +               unsigned int swtq11_fin         : 1;    // bit 19       GMAC1 SW Tx Queue 1 Finish Interrupt
16046 +               unsigned int swtq10_fin         : 1;    // bit 18       GMAC1 SW Tx Queue 0 Finish Interrupt
16047 +               unsigned int swtq05_fin         : 1;    // bit 17       GMAC0 SW Tx Queue 5 Finish Interrupt
16048 +               unsigned int swtq04_fin         : 1;    // bit 16       GMAC0 SW Tx Queue 4 Finish Interrupt
16049 +               unsigned int swtq03_fin         : 1;    // bit 15       GMAC0 SW Tx Queue 3 Finish Interrupt
16050 +               unsigned int swtq02_fin         : 1;    // bit 14       GMAC0 SW Tx Queue 2 Finish Interrupt
16051 +               unsigned int swtq01_fin         : 1;    // bit 13       GMAC0 SW Tx Queue 1 Finish Interrupt
16052 +               unsigned int swtq00_fin         : 1;    // bit 12       GMAC0 SW Tx Queue 0 Finish Interrupt
16053 +               unsigned int swtq15_eof         : 1;    // bit 11       GMAC1 SW Tx Queue 5 EOF Interrupt
16054 +               unsigned int swtq14_eof         : 1;    // bit 10       GMAC1 SW Tx Queue 4 EOF Interrupt
16055 +               unsigned int swtq13_eof         : 1;    // bit 9        GMAC1 SW Tx Queue 3 EOF Interrupt
16056 +               unsigned int swtq12_eof         : 1;    // bit 8        GMAC1 SW Tx Queue 2 EOF Interrupt
16057 +               unsigned int swtq11_eof         : 1;    // bit 7        GMAC1 SW Tx Queue 1 EOF Interrupt
16058 +               unsigned int swtq10_eof         : 1;    // bit 6        GMAC1 SW Tx Queue 0 EOF Interrupt
16059 +               unsigned int swtq05_eof         : 1;    // bit 5        GMAC0 SW Tx Queue 5 EOF Interrupt
16060 +               unsigned int swtq04_eof         : 1;    // bit 4        GMAC0 SW Tx Queue 4 EOF Interrupt
16061 +               unsigned int swtq03_eof         : 1;    // bit 3        GMAC0 SW Tx Queue 3 EOF Interrupt
16062 +               unsigned int swtq02_eof         : 1;    // bit 2        GMAC0 SW Tx Queue 2 EOF Interrupt
16063 +               unsigned int swtq01_eof         : 1;    // bit 1        GMAC0 SW Tx Queue 1 EOF Interrupt
16064 +               unsigned int swtq00_eof         : 1;    // bit 0        GMAC0 SW Tx Queue 0 EOF Interrupt
16065 +#else
16066 +               unsigned int swtq00_eof         : 1;    // bit 0        GMAC0 SW Tx Queue 0 EOF Interrupt
16067 +               unsigned int swtq01_eof         : 1;    // bit 1        GMAC0 SW Tx Queue 1 EOF Interrupt
16068 +               unsigned int swtq02_eof         : 1;    // bit 2        GMAC0 SW Tx Queue 2 EOF Interrupt
16069 +               unsigned int swtq03_eof         : 1;    // bit 3        GMAC0 SW Tx Queue 3 EOF Interrupt
16070 +               unsigned int swtq04_eof         : 1;    // bit 4        GMAC0 SW Tx Queue 4 EOF Interrupt
16071 +               unsigned int swtq05_eof         : 1;    // bit 5        GMAC0 SW Tx Queue 5 EOF Interrupt
16072 +               unsigned int swtq10_eof         : 1;    // bit 6        GMAC1 SW Tx Queue 0 EOF Interrupt
16073 +               unsigned int swtq11_eof         : 1;    // bit 7        GMAC1 SW Tx Queue 1 EOF Interrupt
16074 +               unsigned int swtq12_eof         : 1;    // bit 8        GMAC1 SW Tx Queue 2 EOF Interrupt
16075 +               unsigned int swtq13_eof         : 1;    // bit 9        GMAC1 SW Tx Queue 3 EOF Interrupt
16076 +               unsigned int swtq14_eof         : 1;    // bit 10       GMAC1 SW Tx Queue 4 EOF Interrupt
16077 +               unsigned int swtq15_eof         : 1;    // bit 11       GMAC1 SW Tx Queue 5 EOF Interrupt
16078 +               unsigned int swtq00_fin         : 1;    // bit 12       GMAC0 SW Tx Queue 0 Finish Interrupt
16079 +               unsigned int swtq01_fin         : 1;    // bit 13       GMAC0 SW Tx Queue 1 Finish Interrupt
16080 +               unsigned int swtq02_fin         : 1;    // bit 14       GMAC0 SW Tx Queue 2 Finish Interrupt
16081 +               unsigned int swtq03_fin         : 1;    // bit 15       GMAC0 SW Tx Queue 3 Finish Interrupt
16082 +               unsigned int swtq04_fin         : 1;    // bit 16       GMAC0 SW Tx Queue 4 Finish Interrupt
16083 +               unsigned int swtq05_fin         : 1;    // bit 17       GMAC0 SW Tx Queue 5 Finish Interrupt
16084 +               unsigned int swtq10_fin         : 1;    // bit 18       GMAC1 SW Tx Queue 0 Finish Interrupt
16085 +               unsigned int swtq11_fin         : 1;    // bit 19       GMAC1 SW Tx Queue 1 Finish Interrupt
16086 +               unsigned int swtq12_fin         : 1;    // bit 20       GMAC1 SW Tx Queue 2 Finish Interrupt
16087 +               unsigned int swtq13_fin         : 1;    // bit 21       GMAC1 SW Tx Queue 3 Finish Interrupt
16088 +               unsigned int swtq14_fin         : 1;    // bit 22       GMAC1 SW Tx Queue 4 Finish Interrupt
16089 +               unsigned int swtq15_fin         : 1;    // bit 23       GMAC1 SW Tx Queue 5 Finish Interrupt
16090 +               unsigned int rxPerr0            : 1;    // bit 24       GMAC0 Rx Descriptor Protocol Error
16091 +               unsigned int rxDerr0            : 1;    // bit 25       GMAC0 AHB Bus Error while Rx
16092 +               unsigned int rxPerr1            : 1;    // bit 26       GMAC1 Rx Descriptor Protocol Error
16093 +               unsigned int rxDerr1            : 1;    // bit 27       GMAC1 AHB Bus Error while Rx
16094 +               unsigned int txPerr0            : 1;    // bit 28       GMAC0 Tx Descriptor Protocol Error
16095 +               unsigned int txDerr0            : 1;    // bit 29       GMAC0 AHB Bus Error while Tx
16096 +               unsigned int txPerr1            : 1;    // bit 30       GMAC1 Tx Descriptor Protocol Error
16097 +               unsigned int txDerr1            : 1;    // bit 31       GMAC1 AHB Bus Error while Tx
16098 +#endif
16099 +       } bits;
16100 +} INTR_REG0_T;
16101 +
16102 +#define GMAC1_TXDERR_INT_BIT           BIT(31)
16103 +#define GMAC1_TXPERR_INT_BIT           BIT(30)
16104 +#define GMAC0_TXDERR_INT_BIT           BIT(29)
16105 +#define GMAC0_TXPERR_INT_BIT           BIT(28)
16106 +#define GMAC1_RXDERR_INT_BIT           BIT(27)
16107 +#define GMAC1_RXPERR_INT_BIT           BIT(26)
16108 +#define GMAC0_RXDERR_INT_BIT           BIT(25)
16109 +#define GMAC0_RXPERR_INT_BIT           BIT(24)
16110 +#define GMAC1_SWTQ15_FIN_INT_BIT       BIT(23)
16111 +#define GMAC1_SWTQ14_FIN_INT_BIT       BIT(22)
16112 +#define GMAC1_SWTQ13_FIN_INT_BIT       BIT(21)
16113 +#define GMAC1_SWTQ12_FIN_INT_BIT       BIT(20)
16114 +#define GMAC1_SWTQ11_FIN_INT_BIT       BIT(19)
16115 +#define GMAC1_SWTQ10_FIN_INT_BIT       BIT(18)
16116 +#define GMAC0_SWTQ05_FIN_INT_BIT       BIT(17)
16117 +#define GMAC0_SWTQ04_FIN_INT_BIT       BIT(16)
16118 +#define GMAC0_SWTQ03_FIN_INT_BIT       BIT(15)
16119 +#define GMAC0_SWTQ02_FIN_INT_BIT       BIT(14)
16120 +#define GMAC0_SWTQ01_FIN_INT_BIT       BIT(13)
16121 +#define GMAC0_SWTQ00_FIN_INT_BIT       BIT(12)
16122 +#define GMAC1_SWTQ15_EOF_INT_BIT       BIT(11)
16123 +#define GMAC1_SWTQ14_EOF_INT_BIT       BIT(10)
16124 +#define GMAC1_SWTQ13_EOF_INT_BIT       BIT(9)
16125 +#define GMAC1_SWTQ12_EOF_INT_BIT       BIT(8)
16126 +#define GMAC1_SWTQ11_EOF_INT_BIT       BIT(7)
16127 +#define GMAC1_SWTQ10_EOF_INT_BIT       BIT(6)
16128 +#define GMAC0_SWTQ05_EOF_INT_BIT       BIT(5)
16129 +#define GMAC0_SWTQ04_EOF_INT_BIT       BIT(4)
16130 +#define GMAC0_SWTQ03_EOF_INT_BIT       BIT(3)
16131 +#define GMAC0_SWTQ02_EOF_INT_BIT       BIT(2)
16132 +#define GMAC0_SWTQ01_EOF_INT_BIT       BIT(1)
16133 +#define GMAC0_SWTQ00_EOF_INT_BIT       BIT(0)
16134 +
16135 +
16136 +/**********************************************************************
16137 + * Interrupt Status Register 1         (offset 0x0030)
16138 + * Interrupt Mask Register 1   (offset 0x0034)
16139 + * Interrupt Select Register 1         (offset 0x0038)
16140 + **********************************************************************/
16141 +typedef union
16142 +{
16143 +       unsigned int bits32;
16144 +       struct bit_0030
16145 +       {
16146 +#if (BIG_ENDIAN==1)
16147 +               unsigned int toe_iq3_full       : 1;    // bit 31       TOE Interrupt Queue 3 Full Interrupt
16148 +               unsigned int toe_iq2_full       : 1;    // bit 30       TOE Interrupt Queue 2 Full Interrupt
16149 +               unsigned int toe_iq1_full       : 1;    // bit 29       TOE Interrupt Queue 1 Full Interrupt
16150 +               unsigned int toe_iq0_full       : 1;    // bit 28       TOE Interrupt Queue 0 Full Interrupt
16151 +               unsigned int toe_iq3_intr       : 1;    // bit 27       TOE Interrupt Queue 3 with Interrupts
16152 +               unsigned int toe_iq2_intr       : 1;    // bit 26       TOE Interrupt Queue 2 with Interrupts
16153 +               unsigned int toe_iq1_intr       : 1;    // bit 25       TOE Interrupt Queue 1 with Interrupts
16154 +               unsigned int toe_iq0_intr       : 1;    // bit 24       TOE Interrupt Queue 0 with Interrupts
16155 +               unsigned int hwtq13_eof         : 1;    // bit 23       GMAC1 HW Tx Queue3 EOF Interrupt
16156 +               unsigned int hwtq12_eof         : 1;    // bit 22       GMAC1 HW Tx Queue2 EOF Interrupt
16157 +               unsigned int hwtq11_eof         : 1;    // bit 21       GMAC1 HW Tx Queue1 EOF Interrupt
16158 +               unsigned int hwtq10_eof         : 1;    // bit 20       GMAC1 HW Tx Queue0 EOF Interrupt
16159 +               unsigned int hwtq03_eof         : 1;    // bit 19       GMAC0 HW Tx Queue3 EOF Interrupt
16160 +               unsigned int hwtq02_eof         : 1;    // bit 18       GMAC0 HW Tx Queue2 EOF Interrupt
16161 +               unsigned int hwtq01_eof         : 1;    // bit 17       GMAC0 HW Tx Queue1 EOF Interrupt
16162 +               unsigned int hwtq00_eof         : 1;    // bit 16       GMAC0 HW Tx Queue0 EOF Interrupt
16163 +               unsigned int class_rx           : 14;   // bit 15:2     Classification Queue Rx Interrupt
16164 +               unsigned int default_q1_eof     : 1;    // bit 1        Default Queue 1 EOF Interrupt
16165 +               unsigned int default_q0_eof     : 1;    // bit 0        Default Queue 0 EOF Interrupt
16166 +#else
16167 +               unsigned int default_q0_eof     : 1;    // bit 0        Default Queue 0 EOF Interrupt
16168 +               unsigned int default_q1_eof     : 1;    // bit 1        Default Queue 1 EOF Interrupt
16169 +               unsigned int class_rx           : 14;   // bit 15:2     Classification Queue Rx Interrupt
16170 +               unsigned int hwtq00_eof         : 1;    // bit 16       GMAC0 HW Tx Queue0 EOF Interrupt
16171 +               unsigned int hwtq01_eof         : 1;    // bit 17       GMAC0 HW Tx Queue1 EOF Interrupt
16172 +               unsigned int hwtq02_eof         : 1;    // bit 18       GMAC0 HW Tx Queue2 EOF Interrupt
16173 +               unsigned int hwtq03_eof         : 1;    // bit 19       GMAC0 HW Tx Queue3 EOF Interrupt
16174 +               unsigned int hwtq10_eof         : 1;    // bit 20       GMAC1 HW Tx Queue0 EOF Interrupt
16175 +               unsigned int hwtq11_eof         : 1;    // bit 21       GMAC1 HW Tx Queue1 EOF Interrupt
16176 +               unsigned int hwtq12_eof         : 1;    // bit 22       GMAC1 HW Tx Queue2 EOF Interrupt
16177 +               unsigned int hwtq13_eof         : 1;    // bit 23       GMAC1 HW Tx Queue3 EOF Interrupt
16178 +               unsigned int toe_iq0_intr       : 1;    // bit 24       TOE Interrupt Queue 0 with Interrupts
16179 +               unsigned int toe_iq1_intr       : 1;    // bit 25       TOE Interrupt Queue 1 with Interrupts
16180 +               unsigned int toe_iq2_intr       : 1;    // bit 26       TOE Interrupt Queue 2 with Interrupts
16181 +               unsigned int toe_iq3_intr       : 1;    // bit 27       TOE Interrupt Queue 3 with Interrupts
16182 +               unsigned int toe_iq0_full       : 1;    // bit 28       TOE Interrupt Queue 0 Full Interrupt
16183 +               unsigned int toe_iq1_full       : 1;    // bit 29       TOE Interrupt Queue 1 Full Interrupt
16184 +               unsigned int toe_iq2_full       : 1;    // bit 30       TOE Interrupt Queue 2 Full Interrupt
16185 +               unsigned int toe_iq3_full       : 1;    // bit 31       TOE Interrupt Queue 3 Full Interrupt
16186 +#endif
16187 +       } bits;
16188 +} INTR_REG1_T;
16189 +
16190 +#define TOE_IQ3_FULL_INT_BIT           BIT(31)
16191 +#define TOE_IQ2_FULL_INT_BIT           BIT(30)
16192 +#define TOE_IQ1_FULL_INT_BIT           BIT(29)
16193 +#define TOE_IQ0_FULL_INT_BIT           BIT(28)
16194 +#define TOE_IQ3_INT_BIT                                BIT(27)
16195 +#define TOE_IQ2_INT_BIT                                BIT(26)
16196 +#define TOE_IQ1_INT_BIT                                BIT(25)
16197 +#define TOE_IQ0_INT_BIT                                BIT(24)
16198 +#define GMAC1_HWTQ13_EOF_INT_BIT       BIT(23)
16199 +#define GMAC1_HWTQ12_EOF_INT_BIT       BIT(22)
16200 +#define GMAC1_HWTQ11_EOF_INT_BIT       BIT(21)
16201 +#define GMAC1_HWTQ10_EOF_INT_BIT       BIT(20)
16202 +#define GMAC0_HWTQ03_EOF_INT_BIT       BIT(19)
16203 +#define GMAC0_HWTQ02_EOF_INT_BIT       BIT(18)
16204 +#define GMAC0_HWTQ01_EOF_INT_BIT       BIT(17)
16205 +#define GMAC0_HWTQ00_EOF_INT_BIT       BIT(16)
16206 +#define CLASS_RX_INT_BIT(x)                    BIT((x+2))
16207 +#define DEFAULT_Q1_INT_BIT                     BIT(1)
16208 +#define DEFAULT_Q0_INT_BIT                     BIT(0)
16209 +
16210 +#define TOE_IQ_INT_BITS                                (TOE_IQ0_INT_BIT | TOE_IQ1_INT_BIT | \
16211 +                                                       TOE_IQ2_INT_BIT | TOE_IQ3_INT_BIT)
16212 +#define        TOE_IQ_FULL_BITS                        (TOE_IQ0_FULL_INT_BIT | TOE_IQ1_FULL_INT_BIT | \
16213 +                                                       TOE_IQ2_FULL_INT_BIT | TOE_IQ3_FULL_INT_BIT)
16214 +#define        TOE_IQ_ALL_BITS                         (TOE_IQ_INT_BITS | TOE_IQ_FULL_BITS)
16215 +#define TOE_CLASS_RX_INT_BITS          0xfffc
16216 +
16217 +/**********************************************************************
16218 + * Interrupt Status Register 2         (offset 0x0040)
16219 + * Interrupt Mask Register 2   (offset 0x0044)
16220 + * Interrupt Select Register 2         (offset 0x0048)
16221 + **********************************************************************/
16222 +typedef union
16223 +{
16224 +       unsigned int bits32;
16225 +       struct bit_0040
16226 +       {
16227 +#if (BIG_ENDIAN==1)
16228 +               unsigned int toe_q31_full       : 1;    // bit 31       TOE Queue 31 Full Interrupt
16229 +               unsigned int toe_q30_full       : 1;    // bit 30       TOE Queue 30 Full Interrupt
16230 +               unsigned int toe_q29_full       : 1;    // bit 29       TOE Queue 29 Full Interrupt
16231 +               unsigned int toe_q28_full       : 1;    // bit 28       TOE Queue 28 Full Interrupt
16232 +               unsigned int toe_q27_full       : 1;    // bit 27       TOE Queue 27 Full Interrupt
16233 +               unsigned int toe_q26_full       : 1;    // bit 26       TOE Queue 26 Full Interrupt
16234 +               unsigned int toe_q25_full       : 1;    // bit 25       TOE Queue 25 Full Interrupt
16235 +               unsigned int toe_q24_full       : 1;    // bit 24       TOE Queue 24 Full Interrupt
16236 +               unsigned int toe_q23_full       : 1;    // bit 23       TOE Queue 23 Full Interrupt
16237 +               unsigned int toe_q22_full       : 1;    // bit 22       TOE Queue 22 Full Interrupt
16238 +               unsigned int toe_q21_full       : 1;    // bit 21       TOE Queue 21 Full Interrupt
16239 +               unsigned int toe_q20_full       : 1;    // bit 20       TOE Queue 20 Full Interrupt
16240 +               unsigned int toe_q19_full       : 1;    // bit 19       TOE Queue 19 Full Interrupt
16241 +               unsigned int toe_q18_full       : 1;    // bit 18       TOE Queue 18 Full Interrupt
16242 +               unsigned int toe_q17_full       : 1;    // bit 17       TOE Queue 17 Full Interrupt
16243 +               unsigned int toe_q16_full       : 1;    // bit 16       TOE Queue 16 Full Interrupt
16244 +               unsigned int toe_q15_full       : 1;    // bit 15       TOE Queue 15 Full Interrupt
16245 +               unsigned int toe_q14_full       : 1;    // bit 14       TOE Queue 14 Full Interrupt
16246 +               unsigned int toe_q13_full       : 1;    // bit 13       TOE Queue 13 Full Interrupt
16247 +               unsigned int toe_q12_full       : 1;    // bit 12       TOE Queue 12 Full Interrupt
16248 +               unsigned int toe_q11_full       : 1;    // bit 11       TOE Queue 11 Full Interrupt
16249 +               unsigned int toe_q10_full       : 1;    // bit 10       TOE Queue 10 Full Interrupt
16250 +               unsigned int toe_q9_full        : 1;    // bit 9        TOE Queue 9 Full Interrupt
16251 +               unsigned int toe_q8_full        : 1;    // bit 8        TOE Queue 8 Full Interrupt
16252 +               unsigned int toe_q7_full        : 1;    // bit 7        TOE Queue 7 Full Interrupt
16253 +               unsigned int toe_q6_full        : 1;    // bit 6        TOE Queue 6 Full Interrupt
16254 +               unsigned int toe_q5_full        : 1;    // bit 5        TOE Queue 5 Full Interrupt
16255 +               unsigned int toe_q4_full        : 1;    // bit 4        TOE Queue 4 Full Interrupt
16256 +               unsigned int toe_q3_full        : 1;    // bit 3        TOE Queue 3 Full Interrupt
16257 +               unsigned int toe_q2_full        : 1;    // bit 2        TOE Queue 2 Full Interrupt
16258 +               unsigned int toe_q1_full        : 1;    // bit 1        TOE Queue 1 Full Interrupt
16259 +               unsigned int toe_q0_full        : 1;    // bit 0        TOE Queue 0 Full Interrupt
16260 +#else
16261 +               unsigned int toe_q0_full        : 1;    // bit 0        TOE Queue 0 Full Interrupt
16262 +               unsigned int toe_q1_full        : 1;    // bit 1        TOE Queue 1 Full Interrupt
16263 +               unsigned int toe_q2_full        : 1;    // bit 2        TOE Queue 2 Full Interrupt
16264 +               unsigned int toe_q3_full        : 1;    // bit 3        TOE Queue 3 Full Interrupt
16265 +               unsigned int toe_q4_full        : 1;    // bit 4        TOE Queue 4 Full Interrupt
16266 +               unsigned int toe_q5_full        : 1;    // bit 5        TOE Queue 5 Full Interrupt
16267 +               unsigned int toe_q6_full        : 1;    // bit 6        TOE Queue 6 Full Interrupt
16268 +               unsigned int toe_q7_full        : 1;    // bit 7        TOE Queue 7 Full Interrupt
16269 +               unsigned int toe_q8_full        : 1;    // bit 8        TOE Queue 8 Full Interrupt
16270 +               unsigned int toe_q9_full        : 1;    // bit 9        TOE Queue 9 Full Interrupt
16271 +               unsigned int toe_q10_full       : 1;    // bit 10       TOE Queue 10 Full Interrupt
16272 +               unsigned int toe_q11_full       : 1;    // bit 11       TOE Queue 11 Full Interrupt
16273 +               unsigned int toe_q12_full       : 1;    // bit 12       TOE Queue 12 Full Interrupt
16274 +               unsigned int toe_q13_full       : 1;    // bit 13       TOE Queue 13 Full Interrupt
16275 +               unsigned int toe_q14_full       : 1;    // bit 14       TOE Queue 14 Full Interrupt
16276 +               unsigned int toe_q15_full       : 1;    // bit 15       TOE Queue 15 Full Interrupt
16277 +               unsigned int toe_q16_full       : 1;    // bit 16       TOE Queue 16 Full Interrupt
16278 +               unsigned int toe_q17_full       : 1;    // bit 17       TOE Queue 17 Full Interrupt
16279 +               unsigned int toe_q18_full       : 1;    // bit 18       TOE Queue 18 Full Interrupt
16280 +               unsigned int toe_q19_full       : 1;    // bit 19       TOE Queue 19 Full Interrupt
16281 +               unsigned int toe_q20_full       : 1;    // bit 20       TOE Queue 20 Full Interrupt
16282 +               unsigned int toe_q21_full       : 1;    // bit 21       TOE Queue 21 Full Interrupt
16283 +               unsigned int toe_q22_full       : 1;    // bit 22       TOE Queue 22 Full Interrupt
16284 +               unsigned int toe_q23_full       : 1;    // bit 23       TOE Queue 23 Full Interrupt
16285 +               unsigned int toe_q24_full       : 1;    // bit 24       TOE Queue 24 Full Interrupt
16286 +               unsigned int toe_q25_full       : 1;    // bit 25       TOE Queue 25 Full Interrupt
16287 +               unsigned int toe_q26_full       : 1;    // bit 26       TOE Queue 26 Full Interrupt
16288 +               unsigned int toe_q27_full       : 1;    // bit 27       TOE Queue 27 Full Interrupt
16289 +               unsigned int toe_q28_full       : 1;    // bit 28       TOE Queue 28 Full Interrupt
16290 +               unsigned int toe_q29_full       : 1;    // bit 29       TOE Queue 29 Full Interrupt
16291 +               unsigned int toe_q30_full       : 1;    // bit 30       TOE Queue 30 Full Interrupt
16292 +               unsigned int toe_q31_full       : 1;    // bit 31       TOE Queue 31 Full Interrupt
16293 +#endif
16294 +       } bits;
16295 +} INTR_REG2_T;
16296 +
16297 +#define TOE_QL_FULL_INT_BIT(x)         BIT(x)
16298 +
16299 +/**********************************************************************
16300 + * Interrupt Status Register 3         (offset 0x0050)
16301 + * Interrupt Mask Register 3   (offset 0x0054)
16302 + * Interrupt Select Register 3         (offset 0x0058)
16303 + **********************************************************************/
16304 +typedef union
16305 +{
16306 +       unsigned int bits32;
16307 +       struct bit_0050
16308 +       {
16309 +#if (BIG_ENDIAN==1)
16310 +               unsigned int toe_q63_full       : 1;    // bit 63       TOE Queue 63 Full Interrupt
16311 +               unsigned int toe_q62_full       : 1;    // bit 62       TOE Queue 62 Full Interrupt
16312 +               unsigned int toe_q61_full       : 1;    // bit 61       TOE Queue 61 Full Interrupt
16313 +               unsigned int toe_q60_full       : 1;    // bit 60       TOE Queue 60 Full Interrupt
16314 +               unsigned int toe_q59_full       : 1;    // bit 59       TOE Queue 59 Full Interrupt
16315 +               unsigned int toe_q58_full       : 1;    // bit 58       TOE Queue 58 Full Interrupt
16316 +               unsigned int toe_q57_full       : 1;    // bit 57       TOE Queue 57 Full Interrupt
16317 +               unsigned int toe_q56_full       : 1;    // bit 56       TOE Queue 56 Full Interrupt
16318 +               unsigned int toe_q55_full       : 1;    // bit 55       TOE Queue 55 Full Interrupt
16319 +               unsigned int toe_q54_full       : 1;    // bit 54       TOE Queue 54 Full Interrupt
16320 +               unsigned int toe_q53_full       : 1;    // bit 53       TOE Queue 53 Full Interrupt
16321 +               unsigned int toe_q52_full       : 1;    // bit 52       TOE Queue 52 Full Interrupt
16322 +               unsigned int toe_q51_full       : 1;    // bit 51       TOE Queue 51 Full Interrupt
16323 +               unsigned int toe_q50_full       : 1;    // bit 50       TOE Queue 50 Full Interrupt
16324 +               unsigned int toe_q49_full       : 1;    // bit 49       TOE Queue 49 Full Interrupt
16325 +               unsigned int toe_q48_full       : 1;    // bit 48       TOE Queue 48 Full Interrupt
16326 +               unsigned int toe_q47_full       : 1;    // bit 47       TOE Queue 47 Full Interrupt
16327 +               unsigned int toe_q46_full       : 1;    // bit 46       TOE Queue 46 Full Interrupt
16328 +               unsigned int toe_q45_full       : 1;    // bit 45       TOE Queue 45 Full Interrupt
16329 +               unsigned int toe_q44_full       : 1;    // bit 44       TOE Queue 44 Full Interrupt
16330 +               unsigned int toe_q43_full       : 1;    // bit 43       TOE Queue 43 Full Interrupt
16331 +               unsigned int toe_q42_full       : 1;    // bit 42       TOE Queue 42 Full Interrupt
16332 +               unsigned int toe_q41_full       : 1;    // bit 41       TOE Queue 41 Full Interrupt
16333 +               unsigned int toe_q40_full       : 1;    // bit 40       TOE Queue 40 Full Interrupt
16334 +               unsigned int toe_q39_full       : 1;    // bit 39       TOE Queue 39 Full Interrupt
16335 +               unsigned int toe_q38_full       : 1;    // bit 38       TOE Queue 38 Full Interrupt
16336 +               unsigned int toe_q37_full       : 1;    // bit 37       TOE Queue 37 Full Interrupt
16337 +               unsigned int toe_q36_full       : 1;    // bit 36       TOE Queue 36 Full Interrupt
16338 +               unsigned int toe_q35_full       : 1;    // bit 35       TOE Queue 35 Full Interrupt
16339 +               unsigned int toe_q34_full       : 1;    // bit 34       TOE Queue 34 Full Interrupt
16340 +               unsigned int toe_q33_full       : 1;    // bit 33       TOE Queue 33 Full Interrupt
16341 +               unsigned int toe_q32_full       : 1;    // bit 32       TOE Queue 32 Full Interrupt
16342 +#else
16343 +               unsigned int toe_q32_full       : 1;    // bit 32       TOE Queue 32 Full Interrupt
16344 +               unsigned int toe_q33_full       : 1;    // bit 33       TOE Queue 33 Full Interrupt
16345 +               unsigned int toe_q34_full       : 1;    // bit 34       TOE Queue 34 Full Interrupt
16346 +               unsigned int toe_q35_full       : 1;    // bit 35       TOE Queue 35 Full Interrupt
16347 +               unsigned int toe_q36_full       : 1;    // bit 36       TOE Queue 36 Full Interrupt
16348 +               unsigned int toe_q37_full       : 1;    // bit 37       TOE Queue 37 Full Interrupt
16349 +               unsigned int toe_q38_full       : 1;    // bit 38       TOE Queue 38 Full Interrupt
16350 +               unsigned int toe_q39_full       : 1;    // bit 39       TOE Queue 39 Full Interrupt
16351 +               unsigned int toe_q40_full       : 1;    // bit 40       TOE Queue 40 Full Interrupt
16352 +               unsigned int toe_q41_full       : 1;    // bit 41       TOE Queue 41 Full Interrupt
16353 +               unsigned int toe_q42_full       : 1;    // bit 42       TOE Queue 42 Full Interrupt
16354 +               unsigned int toe_q43_full       : 1;    // bit 43       TOE Queue 43 Full Interrupt
16355 +               unsigned int toe_q44_full       : 1;    // bit 44       TOE Queue 44 Full Interrupt
16356 +               unsigned int toe_q45_full       : 1;    // bit 45       TOE Queue 45 Full Interrupt
16357 +               unsigned int toe_q46_full       : 1;    // bit 46       TOE Queue 46 Full Interrupt
16358 +               unsigned int toe_q47_full       : 1;    // bit 47       TOE Queue 47 Full Interrupt
16359 +               unsigned int toe_q48_full       : 1;    // bit 48       TOE Queue 48 Full Interrupt
16360 +               unsigned int toe_q49_full       : 1;    // bit 49       TOE Queue 49 Full Interrupt
16361 +               unsigned int toe_q50_full       : 1;    // bit 50       TOE Queue 50 Full Interrupt
16362 +               unsigned int toe_q51_full       : 1;    // bit 51       TOE Queue 51 Full Interrupt
16363 +               unsigned int toe_q52_full       : 1;    // bit 52       TOE Queue 52 Full Interrupt
16364 +               unsigned int toe_q53_full       : 1;    // bit 53       TOE Queue 53 Full Interrupt
16365 +               unsigned int toe_q54_full       : 1;    // bit 54       TOE Queue 54 Full Interrupt
16366 +               unsigned int toe_q55_full       : 1;    // bit 55       TOE Queue 55 Full Interrupt
16367 +               unsigned int toe_q56_full       : 1;    // bit 56       TOE Queue 56 Full Interrupt
16368 +               unsigned int toe_q57_full       : 1;    // bit 57       TOE Queue 57 Full Interrupt
16369 +               unsigned int toe_q58_full       : 1;    // bit 58       TOE Queue 58 Full Interrupt
16370 +               unsigned int toe_q59_full       : 1;    // bit 59       TOE Queue 59 Full Interrupt
16371 +               unsigned int toe_q60_full       : 1;    // bit 60       TOE Queue 60 Full Interrupt
16372 +               unsigned int toe_q61_full       : 1;    // bit 61       TOE Queue 61 Full Interrupt
16373 +               unsigned int toe_q62_full       : 1;    // bit 62       TOE Queue 62 Full Interrupt
16374 +               unsigned int toe_q63_full       : 1;    // bit 63       TOE Queue 63 Full Interrupt
16375 +#endif
16376 +       } bits;
16377 +} INTR_REG3_T;
16378 +
16379 +#define TOE_QH_FULL_INT_BIT(x)         BIT(x-32)
16380 +
16381 +/**********************************************************************
16382 + * Interrupt Status Register 4         (offset 0x0060)
16383 + * Interrupt Mask Register 4   (offset 0x0064)
16384 + * Interrupt Select Register 4         (offset 0x0068)
16385 + **********************************************************************/
16386 +typedef union
16387 +{
16388 +       unsigned char byte;
16389 +       struct bit_0060
16390 +       {
16391 +#if (BIG_ENDIAN==1)
16392 +               unsigned char reserved          : 1;    //
16393 +               unsigned char cnt_full          : 1;    // MIB counters half full interrupt
16394 +               unsigned char rx_pause_on       : 1;    // received pause on frame interrupt
16395 +               unsigned char tx_pause_on       : 1;    // transmit pause on frame interrupt
16396 +               unsigned char rx_pause_off  : 1;        // received pause off frame interrupt
16397 +               unsigned char tx_pause_off      : 1;    // received pause off frame interrupt
16398 +               unsigned char rx_overrun        : 1;    // GMAC Rx FIFO overrun interrupt
16399 +               unsigned char status_changed: 1;        // Status Changed Intr for RGMII Mode
16400 +#else
16401 +               unsigned char status_changed: 1;        // Status Changed Intr for RGMII Mode
16402 +               unsigned char rx_overrun        : 1;   // GMAC Rx FIFO overrun interrupt
16403 +               unsigned char tx_pause_off      : 1;    // received pause off frame interrupt
16404 +               unsigned char rx_pause_off  : 1;        // received pause off frame interrupt
16405 +               unsigned char tx_pause_on       : 1;    // transmit pause on frame interrupt
16406 +               unsigned char rx_pause_on       : 1;    // received pause on frame interrupt
16407 +               unsigned char cnt_full          : 1;    // MIB counters half full interrupt
16408 +               unsigned char reserved          : 1;    //
16409 +#endif
16410 +       } _PACKED_ bits;
16411 +} _PACKED_ GMAC_INTR_T;
16412 +
16413 +typedef union
16414 +{
16415 +       unsigned int bits32;
16416 +       struct bit_0060_2
16417 +       {
16418 +#if (BIG_ENDIAN==1)
16419 +               GMAC_INTR_T             gmac1;
16420 +               GMAC_INTR_T             gmac0;
16421 +               unsigned int    class_qf_int: 14;       // bit 15:2 Classification Rx Queue13-0 Full Intr.
16422 +               unsigned int    hwfq_empty      : 1;    // bit 1        Hardware Free Queue Empty Intr.
16423 +               unsigned int    swfq_empty      : 1;    // bit 0        Software Free Queue Empty Intr.
16424 +#else
16425 +#endif
16426 +               unsigned int    swfq_empty      : 1;    // bit 0        Software Free Queue Empty Intr.
16427 +               unsigned int    hwfq_empty      : 1;    // bit 1        Hardware Free Queue Empty Intr.
16428 +               unsigned int    class_qf_int: 14;       // bit 15:2 Classification Rx Queue13-0 Full Intr.
16429 +               GMAC_INTR_T             gmac0;
16430 +               GMAC_INTR_T             gmac1;
16431 +       } bits;
16432 +} INTR_REG4_T;
16433 +
16434 +#define GMAC1_RESERVED_INT_BIT         BIT(31)
16435 +#define GMAC1_MIB_INT_BIT                      BIT(30)
16436 +#define GMAC1_RX_PAUSE_ON_INT_BIT      BIT(29)
16437 +#define GMAC1_TX_PAUSE_ON_INT_BIT      BIT(28)
16438 +#define GMAC1_RX_PAUSE_OFF_INT_BIT     BIT(27)
16439 +#define GMAC1_TX_PAUSE_OFF_INT_BIT     BIT(26)
16440 +#define GMAC1_RX_OVERRUN_INT_BIT       BIT(25)
16441 +#define GMAC1_STATUS_CHANGE_INT_BIT    BIT(24)
16442 +#define GMAC0_RESERVED_INT_BIT         BIT(23)
16443 +#define GMAC0_MIB_INT_BIT                      BIT(22)
16444 +#define GMAC0_RX_PAUSE_ON_INT_BIT      BIT(21)
16445 +#define GMAC0_TX_PAUSE_ON_INT_BIT      BIT(20)
16446 +#define GMAC0_RX_PAUSE_OFF_INT_BIT     BIT(19)
16447 +#define GMAC0_TX_PAUSE_OFF_INT_BIT     BIT(18)
16448 +#define GMAC0_RX_OVERRUN_INT_BIT       BIT(17)
16449 +#define GMAC0_STATUS_CHANGE_INT_BIT    BIT(16)
16450 +#define CLASS_RX_FULL_INT_BIT(x)       BIT((x+2))
16451 +#define HWFQ_EMPTY_INT_BIT                     BIT(1)
16452 +#define SWFQ_EMPTY_INT_BIT                     BIT(0)
16453 +
16454 +#if 1
16455 +#define GMAC0_INT_BITS                         (GMAC0_MIB_INT_BIT)
16456 +#define GMAC1_INT_BITS                         (GMAC1_MIB_INT_BIT)
16457 +#else
16458 +#define GMAC0_INT_BITS                         (GMAC0_RESERVED_INT_BIT | GMAC0_MIB_INT_BIT | \
16459 +                                                                        GMAC0_RX_PAUSE_ON_INT_BIT | GMAC0_TX_PAUSE_ON_INT_BIT |        \
16460 +                                                                        GMAC0_RX_PAUSE_OFF_INT_BIT | GMAC0_TX_PAUSE_OFF_INT_BIT |      \
16461 +                                                                        GMAC0_RX_OVERRUN_INT_BIT | GMAC0_STATUS_CHANGE_INT_BIT)
16462 +#define GMAC1_INT_BITS                         (GMAC1_RESERVED_INT_BIT | GMAC1_MIB_INT_BIT | \
16463 +                                                                        GMAC1_RX_PAUSE_ON_INT_BIT | GMAC1_TX_PAUSE_ON_INT_BIT |        \
16464 +                                                                        GMAC1_RX_PAUSE_OFF_INT_BIT | GMAC1_TX_PAUSE_OFF_INT_BIT |      \
16465 +                                                                        GMAC1_RX_OVERRUN_INT_BIT | GMAC1_STATUS_CHANGE_INT_BIT)
16466 +#endif
16467 +
16468 +#define CLASS_RX_FULL_INT_BITS         0xfffc
16469 +
16470 +/**********************************************************************
16471 + * GLOBAL_QUEUE_THRESHOLD_REG  (offset 0x0070)
16472 + **********************************************************************/
16473 +typedef union
16474 +{
16475 +       unsigned int bits32;
16476 +       struct bit_0070_2
16477 +       {
16478 +#if (BIG_ENDIAN==1)
16479 +               unsigned int    toe_class       : 8;    // 31:24
16480 +               unsigned int    intrq           : 8;    // 23:16
16481 +               unsigned int    hwfq_empty      : 8;    // 15:8         Hardware Free Queue Empty Threshold
16482 +               unsigned int    swfq_empty      : 8;    //  7:0         Software Free Queue Empty Threshold
16483 +#else
16484 +#endif
16485 +               unsigned int    swfq_empty      : 8;    //  7:0         Software Free Queue Empty Threshold
16486 +               unsigned int    hwfq_empty      : 8;    // 15:8         Hardware Free Queue Empty Threshold
16487 +               unsigned int    intrq           : 8;    // 23:16
16488 +               unsigned int    toe_class       : 8;    // 31:24
16489 +       } bits;
16490 +} QUEUE_THRESHOLD_T;
16491 +
16492 +
16493 +/**********************************************************************
16494 + * GMAC DMA Control Register
16495 + * GMAC0 offset 0x8000
16496 + * GMAC1 offset 0xC000
16497 + **********************************************************************/
16498 +typedef union
16499 +{
16500 +       unsigned int bits32;
16501 +       struct bit_8000
16502 +       {
16503 +#if (BIG_ENDIAN==1)
16504 +               unsigned int    rd_enable               : 1;    // bit 31       Rx DMA Enable
16505 +               unsigned int    td_enable               : 1;    // bit 30       Tx DMA Enable
16506 +               unsigned int    loopback                : 1;    // bit 29       Loopback TxDMA to RxDMA
16507 +               unsigned int    drop_small_ack  : 1;    // bit 28       1: Drop, 0: Accept
16508 +               unsigned int    reserved                : 10;   // bit 27:18
16509 +               unsigned int    rd_insert_bytes : 2;    // bit 17:16
16510 +               unsigned int    rd_prot                 : 4;    // bit 15:12 DMA Protection Control
16511 +               unsigned int    rd_burst_size   : 2;    // bit 11:10 DMA max burst size for every AHB request
16512 +               unsigned int    rd_bus              : 2;        // bit 9:8      Peripheral Bus Width
16513 +               unsigned int    td_prot                 : 4;    // bit 7:4  TxDMA protection control
16514 +               unsigned int    td_burst_size   : 2;    // bit 3:2      TxDMA max burst size for every AHB request
16515 +               unsigned int    td_bus              : 2;        // bit 1:0  Peripheral Bus Width
16516 +#else
16517 +               unsigned int    td_bus              : 2;        // bit 1:0  Peripheral Bus Width
16518 +               unsigned int    td_burst_size   : 2;    // bit 3:2      TxDMA max burst size for every AHB request
16519 +               unsigned int    td_prot                 : 4;    // bit 7:4  TxDMA protection control
16520 +               unsigned int    rd_bus              : 2;        // bit 9:8      Peripheral Bus Width
16521 +               unsigned int    rd_burst_size   : 2;    // bit 11:10 DMA max burst size for every AHB request
16522 +               unsigned int    rd_prot                 : 4;    // bit 15:12 DMA Protection Control
16523 +               unsigned int    rd_insert_bytes : 2;    // bit 17:16
16524 +               unsigned int    reserved                : 10;   // bit 27:18
16525 +               unsigned int    drop_small_ack  : 1;    // bit 28       1: Drop, 0: Accept
16526 +               unsigned int    loopback                : 1;    // bit 29       Loopback TxDMA to RxDMA
16527 +               unsigned int    td_enable               : 1;    // bit 30       Tx DMA Enable
16528 +               unsigned int    rd_enable               : 1;    // bit 31       Rx DMA Enable
16529 +#endif
16530 +       } bits;
16531 +} GMAC_DMA_CTRL_T;
16532 +
16533 +/**********************************************************************
16534 + * GMAC Tx Weighting Control Register 0
16535 + * GMAC0 offset 0x8004
16536 + * GMAC1 offset 0xC004
16537 + **********************************************************************/
16538 +typedef union
16539 +{
16540 +       unsigned int bits32;
16541 +       struct bit_8004
16542 +       {
16543 +#if (BIG_ENDIAN==1)
16544 +               unsigned int    reserved                : 8;    // bit 31:24
16545 +               unsigned int    hw_tq3                  : 6;    // bit 23:18    HW TX Queue 0
16546 +               unsigned int    hw_tq2                  : 6;    // bit 17:12    HW TX Queue 1
16547 +               unsigned int    hw_tq1                  : 6;    // bit 11:6             HW TX Queue 2
16548 +               unsigned int    hw_tq0                  : 6;    // bit 5:0              HW TX Queue 3
16549 +#else
16550 +               unsigned int    hw_tq0                  : 6;    // bit 5:0              HW TX Queue 3
16551 +               unsigned int    hw_tq1                  : 6;    // bit 11:6             HW TX Queue 2
16552 +               unsigned int    hw_tq2                  : 6;    // bit 17:12    HW TX Queue 1
16553 +               unsigned int    hw_tq3                  : 6;    // bit 23:18    HW TX Queue 0
16554 +               unsigned int    reserved                : 8;    // bit 31:24
16555 +#endif
16556 +       } bits;
16557 +} GMAC_TX_WCR0_T;      // Weighting Control Register 0
16558 +
16559 +/**********************************************************************
16560 + * GMAC Tx Weighting Control Register 1
16561 + * GMAC0 offset 0x8008
16562 + * GMAC1 offset 0xC008
16563 + **********************************************************************/
16564 +typedef union
16565 +{
16566 +       unsigned int bits32;
16567 +       struct bit_8008
16568 +       {
16569 +#if (BIG_ENDIAN==1)
16570 +               unsigned int    reserved                : 2;    // bit 31:30
16571 +               unsigned int    sw_tq5                  : 5;    // bit 29:25    SW TX Queue 5
16572 +               unsigned int    sw_tq4                  : 5;    // bit 24:20    SW TX Queue 4
16573 +               unsigned int    sw_tq3                  : 5;    // bit 19:15    SW TX Queue 3
16574 +               unsigned int    sw_tq2                  : 5;    // bit 14:10    SW TX Queue 2
16575 +               unsigned int    sw_tq1                  : 5;    // bit 9:5              SW TX Queue 1
16576 +               unsigned int    sw_tq0                  : 5;    // bit 4:0              SW TX Queue 0
16577 +#else
16578 +               unsigned int    sw_tq0                  : 5;    // bit 4:0              SW TX Queue 0
16579 +               unsigned int    sw_tq1                  : 5;    // bit 9:5              SW TX Queue 1
16580 +               unsigned int    sw_tq2                  : 5;    // bit 14:10    SW TX Queue 2
16581 +               unsigned int    sw_tq3                  : 5;    // bit 19:15    SW TX Queue 3
16582 +               unsigned int    sw_tq4                  : 5;    // bit 24:20    SW TX Queue 4
16583 +               unsigned int    sw_tq5                  : 5;    // bit 29:25    SW TX Queue 5
16584 +               unsigned int    reserved                : 2;    // bit 31:30
16585 +#endif
16586 +       } bits;
16587 +} GMAC_TX_WCR1_T;      // Weighting Control Register 1
16588 +
16589 +/**********************************************************************
16590 + * Queue Read/Write Pointer
16591 + * GMAC SW TX Queue 0~5 Read/Write Pointer register
16592 + * GMAC0 offset 0x800C ~ 0x8020
16593 + * GMAC1 offset 0xC00C ~ 0xC020
16594 + * GMAC HW TX Queue 0~3 Read/Write Pointer register
16595 + * GMAC0 offset 0x8024 ~ 0x8030
16596 + * GMAC1 offset 0xC024 ~ 0xC030
16597 + **********************************************************************/
16598 +// see DMA_RWPTR_T structure
16599 +
16600 +/**********************************************************************
16601 + * GMAC DMA Tx First Description Address Register
16602 + * GMAC0 offset 0x8038
16603 + * GMAC1 offset 0xC038
16604 + **********************************************************************/
16605 +typedef union
16606 +{
16607 +       unsigned int bits32;
16608 +       struct bit_8038
16609 +       {
16610 +#if (BIG_ENDIAN==1)
16611 +               unsigned int td_first_des_ptr   : 28;   // bit 31:4     first descriptor address
16612 +               unsigned int td_busy                    :  1;   // bit 3        1: TxDMA busy; 0: TxDMA idle
16613 +               unsigned int reserved                   :  3;
16614 +#else
16615 +               unsigned int reserved                   :  3;
16616 +               unsigned int td_busy                    :  1;   // bit 3        1: TxDMA busy; 0: TxDMA idle
16617 +               unsigned int td_first_des_ptr   : 28;   // bit 31:4     first descriptor address
16618 +#endif
16619 +       } bits;
16620 +} GMAC_TXDMA_FIRST_DESC_T;
16621 +
16622 +/**********************************************************************
16623 + * GMAC DMA Tx Current Description Address Register
16624 + * GMAC0 offset 0x803C
16625 + * GMAC1 offset 0xC03C
16626 + **********************************************************************/
16627 +typedef union
16628 +{
16629 +       unsigned int bits32;
16630 +       struct bit_803C
16631 +       {
16632 +#if (BIG_ENDIAN==1)
16633 +               unsigned int td_curr_desc_ptr   : 28;   // bit 31:4     current descriptor address
16634 +               unsigned int reserved                   :  4;
16635 +#else
16636 +               unsigned int reserved                   :  4;
16637 +               unsigned int td_curr_desc_ptr   : 28;   // bit 31:4     current descriptor address
16638 +#endif
16639 +       } bits;
16640 +} GMAC_TXDMA_CURR_DESC_T;
16641 +
16642 +/**********************************************************************
16643 + * GMAC DMA Tx Description Word 0 Register
16644 + * GMAC0 offset 0x8040
16645 + * GMAC1 offset 0xC040
16646 + **********************************************************************/
16647 +typedef union
16648 +{
16649 +       unsigned int bits32;
16650 +       struct bit_8040
16651 +       {
16652 +#if (BIG_ENDIAN==1)
16653 +               unsigned int reserved           : 1;    // bit 31
16654 +               unsigned int derr                       : 1;    // bit 30        data error during processing this descriptor
16655 +               unsigned int perr                       : 1;    // bit 29        protocol error during processing this descriptor
16656 +               unsigned int status_rvd         : 6;    // bit 28:23 Tx Status, Reserved bits
16657 +               unsigned int status_tx_ok       : 1;    // bit 22    Tx Status, 1: Successful 0: Failed
16658 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
16659 +               unsigned int buffer_size        : 16;   // bit 15:0  Transfer size
16660 +#else
16661 +               unsigned int buffer_size        : 16;   // bit 15:0  Transfer size
16662 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
16663 +               unsigned int status_tx_ok       : 1;    // bit 22    Tx Status, 1: Successful 0: Failed
16664 +               unsigned int status_rvd         : 6;    // bit 28:23 Tx Status, Reserved bits
16665 +               unsigned int perr                       : 1;    // bit 29        protocol error during processing this descriptor
16666 +               unsigned int derr                       : 1;    // bit 30        data error during processing this descriptor
16667 +               unsigned int reserved           : 1;    // bit 31
16668 +#endif
16669 +       } bits;
16670 +} GMAC_TXDESC_0_T;
16671 +
16672 +/**********************************************************************
16673 + * GMAC DMA Tx Description Word 1 Register
16674 + * GMAC0 offset 0x8044
16675 + * GMAC1 offset 0xC044
16676 + **********************************************************************/
16677 +typedef union
16678 +{
16679 +       unsigned int bits32;
16680 +       struct txdesc_word1
16681 +       {
16682 +#if (BIG_ENDIAN==1)
16683 +               unsigned int    reserved        : 9;    // bit 31:23    Tx Flag, Reserved
16684 +               unsigned int    ip_fixed_len: 1;        // bit 22
16685 +               unsigned int    bypass_tss      : 1;    // bit 21
16686 +               unsigned int    udp_chksum      : 1;    // bit 20               UDP Checksum Enable
16687 +               unsigned int    tcp_chksum      : 1;    // bit 19               TCP Checksum Enable
16688 +               unsigned int    ipv6_enable     : 1;    // bit 18               IPV6 Tx Enable
16689 +               unsigned int    ip_chksum       : 1;    // bit 17               IPV4 Header Checksum Enable
16690 +               unsigned int    mtu_enable      : 1;    // bit 16               TSS segmentation use MTU setting
16691 +               unsigned int    byte_count      : 16;   // bit 15: 0    Tx Frame Byte Count
16692 +#else
16693 +               unsigned int    byte_count      : 16;   // bit 15: 0    Tx Frame Byte Count
16694 +               unsigned int    mtu_enable      : 1;    // bit 16               TSS segmentation use MTU setting
16695 +               unsigned int    ip_chksum       : 1;    // bit 17               IPV4 Header Checksum Enable
16696 +               unsigned int    ipv6_enable     : 1;    // bit 18               IPV6 Tx Enable
16697 +               unsigned int    tcp_chksum      : 1;    // bit 19               TCP Checksum Enable
16698 +               unsigned int    udp_chksum      : 1;    // bit 20               UDP Checksum Enable
16699 +               unsigned int    bypass_tss      : 1;    // bit 21
16700 +               unsigned int    ip_fixed_len: 1;        // bit 22
16701 +               unsigned int    reserved        : 9;    // bit 31:23    Tx Flag, Reserved
16702 +#endif
16703 +       } bits;
16704 +} GMAC_TXDESC_1_T;
16705 +
16706 +#define TSS_IP_FIXED_LEN_BIT   BIT(22)
16707 +#define TSS_UDP_CHKSUM_BIT             BIT(20)
16708 +#define TSS_TCP_CHKSUM_BIT             BIT(19)
16709 +#define TSS_IPV6_ENABLE_BIT            BIT(18)
16710 +#define TSS_IP_CHKSUM_BIT              BIT(17)
16711 +#define TSS_MTU_ENABLE_BIT             BIT(16)
16712 +
16713 +/**********************************************************************
16714 + * GMAC DMA Tx Description Word 2 Register
16715 + * GMAC0 offset 0x8048
16716 + * GMAC1 offset 0xC048
16717 + **********************************************************************/
16718 +typedef union
16719 +{
16720 +       unsigned int    bits32;
16721 +       unsigned int    buf_adr;
16722 +} GMAC_TXDESC_2_T;
16723 +
16724 +/**********************************************************************
16725 + * GMAC DMA Tx Description Word 3 Register
16726 + * GMAC0 offset 0x804C
16727 + * GMAC1 offset 0xC04C
16728 + **********************************************************************/
16729 +typedef union
16730 +{
16731 +       unsigned int bits32;
16732 +       struct txdesc_word3
16733 +       {
16734 +#if (BIG_ENDIAN==1)
16735 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
16736 +               unsigned int    eofie           : 1;    // bit 29               End of frame interrupt enable
16737 +               unsigned int    reserved        : 18;   // bit 28:11
16738 +               unsigned int    mtu_size        : 11;   // bit 10: 0    Tx Frame Byte Count
16739 +#else
16740 +               unsigned int    mtu_size        : 11;   // bit 10: 0    Tx Frame Byte Count
16741 +               unsigned int    reserved        : 18;   // bit 28:11
16742 +               unsigned int    eofie           : 1;    // bit 29               End of frame interrupt enable
16743 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
16744 +#endif
16745 +       } bits;
16746 +} GMAC_TXDESC_3_T;
16747 +#define SOF_EOF_BIT_MASK       0x3fffffff
16748 +#define SOF_BIT                                0x80000000
16749 +#define EOF_BIT                                0x40000000
16750 +#define EOFIE_BIT                      BIT(29)
16751 +#define MTU_SIZE_BIT_MASK      0x7ff
16752 +
16753 +/**********************************************************************
16754 + * GMAC Tx Descriptor
16755 + **********************************************************************/
16756 +typedef struct
16757 +{
16758 +       GMAC_TXDESC_0_T word0;
16759 +       GMAC_TXDESC_1_T word1;
16760 +       GMAC_TXDESC_2_T word2;
16761 +       GMAC_TXDESC_3_T word3;
16762 +} GMAC_TXDESC_T;
16763 +
16764 +
16765 +/**********************************************************************
16766 + * GMAC DMA Rx First Description Address Register
16767 + * GMAC0 offset 0x8058
16768 + * GMAC1 offset 0xC058
16769 + **********************************************************************/
16770 +typedef union
16771 +{
16772 +       unsigned int bits32;
16773 +       struct bit_8058
16774 +       {
16775 +#if (BIG_ENDIAN==1)
16776 +               unsigned int rd_first_des_ptr   : 28;   // bit 31:4 first descriptor address
16777 +               unsigned int rd_busy                    :  1;   // bit 3        1-RxDMA busy; 0-RxDMA idle
16778 +               unsigned int reserved                   :  3;   // bit 2:0
16779 +#else
16780 +               unsigned int reserved                   :  3;   // bit 2:0
16781 +               unsigned int rd_busy                    :  1;   // bit 3        1-RxDMA busy; 0-RxDMA idle
16782 +               unsigned int rd_first_des_ptr   : 28;   // bit 31:4 first descriptor address
16783 +#endif
16784 +       } bits;
16785 +} GMAC_RXDMA_FIRST_DESC_T;
16786 +
16787 +/**********************************************************************
16788 + * GMAC DMA Rx Current Description Address Register
16789 + * GMAC0 offset 0x805C
16790 + * GMAC1 offset 0xC05C
16791 + **********************************************************************/
16792 +typedef union
16793 +{
16794 +       unsigned int bits32;
16795 +       struct bit_805C
16796 +       {
16797 +#if (BIG_ENDIAN==1)
16798 +               unsigned int rd_curr_des_ptr    : 28;   // bit 31:4 current descriptor address
16799 +               unsigned int reserved                   :  4;   // bit 3:0
16800 +#else
16801 +               unsigned int reserved                   :  4;   // bit 3:0
16802 +               unsigned int rd_curr_des_ptr    : 28;   // bit 31:4 current descriptor address
16803 +#endif
16804 +       } bits;
16805 +} GMAC_RXDMA_CURR_DESC_T;
16806 +
16807 +/**********************************************************************
16808 + * GMAC DMA Rx Description Word 0 Register
16809 + * GMAC0 offset 0x8060
16810 + * GMAC1 offset 0xC060
16811 + **********************************************************************/
16812 +typedef union
16813 +{
16814 +       unsigned int bits32;
16815 +       struct bit_8060
16816 +       {
16817 +#if (BIG_ENDIAN==1)
16818 +               unsigned int drop                       : 1;    // bit 31        TOE/CIS Queue Full dropped packet to default queue
16819 +               unsigned int derr                       : 1;    // bit 30        data error during processing this descriptor
16820 +               unsigned int perr                       : 1;    // bit 29        protocol error during processing this descriptor
16821 +               unsigned int chksum_status      : 3;    // bit 28:26 Check Sum Status
16822 +               unsigned int status                     : 4;    // bit 24:22 Status of rx frame
16823 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
16824 +               unsigned int buffer_size        : 16;   // bit 15:0  number of descriptors used for the current frame
16825 +#else
16826 +               unsigned int buffer_size        : 16;   // bit 15:0  number of descriptors used for the current frame
16827 +               unsigned int desc_count         : 6;    // bit 21:16 number of descriptors used for the current frame
16828 +               unsigned int status                     : 4;    // bit 24:22 Status of rx frame
16829 +               unsigned int chksum_status      : 3;    // bit 28:26 Check Sum Status
16830 +               unsigned int perr                       : 1;    // bit 29        protocol error during processing this descriptor
16831 +               unsigned int derr                       : 1;    // bit 30        data error during processing this descriptor
16832 +               unsigned int drop                       : 1;    // bit 31        TOE/CIS Queue Full dropped packet to default queue
16833 +#endif
16834 +       } bits;
16835 +} GMAC_RXDESC_0_T;
16836 +
16837 +#define                GMAC_RXDESC_0_T_derr                            BIT(30)
16838 +#define                GMAC_RXDESC_0_T_perr                            BIT(29)
16839 +#define                GMAC_RXDESC_0_T_chksum_status(x)        BIT((x+26))
16840 +#define                GMAC_RXDESC_0_T_status(x)                       BIT((x+22))
16841 +#define                GMAC_RXDESC_0_T_desc_count(x)           BIT((x+16))
16842 +
16843 +#define        RX_CHKSUM_IP_UDP_TCP_OK                 0
16844 +#define        RX_CHKSUM_IP_OK_ONLY                    1
16845 +#define        RX_CHKSUM_NONE                                  2
16846 +#define        RX_CHKSUM_IP_ERR_UNKNOWN                4
16847 +#define        RX_CHKSUM_IP_ERR                                5
16848 +#define        RX_CHKSUM_TCP_UDP_ERR                   6
16849 +#define RX_CHKSUM_NUM                                  8
16850 +
16851 +#define RX_STATUS_GOOD_FRAME                   0
16852 +#define RX_STATUS_TOO_LONG_GOOD_CRC            1
16853 +#define RX_STATUS_RUNT_FRAME                   2
16854 +#define RX_STATUS_SFD_NOT_FOUND                        3
16855 +#define RX_STATUS_CRC_ERROR                            4
16856 +#define RX_STATUS_TOO_LONG_BAD_CRC             5
16857 +#define RX_STATUS_ALIGNMENT_ERROR              6
16858 +#define RX_STATUS_TOO_LONG_BAD_ALIGN   7
16859 +#define RX_STATUS_RX_ERR                               8
16860 +#define RX_STATUS_DA_FILTERED                  9
16861 +#define RX_STATUS_BUFFER_FULL                  10
16862 +#define RX_STATUS_NUM                                  16
16863 +
16864 +
16865 +/**********************************************************************
16866 + * GMAC DMA Rx Description Word 1 Register
16867 + * GMAC0 offset 0x8064
16868 + * GMAC1 offset 0xC064
16869 + **********************************************************************/
16870 +typedef union
16871 +{
16872 +       unsigned int bits32;
16873 +       struct rxdesc_word1
16874 +       {
16875 +#if (BIG_ENDIAN==1)
16876 +               unsigned int    sw_id           : 16;   // bit 31:16    Software ID
16877 +               unsigned int    byte_count      : 16;   // bit 15: 0    Rx Frame Byte Count
16878 +#else
16879 +               unsigned int    byte_count      : 16;   // bit 15: 0    Rx Frame Byte Count
16880 +               unsigned int    sw_id           : 16;   // bit 31:16    Software ID
16881 +#endif
16882 +       } bits;
16883 +} GMAC_RXDESC_1_T;
16884 +
16885 +/**********************************************************************
16886 + * GMAC DMA Rx Description Word 2 Register
16887 + * GMAC0 offset 0x8068
16888 + * GMAC1 offset 0xC068
16889 + **********************************************************************/
16890 +typedef union
16891 +{
16892 +       unsigned int    bits32;
16893 +       unsigned int    buf_adr;
16894 +} GMAC_RXDESC_2_T;
16895 +
16896 +#define RX_INSERT_NONE         0
16897 +#define RX_INSERT_1_BYTE       1
16898 +#define RX_INSERT_2_BYTE       2
16899 +#define RX_INSERT_3_BYTE       3
16900 +
16901 +#define RX_INSERT_BYTES                RX_INSERT_2_BYTE
16902 +/**********************************************************************
16903 + * GMAC DMA Rx Description Word 3 Register
16904 + * GMAC0 offset 0x806C
16905 + * GMAC1 offset 0xC06C
16906 + **********************************************************************/
16907 +typedef union
16908 +{
16909 +       unsigned int bits32;
16910 +       struct rxdesc_word3
16911 +       {
16912 +#if (BIG_ENDIAN==1)
16913 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
16914 +               unsigned int    eofie           : 1;    // bit 29               End of frame interrupt enable
16915 +               unsigned int    ctrl_flag       : 1;    // bit 28               Control Flag is present
16916 +               unsigned int    out_of_seq      : 1;    // bit 27               Out of Sequence packet
16917 +               unsigned int    option          : 1;    // bit 26               IPV4 option or IPV6 extension header
16918 +               unsigned int    abnormal        : 1;    // bit 25               abnormal case found
16919 +               unsigned int    dup_ack         : 1;    // bit 24               Duplicated ACK detected
16920 +               unsigned int    l7_offset       : 8;    // bit 23: 16   L7 data offset
16921 +               unsigned int    l4_offset       : 8;    // bit 15: 8    L4 data offset
16922 +               unsigned int    l3_offset       : 8;    // bit 7: 0             L3 data offset
16923 +#else
16924 +               unsigned int    l3_offset       : 8;    // bit 7: 0             L3 data offset
16925 +               unsigned int    l4_offset       : 8;    // bit 15: 8    L4 data offset
16926 +               unsigned int    l7_offset       : 8;    // bit 23: 16   L7 data offset
16927 +               unsigned int    dup_ack         : 1;    // bit 24               Duplicated ACK detected
16928 +               unsigned int    abnormal        : 1;    // bit 25               abnormal case found
16929 +               unsigned int    option          : 1;    // bit 26               IPV4 option or IPV6 extension header
16930 +               unsigned int    out_of_seq      : 1;    // bit 27               Out of Sequence packet
16931 +               unsigned int    ctrl_flag       : 1;    // bit 28               Control Flag is present
16932 +               unsigned int    eofie           : 1;    // bit 29               End of frame interrupt enable
16933 +               unsigned int    sof_eof         : 2;    // bit 31:30    11: only one, 10: first, 01: last, 00: linking
16934 +#endif
16935 +       } bits;
16936 +} GMAC_RXDESC_3_T;
16937 +
16938 +/**********************************************************************
16939 + * GMAC Rx Descriptor
16940 + **********************************************************************/
16941 +typedef struct
16942 +{
16943 +       GMAC_RXDESC_0_T word0;
16944 +       GMAC_RXDESC_1_T word1;
16945 +       GMAC_RXDESC_2_T word2;
16946 +       GMAC_RXDESC_3_T word3;
16947 +} GMAC_RXDESC_T;
16948 +
16949 +/**********************************************************************
16950 + * GMAC Hash Engine Enable/Action Register 0 Offset Register
16951 + * GMAC0 offset 0x8070
16952 + * GMAC1 offset 0xC070
16953 + **********************************************************************/
16954 +typedef union
16955 +{
16956 +       unsigned int bits32;
16957 +       struct bit_8070
16958 +       {
16959 +#if (BIG_ENDIAN==1)
16960 +               unsigned int    mr1en           : 1;    // bit 31               Enable Matching Rule 1
16961 +               unsigned int    reserved1       : 1;    // bit 30
16962 +               unsigned int    timing          : 3;    // bit 29:27
16963 +               unsigned int    mr1_action      : 5;    // bit 26:22    Matching Rule 1 action offset
16964 +               unsigned int    mr1hel          : 6;    // bit 21:16    match rule 1 hash entry size
16965 +               unsigned int    mr0en           : 1;    // bit 15               Enable Matching Rule 0
16966 +               unsigned int    reserved0       : 4;    // bit 14:11
16967 +               unsigned int    mr0_action      : 5;    // bit 10:6             Matching Rule 0 action offset
16968 +               unsigned int    mr0hel          : 6;    // bit 5:0              match rule 0 hash entry size
16969 +#else
16970 +               unsigned int    mr0hel          : 6;    // bit 5:0              match rule 0 hash entry size
16971 +               unsigned int    mr0_action      : 5;    // bit 10:6             Matching Rule 0 action offset
16972 +               unsigned int    reserved0       : 4;    // bit 14:11
16973 +               unsigned int    mr0en           : 1;    // bit 15               Enable Matching Rule 0
16974 +               unsigned int    mr1hel          : 6;    // bit 21:16    match rule 1 hash entry size
16975 +               unsigned int    mr1_action      : 5;    // bit 26:22    Matching Rule 1 action offset
16976 +               unsigned int    timing          : 3;    // bit 29:27
16977 +               unsigned int    reserved1       : 1;    // bit 30
16978 +               unsigned int    mr1en           : 1;    // bit 31               Enable Matching Rule 1
16979 +#endif
16980 +       } bits;
16981 +} GMAC_HASH_ENABLE_REG0_T;
16982 +
16983 +/**********************************************************************
16984 + * GMAC Hash Engine Enable/Action Register 1 Offset Register
16985 + * GMAC0 offset 0x8074
16986 + * GMAC1 offset 0xC074
16987 + **********************************************************************/
16988 +typedef union
16989 +{
16990 +       unsigned int bits32;
16991 +       struct bit_8074
16992 +       {
16993 +#if (BIG_ENDIAN==1)
16994 +               unsigned int    mr3en           : 1;    // bit 31               Enable Matching Rule 3
16995 +               unsigned int    reserved3       : 4;    // bit 30:27
16996 +               unsigned int    mr3_action      : 5;    // bit 26:22    Matching Rule 3 action offset
16997 +               unsigned int    mr3hel          : 6;    // bit 21:16    match rule 3 hash entry size
16998 +               unsigned int    mr2en           : 1;    // bit 15               Enable Matching Rule 2
16999 +               unsigned int    reserved2       : 4;    // bit 14:11
17000 +               unsigned int    mr2_action      : 5;    // bit 10:6             Matching Rule 2 action offset
17001 +               unsigned int    mr2hel          : 6;    // bit 5:0              match rule 2 hash entry size
17002 +#else
17003 +               unsigned int    mr2hel          : 6;    // bit 5:0              match rule 2 hash entry size
17004 +               unsigned int    mr2_action      : 5;    // bit 10:6             Matching Rule 2 action offset
17005 +               unsigned int    reserved2       : 4;    // bit 14:11
17006 +               unsigned int    mr2en           : 1;    // bit 15               Enable Matching Rule 2
17007 +               unsigned int    mr3hel          : 6;    // bit 21:16    match rule 3 hash entry size
17008 +               unsigned int    mr3_action      : 5;    // bit 26:22    Matching Rule 3 action offset
17009 +               unsigned int    reserved1       : 4;    // bit 30:27
17010 +               unsigned int    mr3en           : 1;    // bit 31               Enable Matching Rule 3
17011 +#endif
17012 +       } bits;
17013 +} GMAC_HASH_ENABLE_REG1_T;
17014 +
17015 +
17016 +/**********************************************************************
17017 + * GMAC Matching Rule Control Register 0
17018 + * GMAC0 offset 0x8078
17019 + * GMAC1 offset 0xC078
17020 + **********************************************************************/
17021 +typedef union
17022 +{
17023 +       unsigned int bits32;
17024 +       struct bit_8078
17025 +       {
17026 +#if (BIG_ENDIAN==1)
17027 +               unsigned int    l2                      : 1;    // bit 31               L2 matching enable
17028 +               unsigned int    l3                      : 1;    // bit 30               L3 matching enable
17029 +               unsigned int    l4                      : 1;    // bit 29               L4 matching enable
17030 +               unsigned int    l7                      : 1;    // bit 28               L7 matching enable
17031 +               unsigned int    port            : 1;    // bit 27               PORT ID matching enable
17032 +               unsigned int    priority        : 3;    // bit 26:24    priority if multi-rules matched
17033 +               unsigned int    da                      : 1;    // bit 23               MAC DA enable
17034 +               unsigned int    sa                      : 1;    // bit 22               MAC SA enable
17035 +               unsigned int    ether_type      : 1;    // bit 21               Ethernet type enable
17036 +               unsigned int    vlan            : 1;    // bit 20               VLAN ID enable
17037 +               unsigned int    pppoe           : 1;    // bit 19               PPPoE Session ID enable
17038 +               unsigned int    reserved1       : 3;    // bit 18:16
17039 +               unsigned int    ip_version      : 1;    // bit 15               0: IPV4, 1: IPV6
17040 +               unsigned int    ip_hdr_len      : 1;    // bit 14               IPV4 Header length
17041 +               unsigned int    flow_lable      : 1;    // bit 13               IPV6 Flow label
17042 +               unsigned int    tos_traffic     : 1;    // bit 12               IPV4 TOS or IPV6 Traffice Class
17043 +               unsigned int    reserved2       : 4;    // bit 11:8
17044 +               unsigned int    sprx            : 8;    // bit 7:0              Support Protocol Register 7:0
17045 +#else
17046 +               unsigned int    sprx            : 8;    // bit 7:0              Support Protocol Register 7:0
17047 +               unsigned int    reserved2       : 4;    // bit 11:8
17048 +               unsigned int    tos_traffic     : 1;    // bit 12               IPV4 TOS or IPV6 Traffice Class
17049 +               unsigned int    flow_lable      : 1;    // bit 13               IPV6 Flow label
17050 +               unsigned int    ip_hdr_len      : 1;    // bit 14               IPV4 Header length
17051 +               unsigned int    ip_version      : 1;    // bit 15               0: IPV4, 1: IPV6
17052 +               unsigned int    reserved1       : 3;    // bit 18:16
17053 +               unsigned int    pppoe           : 1;    // bit 19               PPPoE Session ID enable
17054 +               unsigned int    vlan            : 1;    // bit 20               VLAN ID enable
17055 +               unsigned int    ether_type      : 1;    // bit 21               Ethernet type enable
17056 +               unsigned int    sa                      : 1;    // bit 22               MAC SA enable
17057 +               unsigned int    da                      : 1;    // bit 23               MAC DA enable
17058 +               unsigned int    priority        : 3;    // bit 26:24    priority if multi-rules matched
17059 +               unsigned int    port            : 1;    // bit 27               PORT ID matching enable
17060 +               unsigned int    l7                      : 1;    // bit 28               L7 matching enable
17061 +               unsigned int    l4                      : 1;    // bit 29               L4 matching enable
17062 +               unsigned int    l3                      : 1;    // bit 30               L3 matching enable
17063 +               unsigned int    l2                      : 1;    // bit 31               L2 matching enable
17064 +#endif
17065 +       } bits;
17066 +} GMAC_MRxCR0_T;
17067 +
17068 +#define MR_L2_BIT                      BIT(31)
17069 +#define MR_L3_BIT                      BIT(30)
17070 +#define MR_L4_BIT                      BIT(29)
17071 +#define MR_L7_BIT                      BIT(28)
17072 +#define MR_PORT_BIT                    BIT(27)
17073 +#define MR_PRIORITY_BIT                BIT(26)
17074 +#define MR_DA_BIT                      BIT(23)
17075 +#define MR_SA_BIT                      BIT(22)
17076 +#define MR_ETHER_TYPE_BIT      BIT(21)
17077 +#define MR_VLAN_BIT                    BIT(20)
17078 +#define MR_PPPOE_BIT           BIT(19)
17079 +#define MR_IP_VER_BIT          BIT(15)
17080 +#define MR_IP_HDR_LEN_BIT      BIT(14)
17081 +#define MR_FLOW_LABLE_BIT      BIT(13)
17082 +#define MR_TOS_TRAFFIC_BIT     BIT(12)
17083 +#define MR_SPR_BIT(x)          BIT(x)
17084 +#define MR_SPR_BITS            0xff
17085 +
17086 +/**********************************************************************
17087 + * GMAC Matching Rule Control Register 1
17088 + * GMAC0 offset 0x807C
17089 + * GMAC1 offset 0xC07C
17090 + **********************************************************************/
17091 + typedef union
17092 +{
17093 +       unsigned int bits32;
17094 +       struct bit_807C
17095 +       {
17096 +#if (BIG_ENDIAN==1)
17097 +               unsigned int    sip                     : 1;    // bit 31               Srce IP
17098 +               unsigned int    sip_netmask     : 7;    // bit 30:24    Srce IP net mask, number of mask bits
17099 +               unsigned int    dip                     : 1;    // bit 23               Dest IP
17100 +               unsigned int    dip_netmask     : 7;    // bit 22:16    Dest IP net mask, number of mask bits
17101 +               unsigned int    l4_byte0_15     : 16;   // bit 15: 0
17102 +#else
17103 +               unsigned int    l4_byte0_15     : 16;   // bit 15: 0
17104 +               unsigned int    dip_netmask     : 7;    // bit 22:16    Dest IP net mask, number of mask bits
17105 +               unsigned int    dip                     : 1;    // bit 23               Dest IP
17106 +               unsigned int    sip_netmask     : 7;    // bit 30:24    Srce IP net mask, number of mask bits
17107 +               unsigned int    sip                     : 1;    // bit 31               Srce IP
17108 +#endif
17109 +       } bits;
17110 +} GMAC_MRxCR1_T;
17111 +
17112 +/**********************************************************************
17113 + * GMAC Matching Rule Control Register 2
17114 + * GMAC0 offset 0x8080
17115 + * GMAC1 offset 0xC080
17116 + **********************************************************************/
17117 + typedef union
17118 +{
17119 +       unsigned int bits32;
17120 +       struct bit_8080
17121 +       {
17122 +#if (BIG_ENDIAN==1)
17123 +               unsigned int    l4_byte16_24: 8;        // bit 31: 24
17124 +               unsigned int    l7_byte0_23     : 24;   // bit 23:0
17125 +#else
17126 +               unsigned int    l7_byte0_23     : 24;   // bit 23:0
17127 +               unsigned int    l4_byte16_24: 8;        // bit 31: 24
17128 +#endif
17129 +       } bits;
17130 +} GMAC_MRxCR2_T;
17131 +
17132 +
17133 +/**********************************************************************
17134 + * GMAC Support registers
17135 + * GMAC0 offset 0x80A8
17136 + * GMAC1 offset 0xC0A8
17137 + **********************************************************************/
17138 + typedef union
17139 +{
17140 +       unsigned int bits32;
17141 +       struct bit_80A8
17142 +       {
17143 +#if (BIG_ENDIAN==1)
17144 +               unsigned int    reserved: 21;   // bit 31:11
17145 +               unsigned int    swap    : 3;    // bit 10:8             Swap
17146 +               unsigned int    protocol: 8;    // bit 7:0              Supported protocol
17147 +#else
17148 +               unsigned int    protocol: 8;    // bit 7:0              Supported protocol
17149 +               unsigned int    swap    : 3;    // bit 10:8             Swap
17150 +               unsigned int    reserved: 21;   // bit 31:11
17151 +#endif
17152 +       } bits;
17153 +} GMAC_SPR_T;
17154 +
17155 +/**********************************************************************
17156 + * GMAC_AHB_WEIGHT registers
17157 + * GMAC0 offset 0x80C8
17158 + * GMAC1 offset 0xC0C8
17159 + **********************************************************************/
17160 + typedef union
17161 +{
17162 +       unsigned int bits32;
17163 +       struct bit_80C8
17164 +       {
17165 +#if (BIG_ENDIAN==1)
17166 +               unsigned int    reserved                : 7;    // 31:25
17167 +               unsigned int    tqDV_threshold  : 5;    // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
17168 +               unsigned int    pre_req                 : 5;    // 19:15 Rx Data Pre Request FIFO Threshold
17169 +               unsigned int    tx_weight               : 5;    // 14:10
17170 +               unsigned int    rx_weight               : 5;    // 9:5
17171 +               unsigned int    hash_weight             : 5;    // 4:0
17172 +#else
17173 +               unsigned int    hash_weight             : 5;    // 4:0
17174 +               unsigned int    rx_weight               : 5;    // 9:5
17175 +               unsigned int    tx_weight               : 5;    // 14:10
17176 +               unsigned int    pre_req                 : 5;    // 19:15 Rx Data Pre Request FIFO Threshold
17177 +               unsigned int    tqDV_threshold  : 5;    // 24:20 DMA TqCtrl to Start tqDV FIFO Threshold
17178 +               unsigned int    reserved                : 7;    // 31:25
17179 +#endif
17180 +       } bits;
17181 +} GMAC_AHB_WEIGHT_T;
17182 +/**********************************************************************
17183 + * the register structure of GMAC
17184 + **********************************************************************/
17185 +
17186 +/**********************************************************************
17187 + * GMAC RX FLTR
17188 + * GMAC0 Offset 0xA00C
17189 + * GMAC1 Offset 0xE00C
17190 + **********************************************************************/
17191 +typedef union
17192 +{
17193 +       unsigned int bits32;
17194 +       struct bit1_000c
17195 +       {
17196 +#if (BIG_ENDIAN==1)
17197 +               unsigned int                            : 27;
17198 +               unsigned int error                      :  1;   /* enable receive of all error frames */
17199 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
17200 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
17201 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
17202 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
17203 +#else
17204 +               unsigned int unicast            :  1;   /* enable receive of unicast frames that are sent to STA address */
17205 +               unsigned int multicast          :  1;   /* enable receive of multicast frames that pass multicast filter */
17206 +               unsigned int broadcast          :  1;   /* enable receive of broadcast frames */
17207 +               unsigned int promiscuous        :  1;   /* enable receive of all frames */
17208 +               unsigned int error                      :  1;   /* enable receive of all error frames */
17209 +               unsigned int                            : 27;
17210 +#endif
17211 +       } bits;
17212 +} GMAC_RX_FLTR_T;
17213 +
17214 +/**********************************************************************
17215 + * GMAC Configuration 0
17216 + * GMAC0 Offset 0xA018
17217 + * GMAC1 Offset 0xE018
17218 + **********************************************************************/
17219 +typedef union
17220 +{
17221 +       unsigned int bits32;
17222 +       struct bit1_0018
17223 +       {
17224 +#if (BIG_ENDIAN==1)
17225 +               unsigned int reserved           :  2;   // 31
17226 +               unsigned int port1_chk_classq :  1;     // 29
17227 +               unsigned int port0_chk_classq :  1;     // 28
17228 +               unsigned int port1_chk_toeq     :  1;   // 27
17229 +               unsigned int port0_chk_toeq     :  1;   // 26
17230 +               unsigned int port1_chk_hwq      :  1;   // 25
17231 +               unsigned int port0_chk_hwq      :  1;   // 24
17232 +               unsigned int rx_err_detect  :  1;       // 23
17233 +               unsigned int ipv6_exthdr_order: 1;      // 22
17234 +               unsigned int rxc_inv            :  1;   // 21
17235 +               unsigned int rgmm_edge          :  1;   // 20
17236 +        unsigned int rx_tag_remove  :  1;   /* 19: Remove Rx VLAN tag */
17237 +        unsigned int ipv6_rx_chksum :  1;   /* 18: IPv6 RX Checksum enable */
17238 +        unsigned int ipv4_rx_chksum :  1;   /* 17: IPv4 RX Checksum enable */
17239 +        unsigned int rgmii_en       :  1;   /* 16: RGMII in-band status enable */
17240 +               unsigned int tx_fc_en           :  1;   /* 15: TX flow control enable */
17241 +               unsigned int rx_fc_en           :  1;   /* 14: RX flow control enable */
17242 +               unsigned int sim_test           :  1;   /* 13: speed up timers in simulation */
17243 +               unsigned int dis_col            :  1;   /* 12: disable 16 collisions abort function */
17244 +               unsigned int dis_bkoff          :  1;   /* 11: disable back-off function */
17245 +               unsigned int max_len            :  3;   /* 8-10 maximum receive frame length allowed */
17246 +               unsigned int adj_ifg            :  4;   /* 4-7: adjust IFG from 96+/-56 */
17247 +        unsigned int flow_ctrl      :  1;   /* 3: flow control also trigged by Rx queues */
17248 +               unsigned int loop_back          :  1;   /* 2: transmit data loopback enable */
17249 +               unsigned int dis_rx                     :  1;   /* 1: disable receive */
17250 +               unsigned int dis_tx                     :  1;   /* 0: disable transmit */
17251 +#else
17252 +               unsigned int dis_tx                     :  1;   /* 0: disable transmit */
17253 +               unsigned int dis_rx                     :  1;   /* 1: disable receive */
17254 +               unsigned int loop_back          :  1;   /* 2: transmit data loopback enable */
17255 +        unsigned int flow_ctrl      :  1;   /* 3: flow control also trigged by Rx queues */
17256 +               unsigned int adj_ifg            :  4;   /* 4-7: adjust IFG from 96+/-56 */
17257 +               unsigned int max_len            :  3;   /* 8-10 maximum receive frame length allowed */
17258 +               unsigned int dis_bkoff          :  1;   /* 11: disable back-off function */
17259 +               unsigned int dis_col            :  1;   /* 12: disable 16 collisions abort function */
17260 +               unsigned int sim_test           :  1;   /* 13: speed up timers in simulation */
17261 +               unsigned int rx_fc_en           :  1;   /* 14: RX flow control enable */
17262 +               unsigned int tx_fc_en           :  1;   /* 15: TX flow control enable */
17263 +        unsigned int rgmii_en       :  1;   /* 16: RGMII in-band status enable */
17264 +        unsigned int ipv4_rx_chksum :  1;   /* 17: IPv4 RX Checksum enable */
17265 +        unsigned int ipv6_rx_chksum :  1;   /* 18: IPv6 RX Checksum enable */
17266 +        unsigned int rx_tag_remove  :  1;   /* 19: Remove Rx VLAN tag */
17267 +               unsigned int rgmm_edge          :  1;   // 20
17268 +               unsigned int rxc_inv            :  1;   // 21
17269 +               unsigned int ipv6_exthdr_order: 1;      // 22
17270 +               unsigned int rx_err_detect  :  1;       // 23
17271 +               unsigned int port0_chk_hwq      :  1;   // 24
17272 +               unsigned int port1_chk_hwq      :  1;   // 25
17273 +               unsigned int port0_chk_toeq     :  1;   // 26
17274 +               unsigned int port1_chk_toeq     :  1;   // 27
17275 +               unsigned int port0_chk_classq :  1;     // 28
17276 +               unsigned int port1_chk_classq :  1;     // 29
17277 +               unsigned int reserved           :  2;   // 31
17278 +#endif
17279 +       } bits;
17280 +} GMAC_CONFIG0_T;
17281 +
17282 +/**********************************************************************
17283 + * GMAC Configuration 1
17284 + * GMAC0 Offset 0xA01C
17285 + * GMAC1 Offset 0xE01C
17286 + **********************************************************************/
17287 +typedef union
17288 +{
17289 +       unsigned int bits32;
17290 +       struct bit1_001c
17291 +       {
17292 +#if (BIG_ENDIAN==1)
17293 +               unsigned int reserved           : 16;
17294 +               unsigned int rel_threshold      : 8;    /* flow control release threshold */
17295 +               unsigned int set_threshold      : 8;    /* flow control set threshold */
17296 +#else
17297 +               unsigned int set_threshold      : 8;    /* flow control set threshold */
17298 +               unsigned int rel_threshold      : 8;    /* flow control release threshold */
17299 +               unsigned int reserved           : 16;
17300 +#endif
17301 +       } bits;
17302 +} GMAC_CONFIG1_T;
17303 +
17304 +#define GMAC_FLOWCTRL_SET_MAX          32
17305 +#define GMAC_FLOWCTRL_SET_MIN          0
17306 +#define GMAC_FLOWCTRL_RELEASE_MAX      32
17307 +#define GMAC_FLOWCTRL_RELEASE_MIN      0
17308 +
17309 +/**********************************************************************
17310 + * GMAC Configuration 2
17311 + * GMAC0 Offset 0xA020
17312 + * GMAC1 Offset 0xE020
17313 + **********************************************************************/
17314 +typedef union
17315 +{
17316 +       unsigned int bits32;
17317 +       struct bit1_0020
17318 +       {
17319 +#if (BIG_ENDIAN==1)
17320 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
17321 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
17322 +#else
17323 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
17324 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
17325 +#endif
17326 +       } bits;
17327 +} GMAC_CONFIG2_T;
17328 +
17329 +/**********************************************************************
17330 + * GMAC Configuration 3
17331 + * GMAC0 Offset 0xA024
17332 + * GMAC1 Offset 0xE024
17333 + **********************************************************************/
17334 +typedef union
17335 +{
17336 +       unsigned int bits32;
17337 +       struct bit1_0024
17338 +       {
17339 +#if (BIG_ENDIAN==1)
17340 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
17341 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
17342 +#else
17343 +               unsigned int set_threshold      : 16;   /* flow control set threshold */
17344 +               unsigned int rel_threshold      : 16;   /* flow control release threshold */
17345 +#endif
17346 +       } bits;
17347 +} GMAC_CONFIG3_T;
17348 +
17349 +
17350 +/**********************************************************************
17351 + * GMAC STATUS
17352 + * GMAC0 Offset 0xA02C
17353 + * GMAC1 Offset 0xE02C
17354 + **********************************************************************/
17355 +typedef union
17356 +{
17357 +       unsigned int bits32;
17358 +       struct bit1_002c
17359 +       {
17360 +#if (BIG_ENDIAN==1)
17361 +               unsigned int                            : 25;
17362 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
17363 +               unsigned int reserved           :  1;
17364 +               unsigned int duplex                     :  1;   /* duplex mode */
17365 +               unsigned int speed                      :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
17366 +               unsigned int link                       :  1;   /* link status */
17367 +#else
17368 +               unsigned int link                       :  1;   /* link status */
17369 +               unsigned int speed                      :  2;   /* link speed(00->2.5M 01->25M 10->125M) */
17370 +               unsigned int duplex                     :  1;   /* duplex mode */
17371 +               unsigned int reserved           :  1;
17372 +               unsigned int mii_rmii           :  2;   /* PHY interface type */
17373 +               unsigned int                            : 25;
17374 +#endif
17375 +       } bits;
17376 +} GMAC_STATUS_T;
17377 +
17378 +#define GMAC_SPEED_10                  0
17379 +#define GMAC_SPEED_100                 1
17380 +#define GMAC_SPEED_1000                        2
17381 +
17382 +#define GMAC_PHY_MII                   0
17383 +#define GMAC_PHY_GMII                  1
17384 +#define GMAC_PHY_RGMII_100             2
17385 +#define GMAC_PHY_RGMII_1000            3
17386 +
17387 +/**********************************************************************
17388 + * Queue Header
17389 + *     (1) TOE Queue Header
17390 + *     (2) Non-TOE Queue Header
17391 + *     (3) Interrupt Queue Header
17392 + *
17393 + * memory Layout
17394 + *     TOE Queue Header
17395 + *      0x60003000 +---------------------------+ 0x0000
17396 + *                             |     TOE Queue 0 Header        |
17397 + *                             |         8 * 4 Bytes       |
17398 + *                             +---------------------------+ 0x0020
17399 + *                             |     TOE Queue 1 Header        |
17400 + *                             |         8 * 4 Bytes           |
17401 + *                             +---------------------------+ 0x0040
17402 + *                             |       ......                          |
17403 + *                             |                                               |
17404 + *                             +---------------------------+
17405 + *
17406 + *     Non TOE Queue Header
17407 + *      0x60002000 +---------------------------+ 0x0000
17408 + *                             |   Default Queue 0 Header  |
17409 + *                             |         2 * 4 Bytes           |
17410 + *                             +---------------------------+ 0x0008
17411 + *                             |   Default Queue 1 Header      |
17412 + *                             |         2 * 4 Bytes           |
17413 + *                             +---------------------------+ 0x0010
17414 + *                             |   Classification Queue 0      |
17415 + *                             |         2 * 4 Bytes           |
17416 + *                             +---------------------------+
17417 + *                             |   Classification Queue 1      |
17418 + *                             |         2 * 4 Bytes           |
17419 + *                             +---------------------------+ (n * 8 + 0x10)
17420 + *                             |               ...                             |
17421 + *                             |         2 * 4 Bytes           |
17422 + *                             +---------------------------+ (13 * 8 + 0x10)
17423 + *                             |   Classification Queue 13     |
17424 + *                             |         2 * 4 Bytes           |
17425 + *                             +---------------------------+ 0x80
17426 + *                             |      Interrupt Queue 0        |
17427 + *                             |         2 * 4 Bytes           |
17428 + *                             +---------------------------+
17429 + *                             |      Interrupt Queue 1        |
17430 + *                             |         2 * 4 Bytes           |
17431 + *                             +---------------------------+
17432 + *                             |      Interrupt Queue 2        |
17433 + *                             |         2 * 4 Bytes           |
17434 + *                             +---------------------------+
17435 + *                             |      Interrupt Queue 3        |
17436 + *                             |         2 * 4 Bytes           |
17437 + *                             +---------------------------+
17438 + *
17439 + **********************************************************************/
17440 +#define TOE_QUEUE_HDR_ADDR(n)          (TOE_TOE_QUE_HDR_BASE + n * 32)
17441 +#define TOE_Q_HDR_AREA_END                     (TOE_QUEUE_HDR_ADDR(TOE_TOE_QUEUE_MAX+1))
17442 +#define TOE_DEFAULT_Q0_HDR_BASE                (TOE_NONTOE_QUE_HDR_BASE + 0x00)
17443 +#define TOE_DEFAULT_Q1_HDR_BASE                (TOE_NONTOE_QUE_HDR_BASE + 0x08)
17444 +#define TOE_CLASS_Q_HDR_BASE           (TOE_NONTOE_QUE_HDR_BASE + 0x10)
17445 +#define TOE_INTR_Q_HDR_BASE                    (TOE_NONTOE_QUE_HDR_BASE + 0x80)
17446 +#define INTERRUPT_QUEUE_HDR_ADDR(n)    (TOE_INTR_Q_HDR_BASE + n * 8)
17447 +#define NONTOE_Q_HDR_AREA_END          (INTERRUPT_QUEUE_HDR_ADDR(TOE_INTR_QUEUE_MAX+1))
17448 +/**********************************************************************
17449 + * TOE Queue Header Word 0
17450 + **********************************************************************/
17451 +typedef union
17452 +{
17453 +       unsigned int bits32;
17454 +       unsigned int base_size;
17455 +} TOE_QHDR0_T;
17456 +
17457 +#define TOE_QHDR0_BASE_MASK    (~0x0f)
17458 +
17459 +/**********************************************************************
17460 + * TOE Queue Header Word 1
17461 + **********************************************************************/
17462 +typedef union
17463 +{
17464 +       unsigned int bits32;
17465 +       struct bit_qhdr1
17466 +       {
17467 +#if (BIG_ENDIAN==1)
17468 +
17469 +               unsigned int wptr                       : 16;   // bit 31:16
17470 +               unsigned int rptr                       : 16;   // bit 15:0
17471 +#else
17472 +               unsigned int rptr                       : 16;   // bit 15:0
17473 +               unsigned int wptr                       : 16;   // bit 31:16
17474 +#endif
17475 +       } bits;
17476 +} TOE_QHDR1_T;
17477 +
17478 +/**********************************************************************
17479 + * TOE Queue Header Word 2
17480 + **********************************************************************/
17481 +typedef union
17482 +{
17483 +       unsigned int bits32;
17484 +       struct bit_qhdr2
17485 +       {
17486 +#if (BIG_ENDIAN==1)
17487 +
17488 +               unsigned int usd                        : 1;    // bit 31               0: if no data assembled yet
17489 +               unsigned int ctl                        : 1;    // bit 30               1: have control flag bits (except ack)
17490 +               unsigned int osq                        : 1;    // bit 29               1: out of sequence
17491 +               unsigned int sat                        : 1;    // bit 28               1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
17492 +               unsigned int ip_opt                     : 1;    // bit 27               1: have IPV4 option or IPV6 Extension header
17493 +               unsigned int tcp_opt            : 1;    // bit 26               1: Have TCP option
17494 +               unsigned int abn                        : 1;    // bit 25               1: Abnormal case Found
17495 +               unsigned int dack                       : 1;    // bit 24               1: Duplicated ACK
17496 +               unsigned int reserved           : 7;    // bit 23:17
17497 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
17498 +#else
17499 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
17500 +               unsigned int reserved           : 7;    // bit 23:17
17501 +               unsigned int dack                       : 1;    // bit 24               1: Duplicated ACK
17502 +               unsigned int abn                        : 1;    // bit 25               1: Abnormal case Found
17503 +               unsigned int tcp_opt            : 1;    // bit 26               1: Have TCP option
17504 +               unsigned int ip_opt                     : 1;    // bit 27               1: have IPV4 option or IPV6 Extension header
17505 +               unsigned int sat                        : 1;    // bit 28               1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
17506 +               unsigned int osq                        : 1;    // bit 29               1: out of sequence
17507 +               unsigned int ctl                        : 1;    // bit 30               1: have control flag bits (except ack)
17508 +               unsigned int usd                        : 1;    // bit 31               0: if no data assembled yet
17509 +#endif
17510 +       } bits;
17511 +} TOE_QHDR2_T;
17512 +
17513 +/**********************************************************************
17514 + * TOE Queue Header Word 3
17515 + **********************************************************************/
17516 +typedef union
17517 +{
17518 +       unsigned int bits32;
17519 +       unsigned int seq_num;
17520 +} TOE_QHDR3_T;
17521 +
17522 +/**********************************************************************
17523 + * TOE Queue Header Word 4
17524 + **********************************************************************/
17525 +typedef union
17526 +{
17527 +       unsigned int bits32;
17528 +       unsigned int ack_num;
17529 +} TOE_QHDR4_T;
17530 +
17531 +/**********************************************************************
17532 + * TOE Queue Header Word 5
17533 + **********************************************************************/
17534 +typedef union
17535 +{
17536 +       unsigned int bits32;
17537 +       struct bit_qhdr5
17538 +       {
17539 +#if (BIG_ENDIAN==1)
17540 +
17541 +               unsigned int SeqCnt             : 16;   // bit 31:16
17542 +               unsigned int AckCnt             : 16;   // bit 15:0
17543 +#else
17544 +               unsigned int AckCnt             : 16;   // bit 15:0
17545 +               unsigned int SeqCnt             : 16;   // bit 31:16
17546 +#endif
17547 +       } bits;
17548 +} TOE_QHDR5_T;
17549 +
17550 +/**********************************************************************
17551 + * TOE Queue Header Word 6
17552 + **********************************************************************/
17553 +typedef union
17554 +{
17555 +       unsigned int bits32;
17556 +       struct bit_qhdr6
17557 +       {
17558 +#if (BIG_ENDIAN==1)
17559 +
17560 +               unsigned int MaxPktSize : 14;   // bit 31:18
17561 +               unsigned int iq_num             : 2;    // bit 17:16
17562 +               unsigned int WinSize    : 16;   // bit 15:0
17563 +#else
17564 +               unsigned int WinSize    : 16;   // bit 15:0
17565 +               unsigned int iq_num             : 2;    // bit 17:16
17566 +               unsigned int MaxPktSize : 14;   // bit 31:18
17567 +#endif
17568 +       } bits;
17569 +} TOE_QHDR6_T;
17570 +
17571 +/**********************************************************************
17572 + * TOE Queue Header Word 7
17573 + **********************************************************************/
17574 +typedef union
17575 +{
17576 +       unsigned int bits32;
17577 +       struct bit_qhdr7
17578 +       {
17579 +#if (BIG_ENDIAN==1)
17580 +
17581 +               unsigned int SeqThreshold       : 16;   // bit 31:16
17582 +               unsigned int AckThreshold       : 16;   // bit 15:0
17583 +#else
17584 +               unsigned int AckThreshold       : 16;   // bit 15:0
17585 +               unsigned int SeqThreshold       : 16;   // bit 31:16
17586 +#endif
17587 +       } bits;
17588 +} TOE_QHDR7_T;
17589 +
17590 +/**********************************************************************
17591 + * TOE Queue Header
17592 + **********************************************************************/
17593 +typedef struct
17594 +{
17595 +       TOE_QHDR0_T             word0;
17596 +       TOE_QHDR1_T             word1;
17597 +       TOE_QHDR2_T             word2;
17598 +       TOE_QHDR3_T             word3;
17599 +       TOE_QHDR4_T             word4;
17600 +       TOE_QHDR5_T             word5;
17601 +       TOE_QHDR6_T             word6;
17602 +       TOE_QHDR7_T             word7;
17603 +} TOE_QHDR_T;
17604 +
17605 +/**********************************************************************
17606 + * NONTOE Queue Header Word 0
17607 + **********************************************************************/
17608 +typedef union
17609 +{
17610 +       unsigned int bits32;
17611 +       unsigned int base_size;
17612 +} NONTOE_QHDR0_T;
17613 +
17614 +#define NONTOE_QHDR0_BASE_MASK         (~0x0f)
17615 +
17616 +/**********************************************************************
17617 + * NONTOE Queue Header Word 1
17618 + **********************************************************************/
17619 +typedef union
17620 +{
17621 +       unsigned int bits32;
17622 +       struct bit_nonqhdr1
17623 +       {
17624 +#if (BIG_ENDIAN==1)
17625 +
17626 +               unsigned int wptr                       : 16;   // bit 31:16
17627 +               unsigned int rptr                       : 16;   // bit 15:0
17628 +#else
17629 +               unsigned int rptr                       : 16;   // bit 15:0
17630 +               unsigned int wptr                       : 16;   // bit 31:16
17631 +#endif
17632 +       } bits;
17633 +} NONTOE_QHDR1_T;
17634 +
17635 +/**********************************************************************
17636 + * Non-TOE Queue Header
17637 + **********************************************************************/
17638 +typedef struct
17639 +{
17640 +       NONTOE_QHDR0_T          word0;
17641 +       NONTOE_QHDR1_T          word1;
17642 +} NONTOE_QHDR_T;
17643 +
17644 +/**********************************************************************
17645 + * Interrupt Queue Header Word 0
17646 + **********************************************************************/
17647 +typedef union
17648 +{
17649 +       unsigned int bits32;
17650 +       struct bit_intrqhdr0
17651 +       {
17652 +#if (BIG_ENDIAN==1)
17653 +
17654 +               unsigned int wptr               : 16;   // bit 31:16    Write Pointer where hw stopped
17655 +               unsigned int win_size   : 16;   // bit 15:0     Descriptor Ring Size
17656 +#else
17657 +               unsigned int win_size   : 16;   // bit 15:0     Descriptor Ring Size
17658 +               unsigned int wptr               : 16;   // bit 31:16    Write Pointer where hw stopped
17659 +#endif
17660 +       } bits;
17661 +} INTR_QHDR0_T;
17662 +
17663 +/**********************************************************************
17664 + * Interrupt Queue Header Word 1
17665 + **********************************************************************/
17666 +typedef union
17667 +{
17668 +       unsigned int bits32;
17669 +       struct bit_intrqhdr1
17670 +       {
17671 +#if (BIG_ENDIAN==1)
17672 +
17673 +               unsigned int ctl                        : 1;    // bit 31               1: have control flag bits (except ack)
17674 +               unsigned int osq                        : 1;    // bit 30               1: out of sequence
17675 +               unsigned int sat                        : 1;    // bit 29               1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
17676 +               unsigned int ip_opt                     : 1;    // bit 28               1: have IPV4 option or IPV6 Extension header
17677 +               unsigned int tcp_opt            : 1;    // bit 27               1: Have TCP option
17678 +               unsigned int abn                        : 1;    // bit 26               1: Abnormal case Found
17679 +               unsigned int dack                       : 1;    // bit 25               1: Duplicated ACK
17680 +               unsigned int tcp_qid            : 8;    // bit 24:17    TCP Queue ID
17681 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
17682 +#else
17683 +               unsigned int TotalPktSize       : 17;   // bit 16: 0    Total packet size
17684 +               unsigned int tcp_qid            : 8;    // bit 24:17    TCP Queue ID
17685 +               unsigned int dack                       : 1;    // bit 25               1: Duplicated ACK
17686 +               unsigned int abn                        : 1;    // bit 26               1: Abnormal case Found
17687 +               unsigned int tcp_opt            : 1;    // bit 27               1: Have TCP option
17688 +               unsigned int ip_opt                     : 1;    // bit 28               1: have IPV4 option or IPV6 Extension header
17689 +               unsigned int sat                        : 1;    // bit 29               1: SeqCnt > SeqThreshold, or AckCnt > AckThreshold
17690 +               unsigned int osq                        : 1;    // bit 30               1: out of sequence
17691 +               unsigned int ctl                        : 1;    // bit 31               1: have control flag bits (except ack)
17692 +#endif
17693 +       } bits;
17694 +} INTR_QHDR1_T;
17695 +
17696 +/**********************************************************************
17697 + * Interrupt Queue Header Word 2
17698 + **********************************************************************/
17699 +typedef union
17700 +{
17701 +       unsigned int bits32;
17702 +       unsigned int seq_num;
17703 +} INTR_QHDR2_T;
17704 +
17705 +/**********************************************************************
17706 + * Interrupt Queue Header Word 3
17707 + **********************************************************************/
17708 +typedef union
17709 +{
17710 +       unsigned int bits32;
17711 +       unsigned int ack_num;
17712 +} INTR_QHDR3_T;
17713 +
17714 +/**********************************************************************
17715 + * Interrupt Queue Header Word 4
17716 + **********************************************************************/
17717 +typedef union
17718 +{
17719 +       unsigned int bits32;
17720 +       struct bit_intrqhdr4
17721 +       {
17722 +#if (BIG_ENDIAN==1)
17723 +
17724 +               unsigned int SeqCnt             : 16;   // bit 31:16    Seq# change since last seq# intr.
17725 +               unsigned int AckCnt             : 16;   // bit 15:0     Ack# change since last ack# intr.
17726 +#else
17727 +               unsigned int AckCnt             : 16;   // bit 15:0             Ack# change since last ack# intr.
17728 +               unsigned int SeqCnt             : 16;   // bit 31:16    Seq# change since last seq# intr.
17729 +#endif
17730 +       } bits;
17731 +} INTR_QHDR4_T;
17732 +
17733 +/**********************************************************************
17734 + * Interrupt Queue Header
17735 + **********************************************************************/
17736 +typedef struct
17737 +{
17738 +       INTR_QHDR0_T            word0;
17739 +       INTR_QHDR1_T            word1;
17740 +       INTR_QHDR2_T            word2;
17741 +       INTR_QHDR3_T            word3;
17742 +       INTR_QHDR4_T            word4;
17743 +       unsigned int            word5;
17744 +       unsigned int            word6;
17745 +       unsigned int            word7;
17746 +} INTR_QHDR_T;
17747 +
17748 +/**********************************************************************
17749 + * GMAC Conf
17750 + **********************************************************************/
17751 +typedef struct gmac_conf {
17752 +       struct net_device *dev;
17753 +       int portmap;
17754 +       int vid;
17755 +       int flag;     /* 1: active  0: non-active */
17756 +} sys_gmac_conf;
17757 +
17758 +/**********************************************************************
17759 + * GMAC private data
17760 + **********************************************************************/
17761 +typedef struct {
17762 +       unsigned int            rwptr_reg;
17763 +       unsigned int            desc_base;
17764 +       unsigned int            total_desc_num;
17765 +       unsigned short          finished_idx;
17766 +       GMAC_TXDESC_T           *curr_tx_desc;
17767 +       GMAC_TXDESC_T           *curr_finished_desc;
17768 +       struct sk_buff          *tx_skb[TX_DESC_NUM];
17769 +       unsigned long           total_sent;
17770 +       unsigned long           total_finished;
17771 +       unsigned long           intr_cnt;
17772 +} GMAC_SWTXQ_T;
17773 +
17774 +typedef struct {
17775 +       unsigned int            desc_base;
17776 +       unsigned long           eof_cnt;
17777 +} GMAC_HWTXQ_T;
17778 +
17779 +typedef struct gmac_private{
17780 +       struct net_device       *dev;
17781 +       unsigned int            existed;
17782 +       unsigned int            port_id;        // 0 or 1
17783 +       unsigned int            base_addr;
17784 +       unsigned int            dma_base_addr;
17785 +       unsigned char           *mac_addr1;
17786 +       unsigned char           *mac_addr2;
17787 +       unsigned int            swtxq_desc_base;
17788 +       unsigned int            hwtxq_desc_base;
17789 +       GMAC_SWTXQ_T            swtxq[TOE_SW_TXQ_NUM];
17790 +       GMAC_HWTXQ_T            hwtxq[TOE_HW_TXQ_NUM];
17791 +       NONTOE_QHDR_T           *default_qhdr;
17792 +       unsigned int            default_desc_base;
17793 +       unsigned int            default_desc_num;
17794 +       unsigned int            rx_curr_desc;
17795 +       DMA_RWPTR_T                     rx_rwptr;
17796 +       struct sk_buff          *curr_rx_skb;
17797 +       dma_addr_t                      default_desc_base_dma;
17798 +       dma_addr_t                      swtxq_desc_base_dma;
17799 +       dma_addr_t                      hwtxq_desc_base_dma;
17800 +       unsigned int            irq;
17801 +       unsigned int            flow_control_enable     ;
17802 +       unsigned int            pre_phy_status;
17803 +       unsigned int            full_duplex_cfg;
17804 +       unsigned int            speed_cfg;
17805 +       unsigned int            auto_nego_cfg;
17806 +       unsigned int            full_duplex_status;
17807 +       unsigned int            speed_status;
17808 +       unsigned int            phy_mode;       /* 0->MII 1->GMII 2->RGMII(10/100) 3->RGMII(1000) */
17809 +       unsigned int            phy_addr;
17810 +       unsigned int            intr0_enabled;  // 1: enabled
17811 +       unsigned int            intr1_enabled;  // 1: enabled
17812 +       unsigned int            intr2_enabled;  // 1: enabled
17813 +       unsigned int            intr3_enabled;  // 1: enabled
17814 +       unsigned int            intr4_enabled;  // 1: enabled
17815 +//     unsigned int            intr4_enabled_1;        // 1: enabled
17816 +       unsigned int            intr0_selected; // 1: selected
17817 +       unsigned int            intr1_selected; // 1: selected
17818 +       unsigned int            intr2_selected; // 1: selected
17819 +       unsigned int            intr3_selected; // 1: selected
17820 +       unsigned int            intr4_selected; // 1: selected
17821 +       // void                                 (*gmac_rcv_handler)(struct sk_buff *, int);
17822 +       struct net_device_stats ifStatics;
17823 +       unsigned long           txDerr_cnt[GMAC_NUM];
17824 +       unsigned long           txPerr_cnt[GMAC_NUM];
17825 +       unsigned long           RxDerr_cnt[GMAC_NUM];
17826 +       unsigned long           RxPerr_cnt[GMAC_NUM];
17827 +       unsigned int            isr_rx_cnt;
17828 +       unsigned int            isr_tx_cnt;
17829 +       unsigned long           rx_discard;
17830 +       unsigned long           rx_error;
17831 +       unsigned long           rx_mcast;
17832 +       unsigned long           rx_bcast;
17833 +       unsigned long           rx_status_cnt[8];
17834 +       unsigned long           rx_chksum_cnt[8];
17835 +       unsigned long           rx_sta1_ucast;  // for STA 1 MAC Address
17836 +       unsigned long           rx_sta2_ucast;  // for STA 2 MAC Address
17837 +       unsigned long           mib_full_cnt;
17838 +       unsigned long           rx_pause_on_cnt;
17839 +       unsigned long           tx_pause_on_cnt;
17840 +       unsigned long           rx_pause_off_cnt;
17841 +       unsigned long           tx_pause_off_cnt;
17842 +       unsigned long           rx_overrun_cnt;
17843 +       unsigned long           status_changed_cnt;
17844 +       unsigned long           default_q_cnt;
17845 +       unsigned long           hw_fq_empty_cnt;
17846 +       unsigned long           sw_fq_empty_cnt;
17847 +       unsigned long           default_q_intr_cnt;
17848 +       pid_t               thr_pid;
17849 +       wait_queue_head_t   thr_wait;
17850 +       struct completion   thr_exited;
17851 +    spinlock_t          lock;
17852 +    int                 time_to_die;
17853 +    int                                        operation;
17854 +#ifdef SL351x_GMAC_WORKAROUND
17855 +    unsigned long              short_frames_cnt;
17856 +#endif
17857 +}GMAC_INFO_T ;
17858 +
17859 +typedef struct toe_private {
17860 +       unsigned int    swfq_desc_base;
17861 +       unsigned int    hwfq_desc_base;
17862 +       unsigned int    hwfq_buf_base;
17863 +//     unsigned int    toe_desc_base[TOE_TOE_QUEUE_NUM];
17864 +//     unsigned int    toe_desc_num;
17865 +//     unsigned int    class_desc_base;
17866 +//     unsigned int    class_desc_num;
17867 +//     unsigned int    intr_desc_base;
17868 +//     unsigned int    intr_desc_num;
17869 +//     unsigned int    intr_buf_base;
17870 +       DMA_RWPTR_T             fq_rx_rwptr;
17871 +       GMAC_INFO_T             gmac[GMAC_NUM];
17872 +       dma_addr_t              sw_freeq_desc_base_dma;
17873 +       dma_addr_t              hw_freeq_desc_base_dma;
17874 +       dma_addr_t              hwfq_buf_base_dma;
17875 +       dma_addr_t              hwfq_buf_end_dma;
17876 +//     dma_addr_t              toe_desc_base_dma[TOE_TOE_QUEUE_NUM];
17877 +//     dma_addr_t              class_desc_base_dma;
17878 +//     dma_addr_t              intr_desc_base_dma;
17879 +//     dma_addr_t              intr_buf_base_dma;
17880 +//     unsigned long   toe_iq_intr_full_cnt[TOE_INTR_QUEUE_NUM];
17881 +//     unsigned long   toe_iq_intr_cnt[TOE_INTR_QUEUE_NUM];
17882 +//     unsigned long   toe_q_intr_full_cnt[TOE_TOE_QUEUE_NUM];
17883 +//     unsigned long   class_q_intr_full_cnt[TOE_CLASS_QUEUE_NUM];
17884 +//     unsigned long   class_q_intr_cnt[TOE_CLASS_QUEUE_NUM];
17885 +} TOE_INFO_T;
17886 +
17887 +extern TOE_INFO_T toe_private_data;
17888 +
17889 +#define GMAC_PORT0     0
17890 +#define GMAC_PORT1     1
17891 +/**********************************************************************
17892 + * PHY Definition
17893 + **********************************************************************/
17894 +#define HPHY_ADDR                      0x01
17895 +#define GPHY_ADDR                      0x02
17896 +
17897 +enum phy_state
17898 +{
17899 +    LINK_DOWN   = 0,
17900 +    LINK_UP     = 1
17901 +};
17902 +
17903 +/* transmit timeout value */
17904 +
17905 +#endif //_GMAC_SL351x_H
17906 Index: linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_hash_cfg.h
17907 ===================================================================
17908 --- /dev/null
17909 +++ linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_hash_cfg.h
17910 @@ -0,0 +1,365 @@
17911 +/*-----------------------------------------------------------------------------------
17912 +*      sl351x_hash_cfg.h
17913 +*
17914 +*      Description:
17915 +*      
17916 +*      History:
17917 +*
17918 +*      9/14/2005       Gary Chen       Create
17919 +*
17920 +*-------------------------------------------------------------------------------------*/
17921 +#ifndef _SL351x_HASH_CFG_H_
17922 +#define _SL351x_HASH_CFG_H_    1
17923 +
17924 +// #define NAT_DEBUG_MSG       1
17925 +// #define DEBUG_NAT_MIXED_HW_SW_TX    1
17926 +#ifdef DEBUG_NAT_MIXED_HW_SW_TX
17927 +       // #define NAT_DEBUG_LAN_HASH_TIMEOUT   1
17928 +       // #define NAT_DEBUG_WAN_HASH_TIMEOUT   1
17929 +#endif
17930 +
17931 +#define IPIV(a,b,c,d)          ((a<<24)+(b<<16)+(c<<8)+d)
17932 +#define        IPIV1(a)                        ((a>>24)&0xff)
17933 +#define        IPIV2(a)                        ((a>>16)&0xff)
17934 +#define IPIV3(a)                       ((a>>8)&0xff)
17935 +#define IPIV4(a)                       ((a)&0xff)
17936 +
17937 +#define HASH_MAX_BYTES                 64      // 128
17938 +#define HASH_ACTION_DWORDS             9
17939 +#define HASH_MAX_DWORDS                        (HASH_MAX_BYTES / sizeof(u32))
17940 +#define HASH_MAX_KEY_DWORD             (HASH_MAX_DWORDS - HASH_ACTION_DWORDS)
17941 +#define HASH_INIT_KEY                  0x534C4F52
17942 +#define HASH_BITS                              12      // 12 : Normal, 7: Simulation
17943 +#define HASH_TOTAL_ENTRIES             (1 << HASH_BITS)
17944 +#define HASH_MAX_ENTRIES               (1 << 12)
17945 +#define HASH_TOE_ENTRIES               (HASH_TOTAL_ENTRIES >> 5)
17946 +#define HASH_BITS_MASK                 ((1 << HASH_BITS) - 1)
17947 +
17948 +#define hash_lock(lock)                        // spin_lock_bh(lock)
17949 +#define hash_unlock(lock)              // spin_unlock_bh(lock)
17950 +
17951 +/*----------------------------------------------------------------------
17952 + *  special macro
17953 + ----------------------------------------------------------------------*/
17954 +#define HASH_PUSH_WORD(cp, data)       {*cp++ = (((u16)(data))     ) & 0xff;   \
17955 +                                                                       *cp++ = (((u16)(data)) >> 8) & 0xff;} 
17956 +#define HASH_PUSH_DWORD(cp, data)      {*cp++ = (u8)(((u32)(data))      ) & 0xff;      \
17957 +                                                                       *cp++ = (u8)(((u32)(data)) >>  8) & 0xff;       \
17958 +                                                                       *cp++ = (u8)(((u32)(data)) >> 16) & 0xff;       \
17959 +                                                                       *cp++ = (u8)(((u32)(data)) >> 24) & 0xff;}
17960 +#define HASH_PUSH_BYTE(cp, data)       {*cp++ = ((u8)(data)) & 0xff;}
17961 +
17962 +/*----------------------------------------------------------------------
17963 + *  key
17964 + ----------------------------------------------------------------------*/
17965 +typedef struct {
17966 +       u8              port;
17967 +       u16             Ethertype;
17968 +       u8              da[6];
17969 +       u8              sa[6];
17970 +       u16             pppoe_sid;      
17971 +       u16             vlan_id;        
17972 +       u8              ipv4_hdrlen;    
17973 +       u8              ip_tos; 
17974 +       u8              ip_protocol;    
17975 +       u32             ipv6_flow_label;
17976 +       u8              sip[16];
17977 +       u8              dip[16];
17978 +       //__u32                 sip[4];
17979 +       //__u32                 dip[4];
17980 +       u8              l4_bytes[24];
17981 +       u8              l7_bytes[24];
17982 +       u8              ipv6;   // 1: IPv6, 0: IPV4
17983 +} ENTRY_KEY_T;
17984 +
17985 +/*----------------------------------------------------------------------
17986 + *  key for NAT
17987 + *     Note: packed
17988 + ----------------------------------------------------------------------*/
17989 +typedef struct {
17990 +       u16             Ethertype;              // not used
17991 +       u8              port_id;
17992 +       u8              rule_id;
17993 +       u8              ip_protocol;
17994 +       u8              reserved1;              // ip_tos, not used
17995 +       u16             reserved2;              // not used
17996 +       u32             sip;
17997 +       u32             dip;
17998 +       u16             sport;
17999 +       u16             dport;
18000 +} NAT_KEY_T;
18001 +
18002 +#define NAT_KEY_DWORD_SIZE     (sizeof(NAT_KEY_T)/sizeof(u32))
18003 +#define NAT_KEY_SIZE           (sizeof(NAT_KEY_T))
18004 +
18005 +/*----------------------------------------------------------------------
18006 + *  key for NAT
18007 + *     Note: packed
18008 + ----------------------------------------------------------------------*/
18009 +typedef struct {
18010 +       u16             Ethertype;              // not used
18011 +       u8              port_id;
18012 +       u8              rule_id;
18013 +       u8              ip_protocol;
18014 +       u8              reserved1;              // ip_tos, not used
18015 +       u16             reserved2;              // not used
18016 +       u32             sip;
18017 +       u32             dip;
18018 +       u16             reserved3;
18019 +       u16             protocol;
18020 +       u16             reserved4;
18021 +       u16             call_id;
18022 +} GRE_KEY_T;
18023 +
18024 +#define GRE_KEY_DWORD_SIZE     (sizeof(GRE_KEY_T)/sizeof(u32))
18025 +#define GRE_KEY_SIZE           (sizeof(GRE_KEY_T))
18026 +/*----------------------------------------------------------------------
18027 + *  key present or not
18028 + ----------------------------------------------------------------------*/
18029 +typedef struct {
18030 +       u32             port                    : 1;
18031 +       u32             Ethertype               : 1;
18032 +       u32             da                              : 1;
18033 +       u32             sa                              : 1;
18034 +       u32             pppoe_sid               : 1;    
18035 +       u32             vlan_id                 : 1;    
18036 +       u32             ipv4_hdrlen             : 1;    
18037 +       u32             ip_tos                  : 1;
18038 +       u32             ip_protocol             : 1;    
18039 +       u32             ipv6_flow_label : 1;
18040 +       u32             sip                             : 1;
18041 +       u32             dip                             : 1;
18042 +       u32             l4_bytes_0_3    : 1;
18043 +       u32             l4_bytes_4_7    : 1;
18044 +       u32             l4_bytes_8_11   : 1;
18045 +       u32             l4_bytes_12_15  : 1;
18046 +       u32             l4_bytes_16_19  : 1;
18047 +       u32             l4_bytes_20_23  : 1;
18048 +       u32             l7_bytes_0_3    : 1;
18049 +       u32             l7_bytes_4_7    : 1;
18050 +       u32             l7_bytes_8_11   : 1;
18051 +       u32             l7_bytes_12_15  : 1;
18052 +       u32             l7_bytes_16_19  : 1;
18053 +       u32             l7_bytes_20_23  : 1;
18054 +       u32             reserved                : 8;
18055 +} KEY_FIELD_T;
18056 +
18057 +/*----------------------------------------------------------------------
18058 + *  action
18059 + ----------------------------------------------------------------------*/
18060 +typedef struct {
18061 +       u32             reserved0       : 5;    // bit 0:4
18062 +       u32             pppoe           : 2;    // bit 5:6
18063 +       u32             vlan            : 2;    // bit 7:8
18064 +       u32             sa                      : 1;    // bit 9
18065 +       u32             da                      : 1;    // bit 10
18066 +       u32             Dport           : 1;    // bit 11
18067 +       u32             Sport           : 1;    // bit 12
18068 +       u32             Dip                     : 1;    // bit 13
18069 +       u32             Sip                     : 1;    // bit 14
18070 +       u32             sw_id           : 1;    // bit 15
18071 +       u32             frag            : 1;    // bit 16
18072 +       u32             option          : 1;    // bit 17
18073 +       u32             ttl_0           : 1;    // bit 18
18074 +       u32             ttl_1           : 1;    // bit 19
18075 +       u32             mtu                     : 1;    // bit 20
18076 +       u32             exception       : 1;    // bit 21
18077 +       u32             srce_qid        : 1;    // bit 22
18078 +       u32             discard         : 1;    // bit 23
18079 +       u32             dest_qid        : 8;    // bit 24:31
18080 +} ENTRY_ACTION_T;
18081 +
18082 +#define ACTION_DISCARD_BIT             BIT(23)
18083 +#define ACTION_SRCE_QID_BIT            BIT(22)
18084 +#define ACTION_EXCEPTION_BIT   BIT(21)
18085 +#define ACTION_MTU_BIT                 BIT(20)
18086 +#define ACTION_TTL_1_BIT               BIT(19)
18087 +#define ACTION_TTL_0_BIT               BIT(18)
18088 +#define ACTION_IP_OPTION               BIT(17)
18089 +#define ACTION_FRAG_BIT                        BIT(16)
18090 +#define ACTION_SWID_BIT                        BIT(15)
18091 +#define ACTION_SIP_BIT                 BIT(14)
18092 +#define ACTION_DIP_BIT                 BIT(13)
18093 +#define ACTION_SPORT_BIT               BIT(12)
18094 +#define ACTION_DPORT_BIT               BIT(11)
18095 +#define ACTION_DA_BIT                  BIT(10)
18096 +#define ACTION_SA_BIT                  BIT(9)
18097 +#define ACTION_VLAN_DEL_BIT            BIT(8)
18098 +#define ACTION_VLAN_INS_BIT            BIT(7)
18099 +#define ACTION_PPPOE_DEL_BIT   BIT(6)
18100 +#define ACTION_PPPOE_INS_BIT   BIT(5)
18101 +#define ACTION_L4_THIRD_BIT            BIT(4)
18102 +#define ACTION_L4_FOURTH_BIT   BIT(3)
18103 +
18104 +#define NAT_ACTION_BITS                        (ACTION_SRCE_QID_BIT  | ACTION_EXCEPTION_BIT |  \
18105 +                                                               ACTION_TTL_1_BIT | ACTION_TTL_0_BIT |                   \
18106 +                                                               ACTION_IP_OPTION | ACTION_FRAG_BIT |                    \
18107 +                                                               ACTION_DA_BIT | ACTION_SA_BIT)
18108 +#define NAT_LAN2WAN_ACTIONS            (NAT_ACTION_BITS | ACTION_SIP_BIT | ACTION_SPORT_BIT)
18109 +#define NAT_WAN2LAN_ACTIONS            (NAT_ACTION_BITS | ACTION_DIP_BIT | ACTION_DPORT_BIT)
18110 +#define NAT_PPPOE_LAN2WAN_ACTIONS      (NAT_LAN2WAN_ACTIONS | ACTION_PPPOE_INS_BIT)
18111 +#define NAT_PPPOE_WAN2LAN_ACTIONS      (NAT_WAN2LAN_ACTIONS | ACTION_PPPOE_DEL_BIT)
18112 +#define NAT_PPTP_LAN2WAN_ACTIONS       (NAT_ACTION_BITS | ACTION_SIP_BIT | ACTION_L4_FOURTH_BIT)
18113 +#define NAT_PPTP_WAN2LAN_ACTIONS       (NAT_ACTION_BITS | ACTION_DIP_BIT | ACTION_L4_FOURTH_BIT)
18114 +#define NAT_PPPOE_PPTP_LAN2WAN_ACTIONS (NAT_PPTP_LAN2WAN_ACTIONS | ACTION_PPPOE_INS_BIT)
18115 +#define NAT_PPPOE_PPTP_WAN2LAN_ACTIONS (NAT_PPTP_WAN2LAN_ACTIONS | ACTION_PPPOE_DEL_BIT)
18116 +                                                               
18117 +/*----------------------------------------------------------------------
18118 + *  parameter
18119 + ----------------------------------------------------------------------*/
18120 +typedef struct {
18121 +       u8              da[6];
18122 +       u8              sa[6];
18123 +       u16             vlan;   
18124 +       u16     pppoe;  
18125 +       u32             Sip;
18126 +       u32             Dip;
18127 +       u16     Sport;  
18128 +       u16     Dport;  
18129 +       u16     sw_id;  
18130 +       u16     mtu;    
18131 +} ENTRY_PARAM_T;
18132 +
18133 +/*----------------------------------------------------------------------
18134 + *  Hash Entry
18135 + ----------------------------------------------------------------------*/
18136 +typedef struct {
18137 +       char                    rule;
18138 +       ENTRY_KEY_T             key;
18139 +       KEY_FIELD_T             key_present;
18140 +       ENTRY_ACTION_T  action;
18141 +       ENTRY_PARAM_T   param;
18142 +       int                             index;
18143 +       int                             total_dwords;
18144 +} HASH_ENTRY_T;
18145 +
18146 +/*----------------------------------------------------------------------
18147 + *  NAT Hash Entry
18148 + ----------------------------------------------------------------------*/
18149 +typedef struct {
18150 +       short   counter;
18151 +       short   interval;
18152 +} HASH_TIMEOUT_T;
18153 +
18154 +/*----------------------------------------------------------------------
18155 + *  NAT Hash Entry for TCP/UDP protocol
18156 + ----------------------------------------------------------------------*/
18157 +typedef struct {
18158 +       NAT_KEY_T                       key;
18159 +       union {
18160 +               u32                             dword;
18161 +               ENTRY_ACTION_T  bits;
18162 +       } action;
18163 +       ENTRY_PARAM_T           param;
18164 +       HASH_TIMEOUT_T          tmo;    // used by software only, to use memory space efficiently
18165 +} NAT_HASH_ENTRY_T;
18166 +
18167 +#define NAT_HASH_ENTRY_SIZE            (sizeof(NAT_HASH_ENTRY_T))
18168 +
18169 +/*----------------------------------------------------------------------
18170 + *  GRE Hash Entry for PPTP/GRE protocol
18171 + ----------------------------------------------------------------------*/
18172 +typedef struct {
18173 +       GRE_KEY_T                       key;
18174 +       union {
18175 +               u32                             dword;
18176 +               ENTRY_ACTION_T  bits;
18177 +       } action;
18178 +       ENTRY_PARAM_T           param;
18179 +       HASH_TIMEOUT_T          tmo;    // used by software only, to use memory space efficiently
18180 +} GRE_HASH_ENTRY_T;
18181 +
18182 +#define GRE_HASH_ENTRY_SIZE            (sizeof(GRE_HASH_ENTRY_T))
18183 +
18184 +/*----------------------------------------------------------------------
18185 + *  External Variables
18186 + ----------------------------------------------------------------------*/
18187 +extern char                            hash_tables[HASH_TOTAL_ENTRIES][HASH_MAX_BYTES] __attribute__ ((aligned(16)));
18188 +extern u32                             hash_nat_owner_bits[HASH_TOTAL_ENTRIES/32];
18189 +/*----------------------------------------------------------------------
18190 +* hash_get_valid_flag
18191 +*----------------------------------------------------------------------*/
18192 +static inline int hash_get_valid_flag(int index)
18193 +{
18194 +       volatile u32 *hash_valid_bits_ptr = (volatile u32 *)TOE_V_BIT_BASE;
18195 +
18196 +#ifdef SL351x_GMAC_WORKAROUND
18197 +       if (index >= (0x80 * 8) && index < (0x8c * 8))
18198 +               return 1;
18199 +#endif 
18200 +       return (hash_valid_bits_ptr[index/32] & (1 << (index %32)));
18201 +}
18202 +
18203 +/*----------------------------------------------------------------------
18204 +* hash_get_nat_owner_flag
18205 +*----------------------------------------------------------------------*/
18206 +static inline int hash_get_nat_owner_flag(int index)
18207 +{
18208 +       return (hash_nat_owner_bits[index/32] & (1 << (index %32)));
18209 +}
18210 +
18211 +/*----------------------------------------------------------------------
18212 +* hash_validate_entry
18213 +*----------------------------------------------------------------------*/
18214 +static inline void hash_validate_entry(int index)
18215 +{
18216 +       volatile u32    *hash_valid_bits_ptr = (volatile u32 *)TOE_V_BIT_BASE;
18217 +       register int    ptr = index/32, bits = 1 << (index %32);
18218 +       
18219 +       hash_valid_bits_ptr[ptr] |= bits;
18220 +}
18221 +
18222 +/*----------------------------------------------------------------------
18223 +* hash_invalidate_entry
18224 +*----------------------------------------------------------------------*/
18225 +static inline void hash_invalidate_entry(int index)
18226 +{
18227 +       volatile u32 *hash_valid_bits_ptr = (volatile u32 *)TOE_V_BIT_BASE;
18228 +       register int    ptr = index/32, bits = 1 << (index %32);
18229 +       
18230 +       hash_valid_bits_ptr[ptr] &= ~(bits);
18231 +}
18232 +
18233 +/*----------------------------------------------------------------------
18234 +* hash_nat_enable_owner
18235 +*----------------------------------------------------------------------*/
18236 +static inline void hash_nat_enable_owner(int index)
18237 +{
18238 +       hash_nat_owner_bits[index/32] |= (1 << (index % 32));
18239 +}
18240 +
18241 +/*----------------------------------------------------------------------
18242 +* hash_nat_disable_owner
18243 +*----------------------------------------------------------------------*/
18244 +static inline void hash_nat_disable_owner(int index)
18245 +{
18246 +       hash_nat_owner_bits[index/32] &= ~(1 << (index % 32));
18247 +}
18248 +
18249 +/*----------------------------------------------------------------------
18250 +* hash_get_entry
18251 +*----------------------------------------------------------------------*/
18252 +static inline void *hash_get_entry(int index)
18253 +{
18254 +       return (void*) &hash_tables[index][0];
18255 +}
18256 +
18257 +/*----------------------------------------------------------------------
18258 +* Functions
18259 +*----------------------------------------------------------------------*/
18260 +extern int hash_add_entry(HASH_ENTRY_T *entry);
18261 +extern void sl351x_hash_init(void);
18262 +extern void hash_set_valid_flag(int index, int valid);
18263 +extern void hash_set_nat_owner_flag(int index, int valid);
18264 +extern void *hash_get_entry(int index);
18265 +extern int hash_build_keys(u32 *destp, HASH_ENTRY_T *entry);
18266 +extern void hash_build_nat_keys(u32 *destp, HASH_ENTRY_T *entry);
18267 +extern int hash_write_entry(HASH_ENTRY_T *entry, u8 *key);
18268 +extern int hash_add_entry(HASH_ENTRY_T *entry);
18269 +extern u16 hash_crc16(u16 crc, u8 *datap, u32 len);
18270 +extern u16 hash_gen_crc16(u8 *datap, u32 len);
18271 +
18272 +#endif // _SL351x_HASH_CFG_H_
18273 +
18274 +
18275 +
18276 Index: linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_nat_cfg.h
18277 ===================================================================
18278 --- /dev/null
18279 +++ linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_nat_cfg.h
18280 @@ -0,0 +1,211 @@
18281 +/**************************************************************************
18282 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.                
18283 +*--------------------------------------------------------------------------
18284 +*      sl_nat_cfg.h
18285 +*
18286 +*      Description:
18287 +*              - Define the Device Control Commands for NAT Configuration
18288 +*      
18289 +*      History:
18290 +*
18291 +*      4/28/2006       Gary Chen       Create
18292 +*
18293 +*-----------------------------------------------------------------------------*/
18294 +#ifndef _SL351x_NAT_CFG_H_
18295 +#define _SL351x_NAT_CFG_H_     1
18296 +
18297 +/*----------------------------------------------------------------------
18298 +* Confiuration
18299 +*----------------------------------------------------------------------*/
18300 +#ifdef CONFIG_NETFILTER
18301 +#define CONFIG_SL351x_NAT                      1
18302 +#undef CONFIG_SL351x_NAT
18303 +#undef CONFIG_SL351x_SYSCTL
18304 +#endif
18305 +#define CONFIG_NAT_MAX_IP_NUM          4       // per device (eth0 or eth1)
18306 +#define CONFIG_NAT_MAX_XPORT           64
18307 +#define CONFIG_NAT_MAX_WRULE           16      // per Queue
18308 +#define CONFIG_NAT_TXQ_NUM                     4
18309 +/*----------------------------------------------------------------------
18310 +* Command set
18311 +*----------------------------------------------------------------------*/
18312 +#define SIOCDEVSL351x  SIOCDEVPRIVATE  // 0x89F0
18313 +#define NATSSTATUS             0
18314 +#define NATGSTATUS             1
18315 +#define NATSETPORT             2
18316 +#define NATGETPORT             3
18317 +#define NATADDIP               4
18318 +#define NATDELIP               5
18319 +#define NATGETIP               6
18320 +#define NATAXPORT              7
18321 +#define NATDXPORT              8
18322 +#define NATGXPORT              9
18323 +#define NATSWEIGHT             10
18324 +#define NATGWEIGHT             11
18325 +#define NATAWRULE              12
18326 +#define NATDWRULE              13
18327 +#define NATGWRULE              14
18328 +#define NATSDEFQ               15
18329 +#define NATGDEFQ               16
18330 +#define NATRMIPCFG             17              // remove IP config
18331 +#define NATTESTENTRY   18
18332 +#define NATSETMEM              19
18333 +#define NATSHOWMEM             20
18334 +/*----------------------------------------------------------------------
18335 +* Command Structure
18336 +*----------------------------------------------------------------------*/
18337 +// Common Header
18338 +typedef struct {
18339 +       unsigned short          cmd;    // command ID
18340 +       unsigned short          len;    // data length, excluding this header
18341 +} NATCMD_HDR_T;
18342 +
18343 +// NATSSTATUS & NATGSTATUS commands
18344 +typedef struct {
18345 +       unsigned char           enable;
18346 +} NAT_STATUS_T;        
18347 +
18348 +// NATSETPORT & NATGETPORT commands
18349 +typedef struct {
18350 +       unsigned char           portmap;
18351 +} NAT_PORTCFG_T;
18352 +
18353 +typedef struct {
18354 +       unsigned int            ipaddr;
18355 +       unsigned int            netmask;
18356 +} NAT_IP_ENTRY_T;
18357 +
18358 +// NATADDIP & NATDELIP commands
18359 +typedef struct {
18360 +       NAT_IP_ENTRY_T  entry;
18361 +} NAT_IPCFG_T;
18362 +
18363 +// NATGETIP command
18364 +typedef struct {
18365 +       unsigned int    total;
18366 +       NAT_IP_ENTRY_T  entry[CONFIG_NAT_MAX_IP_NUM];
18367 +} NAT_IPCFG_ALL_T;
18368 +
18369 +typedef struct {
18370 +       unsigned int            protocol;
18371 +       unsigned short          sport_start;
18372 +       unsigned short          sport_end;
18373 +       unsigned short          dport_start;
18374 +       unsigned short          dport_end;
18375 +} NAT_XPORT_ENTRY_T;
18376 +
18377 +// NATAXPORT & NATDXPORT Commands
18378 +typedef struct {
18379 +       NAT_XPORT_ENTRY_T       entry;
18380 +} NAT_XPORT_T;
18381 +
18382 +// NATGXPORT Command
18383 +typedef struct {
18384 +       unsigned int            total;
18385 +       NAT_XPORT_ENTRY_T       entry[CONFIG_NAT_MAX_XPORT];
18386 +} NAT_XPORT_ALL_T;
18387 +
18388 +// NATSWEIGHT & NATGWEIGHT Commands
18389 +typedef struct {
18390 +       unsigned char           weight[CONFIG_NAT_TXQ_NUM];
18391 +} NAT_WEIGHT_T;
18392 +
18393 +typedef struct {
18394 +       unsigned int            protocol;
18395 +       unsigned int            sip_start;
18396 +       unsigned int            sip_end;
18397 +       unsigned int            dip_start;
18398 +       unsigned int            dip_end;
18399 +       unsigned short          sport_start;
18400 +       unsigned short          sport_end;
18401 +       unsigned short          dport_start;
18402 +       unsigned short          dport_end;
18403 +} NAT_WRULE_ENTRY_T;   
18404 +
18405 +// NATAWRULE & NATDWRULE Commands
18406 +typedef struct {
18407 +       unsigned int            qid;
18408 +       NAT_WRULE_ENTRY_T       entry;
18409 +} NAT_WRULE_T;
18410 +
18411 +// NATGWRULE Command
18412 +typedef struct {
18413 +       unsigned int            total;
18414 +       NAT_WRULE_ENTRY_T       entry[CONFIG_NAT_MAX_WRULE];
18415 +} NAT_WRULE_ALL_T;
18416 +
18417 +// NATSDEFQ & NATGDEFQ commands
18418 +typedef struct {
18419 +       unsigned int            qid;
18420 +} NAT_QUEUE_T; 
18421 +
18422 +// NATTESTENTRY 
18423 +typedef struct {
18424 +       u_int16_t               cmd;    // command ID
18425 +       u_int16_t               len;    // data length, excluding this header
18426 +       u_int8_t                init_enable;
18427 +} NAT_TESTENTRY_T;     
18428 +       
18429 +typedef union
18430 +{
18431 +       NAT_STATUS_T            status;
18432 +       NAT_PORTCFG_T           portcfg;
18433 +       NAT_IPCFG_T                     ipcfg;
18434 +       NAT_XPORT_T                     xport;
18435 +       NAT_WEIGHT_T            weight;
18436 +       NAT_WRULE_T                     wrule;
18437 +       NAT_QUEUE_T                     queue;
18438 +       NAT_TESTENTRY_T init_entry;
18439 +} NAT_REQ_E;
18440 +       
18441 +/*----------------------------------------------------------------------
18442 +* NAT Configuration
18443 +*      - Used by driver only
18444 +*----------------------------------------------------------------------*/
18445 +typedef struct {
18446 +       unsigned int            enabled;
18447 +       unsigned int            init_enabled;
18448 +       unsigned int            tcp_udp_rule_id;
18449 +       unsigned int            gre_rule_id;
18450 +       unsigned int            lan_port;
18451 +       unsigned int            wan_port;
18452 +       unsigned int            default_hw_txq;
18453 +       short                           tcp_tmo_interval;
18454 +       short                           udp_tmo_interval;
18455 +       short                           gre_tmo_interval;
18456 +       NAT_IPCFG_ALL_T         ipcfg[2];       // LAN/WAN port
18457 +       NAT_XPORT_ALL_T         xport;
18458 +       NAT_WEIGHT_T            weight;
18459 +       NAT_WRULE_ALL_T         wrule[CONFIG_NAT_TXQ_NUM];
18460 +} NAT_CFG_T;
18461 +
18462 +/*----------------------------------------------------------------------
18463 +* NAT Control Block
18464 +*      - Used by driver only
18465 +*      - Stores LAN-IN or WAN-IN information
18466 +*      - WAN-OUT and LAN-OUT driver use them to build up a hash entry
18467 +*      - NOTES: To update this data structure, MUST take care of alignment issue
18468 +*   -           MUST make sure that the size of skbuff structure must 
18469 +*            be larger than (40 + sizof(NAT_CB_T))
18470 +*----------------------------------------------------------------------*/
18471 +typedef struct {
18472 +       unsigned short          tag;
18473 +       unsigned char           sa[6];
18474 +       unsigned int            sip;
18475 +       unsigned int            dip;
18476 +       unsigned short          sport;
18477 +       unsigned short          dport;
18478 +       unsigned char           pppoe_frame;
18479 +       unsigned char           state;                  // same to enum tcp_conntrack
18480 +       unsigned char           reserved[2];
18481 +} NAT_CB_T;
18482 +
18483 +#define NAT_CB_TAG             0x4C53  // "SL"
18484 +#define NAT_CB_SIZE            sizeof(NAT_CB_T)
18485 +// #define NAT_SKB_CB(skb)     (NAT_CB_T *)(((unsigned int)&((skb)->cb[40]) + 3) & ~3)  // for align 4
18486 +#define NAT_SKB_CB(skb)        (NAT_CB_T *)&((skb)->cb[40])  // for align 4
18487 +
18488 +#endif // _SL351x_NAT_CFG_H_
18489 +
18490 +
18491 +
18492 Index: linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_toe.h
18493 ===================================================================
18494 --- /dev/null
18495 +++ linux-2.6.23.17/include/asm-arm/arch-sl2312/sl351x_toe.h
18496 @@ -0,0 +1,88 @@
18497 +/**************************************************************************
18498 +* Copyright 2006 StorLink Semiconductors, Inc.  All rights reserved.
18499 +*--------------------------------------------------------------------------
18500 +* Name                 : sl351x_toe.h
18501 +* Description  :
18502 +*              Define for TOE driver of Storlink SL351x
18503 +*
18504 +* History
18505 +*
18506 +*      Date            Writer          Description
18507 +*----------------------------------------------------------------------------
18508 +*                              Xiaochong       Create
18509 +*
18510 +****************************************************************************/
18511 +#ifndef __SL351x_TOE_H
18512 +#define __SL351x_TOE_H 1
18513 +#include <net/sock.h>
18514 +#include <asm/arch/sl351x_gmac.h>
18515 +#include <linux/timer.h>
18516 +#include <linux/netdevice.h>
18517 +#include <linux/ip.h>
18518 +#include <linux/if_ether.h>
18519 +/*
18520 + * TOE_CONN_T is data structure of tcp connection info, used at both
18521 + * device layer and kernel tcp layer
18522 + * skb is the jumbo frame
18523 + */
18524 +
18525 +struct toe_conn{
18526 +       __u8    qid;            // connection qid 0~63.
18527 +       __u8    ip_ver;         // 0: not used; 4: ipv4; 6: ipv6.
18528 +       /* hash key of the connection */
18529 +       __u16   source;
18530 +       __u16   dest;
18531 +       __u32   saddr[4];
18532 +       __u32   daddr[4];
18533 +
18534 +       __u32   seq;
18535 +       __u32   ack_seq;
18536 +
18537 +       /* these fields are used to set TOE QHDR */
18538 +       __u32   ack_threshold;
18539 +       __u32   seq_threshold;
18540 +       __u16   max_pktsize;
18541 +
18542 +       /* used by sw toe, accumulated ack_seq of ack frames */
18543 +       __u16   ack_cnt;
18544 +       /* used by sw toe, accumulated data frames held at driver */
18545 +       __u16   cur_pktsize;
18546 +
18547 +       __u8    status;
18548 +#define        TCP_CONN_UNDEFINE               0X00
18549 +#define        TCP_CONN_CREATION               0X01
18550 +#define        TCP_CONN_CONNECTING             0X02
18551 +#define        TCP_CONN_ESTABLISHED    0X04
18552 +#define        TCP_CONN_RESET                  0X08    // this is used for out-of-order
18553 +                                               // or congestion window is small
18554 +#define        TCP_CONN_CLOSING                0X10
18555 +#define        TCP_CONN_CLOSED                 0x11
18556 +
18557 +       __u16   hash_entry_index;       /* associated hash entry */
18558 +
18559 +       // one timer per connection. Otherwise all connections should be scanned
18560 +       // in a timeout interrupt, and timeout interrupt is triggered no matter
18561 +       // a connection is actually timeout or not.
18562 +       struct timer_list       rx_timer;
18563 +       unsigned long           last_rx_jiffies;
18564 +       GMAC_INFO_T                     *gmac;
18565 +       struct net_device       *dev;
18566 +
18567 +       //      for generating pure ack frame.
18568 +       struct ethhdr           l2_hdr;
18569 +       struct iphdr            l3_hdr;
18570 +
18571 +       spinlock_t                      conn_lock;
18572 +       DMA_RWPTR_T                     toeq_rwptr;
18573 +       GMAC_RXDESC_T           *curr_desc;
18574 +       struct sk_buff          *curr_rx_skb;
18575 +};
18576 +
18577 +struct jumbo_frame {
18578 +       struct sk_buff  *skb0;          // the head of jumbo frame
18579 +       struct sk_buff  *tail;          // the tail of jumbo frame
18580 +       struct iphdr    *iphdr0;        // the ip hdr of skb0.
18581 +       struct tcphdr   *tcphdr0;       // the tcp hdr of skb0.
18582 +};
18583 +
18584 +#endif // __SL351x_TOE_H