target/linux/storm/patches/1001-arch.patch

   1 Index: linux-2.6.23.16/arch/arm/Kconfig
   2 ===================================================================
   3 --- linux-2.6.23.16.orig/arch/arm/Kconfig       2008-03-13 17:46:04.000791190 +0200
   4 +++ linux-2.6.23.16/arch/arm/Kconfig    2008-03-13 17:48:24.508798285 +0200
   5 @@ -220,6 +220,9 @@
   6         help
   7           This enables support for the Cirrus EP93xx series of CPUs.
   8
   9 +config ARCH_SL2312
  10 +    bool "SL2312"
  11 +
  12  config ARCH_FOOTBRIDGE
  13         bool "FootBridge"
  14         select FOOTBRIDGE
  15 @@ -414,6 +417,8 @@
  16
  17  source "arch/arm/mach-footbridge/Kconfig"
  18
  19 +source "arch/arm/mach-sl2312/Kconfig"
  20 +
  21  source "arch/arm/mach-integrator/Kconfig"
  22
  23  source "arch/arm/mach-iop32x/Kconfig"
  24 @@ -549,6 +554,16 @@
  25  config PCI_SYSCALL
  26         def_bool PCI
  27
  28 +config SL2312_LPC
  29 +    bool "LPC Host Support"
  30 +    depends on ARCH_SL2312
  31 +    help
  32 +
  33 +config SL2312_LPC_IT8712
  34 +    bool "IT8712 Support"
  35 +    depends on ARCH_SL2312 && SL2312_LPC
  36 +    help
  37 +
  38  # Select the host bridge type
  39  config PCI_HOST_VIA82C505
  40         bool
  41 @@ -988,6 +1003,10 @@
  42  source "drivers/mtd/Kconfig"
  43  endif
  44
  45 +if ARCH_SL2312
  46 +source "drivers/telephony/Kconfig"
  47 +endif
  48 +
  49  source "drivers/parport/Kconfig"
  50
  51  source "drivers/pnp/Kconfig"
  52 @@ -997,7 +1016,7 @@
  53  if PCMCIA || ARCH_CLPS7500 || ARCH_IOP32X || ARCH_IOP33X || ARCH_IXP4XX \
  54         || ARCH_L7200 || ARCH_LH7A40X || ARCH_PXA || ARCH_RPC \
  55         || ARCH_S3C2410 || ARCH_SA1100 || ARCH_SHARK || FOOTBRIDGE \
  56 -       || ARCH_IXP23XX
  57 +       || ARCH_IXP23XX || ARCH_SL2312
  58  source "drivers/ide/Kconfig"
  59  endif
  60
  61 Index: linux-2.6.23.16/arch/arm/Makefile
  62 ===================================================================
  63 --- linux-2.6.23.16.orig/arch/arm/Makefile      2008-03-13 17:46:04.500819685 +0200
  64 +++ linux-2.6.23.16/arch/arm/Makefile   2008-03-13 17:48:24.508798285 +0200
  65 @@ -72,6 +72,7 @@
  66  tune-$(CONFIG_CPU_ARM922T)     :=-mtune=arm9tdmi
  67  tune-$(CONFIG_CPU_ARM925T)     :=-mtune=arm9tdmi
  68  tune-$(CONFIG_CPU_ARM926T)     :=-mtune=arm9tdmi
  69 +tune-$(CONFIG_CPU_FA52X)    :=-mtune=arm9tdmi
  70  tune-$(CONFIG_CPU_SA110)       :=-mtune=strongarm110
  71  tune-$(CONFIG_CPU_SA1100)      :=-mtune=strongarm1100
  72  tune-$(CONFIG_CPU_XSCALE)      :=$(call cc-option,-mtune=xscale,-mtune=strongarm110) -Wa,-mcpu=xscale
  73 @@ -111,6 +112,7 @@
  74   machine-$(CONFIG_ARCH_PXA)       := pxa
  75   machine-$(CONFIG_ARCH_L7200)     := l7200
  76   machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
  77 + machine-$(CONFIG_ARCH_SL2312)     := sl2312
  78   textofs-$(CONFIG_ARCH_CLPS711X)   := 0x00028000
  79   machine-$(CONFIG_ARCH_CLPS711X)   := clps711x
  80   machine-$(CONFIG_ARCH_IOP32X)    := iop32x
  81 Index: linux-2.6.23.16/arch/arm/boot/compressed/Makefile
  82 ===================================================================
  83 --- linux-2.6.23.16.orig/arch/arm/boot/compressed/Makefile      2008-03-13 17:46:04.500819685 +0200
  84 +++ linux-2.6.23.16/arch/arm/boot/compressed/Makefile   2008-03-13 17:48:24.508798285 +0200
  85 @@ -19,6 +19,10 @@
  86  OBJS           += head-shark.o ofw-shark.o
  87  endif
  88
  89 +ifeq ($(CONFIG_ARCH_SL2312),y)
  90 +OBJS           += head-sl2312.o
  91 +endif
  92 +
  93  ifeq ($(CONFIG_ARCH_L7200),y)
  94  OBJS           += head-l7200.o
  95  endif
  96 Index: linux-2.6.23.16/arch/arm/boot/compressed/head-sl2312.S
  97 ===================================================================
  98 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  99 +++ linux-2.6.23.16/arch/arm/boot/compressed/head-sl2312.S      2008-03-13 17:48:24.508798285 +0200
 100 @@ -0,0 +1,6 @@
 101 +#include <asm/mach-types.h>
 102 +#include <asm/arch/sl2312.h>
 103 +
 104 +               .section        ".start", "ax"
 105 +               mov     r7, #MACH_TYPE_SL2312
 106 +
 107 Index: linux-2.6.23.16/arch/arm/boot/compressed/head.S
 108 ===================================================================
 109 --- linux-2.6.23.16.orig/arch/arm/boot/compressed/head.S        2008-03-13 17:46:04.500819685 +0200
 110 +++ linux-2.6.23.16/arch/arm/boot/compressed/head.S     2008-03-13 17:48:24.508798285 +0200
 111 @@ -57,6 +57,17 @@
 112                 mov     \rb, #0x50000000
 113                 add     \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
 114                 .endm
 115 +/*****************************************************
 116 + *      for Storlink SoC
 117 + *****************************************************/
 118 +#elif defined(CONFIG_ARCH_SL2312)
 119 +               .macro  loadsp, rb
 120 +               mov     \rb, #0x16000000
 121 +               .endm
 122 +               .macro  writeb, rb
 123 +               strb    \rb, [r3, #0]
 124 +               .endm
 125 +/****************************************************/
 126  #else
 127                 .macro  loadsp, rb
 128                 addruart \rb
 129 @@ -116,7 +127,28 @@
 130                 .rept   8
 131                 mov     r0, r0
 132                 .endr
 133 -
 134 +/*****************************************************************************
 135 + *  for Storlink Soc -- on chip UART
 136 + *****************************************************************************/
 137 +#ifndef CONFIG_SERIAL_IT8712           // Jason test
 138 +@                mov     r3, #0x22000000
 139 +                mov     r3, #0x42000000
 140 +                mov     r11, #0x80
 141 +                strb    r11, [r3, #0xc]
 142 +                mov     r11, #0x0
 143 +                strb    r11, [r3, #0x4]
 144 +#ifndef CONFIG_SL3516_ASIC
 145 +                mov     r11, #0x9C             /*0x9c->19200 0x4E->38400 0x34->57600 */
 146 +#else
 147 +               mov     r11, #0x9C              /* 0x61 for 30MHz on GeminiA chip*/
 148 +#endif
 149 +                strb    r11, [r3, #0x0]
 150 +                mov     r11, #0x03
 151 +                strb    r11, [r3, #0xc]
 152 +                       mov     r11, #0xFB
 153 +                strb    r11, [r3, #0x18]
 154 +#endif
 155 +/*****************************************************************************/
 156                 b       1f
 157                 .word   0x016f2818              @ Magic numbers to help the loader
 158                 .word   start                   @ absolute load/run zImage address
 159 @@ -458,6 +490,39 @@
 160                 mcr     p15, 0, r0, c7, c5, 4   @ ISB
 161                 mov     pc, r12
 162
 163 +/*****************************************************************************
 164 + *  for Storlink Soc -- CPU cache
 165 + *****************************************************************************/
 166 +__fa526_cache_on:
 167 +                mov     r12, lr
 168 +                bl      __setup_mmu
 169 +                mov     r0, #0
 170 +                mcr     p15, 0, r0, c7, c6, 0   @ Invalidate D cache
 171 +                mcr     p15, 0, r0, c7, c5, 0   @ Invalidate I cache
 172 +                mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
 173 +                mcr     p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
 174 +                mcr     p15, 0, r3, c2, c0, 0   @ load page table pointer
 175 +                mov     r0, #-1
 176 +                mcr     p15, 0, r0, c3, c0, 0   @ load domain access register
 177 +                mrc     p15, 0, r0, c1, c0, 0
 178 +                mov     r0, r0
 179 +                mov     r0, r0
 180 +#ifndef CONFIG_CPU_DCACHE_DISABLE
 181 +        orr     r0, r0, #0x0004                 @ .... .... .... .1..
 182 +#endif
 183 +#ifndef CONFIG_CPU_ICACHE_DISABLE
 184 +        orr     r0, r0, #0x1000                 @ ...1 .... .... ....
 185 +#endif
 186 +
 187 +#ifndef DEBUG
 188 +                orr     r0, r0, #0x0039         @ Write buffer, mmu
 189 +#endif
 190 +                mcr     p15, 0, r0, c1, c0
 191 +                mov     r0, r0
 192 +                mov     r0, r0
 193 +                mov     pc, r12
 194 +/********************************************************************************/
 195 +
 196  __arm6_mmu_cache_on:
 197                 mov     r12, lr
 198                 bl      __setup_mmu
 199 @@ -625,6 +690,16 @@
 200
 201                 @ These match on the architecture ID
 202
 203 +/*****************************************************************************
 204 + *  for Storlink Soc -- CPU architecture ID
 205 + *****************************************************************************/
 206 +        .word   0x66015261              @ FA526
 207 +        .word   0xff01fff1
 208 +        b       __fa526_cache_on
 209 +        b       __fa526_cache_off
 210 +        b       __fa526_cache_flush
 211 +/*****************************************************************************/
 212 +
 213                 .word   0x00020000              @ ARMv4T
 214                 .word   0x000f0000
 215                 b       __armv4_mmu_cache_on
 216 @@ -712,6 +787,23 @@
 217                 mcr     p15, 0, r0, c8, c7, 0   @ invalidate whole TLB
 218                 mov     pc, r12
 219
 220 +/*****************************************************************************
 221 + *  for Storlink Soc -- CPU cache
 222 + *****************************************************************************/
 223 +__fa526_cache_off:
 224 +        mrc     p15, 0, r0, c1, c0
 225 +        bic     r0, r0, #0x000d
 226 +        mov     r1, #0
 227 +        mcr     p15, 0, r1, c7, c14, 0  @ clean and invalidate D cache
 228 +        mcr     p15, 0, r1, c7, c10, 4  @ drain WB
 229 +        mcr     p15, 0, r0, c1, c0      @ turn MMU and cache off
 230 +        mov     r0, #0
 231 +        mcr     p15, 0, r0, c7, c5, 0   @ invalidate whole cache v4
 232 +        mcr     p15, 0, r0, c8, c7, 0   @ invalidate whole TLB v4
 233 +        mov     pc, lr
 234 +/*****************************************************************************/
 235 +
 236 +
 237  __arm6_mmu_cache_off:
 238                 mov     r0, #0x00000030         @ ARM6 control reg.
 239                 b       __armv3_mmu_cache_off
 240 @@ -759,6 +851,17 @@
 241                 mcr     p15, 0, ip, c7, c10, 4  @ drain WB
 242                 mov     pc, lr
 243
 244 +/*****************************************************************************
 245 + *  for Storlink Soc -- CPU cache
 246 + *****************************************************************************/
 247 +__fa526_cache_flush:
 248 +                mov     r1, #0
 249 +                mcr     p15, 0, r1, c7, c14, 0  @ clean and invalidate D cache
 250 +                mcr     p15, 0, r1, c7, c5, 0   @ flush I cache
 251 +                mcr     p15, 0, r1, c7, c10, 4  @ drain WB
 252 +                mov     pc, lr
 253 +/*****************************************************************************/
 254 +
 255
 256  __armv6_mmu_cache_flush:
 257                 mov     r1, #0
 258 Index: linux-2.6.23.16/arch/arm/boot/compressed/it8712.h
 259 ===================================================================
 260 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 261 +++ linux-2.6.23.16/arch/arm/boot/compressed/it8712.h   2008-03-13 17:48:24.508798285 +0200
 262 @@ -0,0 +1,25 @@
 263 +
 264 +#ifndef __IT8712_H__
 265 +#define __IT8712_H__
 266 +
 267 +#include "asm/arch/sl2312.h"
 268 +
 269 +#define IT8712_IO_BASE                 SL2312_LPC_IO_BASE
 270 +//#define IT8712_IO_BASE                       0x27000000
 271 +// Device LDN
 272 +#define LDN_SERIAL1                            0x01
 273 +#define LDN_SERIAL2                            0x02
 274 +#define LDN_PARALLEL                   0x03
 275 +#define LDN_KEYBOARD                   0x05
 276 +#define LDN_MOUSE                              0x06
 277 +#define LDN_GPIO                               0x07
 278 +
 279 +#define IT8712_UART1_PORT              0x3F8
 280 +#define IT8712_UART2_PORT              0x2F8
 281 +
 282 +#define IT8712_GPIO_BASE               0x800   // 0x800-0x804 for GPIO set1-set5
 283 +
 284 +void LPCSetConfig(char LdnNumber, char Index, char data);
 285 +char LPCGetConfig(char LdnNumber, char Index);
 286 +
 287 +#endif
 288 Index: linux-2.6.23.16/arch/arm/boot/compressed/misc.c
 289 ===================================================================
 290 --- linux-2.6.23.16.orig/arch/arm/boot/compressed/misc.c        2008-03-13 17:46:04.500819685 +0200
 291 +++ linux-2.6.23.16/arch/arm/boot/compressed/misc.c     2008-03-13 17:48:24.508798285 +0200
 292 @@ -30,7 +30,7 @@
 293  #include <asm/arch/uncompress.h>
 294
 295  #ifdef CONFIG_DEBUG_ICEDCC
 296 -
 297 +#include "it8712.h"
 298  #ifdef CONFIG_CPU_V6
 299
 300  static void icedcc_putc(int ch)
 301 @@ -69,6 +69,7 @@
 302  #define flush()        do { } while (0)
 303  #endif
 304
 305 +#if 0
 306  static void putstr(const char *ptr)
 307  {
 308         char c;
 309 @@ -81,11 +82,36 @@
 310
 311         flush();
 312  }
 313 +#endif
 314
 315  #endif
 316
 317  #define __ptr_t void *
 318
 319 +#ifdef CONFIG_SERIAL_IT8712
 320 +unsigned int it8712_uart_base;
 321 +#define UART_RX         0
 322 +#define UART_TX         0
 323 +#define UART_DLL        0
 324 +#define UART_TRG        0
 325 +#define UART_DLM        1
 326 +#define UART_IER        1
 327 +#define UART_FCTR       1
 328 +#define UART_IIR        2
 329 +#define UART_FCR        2
 330 +#define UART_EFR        2
 331 +#define UART_LCR        3
 332 +#define UART_MCR        4
 333 +#define UART_LSR        5
 334 +#define UART_MSR        6
 335 +#define UART_SCR        7
 336 +#define UART_EMSR       7
 337 +void LPCEnterMBPnP(void);
 338 +void LPCExitMBPnP(void);
 339 +int SearchIT8712(void);
 340 +int InitLPCInterface(void);
 341 +#endif
 342 +
 343  /*
 344   * Optimised C version of memzero for the ARM.
 345   */
 346 @@ -346,6 +372,9 @@
 347  decompress_kernel(ulg output_start, ulg free_mem_ptr_p, ulg free_mem_ptr_end_p,
 348                   int arch_id)
 349  {
 350 +#ifdef CONFIG_SERIAL_IT8712
 351 +        unsigned char *addr;
 352 +#endif
 353         output_data             = (uch *)output_start;  /* Points to kernel start */
 354         free_mem_ptr            = free_mem_ptr_p;
 355         free_mem_ptr_end        = free_mem_ptr_end_p;
 356 @@ -353,6 +382,33 @@
 357
 358         arch_decomp_setup();
 359
 360 +#ifdef CONFIG_SERIAL_IT8712
 361 +
 362 +        InitLPCInterface();
 363 +        LPCSetConfig(0, 0x02, 0x01);
 364 +        LPCSetConfig(LDN_SERIAL1, 0x30, 0x1);
 365 +        LPCSetConfig(LDN_SERIAL1, 0x23, 0x0);
 366 +        it8712_uart_base = IT8712_IO_BASE;
 367 +        it8712_uart_base += ((LPCGetConfig(LDN_SERIAL1, 0x60) << 8) + LPCGetConfig(LDN_SERIAL1, 0x61));
 368 +
 369 +        do {
 370 +        addr = (unsigned char *)(it8712_uart_base + UART_LCR) ;
 371 +        *addr = 0x80;
 372 +        // Set Baud Rate
 373 +        addr = (unsigned char *)(it8712_uart_base+UART_DLL);
 374 +        *addr = 0x06 ;
 375 +        addr = (unsigned char *)(it8712_uart_base+UART_DLM);
 376 +        *addr = 0x00 ;
 377 +
 378 +        addr = (unsigned char *)(it8712_uart_base+UART_LCR);    // LCR
 379 +        *addr = 0x07 ;
 380 +        addr = (unsigned char *)(it8712_uart_base+UART_MCR);    // MCR
 381 +        *addr = 0x08 ;
 382 +        addr = (unsigned char *)(it8712_uart_base+UART_FCR);    // FCR
 383 +        *addr = 0x01 ;
 384 +       } while(0);
 385 +#endif
 386 +
 387         makecrc();
 388         putstr("Uncompressing Linux...");
 389         gunzip();
 390 @@ -374,4 +430,119 @@
 391         return 0;
 392  }
 393  #endif
 394 +
 395 +#ifdef CONFIG_SERIAL_IT8712
 396 +
 397 +#define LPC_KEY_ADDR    (unsigned char *)(SL2312_LPC_IO_BASE + 0x2e)
 398 +#define LPC_DATA_ADDR   (unsigned char *)(SL2312_LPC_IO_BASE + 0x2f)
 399 +#define LPC_BUS_CTRL                    *( unsigned char*) (SL2312_LPC_HOST_BASE + 0)
 400 +#define LPC_BUS_STATUS                  *( unsigned char*) (SL2312_LPC_HOST_BASE + 2)
 401 +#define LPC_SERIAL_IRQ_CTRL             *( unsigned char*) (SL2312_LPC_HOST_BASE + 4)
 402 +
 403 +char LPCGetConfig(char LdnNumber, char Index)
 404 +{
 405 +        char rtn;
 406 +        unsigned char *addr ;
 407 +
 408 +        LPCEnterMBPnP();                                // Enter IT8712 MB PnP mode
 409 +
 410 +        addr = LPC_KEY_ADDR;
 411 +        *addr = 0x07 ;
 412 +
 413 +        addr = LPC_DATA_ADDR;
 414 +        *addr = LdnNumber ;
 415 +
 416 +        addr = LPC_KEY_ADDR;
 417 +        *addr = Index ;
 418 +
 419 +        addr = LPC_DATA_ADDR ;
 420 +        rtn = *addr ;
 421 +
 422 +        LPCExitMBPnP();
 423 +        return rtn;
 424 +
 425 +}
 426 +
 427 +void LPCSetConfig(char LdnNumber, char Index, char data)
 428 +{
 429 +        unsigned char *addr;
 430 +        LPCEnterMBPnP();                                // Enter IT8712 MB PnP mode
 431 +        addr = LPC_KEY_ADDR;
 432 +        *addr = 0x07;
 433 +        addr = LPC_DATA_ADDR;
 434 +        *addr = LdnNumber;
 435 +        addr = LPC_KEY_ADDR;
 436 +        *addr = Index;
 437 +        addr = LPC_DATA_ADDR;
 438 +        *addr = data;
 439 +
 440 +        LPCExitMBPnP();
 441 +}
 442 +
 443 +//unsigned char key[4] ;
 444 +void LPCEnterMBPnP(void)
 445 +{
 446 +        unsigned char *addr;
 447 +        addr = LPC_KEY_ADDR;
 448 +        unsigned char key[4] = {0x87, 0x01, 0x55, 0x55};
 449 +
 450 +               do {
 451 +               *addr = key[0];
 452 +               *addr = key[1];
 453 +               *addr = key[2];
 454 +               *addr = key[3];
 455 +               }while(0);
 456 +}
 457 +
 458 +void LPCExitMBPnP(void)
 459 +{
 460 +        unsigned char *addr;
 461 +        addr = LPC_KEY_ADDR;
 462 +        *addr = 0x02 ;
 463 +
 464 +        addr = LPC_DATA_ADDR;
 465 +        *addr = 0x02 ;
 466 +}
 467 +
 468 +int InitLPCInterface(void)
 469 +{
 470 +        int i;
 471 +        LPC_BUS_CTRL = 0xc0;
 472 +        LPC_SERIAL_IRQ_CTRL = 0xc0;
 473 +
 474 +        for(i=0;i<0x2000;i++) ;
 475 +
 476 +        LPC_SERIAL_IRQ_CTRL = 0x80;
 477 +        if (!SearchIT8712()) ;
 478 +//                     while(1);
 479 +        return 0;
 480 +}
 481 +
 482 +int SearchIT8712(void)
 483 +{
 484 +        unsigned char Id1, Id2;
 485 +        unsigned short Id;
 486 +        unsigned char *addr;
 487 +
 488 +        LPCEnterMBPnP();
 489 +        addr = LPC_KEY_ADDR;
 490 +        *addr = 0x20 ;
 491 +        addr = LPC_DATA_ADDR;
 492 +        Id1 = *addr ;
 493 +
 494 +        addr = LPC_KEY_ADDR;
 495 +        *addr = 0x21 ;
 496 +        addr = LPC_DATA_ADDR;
 497 +        Id2 = *addr ;
 498 +
 499 +        Id = (Id1 << 8) | Id2;
 500 +        LPCExitMBPnP();
 501 +
 502 +        if (Id == 0x8712)
 503 +                return 1;
 504 +        else
 505 +                return 0;
 506 +}
 507 +
 508 +#endif
 509
 510 Index: linux-2.6.23.16/arch/arm/kernel/entry-armv.S
 511 ===================================================================
 512 --- linux-2.6.23.16.orig/arch/arm/kernel/entry-armv.S   2008-03-13 17:46:04.500819685 +0200
 513 +++ linux-2.6.23.16/arch/arm/kernel/entry-armv.S        2008-03-13 17:48:24.508798285 +0200
 514 @@ -18,6 +18,8 @@
 515  #include <asm/memory.h>
 516  #include <asm/glue.h>
 517  #include <asm/vfpmacros.h>
 518 +#include <asm/arch/irqs.h>
 519 +#include <asm/hardware.h>
 520  #include <asm/arch/entry-macro.S>
 521  #include <asm/thread_notify.h>
 522
 523 Index: linux-2.6.23.16/arch/arm/kernel/irq.c
 524 ===================================================================
 525 --- linux-2.6.23.16.orig/arch/arm/kernel/irq.c  2008-03-13 17:46:04.500819685 +0200
 526 +++ linux-2.6.23.16/arch/arm/kernel/irq.c       2008-03-13 17:48:24.508798285 +0200
 527 @@ -40,6 +40,8 @@
 528  #include <asm/system.h>
 529  #include <asm/mach/time.h>
 530
 531 +extern int fixup_irq(unsigned int irq);
 532 +
 533  /*
 534   * No architecture-specific irq_finish function defined in arm/arch/irqs.h.
 535   */
 536 @@ -111,8 +113,11 @@
 537  asmlinkage void __exception asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
 538  {
 539         struct pt_regs *old_regs = set_irq_regs(regs);
 540 -       struct irq_desc *desc = irq_desc + irq;
 541 +//     struct irq_desc *desc = irq_desc + irq;
 542 +       struct irq_desc *desc;
 543
 544 +       irq = fixup_irq(irq);
 545 +       desc = irq_desc + irq;
 546         /*
 547          * Some hardware gives randomly wrong interrupts.  Rather
 548          * than crashing, do something sensible.
 549 Index: linux-2.6.23.16/arch/arm/kernel/process.c
 550 ===================================================================
 551 --- linux-2.6.23.16.orig/arch/arm/kernel/process.c      2008-03-13 17:46:04.500819685 +0200
 552 +++ linux-2.6.23.16/arch/arm/kernel/process.c   2008-03-13 17:48:24.508798285 +0200
 553 @@ -117,7 +117,7 @@
 554  void (*pm_idle)(void);
 555  EXPORT_SYMBOL(pm_idle);
 556
 557 -void (*pm_power_off)(void);
 558 +//void (*pm_power_off)(void);
 559  EXPORT_SYMBOL(pm_power_off);
 560
 561  void (*arm_pm_restart)(char str) = arm_machine_restart;
 562 @@ -188,13 +188,37 @@
 563
 564  void machine_halt(void)
 565  {
 566 +       unsigned int reg_v;
 567 +
 568 +       printk("arch_power_off\n");
 569 +
 570 +       reg_v = readl(IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
 571 +       reg_v &= ~0x00000002;
 572 +       reg_v |= 0x1;
 573 +       mdelay(5);
 574 +       // Power off
 575 +       __raw_writel( reg_v, IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
 576 +
 577  }
 578
 579
 580  void machine_power_off(void)
 581  {
 582 -       if (pm_power_off)
 583 +       unsigned int reg_v;
 584 +
 585 +//     if (pm_power_off)
 586 +       if (&pm_power_off!=NULL)
 587                 pm_power_off();
 588 +
 589 +       printk("arch_power_off\n");
 590 +
 591 +       reg_v = readl(IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
 592 +       reg_v &= ~0x00000002;
 593 +       reg_v |= 0x1;
 594 +       mdelay(5);
 595 +       // Power off
 596 +       __raw_writel( reg_v, IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
 597 +
 598  }
 599
 600  void machine_restart(char * __unused)
 601 Index: linux-2.6.23.16/arch/arm/kernel/time.c
 602 ===================================================================
 603 --- linux-2.6.23.16.orig/arch/arm/kernel/time.c 2008-03-13 17:46:04.500819685 +0200
 604 +++ linux-2.6.23.16/arch/arm/kernel/time.c      2008-03-13 17:48:24.508798285 +0200
 605 @@ -502,8 +502,13 @@
 606
 607  device_initcall(timer_init_sysfs);
 608
 609 +extern unsigned int rtc_get_time_second(void);
 610 +
 611  void __init time_init(void)
 612  {
 613 +#ifdef CONFIG_SL2312_RTC
 614 +       xtime.tv_sec  = rtc_get_time_second() ;
 615 +#endif
 616  #ifndef CONFIG_GENERIC_TIME
 617         if (system_timer->offset == NULL)
 618                 system_timer->offset = dummy_gettimeoffset;
 619 Index: linux-2.6.23.16/arch/arm/mach-sl2312/Kconfig
 620 ===================================================================
 621 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 622 +++ linux-2.6.23.16/arch/arm/mach-sl2312/Kconfig        2008-03-13 17:48:24.508798285 +0200
 623 @@ -0,0 +1,33 @@
 624 +
 625 +menu "SL2312"
 626 +
 627 +config SL3516_ASIC
 628 +       bool "SL3516 ASIC version"
 629 +       depends on ARCH_SL2312
 630 +       help
 631 +         This option to select AISC or FPGA
 632 +config PCI
 633 +       bool "SL2312 PCI"
 634 +       depends on ARCH_SL2312
 635 +       help
 636 +         This option to enable Storlink PCI controller
 637 +
 638 +config SL2312_LPC
 639 +       bool "SL2312 LPC"
 640 +       depends on ARCH_SL2312
 641 +       help
 642 +         This option to enable Low Pin Count controller
 643 +
 644 +config SL2312_USB
 645 +       bool "SL2312 USB"
 646 +       depends on ARCH_SL2312
 647 +       help
 648 +         This option to enable USB OTG host controller
 649 +
 650 +config GEMINI_IPI
 651 +       bool "Gemini IPI test"
 652 +       depends on ARCH_SL2312
 653 +       help
 654 +        Enable this option to test dual cpu Inter-Processor-Interrupt
 655 +endmenu
 656 +
 657 Index: linux-2.6.23.16/arch/arm/mach-sl2312/Makefile
 658 ===================================================================
 659 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 660 +++ linux-2.6.23.16/arch/arm/mach-sl2312/Makefile       2008-03-13 17:48:24.508798285 +0200
 661 @@ -0,0 +1,16 @@
 662 +#
 663 +# Makefile for the linux kernel.
 664 +#
 665 +
 666 +# Object file lists.
 667 +
 668 +obj-y                  := arch.o irq.o mm.o time.o sl3516_device.o
 669 +obj-m                  :=
 670 +obj-n                  :=
 671 +
 672 +
 673 +obj-$(CONFIG_PCI) += pci.o
 674 +obj-$(CONFIG_SL2312_LPC) += lpc.o
 675 +obj-$(CONFIG_SL2312_USB) += sl2312-otg.o # sl2312-otg-1.o
 676 +obj-$(CONFIG_GEMINI_XOR_ACCE) += xor.o
 677 +obj-$(CONFIG_GEMINI_IPI)      += gemini_ipi.o
 678 Index: linux-2.6.23.16/arch/arm/mach-sl2312/Makefile.boot
 679 ===================================================================
 680 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 681 +++ linux-2.6.23.16/arch/arm/mach-sl2312/Makefile.boot  2008-03-13 17:48:24.508798285 +0200
 682 @@ -0,0 +1,5 @@
 683 +   zreladdr-y  := 0x00008000
 684 +params_phys-y  := 0x00508100
 685 +#params_phys-y := 0x00008100
 686 +initrd_phys-y  := 0x00800000
 687 +
 688 Index: linux-2.6.23.16/arch/arm/mach-sl2312/arch.c
 689 ===================================================================
 690 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 691 +++ linux-2.6.23.16/arch/arm/mach-sl2312/arch.c 2008-03-13 17:48:24.508798285 +0200
 692 @@ -0,0 +1,72 @@
 693 +/*
 694 + *  linux/arch/arm/mach-epxa10db/arch.c
 695 + *
 696 + *  Copyright (C) 2000 Deep Blue Solutions Ltd
 697 + *  Copyright (C) 2001 Altera Corporation
 698 + *
 699 + * This program is free software; you can redistribute it and/or modify
 700 + * it under the terms of the GNU General Public License as published by
 701 + * the Free Software Foundation; either version 2 of the License, or
 702 + * (at your option) any later version.
 703 + *
 704 + * This program is distributed in the hope that it will be useful,
 705 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 706 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 707 + * GNU General Public License for more details.
 708 + *
 709 + * You should have received a copy of the GNU General Public License
 710 + * along with this program; if not, write to the Free Software
 711 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 712 + */
 713 +#include <linux/types.h>
 714 +#include <linux/init.h>
 715 +
 716 +#include <asm/hardware.h>
 717 +#include <asm/setup.h>
 718 +#include <asm/mach-types.h>
 719 +#include <asm/mach/time.h>
 720 +#include <asm/mach/arch.h>
 721 +
 722 +extern void sl2312_map_io(void);
 723 +extern void sl2312_init_irq(void);
 724 +extern unsigned long sl2312_gettimeoffset (void);
 725 +extern void __init sl2312_time_init(void);
 726 +
 727 +static struct sys_timer sl2312_timer = {
 728 +       .init           = sl2312_time_init,
 729 +       .offset         = sl2312_gettimeoffset,
 730 +};
 731 +
 732 +static void __init
 733 +sl2312_fixup(struct machine_desc *desc, struct tag *tags,
 734 +                 char **cmdline, struct meminfo *mi)
 735 +{
 736 +        mi->nr_banks      = 1;
 737 +        mi->bank[0].start = 0;
 738 +#ifdef CONFIG_GEMINI_IPI
 739 +        mi->bank[0].size  = (64*1024*1024);  // 128M
 740 +#else
 741 +        mi->bank[0].size  = (128*1024*1024);  // 128M
 742 +#endif
 743 +        mi->bank[0].node  = 0;
 744 +}
 745 +
 746 +/* MACHINE_START(SL2312, "GeminiA")
 747 +       MAINTAINER("Storlink Semi")
 748 +       BOOT_MEM(0x00000000, 0x90000000, 0xf0000000)
 749 +        FIXUP(sl2312_fixup)
 750 +       MAPIO(sl2312_map_io)
 751 +       INITIRQ(sl2312_init_irq)
 752 +       .timer = &sl2312_timer,
 753 +MACHINE_END */
 754 +
 755 +MACHINE_START(SL2312, "GeminiA")
 756 +       /* .phys_ram    = 0x00000000, */
 757 +       .phys_io        = 0x7fffc000,
 758 +       .io_pg_offst    = ((0xffffc000) >> 18) & 0xfffc,
 759 +       .boot_params    = 0x100,
 760 +       .fixup      = sl2312_fixup,
 761 +       .map_io         = sl2312_map_io,
 762 +       .init_irq       = sl2312_init_irq,
 763 +       .timer          = &sl2312_timer,
 764 +MACHINE_END
 765 Index: linux-2.6.23.16/arch/arm/mach-sl2312/gemini_ipi.c
 766 ===================================================================
 767 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 768 +++ linux-2.6.23.16/arch/arm/mach-sl2312/gemini_ipi.c   2008-03-15 16:53:01.339687322 +0200
 769 @@ -0,0 +1,593 @@
 770 +/*
 771 + * FILE NAME sl_cir.c
 772 + *
 773 + * BRIEF MODULE DESCRIPTION
 774 + *  IPI Driver for CPU1.
 775 + *
 776 + *  Author: StorLink, Corp.
 777 + *          Jason Lee
 778 + *
 779 + * Copyright 2002~2006 StorLink, Corp.
 780 + *
 781 + *  This program is free software; you can redistribute  it and/or modify it
 782 + *  under  the terms of  the GNU General  Public License as published by the
 783 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 784 + *  option) any later version.
 785 + *
 786 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 787 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMit8712D  TO, THE IMPLIED WARRANTIES OF
 788 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 789 + *  NO  EVENT  SHALL   THE AUTHOR  BE  LIABLE FOR ANY   DIRECT, INDIRECT,
 790 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 791 + *  NOT LIMit8712D   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 792 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 793 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 794 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 795 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 796 + *
 797 + *  You should have received a copy of the  GNU General Public License along
 798 + *  with this program; if not, writ8712  to the Free Software Foundation, Inc.,
 799 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 800 + */
 801 +
 802 +#include <linux/module.h>
 803 +#include <linux/types.h>
 804 +#include <linux/kernel.h>
 805 +#include <linux/miscdevice.h>
 806 +#include <linux/init.h>
 807 +#include <linux/pagemap.h>
 808 +#include <asm/uaccess.h>
 809 +#include <linux/ioport.h>
 810 +#include <linux/sched.h>
 811 +#include <linux/delay.h>
 812 +#include <linux/fs.h>
 813 +#include <linux/interrupt.h>
 814 +#include <asm/io.h>
 815 +#include <asm/delay.h>
 816 +#include <linux/signal.h>
 817 +#include <asm/arch/sl2312.h>
 818 +#include <asm/arch/int_ctrl.h>
 819 +#include <asm/arch/ipi.h>
 820 +#include <linux/dma-mapping.h>
 821 +
 822 +
 823 +#include <linux/mm.h>
 824 +
 825 +#include <linux/bootmem.h>
 826 +
 827 +#include <asm/hardware.h>
 828 +#include <asm/page.h>
 829 +#include <asm/setup.h>
 830 +#include <asm/pgtable.h>
 831 +#include <asm/pgalloc.h>
 832 +
 833 +#include <asm/mach/map.h>
 834 +
 835 +
 836 +static int sl_ipi_debug = 1 ;
 837 +#define DEB(x)  if(sl_ipi_debug>=1) x
 838 +
 839 +#define SRAM_PTR               IO_ADDRESS(SL2312_SRAM_BASE)
 840 +volatile JSCALE_REQ_T *req=(JSCALE_REQ_T*)SRAM_PTR;
 841 +volatile JSCALE_RSP_T *rsp=(JSCALE_RSP_T*)(SRAM_PTR+0x20);
 842 +
 843 +unsigned int jscale_status=0;
 844 +
 845 +#define JSCALE_WAIT    0
 846 +#define XXXXXX_WAIT    1
 847 +#define MAX_WAIT_Q     8
 848 +wait_queue_head_t gemini_ipi_wait[MAX_WAIT_Q];
 849 +
 850 +#define DRAMCTL_DMA_CTL                0X20
 851 +#define DRAMCTL_DMA_SA         0X24
 852 +#define DRAMCTL_DMA_DA         0X28
 853 +#define DRAMCTL_DMA_CNT                0X2C
 854 +#define MEMCPY_UNIT            0x40000
 855 +int hw_memcpy(const void *to, const void *from, unsigned int bytes)
 856 +{
 857 +       unsigned int reg_a,reg_d;
 858 +       int count = bytes,i=0;
 859 +
 860 +       consistent_sync((unsigned int *)to, bytes, DMA_BIDIRECTIONAL);
 861 +       consistent_sync((unsigned int *)from,bytes, DMA_TO_DEVICE);
 862 +
 863 +       DEB(printk("hwmemcpy:count %d\n",count));
 864 +       while(count>0){
 865 +               // SA
 866 +               reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_SA;
 867 +               reg_d = (unsigned int )__virt_to_phys(from) + i*MEMCPY_UNIT;
 868 +               DEB(printk("hwmemcpy:from 0x%08x\n",reg_d));
 869 +               writel(reg_d,reg_a);
 870 +               // DA
 871 +               reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_DA;
 872 +               reg_d = (unsigned int )__virt_to_phys(to) + i*MEMCPY_UNIT;
 873 +               writel(reg_d,reg_a);
 874 +               DEB(printk("hwmemcpy:to 0x%08x\n",reg_d));
 875 +               // byte count
 876 +               reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_CNT;
 877 +               reg_d = (count>=MEMCPY_UNIT)?MEMCPY_UNIT:count;
 878 +               writel(reg_d,reg_a);
 879 +               // start DMA
 880 +               reg_a = IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_CTL;
 881 +               writel(0x80000001,reg_a);
 882 +
 883 +               do{
 884 +                       cond_resched();
 885 +//                     msleep(4);
 886 +                       reg_d = readl(IO_ADDRESS(SL2312_DRAM_CTRL_BASE)+DRAMCTL_DMA_CTL);
 887 +               }while(reg_d&0x1);
 888 +
 889 +               count -= MEMCPY_UNIT;
 890 +               i++;
 891 +       }
 892 +
 893 +       return bytes;
 894 +}
 895 +
 896 +static irqreturn_t ipi_interrupt()
 897 +{
 898 +       unsigned int id=getcpuid(),tmp;
 899 +
 900 +       //dmac_inv_range(__phys_to_virt(SL2312_SRAM_BASE),__phys_to_virt(SHAREADDR)+0x2000);
 901 +
 902 +
 903 +       // Clear Interrupt
 904 +       if(id==CPU0) {
 905 +               tmp = readl(CPU1_STATUS);
 906 +               tmp &= ~CPU_IPI_BIT_MASK;
 907 +               writel(tmp,CPU1_STATUS);
 908 +       }
 909 +       else{
 910 +               tmp = readl(CPU0_STATUS);
 911 +               tmp &= ~CPU_IPI_BIT_MASK;
 912 +               writel(tmp,CPU0_STATUS);
 913 +       }
 914 +
 915 +       //
 916 +       DEB(printk("ipi interrupt:0x%x\n",rsp->status));
 917 +       switch(rsp->status){
 918 +               case JSCALE_STATUS_OK:
 919 +
 920 +                       break;
 921 +               case JSCALE_UNKNOWN_MSG_TYPE:
 922 +
 923 +                       break;
 924 +               case JSCALE_FAILED_FILE_SIZE:
 925 +
 926 +                       break;
 927 +               case JSCALE_FAILED_MALLOC:
 928 +
 929 +                       break;
 930 +               case JSCALE_FAILED_FORMAT:
 931 +
 932 +                       break;
 933 +               case JSCALE_DECODE_ERROR:
 934 +
 935 +                       break;
 936 +
 937 +       }
 938 +       jscale_status = rsp->status;
 939 +//     wake_up(&gemini_ipi_wait[JSCALE_WAIT]);
 940 +
 941 +       return IRQ_HANDLED;
 942 +}
 943 +
 944 +static int gemini_ipi_open(struct inode *inode, struct file *file)
 945 +{
 946 +       DEB(printk("ipi open\n"));
 947 +       return 0;
 948 +}
 949 +
 950 +
 951 +static int gemini_ipi_release(struct inode *inode, struct file *file)
 952 +{
 953 +       DEB(printk("ipi release\n"));
 954 +       return 0;
 955 +}
 956 +
 957 +
 958 +static int gemini_ipi_ioctl(struct inode *inode, struct file *file,
 959 +       unsigned int cmd, unsigned long arg)
 960 +{
 961 +       JSCALE_RSP_T tmp;
 962 +
 963 +       switch(cmd) {
 964 +               case GEMINI_IPI_JSCALE_REQ:
 965 +                       DEB(printk("ipi:ioctl jscale request %dX%d Q:%d\n",req->ScaledImageWidth,req->ScaledImageHeight,req->ScaledImageQuality));
 966 +                       if (copy_from_user(req, (JSCALE_REQ_T *)arg, sizeof(JSCALE_REQ_T)))
 967 +                               return -EFAULT;
 968 +                       req->hdr.type = IPC_JSCALE_REQ_MSG;
 969 +                       req->hdr.length = sizeof(JSCALE_REQ_T);
 970 +                       req->input_location  = CPU_1_DATA_OFFSET;
 971 +                       req->output_location = CPU_1_DATA_OFFSET;
 972 +                       break;
 973 +               case GEMINI_IPI_JSCALE_STAT:
 974 +                       DEB(printk("ipi:ioctl jscale stat \n"));
 975 +                       if(jscale_status==JSCALE_BUSY){                                         // not yet
 976 +                               tmp.status = JSCALE_BUSY;
 977 +                               if (copy_to_user((JSCALE_RSP_T *)arg,&tmp, sizeof(JSCALE_RSP_T)))
 978 +                                       return -EFAULT;
 979 +                       }
 980 +                       else{                                                                                           // finish or error
 981 +                               if (copy_to_user((JSCALE_RSP_T *)arg,rsp, sizeof(JSCALE_RSP_T)))
 982 +                                       return -EFAULT;
 983 +                       }
 984 +                       break;
 985 +               default:
 986 +                       printk("IPI: Error IOCTL number\n");
 987 +                       return -ENOIOCTLCMD;
 988 +       }
 989 +
 990 +       return 0;
 991 +}
 992 +
 993 +#define SRAM_SIZE      0x2000
 994 +static ssize_t gemini_ipi_write(struct file *file_p, const char *buf, size_t count, loff_t * ppos)
 995 +{
 996 +       int i=0,tmp=0,j;
 997 +       const char *ptr=(unsigned int)__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET);
 998 +       DEB(printk("ipi:write 0x%x to 0x%x length:%d\n",&buf,ptr,count));
 999 +       memcpy(ptr,buf,count);
1000 +       consistent_sync(ptr,count, DMA_TO_DEVICE);
1001 +       //hw_memcpy(ptr,&buf,count);
1002 +
1003 +/*     if(count>SRAM_SIZE){
1004 +               for(i=0;i<(count/SRAM_SIZE);i++)
1005 +                       raid_memcpy(ptr+i*SRAM_SIZE,buf+i*SRAM_SIZE,SRAM_SIZE);
1006 +               if(count%SRAM_SIZE)
1007 +                       raid_memcpy(ptr+i*SRAM_SIZE,buf+i*SRAM_SIZE,count%SRAM_SIZE);
1008 +       }
1009 +       else
1010 +               raid_memcpy(ptr,buf,count);
1011 +*/
1012 +
1013 +/*     for(i=0;i<count;i++){
1014 +               if(buf[i]!=ptr[i])
1015 +                       printk("ipi error:offset %d valud %x[should %x]\n",i,ptr[i],buf[i]);
1016 +       }
1017 +
1018 +       printk("===========input buf===============\n");
1019 +       for(i=0;i<64;i+=16){
1020 +               for(j=0;j<16;j++)
1021 +                       printk("%02x ",buf[i+j]);
1022 +               printk("\n");
1023 +               cond_resched();
1024 +       }
1025 +       printk("===========output buf==============\n");
1026 +       for(i=0;i<64;i+=16){
1027 +               for(j=0;j<16;j++)
1028 +                       printk("%02x ",ptr[i+j]);
1029 +               printk("\n");
1030 +               cond_resched();
1031 +       }
1032 +*/
1033 +       // send irq for CPU1
1034 +       tmp |= CPU_IPI_BIT_MASK;
1035 +       writel(tmp,CPU0_STATUS);
1036 +       jscale_status = JSCALE_BUSY;
1037 +
1038 +       return count;
1039 +}
1040 +
1041 +static ssize_t gemini_ipi_read(struct file * file_p, char *buf, size_t length, loff_t * ppos)
1042 +{
1043 +       int i=0;
1044 +       const char *ptr=(unsigned int )__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET);
1045 +
1046 +       consistent_sync(ptr,length, DMA_FROM_DEVICE);
1047 +       memcpy(buf,ptr,length);
1048 +       DEB(printk("ipi:read 0x%x to 0x%x length:%d\n",ptr,buf,length));
1049 +
1050 +       //consistent_sync((unsigned int *)ptr,0x2000, DMA_FROM_DEVICE);         // invalid
1051 +       //hw_memcpy(buf,ptr,length);
1052 +
1053 +       // need encoded file size ********
1054 +/*     if(count>SRAM_SIZE){
1055 +               for(i=0;i<(count/SRAM_SIZE);i++)
1056 +                       raid_memcpy(buf+i*SRAM_SIZE,p_mbox->message+i*SRAM_SIZE,SRAM_SIZE);
1057 +               if(count%0xFFFF)
1058 +                       raid_memcpy(buf+i*SRAM_SIZE,p_mbox->message+i*SRAM_SIZE,length%SRAM_SIZE);
1059 +       }
1060 +       else
1061 +               raid_memcpy(buf,p_mbox->message,length);
1062 +*/
1063 +       return length;
1064 +}
1065 +
1066 +void do_mapping_read(struct address_space *mapping,
1067 +                            struct file_ra_state *_ra,
1068 +                            struct file *filp,
1069 +                            loff_t *ppos,
1070 +                            read_descriptor_t *desc,
1071 +                            read_actor_t actor)
1072 +{
1073 +       struct inode *inode = mapping->host;
1074 +       unsigned long index;
1075 +       unsigned long end_index;
1076 +       unsigned long offset;
1077 +       unsigned long last_index;
1078 +       unsigned long next_index;
1079 +       unsigned long prev_index;
1080 +       loff_t isize;
1081 +       struct page *cached_page;
1082 +       int error;
1083 +       struct file_ra_state ra = *_ra;
1084 +
1085 +       cached_page = NULL;
1086 +       index = *ppos >> PAGE_CACHE_SHIFT;
1087 +       next_index = index;
1088 +       prev_index = ra.prev_page;
1089 +       last_index = (*ppos + desc->count + PAGE_CACHE_SIZE-1) >> PAGE_CACHE_SHIFT;
1090 +       offset = *ppos & ~PAGE_CACHE_MASK;
1091 +
1092 +       isize = i_size_read(inode);
1093 +       if (!isize)
1094 +               goto out;
1095 +
1096 +       end_index = (isize - 1) >> PAGE_CACHE_SHIFT;
1097 +       for (;;) {
1098 +               struct page *page;
1099 +               unsigned long nr, ret;
1100 +
1101 +               /* nr is the maximum number of bytes to copy from this page */
1102 +               nr = PAGE_CACHE_SIZE;
1103 +               if (index >= end_index) {
1104 +                       if (index > end_index)
1105 +                               goto out;
1106 +                       nr = ((isize - 1) & ~PAGE_CACHE_MASK) + 1;
1107 +                       if (nr <= offset) {
1108 +                               goto out;
1109 +                       }
1110 +               }
1111 +               nr = nr - offset;
1112 +
1113 +               cond_resched();
1114 +               if (index == next_index)
1115 +                       next_index = page_cache_readahead(mapping, &ra, filp,
1116 +                                       index, last_index - index);
1117 +
1118 +find_page:
1119 +               page = find_get_page(mapping, index);
1120 +               if (unlikely(page == NULL)) {
1121 +                       handle_ra_miss(mapping, &ra, index);
1122 +                       goto no_cached_page;
1123 +               }
1124 +               if (!PageUptodate(page))
1125 +                       goto page_not_up_to_date;
1126 +page_ok:
1127 +
1128 +               /* If users can be writing to this page using arbitrary
1129 +                * virtual addresses, take care about potential aliasing
1130 +                * before reading the page on the kernel side.
1131 +                */
1132 +               if (mapping_writably_mapped(mapping))
1133 +                       flush_dcache_page(page);
1134 +
1135 +               /*
1136 +                * When (part of) the same page is read multiple times
1137 +                * in succession, only mark it as accessed the first time.
1138 +                */
1139 +               if (prev_index != index)
1140 +                       mark_page_accessed(page);
1141 +               prev_index = index;
1142 +
1143 +               /*
1144 +                * Ok, we have the page, and it's up-to-date, so
1145 +                * now we can copy it to user space...
1146 +                *
1147 +                * The actor routine returns how many bytes were actually used..
1148 +                * NOTE! This may not be the same as how much of a user buffer
1149 +                * we filled up (we may be padding etc), so we can only update
1150 +                * "pos" here (the actor routine has to update the user buffer
1151 +                * pointers and the remaining count).
1152 +                */
1153 +               ret = actor(desc, page, offset, nr);
1154 +               offset += ret;
1155 +               index += offset >> PAGE_CACHE_SHIFT;
1156 +               offset &= ~PAGE_CACHE_MASK;
1157 +
1158 +               page_cache_release(page);
1159 +               if (ret == nr && desc->count)
1160 +                       continue;
1161 +               goto out;
1162 +
1163 +page_not_up_to_date:
1164 +               /* Get exclusive access to the page ... */
1165 +               lock_page(page);
1166 +
1167 +               /* Did it get unhashed before we got the lock? */
1168 +               if (!page->mapping) {
1169 +                       unlock_page(page);
1170 +                       page_cache_release(page);
1171 +                       continue;
1172 +               }
1173 +
1174 +               /* Did somebody else fill it already? */
1175 +               if (PageUptodate(page)) {
1176 +                       unlock_page(page);
1177 +                       goto page_ok;
1178 +               }
1179 +
1180 +readpage:
1181 +               /* Start the actual read. The read will unlock the page. */
1182 +               error = mapping->a_ops->readpage(filp, page);
1183 +
1184 +               if (unlikely(error))
1185 +                       goto readpage_error;
1186 +
1187 +               if (!PageUptodate(page)) {
1188 +                       lock_page(page);
1189 +                       if (!PageUptodate(page)) {
1190 +                               if (page->mapping == NULL) {
1191 +                                       /*
1192 +                                        * invalidate_inode_pages got it
1193 +                                        */
1194 +                                       unlock_page(page);
1195 +                                       page_cache_release(page);
1196 +                                       goto find_page;
1197 +                               }
1198 +                               unlock_page(page);
1199 +                               error = -EIO;
1200 +                               goto readpage_error;
1201 +                       }
1202 +                       unlock_page(page);
1203 +               }
1204 +
1205 +               /*
1206 +                * i_size must be checked after we have done ->readpage.
1207 +                *
1208 +                * Checking i_size after the readpage allows us to calculate
1209 +                * the correct value for "nr", which means the zero-filled
1210 +                * part of the page is not copied back to userspace (unless
1211 +                * another truncate extends the file - this is desired though).
1212 +                */
1213 +               isize = i_size_read(inode);
1214 +               end_index = (isize - 1) >> PAGE_CACHE_SHIFT;
1215 +               if (unlikely(!isize || index > end_index)) {
1216 +                       page_cache_release(page);
1217 +                       goto out;
1218 +               }
1219 +
1220 +               /* nr is the maximum number of bytes to copy from this page */
1221 +               nr = PAGE_CACHE_SIZE;
1222 +               if (index == end_index) {
1223 +                       nr = ((isize - 1) & ~PAGE_CACHE_MASK) + 1;
1224 +                       if (nr <= offset) {
1225 +                               page_cache_release(page);
1226 +                               goto out;
1227 +                       }
1228 +               }
1229 +               nr = nr - offset;
1230 +               goto page_ok;
1231 +
1232 +readpage_error:
1233 +               /* UHHUH! A synchronous read error occurred. Report it */
1234 +               desc->error = error;
1235 +               page_cache_release(page);
1236 +               goto out;
1237 +
1238 +no_cached_page:
1239 +               /*
1240 +                * Ok, it wasn't cached, so we need to create a new
1241 +                * page..
1242 +                */
1243 +               if (!cached_page) {
1244 +                       cached_page = page_cache_alloc_cold(mapping);
1245 +                       if (!cached_page) {
1246 +                               desc->error = -ENOMEM;
1247 +                               goto out;
1248 +                       }
1249 +               }
1250 +               error = add_to_page_cache_lru(cached_page, mapping,
1251 +                                               index, GFP_KERNEL);
1252 +               if (error) {
1253 +                       if (error == -EEXIST)
1254 +                               goto find_page;
1255 +                       desc->error = error;
1256 +                       goto out;
1257 +               }
1258 +               page = cached_page;
1259 +               cached_page = NULL;
1260 +               goto readpage;
1261 +       }
1262 +
1263 +out:
1264 +       *_ra = ra;
1265 +
1266 +       *ppos = ((loff_t) index << PAGE_CACHE_SHIFT) + offset;
1267 +       if (cached_page)
1268 +               page_cache_release(cached_page);
1269 +       if (filp)
1270 +               file_accessed(filp);
1271 +}
1272 +
1273 +int ipi_send_actor(read_descriptor_t * desc, struct page *page, unsigned long offset, unsigned long size)
1274 +{
1275 +       ssize_t written;
1276 +       unsigned long count = desc->count;
1277 +       struct file *file = desc->arg.data;
1278 +       unsigned int *ptr_to=(unsigned int)__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET) + desc->written;
1279 +       void *ptr_from;
1280 +
1281 +       if (size > count)
1282 +               size = count;
1283 +
1284 +       ptr_from = page_address(page)+offset;
1285 +       written = memcpy(ptr_to,ptr_from,size);
1286 +
1287 +       if (written < 0) {
1288 +               desc->error = written;
1289 +               written = 0;
1290 +       }
1291 +       desc->count = count - written;
1292 +       desc->written += written;
1293 +       return written;
1294 +}
1295 +
1296 +ssize_t gemini_ipi_sendfile(struct file *in_file, loff_t *ppos,
1297 +                        size_t count, read_actor_t actor, void *TARGET)
1298 +{
1299 +       read_descriptor_t desc;
1300 +
1301 +       if (!count)
1302 +               return 0;
1303 +
1304 +       desc.written = 0;
1305 +       desc.count = count;
1306 +       desc.arg.data = TARGET;
1307 +       desc.error = 0;
1308 +
1309 +       do_mapping_read(in_file->f_mapping,&in_file->f_ra,in_file, ppos, &desc, ipi_send_actor);
1310 +
1311 +       if (desc.written)
1312 +               return desc.written;
1313 +       return desc.error;
1314 +}
1315 +static struct file_operations gemini_ipi_fops = {
1316 +       .owner  =       THIS_MODULE,
1317 +       .ioctl  =       gemini_ipi_ioctl,
1318 +       .open   =       gemini_ipi_open,
1319 +       .release=       gemini_ipi_release,
1320 +       .write  =       gemini_ipi_write,
1321 +       .read   =       gemini_ipi_read,
1322 +       .sendfile = gemini_ipi_sendfile,
1323 +};
1324 +
1325 +#ifndef STORLINK_IPI
1326 +#define STORLINK_IPI   242             // Documents/devices.txt suggest to use 240~255 for local driver!!
1327 +#endif
1328 +
1329 +static struct miscdevice gemini_ipi_miscdev =
1330 +{
1331 +       STORLINK_IPI,
1332 +       "slave_ipc",
1333 +       &gemini_ipi_fops
1334 +};
1335 +
1336 +int __init sl_ipi_init(void)
1337 +{
1338 +
1339 +       printk("Gemini IPI Driver Initialization...\n");
1340 +       printk("REQ Head :0x%x(phy:0x%x)\n",(unsigned int)req,(unsigned int)SL2312_SRAM_BASE);
1341 +       printk("RSP Head :0x%x(phy:0x%x)\n",(unsigned int)rsp,(unsigned int)SL2312_SRAM_BASE+0x20);
1342 +       printk("Data buff:0x%x(phy:0x%x)\n",__phys_to_virt(CPU_1_MEM_BASE+CPU_1_DATA_OFFSET),CPU_1_MEM_BASE+CPU_1_DATA_OFFSET);
1343 +
1344 +       misc_register(&gemini_ipi_miscdev);
1345 +
1346 +       if (request_irq(IRQ_CPU0_IP_IRQ_OFFSET, ipi_interrupt, SA_INTERRUPT, "ipi", NULL))
1347 +               printk("Error: Register IRQ for Storlink IPI failed\n");
1348 +
1349 +       return 0;
1350 +}
1351 +
1352 +void __exit sl_ipi_exit(void)
1353 +{
1354 +
1355 +}
1356 +
1357 +module_init(sl_ipi_init);
1358 +module_exit(sl_ipi_exit);
1359 +
1360 +MODULE_AUTHOR("Jason Lee <jason@storlink.com.tw>");
1361 +MODULE_DESCRIPTION("Storlink IPI driver");
1362 +MODULE_LICENSE("GPL");
1363 Index: linux-2.6.23.16/arch/arm/mach-sl2312/hw_xor.h
1364 ===================================================================
1365 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1366 +++ linux-2.6.23.16/arch/arm/mach-sl2312/hw_xor.h       2008-03-13 17:48:24.508798285 +0200
1367 @@ -0,0 +1,573 @@
1368 +/*
1369 +*  linux/include/asm-arm/xor.h
1370 +*
1371 +*  Copyright (C) 2001 Storlink Semi.
1372 +*      Jason Lee <jason@storlink.com.tw>
1373 +*
1374 +*/
1375 +#include <asm/arch/sl2312.h>
1376 +#include <asm/io.h>
1377 +//#include <linux/compatmac.h>
1378 +
1379 +#undef BIG_ENDIAN
1380 +#define CPU            0
1381 +#define DMA            1
1382 +
1383 +#define DESC_NO        8
1384 +#define TX_DESC_NUM            DESC_NO
1385 +#define RX_DESC_NUM            DESC_NO
1386 +
1387 +#define RAID_BASE_ADDR IO_ADDRESS(SL2312_RAID_BASE)
1388 +
1389 +#define SRAM_PAR_0k            0
1390 +#define SRAM_PAR_4k            1
1391 +#define SRAM_PAR_8k            2
1392 +#define SRAM_PAR_16k           3
1393 +#define SRAM_PAR_SIZE  SRAM_PAR_8k
1394 +
1395 +#define RUNNING                0x1
1396 +#define COMPLETE       0x2
1397 +#define ERROR          0x4
1398 +
1399 +#define CMD_XOR                0x0
1400 +#define CMD_FILL       0x1
1401 +#define CMD_CPY                0x3
1402 +#define CMD_CHK                0x4
1403 +
1404 +enum RAID_DMA_REGISTER {
1405 +       RAID_DMA_DEVICE_ID              = 0xff00,
1406 +       RAID_DMA_STATUS                 = 0xff04,
1407 +       RAID_FCHDMA_CTRL                = 0xff08,
1408 +       RAID_FCHDMA_FIRST_DESC  = 0xff0C,
1409 +       RAID_FCHDMA_CURR_DESC   = 0xff10,
1410 +       RAID_STRDMA_CTRL                = 0xff14,
1411 +       RAID_STRDMA_FIRST_DESC  = 0xff18,
1412 +       RAID_STRDMA_CURR_DESC   = 0xff1C,
1413 +       RAID_TX_FLG_REG                 = 0xff24,
1414 +       RAID_RX_FLG_REG                 = 0xff34,
1415 +       RAID_PCR                                = 0xff50,
1416 +       SMC_CMD_REG                             = 0xff60,
1417 +       SMC_STATUS_REG                  = 0xff64
1418 +       };
1419 +
1420 +enum RAID_FUNC_MODE {
1421 +       RAID_XOR                        = 0,
1422 +       RAID_MIX                        = 2,
1423 +       RAID_SRAM                       = 3,
1424 +       RAID_ENDIAN                     = 4,
1425 +       RAID_MEM_BLK            = 5,
1426 +       RAID_MEM2MEM            = 7,
1427 +       RAID_BUF_SIZE           = 8,
1428 +       RAID_ERR_TEST           = 9,
1429 +       RAID_BURST                      = 10,
1430 +       RAID_BUS                        = 11
1431 +       };
1432 +
1433 +typedef struct reg_info {
1434 +       int mask;
1435 +       char err[32];
1436 +       int offset;
1437 +} REG_INFO;
1438 +
1439 +/********************************************************/
1440 +/*     the definition of RAID DMA Module Register      */
1441 +/********************************************************/
1442 +typedef union
1443 +{
1444 +       unsigned int bit32;
1445 +       struct bits_ff00
1446 +       {
1447 +               #ifdef BIG_ENDIAN
1448 +               unsigned int                            : 8;
1449 +               unsigned int teytPerr           : 4; /* define protocol error under tsPErrI*/
1450 +               unsigned int reytPerr           : 14; /* define protocol error under rsPErrI */
1451 +               unsigned int device_id          : 12;
1452 +               unsigned int revision_id        : 4;
1453 +               #else
1454 +               unsigned int revision_id        : 4;
1455 +               unsigned int device_id          : 12;
1456 +               unsigned int reytPerr           : 14; /* define protocol error under rsPErrI */
1457 +               unsigned int teytPerr           : 4; /* define protocol error under tsPErrI*/
1458 +               unsigned int                            : 8;
1459 +               #endif
1460 +       } bits;
1461 +} RAID_DMA_DEVICE_ID_T;
1462 +
1463 +typedef union
1464 +{
1465 +       unsigned int bits32;
1466 +       struct bits_ff04
1467 +       {
1468 +               #ifdef BIG_ENDIAN
1469 +               unsigned int tsFinishI          : 1; /* owner bit error interrupt */
1470 +               unsigned int tsDErrI            : 1; /* AHB bus error interrupt */
1471 +               unsigned int tsPErrI            : 1; /* RAID XOR fetch descriptor protocol error interrupt */
1472 +               unsigned int tsEODI                     : 1; /* RAID XOR fetch DMA end of descriptor interrupt */
1473 +               unsigned int tsEOFI                     : 1; /* RAID XOR fetch DMA end of frame interrupt */
1474 +               unsigned int rsFinishI          : 1; /* owner bit error interrupt */
1475 +               unsigned int rsDErrI            : 1; /* AHB bus error while RAID XOR store interrupt */
1476 +               unsigned int rsPErrI            : 1; /* RAID XOR store descriptor protocol error interrupt */
1477 +               unsigned int rsEODI                     : 1; /* RAID XOR store DMA end of descriptor interrupt */
1478 +               unsigned int rsEOFI                     : 1; /* RAID XOR store DMA end of frame interrupt */
1479 +               unsigned int inter                      : 8; /* pattern check error interrupt */
1480 +               unsigned int                            : 5;
1481 +               unsigned int Loopback           : 1; /* loopback */
1482 +               unsigned int intEnable          : 8; /*pattern check error interrupt enable */
1483 +               #else
1484 +               unsigned int intEnable          : 8; /*pattern check error interrupt enable */
1485 +               unsigned int Loopback           : 1; /* loopback */
1486 +               unsigned int                            : 5;
1487 +               unsigned int inter                      : 8; /* pattern check error interrupt */
1488 +               unsigned int rsEOFI                     : 1; /* RAID XOR store DMA end of frame interrupt */
1489 +               unsigned int rsEODI                     : 1; /* RAID XOR store DMA end of descriptor interrupt */
1490 +               unsigned int rsPErrI            : 1; /* RAID XOR store descriptor protocol error interrupt */
1491 +               unsigned int rsDErrI            : 1; /* AHB bus error while RAID XOR store interrupt */
1492 +               unsigned int rsFinishI          : 1; /* owner bit error interrupt */
1493 +               unsigned int tsEOFI                     : 1; /* RAID XOR fetch DMA end of frame interrupt */
1494 +               unsigned int tsEODI                     : 1; /* RAID XOR fetch DMA end of descriptor interrupt */
1495 +               unsigned int tsPErrI            : 1; /* RAID XOR fetch descriptor protocol error interrupt */
1496 +               unsigned int tsDErrI            : 1; /* AHB bus error interrupt */
1497 +               unsigned int tsFinishI          : 1; /* owner bit error interrupt */
1498 +               #endif
1499 +       } bits;
1500 +} RAID_DMA_STATUS_T;
1501 +
1502 +
1503 +typedef union
1504 +{
1505 +       unsigned int bits32;
1506 +       struct bits_ff08
1507 +       {
1508 +               #ifdef BIG_ENDIAN
1509 +               unsigned int td_start           :  1;   /* Start DMA transfer */
1510 +               unsigned int td_continue        :  1;   /* Continue DMA operation */
1511 +               unsigned int td_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
1512 +               unsigned int                            :  1;
1513 +               unsigned int td_prot            :  4;   /* DMA protection control */
1514 +               unsigned int td_burst_size  :  2;       /* DMA max burst size for every AHB request */
1515 +               unsigned int td_bus                 :  2;       /* peripheral bus width */
1516 +               unsigned int td_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
1517 +               unsigned int td_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
1518 +               unsigned int td_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
1519 +               unsigned int td_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
1520 +               unsigned int td_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
1521 +               unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
1522 +               unsigned int                            : 14;
1523 +               #else
1524 +               unsigned int                            : 14;
1525 +               unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
1526 +               unsigned int td_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
1527 +               unsigned int td_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
1528 +               unsigned int td_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
1529 +               unsigned int td_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
1530 +               unsigned int td_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
1531 +               unsigned int td_bus                 :  2;       /* peripheral bus width;0 - 8 bits;1 - 16 bits */
1532 +               unsigned int td_burst_size  :  2;       /* TxDMA max burst size for every AHB request */
1533 +               unsigned int td_prot            :  4;   /* TxDMA protection control */
1534 +               unsigned int                            :  1;
1535 +               unsigned int td_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
1536 +               unsigned int td_continue        :  1;   /* Continue DMA operation */
1537 +               unsigned int td_start           :  1;   /* Start DMA transfer */
1538 +               #endif
1539 +       } bits;
1540 +} RAID_TXDMA_CTRL_T;
1541 +
1542 +typedef union
1543 +{
1544 +       unsigned int bits32;
1545 +       struct bits_ff0c
1546 +       {
1547 +               #ifdef BIG_ENDIAN
1548 +               unsigned int td_first_des_ptr   : 28;/* first descriptor address */
1549 +               unsigned int td_busy                    :  1;/* 1-TxDMA busy; 0-TxDMA idle */
1550 +               unsigned int                                    :  3;
1551 +               #else
1552 +               unsigned int                                    :  3;
1553 +               unsigned int td_busy                    :  1;/* 1-TxDMA busy; 0-TxDMA idle */
1554 +               unsigned int td_first_des_ptr   : 28;/* first descriptor address */
1555 +               #endif
1556 +       } bits;
1557 +} RAID_TXDMA_FIRST_DESC_T;
1558 +
1559 +typedef union
1560 +{
1561 +       unsigned int bits32;
1562 +       struct bits_ff10
1563 +       {
1564 +               #ifdef BIG_ENDIAN
1565 +               unsigned int ndar                       : 28;   /* next descriptor address */
1566 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
1567 +               unsigned int                            :  1;
1568 +               unsigned int sof_eof            :  2;
1569 +               #else
1570 +               unsigned int sof_eof            :  2;
1571 +               unsigned int                            :  1;
1572 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
1573 +               unsigned int ndar                       : 28;   /* next descriptor address */
1574 +               #endif
1575 +       } bits;
1576 +} RAID_TXDMA_CURR_DESC_T;
1577 +
1578 +typedef union
1579 +{
1580 +       unsigned int bits32;
1581 +       struct bits_ff14
1582 +       {
1583 +               #ifdef BIG_ENDIAN
1584 +               unsigned int rd_start           :  1;   /* Start DMA transfer */
1585 +               unsigned int rd_continue        :  1;   /* Continue DMA operation */
1586 +               unsigned int rd_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
1587 +               unsigned int                            :  1;
1588 +               unsigned int rd_prot            :  4;   /* DMA protection control */
1589 +               unsigned int rd_burst_size  :  2;       /* DMA max burst size for every AHB request */
1590 +               unsigned int rd_bus                 :  2;       /* peripheral bus width;0 - 8 bits;1 - 16 bits */
1591 +               unsigned int rd_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
1592 +               unsigned int rd_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
1593 +               unsigned int rd_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
1594 +               unsigned int rd_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
1595 +               unsigned int rd_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
1596 +               unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
1597 +               unsigned int                            : 14;
1598 +               #else
1599 +               unsigned int                            : 14;
1600 +               unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
1601 +               unsigned int rd_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
1602 +               unsigned int rd_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
1603 +               unsigned int rd_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
1604 +               unsigned int rd_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
1605 +               unsigned int rd_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
1606 +               unsigned int rd_bus                 :  2;       /* peripheral bus width;0 - 8 bits;1 - 16 bits */
1607 +               unsigned int rd_burst_size  :  2;       /* DMA max burst size for every AHB request */
1608 +               unsigned int rd_prot            :  4;   /* DMA protection control */
1609 +               unsigned int                            :  1;
1610 +               unsigned int rd_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
1611 +               unsigned int rd_continue        :  1;   /* Continue DMA operation */
1612 +               unsigned int rd_start           :  1;   /* Start DMA transfer */
1613 +               #endif
1614 +       } bits;
1615 +} RAID_RXDMA_CTRL_T;
1616 +
1617 +typedef union
1618 +{
1619 +       unsigned int bits32;
1620 +       struct bits_ff18
1621 +       {
1622 +               #ifdef BIG_ENDIAN
1623 +               unsigned int rd_first_des_ptr   : 28;/* first descriptor address */
1624 +               unsigned int rd_busy                    :  1;/* 1-RxDMA busy; 0-RxDMA idle */
1625 +               unsigned int                                    :  3;
1626 +               #else
1627 +               unsigned int                                    :  3;
1628 +               unsigned int rd_busy                    :  1;/* 1-RxDMA busy; 0-RxDMA idle */
1629 +               unsigned int rd_first_des_ptr   : 28;/* first descriptor address */
1630 +               #endif
1631 +       } bits;
1632 +} RAID_RXDMA_FIRST_DESC_T;
1633 +
1634 +typedef union
1635 +{
1636 +       unsigned int bits32;
1637 +       struct bits_ff1c
1638 +       {
1639 +               #ifdef BIG_ENDIAN
1640 +               unsigned int ndar                       : 28;   /* next descriptor address */
1641 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
1642 +               unsigned int dec                        :  1;   /* AHB bus address increment(0)/decrement(1) */
1643 +               unsigned int sof_eof            :  2;
1644 +               #else
1645 +               unsigned int sof_eof            :  2;
1646 +               unsigned int dec                        :  1;   /* AHB bus address increment(0)/decrement(1) */
1647 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
1648 +               unsigned int ndar                       : 28;   /* next descriptor address */
1649 +               #endif
1650 +       } bits;
1651 +} RAID_RXDMA_CURR_DESC_T;
1652 +
1653 +typedef union
1654 +{
1655 +       unsigned int bit32;
1656 +       struct bits_ff50
1657 +       {
1658 +               unsigned int pat                        : 32; /* data for pattern check */
1659 +       } bits;
1660 +} RAID_PACR_T;
1661 +
1662 +/******************************************************/
1663 +/*     the definition of DMA Descriptor Register     */
1664 +/******************************************************/
1665 +typedef struct raid_descriptor_t
1666 +{
1667 +       union func_ctrl_t
1668 +       {
1669 +               unsigned int bit32;
1670 +               struct bits_0000
1671 +               {
1672 +                       #ifdef BIG_ENDIAN
1673 +                       unsigned int own                                : 1; /* owner bit */
1674 +                       unsigned int derr                               : 1;    /* data error during processing this descriptor */
1675 +                       unsigned int perr                               : 1;    /* protocol error during processing this descriptor */
1676 +                       unsigned int raid_ctrl_status   : 7; /* pass RAID XOR fetch/store control status to CPU */
1677 +                       unsigned int desc_cnt                   : 6;
1678 +                       unsigned int buffer_size                : 16;   /* transfer buffer size associated with current description*/
1679 +                       #else
1680 +                       unsigned int buffer_size                : 16;   /* transfer buffer size associated with current description*/
1681 +                       unsigned int desc_cnt                   : 6;
1682 +                       unsigned int raid_ctrl_status   : 7; /* pass RAID XOR fetch/store control status to CPU */
1683 +                       unsigned int perr                               : 1;    /* protocol error during processing this descriptor */
1684 +                       unsigned int derr                               : 1;    /* data error during processing this descriptor */
1685 +                       unsigned int own                                : 1; /* owner bit */
1686 +                       #endif
1687 +               } bits;
1688 +       } func_ctrl;
1689 +
1690 +       union flg_status_t
1691 +       {
1692 +               unsigned int bits32;
1693 +               struct bit_004
1694 +               {
1695 +                       #ifdef BIG_ENDIAN
1696 +                       unsigned int bcc                : 16;
1697 +                       unsigned int                    : 13
1698 +                       unsigned int mode               : 3;
1699 +                       #else
1700 +                       unsigned int mode               : 3;
1701 +                       unsigned int                    : 13;
1702 +                       unsigned int bcc                : 16;
1703 +                       #endif
1704 +               } bits_cmd_status;
1705 +       } flg_status;  //Sanders
1706 +
1707 +       unsigned int buf_addr;
1708 +
1709 +       union next_desc_addr_t
1710 +       {
1711 +               unsigned int bits32;
1712 +               struct bits_000c
1713 +               {
1714 +                       #ifdef BIG_ENDIAN
1715 +                       unsigned int ndar               : 28; /* next descriptor address */
1716 +                       unsigned int eofie              : 1; /* end of frame interrupt enable */
1717 +                       unsigned int                    : 1;
1718 +                       unsigned int sof_eof    : 2; /* the position of the descriptor in chain */
1719 +                       #else
1720 +                       unsigned int sof_eof    : 2; /* the position of the descriptor in chain */
1721 +                       unsigned int                    : 1;
1722 +                       unsigned int eofie              : 1; /* end of frame interrupt enable */
1723 +                       unsigned int ndar               : 28; /* next descriptor address */
1724 +                       #endif
1725 +               } bits;
1726 +       } next_desc_addr;
1727 +} RAID_DESCRIPTOR_T;
1728 +
1729 +/******************************************************/
1730 +/*     the offset of RAID SMC register               */
1731 +/******************************************************/
1732 +enum RAID_SMC_REGISTER {
1733 +       RAID_SMC_CMD_REG                = 0xff60,
1734 +       RAID_SMC_STATUS_REG             = 0xff64
1735 +       };
1736 +
1737 +/******************************************************/
1738 +/*     the definition of RAID SMC module register    */
1739 +/******************************************************/
1740 +typedef union
1741 +{
1742 +       unsigned int bits32;
1743 +       struct bits_ff60
1744 +       {
1745 +               #ifdef BIG_ENDIAN
1746 +               unsigned int pat_mode           : 2; /* partition mode selection */
1747 +               unsigned int                            : 14;
1748 +               unsigned int device_id          : 12;
1749 +               unsigned int revision_id        : 4;
1750 +               #else
1751 +               unsigned int revision_id        : 4;
1752 +               unsigned int device_id          : 12;
1753 +               unsigned int                            : 14;
1754 +               unsigned int pat_mode           : 2; /* partition mode selection */
1755 +               #endif
1756 +       } bits;
1757 +} RAID_SMC_CMD;
1758 +
1759 +typedef union
1760 +{
1761 +       unsigned int bits32;
1762 +       struct bits_ff64
1763 +       {
1764 +               #ifdef BIG_ENDIAN
1765 +               unsigned int addr_err1          : 1; /* address is out of range for controller 1 */
1766 +               unsigned int ahb_err1           : 1; /* AHB bus error for controller 1 */
1767 +               unsigned int                            : 14;
1768 +               unsigned int addr_err2          : 1;    /* address is out of range for controller 2 */
1769 +               unsigned int ahb_err2           : 1; /* AHB bus error for controller 2 */
1770 +               unsigned int                            : 14;
1771 +               #else
1772 +               unsigned int                            : 14;
1773 +               unsigned int ahb_err2           : 1; /* AHB bus error for controller 2 */
1774 +               unsigned int addr_err2          : 1;    /* address is out of range for controller 2 */
1775 +               unsigned int                            : 14;
1776 +               unsigned int ahb_err1           : 1; /* AHB bus error for controller 1 */
1777 +               unsigned int addr_err1          : 1; /* address is out of range for controller 1 */
1778 +               #endif
1779 +       } bits;
1780 +} RAID_SMC_STATUS;
1781 +
1782 +typedef struct RAID_S
1783 +{
1784 +       const char *device_name;
1785 +       wait_queue_head_t wait;
1786 +       unsigned int busy;
1787 +       int irq;
1788 +       unsigned int status;
1789 +       RAID_DESCRIPTOR_T *tx_desc;  /*   point to virtual TX descriptor address */
1790 +       RAID_DESCRIPTOR_T *rx_desc;  /* point ot virtual RX descriptor address */
1791 +       RAID_DESCRIPTOR_T *tx_cur_desc; /* current TX descriptor */
1792 +       RAID_DESCRIPTOR_T *rx_cur_desc; /* current RX descriptor */
1793 +       RAID_DESCRIPTOR_T *tx_finished_desc;
1794 +       RAID_DESCRIPTOR_T *rx_finished_desc;
1795 +       RAID_DESCRIPTOR_T *tx_first_desc;
1796 +       RAID_DESCRIPTOR_T *rx_first_desc;
1797 +
1798 +//     unsigned int *tx_buf[TX_DESC_NUM];
1799 +       unsigned int *rx_desc_dma;                      // physical address of rx_descript
1800 +       unsigned int *tx_desc_dma;                      // physical address of tx_descript
1801 +       unsigned int *rx_bufs_dma;
1802 +       unsigned int *tx_bufs_dma;
1803 +
1804 +} RAID_T;
1805 +
1806 +struct reg_ioctl
1807 +{
1808 +       unsigned int reg_addr;
1809 +       unsigned int val_in;
1810 +       unsigned int val_out;
1811 +};
1812 +
1813 +typedef struct dma_ctrl {
1814 +       int sram;
1815 +       int prot;
1816 +       int burst;
1817 +       int bus;
1818 +       int endian;
1819 +       int mode;
1820 +} DMA_CTRL;
1821 +
1822 +
1823 +#ifdef XOR_SW_FILL_IN
1824 +
1825 +#define __XOR(a1, a2) a1 ^= a2
1826 +
1827 +#define GET_BLOCK_2(dst) \
1828 +       __asm__("ldmia  %0, {%1, %2}" \
1829 +               : "=r" (dst), "=r" (a1), "=r" (a2) \
1830 +               : "0" (dst))
1831 +
1832 +#define GET_BLOCK_4(dst) \
1833 +       __asm__("ldmia  %0, {%1, %2, %3, %4}" \
1834 +               : "=r" (dst), "=r" (a1), "=r" (a2), "=r" (a3), "=r" (a4) \
1835 +               : "0" (dst))
1836 +
1837 +#define XOR_BLOCK_2(src) \
1838 +       __asm__("ldmia  %0!, {%1, %2}" \
1839 +               : "=r" (src), "=r" (b1), "=r" (b2) \
1840 +               : "0" (src)); \
1841 +       __XOR(a1, b1); __XOR(a2, b2);
1842 +
1843 +#define XOR_BLOCK_4(src) \
1844 +       __asm__("ldmia  %0!, {%1, %2, %3, %4}" \
1845 +               : "=r" (src), "=r" (b1), "=r" (b2), "=r" (b3), "=r" (b4) \
1846 +               : "0" (src)); \
1847 +       __XOR(a1, b1); __XOR(a2, b2); __XOR(a3, b3); __XOR(a4, b4)
1848 +
1849 +#define PUT_BLOCK_2(dst) \
1850 +       __asm__ __volatile__("stmia     %0!, {%2, %3}" \
1851 +               : "=r" (dst) \
1852 +               : "0" (dst), "r" (a1), "r" (a2))
1853 +
1854 +#define PUT_BLOCK_4(dst) \
1855 +       __asm__ __volatile__("stmia     %0!, {%2, %3, %4, %5}" \
1856 +               : "=r" (dst) \
1857 +               : "0" (dst), "r" (a1), "r" (a2), "r" (a3), "r" (a4))
1858 +
1859 +static void
1860 +xor_arm4regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
1861 +{
1862 +       unsigned int lines = bytes / sizeof(unsigned long) / 4;
1863 +       register unsigned int a1 __asm__("r4");
1864 +       register unsigned int a2 __asm__("r5");
1865 +       register unsigned int a3 __asm__("r6");
1866 +       register unsigned int a4 __asm__("r7");
1867 +       register unsigned int b1 __asm__("r8");
1868 +       register unsigned int b2 __asm__("r9");
1869 +       register unsigned int b3 __asm__("ip");
1870 +       register unsigned int b4 __asm__("lr");
1871 +
1872 +       do {
1873 +               GET_BLOCK_4(p1);
1874 +               XOR_BLOCK_4(p2);
1875 +               PUT_BLOCK_4(p1);
1876 +       } while (--lines);
1877 +}
1878 +
1879 +static void
1880 +xor_arm4regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
1881 +               unsigned long *p3)
1882 +{
1883 +       unsigned int lines = bytes / sizeof(unsigned long) / 4;
1884 +       register unsigned int a1 __asm__("r4");
1885 +       register unsigned int a2 __asm__("r5");
1886 +       register unsigned int a3 __asm__("r6");
1887 +       register unsigned int a4 __asm__("r7");
1888 +       register unsigned int b1 __asm__("r8");
1889 +       register unsigned int b2 __asm__("r9");
1890 +       register unsigned int b3 __asm__("ip");
1891 +       register unsigned int b4 __asm__("lr");
1892 +
1893 +       do {
1894 +               GET_BLOCK_4(p1);
1895 +               XOR_BLOCK_4(p2);
1896 +               XOR_BLOCK_4(p3);
1897 +               PUT_BLOCK_4(p1);
1898 +       } while (--lines);
1899 +}
1900 +
1901 +static void
1902 +xor_arm4regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
1903 +               unsigned long *p3, unsigned long *p4)
1904 +{
1905 +       unsigned int lines = bytes / sizeof(unsigned long) / 2;
1906 +       register unsigned int a1 __asm__("r8");
1907 +       register unsigned int a2 __asm__("r9");
1908 +       register unsigned int b1 __asm__("ip");
1909 +       register unsigned int b2 __asm__("lr");
1910 +
1911 +       do {
1912 +               GET_BLOCK_2(p1);
1913 +               XOR_BLOCK_2(p2);
1914 +               XOR_BLOCK_2(p3);
1915 +               XOR_BLOCK_2(p4);
1916 +               PUT_BLOCK_2(p1);
1917 +       } while (--lines);
1918 +}
1919 +
1920 +static void
1921 +xor_arm4regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
1922 +               unsigned long *p3, unsigned long *p4, unsigned long *p5)
1923 +{
1924 +       unsigned int lines = bytes / sizeof(unsigned long) / 2;
1925 +       register unsigned int a1 __asm__("r8");
1926 +       register unsigned int a2 __asm__("r9");
1927 +       register unsigned int b1 __asm__("ip");
1928 +       register unsigned int b2 __asm__("lr");
1929 +
1930 +       do {
1931 +               GET_BLOCK_2(p1);
1932 +               XOR_BLOCK_2(p2);
1933 +               XOR_BLOCK_2(p3);
1934 +               XOR_BLOCK_2(p4);
1935 +               XOR_BLOCK_2(p5);
1936 +               PUT_BLOCK_2(p1);
1937 +       } while (--lines);
1938 +}
1939 +#endif //XOR_SW_FILL_IN
1940 +
1941 Index: linux-2.6.23.16/arch/arm/mach-sl2312/irq.c
1942 ===================================================================
1943 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1944 +++ linux-2.6.23.16/arch/arm/mach-sl2312/irq.c  2008-03-14 11:58:14.702460322 +0200
1945 @@ -0,0 +1,202 @@
1946 +/*
1947 + *  linux/arch/arm/mach-epxa10db/irq.c
1948 + *
1949 + *  Copyright (C) 2001 Altera Corporation
1950 + *
1951 + * This program is free software; you can redistribute it and/or modify
1952 + * it under the terms of the GNU General Public License as published by
1953 + * the Free Software Foundation; either version 2 of the License, or
1954 + * (at your option) any later version.
1955 + *
1956 + * This program is distributed in the hope that it will be useful,
1957 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1958 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1959 + * GNU General Public License for more details.
1960 + *
1961 + * You should have received a copy of the GNU General Public License
1962 + * along with this program; if not, write to the Free Software
1963 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
1964 + */
1965 +#include <linux/init.h>
1966 +#include <linux/ioport.h>
1967 +#include <linux/stddef.h>
1968 +#include <linux/list.h>
1969 +#include <linux/sched.h>
1970 +#include <asm/hardware.h>
1971 +#include <asm/irq.h>
1972 +#include <asm/io.h>
1973 +#include <asm/mach/irq.h>
1974 +#include <asm/arch/platform.h>
1975 +#include <asm/arch/int_ctrl.h>
1976 +
1977 +#ifdef CONFIG_PCI
1978 +#include <asm/arch/pci.h>
1979 +#endif
1980 +
1981 +int fixup_irq(unsigned int irq)
1982 +{
1983 +#ifdef CONFIG_PCI
1984 +       if (irq == IRQ_PCI) {
1985 +               return sl2312_pci_get_int_src();
1986 +       }
1987 +#endif
1988 +       return irq;
1989 +}
1990 +
1991 +static void sl2312_ack_irq(unsigned int irq)
1992 +{
1993 +   __raw_writel(1 << irq, IRQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
1994 +}
1995 +
1996 +static void sl2312_mask_irq(unsigned int irq)
1997 +{
1998 +       unsigned int mask;
1999 +
2000 +#ifdef CONFIG_PCI
2001 +       if (irq >= PCI_IRQ_OFFSET)
2002 +       {
2003 +               mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2004 +               mask &= ~IRQ_PCI_MASK ;
2005 +               __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2006 +               sl2312_pci_mask_irq(irq - PCI_IRQ_OFFSET);
2007 +       }
2008 +       else
2009 +#endif
2010 +       if(irq >= FIQ_OFFSET)
2011 +       {
2012 +           mask = __raw_readl(FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2013 +           mask &= ~(1 << (irq - FIQ_OFFSET));
2014 +           __raw_writel(mask, FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2015 +        }
2016 +        else
2017 +        {
2018 +           mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2019 +           mask &= ~(1 << irq);
2020 +           __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2021 +        }
2022 +
2023 +}
2024 +
2025 +static void sl2312_unmask_irq(unsigned int irq)
2026 +{
2027 +       unsigned int mask;
2028 +
2029 +#ifdef CONFIG_PCI
2030 +       if (irq >= PCI_IRQ_OFFSET)
2031 +       {
2032 +               mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2033 +               mask |= IRQ_PCI_MASK ;
2034 +               __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2035 +               sl2312_pci_unmask_irq(irq - PCI_IRQ_OFFSET);
2036 +       }
2037 +       else
2038 +#endif
2039 +       if(irq >= FIQ_OFFSET)
2040 +        {
2041 +          mask = __raw_readl(FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2042 +          mask |= (1 << (irq - FIQ_OFFSET));
2043 +          __raw_writel(mask, FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2044 +       }
2045 +        else
2046 +        {
2047 +          mask = __raw_readl(IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2048 +          mask |= (1 << irq);
2049 +          __raw_writel(mask, IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2050 +        }
2051 +}
2052 +
2053 +static struct irq_chip sl2312_level_irq = {
2054 +        .ack            = sl2312_mask_irq,
2055 +        .mask           = sl2312_mask_irq,
2056 +        .unmask         = sl2312_unmask_irq,
2057 +//             .set_type       = ixp4xx_set_irq_type,
2058 +};
2059 +
2060 +static struct irq_chip sl2312_edge_irq = {
2061 +        .ack            = sl2312_ack_irq,
2062 +        .mask           = sl2312_mask_irq,
2063 +        .unmask         = sl2312_unmask_irq,
2064 +//             .set_type       = ixp4xx_set_irq_type,
2065 +};
2066 +
2067 +static struct resource irq_resource = {
2068 +        .name   = "irq_handler",
2069 +        .start  = IO_ADDRESS(SL2312_INTERRUPT_BASE),
2070 +        .end    = IO_ADDRESS(FIQ_STATUS(SL2312_INTERRUPT_BASE))+4,
2071 +};
2072 +
2073 +void __init sl2312_init_irq(void)
2074 +{
2075 +       unsigned int i, mode, level;
2076 +
2077 +    request_resource(&iomem_resource, &irq_resource);
2078 +
2079 +       for (i = 0; i < NR_IRQS; i++)
2080 +       {
2081 +           if((i>=IRQ_TIMER1 && i<=IRQ_TIMER3)||(i>=IRQ_SERIRQ0 && i<=IRQ_SERIRQ_MAX))
2082 +        {
2083 +               set_irq_chip(i, &sl2312_edge_irq);
2084 +               set_irq_handler(i, handle_edge_irq);
2085 +        }
2086 +           else
2087 +        {
2088 +               set_irq_chip(i, &sl2312_level_irq);
2089 +            set_irq_handler(i,handle_level_irq);
2090 +        }
2091 +        set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
2092 +       }
2093 +
2094 +       /* Disable all interrupt */
2095 +       __raw_writel(0,IRQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2096 +       __raw_writel(0,FIQ_MASK(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2097 +
2098 +       /* Set interrupt mode */
2099 +    /* emac & ipsec type is level trigger and high active */
2100 +    mode = __raw_readl(IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2101 +    level = __raw_readl(IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2102 +
2103 +       mode &= ~IRQ_GMAC0_MASK;
2104 +       level &= ~IRQ_GMAC0_MASK;
2105 +
2106 +       mode &= ~IRQ_GMAC1_MASK;
2107 +       level &= ~IRQ_GMAC1_MASK;
2108 +
2109 +       mode &= ~IRQ_IPSEC_MASK;
2110 +       level &= ~IRQ_IPSEC_MASK;
2111 +
2112 +       // for IDE0,1, high active and level trigger
2113 +       mode &= ~IRQ_IDE0_MASK;
2114 +       level &= ~IRQ_IDE0_MASK;
2115 +       mode &= ~IRQ_IDE1_MASK;
2116 +       level &= ~IRQ_IDE1_MASK;
2117 +
2118 +
2119 +       // for PCI, high active and level trigger
2120 +       mode &= ~IRQ_PCI_MASK;
2121 +       level &= ~IRQ_PCI_MASK;
2122 +
2123 +       // for USB, high active and level trigger
2124 +       mode &= ~IRQ_USB0_MASK;
2125 +       level &= ~IRQ_USB0_MASK;
2126 +
2127 +       mode &= ~IRQ_USB1_MASK;
2128 +       level &= ~IRQ_USB1_MASK;
2129 +
2130 +       // for LPC, high active and edge trigger
2131 +       mode |= 0xffff0000;
2132 +       level &= 0x0000ffff;
2133 +
2134 +       // for GPIO, high active and level trigger
2135 +       mode &= ~(IRQ_GPIO_MASK);
2136 +       level &= ~(IRQ_GPIO_MASK);
2137 +
2138 +       mode &= ~(IRQ_GPIO1_MASK);
2139 +       level &= ~(IRQ_GPIO1_MASK);
2140 +
2141 +       mode &= ~(IRQ_GPIO2_MASK);
2142 +       level &= ~(IRQ_GPIO2_MASK);
2143 +
2144 +       __raw_writel(mode,IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2145 +       __raw_writel(level,IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE)));
2146 +
2147 +}
2148 Index: linux-2.6.23.16/arch/arm/mach-sl2312/lpc.c
2149 ===================================================================
2150 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2151 +++ linux-2.6.23.16/arch/arm/mach-sl2312/lpc.c  2008-03-13 17:48:24.508798285 +0200
2152 @@ -0,0 +1,125 @@
2153 +/*
2154 + *
2155 + * BRIEF MODULE DESCRIPTION
2156 + *     ITE Semi IT8712 Super I/O functions.
2157 + *
2158 + * Copyright 2001 MontaVista Software Inc.
2159 + * Author: MontaVista Software, Inc.
2160 + *             ppopov@mvista.com or source@mvista.com
2161 + *
2162 + *  This program is free software; you can redistribute  it and/or modify it
2163 + *  under  the terms of  the GNU General  Public License as published by the
2164 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2165 + *  option) any later version.
2166 + *
2167 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2168 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2169 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2170 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2171 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2172 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2173 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2174 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2175 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2176 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2177 + *
2178 + *  You should have received a copy of the  GNU General Public License along
2179 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2180 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2181 + */
2182 +#include <linux/kernel.h>
2183 +#include <linux/delay.h>
2184 +#include <asm/io.h>
2185 +#include <asm/types.h>
2186 +#include <asm/arch/it8712.h>
2187 +#include <linux/init.h>
2188 +#include <asm/arch/hardware.h>
2189 +
2190 +#ifndef TRUE
2191 +#define TRUE 1
2192 +#endif
2193 +
2194 +#ifndef FALSE
2195 +#define FALSE 0
2196 +#endif
2197 +
2198 +
2199 +// MB PnP configuration register
2200 +#define LPC_KEY_ADDR   (IO_ADDRESS(SL2312_LPC_IO_BASE) + 0x2e)
2201 +#define LPC_DATA_ADDR  (IO_ADDRESS(SL2312_LPC_IO_BASE) + 0x2f)
2202 +
2203 +#define LPC_BUS_CTRL                   *(volatile unsigned char*) (IO_ADDRESS(SL2312_LPC_HOST_BASE) + 0)
2204 +#define LPC_BUS_STATUS                 *(volatile unsigned char*) (IO_ADDRESS(SL2312_LPC_HOST_BASE) + 2)
2205 +#define LPC_SERIAL_IRQ_CTRL            *(volatile unsigned char*) (IO_ADDRESS(SL2312_LPC_HOST_BASE) + 4)
2206 +
2207 +int it8712_exist;
2208 +
2209 +static void LPCEnterMBPnP(void)
2210 +{
2211 +       int i;
2212 +       unsigned char key[4] = {0x87, 0x01, 0x55, 0x55};
2213 +
2214 +       for (i = 0; i<4; i++)
2215 +               outb(key[i], LPC_KEY_ADDR);
2216 +
2217 +}
2218 +
2219 +static void LPCExitMBPnP(void)
2220 +{
2221 +       outb(0x02, LPC_KEY_ADDR);
2222 +       outb(0x02, LPC_DATA_ADDR);
2223 +}
2224 +
2225 +void LPCSetConfig(char LdnNumber, char Index, char data)
2226 +{
2227 +       LPCEnterMBPnP();                                // Enter IT8712 MB PnP mode
2228 +       outb(0x07, LPC_KEY_ADDR);
2229 +       outb(LdnNumber, LPC_DATA_ADDR);
2230 +       outb(Index, LPC_KEY_ADDR);
2231 +       outb(data, LPC_DATA_ADDR);
2232 +       LPCExitMBPnP();
2233 +}
2234 +
2235 +char LPCGetConfig(char LdnNumber, char Index)
2236 +{
2237 +       char rtn;
2238 +
2239 +       LPCEnterMBPnP();                                // Enter IT8712 MB PnP mode
2240 +       outb(0x07, LPC_KEY_ADDR);
2241 +       outb(LdnNumber, LPC_DATA_ADDR);
2242 +       outb(Index, LPC_KEY_ADDR);
2243 +       rtn = inb(LPC_DATA_ADDR);
2244 +       LPCExitMBPnP();
2245 +       return rtn;
2246 +}
2247 +
2248 +static int SearchIT8712(void)
2249 +{
2250 +       unsigned char Id1, Id2;
2251 +       unsigned short Id;
2252 +
2253 +       LPCEnterMBPnP();
2254 +       outb(0x20, LPC_KEY_ADDR); /* chip id byte 1 */
2255 +       Id1 = inb(LPC_DATA_ADDR);
2256 +       outb(0x21, LPC_KEY_ADDR); /* chip id byte 2 */
2257 +       Id2 = inb(LPC_DATA_ADDR);
2258 +       Id = (Id1 << 8) | Id2;
2259 +       LPCExitMBPnP();
2260 +       if (Id == 0x8712)
2261 +               return TRUE;
2262 +       else
2263 +               return FALSE;
2264 +}
2265 +
2266 +int InitLPCInterface(void)
2267 +{
2268 +       LPC_BUS_CTRL = 0xc0;
2269 +       LPC_SERIAL_IRQ_CTRL = 0xc0;
2270 +       mdelay(1);              // wait for 1 serial IRQ cycle
2271 +       LPC_SERIAL_IRQ_CTRL = 0x80;
2272 +       it8712_exist = SearchIT8712();
2273 +       printk("IT8712 %s exist\n", it8712_exist?"":"doesn't");
2274 +       return 0;
2275 +}
2276 +
2277 +//__initcall(InitLPCInterface);
2278 Index: linux-2.6.23.16/arch/arm/mach-sl2312/mm.c
2279 ===================================================================
2280 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2281 +++ linux-2.6.23.16/arch/arm/mach-sl2312/mm.c   2008-03-13 17:48:24.508798285 +0200
2282 @@ -0,0 +1,80 @@
2283 +/*
2284 + *  linux/arch/arm/mach-epxa10db/mm.c
2285 + *
2286 + *  MM routines for Altera'a Epxa10db board
2287 + *
2288 + *  Copyright (C) 2001 Altera Corporation
2289 + *
2290 + * This program is free software; you can redistribute it and/or modify
2291 + * it under the terms of the GNU General Public License as published by
2292 + * the Free Software Foundation; either version 2 of the License, or
2293 + * (at your option) any later version.
2294 + *
2295 + * This program is distributed in the hope that it will be useful,
2296 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2297 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2298 + * GNU General Public License for more details.
2299 + *
2300 + * You should have received a copy of the GNU General Public License
2301 + * along with this program; if not, write to the Free Software
2302 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2303 + */
2304 +#include <linux/sched.h>
2305 +#include <linux/mm.h>
2306 +#include <linux/init.h>
2307 +
2308 +#include <asm/hardware.h>
2309 +#include <asm/io.h>
2310 +#include <asm/pgtable.h>
2311 +#include <asm/page.h>
2312 +#include <asm/sizes.h>
2313 +
2314 +#include <asm/mach/map.h>
2315 +
2316 +/* Page table mapping for I/O region */
2317 +static struct map_desc sl2312_io_desc[] __initdata = {
2318 +#ifdef CONFIG_GEMINI_IPI
2319 +{__phys_to_virt(CPU_1_MEM_BASE),         __phys_to_pfn(CPU_1_MEM_BASE),        SZ_64M,  MT_MEMORY},
2320 +#endif
2321 +{IO_ADDRESS(SL2312_SRAM_BASE),         __phys_to_pfn(SL2312_SRAM_BASE),        SZ_512K,  MT_DEVICE},
2322 +{IO_ADDRESS(SL2312_DRAM_CTRL_BASE),    __phys_to_pfn(SL2312_DRAM_CTRL_BASE),   SZ_512K,  MT_DEVICE},
2323 +{IO_ADDRESS(SL2312_GLOBAL_BASE),       __phys_to_pfn(SL2312_GLOBAL_BASE),      SZ_512K,  MT_DEVICE},
2324 +{IO_ADDRESS(SL2312_WAQTCHDOG_BASE),    __phys_to_pfn(SL2312_WAQTCHDOG_BASE),   SZ_512K,  MT_DEVICE},
2325 +{IO_ADDRESS(SL2312_UART_BASE),         __phys_to_pfn(SL2312_UART_BASE),        SZ_512K,  MT_DEVICE},
2326 +{IO_ADDRESS(SL2312_TIMER_BASE),        __phys_to_pfn(SL2312_TIMER_BASE),       SZ_512K,  MT_DEVICE},
2327 +{IO_ADDRESS(SL2312_LCD_BASE),          __phys_to_pfn(SL2312_LCD_BASE),         SZ_512K,  MT_DEVICE},
2328 +{IO_ADDRESS(SL2312_RTC_BASE),          __phys_to_pfn(SL2312_RTC_BASE),         SZ_512K,  MT_DEVICE},
2329 +{IO_ADDRESS(SL2312_SATA_BASE),         __phys_to_pfn(SL2312_SATA_BASE),        SZ_512K,  MT_DEVICE},
2330 +{IO_ADDRESS(SL2312_LPC_HOST_BASE),     __phys_to_pfn(SL2312_LPC_HOST_BASE),    SZ_512K,  MT_DEVICE},
2331 +{IO_ADDRESS(SL2312_LPC_IO_BASE),       __phys_to_pfn(SL2312_LPC_IO_BASE),      SZ_512K,  MT_DEVICE},
2332 +{IO_ADDRESS(SL2312_INTERRUPT_BASE),    __phys_to_pfn(SL2312_INTERRUPT_BASE),   SZ_512K,  MT_DEVICE},
2333 +{IO_ADDRESS(SL2312_INTERRUPT1_BASE),   __phys_to_pfn(SL2312_INTERRUPT1_BASE),  SZ_512K,  MT_DEVICE},
2334 +{IO_ADDRESS(SL2312_SSP_CTRL_BASE),     __phys_to_pfn(SL2312_SSP_CTRL_BASE),    SZ_512K,  MT_DEVICE},
2335 +{IO_ADDRESS(SL2312_POWER_CTRL_BASE),   __phys_to_pfn(SL2312_POWER_CTRL_BASE),  SZ_512K,  MT_DEVICE},
2336 +{IO_ADDRESS(SL2312_CIR_BASE),          __phys_to_pfn(SL2312_CIR_BASE),         SZ_512K,  MT_DEVICE},
2337 +{IO_ADDRESS(SL2312_GPIO_BASE),         __phys_to_pfn(SL2312_GPIO_BASE),        SZ_512K,  MT_DEVICE},
2338 +{IO_ADDRESS(SL2312_GPIO_BASE1),        __phys_to_pfn(SL2312_GPIO_BASE1),       SZ_512K,  MT_DEVICE},
2339 +{IO_ADDRESS(SL2312_GPIO_BASE2),        __phys_to_pfn(SL2312_GPIO_BASE2),       SZ_512K,  MT_DEVICE},
2340 +{IO_ADDRESS(SL2312_PCI_IO_BASE),          __phys_to_pfn(SL2312_PCI_IO_BASE),      SZ_512K,  MT_DEVICE},
2341 +{IO_ADDRESS(SL2312_PCI_MEM_BASE),         __phys_to_pfn(SL2312_PCI_MEM_BASE),     SZ_512K,  MT_DEVICE},
2342 +#ifdef CONFIG_NET_SL351X
2343 +{IO_ADDRESS(SL2312_TOE_BASE),          __phys_to_pfn(SL2312_TOE_BASE)       ,   SZ_512K,  MT_DEVICE},
2344 +#endif
2345 +{IO_ADDRESS(SL2312_GMAC0_BASE),               __phys_to_pfn(SL2312_GMAC0_BASE),           SZ_512K,  MT_DEVICE},
2346 +{IO_ADDRESS(SL2312_GMAC1_BASE),               __phys_to_pfn(SL2312_GMAC1_BASE),           SZ_512K,  MT_DEVICE},
2347 +{IO_ADDRESS(SL2312_SECURITY_BASE),     __phys_to_pfn(SL2312_SECURITY_BASE),    SZ_512K,  MT_DEVICE},
2348 +{IO_ADDRESS(SL2312_IDE0_BASE),         __phys_to_pfn(SL2312_IDE0_BASE),        SZ_512K,  MT_DEVICE},
2349 +{IO_ADDRESS(SL2312_IDE1_BASE),         __phys_to_pfn(SL2312_IDE1_BASE),        SZ_512K,  MT_DEVICE},
2350 +{IO_ADDRESS(SL2312_RAID_BASE),         __phys_to_pfn(SL2312_RAID_BASE),        SZ_512K,  MT_DEVICE},
2351 +{IO_ADDRESS(SL2312_FLASH_CTRL_BASE),   __phys_to_pfn(SL2312_FLASH_CTRL_BASE),  SZ_512K,  MT_DEVICE},
2352 +{IO_ADDRESS(SL2312_DRAM_CTRL_BASE),    __phys_to_pfn(SL2312_DRAM_CTRL_BASE),   SZ_512K,  MT_DEVICE},
2353 +{IO_ADDRESS(SL2312_GENERAL_DMA_BASE),  __phys_to_pfn(SL2312_GENERAL_DMA_BASE), SZ_512K,  MT_DEVICE},
2354 +{IO_ADDRESS(SL2312_USB0_BASE),         __phys_to_pfn(SL2312_USB_BASE),         SZ_512K,  MT_DEVICE},
2355 +{IO_ADDRESS(SL2312_USB1_BASE),         __phys_to_pfn(SL2312_USB1_BASE),        SZ_512K,  MT_DEVICE},
2356 +{FLASH_VADDR(SL2312_FLASH_BASE),       __phys_to_pfn(SL2312_FLASH_BASE),       SZ_16M,    MT_DEVICE},
2357 +};
2358 +
2359 +void __init sl2312_map_io(void)
2360 +{
2361 +       iotable_init(sl2312_io_desc, ARRAY_SIZE(sl2312_io_desc));
2362 +}
2363 Index: linux-2.6.23.16/arch/arm/mach-sl2312/pci.c
2364 ===================================================================
2365 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2366 +++ linux-2.6.23.16/arch/arm/mach-sl2312/pci.c  2008-03-14 12:56:27.401497897 +0200
2367 @@ -0,0 +1,359 @@
2368 +/*
2369 + *  linux/arch/arm/mach-sl2312/pci_sl2312.c
2370 + *
2371 + *  PCI functions for sl2312 host PCI bridge
2372 + *
2373 + *  Copyright (C) 2003 StorLink Corp.
2374 + *
2375 + * This program is free software; you can redistribute it and/or modify
2376 + * it under the terms of the GNU General Public License as published by
2377 + * the Free Software Foundation; either version 2 of the License, or
2378 + * (at your option) any later version.
2379 + *
2380 + * This program is distributed in the hope that it will be useful,
2381 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2382 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2383 + * GNU General Public License for more details.
2384 + *
2385 + * You should have received a copy of the GNU General Public License
2386 + * along with this program; if not, write to the Free Software
2387 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
2388 + */
2389 +#include <linux/sched.h>
2390 +#include <linux/kernel.h>
2391 +#include <linux/pci.h>
2392 +#include <linux/ptrace.h>
2393 +#include <linux/slab.h>
2394 +#include <linux/ioport.h>
2395 +#include <linux/interrupt.h>
2396 +#include <linux/spinlock.h>
2397 +#include <linux/init.h>
2398 +
2399 +#include <asm/sizes.h>
2400 +#include <asm/hardware.h>
2401 +#include <asm/irq.h>
2402 +#include <asm/system.h>
2403 +#include <asm/mach/pci.h>
2404 +#include <asm/mach/irq.h>
2405 +#include <asm/mach-types.h>
2406 +
2407 +#include <asm/arch/pci.h>
2408 +
2409 +//#define DEBUG
2410 +
2411 +// sl2312 PCI bridge access routines
2412 +
2413 +#define PCI_IOSIZE_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE)))
2414 +#define PCI_PROT_REG   (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x04))
2415 +#define PCI_CTRL_REG   (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x08))
2416 +#define PCI_SOFTRST_REG        (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x10))
2417 +#define PCI_CONFIG_REG (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x28))
2418 +#define PCI_DATA_REG   (*(volatile unsigned long *) (IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x2C))
2419 +
2420 +static spinlock_t sl2312_pci_lock = SPIN_LOCK_UNLOCKED;
2421 +// for initialize PCI devices
2422 +struct resource pci_ioport_resource = {
2423 +               .name = "PCI I/O Space",
2424 +               .start = IO_ADDRESS(SL2312_PCI_IO_BASE) + 0x100,
2425 +               .end = IO_ADDRESS(SL2312_PCI_IO_BASE) + SZ_512K - 1,
2426 +               .flags = IORESOURCE_IO,
2427 +};
2428 +struct resource pci_iomem_resource = {
2429 +               .name = "PCI Mem Space",
2430 +               .start = SL2312_PCI_MEM_BASE,
2431 +               .end = SL2312_PCI_MEM_BASE + SZ_128M - 1,
2432 +               .flags = IORESOURCE_MEM,
2433 +};
2434 +
2435 +static int sl2312_read_config(struct pci_bus *bus, unsigned int devfn, int where,int size, u32 *val)
2436 +{
2437 +       unsigned long addr,data;
2438 +       unsigned long flags;
2439 +
2440 +       spin_lock_irqsave(&sl2312_pci_lock, flags);
2441 +    addr = 0x80000000 | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | (where & ~3);
2442 +       PCI_CONFIG_REG = addr;
2443 +       data = PCI_DATA_REG;
2444 +
2445 +       switch (size) {
2446 +       case 1:
2447 +           *val = (u8) (data >> ((where & 0x03) * 8));
2448 +               break;
2449 +       case 2:
2450 +           *val = (u16) (data >> ((where & 0x02) * 8));
2451 +               break;
2452 +       case 4:
2453 +           *val = data;
2454 +       if ((where >= 0x10) && (where <= 0x24)) {
2455 +               if ((*val & 0xfff00000) == SL2312_PCI_IO_BASE) {
2456 +                       *val &= 0x000fffff;
2457 +                       *val |= IO_ADDRESS(SL2312_PCI_IO_BASE);
2458 +               }
2459 +       }
2460 +               break;
2461 +       }
2462 +       spin_unlock_irqrestore(&sl2312_pci_lock, flags);
2463 +//     printk("READ==>slot=%d fn=%d where=%d value=%x\n",PCI_SLOT(devfn),PCI_FUNC(devfn),where,*val);
2464 +       return PCIBIOS_SUCCESSFUL;
2465 +}
2466 +
2467 +static int sl2312_write_config(struct pci_bus *bus, unsigned int devfn, int where,int size, u32 val)
2468 +{
2469 +       unsigned long addr,data;
2470 +       unsigned long flags;
2471 +
2472 +       spin_lock_irqsave(&sl2312_pci_lock, flags);
2473 +    addr = 0x80000000 | (PCI_SLOT(devfn) << 11) | (PCI_FUNC(devfn) << 8) | (where & ~3);
2474 +       PCI_CONFIG_REG = addr;
2475 +       data = PCI_DATA_REG;
2476 +
2477 +       switch (size) {
2478 +       case 1:
2479 +       data &= ~(0xff << ((where & 0x03) * 8));
2480 +       data |= (val << ((where & 0x03) * 8));
2481 +       PCI_DATA_REG = data;
2482 +               break;
2483 +       case 2:
2484 +       data &= ~(0xffff << ((where & 0x02) * 8));
2485 +       data |= (val << ((where & 0x02) * 8));
2486 +       PCI_DATA_REG = data;
2487 +               break;
2488 +       case 4:
2489 +       if ((where >= 0x10) && (where <= 0x24)) {
2490 +               if ((val & 0xfff00000) == IO_ADDRESS(SL2312_PCI_IO_BASE)) {
2491 +                       val &= 0x000fffff;
2492 +                       val |= SL2312_PCI_IO_BASE;
2493 +               }
2494 +       }
2495 +           PCI_DATA_REG = val;
2496 +               break;
2497 +       }
2498 +       spin_unlock_irqrestore(&sl2312_pci_lock, flags);
2499 +
2500 +//     printk("WRITE==> slot=%d fn=%d where=%d value=%x \n",PCI_SLOT(devfn),PCI_FUNC(devfn),where,val);
2501 +       return PCIBIOS_SUCCESSFUL;
2502 +}
2503 +
2504 +static struct pci_ops sl2312_pci_ops = {
2505 +       .read   = sl2312_read_config,
2506 +       .write  = sl2312_write_config,
2507 +};
2508 +
2509 +
2510 +int __init sl2312_pci_setup_resources(struct resource **resource)
2511 +{
2512 +       PCI_IOSIZE_REG = 0;             // 1M IO size
2513 +       PCI_CTRL_REG = 0x06;
2514 +
2515 +       resource[0] = &pci_ioport_resource;
2516 +       resource[1] = &pci_iomem_resource;
2517 +       resource[2] = NULL;
2518 +
2519 +       return 1;
2520 +}
2521 +
2522 +//static int sl2312_pci_fault(unsigned long addr, struct pt_regs *regs)
2523 +//{
2524 +//     return 1;
2525 +//}
2526 +
2527 +
2528 +/**********************************************************************
2529 + * MASK(disable) PCI interrupt
2530 + *    0: PCI INTA, 1: PCI INTB, ...            // for Linux interrupt routing
2531 + *   16: PERR                                                          // for PCI module internal use
2532 + *   17: SERR,.. respect to PCI CTRL2 REG
2533 + **********************************************************************/
2534 +void sl2312_pci_mask_irq(unsigned int irq)
2535 +{
2536 +    struct pci_bus bus;
2537 +       unsigned int tmp;
2538 +
2539 +    bus.number = 0;
2540 +    sl2312_read_config(&bus, 0, SL2312_PCI_CTRL2, 4, &tmp);
2541 +       if (irq < 16) {                                         // for linux int routing
2542 +               tmp &= ~(1 << (irq + 16 + 6));
2543 +       }
2544 +       else {
2545 +               tmp &= ~(1 << irq);
2546 +       }
2547 +    sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2548 +}
2549 +
2550 +/* UNMASK(enable) PCI interrupt */
2551 +void sl2312_pci_unmask_irq(unsigned int irq)
2552 +{
2553 +    struct pci_bus bus;
2554 +       unsigned int tmp;
2555 +
2556 +    bus.number = 0;
2557 +    sl2312_read_config(&bus, 0, SL2312_PCI_CTRL2, 4, &tmp);
2558 +       if (irq < 16) {                                         // for linux int routing
2559 +               tmp |= (1 << (irq + 16 + 6));
2560 +       }
2561 +       else {
2562 +               tmp |= (1 << irq);
2563 +       }
2564 +    sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2565 +}
2566 +
2567 +/* Get PCI interrupt source */
2568 +int sl2312_pci_get_int_src(void)
2569 +{
2570 +    struct pci_bus bus;
2571 +       unsigned int tmp=0;
2572 +
2573 +    bus.number = 0;
2574 +    sl2312_read_config(&bus, 0, SL2312_PCI_CTRL2, 4, &tmp);
2575 +       if (tmp & (1 << 28)) {          // PCI INTA
2576 +        sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2577 +               return IRQ_PCI_INTA;
2578 +       }
2579 +       if (tmp & (1 << 29)) {          // PCI INTB
2580 +        sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2581 +               return IRQ_PCI_INTB;
2582 +       }
2583 +       if (tmp & (1 << 30)) {          // PCI INTC
2584 +        sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2585 +               return IRQ_PCI_INTC;
2586 +       }
2587 +       if (tmp & (1 << 31)) {          // PCI INTD
2588 +        sl2312_write_config(&bus, 0, SL2312_PCI_CTRL2, 4, tmp);
2589 +               return IRQ_PCI_INTD;
2590 +       }
2591 +       // otherwise, it should be a PCI error
2592 +       return IRQ_PCI;
2593 +}
2594 +
2595 +static irqreturn_t sl2312_pci_irq(int irq, void *devid)
2596 +{
2597 +    struct irq_desc *desc;
2598 +       struct irqaction *action;
2599 +       int retval = 0;
2600 +
2601 +    return 1;
2602 +
2603 +       irq = sl2312_pci_get_int_src();
2604 +       desc = &irq_desc[irq];
2605 +       action = desc->action;
2606 +       do {
2607 +               retval |= action->handler(irq, devid);
2608 +               action = action->next;
2609 +       } while (action);
2610 +
2611 +    return 1;
2612 +}
2613 +
2614 +//extern int (*external_fault)(unsigned long addr, struct pt_regs *regs);
2615 +
2616 +void __init sl2312_pci_preinit(void)
2617 +{
2618 +    struct pci_bus bus;
2619 +       unsigned long flags;
2620 +       unsigned int temp;
2621 +       int ret;
2622 +
2623 +       /*
2624 +        * Hook in our fault handler for PCI errors
2625 +        */
2626 +//     external_fault = sl2312_pci_fault;
2627 +
2628 +       spin_lock_irqsave(&sl2312_pci_lock, flags);
2629 +
2630 +       /*
2631 +        * Grab the PCI interrupt.
2632 +        */
2633 +       ret = request_irq(IRQ_PCI, sl2312_pci_irq, 0, "sl2312 pci int", NULL);
2634 +       if (ret)
2635 +               printk(KERN_ERR "PCI: unable to grab PCI error "
2636 +                      "interrupt: %d\n", ret);
2637 +
2638 +       spin_unlock_irqrestore(&sl2312_pci_lock, flags);
2639 +
2640 +       // setup pci bridge
2641 +    bus.number = 0;   /* device 0, function 0 */
2642 +       temp = (SL2312_PCI_DMA_MEM1_BASE & 0xfff00000) | (SL2312_PCI_DMA_MEM1_SIZE << 16);
2643 +    sl2312_write_config(&bus, 0, SL2312_PCI_MEM1_BASE_SIZE, 4, temp);
2644 +}
2645 +
2646 +/*
2647 + *     No swizzle on SL2312
2648 + */
2649 +static u8 __init sl2312_pci_swizzle(struct pci_dev *dev, u8 *pinp)
2650 +{
2651 +       return PCI_SLOT(dev->devfn);
2652 +}
2653 +
2654 +/*
2655 + * map the specified device/slot/pin to an IRQ.  This works out such
2656 + * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
2657 + */
2658 +static int __init sl2312_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
2659 +{
2660 +       int intnr = ((slot  + (pin - 1)) & 3) + 4;  /* the IRQ number of PCI bridge */
2661 +
2662 +       // printk("%s : slot = %d  pin = %d \n",__func__,slot,pin);
2663 +    switch (slot)
2664 +    {
2665 +        case 12:
2666 +               if (pin==1)
2667 +               {
2668 +                       intnr = 3;
2669 +                   }
2670 +                   else
2671 +                   {
2672 +                       intnr = 0;
2673 +                   }
2674 +            break;
2675 +        case 11:
2676 +                   intnr = (2 + (pin - 1)) & 3;
2677 +            break;
2678 +        case 10:
2679 +                   intnr = (1 + (pin - 1)) & 3;
2680 +            break;
2681 +        case  9:
2682 +                   intnr = (pin - 1) & 3;
2683 +            break;
2684 +    }
2685 +//     if (slot == 10)
2686 +//             intnr = (1 + (pin - 1)) & 3;
2687 +//     else if (slot == 9)
2688 +//             intnr = (pin - 1) & 3;
2689 +       return (IRQ_PCI_INTA + intnr);
2690 +}
2691 +
2692 +struct pci_bus * __init sl2312_pci_scan_bus(int nr, struct pci_sys_data *sysdata)
2693 +{
2694 +       return (pci_scan_bus(0, &sl2312_pci_ops, sysdata));
2695 +
2696 +}
2697 +
2698 +int __init sl2312_pci_setup(int nr, struct pci_sys_data *sys)
2699 +{
2700 +       int ret = 0;
2701 +
2702 +       if (nr == 0) {
2703 +               ret = sl2312_pci_setup_resources(sys->resource);
2704 +       }
2705 +
2706 +       return ret;
2707 +}
2708 +
2709 +
2710 +struct hw_pci sl2312_pci __initdata = {
2711 +       .setup          =       sl2312_pci_setup,
2712 +       .preinit                =       sl2312_pci_preinit,
2713 +       .nr_controllers =   1,
2714 +       .swizzle                =       sl2312_pci_swizzle,
2715 +       .map_irq                =       sl2312_pci_map_irq,
2716 +       .scan           =   sl2312_pci_scan_bus,
2717 +};
2718 +
2719 +static int __init sl2312_pci_init(void)
2720 +{
2721 +       if (machine_is_sl2312())
2722 +               pci_common_init(&sl2312_pci);
2723 +       return 0;
2724 +}
2725 +
2726 +subsys_initcall(sl2312_pci_init);
2727 Index: linux-2.6.23.16/arch/arm/mach-sl2312/sl2312-otg-1.c
2728 ===================================================================
2729 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2730 +++ linux-2.6.23.16/arch/arm/mach-sl2312/sl2312-otg-1.c 2008-03-15 16:53:18.340655940 +0200
2731 @@ -0,0 +1,64 @@
2732 +/*
2733 + *  linux/arch/arm/mach-pxa/sl2312.c
2734 + *
2735 + *  Author:    Nicolas Pitre
2736 + *  Created:   Nov 05, 2002
2737 + *  Copyright: MontaVista Software Inc.
2738 + *
2739 + * Code specific to sl2312 aka Bulverde.
2740 + *
2741 + * This program is free software; you can redistribute it and/or modify
2742 + * it under the terms of the GNU General Public License version 2 as
2743 + * published by the Free Software Foundation.
2744 + */
2745 +#include <linux/module.h>
2746 +#include <linux/kernel.h>
2747 +#include <linux/init.h>
2748 +#include <linux/pm.h>
2749 +#include <linux/device.h>
2750 +#include "asm/arch/sl2312.h"
2751 +#include "asm/arch/irqs.h"
2752 +#include <asm/hardware.h>
2753 +#include <asm/irq.h>
2754 +#include <linux/platform_device.h>
2755 +
2756 +/*
2757 + * device registration specific to sl2312.
2758 + */
2759 +
2760 +static u64 sl2312_dmamask_1 = 0xffffffffUL;
2761 +
2762 +static struct resource sl2312_otg_resources_1[] = {
2763 +       [0] = {
2764 +               .start  = 0x69000000,
2765 +               .end    = 0x69000fff,
2766 +               .flags  = IORESOURCE_MEM,
2767 +       },
2768 +       [1] = {
2769 +               .start  = IRQ_USB1,
2770 +               .end    = IRQ_USB1,
2771 +               .flags  = IORESOURCE_IRQ,
2772 +       },
2773 +};
2774 +
2775 +static struct platform_device ehci_1_device = {
2776 +       .name           = "ehci-hcd-FOTG2XX",
2777 +       .id             = -1,
2778 +       .dev            = {
2779 +               .dma_mask = &sl2312_dmamask_1,
2780 +               .coherent_dma_mask = 0xffffffff,
2781 +       },
2782 +       .num_resources  = ARRAY_SIZE(sl2312_otg_resources_1),
2783 +       .resource       = sl2312_otg_resources_1,
2784 +};
2785 +
2786 +static struct platform_device *devices[] __initdata = {
2787 +       &ehci_1_device,
2788 +};
2789 +
2790 +static int __init sl2312_1_init(void)
2791 +{
2792 +       return platform_add_devices(devices, ARRAY_SIZE(devices));
2793 +}
2794 +
2795 +subsys_initcall(sl2312_1_init);
2796 Index: linux-2.6.23.16/arch/arm/mach-sl2312/sl2312-otg.c
2797 ===================================================================
2798 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2799 +++ linux-2.6.23.16/arch/arm/mach-sl2312/sl2312-otg.c   2008-03-14 12:33:51.324219457 +0200
2800 @@ -0,0 +1,87 @@
2801 +/*
2802 + *  linux/arch/arm/mach-pxa/sl2312.c
2803 + *
2804 + *  Author:    Nicolas Pitre
2805 + *  Created:   Nov 05, 2002
2806 + *  Copyright: MontaVista Software Inc.
2807 + *
2808 + * Code specific to sl2312 aka Bulverde.
2809 + *
2810 + * This program is free software; you can redistribute it and/or modify
2811 + * it under the terms of the GNU General Public License version 2 as
2812 + * published by the Free Software Foundation.
2813 + */
2814 +#include <linux/module.h>
2815 +#include <linux/kernel.h>
2816 +#include <linux/init.h>
2817 +#include <linux/pm.h>
2818 +#include <linux/device.h>
2819 +#include "asm/arch/sl2312.h"
2820 +#include "asm/arch/irqs.h"
2821 +#include <asm/hardware.h>
2822 +#include <asm/irq.h>
2823 +#include <linux/platform_device.h>
2824 +
2825 +/*
2826 + * device registration specific to sl2312.
2827 + */
2828 +
2829 +static u64 sl2312_dmamask = 0xffffffffUL;
2830 +
2831 +static struct resource sl2312_otg_resources_1[] = {
2832 +       [0] = {
2833 +               .start  = 0x68000000,
2834 +               .end    = 0x68000fff,
2835 +               .flags  = IORESOURCE_MEM,
2836 +       },
2837 +       [1] = {
2838 +               .start  = IRQ_USB0,
2839 +               .end    = IRQ_USB0,
2840 +               .flags  = IORESOURCE_IRQ,
2841 +       },
2842 +};
2843 +static struct resource sl2312_otg_resources_2[] = {
2844 +       [2] = {
2845 +               .start  = 0x69000000,
2846 +               .end    = 0x69000fff,
2847 +               .flags  = IORESOURCE_MEM,
2848 +       },
2849 +       [3] = {
2850 +               .start  = IRQ_USB1,
2851 +               .end    = IRQ_USB1,
2852 +               .flags  = IORESOURCE_IRQ,
2853 +       },
2854 +};
2855 +
2856 +static struct platform_device ehci_device_1 = {
2857 +       .name           = "ehci-hcd-FOTG2XX",
2858 +       .id             = 1,
2859 +       .dev            = {
2860 +               .dma_mask = &sl2312_dmamask,
2861 +               .coherent_dma_mask = 0xffffffff,
2862 +       },
2863 +       .num_resources  = ARRAY_SIZE(sl2312_otg_resources_1),
2864 +       .resource       = sl2312_otg_resources_1,
2865 +};
2866 +
2867 +static struct platform_device ehci_device_2 = {
2868 +       .name           = "ehci-hcd-FOTG2XX",
2869 +       .id             = 2,
2870 +       .dev            = {
2871 +               .dma_mask = &sl2312_dmamask,
2872 +               .coherent_dma_mask = 0xffffffff,
2873 +       },
2874 +       .num_resources  = ARRAY_SIZE(sl2312_otg_resources_2),
2875 +       .resource       = sl2312_otg_resources_2,
2876 +};
2877 +
2878 +static struct platform_device *devices[] __initdata = {
2879 +       &ehci_device_1, /* &ehci_device_2, */
2880 +};
2881 +
2882 +static int __init sl2312_init(void)
2883 +{
2884 +       return platform_add_devices(devices, ARRAY_SIZE(devices));
2885 +}
2886 +
2887 +subsys_initcall(sl2312_init);
2888 Index: linux-2.6.23.16/arch/arm/mach-sl2312/sl3516_device.c
2889 ===================================================================
2890 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2891 +++ linux-2.6.23.16/arch/arm/mach-sl2312/sl3516_device.c        2008-03-14 12:19:14.774267722 +0200
2892 @@ -0,0 +1,89 @@
2893 +/*
2894 + *  linux/arch/arm/mach-2312/sl3516_device.c
2895 + *
2896 + *  Author:    Nicolas Pitre
2897 + *  Created:   Nov 05, 2002
2898 + *  Copyright: MontaVista Software Inc.
2899 + *
2900 + * Code specific to sl2312 aka Bulverde.
2901 + *
2902 + * This program is free software; you can redistribute it and/or modify
2903 + * it under the terms of the GNU General Public License version 2 as
2904 + * published by the Free Software Foundation.
2905 + */
2906 +#include <linux/module.h>
2907 +#include <linux/kernel.h>
2908 +#include <linux/init.h>
2909 +#include <linux/pm.h>
2910 +#include <linux/device.h>
2911 +#include <linux/platform_device.h>
2912 +#include "asm/arch/sl2312.h"
2913 +#include "asm/arch/irqs.h"
2914 +#include <asm/hardware.h>
2915 +#include <asm/irq.h>
2916 +
2917 +/*
2918 + * device registration specific to sl2312.
2919 + */
2920 +
2921 +static u64 sl3516_dmamask = 0xffffffffUL;
2922 +
2923 +static struct resource sl3516_sata_resources[] = {
2924 +       [0] = {
2925 +               .start  = 0x63400000,
2926 +               .end    = 0x63400040,
2927 +               .flags  = IORESOURCE_MEM,
2928 +       },
2929 +       [1] = {
2930 +               .start  = IRQ_IDE1,
2931 +               .end    = IRQ_IDE1,
2932 +               .flags  = IORESOURCE_IRQ,
2933 +       },
2934 +};
2935 +
2936 +static struct platform_device sata_device = {
2937 +       .name           = "lepus-sata",
2938 +       .id             = -1,
2939 +       .dev            = {
2940 +               .dma_mask = &sl3516_dmamask,
2941 +               .coherent_dma_mask = 0xffffffff,
2942 +       },
2943 +       .num_resources  = ARRAY_SIZE(sl3516_sata_resources),
2944 +       .resource       = sl3516_sata_resources,
2945 +};
2946 +
2947 +static struct resource sl3516_sata0_resources[] = {
2948 +       [0] = {
2949 +               .start  = 0x63000000,
2950 +               .end    = 0x63000040,
2951 +               .flags  = IORESOURCE_MEM,
2952 +       },
2953 +       [1] = {
2954 +               .start  = IRQ_IDE0,
2955 +               .end    = IRQ_IDE0,
2956 +               .flags  = IORESOURCE_IRQ,
2957 +       },
2958 +};
2959 +
2960 +static struct platform_device sata0_device = {
2961 +       .name           = "lepus-sata0",
2962 +       .id             = -1,
2963 +       .dev            = {
2964 +               .dma_mask = &sl3516_dmamask,
2965 +               .coherent_dma_mask = 0xffffffff,
2966 +       },
2967 +       .num_resources  = ARRAY_SIZE(sl3516_sata0_resources),
2968 +       .resource       = sl3516_sata0_resources,
2969 +};
2970 +
2971 +static struct platform_device *sata_devices[] __initdata = {
2972 +       &sata_device,
2973 +       &sata0_device,
2974 +};
2975 +
2976 +static int __init sl3516_init(void)
2977 +{
2978 +       return platform_add_devices(sata_devices, ARRAY_SIZE(sata_devices));
2979 +}
2980 +
2981 +subsys_initcall(sl3516_init);
2982 Index: linux-2.6.23.16/arch/arm/mach-sl2312/time.c
2983 ===================================================================
2984 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2985 +++ linux-2.6.23.16/arch/arm/mach-sl2312/time.c 2008-03-14 12:16:06.263525107 +0200
2986 @@ -0,0 +1,134 @@
2987 +/*
2988 + *  linux/include/asm-arm/arch-epxa10db/time.h
2989 + *
2990 + *  Copyright (C) 2001 Altera Corporation
2991 + *
2992 + * This program is free software; you can redistribute it and/or modify
2993 + * it under the terms of the GNU General Public License as published by
2994 + * the Free Software Foundation; either version 2 of the License, or
2995 + * (at your option) any later version.
2996 + *
2997 + * This program is distributed in the hope that it will be useful,
2998 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2999 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3000 + * GNU General Public License for more details.
3001 + *
3002 + * You should have received a copy of the GNU General Public License
3003 + * along with this program; if not, write to the Free Software
3004 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
3005 + */
3006 +#include <linux/interrupt.h>
3007 +#include <linux/irq.h>
3008 +#include <asm/io.h>
3009 +#include <asm/system.h>
3010 +#include <asm/leds.h>
3011 +#include <asm/arch/hardware.h>
3012 +#include <asm/mach/time.h>
3013 +#define TIMER_TYPE (volatile unsigned int*)
3014 +#include <asm/arch/timer.h>
3015 +// #define FIQ_PLUS     1
3016 +
3017 +
3018 +/*
3019 + * IRQ handler for the timer
3020 + */
3021 +static irqreturn_t sl2312_timer_interrupt(int irq, void *dev_id)
3022 +{
3023 +//        unsigned int led;
3024 +       // ...clear the interrupt
3025 +#ifdef FIQ_PLUS
3026 +       *((volatile unsigned int *)FIQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER1_MASK);
3027 +#else
3028 +       *((volatile unsigned int *)IRQ_CLEAR(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER2_MASK);
3029 +#endif
3030 +
3031 +#if 0
3032 +        if(!(jiffies % HZ))
3033 +        {
3034 +            led = jiffies / HZ;
3035 +//            printk("ticks %x \n", led);
3036 +           }
3037 +       do_leds();
3038 +       do_timer(regs);
3039 +       do_profile(regs);
3040 +#endif
3041 +    timer_tick();
3042 +    return IRQ_HANDLED;
3043 +}
3044 +
3045 +static struct irqaction sl2312_timer_irq = {
3046 +       .name           = "SL2312 Timer Tick",
3047 +       .flags          = IRQF_DISABLED | IRQF_TIMER,
3048 +       .handler        = sl2312_timer_interrupt,
3049 +};
3050 +
3051 +unsigned long sl2312_gettimeoffset (void)
3052 +{
3053 +    return 0L;
3054 +}
3055 +
3056 +/*
3057 + * Set up timer interrupt, and return the current time in seconds.
3058 + */
3059 +void __init sl2312_time_init(void)
3060 +{
3061 +       // For clock rate adjusting
3062 +       unsigned int tick_rate=0;
3063 +
3064 +#ifdef CONFIG_SL3516_ASIC
3065 +       unsigned int clock_rate_base = 130000000;
3066 +       unsigned int reg_v=0;
3067 +
3068 +       //--> Add by jason for clock adjust
3069 +       reg_v = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+GLOBAL_STATUS)));
3070 +       reg_v >>= 15;
3071 +       tick_rate = (clock_rate_base + (reg_v & 0x07)*10000000);
3072 +
3073 +       //  FPGA use AHB bus tick rate
3074 +       printk("Bus: %dMHz",tick_rate/1000000);
3075 +
3076 +       tick_rate /= 6;                         // APB bus run AHB*(1/6)
3077 +
3078 +       switch((reg_v>>3)&3){
3079 +               case 0: printk("(1/1)\n") ;
3080 +                                       break;
3081 +               case 1: printk("(3/2)\n") ;
3082 +                                       break;
3083 +               case 2: printk("(24/13)\n") ;
3084 +                                       break;
3085 +               case 3: printk("(2/1)\n") ;
3086 +                                       break;
3087 +       }
3088 +       //<--
3089 +#else
3090 +       printk("Bus: %dMHz(1/1)\n",CLOCK_TICK_RATE/1000000);            // FPGA use 20MHz
3091 +       tick_rate = CLOCK_TICK_RATE;
3092 +#endif
3093 +
3094 +
3095 +       /*
3096 +        * Make irqs happen for the system timer
3097 +        */
3098 +       // initialize timer interrupt
3099 +       // low active and edge trigger
3100 +#ifdef FIQ_PLUS
3101 +       *((volatile unsigned int *)FIQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER1_MASK);
3102 +       *((volatile unsigned int *)FIQ_LEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER1_MASK);
3103 +       setup_irq(IRQ_TIMER1, &sl2312_timer_irq);
3104 +       /* Start the timer */
3105 +       *TIMER_COUNT(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(tick_rate/HZ);
3106 +       *TIMER_LOAD(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(tick_rate/HZ);
3107 +       *TIMER_CR(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(TIMER_1_CR_ENABLE_MSK|TIMER_1_CR_INT_MSK);
3108 +#else
3109 +       *((volatile unsigned int *)IRQ_TMODE(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER2_MASK);
3110 +       *((volatile unsigned int *)IRQ_TLEVEL(IO_ADDRESS(SL2312_INTERRUPT_BASE))) |= (unsigned int)(IRQ_TIMER2_MASK);
3111 +       setup_irq(IRQ_TIMER2, &sl2312_timer_irq);
3112 +       /* Start the timer */
3113 +       *TIMER_COUNT(IO_ADDRESS(SL2312_TIMER2_BASE))=(unsigned int)(tick_rate/HZ);
3114 +       *TIMER_LOAD(IO_ADDRESS(SL2312_TIMER2_BASE))=(unsigned int)(tick_rate/HZ);
3115 +       *TIMER_CR(IO_ADDRESS(SL2312_TIMER1_BASE))=(unsigned int)(TIMER_2_CR_ENABLE_MSK|TIMER_2_CR_INT_MSK);
3116 +#endif
3117 +
3118 +}
3119 +
3120 +
3121 Index: linux-2.6.23.16/arch/arm/mach-sl2312/xor.c
3122 ===================================================================
3123 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
3124 +++ linux-2.6.23.16/arch/arm/mach-sl2312/xor.c  2008-03-13 17:48:24.508798285 +0200
3125 @@ -0,0 +1,1200 @@
3126 +/*
3127 + * arch/arm/mach-sl2312/xor.c
3128 + *
3129 + * Support functions for the Gemini Soc. This is
3130 + * a HW XOR unit that is specifically designed for use with RAID5
3131 + * applications.  This driver provides an interface that is used by
3132 + * the Linux RAID stack.
3133 + *
3134 + * Original Author: Jason Lee<jason@storlink.com.tw>
3135 + *
3136 + * Contributors:Sanders<sanders@storlink.com.tw>
3137 +                               Jason Lee<jason@storlink.com.tw>
3138 + *
3139 + *
3140 + * Maintainer: Jason Lee<jason@storlink.com.tw>
3141 + *
3142 + * Copyright (C) 2005 Storlink Corporation
3143 + *
3144 + * This program is free software; you can redistribute it and/or modify
3145 + * it under the terms of the GNU General Public License version 2 as
3146 + * published by the Free Software Foundation.
3147 + *
3148 + *
3149 + * History:    (06/25/2005, DJ) Initial Creation
3150 + *
3151 + *     Versing 1.0.0   Initial version
3152 + */
3153 +
3154 +#include <linux/types.h>
3155 +#include <linux/init.h>
3156 +#include <linux/sched.h>
3157 +#include <linux/spinlock.h>
3158 +#include <linux/slab.h>
3159 +#include <linux/errno.h>
3160 +#include <linux/interrupt.h>
3161 +#include <linux/sched.h>
3162 +#include <linux/wait.h>
3163 +#include <linux/list.h>
3164 +#include <linux/pci.h>
3165 +#include <linux/delay.h>
3166 +#include <linux/dma-mapping.h>
3167 +#include <linux/mm.h>
3168 +#include <asm/irq.h>
3169 +#include <asm/delay.h>
3170 +#include <asm/uaccess.h>
3171 +#include <asm/cacheflush.h>
3172 +#include <asm/hardware.h>
3173 +#include <asm/arch/xor.h>
3174 +#include <asm/pci.h>
3175 +#include <linux/version.h>
3176 +
3177 +/*
3178 + * pick up local definitions
3179 + */
3180 +#define XOR_SW_FILL_IN
3181 +#include "hw_xor.h"
3182 +
3183 +
3184 +//#define XOR_DEBUG
3185 +//#define XOR_TEST     1
3186 +#ifdef XOR_TEST
3187 +#define TEST_ITERATION 1000
3188 +#define SPIN_WAIT      1
3189 +#endif
3190 +#ifdef XOR_DEBUG
3191 +#define DPRINTK(s, args...) printk("Gemini XOR: " s "\n", ## args)
3192 +#define DENTER() DPRINTK("Entered...\n");
3193 +#define DEXIT() DPRINTK("Exited...\n");
3194 +#else
3195 +#define DPRINTK(s, args...)
3196 +#define DENTER()
3197 +#define DEXIT()
3198 +#endif
3199 +
3200 +//#define SPIN_WAIT
3201 +
3202 +/* globals */
3203 +static RAID_T tp;
3204 +static RAID_TXDMA_CTRL_T       txdma_ctrl;
3205 +RAID_RXDMA_CTRL_T                      rxdma_ctrl;
3206 +
3207 +//#ifndef SPIN_WAIT
3208 +static spinlock_t          raid_lock;
3209 +//#endif
3210 +
3211 +static unsigned int     tx_desc_virtual_base;
3212 +static unsigned int     rx_desc_virtual_base;
3213 +RAID_DESCRIPTOR_T      *tx_desc_ptr;
3214 +RAID_DESCRIPTOR_T      *rx_desc_ptr;
3215 +
3216 +/* static prototypes */
3217 +#define DMA_MALLOC(size,handle)                pci_alloc_consistent(NULL,size,handle)
3218 +#define DMA_MFREE(mem,size,handle)     pci_free_consistent(NULL,size,mem,handle)
3219 +
3220 +static int gemini_xor_init_desc(void);
3221 +
3222 +static unsigned int raid_read_reg(unsigned int offset)
3223 +{
3224 +    unsigned int    reg_val;
3225 +
3226 +    reg_val = readl(RAID_BASE_ADDR + offset);
3227 +       return (reg_val);
3228 +}
3229 +
3230 +static void raid_write_reg(unsigned int offset,unsigned int data,unsigned int bit_mask)
3231 +{
3232 +       unsigned int reg_val;
3233 +    unsigned int *addr;
3234 +
3235 +       reg_val = ( raid_read_reg(offset) & (~bit_mask) ) | (data & bit_mask);
3236 +       addr = (unsigned int *)(RAID_BASE_ADDR + offset);
3237 +    writel(reg_val,addr);
3238 +       return;
3239 +}
3240 +
3241 +#ifndef SPIN_WAIT
3242 +__inline__ void xor_queue_descriptor(void)
3243 +{
3244 +       unsigned int flags,status=1;
3245 +
3246 +       DPRINTK("Going to sleep");
3247 +
3248 +       while(status){
3249 +               yield();
3250 +               //schedule();
3251 +               spin_lock_irqsave(&raid_lock,flags);
3252 +               status = tp.busy;
3253 +               spin_unlock_irqrestore(&raid_lock, flags);
3254 +       }
3255 +//     tp.status = COMPLETE;
3256 +       DPRINTK("woken up!");
3257 +
3258 +}
3259 +#endif
3260 +
3261 +#ifdef SPIN_WAIT
3262 +static void gemini_xor_isr(int d_n)
3263 +#else
3264 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28)
3265 +static void gemini_xor_isr(int irq, void *dev_id, struct pt_regs *regs)
3266 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3267 +static irqreturn_t gemini_xor_isr(int irq, void *dev_instance, struct pt_regs *regs)
3268 +#endif
3269 +#endif
3270 +{
3271 +
3272 +       unsigned int err;
3273 +       RAID_DMA_STATUS_T       dma_status;
3274 +//     RAID_DESCRIPTOR_T *rdesc,*tdesc;
3275 +//     unsigned int *paddr;
3276 +
3277 +       dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS);
3278 +#ifdef SPIN_WAIT
3279 +       while( (dma_status.bits32& (1<<31) ) ==0 ){
3280 +               udelay(1);
3281 +               dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS);
3282 +       }
3283 +
3284 +/*     tdesc = tp.tx_first_desc;
3285 +       rdesc = tp.rx_first_desc;
3286 +       for(d_n;d_n>0;d_n--){
3287 +               if( tdesc->func_ctrl.bits.own == DMA ){
3288 +                       paddr = tdesc;
3289 +                       printk("error tx desc:0x%x\n",*paddr++);
3290 +                       printk("error tx desc:0x%x\n",*paddr++);
3291 +                       printk("error tx desc:0s%x\n",*paddr++);
3292 +                       printk("error tx desc:0x%x\n",*paddr);
3293 +                       while(1);
3294 +               }
3295 +               tdesc = (RAID_DESCRIPTOR_T *)((tdesc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3296 +       }
3297 +
3298 +       if( rdesc->func_ctrl.bits.own == DMA ){
3299 +               paddr = rdesc;
3300 +               printk("error rx desc:0x%x\n",*paddr++);
3301 +               printk("error rx desc:0x%x\n",*paddr++);
3302 +               printk("error rx desc:0s%x\n",*paddr++);
3303 +               printk("error rx desc:0x%x\n",*paddr);
3304 +               while(1);
3305 +       }
3306 +*/
3307 +#endif
3308 +
3309 +       if(dma_status.bits32 & ((1<<31)|(1<<26))){
3310 +               // if no bug , we can turn off rx finish interrupt
3311 +               dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS);
3312 +               err = raid_read_reg(RAID_DMA_DEVICE_ID);
3313 +               tp.busy = 0;
3314 +
3315 +               if(err&0x00FF0000){
3316 +                       tp.status = ERROR;
3317 +                       printk("XOR:<HW>%s error code %x\n",(err&0x00F00000)?"tx":"rx",err);
3318 +
3319 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28)
3320 +                       return ;
3321 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3322 +#ifndef SPIN_WAIT
3323 +                       return IRQ_RETVAL(IRQ_HANDLED);
3324 +#endif
3325 +#endif
3326 +               }
3327 +               // 16~19 rx error code
3328 +               // 20~23 tx error codd
3329 +
3330 +               dma_status.bits.tsFinishI = 1;
3331 +               dma_status.bits.rsFinishI = 1;
3332 +               raid_write_reg(RAID_DMA_STATUS, dma_status.bits32,0x84000000);  // clear INT
3333 +
3334 +//             printk("xor %d\n",d_n);
3335 +#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28)
3336 +                       return ;
3337 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3338 +#ifndef SPIN_WAIT
3339 +                       return IRQ_RETVAL(IRQ_HANDLED);
3340 +#endif
3341 +#endif
3342 +       }
3343 +
3344 +       #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,28)
3345 +               return ;
3346 +       #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
3347 +       #ifndef SPIN_WAIT
3348 +               printk("XOR: DMA status register(0x%8x)\n",dma_status.bits32);
3349 +               return IRQ_RETVAL(IRQ_HANDLED);
3350 +       #endif
3351 +       #endif
3352 +}
3353 +
3354 +void
3355 +xor_gemini_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
3356 +{
3357 +       int status=0;
3358 +       unsigned int flags;
3359 +
3360 +       if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3361 +               printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3362 +       }
3363 +
3364 +       spin_lock_irqsave(&raid_lock,flags);
3365 +       while(tp.status != COMPLETE){
3366 +               spin_unlock_irqrestore(&raid_lock, flags);
3367 +               //printk("XOR yield2\n");
3368 +#ifdef XOR_SW_FILL_IN
3369 +               xor_arm4regs_2(bytes,p1,p2);
3370 +               return ;
3371 +#else
3372 +               yield();
3373 +#endif
3374 +       }
3375 +       spin_unlock_irqrestore(&raid_lock, flags);
3376 +       tp.status = RUNNING;
3377 +
3378 +       // flush the cache to memory before H/W XOR touches them
3379 +       consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3380 +       consistent_sync(p2, bytes, DMA_TO_DEVICE);
3381 +
3382 +
3383 +       tp.tx_desc = tp.tx_first_desc;
3384 +       tp.rx_desc = tp.rx_first_desc;
3385 +       if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3386 +               // prepare tx descript
3387 +               raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff);
3388 +               tp.tx_desc->buf_addr = (unsigned int)__pa(p1);          // physical address
3389 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3390 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 2;                 // first descript
3391 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3392 +               tp.tx_desc->flg_status.bits32 = 0x00020000;
3393 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3394 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3395 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3396 +               wmb();
3397 +       tp.tx_desc = tp.tx_cur_desc;
3398 +       tp.tx_desc->buf_addr = (unsigned int)__pa(p2);          // pysical address
3399 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3400 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 1;                 // last descript
3401 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3402 +               tp.tx_desc->flg_status.bits32 = 0x00010000;
3403 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3404 +       tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3405 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);                                                  // keep last descript
3406 +
3407 +       wmb();
3408 +       // prepare rx descript
3409 +       raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFf);
3410 +       tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3411 +       tp.rx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3412 +       tp.rx_desc->flg_status.bits32 = 0;                              // link data from XOR
3413 +//     tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3414 +       tp.rx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3415 +       tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3416 +
3417 +       }
3418 +       else{
3419 +               /* no free tx descriptor */
3420 +               printk("XOR:no free tx descript");
3421 +               return ;
3422 +       }
3423 +
3424 +       // change status
3425 +//     tp.status = RUNNING;
3426 +       status = tp.busy = 1;
3427 +
3428 +       // start tx DMA
3429 +       rxdma_ctrl.bits.rd_start = 1;
3430 +       // start rx DMA
3431 +       txdma_ctrl.bits.td_start = 1;
3432 +
3433 +       raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3434 +       raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3435 +
3436 +#ifdef SPIN_WAIT
3437 +       gemini_xor_isr(2);
3438 +#else
3439 +       xor_queue_descriptor();
3440 +#endif
3441 +
3442 +       tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*2) ;
3443 +       tp.status = COMPLETE;
3444 +//     tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3445 +//     tp.rx_desc = tp.rx_first_desc ;
3446 +//     tp.rx_desc->func_ctrl.bits.own = DMA;
3447 +
3448 +}
3449 +
3450 +void
3451 +xor_gemini_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
3452 +               unsigned long *p3)
3453 +{
3454 +       int status=0;
3455 +       unsigned int flags;
3456 +
3457 +       if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3458 +               printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3459 +       }
3460 +
3461 +       spin_lock_irqsave(&raid_lock,flags);
3462 +       if(tp.status != COMPLETE){
3463 +               spin_unlock_irqrestore(&raid_lock, flags);
3464 +               //printk("XOR yield3\n");
3465 +#ifdef XOR_SW_FILL_IN
3466 +               xor_arm4regs_3(bytes,p1,p2,p3);
3467 +               return;
3468 +#else
3469 +               yield();
3470 +#endif
3471 +       }
3472 +       spin_unlock_irqrestore(&raid_lock, flags);
3473 +       tp.status = RUNNING;
3474 +
3475 +       // flush the cache to memory before H/W XOR touches them
3476 +       consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3477 +       consistent_sync(p2, bytes, DMA_TO_DEVICE);
3478 +       consistent_sync(p3, bytes, DMA_TO_DEVICE);
3479 +
3480 +       tp.tx_desc = tp.tx_first_desc;
3481 +       tp.rx_desc = tp.rx_first_desc;
3482 +       if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3483 +               // prepare tx descript
3484 +               raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff);
3485 +               tp.tx_desc->buf_addr = (unsigned int)__pa(p1);          // physical address
3486 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3487 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 2;                 // first descript
3488 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3489 +               tp.tx_desc->flg_status.bits32 = 0x00020000;
3490 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3491 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3492 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3493 +
3494 +       tp.tx_desc = tp.tx_cur_desc;
3495 +       tp.tx_desc->buf_addr = (unsigned int)__pa(p2);          // pysical address
3496 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3497 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 0;                 // first descript
3498 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3499 +               tp.tx_desc->flg_status.bits32 = 0x0000000;
3500 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3501 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3502 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3503 +
3504 +       tp.tx_desc = tp.tx_cur_desc;
3505 +       tp.tx_desc->buf_addr = (unsigned int)__pa(p3);          // pysical address
3506 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3507 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 1;                 // last descript
3508 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3509 +               tp.tx_desc->flg_status.bits32 = 0x00010000;
3510 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3511 +       tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3512 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);                                                  // keep last descript
3513 +
3514 +       // prepare rx descript
3515 +       raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFf);
3516 +       tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3517 +       tp.rx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3518 +       tp.rx_desc->flg_status.bits32 = 0;                              // link data from XOR
3519 +//     tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3520 +       tp.rx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3521 +       tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3522 +
3523 +       }
3524 +       else{
3525 +               /* no free tx descriptor */
3526 +               printk("XOR:no free tx descript \n");
3527 +               return ;
3528 +       }
3529 +
3530 +       // change status
3531 +//     tp.status = RUNNING;
3532 +       status = tp.busy = 1;
3533 +
3534 +       // start tx DMA
3535 +       rxdma_ctrl.bits.rd_start = 1;
3536 +       // start rx DMA
3537 +       txdma_ctrl.bits.td_start = 1;
3538 +       wmb();
3539 +       raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3540 +       raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3541 +
3542 +#ifdef SPIN_WAIT
3543 +       gemini_xor_isr(3);
3544 +#else
3545 +       xor_queue_descriptor();
3546 +#endif
3547 +       tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*3) | 0x0B;
3548 +       tp.status = COMPLETE;
3549 +//     tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) | 0x0B;
3550 +       //tp.rx_desc = tp.rx_first_desc ;
3551 +//     tp.rx_desc->func_ctrl.bits.own = DMA;
3552 +
3553 +}
3554 +
3555 +void
3556 +xor_gemini_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
3557 +               unsigned long *p3, unsigned long *p4)
3558 +{
3559 +       int status=0;
3560 +       unsigned int flags;
3561 +
3562 +       if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3563 +               printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3564 +       }
3565 +
3566 +       spin_lock_irqsave(&raid_lock,flags);
3567 +       if(tp.status != COMPLETE){
3568 +               spin_unlock_irqrestore(&raid_lock, flags);
3569 +               //printk("S\n");
3570 +#ifdef XOR_SW_FILL_IN
3571 +               xor_arm4regs_4(bytes,p1,p2,p3,p4);
3572 +               return;
3573 +#else
3574 +               msleep(1);
3575 +               yield();
3576 +#endif
3577 +       }
3578 +       spin_unlock_irqrestore(&raid_lock, flags);
3579 +
3580 +       tp.status = RUNNING;
3581 +
3582 +       // flush the cache to memory before H/W XOR touches them
3583 +       consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3584 +       consistent_sync(p2, bytes, DMA_TO_DEVICE);
3585 +       consistent_sync(p3, bytes, DMA_TO_DEVICE);
3586 +       consistent_sync(p4, bytes, DMA_TO_DEVICE);
3587 +
3588 +       tp.tx_desc = tp.tx_first_desc;
3589 +       tp.rx_desc = tp.rx_first_desc;
3590 +       if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3591 +               // prepare tx descript
3592 +               raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff);
3593 +               tp.tx_desc->buf_addr = (unsigned int)__pa(p1);          // physical address
3594 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3595 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 2;                 // first descript
3596 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3597 +               tp.tx_desc->flg_status.bits32 = 0x00020000;
3598 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3599 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3600 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3601 +
3602 +       tp.tx_desc = tp.tx_cur_desc;
3603 +       tp.tx_cur_desc->buf_addr = (unsigned int)__pa(p2);              // pysical address
3604 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3605 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 0;                 // first descript
3606 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3607 +               tp.tx_desc->flg_status.bits32 = 0x00000000;
3608 +       tp.tx_cur_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3609 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3610 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3611 +
3612 +       tp.tx_desc = tp.tx_cur_desc;
3613 +       tp.tx_desc->buf_addr = (unsigned int)__pa(p3);          // pysical address
3614 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3615 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 0;                 // first descript
3616 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3617 +               tp.tx_desc->flg_status.bits32 = 0x00000000;
3618 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3619 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3620 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3621 +
3622 +
3623 +       tp.tx_desc = tp.tx_cur_desc;
3624 +       tp.tx_desc->buf_addr = (unsigned int)__pa(p4);          // pysical address
3625 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3626 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 1;                 // last descript
3627 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3628 +               tp.tx_desc->flg_status.bits32 = 0x00010000;
3629 +//     tp.tx_cur_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3630 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3631 +       tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3632 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);                                                  // keep last descript
3633 +
3634 +       // prepare rx descript
3635 +       raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF);
3636 +       tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3637 +       tp.rx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3638 +       tp.rx_desc->flg_status.bits32 = 0;                              // link data from XOR
3639 +//     tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3640 +       tp.rx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3641 +       tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3642 +
3643 +       }
3644 +       else{
3645 +               /* no free tx descriptor */
3646 +               printk("XOR:no free tx descript");
3647 +               return ;
3648 +       }
3649 +
3650 +       // change status
3651 +//     tp.status = RUNNING;
3652 +       status = tp.busy = 1;
3653 +
3654 +       // start tx DMA
3655 +       rxdma_ctrl.bits.rd_start = 1;
3656 +       // start rx DMA
3657 +       txdma_ctrl.bits.td_start = 1;
3658 +       wmb();
3659 +       raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3660 +       raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3661 +
3662 +#ifdef SPIN_WAIT
3663 +       gemini_xor_isr(4);
3664 +#else
3665 +       xor_queue_descriptor();
3666 +#endif
3667 +
3668 +       tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*4) | 0x0B;
3669 +       tp.status = COMPLETE;
3670 +//     tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) | 0x0B;
3671 +       //tp.rx_desc = tp.rx_first_desc ;
3672 +//     tp.rx_desc->func_ctrl.bits.own = DMA;
3673 +
3674 +}
3675 +
3676 +void
3677 +xor_gemini_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
3678 +               unsigned long *p3, unsigned long *p4, unsigned long *p5)
3679 +{
3680 +
3681 +       int status=0;
3682 +       unsigned int flags;
3683 +
3684 +
3685 +       if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3686 +               printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3687 +       }
3688 +
3689 +       spin_lock_irqsave(&raid_lock,flags);
3690 +       while(tp.status != COMPLETE){
3691 +               spin_unlock_irqrestore(&raid_lock, flags);
3692 +               //printk("XOR yield5\n");
3693 +#ifdef XOR_SW_FILL_IN
3694 +               xor_arm4regs_5(bytes,p1,p2,p3,p4,p5);
3695 +               return;
3696 +#else
3697 +               msleep(1);
3698 +               yield();
3699 +#endif
3700 +       }
3701 +       spin_unlock_irqrestore(&raid_lock, flags);
3702 +       tp.status = RUNNING;
3703 +
3704 +       // flush the cache to memory before H/W XOR touches them
3705 +       consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3706 +       consistent_sync(p2, bytes, DMA_TO_DEVICE);
3707 +       consistent_sync(p3, bytes, DMA_TO_DEVICE);
3708 +       consistent_sync(p4, bytes, DMA_TO_DEVICE);
3709 +       consistent_sync(p5, bytes, DMA_TO_DEVICE);
3710 +
3711 +       tp.tx_desc = tp.tx_first_desc;
3712 +       tp.rx_desc = tp.rx_first_desc;
3713 +       if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3714 +               // prepare tx descript
3715 +               raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xffffffff);
3716 +               tp.tx_desc->buf_addr = (unsigned int)__pa(p1);          // physical address
3717 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3718 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 2;                 // first descript
3719 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3720 +               tp.tx_desc->flg_status.bits32 = 0x00020000;
3721 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3722 +       wmb();
3723 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3724 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3725 +
3726 +       tp.tx_desc = tp.tx_cur_desc;
3727 +       tp.tx_desc->buf_addr = (unsigned int)__pa(p2);          // pysical address
3728 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3729 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 0;                 // first descript
3730 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3731 +               tp.tx_desc->flg_status.bits32 = 0x00000000;
3732 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3733 +       wmb();
3734 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3735 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3736 +
3737 +       tp.tx_desc = tp.tx_cur_desc;
3738 +       tp.tx_desc->buf_addr = (unsigned int)__pa(p3);          // pysical address
3739 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3740 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 0;                 // first descript
3741 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3742 +               tp.tx_desc->flg_status.bits32 = 0x00000000;
3743 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3744 +       wmb();
3745 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3746 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3747 +
3748 +               tp.tx_desc = tp.tx_cur_desc;
3749 +       tp.tx_desc->buf_addr = (unsigned int)__pa(p4);          // pysical address
3750 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3751 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 0;                 // first descript
3752 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3753 +               tp.tx_desc->flg_status.bits32 = 0x00000000;
3754 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3755 +       wmb();
3756 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3757 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3758 +
3759 +
3760 +       tp.tx_desc = tp.tx_cur_desc;
3761 +       tp.tx_desc->buf_addr = (unsigned int)__pa(p5);          // pysical address
3762 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3763 +//     tp.tx_desc->flg_status.bits_cmd_status.bcc = 1;                 // last descript
3764 +//     tp.tx_desc->flg_status.bits_cmd_status.mode = 0;                // only support XOR command
3765 +//     tp.tx_cur_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3766 +               tp.tx_desc->flg_status.bits32 = 0x00010000;
3767 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3768 +       tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3769 +       tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xfffffff0)+tx_desc_virtual_base);
3770 +       tp.tx_finished_desc = tp.tx_desc;                                                               // keep last descript
3771 +
3772 +       // prepare rx descript
3773 +       raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF);
3774 +       tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3775 +       tp.rx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3776 +       tp.rx_desc->flg_status.bits32 = 0;                              // link data from XOR
3777 +//     tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3778 +       tp.rx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3779 +       tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3780 +
3781 +       }
3782 +       else{
3783 +               /* no free tx descriptor */
3784 +               printk("XOR:no free tx descript");
3785 +               return ;
3786 +       }
3787 +
3788 +       // change status
3789 +//     tp.status = RUNNING;
3790 +       status = tp.busy = 1;
3791 +
3792 +       // start tx DMA
3793 +       rxdma_ctrl.bits.rd_start = 1;
3794 +       // start rx DMA
3795 +       txdma_ctrl.bits.td_start = 1;
3796 +       wmb();
3797 +       raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3798 +       raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3799 +
3800 +#ifdef SPIN_WAIT
3801 +       gemini_xor_isr(5);
3802 +#else
3803 +       xor_queue_descriptor();
3804 +#endif
3805 +
3806 +       tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*5) | 0x0B;
3807 +       tp.status = COMPLETE;
3808 +//     tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) | 0x0B;
3809 +       //tp.rx_desc = tp.rx_first_desc ;
3810 +//     tp.rx_desc->func_ctrl.bits.own = DMA;
3811 +
3812 +}
3813 +
3814 +#ifdef XOR_TEST
3815 +void
3816 +raid_memset(unsigned int *p1, unsigned int pattern, unsigned int bytes)
3817 +{
3818 +       int status=0,i;
3819 +
3820 +       if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3821 +               printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3822 +       }
3823 +
3824 +       *p1 = pattern;
3825 +
3826 +       // flush the cache to memory before H/W XOR touches them
3827 +       consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
3828 +
3829 +       while(tp.status != COMPLETE){
3830 +               DPRINTK("XOR yield\n");
3831 +               //schedule();
3832 +               yield();
3833 +       }
3834 +       tp.status = RUNNING;
3835 +
3836 +       tp.tx_desc = tp.tx_first_desc;
3837 +       tp.rx_desc = tp.rx_first_desc;
3838 +       if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3839 +               // prepare tx descript
3840 +               raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xFFFFFFFF);
3841 +               tp.tx_desc->buf_addr = (unsigned int)__pa(p1);          // physical address
3842 +       tp.tx_desc->func_ctrl.bits.buffer_size = 4;             /* total frame byte count */
3843 +       tp.tx_desc->flg_status.bits_cmd_status.bcc = bytes;                     // bytes to fill
3844 +       tp.tx_desc->flg_status.bits_cmd_status.mode = CMD_FILL;         // only support memory FILL command
3845 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3846 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3847 +       tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;
3848 +//     tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xFFFFFFF0)+tx_desc_virtual_base);
3849 +
3850 +       // prepare rx descript
3851 +       raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF);
3852 +       tp.rx_desc->buf_addr = (unsigned int)__pa(p1);
3853 +       tp.rx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3854 +       tp.rx_desc->flg_status.bits32 = 0;                              // link data from XOR
3855 +       tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3856 +       tp.rx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3857 +//     tp.rx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.rx_cur_desc->next_desc_addr.bits32 & 0xfffffff0)+rx_desc_virtual_base);
3858 +       tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3859 +       tp.rx_finished_desc = tp.rx_desc;
3860 +
3861 +       }
3862 +       else{
3863 +               /* no free tx descriptor */
3864 +               printk("XOR:no free tx descript");
3865 +               return ;
3866 +       }
3867 +
3868 +       // change status
3869 +       //tp.status = RUNNING;
3870 +       status = tp.busy = 1;
3871 +
3872 +       // start tx DMA
3873 +       rxdma_ctrl.bits.rd_start = 1;
3874 +       // start rx DMA
3875 +       txdma_ctrl.bits.td_start = 1;
3876 +
3877 +       raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3878 +       raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3879 +
3880 +#ifdef SPIN_WAIT
3881 +       gemini_xor_isr(2);
3882 +#else
3883 +       xor_queue_descriptor();
3884 +#endif
3885 +
3886 +       for(i=1; i<(bytes/sizeof(int)); i++) {
3887 +               if(p1[0]!=p1[i]){
3888 +                       printk("pattern set error!\n");
3889 +                       while(1);
3890 +               }
3891 +       }
3892 +
3893 +       tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3894 +       tp.status = COMPLETE;
3895 +//     tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3896 +       //tp.rx_desc = tp.rx_first_desc ;
3897 +//     tp.rx_desc->func_ctrl.bits.own = DMA;
3898 +
3899 +}
3900 +#endif
3901 +
3902 +void
3903 +raid_memcpy(unsigned int *to, unsigned int *from, unsigned int bytes)
3904 +{
3905 +       int status=0,i;
3906 +
3907 +       if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3908 +               printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3909 +       }
3910 +
3911 +       // flush the cache to memory before H/W XOR touches them
3912 +       consistent_sync(to, bytes, DMA_BIDIRECTIONAL);
3913 +       consistent_sync(from,bytes, DMA_TO_DEVICE);
3914 +
3915 +       while(tp.status != COMPLETE){
3916 +               DPRINTK("XOR yield\n");
3917 +               //schedule();
3918 +               yield();
3919 +       }
3920 +       tp.status = RUNNING;
3921 +
3922 +       tp.tx_desc = tp.tx_first_desc;
3923 +       tp.rx_desc = tp.rx_first_desc;
3924 +       if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
3925 +               // prepare tx descript
3926 +               raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xFFFFFFFF);
3927 +               tp.tx_desc->buf_addr = (unsigned int)__pa(from);                // physical address
3928 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3929 +       tp.tx_desc->flg_status.bits32 = CMD_CPY;                // only support memory FILL command
3930 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3931 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3932 +       tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;
3933 +//     tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xFFFFFFF0)+tx_desc_virtual_base);
3934 +
3935 +       // prepare rx descript
3936 +       raid_write_reg(RAID_STRDMA_CURR_DESC,(unsigned int)tp.rx_desc-rx_desc_virtual_base,0xFFFFFFFF);
3937 +       tp.rx_desc->buf_addr = (unsigned int)__pa(to);
3938 +       tp.rx_desc->func_ctrl.bits.buffer_size = bytes;                 /* total frame byte count */
3939 +       tp.rx_desc->flg_status.bits32 = 0;                              // link data from XOR
3940 +       tp.rx_cur_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
3941 +       tp.rx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
3942 +//     tp.rx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.rx_cur_desc->next_desc_addr.bits32 & 0xfffffff0)+rx_desc_virtual_base);
3943 +       tp.rx_desc->next_desc_addr.bits32 = 0x0000000b;// end of descript
3944 +
3945 +       }
3946 +       else{
3947 +               /* no free tx descriptor */
3948 +               printk("XOR:no free tx descript");
3949 +               return ;
3950 +       }
3951 +
3952 +       // change status
3953 +       //tp.status = RUNNING;
3954 +       status = tp.busy = 1;
3955 +
3956 +       // start tx DMA
3957 +       rxdma_ctrl.bits.rd_start = 1;
3958 +       // start rx DMA
3959 +       txdma_ctrl.bits.td_start = 1;
3960 +
3961 +       raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
3962 +       raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
3963 +
3964 +#ifdef SPIN_WAIT
3965 +       gemini_xor_isr(2);
3966 +#else
3967 +       xor_queue_descriptor();
3968 +#endif
3969 +
3970 +#ifdef XOR_TEST
3971 +       for(i=1; i<(bytes/sizeof(int)); i++) {
3972 +               if(to[i]!=from[i]){
3973 +                       printk("pattern check error!\n");
3974 +                       printk("offset=0x%x p1=%x p2=%x\n",i*4,to[i],from[i]);
3975 +                       while(1);
3976 +               }
3977 +       }
3978 +#endif
3979 +
3980 +       tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3981 +       tp.status = COMPLETE;
3982 +//     tp.rx_desc->next_desc_addr.bits32 = ((unsigned long)tp.rx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
3983 +       //tp.rx_desc = tp.rx_first_desc ;
3984 +//     tp.rx_desc->func_ctrl.bits.own = DMA;
3985 +
3986 +}
3987 +EXPORT_SYMBOL(raid_memcpy);
3988 +
3989 +#ifdef XOR_TEST
3990 +int
3991 +raid_memchk(unsigned int *p1, unsigned int pattern, unsigned int bytes)
3992 +{
3993 +       int status=0;
3994 +       RAID_DMA_STATUS_T       dma_status;
3995 +
3996 +       if(bytes > (1<<(SRAM_PAR_SIZE+11))){
3997 +               printk("XOR: out of SRAM partition!![0x%x]\n",(unsigned int)bytes);
3998 +       }
3999 +
4000 +       status = ((pattern&0xFFFF)%bytes )/4;
4001 +       p1[status] = pattern;
4002 +
4003 +       while(tp.status != COMPLETE){
4004 +               DPRINTK("XOR yield\n");
4005 +               //schedule();
4006 +               yield();
4007 +       }
4008 +       tp.status = RUNNING;
4009 +
4010 +       // flush the cache to memory before H/W XOR touches them
4011 +       consistent_sync(p1, bytes, DMA_BIDIRECTIONAL);
4012 +
4013 +       tp.tx_desc = tp.tx_first_desc;
4014 +       if((tp.tx_desc->func_ctrl.bits.own == CPU)/*&&(tp.rx_desc->func_ctrl.bits.own == DMA)*/){
4015 +               // prepare tx descript
4016 +               raid_write_reg(RAID_FCHDMA_CURR_DESC,(unsigned int)tp.tx_desc-tx_desc_virtual_base,0xFFFFFFFF);
4017 +               tp.tx_desc->buf_addr = (unsigned int)__pa(p1);          // physical address
4018 +       tp.tx_desc->func_ctrl.bits.raid_ctrl_status = 0;
4019 +       tp.tx_desc->func_ctrl.bits.buffer_size = bytes ;                /* total frame byte count */
4020 +       tp.tx_desc->flg_status.bits32 = CMD_CHK;                // only support memory FILL command
4021 +       tp.tx_desc->next_desc_addr.bits.sof_eof = 0x03;          /*only one descriptor*/
4022 +       tp.tx_desc->func_ctrl.bits.own = DMA;                           /* set owner bit */
4023 +       tp.tx_desc->next_desc_addr.bits32 = 0x0000000b;
4024 +//     tp.tx_cur_desc = (RAID_DESCRIPTOR_T *)((tp.tx_desc->next_desc_addr.bits32 & 0xFFFFFFF0)+tx_desc_virtual_base);
4025 +
4026 +       }
4027 +       else{
4028 +               /* no free tx descriptor */
4029 +               printk("XOR:no free tx descript");
4030 +               return -1;
4031 +       }
4032 +
4033 +       // change status
4034 +       //tp.status = RUNNING;
4035 +       status = tp.busy = 1;
4036 +
4037 +       // start tx DMA
4038 +       txdma_ctrl.bits.td_start = 1;
4039 +
4040 +       raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0x80000000);
4041 +//     raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0x80000000);
4042 +
4043 +#ifdef SPIN_WAIT
4044 +       gemini_xor_isr(2);
4045 +#else
4046 +       xor_queue_descriptor();
4047 +#endif
4048 +
4049 +//     dma_status.bits32 = raid_read_reg(RAID_DMA_STATUS);
4050 +//     if (dma_status.bits32 & (1<<15))        {
4051 +
4052 +       if((tp.tx_first_desc->func_ctrl.bits.raid_ctrl_status & 0x2)) {
4053 +               status = 1;
4054 +//             raid_write_reg(RAID_DMA_STATUS,0x00008000,0x00080000);
4055 +       }
4056 +       else{
4057 +               status = 0;
4058 +       }
4059 +
4060 +       tp.tx_desc->next_desc_addr.bits32 = ((unsigned long)tp.tx_first_desc - tx_desc_virtual_base + sizeof(RAID_DESCRIPTOR_T)*1) ;
4061 +       tp.status = COMPLETE;
4062 +//     tp.rx_desc->func_ctrl.bits.own = DMA;
4063 +       return status ;
4064 +}
4065 +#endif
4066 +
4067 +int __init gemini_xor_init(void)
4068 +{
4069 +       unsigned int res;
4070 +       unsigned int *paddr1,*paddr2,*paddr3,i;
4071 +       unsigned volatile char  *charact;
4072 +       unsigned volatile short *two_char;
4073 +       unsigned volatile int   *four_char;
4074 +
4075 +       // init descript
4076 +       res = gemini_xor_init_desc();
4077 +       if(res) {
4078 +               printk("Init RAID Descript Fail!!\n");
4079 +               return -res;
4080 +       }
4081 +
4082 +       tp.device_name = "Gemini XOR Acceleration";
4083 +
4084 +       // request irq
4085 +#ifndef SPIN_WAIT
4086 +       res = request_irq(IRQ_RAID, gemini_xor_isr, SA_INTERRUPT, tp.device_name, NULL);
4087 +#endif
4088 +       if(res){
4089 +               printk(KERN_ERR "%s: unable to request IRQ %d for "
4090 +                      "HW XOR %d\n", tp.device_name, IRQ_RAID, res);
4091 +               return -EBUSY;
4092 +       }
4093 +
4094 +#ifdef XOR_TEST
4095 +
4096 +RETEST:
4097 +       paddr1 = kmalloc(0x1000,GFP_KERNEL);
4098 +       paddr2 = kmalloc(0x1000,GFP_KERNEL);
4099 +       paddr3 = kmalloc(0x1000,GFP_KERNEL);
4100 +       for(i=0;i<TEST_ITERATION;i++) {
4101 +               printk("XOR test round %d\n",i);
4102 +               for(res=0;res<(0x1000)/sizeof(int);res++){              // prepare data pattern
4103 +                       paddr1[res]= readl(0xf62000ac);
4104 +                       paddr2[res]= readl(0xf62000ac);
4105 +               }
4106 +               for(res=0;res<0x1000/sizeof(int);res++){                // calculate xor by software
4107 +                       paddr3[res] = paddr1[res]^paddr2[res];
4108 +               }
4109 +               xor_gemini_2(0x1000,paddr1,paddr2);                             // calculate xor by hw
4110 +               for(res=0;res<0x1000/sizeof(int);res++){                // check error
4111 +                       if(paddr1[res]!=paddr3[res]){
4112 +                               printk("XOR ERROR\n");
4113 +                               printk("[%d][0x%x]=0x%x should be %x\n",res,&paddr1[res],paddr1[res],paddr3[res]);
4114 +                               while(1);
4115 +                       }
4116 +               }
4117 +       }
4118 +       kfree(paddr1);
4119 +       kfree(paddr2);
4120 +       kfree(paddr3);
4121 +
4122 +
4123 +       // memcpy test
4124 +       paddr1 = kmalloc(0x4000,GFP_KERNEL);
4125 +       for(i=0;i<TEST_ITERATION;i++) {
4126 +               for(res=0;res<(0x4000)/sizeof(int);res++)
4127 +                       paddr1[res]= readl(0xf62000ac);
4128 +
4129 +               printk("MEMCOPY round %d\n",i);
4130 +               paddr2 = kmalloc(0x4000,GFP_KERNEL);
4131 +               raid_memcpy(paddr2,paddr1,0x4000);
4132 +               kfree(paddr2);
4133 +       }
4134 +       kfree(paddr1);
4135 +
4136 +       // memset test
4137 +       for(i=0;i<TEST_ITERATION;i++) {
4138 +               raid_memset(paddr1,0xFFFFFFFF,0x4000);
4139 +               res = readl(0xf62000ac);
4140 +               printk("MEMFILL fill 0x%x round %d\n",res,i);
4141 +               paddr1 = kmalloc(0x4000,GFP_KERNEL);
4142 +               raid_memset(paddr1,res,0x4000);
4143 +               raid_memset(paddr1,0x0,0x4000);
4144 +               kfree(paddr1);
4145 +       }
4146 +
4147 +       paddr1 = kmalloc(0x4000,GFP_KERNEL);
4148 +       for(i=0;i<TEST_ITERATION;i++){
4149 +               raid_memset(paddr1, i,0x4000);
4150 +               printk("Pattern check same ? ");
4151 +               res = raid_memchk(paddr1, i,0x4000);
4152 +               printk("%s\n",res?"Fail":"OK");
4153 +               if(res) while(1);
4154 +
4155 +               printk("Pattern check diff ? ");
4156 +               res = raid_memchk(paddr1,readl(0xf62000ac),0x4000);
4157 +               printk("%s\n",res?"OK":"Fail");
4158 +               if(!res)        while(1);
4159 +       }
4160 +       kfree(paddr1);
4161 +
4162 +       // SRAM test
4163 +       raid_write_reg(RAID_PCR, 0,0x00000003);
4164 +       for(i=0;i<TEST_ITERATION;i++) {
4165 +               printk("SRAM test %d\n",i);
4166 +               charact = 0xF7000000;
4167 +               two_char = 0xF7000000;
4168 +               four_char = 0xF7000000;
4169 +               for(res=0;res<(16*1024)/sizeof(char);res++) {           // 8-bit access
4170 +                       *charact++ = (unsigned char)res;
4171 +               }
4172 +               charact = 0xF7000000;
4173 +               for(res=0;res<(16*1024)/sizeof(char);res++) {
4174 +                       if(*charact++ != (unsigned char)res){
4175 +                               printk("SRAM data error(8)\n");
4176 +                               while(1);
4177 +                       }
4178 +               }
4179 +
4180 +               for(res=0;res<(16*1024)/sizeof(short);res++) {          // 16-bit access
4181 +                       *two_char++ = (unsigned short)res;
4182 +               }
4183 +               two_char = 0xF7000000;
4184 +               for(res=0;res<(16*1024)/sizeof(short);res++) {
4185 +                       if(*two_char++ != (unsigned short)res){
4186 +                               printk("SRAM data error(16)\n");
4187 +                               while(1);
4188 +                       }
4189 +               }
4190 +
4191 +               for(res=0;res<(16*1024)/sizeof(int);res++) {            // 32-bit access
4192 +                       *four_char++ = (unsigned int)res;
4193 +               }
4194 +               four_char = 0xF7000000;
4195 +               for(res=0;res<(16*1024)/sizeof(int);res++) {
4196 +                       if(*four_char++ != (unsigned int)res){
4197 +                               printk("SRAM data error(32)\n");
4198 +                               while(1);
4199 +                       }
4200 +               }
4201 +       }
4202 +       raid_write_reg(RAID_PCR, SRAM_PAR_SIZE,0x00000003);
4203 +
4204 +#endif
4205 +       return 0;
4206 +}
4207 +
4208 +void __exit gemini_xor_exit(void)
4209 +{
4210 +       DMA_MFREE(tp.tx_desc, TX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(unsigned int)tp.tx_desc_dma);
4211 +       DMA_MFREE(tp.rx_desc, RX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(unsigned int)tp.rx_desc_dma);
4212 +       free_irq(IRQ_RAID, NULL);
4213 +}
4214 +
4215 +
4216 +static int gemini_xor_init_desc(void)
4217 +{
4218 +       unsigned int i;
4219 +       dma_addr_t          tx_first_desc_dma;
4220 +       dma_addr_t          rx_first_desc_dma;
4221 +       RAID_DMA_STATUS_T       dma_status;
4222 +
4223 +       printk("Initial RAID Descripter...\n");
4224 +
4225 +       tp.tx_desc = (RAID_DESCRIPTOR_T*)DMA_MALLOC(TX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(dma_addr_t *)&tp.tx_desc_dma);
4226 +    tx_desc_virtual_base = (unsigned int)tp.tx_desc - (unsigned int)tp.tx_desc_dma;
4227 +    memset(tp.tx_desc,0x00,TX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T));
4228 +
4229 +       tp.rx_desc = (RAID_DESCRIPTOR_T*)DMA_MALLOC(RX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(dma_addr_t *)&tp.rx_desc_dma);
4230 +    rx_desc_virtual_base = (unsigned int)tp.rx_desc - (unsigned int)tp.rx_desc_dma;
4231 +    memset(tp.rx_desc,0x00,RX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T));
4232 +       printk("XOR:tx_desc = %08x\n",(unsigned int)tp.tx_desc);
4233 +    printk("XOR:rx_desc = %08x\n",(unsigned int)tp.rx_desc);
4234 +       printk("XOR:tx_desc_dma = %08x\n",(unsigned int)tp.tx_desc_dma);
4235 +       printk("XOR:rx_desc_dma = %08x\n",(unsigned int)tp.rx_desc_dma);
4236 +
4237 +       if ((tp.tx_desc == NULL) || (tp.rx_desc == NULL)) {
4238 +               if (tp.tx_desc)
4239 +                       DMA_MFREE(tp.tx_desc, TX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(dma_addr_t)tp.tx_desc_dma);
4240 +               if (tp.rx_desc)
4241 +                       DMA_MFREE(tp.rx_desc, RX_DESC_NUM*sizeof(RAID_DESCRIPTOR_T),(dma_addr_t)tp.rx_desc_dma);
4242 +               return -ENOMEM;
4243 +       }
4244 +
4245 +       tp.tx_cur_desc = tp.tx_desc;  /* virtual address */
4246 +       tp.tx_finished_desc = tp.tx_desc; /* virtual address */
4247 +       tx_first_desc_dma = (dma_addr_t)tp.tx_desc_dma; /* physical address */
4248 +       for (i = 1; i < TX_DESC_NUM; i++) {
4249 +               tp.tx_desc->func_ctrl.bits.own = CPU;
4250 +               tp.tx_desc->func_ctrl.bits.buffer_size = 0;
4251 +               tp.tx_desc_dma = tp.tx_desc_dma + sizeof(RAID_DESCRIPTOR_T);
4252 +//             tp.tx_desc->next_desc_addr.bits32 = (unsigned int)tp.tx_desc_dma | 0x0B;
4253 +               tp.tx_desc->next_desc_addr.bits32 = ((unsigned int)tx_first_desc_dma | 0x0B) + i*0x10;
4254 +               tp.tx_desc = &tp.tx_desc[1];
4255 +       }
4256 +       tp.tx_desc->func_ctrl.bits.own = DMA;
4257 +       tp.tx_desc->next_desc_addr.bits32 = (unsigned int)tx_first_desc_dma|0x0b;
4258 +       tp.tx_desc = tp.tx_cur_desc;
4259 +       tp.tx_desc_dma = (unsigned int*)tx_first_desc_dma;
4260 +       tp.tx_first_desc = tp.tx_desc ;
4261 +
4262 +       tp.rx_cur_desc = tp.rx_desc;  /* virtual address */
4263 +       tp.rx_finished_desc = tp.rx_desc; /* virtual address */
4264 +       rx_first_desc_dma = (dma_addr_t)tp.rx_desc_dma; /* physical address */
4265 +       for (i = 1; i < RX_DESC_NUM; i++) {
4266 +               tp.rx_desc->func_ctrl.bits.own = DMA;
4267 +               tp.rx_desc->func_ctrl.bits.buffer_size = 0;
4268 +               tp.rx_desc_dma = tp.rx_desc_dma + sizeof(RAID_DESCRIPTOR_T);
4269 +//             tp.rx_desc->next_desc_addr.bits32 = (unsigned int)tp.rx_desc_dma | 0x0B;
4270 +               tp.rx_desc->next_desc_addr.bits32 = ((unsigned int)rx_first_desc_dma | 0x0B) + i*0x10;
4271 +               tp.rx_desc = &tp.rx_desc[1];
4272 +       }
4273 +       tp.rx_desc->func_ctrl.bits.own = DMA;
4274 +       tp.rx_desc->next_desc_addr.bits32 = rx_first_desc_dma|0x0b;
4275 +       tp.rx_desc = tp.rx_cur_desc;
4276 +       tp.rx_desc_dma = (unsigned int*)rx_first_desc_dma;
4277 +       tp.rx_first_desc = tp.rx_desc ;
4278 +       tp.busy = 0;
4279 +       tp.status = COMPLETE;
4280 +
4281 +       // Partition SRAM size
4282 +       raid_write_reg(RAID_PCR, SRAM_PAR_SIZE,0x00000003);
4283 +
4284 +       // config tx DMA controler
4285 +       txdma_ctrl.bits32 = 0;
4286 +       txdma_ctrl.bits.td_start = 0;
4287 +       txdma_ctrl.bits.td_continue = 1;
4288 +       txdma_ctrl.bits.td_chain_mode = 1;
4289 +       txdma_ctrl.bits.td_prot = 0;
4290 +       txdma_ctrl.bits.td_burst_size = 1;
4291 +       txdma_ctrl.bits.td_bus = 3;
4292 +       txdma_ctrl.bits.td_endian = 0;
4293 +       txdma_ctrl.bits.td_finish_en = 1;
4294 +       txdma_ctrl.bits.td_fail_en = 1;
4295 +       txdma_ctrl.bits.td_perr_en = 1;
4296 +       txdma_ctrl.bits.td_eod_en = 0;  // enable tx descript
4297 +       txdma_ctrl.bits.td_eof_en = 0;
4298 +       raid_write_reg(RAID_FCHDMA_CTRL, txdma_ctrl.bits32,0xFFFFFFFF);
4299 +
4300 +       // config rx DMA controler
4301 +       rxdma_ctrl.bits32 = 0;
4302 +       rxdma_ctrl.bits.rd_start = 0;
4303 +       rxdma_ctrl.bits.rd_continue = 1;
4304 +       rxdma_ctrl.bits.rd_chain_mode = 1;
4305 +       rxdma_ctrl.bits.rd_prot = 0;
4306 +       rxdma_ctrl.bits.rd_burst_size = 1;
4307 +       rxdma_ctrl.bits.rd_bus = 3;
4308 +       rxdma_ctrl.bits.rd_endian = 0;
4309 +       rxdma_ctrl.bits.rd_finish_en = 0;
4310 +       rxdma_ctrl.bits.rd_fail_en = 1;
4311 +       rxdma_ctrl.bits.rd_perr_en = 1;
4312 +       rxdma_ctrl.bits.rd_eod_en = 0;
4313 +       rxdma_ctrl.bits.rd_eof_en = 0;
4314 +       raid_write_reg(RAID_STRDMA_CTRL, rxdma_ctrl.bits32,0xFFFFFFFF);
4315 +
4316 +       // enable interrupt
4317 +       dma_status.bits32 = 3;  // enable RpInt
4318 +       raid_write_reg(RAID_DMA_STATUS, dma_status.bits32,0xFFFFFFFF);
4319 +
4320 +       return 0;
4321 +}
4322 +
4323 +module_init(gemini_xor_init);
4324 +module_exit(gemini_xor_exit);
4325 +
4326 Index: linux-2.6.23.16/arch/arm/mm/Kconfig
4327 ===================================================================
4328 --- linux-2.6.23.16.orig/arch/arm/mm/Kconfig    2008-03-13 17:46:04.500819685 +0200
4329 +++ linux-2.6.23.16/arch/arm/mm/Kconfig 2008-03-13 17:48:24.508798285 +0200
4330 @@ -187,6 +187,26 @@
4331           Say Y if you want support for the ARM926T processor.
4332           Otherwise, say N.
4333
4334 +###### for Storlink SoC ######
4335 +config CPU_FA526
4336 +       bool "FA526 processor"
4337 +       depends on ARCH_SL2312
4338 +       default y
4339 +       select CPU_32v4
4340 +       select CPU_ABRT_EV4
4341 +       select CPU_CACHE_FA
4342 +       select CPU_CACHE_VIVT
4343 +       select CPU_CP15_MMU
4344 +       select CPU_COPY_FA
4345 +       select CPU_TLB_FA
4346 +       select CPU_FA_BTB
4347 +       help
4348 +         The FA526 is a version of the ARM9 compatible processor, but with smaller
4349 +         instruction and data caches. It is used in Storlink Sword device family.
4350 +
4351 +         Say Y if you want support for the FA526 processor.
4352 +         Otherwise, say N.
4353 +
4354  # ARM940T
4355  config CPU_ARM940T
4356         bool "Support ARM940T processor" if ARCH_INTEGRATOR
4357 @@ -461,6 +481,9 @@
4358  config CPU_CACHE_VIPT
4359         bool
4360
4361 +config CPU_CACHE_FA
4362 +       bool
4363 +
4364  if MMU
4365  # The copy-page model
4366  config CPU_COPY_V3
4367 @@ -475,6 +498,12 @@
4368  config CPU_COPY_V6
4369         bool
4370
4371 +config CPU_COPY_FA
4372 +       bool
4373 +
4374 +config CPU_FA_BTB
4375 +       bool
4376 +
4377  # This selects the TLB model
4378  config CPU_TLB_V3
4379         bool
4380 @@ -534,6 +563,14 @@
4381  config IO_36
4382         bool
4383
4384 +config CPU_TLB_FA
4385 +       bool
4386 +       help
4387 +         //TODO
4388 +         Faraday ARM FA526 architecture, unified TLB with writeback cache
4389 +         and invalidate instruction cache entry. Branch target buffer is also
4390 +         supported.
4391 +
4392  comment "Processor Features"
4393
4394  config ARM_THUMB
4395 @@ -600,7 +637,7 @@
4396
4397  config CPU_DCACHE_WRITETHROUGH
4398         bool "Force write through D-cache"
4399 -       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020) && !CPU_DCACHE_DISABLE
4400 +       depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
4401         default y if CPU_ARM925T
4402         help
4403           Say Y here to use the data cache in writethrough mode. Unless you
4404 Index: linux-2.6.23.16/arch/arm/mm/Makefile
4405 ===================================================================
4406 --- linux-2.6.23.16.orig/arch/arm/mm/Makefile   2008-03-13 17:46:04.500819685 +0200
4407 +++ linux-2.6.23.16/arch/arm/mm/Makefile        2008-03-13 17:48:24.508798285 +0200
4408 @@ -32,6 +32,7 @@
4409  obj-$(CONFIG_CPU_CACHE_V4WB)   += cache-v4wb.o
4410  obj-$(CONFIG_CPU_CACHE_V6)     += cache-v6.o
4411  obj-$(CONFIG_CPU_CACHE_V7)     += cache-v7.o
4412 +obj-$(CONFIG_CPU_CACHE_FA)     += cache-fa.o
4413
4414  obj-$(CONFIG_CPU_COPY_V3)      += copypage-v3.o
4415  obj-$(CONFIG_CPU_COPY_V4WT)    += copypage-v4wt.o
4416 @@ -40,6 +41,7 @@
4417  obj-$(CONFIG_CPU_SA1100)       += copypage-v4mc.o
4418  obj-$(CONFIG_CPU_XSCALE)       += copypage-xscale.o
4419  obj-$(CONFIG_CPU_XSC3)         += copypage-xsc3.o
4420 +obj-$(CONFIG_CPU_COPY_FA)      += copypage-fa.o
4421
4422  obj-$(CONFIG_CPU_TLB_V3)       += tlb-v3.o
4423  obj-$(CONFIG_CPU_TLB_V4WT)     += tlb-v4.o
4424 @@ -47,6 +49,7 @@
4425  obj-$(CONFIG_CPU_TLB_V4WBI)    += tlb-v4wbi.o
4426  obj-$(CONFIG_CPU_TLB_V6)       += tlb-v6.o
4427  obj-$(CONFIG_CPU_TLB_V7)       += tlb-v7.o
4428 +obj-$(CONFIG_CPU_TLB_FA)       += tlb-fa.o
4429
4430  obj-$(CONFIG_CPU_ARM610)       += proc-arm6_7.o
4431  obj-$(CONFIG_CPU_ARM710)       += proc-arm6_7.o
4432 @@ -60,6 +63,7 @@
4433  obj-$(CONFIG_CPU_ARM926T)      += proc-arm926.o
4434  obj-$(CONFIG_CPU_ARM940T)      += proc-arm940.o
4435  obj-$(CONFIG_CPU_ARM946E)      += proc-arm946.o
4436 +obj-$(CONFIG_CPU_FA526)                += proc-fa526.o
4437  obj-$(CONFIG_CPU_ARM1020)      += proc-arm1020.o
4438  obj-$(CONFIG_CPU_ARM1020E)     += proc-arm1020e.o
4439  obj-$(CONFIG_CPU_ARM1022)      += proc-arm1022.o
4440 Index: linux-2.6.23.16/arch/arm/mm/cache-fa.S
4441 ===================================================================
4442 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
4443 +++ linux-2.6.23.16/arch/arm/mm/cache-fa.S      2008-03-13 18:01:19.552965535 +0200
4444 @@ -0,0 +1,400 @@
4445 +/*
4446 + *  linux/arch/arm/mm/cache-fa.S
4447 + *
4448 + *  Copyright (C) 2005 Faraday Corp.
4449 + *
4450 + * This program is free software; you can redistribute it and/or modify
4451 + * it under the terms of the GNU General Public License version 2 as
4452 + * published by the Free Software Foundation.
4453 + *
4454 + *  Processors: FA520 FA526 FA626
4455 + * 03/31/2005 :        Luke Lee created, modified from cache-v4wb.S
4456 + * 04/06/2005 :        1. Read CR0-1 and determine the cache size dynamically,
4457 + *                to suit all Faraday CPU series
4458 + *             2. Fixed all functions
4459 + * 04/08/2005 :        insert CONFIG_CPU_ICACHE_DISABLE and CONFIG_CPU_DCACHE_DISABLE
4460 + * 04/12/2005 :        TODO: make this processor dependent or a self-modifying code to
4461 + *             inline cache len/size info into the instructions, as reading cache
4462 + *             size and len info in memory could cause another cache miss.
4463 + * 05/05/2005 :        Modify fa_flush_user_cache_range to comply APCS.
4464 + * 05/19/2005 :        Adjust for boundary conditions.
4465 + */
4466 +#include <linux/linkage.h>
4467 +#include <linux/init.h>
4468 +#include <asm/hardware.h>
4469 +#include <asm/page.h>
4470 +#include "proc-macros.S"
4471 +
4472 +#define CACHE_DLINESIZE           16
4473 +#ifdef CONFIG_SL3516_ASIC
4474 +#define CACHE_DSIZE       8192
4475 +#else
4476 +#define CACHE_DSIZE       16384
4477 +#endif
4478 +#define CACHE_ILINESIZE           16
4479 +#define CACHE_ISIZE       16384
4480 +
4481 +/* Luke Lee 04/06/2005 ins begin */
4482 +/*
4483 + *     initialize_cache_info()
4484 + *
4485 + *     Automatic detection of DSIZE, DLEN, ISIZE, ILEN variables according to
4486 + *     system register CR0-1
4487 + *     Destroyed register: r0, r1, r2, r3, ip
4488 + */
4489 +       .align
4490 +ENTRY(fa_initialize_cache_info)
4491 +       mov     r3, #1                          @ r3 always = 1
4492 +       adr     ip, __fa_cache_ilen
4493 +
4494 +       mrc     p15, 0, r0, c0, c0, 1
4495 +       /* ILEN */
4496 +       and     r1, r0, #3                      @ bits [1:0]
4497 +       add     r1, r1, #3                      @ cache line size is at least 8 bytes (2^3)
4498 +       mov     r2, r3, lsl r1                  @ r2 = 1<<r1
4499 +       str     r2, [ip], #4
4500 +       /* ISIZE */
4501 +       mov     r1, r0, lsr #6                  @ bits [8:6]
4502 +       and     r1, r1, #7
4503 +       add     r1, r1, #9                      @ cache size is at least 512 bytes (2^9)
4504 +       mov     r2, r3, lsl r1
4505 +       str     r2, [ip], #4
4506 +       /* DLEN */
4507 +       mov     r1, r0, lsr #12
4508 +       and     r1, r1, #3                      @ bits [13:12]
4509 +       add     r1, r1, #3                      @ cache line size is at least 8 bytes (2^3)
4510 +       mov     r2, r3, lsl r1                  @ r2 = 1<<r1
4511 +       str     r2, [ip], #4
4512 +       /* DSIZE */
4513 +       mov     r1, r0, lsr #18                 @ bits [20:18]
4514 +       and     r1, r1, #7
4515 +       add     r1, r1, #9                      @ cache size is at least 512 bytes (2^9)
4516 +       mov     r2, r3, lsl r1
4517 +       str     r2, [ip]
4518 +       mov     pc, lr
4519 +
4520 +       /* Warning : Do not change the order ! Successive codes depends on this */
4521 +       .align
4522 +       .globl __fa_cache_ilen, __fa_cache_isize, __fa_cache_dlen, __fa_cache_dsize
4523 +__fa_cache_ilen:
4524 +       .word   0                               @ instruction cache line length
4525 +__fa_cache_isize:
4526 +       .word   0                               @ instruction cache size
4527 +__fa_cache_dlen:
4528 +       .word   0                               @ data cahce line length
4529 +__fa_cache_dsize:
4530 +       .word   0                               @ data cache size
4531 +
4532 +/* Luke Lee 04/06/2005 ins end */
4533 +
4534 +/*
4535 + *     flush_user_cache_all()
4536 + *
4537 + *     Clean and invalidate all cache entries in a particular address
4538 + *     space.
4539 + */
4540 +ENTRY(fa_flush_user_cache_all)
4541 +       /* FALLTHROUGH */
4542 +/*
4543 + *     flush_kern_cache_all()
4544 + *
4545 + *     Clean and invalidate the entire cache.
4546 + */
4547 +ENTRY(fa_flush_kern_cache_all)
4548 +/* Luke Lee 04/06/2005 mod ok */
4549 +       mov     ip, #0
4550 +
4551 +#ifndef CONFIG_CPU_ICACHE_DISABLE
4552 +       mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
4553 +#endif
4554 +
4555 +__flush_whole_cache:
4556 +
4557 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4558 +       mov     ip, #0
4559 +#  ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4560 +       mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
4561 +#  else
4562 +       mcr     p15, 0, ip, c7,c14, 0           @ clean/invalidate D cache
4563 +#  endif
4564 +#endif /*CONFIG_CPU_DCACHE_DISABLE*/
4565 +
4566 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4567 +       mcr     p15, 0, ip, c7, c10, 4          @ drain write buffer
4568 +#endif
4569 +
4570 +#ifdef CONFIG_CPU_FA_BTB
4571 +       mcr     p15, 0, ip, c7, c5, 6           @ invalidate BTB
4572 +       nop
4573 +       nop
4574 +#endif
4575 +
4576 +/* Luke Lee 04/06/2005 que todo tofix : should iscratchpad and dscratchpad be invalidated ? */
4577 +       mov     pc, lr
4578 +
4579 +/*
4580 + *     flush_user_cache_range(start, end, flags)
4581 + *
4582 + *     Invalidate a range of cache entries in the specified
4583 + *     address space.
4584 + *
4585 + *     - start - start address (inclusive, page aligned)
4586 + *     - end   - end address (exclusive, page aligned)
4587 + *     - flags - vma_area_struct flags describing address space
4588 + */
4589 +ENTRY(fa_flush_user_cache_range)
4590 +
4591 +/* Luke Lee 04/06/2005 mod ok */
4592 +       /* Luke Lee 04/07/2005 ins 1 */
4593 +       mov     ip, #0
4594 +       sub     r3, r1, r0                      @ calculate total size
4595 +#ifndef CONFIG_CPU_ICACHE_DISABLE
4596 +       tst     r2, #VM_EXEC                    @ executable region?
4597 +       mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
4598 +#endif
4599 +
4600 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4601 +       /* Luke Lee 04/06/2005 ins 2 mod 1 */
4602 +       cmp     r3, #CACHE_DSIZE                @ total size >= limit?
4603 +       bhs     __flush_whole_cache             @ flush whole D cache
4604 +
4605 +       //debug_Aaron
4606 +        bic     r0, r0, #CACHE_DLINESIZE-1
4607 +       mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate boundary D entry
4608 +        bic     r1, r1, #CACHE_DLINESIZE-1
4609 +       mcr     p15, 0, r1, c7, c14, 1          @ clean and invalidate boundary D entry
4610 +
4611 +
4612 +1:     /* Luke Lee 04/06/2005 del 2 ins 5 */
4613 +
4614 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4615 +       mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
4616 +#else
4617 +       mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
4618 +#endif
4619 +       /* Luke Lee 04/06/2005 mod 1 */
4620 +       add     r0, r0, #CACHE_DLINESIZE
4621 +       cmp     r0, r1
4622 +       bls     1b                              @ Luke Lee 05/19/2005
4623 +#endif /* CONFIG_CPU_DCACHE_DISABLE */
4624 +
4625 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4626 +       tst     r2, #VM_EXEC
4627 +       /* Luke Lee 04/06/2005 mod 1 tofix todo : ne->eq */
4628 +       mcreq   p15, 0, r4, c7, c10, 4          @ drain write buffer
4629 +#endif
4630 +
4631 +       /* Luke Lee 04/06/2005 ins block */
4632 +#ifdef CONFIG_CPU_FA_BTB
4633 +        tst     r2, #VM_EXEC
4634 +       mov     ip, #0
4635 +       mcrne   p15, 0, ip, c7, c5, 6           @ invalidate BTB
4636 +       nop
4637 +       nop
4638 +#endif
4639 +       mov     pc, lr
4640 +
4641 +/*
4642 + *     flush_kern_dcache_page(void *page)
4643 + *
4644 + *     Ensure no D cache aliasing occurs, either with itself or
4645 + *     the I cache
4646 + *
4647 + *     - addr  - page aligned address
4648 + */
4649 +ENTRY(fa_flush_kern_dcache_page)
4650 +       add     r1, r0, #PAGE_SZ
4651 +       /* fall through */
4652 +
4653 +/*
4654 + *     coherent_kern_range(start, end)
4655 + *
4656 + *     Ensure coherency between the Icache and the Dcache in the
4657 + *     region described by start.  If you have non-snooping
4658 + *     Harvard caches, you need to implement this function.
4659 + *
4660 + *     - start  - virtual start address
4661 + *     - end    - virtual end address
4662 + */
4663 +ENTRY(fa_coherent_kern_range)
4664 +       /* fall through */
4665 +
4666 +/*
4667 + *     coherent_user_range(start, end)
4668 + *
4669 + *     Ensure coherency between the Icache and the Dcache in the
4670 + *     region described by start.  If you have non-snooping
4671 + *     Harvard caches, you need to implement this function.
4672 + *
4673 + *     - start  - virtual start address
4674 + *     - end    - virtual end address
4675 + */
4676 +ENTRY(fa_coherent_user_range)
4677 +
4678 +/* Luke Lee 04/06/2005 mod ok */
4679 +       /* Luke Lee 04/06/2005 ins 3 mod 1 */
4680 +       bic     r0, r0, #CACHE_DLINESIZE-1
4681 +
4682 + //debug_Aaron
4683 +        bic     r0, r0, #CACHE_DLINESIZE-1
4684 +        mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate boundary D entry
4685 +        bic     r1, r1, #CACHE_DLINESIZE-1
4686 +        mcr     p15, 0, r1, c7, c14, 1          @ clean and invalidate boundary D entry
4687 +
4688 +#if !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE))
4689 +1:     /* Luke Lee 04/06/2005 del 2 ins 5 mod 1 */
4690 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4691 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4692 +       mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
4693 +#else
4694 +       mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
4695 +#endif
4696 +#endif /* CONFIG_CPU_DCACHE_DISABLE */
4697 +
4698 +#ifndef CONFIG_CPU_ICACHE_DISABLE
4699 +       mcr     p15, 0, r0, c7, c5, 1           @ invalidate I entry
4700 +#endif
4701 +       add     r0, r0, #CACHE_DLINESIZE
4702 +       cmp     r0, r1
4703 +       bls     1b                              @ Luke Lee 05/19/2005 blo->bls
4704 +#endif /* !(defined(CONFIG_CPU_DCACHE_DISABLE) && defined(CONFIG_CPU_ICACHE_DISABLE)) */
4705 +
4706 +       mov     ip, #0
4707 +#ifdef CONFIG_CPU_FA_BTB
4708 +       mcr     p15, 0, ip, c7, c5, 6           @ invalidate BTB
4709 +       nop
4710 +       nop
4711 +#endif
4712 +
4713 +/* Luke Lee 04/08/2005 ins 1 skp 1 ins 1 */
4714 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4715 +       mcr     p15, 0, ip, c7, c10, 4          @ drain WB
4716 +#endif
4717 +
4718 +       mov     pc, lr
4719 +
4720 +/*
4721 + *     dma_inv_range(start, end)
4722 + *
4723 + *     Invalidate (discard) the specified virtual address range.
4724 + *     May not write back any entries.  If 'start' or 'end'
4725 + *     are not cache line aligned, those lines must be written
4726 + *     back.
4727 + *
4728 + *     - start  - virtual start address
4729 + *     - end    - virtual end address
4730 + */
4731 +ENTRY(fa_dma_inv_range)
4732 +
4733 +/* Luke Lee 04/06/2005 mod ok */
4734 +
4735 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4736 +
4737 + //debug_Aaron
4738 +        bic     r0, r0, #CACHE_DLINESIZE-1
4739 +        mcr     p15, 0, r0, c7, c6, 1          @ invalidate boundary D entry
4740 +        bic     r1, r1, #CACHE_DLINESIZE-1
4741 +        mcr     p15, 0, r1, c7, c6, 1          @ invalidate boundary D entry
4742 +
4743 +       /* Luke Lee 04/06/2005 ins 4 mod 2 */
4744 +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
4745 +       tst     r0, #CACHE_DLINESIZE -1
4746 +       bic     r0, r0, #CACHE_DLINESIZE -1
4747 +
4748 +//debug_Aaron
4749 +       //mcrne p15, 0, r0, c7, c10, 1          @ clean boundary D entry
4750 +
4751 +       /* Luke Lee 04/06/2005 mod 1 */
4752 +       /* Luke Lee 05/19/2005 always clean the end-point boundary mcrne->mcr */
4753 +       ////tst r1, #CACHE_DLINESIZE -1
4754 +       //mcr   p15, 0, r1, c7, c10, 1          @ clean boundary D entry
4755 +       /* Luke Lee 04/06/2005 ins 1 */
4756 +#else
4757 +       bic     r0, r0, #CACHE_DLINESIZE -1
4758 +#endif
4759 +
4760 +//debug_Aaron
4761 +1:     mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
4762 +//1:   mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
4763 +
4764 +       /* Luke Lee 04/06/2005 mod 1 */
4765 +       add     r0, r0, #CACHE_DLINESIZE
4766 +       cmp     r0, r1
4767 +       bls     1b                              @ Luke Lee 05/19/2005 blo->bls
4768 +#endif /* CONFIG_CPU_DCACHE_DISABLE */
4769 +
4770 +       /* Luke Lee 04/06/2005 ins 1 */
4771 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4772 +       mov     r0, #0
4773 +       mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
4774 +#endif
4775 +
4776 +       mov     pc, lr
4777 +
4778 +/*
4779 + *     dma_clean_range(start, end)
4780 + *
4781 + *     Clean (write back) the specified virtual address range.
4782 + *
4783 + *     - start  - virtual start address
4784 + *     - end    - virtual end address
4785 + */
4786 +ENTRY(fa_dma_clean_range)
4787 +
4788 +/* Luke Lee 04/06/2005 mod ok */
4789 +#ifndef CONFIG_CPU_DCACHE_DISABLE
4790 +
4791 + //debug_Aaron
4792 +        bic     r0, r0, #CACHE_DLINESIZE-1
4793 +        mcr     p15, 0, r0, c7, c10, 1          @ clean boundary D entry
4794 +        bic     r1, r1, #CACHE_DLINESIZE-1
4795 +        mcr     p15, 0, r1, c7, c10, 1          @ clean boundary D entry
4796 +
4797 +       /* Luke Lee 04/06/2005 ins 4 mod 2 */
4798 +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
4799 +       bic     r0, r0, #CACHE_DLINESIZE - 1
4800 +
4801 +//debug_Aaron
4802 +1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
4803 +//1:   mcr     p15, 0, r0, c7, c14, 1          @ clean D entry
4804 +       add     r0, r0, #CACHE_DLINESIZE
4805 +       cmp     r0, r1
4806 +       bls     1b                              @ Luke Lee 05/19/2005 blo->bls
4807 +       /* Luke Lee 04/06/2005 ins 2 */
4808 +#endif
4809 +#endif /* CONFIG_CPU_DCACHE_DISABLE */
4810 +
4811 +#ifndef CONFIG_CPU_FA_WB_DISABLE
4812 +       mov     r0, #0
4813 +       mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer
4814 +#endif
4815 +
4816 +       mov     pc, lr
4817 +
4818 +/*
4819 + *     dma_flush_range(start, end)
4820 + *
4821 + *     Clean and invalidate the specified virtual address range.
4822 + *
4823 + *     - start  - virtual start address
4824 + *     - end    - virtual end address
4825 + *
4826 + *     This is actually the same as fa_coherent_kern_range()
4827 + */
4828 +       .globl  fa_dma_flush_range
4829 +       .set    fa_dma_flush_range, fa_coherent_kern_range
4830 +
4831 +       __INITDATA
4832 +
4833 +       .type   fa_cache_fns, #object
4834 +ENTRY(fa_cache_fns)
4835 +       .long   fa_flush_kern_cache_all
4836 +       .long   fa_flush_user_cache_all
4837 +       .long   fa_flush_user_cache_range
4838 +       .long   fa_coherent_kern_range
4839 +       .long   fa_coherent_user_range
4840 +       .long   fa_flush_kern_dcache_page
4841 +       .long   fa_dma_inv_range
4842 +       .long   fa_dma_clean_range
4843 +       .long   fa_dma_flush_range
4844 +       .size   fa_cache_fns, . - fa_cache_fns
4845 Index: linux-2.6.23.16/arch/arm/mm/copypage-fa.S
4846 ===================================================================
4847 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
4848 +++ linux-2.6.23.16/arch/arm/mm/copypage-fa.S   2008-03-13 17:48:24.508798285 +0200
4849 @@ -0,0 +1,106 @@
4850 +/*
4851 + *  linux/arch/arm/lib/copypage-fa.S
4852 + *
4853 + *  Copyright (C) 2005 Faraday Corp.
4854 + *
4855 + * This program is free software; you can redistribute it and/or modify
4856 + * it under the terms of the GNU General Public License version 2 as
4857 + * published by the Free Software Foundation.
4858 + *
4859 + *  ASM optimised string functions
4860 + * 05/18/2005 :        Luke Lee created, modified from copypage-v4wb.S
4861 + */
4862 +#include <linux/linkage.h>
4863 +#include <linux/init.h>
4864 +#include <asm/asm-offsets.h>
4865 +
4866 +       .text
4867 +/*
4868 + * ARMv4 optimised copy_user_page for Faraday processors
4869 + *
4870 + * We flush the destination cache lines just before we write the data into the
4871 + * corresponding address.  Since the Dcache is read-allocate, this removes the
4872 + * Dcache aliasing issue.  The writes will be forwarded to the write buffer,
4873 + * and merged as appropriate.
4874 + *
4875 + * Note: We rely on all ARMv4 processors implementing the "invalidate D line"
4876 + * instruction.  If your processor does not supply this, you have to write your
4877 + * own copy_user_page that does the right thing.
4878 + *
4879 + * copy_user_page(to,from,vaddr)
4880 + */
4881 +       .align  4
4882 +ENTRY(fa_copy_user_page)
4883 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4884 +       /* Write through */
4885 +       stmfd   sp!, {r4, lr}                   @ 2
4886 +       mov     r2, #PAGE_SZ/32                 @ 1
4887 +
4888 +       ldmia   r1!, {r3, r4, ip, lr}           @ 4
4889 +1:     stmia   r0!, {r3, r4, ip, lr}           @ 4
4890 +       ldmia   r1!, {r3, r4, ip, lr}           @ 4+1
4891 +       subs    r2, r2, #1                      @ 1
4892 +       stmia   r0!, {r3, r4, ip, lr}           @ 4
4893 +       ldmneia r1!, {r3, r4, ip, lr}           @ 4
4894 +       bne     1b                              @ 1
4895 +
4896 +       mcr     p15, 0, r2, c7, c7, 0           @ flush ID cache
4897 +       ldmfd   sp!, {r4, pc}                   @ 3
4898 +#else
4899 +       /* Write back */
4900 +       stmfd   sp!, {r4, lr}                   @ 2
4901 +       mov     r2, #PAGE_SZ/32                 @ 1
4902 +
4903 +1:     ldmia   r1!, {r3, r4, ip, lr}           @ 4
4904 +       mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line
4905 +       stmia   r0!, {r3, r4, ip, lr}           @ 4
4906 +       ldmia   r1!, {r3, r4, ip, lr}           @ 4
4907 +       mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line
4908 +       stmia   r0!, {r3, r4, ip, lr}           @ 4
4909 +       subs    r2, r2, #1                      @ 1
4910 +       bne     1b
4911 +       mcr     p15, 0, r2, c7, c10, 4          @ 1   drain WB
4912 +       ldmfd   sp!, {r4, pc}                   @ 3
4913 +#endif
4914 +
4915 +/*
4916 + * ARMv4 optimised clear_user_page
4917 + *
4918 + * Same story as above.
4919 + */
4920 +       .align  4
4921 +ENTRY(fa_clear_user_page)
4922 +       str     lr, [sp, #-4]!
4923 +       mov     r1, #PAGE_SZ/32                 @ 1
4924 +       mov     r2, #0                          @ 1
4925 +       mov     r3, #0                          @ 1
4926 +       mov     ip, #0                          @ 1
4927 +       mov     lr, #0                          @ 1
4928 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
4929 +       /* Write through */
4930 +1:     stmia   r0!, {r2, r3, ip, lr}           @ 4
4931 +       stmia   r0!, {r2, r3, ip, lr}           @ 4
4932 +       subs    r1, r1, #1                      @ 1
4933 +       bne     1b                              @ 1
4934 +
4935 +       mcr     p15, 0, r1, c7, c7, 0           @ flush ID cache
4936 +       ldr     pc, [sp], #4
4937 +#else
4938 +       /* Write back */
4939 +1:     mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line
4940 +       stmia   r0!, {r2, r3, ip, lr}           @ 4
4941 +       mcr     p15, 0, r0, c7, c6, 1           @ 1   invalidate D line
4942 +       stmia   r0!, {r2, r3, ip, lr}           @ 4
4943 +       subs    r1, r1, #1                      @ 1
4944 +       bne     1b                              @ 1
4945 +       mcr     p15, 0, r1, c7, c10, 4          @ 1   drain WB
4946 +       ldr     pc, [sp], #4
4947 +#endif
4948 +
4949 +       __INITDATA
4950 +
4951 +       .type   fa_user_fns, #object
4952 +ENTRY(fa_user_fns)
4953 +       .long   fa_clear_user_page
4954 +       .long   fa_copy_user_page
4955 +       .size   fa_user_fns, . - fa_user_fns
4956 Index: linux-2.6.23.16/arch/arm/mm/init.c
4957 ===================================================================
4958 --- linux-2.6.23.16.orig/arch/arm/mm/init.c     2008-03-13 17:46:04.500819685 +0200
4959 +++ linux-2.6.23.16/arch/arm/mm/init.c  2008-03-13 17:48:24.508798285 +0200
4960 @@ -23,6 +23,7 @@
4961
4962  #include <asm/mach/arch.h>
4963  #include <asm/mach/map.h>
4964 +#include <asm/arch/ipi.h>
4965
4966  #include "mm.h"
4967
4968 @@ -252,6 +253,11 @@
4969                 initrd_end = initrd_start + phys_initrd_size;
4970         }
4971  #endif
4972 +#ifdef CONFIG_GEMINI_IPI
4973 +       printk("CPU ID:%d\n",getcpuid());
4974 +//     reserve_bootmem_node(NODE_DATA(0), 0x400000, 0x400000);         //CPU0 space
4975 +//     reserve_bootmem_node(NODE_DATA(0), SHAREADDR, SHARE_MEM_SIZE);          //share memory
4976 +#endif
4977
4978         /*
4979          * Finally, reserve any node zero regions.
4980 Index: linux-2.6.23.16/arch/arm/mm/proc-fa526.S
4981 ===================================================================
4982 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
4983 +++ linux-2.6.23.16/arch/arm/mm/proc-fa526.S    2008-03-14 14:59:46.823166907 +0200
4984 @@ -0,0 +1,407 @@
4985 +/*
4986 + *  linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
4987 + *
4988 + *  Copyright (C) 2005 Faraday Corp.
4989 + *
4990 + * This program is free software; you can redistribute it and/or modify
4991 + * it under the terms of the GNU General Public License as published by
4992 + * the Free Software Foundation; either version 2 of the License, or
4993 + * (at your option) any later version.
4994 + *
4995 + * This program is distributed in the hope that it will be useful,
4996 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4997 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4998 + * GNU General Public License for more details.
4999 + *
5000 + * You should have received a copy of the GNU General Public License
5001 + * along with this program; if not, write to the Free Software
5002 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5003 + *
5004 + *
5005 + * These are the low level assembler for performing cache and TLB
5006 + * functions on the fa526.
5007 + *
5008 + *  Written by : Luke Lee
5009 + */
5010 +#include <linux/linkage.h>
5011 +#include <linux/init.h>
5012 +#include <asm/assembler.h>
5013 +#include <asm/pgtable.h>
5014 +#include <asm/pgtable-hwdef.h>
5015 +#include <asm/elf.h>
5016 +#include <asm/hardware.h>
5017 +#include <asm/page.h>
5018 +#include <asm/ptrace.h>
5019 +#include <asm/system.h>
5020 +#include "proc-macros.S"
5021 +
5022 +#define CACHE_DLINESIZE           16
5023 +
5024 +       .text
5025 +/*
5026 + * cpu_fa526_proc_init()
5027 + */
5028 +ENTRY(cpu_fa526_proc_init)
5029 +       /* MMU is already ON here, ICACHE, DCACHE conditionally disabled */
5030 +
5031 +        mov     r0, #1
5032 +       nop
5033 +       nop
5034 +        mcr     p15, 0, r0, c1, c1, 0          @ turn-on ECR
5035 +       nop
5036 +       nop
5037 +
5038 +       mrc     p15, 0, r0, c1, c0, 0           @ read ctrl register
5039 +
5040 +#ifdef CONFIG_CPU_FA_BTB
5041 +       orr     r0, r0, #CR_Z
5042 +#else
5043 +       bic     r0, r0, #CR_Z
5044 +#endif
5045 +#ifdef CONFIG_CPU_FA_WB_DISABLE
5046 +       mov     r1, #0
5047 +       mcr     p15, 0, r1, c7, c10, 4          @ drain write buffer
5048 +       nop
5049 +       nop
5050 +       bic     r0, r0, #CR_W
5051 +#else
5052 +       orr     r0, r0, #CR_W
5053 +#endif
5054 +#ifdef CONFIG_CPU_DCACHE_DISABLE
5055 +       bic     r0, r0, #CR_C
5056 +#else
5057 +       orr     r0, r0, #CR_C
5058 +#endif
5059 +#ifdef CONFIG_CPU_ICACHE_DISABLE
5060 +       bic     r0, r0, #CR_I
5061 +#else
5062 +       orr     r0, r0, #CR_I
5063 +#endif
5064 +
5065 +       nop
5066 +       nop
5067 +       mcr     p15, 0, r0, c1, c0, 0
5068 +       nop
5069 +       nop
5070 +
5071 +       mov     r5, lr
5072 +       bl      fa_initialize_cache_info        @ destroy r0~r4
5073 +       mov     pc, r5                          @ return
5074 +
5075 +
5076 +/*
5077 + * cpu_fa526_proc_fin()
5078 + */
5079 +ENTRY(cpu_fa526_proc_fin)
5080 +       stmfd   sp!, {lr}
5081 +       mov     ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
5082 +       msr     cpsr_c, ip
5083 +
5084 +       bl      fa_flush_kern_cache_all
5085 +       mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
5086 +       bic     r0, r0, #0x1000                 @ ...i............
5087 +       bic     r0, r0, #0x000e                 @ ............wca.
5088 +       mcr     p15, 0, r0, c1, c0, 0           @ disable caches
5089 +
5090 +       nop
5091 +       nop
5092 +       ldmfd   sp!, {pc}
5093 +
5094 +/*
5095 + * cpu_fa526_reset(loc)
5096 + *
5097 + * Perform a soft reset of the system.  Put the CPU into the
5098 + * same state as it would be if it had been reset, and branch
5099 + * to what would be the reset vector.
5100 + *
5101 + * loc: location to jump to for soft reset
5102 + */
5103 +       .align  4
5104 +ENTRY(cpu_fa526_reset)
5105 +       mov     ip, #0
5106 +       mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
5107 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5108 +       mcr     p15, 0, ip, c7, c10, 4          @ drain WB
5109 +#endif
5110 +       mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
5111 +       mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
5112 +       bic     ip, ip, #0x000f                 @ ............wcam
5113 +       bic     ip, ip, #0x1100                 @ ...i...s........
5114 +
5115 +       bic     ip, ip, #0x0800                 @ BTB off
5116 +       mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
5117 +       nop
5118 +       nop
5119 +       mov     pc, r0
5120 +
5121 +/*
5122 + * cpu_fa526_do_idle()
5123 + */
5124 +       .align  4
5125 +ENTRY(cpu_fa526_do_idle)
5126 +
5127 +#ifdef CONFIG_CPU_FA_IDLE
5128 +       nop
5129 +       nop
5130 +       mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt (IDLE mode)
5131 +#endif
5132 +       mov     pc, lr
5133 +
5134 +
5135 +ENTRY(cpu_fa526_dcache_clean_area)
5136 +
5137 +#ifndef CONFIG_CPU_DCACHE_DISABLE
5138 +#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
5139 +1:     mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
5140 +       add     r0, r0, #CACHE_DLINESIZE
5141 +       subs    r1, r1, #CACHE_DLINESIZE
5142 +       bhi     1b
5143 +#endif
5144 +#endif
5145 +       mov     pc, lr
5146 +
5147 +
5148 +/* =============================== PageTable ============================== */
5149 +
5150 +/*
5151 + * cpu_fa526_switch_mm(pgd)
5152 + *
5153 + * Set the translation base pointer to be as described by pgd.
5154 + *
5155 + * pgd: new page tables
5156 + */
5157 +       .align  4
5158 +
5159 +       .globl  fault_address
5160 +fault_address:
5161 +       .long   0
5162 +
5163 +ENTRY(cpu_fa526_switch_mm)
5164 +
5165 +       mov     ip, #0
5166 +#ifndef CONFIG_CPU_DCACHE_DISABLE
5167 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
5168 +       mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
5169 +#else
5170 +       mcr     p15, 0, ip, c7, c14, 0          @ Clean and invalidate whole DCache
5171 +#endif
5172 +#endif /*CONFIG_CPU_DCACHE_DISABLE*/
5173 +
5174 +#ifndef CONFIG_CPU_ICACHE_DISABLE
5175 +       mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
5176 +#endif
5177 +
5178 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5179 +       mcr     p15, 0, ip, c7, c10, 4          @ drain WB
5180 +#endif
5181 +
5182 +#ifdef CONFIG_CPU_FA_BTB
5183 +       mcr     p15, 0, ip, c7, c5, 6           @ invalidate BTB since mm changed
5184 +       nop
5185 +       nop
5186 +#endif
5187 +       bic     r0, r0, #0xff                   @ clear bits [7:0]
5188 +       bic     r0, r0, #0x3f00                 @ clear bits [13:8]
5189 +       mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
5190 +       mcr     p15, 0, ip, c8, c7, 0           @ invalidate UTLB
5191 +       nop
5192 +       nop
5193 +       mov     pc, lr
5194 +
5195 +/*
5196 + * cpu_fa526_set_pte_ext(ptep, pte, ext)
5197 + *
5198 + * Set a PTE and flush it out
5199 + */
5200 +       .align  4
5201 +ENTRY(cpu_fa526_set_pte_ext)
5202 +       str     r1, [r0], #-2048                @ linux version
5203 +
5204 +       eor     r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
5205 +
5206 +       bic     r2, r1, #PTE_SMALL_AP_MASK
5207 +       bic     r2, r2, #PTE_TYPE_MASK
5208 +       orr     r2, r2, #PTE_TYPE_SMALL
5209 +
5210 +       tst     r1, #L_PTE_USER                 @ User?
5211 +       orrne   r2, r2, #PTE_SMALL_AP_URO_SRW
5212 +
5213 +       tst     r1, #L_PTE_WRITE | L_PTE_DIRTY  @ Write and Dirty?
5214 +       orreq   r2, r2, #PTE_SMALL_AP_UNO_SRW
5215 +
5216 +       tst     r1, #L_PTE_PRESENT | L_PTE_YOUNG        @ Present and Young?
5217 +       movne   r2, #0
5218 +
5219 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
5220 +       eor     r3, r2, #0x0a                   @ C & small page?  1010
5221 +       tst     r3, #0x0b                       @                  1011
5222 +       biceq   r2, r2, #4
5223 +#endif
5224 +       str     r2, [r0]                        @ hardware version
5225 +
5226 +       mov     r2, #0
5227 +       mcr     p15, 0, r2, c7, c10, 0          @ clean D cache all
5228 +
5229 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5230 +       mcr     p15, 0, r2, c7, c10, 4          @ drain WB
5231 +#endif
5232 +#ifdef CONFIG_CPU_FA_BTB
5233 +       mcr     p15, 0, r2, c7, c5, 6           @ invalidate BTB
5234 +       nop
5235 +       nop
5236 +#endif
5237 +       mov     pc, lr
5238 +
5239 +       __INIT
5240 +
5241 +       .type   __fa526_setup, #function
5242 +__fa526_setup:
5243 +       /* On return of this routine, r0 must carry correct flags for CFG register */
5244 +       mov     r0, #0
5245 +       mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
5246 +       mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
5247 +       mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
5248 +
5249 +       mcr     p15, 0, r0, c7, c5, 5           @ invalidate IScratchpad RAM
5250 +
5251 +        mov     r0, #1
5252 +        mcr     p15, 0, r0, c1, c1, 0          @ turn-on ECR
5253 +
5254 +       mrc     p15, 0, r0, c9, c1, 0           @ DScratchpad
5255 +       bic     r0, r0, #1
5256 +       mcr     p15, 0, r0, c9, c1, 0
5257 +       mrc     p15, 0, r0, c9, c1, 1           @ IScratchpad
5258 +       bic     r0, r0, #1
5259 +       mcr     p15, 0, r0, c9, c1, 1
5260 +
5261 +       mov     r0, #0
5262 +       mcr     p15, 0, r0, c1, c1, 0           @ turn-off ECR
5263 +
5264 +#ifdef CONFIG_CPU_FA_BTB
5265 +       mcr     p15, 0, r0, c7, c5, 6           @ invalidate BTB All
5266 +       nop
5267 +       nop
5268 +#endif
5269 +
5270 +       mov     r0, #0x1f                       @ Domains 0, 1 = manager, 2 = client
5271 +       mcr     p15, 0, r0, c3, c0              @ load domain access register
5272 +
5273 +       mrc     p15, 0, r0, c1, c0              @ get control register v4
5274 +       ldr     r5, fa526_cr1_clear
5275 +       bic     r0, r0, r5
5276 +       ldr     r5, fa526_cr1_set
5277 +       orr     r0, r0, r5
5278 +
5279 +#ifdef CONFIG_CPU_FA_BTB
5280 +       orr     r0, r0, #CR_Z
5281 +#else
5282 +       bic     r0, r0, #CR_Z
5283 +#endif
5284 +#ifdef CONFIG_CPU_FA_WB_DISABLE
5285 +       mov     r12, #0
5286 +       mcr     p15, 0, r12, c7, c10, 4         @ drain write buffer
5287 +       nop
5288 +       nop
5289 +       bic     r0, r0, #CR_W                   @ .... .... .... 1...
5290 +#else
5291 +       orr     r0, r0, #CR_W
5292 +#endif
5293 +
5294 +       mov     pc, lr
5295 +       .size   __fa526_setup, . - __fa526_setup
5296 +
5297 +       /*
5298 +        * .RVI ZFRS BLDP WCAM
5299 +        * ..11 0001 .111 1101
5300 +        *
5301 +        */
5302 +       .type   fa526_cr1_clear, #object
5303 +       .type   fa526_cr1_set, #object
5304 +fa526_cr1_clear:
5305 +       .word   0x3f3f
5306 +fa526_cr1_set:
5307 +       .word   0x317D
5308 +
5309 +       __INITDATA
5310 +
5311 +/*
5312 + * Purpose : Function pointers used to access above functions - all calls
5313 + *          come through these
5314 + */
5315 +       .type   fa526_processor_functions, #object
5316 +fa526_processor_functions:
5317 +       .word   v4_early_abort
5318 +       .word   cpu_fa526_proc_init
5319 +       .word   cpu_fa526_proc_fin
5320 +       .word   cpu_fa526_reset
5321 +       .word   cpu_fa526_do_idle
5322 +       .word   cpu_fa526_dcache_clean_area
5323 +       .word   cpu_fa526_switch_mm
5324 +       .word   cpu_fa526_set_pte_ext
5325 +       .size   fa526_processor_functions, . - fa526_processor_functions
5326 +
5327 +       .section ".rodata"
5328 +
5329 +       .type   cpu_arch_name, #object
5330 +cpu_arch_name:
5331 +       .asciz  "armv4"
5332 +       .size   cpu_arch_name, . - cpu_arch_name
5333 +
5334 +       .type   cpu_elf_name, #object
5335 +cpu_elf_name:
5336 +       .asciz  "v4"
5337 +       .size   cpu_elf_name, . - cpu_elf_name
5338 +
5339 +       .type   cpu_fa526_name, #object
5340 +cpu_fa526_name:
5341 +       .ascii  "FA526"
5342 +#ifndef CONFIG_CPU_ICACHE_DISABLE
5343 +       .ascii  "i"
5344 +#endif
5345 +#ifndef CONFIG_CPU_DCACHE_DISABLE
5346 +       .ascii  "d"
5347 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
5348 +       .ascii  "(wt)"
5349 +#else
5350 +       .ascii  "(wb)"
5351 +#endif
5352 +#endif
5353 +       .ascii  "\0"
5354 +       .size   cpu_fa526_name, . - cpu_fa526_name
5355 +
5356 +       .align
5357 +
5358 +       .section ".proc.info.init", #alloc, #execinstr
5359 +
5360 +#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
5361 +#define __PMD_SECT_BUFFERABLE  0
5362 +#else
5363 +#define __PMD_SECT_BUFFERABLE  PMD_SECT_BUFFERABLE
5364 +#endif
5365 +
5366 +       .type   __fa526_proc_info,#object
5367 +__fa526_proc_info:
5368 +       .long   0x66015261
5369 +       .long   0xff01fff1
5370 +       .long   PMD_TYPE_SECT | \
5371 +               __PMD_SECT_BUFFERABLE | \
5372 +               PMD_SECT_CACHEABLE | \
5373 +               PMD_BIT4 | \
5374 +               PMD_SECT_AP_WRITE | \
5375 +               PMD_SECT_AP_READ
5376 +       .long   PMD_TYPE_SECT | \
5377 +               PMD_BIT4 | \
5378 +               PMD_SECT_AP_WRITE | \
5379 +               PMD_SECT_AP_READ
5380 +       b       __fa526_setup
5381 +       .long   cpu_arch_name
5382 +       .long   cpu_elf_name
5383 +       .long   HWCAP_SWP | HWCAP_HALF
5384 +       .long   cpu_fa526_name
5385 +       .long   fa526_processor_functions
5386 +       .long   fa_tlb_fns
5387 +       .long   fa_user_fns
5388 +       .long   fa_cache_fns
5389 +       .size   __fa526_proc_info, . - __fa526_proc_info
5390 +
5391 +
5392 Index: linux-2.6.23.16/arch/arm/mm/tlb-fa.S
5393 ===================================================================
5394 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5395 +++ linux-2.6.23.16/arch/arm/mm/tlb-fa.S        2008-03-13 17:48:24.508798285 +0200
5396 @@ -0,0 +1,96 @@
5397 +/*
5398 + *  linux/arch/arm/mm/tlb-fa.S
5399 + *
5400 + *  Copyright (C) 2005 Faraday Corp.
5401 + *
5402 + * This program is free software; you can redistribute it and/or modify
5403 + * it under the terms of the GNU General Public License version 2 as
5404 + * published by the Free Software Foundation.
5405 + *
5406 + *  ARM architecture version 4, Faraday variation.
5407 + *  This assume an unified TLBs, with a write buffer, and branch target buffer (BTB)
5408 + *
5409 + *  Processors: FA520 FA526 FA626
5410 + *  03/31/2005 : Created by Luke Lee, modified from tlb-v4wbi.S
5411 + *  05/06/2005 : Fixed buggy CPU versions that did not invalidate the associated
5412 + *               data cache entries when invalidating TLB entries.
5413 + */
5414 +#include <linux/linkage.h>
5415 +#include <linux/init.h>
5416 +#include <asm/asm-offsets.h>
5417 +#include <asm/tlbflush.h>
5418 +#include "proc-macros.S"
5419 +
5420 +
5421 +/*
5422 + *     flush_user_tlb_range(start, end, mm)
5423 + *
5424 + *     Invalidate a range of TLB entries in the specified address space.
5425 + *
5426 + *     - start - range start address
5427 + *     - end   - range end address
5428 + *     - mm    - mm_struct describing address space
5429 + */
5430 +       .align  4
5431 +ENTRY(fa_flush_user_tlb_range)
5432 +
5433 +       vma_vm_mm ip, r2
5434 +       act_mm  r3                              @ get current->active_mm
5435 +       eors    r3, ip, r3                      @ == mm ?
5436 +       movne   pc, lr                          @ no, we dont do anything
5437 +       mov     r3, #0
5438 +
5439 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5440 +       mcr     p15, 0, r3, c7, c10, 4          @ drain WB
5441 +#endif
5442 +
5443 +       vma_vm_flags r2, r2
5444 +       bic     r0, r0, #0x0ff
5445 +       bic     r0, r0, #0xf00
5446 +
5447 +1:     mcr     p15, 0, r0, c8, c7, 1           @ invalidate UTLB entry
5448 +       add     r0, r0, #PAGE_SZ
5449 +       cmp     r0, r1
5450 +       bls     1b                              @ Luke Lee 05/19/2005 blo -> bls
5451 +
5452 +#ifdef CONFIG_CPU_FA_BTB
5453 +       mcr     p15, 0, r3, c7, c5, 6           @ invalidate BTB
5454 +       nop
5455 +       nop
5456 +#endif
5457 +       mov     pc, lr
5458 +
5459 +
5460 +ENTRY(fa_flush_kern_tlb_range)
5461 +       mov     r3, #0
5462 +
5463 +       mcr     p15, 0, r3, c7, c10, 0          @ clean Dcache all 06/03/2005
5464 +
5465 +#ifndef CONFIG_CPU_FA_WB_DISABLE
5466 +       mcr     p15, 0, r3, c7, c10, 4          @ drain WB
5467 +#endif
5468 +
5469 +       bic     r0, r0, #0x0ff
5470 +       bic     r0, r0, #0xf00
5471 +1:
5472 +       mcr     p15, 0, r0, c8, c7, 1           @ invalidate UTLB entry
5473 +       add     r0, r0, #PAGE_SZ
5474 +       cmp     r0, r1
5475 +       bls     1b                              @ Luke Lee 05/19/2005 blo -> bls
5476 +
5477 +#ifdef CONFIG_CPU_FA_BTB
5478 +       mcr     p15, 0, r3, c7, c5, 6           @ invalidate BTB
5479 +       nop
5480 +       nop
5481 +#endif
5482 +       mov     pc, lr
5483 +
5484 +
5485 +       __INITDATA
5486 +
5487 +       .type   fa_tlb_fns, #object
5488 +ENTRY(fa_tlb_fns)
5489 +       .long   fa_flush_user_tlb_range
5490 +       .long   fa_flush_kern_tlb_range
5491 +       .long   fa_tlb_flags
5492 +       .size   fa_tlb_fns, . - fa_tlb_fns
5493 Index: linux-2.6.23.16/arch/arm/tools/mach-types
5494 ===================================================================
5495 --- linux-2.6.23.16.orig/arch/arm/tools/mach-types      2008-03-13 17:46:04.500819685 +0200
5496 +++ linux-2.6.23.16/arch/arm/tools/mach-types   2008-03-13 17:48:24.508798285 +0200
5497 @@ -208,7 +208,8 @@
5498  fester                 SA1100_FESTER           FESTER                  191
5499  gpi                    ARCH_GPI                GPI                     192
5500  smdk2410               ARCH_SMDK2410           SMDK2410                193
5501 -i519                   ARCH_I519               I519                    194
5502 +#i519                  ARCH_I519               I519                    194
5503 +sl2312          ARCH_SL2312         SL2312          194
5504  nexio                  SA1100_NEXIO            NEXIO                   195
5505  bitbox                 SA1100_BITBOX           BITBOX                  196
5506  g200                   SA1100_G200             G200                    197
5507 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/SL_gpio.h
5508 ===================================================================
5509 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5510 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/SL_gpio.h       2008-03-13 17:48:24.508798285 +0200
5511 @@ -0,0 +1,59 @@
5512 +#define GPIO_MINOR_LAST 31
5513 +#define GPIO_MAJOR     120     // Experiemental
5514 +
5515 +#define GPIO_IRQ_NBR   12
5516 +
5517 +#define GPIOBASEADDR           (IO_ADDRESS(0x021000000))
5518 +
5519 +#define GPIODATAOUTOFF         0x00
5520 +#define GPIODATAINOFF          0x04
5521 +#define GPIOPINDIROFF          0x08
5522 +#define GPIOPINBYPASSOFF       0x0C
5523 +#define GPIODATASETOFF         0x10
5524 +#define GPIODATACLEAROFF       0x14
5525 +#define GPIOPINPULLENBOFF      0x18
5526 +#define GPIOPINPULLTPOFF       0x1C
5527 +#define GPIOINTRENBOFF         0x20
5528 +#define GPIOINTRRAWSOFF                0x24
5529 +#define GPIOINTRMASKEDSTATEOFF 0x28
5530 +#define GPIOINTRMASKOFF                0x2C
5531 +#define GPIOINTRCLEAROFF       0x30
5532 +#define GPIOINTRTRIGGEROFF     0x34
5533 +#define GPIOINTRBOTHOFF                0x38
5534 +#define GPIOINTRRISENEGOFF     0x3C
5535 +#define GPIOBNCEENBOFF         0x40
5536 +#define GPIOBNCEPRESOFF                0x44
5537 +
5538 +#define GPIO_IOCTRL_SETDIR     0x20
5539 +#define GPIO_IOCTRL_SET                0x40
5540 +#define GPIO_IOCTRL_CLEAR      0x50
5541 +#define GPIO_IOCTRL_ENBINT     0x60
5542 +#define GPIO_IOCTRL_MASKINT    0x70
5543 +#define GPIO_IOCTRL_LVLTRIG    0x75
5544 +#define GPIO_IOCTRL_EDGINT     0x77
5545 +#define GPIO_IOCTRL_EDGPOLINT  0x78
5546 +#define GPIO_IOCTRL_BYPASS     0x30
5547 +#define GPIO_IOCTRL_PRESCLK    0x80
5548 +#define GPIO_IOCTRL_CLKVAL     0x90
5549 +#define GPIO_IOCTRL_PULLENB    0xA0
5550 +#define GPIO_IOCTRL_PULLTYPE   0xA8
5551 +
5552 +
5553 +#define GPIO_MAJOR     120     /* experimental MAJOR number */
5554 +                               // Minor - 0 : 31 gpio pins
5555 +
5556 +#define GPIO_SET       0x01
5557 +#define GPIO_CLEAR     0x01
5558 +
5559 +#define GPIO_INPUT     0
5560 +#define GPIO_OUTPUT    1
5561 +#define GPIO_EDGEINTR  0
5562 +#define GPIO_EDGESINGL 0
5563 +#define GPIO_EDGEBOTH  1
5564 +#define GPIO_POSITIVE  0
5565 +#define GPIO_ENBINT    1
5566 +#define GPIO_DISABLEMASK       1
5567 +#define GPIO_PULLDOWN  0
5568 +#define GPIO_PULLUP    1
5569 +#define GPIO_ENABLEPULL        1
5570 +#define GPIO_DISABLEPULL       0
5571 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/debug-macro.S
5572 ===================================================================
5573 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5574 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/debug-macro.S   2008-03-13 17:48:24.508798285 +0200
5575 @@ -0,0 +1,20 @@
5576 +/* linux/include/asm-arm/arch-ebsa110/debug-macro.S
5577 + *
5578 + * Debugging macro include header
5579 + *
5580 + *  Copyright (C) 1994-1999 Russell King
5581 + *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
5582 + *
5583 + * This program is free software; you can redistribute it and/or modify
5584 + * it under the terms of the GNU General Public License version 2 as
5585 + * published by the Free Software Foundation.
5586 + *
5587 +**/
5588 +
5589 +               .macro  addruart,rx
5590 +               mov     \rx, #0x42000000
5591 +               .endm
5592 +
5593 +#define UART_SHIFT     2
5594 +#define FLOW_CONTROL
5595 +#include <asm/hardware/debug-8250.S>
5596 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/dma.h
5597 ===================================================================
5598 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5599 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/dma.h   2008-03-13 17:48:24.508798285 +0200
5600 @@ -0,0 +1,28 @@
5601 +/*
5602 + *  linux/include/asm-arm/arch-camelot/dma.h
5603 + *
5604 + *  Copyright (C) 1997,1998 Russell King
5605 + *
5606 + * This program is free software; you can redistribute it and/or modify
5607 + * it under the terms of the GNU General Public License as published by
5608 + * the Free Software Foundation; either version 2 of the License, or
5609 + * (at your option) any later version.
5610 + *
5611 + * This program is distributed in the hope that it will be useful,
5612 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5613 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5614 + * GNU General Public License for more details.
5615 + *
5616 + * You should have received a copy of the GNU General Public License
5617 + * along with this program; if not, write to the Free Software
5618 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
5619 + */
5620 +#ifndef __ASM_ARCH_DMA_H
5621 +#define __ASM_ARCH_DMA_H
5622 +
5623 +#define MAX_DMA_ADDRESS                0xffffffff
5624 +
5625 +#define MAX_DMA_CHANNELS       0
5626 +
5627 +#endif /* _ASM_ARCH_DMA_H */
5628 +
5629 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/entry-macro.S
5630 ===================================================================
5631 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5632 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/entry-macro.S   2008-03-13 17:49:18.511875745 +0200
5633 @@ -0,0 +1,42 @@
5634 +/*
5635 + * include/asm-arm/arch-arm/entry-macro.S
5636 + *
5637 + * Low-level IRQ helper macros for ebsa110 platform.
5638 + *
5639 + * This file is licensed under  the terms of the GNU General Public
5640 + * License version 2. This program is licensed "as is" without any
5641 + * warranty of any kind, whether express or implied.
5642 + */
5643 +#include <asm/arch/platform.h>
5644 +#include <asm/arch/int_ctrl.h>
5645 +
5646 +
5647 +                .macro  disable_fiq
5648 +                .endm
5649 +
5650 +                .macro  get_irqnr_preamble, base, tmp
5651 +                .endm
5652 +
5653 +                .macro  arch_ret_to_user, tmp1, tmp2
5654 +                .endm
5655 +
5656 +                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
5657 +                ldr     \irqstat, =IRQ_STATUS(IO_ADDRESS(SL2312_INTERRUPT_BASE))
5658 +                ldr     \irqnr,[\irqstat]
5659 +                cmp     \irqnr,#0
5660 +                beq     2313f
5661 +                mov     \tmp,\irqnr
5662 +                mov     \irqnr,#0
5663 +2312:
5664 +                tst     \tmp, #1
5665 +                bne     2313f
5666 +                add     \irqnr, \irqnr, #1
5667 +                mov     \tmp, \tmp, lsr #1
5668 +                cmp     \irqnr, #31
5669 +                bcc     2312b
5670 +2313:
5671 +                .endm
5672 +
5673 +                .macro  irq_prio_table
5674 +                .endm
5675 +
5676 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/flash.h
5677 ===================================================================
5678 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5679 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/flash.h 2008-03-13 17:48:24.508798285 +0200
5680 @@ -0,0 +1,83 @@
5681 +#ifndef __ASM_ARM_ARCH_FLASH_H
5682 +#define __ASM_ARM_ARCH_FLASH_H
5683 +
5684 +#define FLASH_START                                     SL2312_FLASH_BASE
5685 +#define SFLASH_SIZE                                    0x00400000
5686 +#define SPAGE_SIZE                                     0x200
5687 +#define BLOCK_ERASE                                    0x50
5688 +#define BUFFER1_READ                                   0x54
5689 +#define BUFFER2_READ                                   0x56
5690 +#define PAGE_ERASE                                     0x81
5691 +#define MAIN_MEMORY_PAGE_READ                          0x52
5692 +#define MAIN_MEMORY_PROGRAM_BUFFER1                    0x82
5693 +#define MAIN_MEMORY_PROGRAM_BUFFER2                    0x85
5694 +#define BUFFER1_TO_MAIN_MEMORY                         0x83
5695 +#define BUFFER2_TO_MAIN_MEMORY                         0x86
5696 +#define MAIN_MEMORY_TO_BUFFER1                         0x53
5697 +#define MAIN_MEMORY_TO_BUFFER2                         0x55
5698 +#define BUFFER1_WRITE                                  0x84
5699 +#define BUFFER2_WRITE                                  0x87
5700 +#define AUTO_PAGE_REWRITE_BUFFER1                      0x58
5701 +#define AUTO_PAGE_REWRITE_BUFFER2                      0x59
5702 +#define READ_STATUS                                    0x57
5703 +
5704 +#define MAIN_MEMORY_PAGE_READ_SPI                      0xD2
5705 +#define BUFFER1_READ_SPI                               0xD4
5706 +#define BUFFER2_READ_SPI                               0xD6
5707 +#define READ_STATUS_SPI                                0xD7
5708 +
5709 +#define        FLASH_ACCESS_OFFSET                             0x00000010
5710 +#define        FLASH_ADDRESS_OFFSET                            0x00000014
5711 +#define        FLASH_WRITE_DATA_OFFSET                         0x00000018
5712 +#define        FLASH_READ_DATA_OFFSET                          0x00000018
5713 +#define SERIAL_FLASH_CHIP1_EN            0x00010000  // 16th bit = 1
5714 +#define SERIAL_FLASH_CHIP0_EN            0x00000000  // 16th bit = 0
5715 +#define AT45DB321_PAGE_SHIFT                    0xa
5716 +#define AT45DB642_PAGE_SHIFT                    0xb
5717 +#define CONTINUOUS_MODE                         0x00008000
5718 +
5719 +#define FLASH_ACCESS_ACTION_OPCODE                      0x0000
5720 +#define FLASH_ACCESS_ACTION_OPCODE_DATA                 0x0100
5721 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS               0x0200
5722 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_DATA          0x0300
5723 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_X_DATA          0x0400
5724 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_2X_DATA         0x0500
5725 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_3X_DATA         0x0600
5726 +#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA         0x0700
5727 +//#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_X_DATA        0x0600
5728 +//#define FLASH_ACCESS_ACTION_SHIFT_ADDRESS_4X_DATA       0x0700
5729 +
5730 +#define M25P80_PAGE_SIZE  0x100
5731 +#define M25P80_SECTOR_SIZE  0x10000
5732 +
5733 +
5734 +//#define M25P80_BULK_ERASE                                      1
5735 +//#define M25P80_SECTOR_ERASE                                    2
5736 +//#define M25P80_SECTOR_SIZE                                     0x10000
5737 +
5738 +#define M25P80_WRITE_ENABLE                            0x06
5739 +#define M25P80_WRITE_DISABLE                           0x04
5740 +#define M25P80_READ_STATUS                             0x05
5741 +#define M25P80_WRITE_STATUS                            0x01
5742 +#define M25P80_READ                                    0x03
5743 +#define M25P80_FAST_READ                               0x0B
5744 +#define M25P80_PAGE_PROGRAM                            0x02
5745 +#define M25P80_SECTOR_ERASE                            0xD8
5746 +#define M25P80_BULK_ERASE                              0xC7
5747 +#define FLASH_ERR_OK                                                   0x0
5748 +
5749 +extern void address_to_page(__u32, __u16 *, __u16 *);
5750 +extern void main_memory_page_read(__u8, __u16, __u16, __u8 *);
5751 +extern void buffer_to_main_memory(__u8, __u16);
5752 +extern void main_memory_to_buffer(__u8, __u16);
5753 +extern void main_memory_page_program(__u8, __u16, __u16, __u8);
5754 +extern void atmel_flash_read_page(__u32, __u8 *, __u32);
5755 +extern void atmel_erase_page(__u8, __u16);
5756 +extern void atmel_read_status(__u8, __u8 *);
5757 +extern void atmel_flash_program_page(__u32, __u8 *, __u32);
5758 +extern void atmel_buffer_write(__u8, __u16, __u8);
5759 +extern void flash_delay(void);
5760 +
5761 +extern int m25p80_sector_erase(__u32 address, __u32 schip_en);
5762 +
5763 +#endif
5764 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/gemini_cir.h
5765 ===================================================================
5766 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5767 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/gemini_cir.h    2008-03-13 17:48:24.508798285 +0200
5768 @@ -0,0 +1,102 @@
5769 +#ifndef _ASM_ARCH_CIR_H
5770 +#define _ASM_ARCH_CIR_H
5771 +#include <linux/ioctl.h>
5772 +
5773 +#define VCR_KEY_POWER          0x613E609F
5774 +#define TV1_KEY_POWER          0x40040100
5775 +#define TV1_KEY_POWER_EXT      0xBCBD
5776 +#define RC5_KER_POWER          0x0CF3
5777 +
5778 +#define VCC_H_ACT_PER          (16-1)
5779 +#define VCC_L_ACT_PER          (8-1)
5780 +#define VCC_DATA_LEN           (32-1)
5781 +#define TV1_H_ACT_PER          (8-1)
5782 +#define TV1_L_ACT_PER          (4-1)
5783 +#define TV1_DATA_LEN           (48-1)
5784 +
5785 +#define VCC_BAUD               540
5786 +#define TV1_BAUD               430
5787 +#ifdef  CONFIG_SL3516_ASIC
5788 +#define        EXT_CLK                 60
5789 +#else
5790 +#define        EXT_CLK                 20
5791 +#endif
5792 +
5793 +#define        NEC_PROTOCOL    0x0
5794 +#define        RC5_PROTOCOL    0x1
5795 +#define VCC_PROTOCOL   0x0
5796 +#define TV1_PROTOCOL   0x01
5797 +
5798 +#ifndef        SL2312_CIR_BASE
5799 +#define        SL2312_CIR_BASE         0x4C000000
5800 +#endif
5801 +#define        CIR_BASE_ADDR           IO_ADDRESS(SL2312_CIR_BASE)
5802 +#define STORLINK_CIR_ID                0x00010400
5803 +
5804 +#define        CIR_IP_ID               *(volatile unsigned int *)(CIR_BASE_ADDR + 0x00)
5805 +#define        CIR_CTR_REG             *(volatile unsigned int *)(CIR_BASE_ADDR + 0x04)
5806 +#define        CIR_STATUS_REG          *(volatile unsigned int *)(CIR_BASE_ADDR + 0x08)
5807 +#define        CIR_RX_REG              *(volatile unsigned int *)(CIR_BASE_ADDR + 0x0C)
5808 +#define        CIR_RX_EXT_REG          *(volatile unsigned int *)(CIR_BASE_ADDR + 0x10)
5809 +#define        CIR_PWR_REG             *(volatile unsigned int *)(CIR_BASE_ADDR + 0x14)
5810 +#define        CIR_PWR_EXT_REG         *(volatile unsigned int *)(CIR_BASE_ADDR + 0x18)
5811 +#define        CIR_TX_CTR_REG          *(volatile unsigned int *)(CIR_BASE_ADDR + 0x1C)
5812 +#define        CIR_TX_FEQ_REG          *(volatile unsigned int *)(CIR_BASE_ADDR + 0x20)
5813 +#define        CIR_TX_REG              *(volatile unsigned int *)(CIR_BASE_ADDR + 0x24)
5814 +#define        CIR_TX_EXT_REG          *(volatile unsigned int *)(CIR_BASE_ADDR + 0x28)
5815 +
5816 +
5817 +#ifndef        SL2312_POWER_CTRL_BASE
5818 +#define        SL2312_POWER_CTRL_BASE          0x4B000000
5819 +#endif
5820 +
5821 +#ifndef PWR_BASE_ADDR
5822 +#define        PWR_BASE_ADDR           IO_ADDRESS(SL2312_POWER_CTRL_BASE)
5823 +#endif
5824 +#define        PWR_CTRL_ID             *(unsigned int*)(PWR_BASE_ADDR+0x00)
5825 +#define        PWR_CTRL_REG            *(unsigned int*)(PWR_BASE_ADDR+0x04)
5826 +#define        PWR_STATUS_REG          *(unsigned int*)(PWR_BASE_ADDR+0x08)
5827 +
5828 +
5829 +#define BIT(x)                 (1<<x)
5830 +#define TX_STATUS              BIT(3)
5831 +
5832 +#define        PWR_STAT_CIR            0x10
5833 +#define        PWR_STAT_RTC            0x20
5834 +#define        PWR_STAT_PUSH           0x40
5835 +#define        PWR_SHUTDOWN            0x01
5836 +
5837 +#define CARR_FREQ              38000
5838 +
5839 +struct cir_ioctl_data {
5840 +       __u32 data;
5841 +};
5842 +struct cir_ioctl_data48 {
5843 +       __u32 timeout;
5844 +       __u32 length;
5845 +       __u8  ret;
5846 +       __u32 data;
5847 +       __u32 data_ext;
5848 +};
5849 +#define OLD_DATA                       0
5850 +#define NEW_RECEIVE                    1
5851 +
5852 +#define        CIR_IOCTL_BASE          ('I'|'R')
5853 +#define CIR_SET_BAUDRATE                       _IOW (CIR_IOCTL_BASE,  0, struct cir_ioctl_data)
5854 +#define CIR_SET_HIGH_PERIOD                    _IOW (CIR_IOCTL_BASE,  1, struct cir_ioctl_data)
5855 +#define CIR_SET_LOW_PERIOD                     _IOW (CIR_IOCTL_BASE,  2, struct cir_ioctl_data)
5856 +#define CIR_SET_PROTOCOL                       _IOW (CIR_IOCTL_BASE,  3, struct cir_ioctl_data)
5857 +#define CIR_SET_ENABLE_COMPARE         _IOW (CIR_IOCTL_BASE,  4, struct cir_ioctl_data)
5858 +#define CIR_SET_ENABLE_DEMOD           _IOW (CIR_IOCTL_BASE,  5, struct cir_ioctl_data)
5859 +#define CIR_SET_POWER_KEY                      _IOW (CIR_IOCTL_BASE,  6, struct cir_ioctl_data)
5860 +#define CIR_GET_BAUDRATE                       _IOR (CIR_IOCTL_BASE,  7, struct cir_ioctl_data)
5861 +#define CIR_GET_HIGH_PERIOD                    _IOR (CIR_IOCTL_BASE,  8 ,struct cir_ioctl_data)
5862 +#define CIR_GET_LOW_PERIOD                     _IOR (CIR_IOCTL_BASE,  9 ,struct cir_ioctl_data)
5863 +#define CIR_GET_PROTOCOL                       _IOR (CIR_IOCTL_BASE, 10, struct cir_ioctl_data)
5864 +#define CIR_GET_ENABLE_COMPARE         _IOR (CIR_IOCTL_BASE, 11, struct cir_ioctl_data)
5865 +#define CIR_GET_ENABLE_DEMOD           _IOR (CIR_IOCTL_BASE, 12, struct cir_ioctl_data)
5866 +#define CIR_GET_POWER_KEY                      _IOR (CIR_IOCTL_BASE, 13, struct cir_ioctl_data)
5867 +#define CIR_GET_DATA                           _IOWR (CIR_IOCTL_BASE, 14, struct cir_ioctl_data48)
5868 +#define CIR_WAIT_INT_DATA                      _IOWR (CIR_IOCTL_BASE, 15, struct cir_ioctl_data48)
5869 +
5870 +#endif //_ASM_ARCH_CIR_H
5871 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/gemini_gpio.h
5872 ===================================================================
5873 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5874 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/gemini_gpio.h   2008-03-13 17:48:24.508798285 +0200
5875 @@ -0,0 +1,77 @@
5876 +/*
5877 + * FILE NAME gemini_gpio.h
5878 + *
5879 + * BRIEF MODULE DESCRIPTION
5880 + *     Generic Gemini GPIO
5881 + *
5882 + *  Author: Storlink Software [Device driver]
5883 + *          Jason Lee <jason@storlink.com.tw>
5884 + *
5885 + * Copyright 2005 Storlink Inc.
5886 + *
5887 + *  This program is free software; you can redistribute  it and/or modify it
5888 + *  under  the terms of  the GNU General  Public License as published by the
5889 + *  Free Software Foundation;  either version 2 of the  License, or (at your
5890 + *  option) any later version.
5891 + *
5892 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
5893 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
5894 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
5895 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
5896 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
5897 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
5898 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
5899 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
5900 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
5901 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
5902 + *
5903 + *  You should have received a copy of the  GNU General Public License along
5904 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
5905 + *  675 Mass Ave, Cambridge, MA 02139, USA.
5906 + */
5907 +
5908 +#ifndef __GEMINI_GPIO_H
5909 +#define __GEMINI_GPIO_H
5910 +
5911 +#include <linux/ioctl.h>
5912 +
5913 +#define STATUS_HIGH    1
5914 +#define STATUS_LOW     0
5915 +#define DIRECT_OUT     1
5916 +#define DIRECT_IN      0
5917 +
5918 +#define EDGE_TRIG      0
5919 +#define RISING_EDGE    0
5920 +#define FALL_EDGE      1
5921 +#define SINGLE_EDGE    0
5922 +#define BOTH_EDGE      1
5923 +
5924 +#define LEVEL_TRIG     1
5925 +#define HIGH_ACTIVE    0
5926 +#define LOW_ACTIVE     1
5927 +
5928 +struct gemini_gpio_ioctl_data {
5929 +       __u32 pin;
5930 +       __u8 status;                    // status or pin direction
5931 +                                       // 0: status low or Input
5932 +                                       // 1: status high or Output
5933 +
5934 +       /* these member are used to config GPIO interrupt parameter */
5935 +       __u8    use_default;            // if not sure ,set this argument 1
5936 +       __u8    trig_type;              // 0/1:edge/level triger ?
5937 +       __u8    trig_polar;             // 0/1:rising/falling high/low active ?
5938 +       __u8    trig_both;              // 0/1:single/both detect both ?
5939 +};
5940 +
5941 +#define GEMINI_GPIO_IOCTL_BASE 'Z'
5942 +
5943 +#define GEMINI_SET_GPIO_PIN_DIR                _IOW (GEMINI_GPIO_IOCTL_BASE,16, struct gemini_gpio_ioctl_data)
5944 +#define        GEMINI_SET_GPIO_PIN_STATUS      _IOW (GEMINI_GPIO_IOCTL_BASE,17, struct gemini_gpio_ioctl_data)
5945 +#define        GEMINI_GET_GPIO_PIN_STATUS      _IOWR(GEMINI_GPIO_IOCTL_BASE,18, struct gemini_gpio_ioctl_data)
5946 +#define GEMINI_WAIT_GPIO_PIN_INT       _IOWR(GEMINI_GPIO_IOCTL_BASE,19, struct gemini_gpio_ioctl_data)
5947 +
5948 +
5949 +extern void init_gpio_int(__u32 pin,__u8 trig_type,__u8 trig_polar,__u8 trig_both);
5950 +extern int request_gpio_irq(int bit,void (*handler)(int),char level,char high,char both);
5951 +extern int free_gpio_irq(int bit);
5952 +#endif
5953 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/gemini_i2s.h
5954 ===================================================================
5955 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5956 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/gemini_i2s.h    2008-03-13 17:48:24.508798285 +0200
5957 @@ -0,0 +1,169 @@
5958 +#ifndef __GEMINI_I2S_H__
5959 +#define __GEMINI_I2S_H__
5960 +#include <linux/ioctl.h>
5961 +#include <linux/types.h>
5962 +#include <asm/arch-sl2312/irqs.h>
5963 +
5964 +typedef __u16 UINT16;
5965 +typedef __u32 UINT32;
5966 +typedef __u8 UINT8;
5967 +typedef __u8 BOOL;
5968 +
5969 +/***************************************/
5970 +/* define GPIO module base address     */
5971 +/***************************************/
5972 +#define DMA_CONTROL_PHY_BASE  (IO_ADDRESS(SL2312_GENERAL_DMA_BASE))
5973 +#define DMA_CONTROL_SSP_BASE  (IO_ADDRESS(SL2312_SSP_CTRL_BASE))
5974 +#define SSP_INT                                IRQ_SSP
5975 +#define GPIO_BASE_ADDR      (IO_ADDRESS(SL2312_GPIO_BASE))
5976 +#define GPIO_BASE_ADDR1      (IO_ADDRESS(SL2312_GPIO_BASE1))
5977 +#define GLOBAL_BASE      (IO_ADDRESS(SL2312_GLOBAL_BASE))
5978 +
5979 +/* define read/write register utility */
5980 +#define READ_SSP_REG(offset)                   (__raw_readl(offset+DMA_CONTROL_SSP_BASE))
5981 +#define WRITE_SSP_REG(offset,val)      (__raw_writel(val,offset+DMA_CONTROL_SSP_BASE))
5982 +
5983 +#define READ_GPIO_REG(offset)                  (__raw_readl(offset+GPIO_BASE_ADDR))
5984 +#define WRITE_GPIO_REG(offset,val)     (__raw_writel(val,offset+GPIO_BASE_ADDR))
5985 +
5986 +#define READ_GPIO1_REG(offset)                 (__raw_readl(offset+GPIO_BASE_ADDR1))
5987 +#define WRITE_GPIO1_REG(offset,val)    (__raw_writel(val,offset+GPIO_BASE_ADDR1))
5988 +
5989 +#define READ_DMA_REG(offset)                   (__raw_readl(offset+DMA_CONTROL_PHY_BASE))
5990 +#define WRITE_DMA_REG(offset,val)      (__raw_writel(val,offset+DMA_CONTROL_PHY_BASE))
5991 +
5992 +#define READ_GLOBAL_REG(offset)                        (__raw_readl(offset+GLOBAL_BASE))
5993 +#define WRITE_GLOBAL_REG(offset,val)   (__raw_writel(val,offset+GLOBAL_BASE))
5994 +
5995 +#define SSP_GPIO_INT           IRQ_GPIO
5996 +
5997 +#ifndef CONFIG_SL3516_ASIC
5998 +#define SSP_GPIO_INT_BIT    0x00000400                         //GPIO[10] : SLIC interrupt pin
5999 +
6000 +#define GPIO_EECK           0x00000040         /*   SCK: GPIO[06]   */
6001 +#define GPIO_EECS           0x00000080                 /*   SCS: GPIO[07]   */
6002 +#define GPIO_MISO           0x00000200         /*   SDO: GPIO[09]   receive from 6996*/
6003 +#define GPIO_MOSI           0x00000100         /*   SDI: GPIO[08]   send to 6996*/
6004 +#define GPIO_MISO_BIT   9
6005 +#else
6006 +#define SSP_GPIO_INT_BIT    0x00000001                         //GPIO[0] : SLIC interrupt pin
6007 +
6008 +//#if 0
6009 +//#define GPIO_EECK         0x80000000         /*   SCK: GPIO1[31]   */
6010 +//#define GPIO_EECS         0x40000000                 /*   SCS: GPIO1[30]   */
6011 +//#define GPIO_MISO         0x20000000         /*   SDO: GPIO1[29]   receive from 6996*/
6012 +//#define GPIO_MOSI         0x10000000         /*   SDI: GPIO1[28]   send to 6996*/
6013 +//#define GPIO_MISO_BIT        29
6014 +//#else
6015 +//#define GPIO_EECK         0x00000100         /*   SCK: GPIO1[08]   */
6016 +//#define GPIO_EECS         0x08000000                 /*   SCS: GPIO1[27]   */
6017 +//#define GPIO_MISO         0x00000080         /*   SDO: GPIO1[07]   receive from 6996*/
6018 +//#define GPIO_MOSI         0x00000200         /*   SDI: GPIO1[09]   send to 6996*/
6019 +//#define GPIO_MISO_BIT        7
6020 +//#endif
6021 +#endif
6022 +
6023 +
6024 +enum GPIO_REG
6025 +{
6026 +       GPIO_DATA_OUT           = 0x00,
6027 +       GPIO_DATA_IN            = 0x04,
6028 +       GPIO_PIN_DIR            = 0x08,
6029 +       GPIO_BY_PASS            = 0x0c,
6030 +       GPIO_DATA_SET           = 0x10,
6031 +       GPIO_DATA_CLEAR         = 0x14,
6032 +       GPIO_INT_ENABLE     = 0x20,
6033 +       GPIO_INT_RAWSTATE   = 0x24,
6034 +       GPIO_INT_MASKSTATE  = 0x28,
6035 +       GPIO_INT_MASK       = 0x2C,
6036 +       GPIO_INT_CLEAR      = 0x30,
6037 +       GPIO_INT_TRIGGER    = 0x34,
6038 +       GPIO_INT_BOTH       = 0x38,
6039 +       GPIO_INT_POLARITY   = 0x3C
6040 +};
6041 +
6042 +typedef struct
6043 +{
6044 +       UINT32 src_addr;
6045 +       UINT32 dst_addr;
6046 +       UINT32 llp;
6047 +       UINT32 ctrl_size;
6048 +       UINT32 owner;
6049 +}DMA_LLP_t;
6050 +
6051 +typedef struct
6052 +{
6053 +       UINT32 owner;
6054 +       UINT32 src_addr;
6055 +       UINT32 ctrl_size;
6056 +}IOCTL_LLP_t;
6057 +
6058 +typedef unsigned char byte;
6059 +typedef unsigned short word;
6060 +typedef unsigned long dword;
6061 +
6062 +/* DMA Registers */
6063 +#define        DMA_INT                                 0x00000000
6064 +#define        DMA_INT_TC                              0x00000004
6065 +#define        DMA_CFG                                 0x00000024
6066 +#define        DMA_INT_TC_CLR                          0x00000008
6067 +#define        DMA_TC                                          0x00000014
6068 +#define        DMA_CSR                                         0x00000024
6069 +#define        DMA_SYNC                                        0x00000028
6070 +
6071 +#define        DMA_CH2_CSR                             0x00000140
6072 +#define        DMA_CH2_CFG                             0x00000144
6073 +#define        DMA_CH2_SRC_ADDR                0x00000148
6074 +#define        DMA_CH2_DST_ADDR                0x0000014c
6075 +#define        DMA_CH2_LLP                             0x00000150
6076 +#define        DMA_CH2_SIZE                            0x00000154
6077 +
6078 +#define        DMA_CH3_CSR                             0x00000160
6079 +#define        DMA_CH3_CFG                             0x00000164
6080 +#define        DMA_CH3_SRC_ADDR                0x00000168
6081 +#define        DMA_CH3_DST_ADDR                0x0000016c
6082 +#define        DMA_CH3_LLP                             0x00000170
6083 +#define        DMA_CH3_SIZE                            0x00000174
6084 +
6085 +#define    SSP_DEVICE_ID                       0x00
6086 +#define    SSP_CTRL_STATUS                     0x04
6087 +#define           SSP_FRAME_CTRL           0x08
6088 +#define    SSP_BAUD_RATE            0x0c
6089 +#define    SSP_FRAME_CTRL2          0x10
6090 +#define    SSP_FIFO_CTRL            0x14
6091 +#define    SSP_TX_SLOT_VALID0       0x18
6092 +#define    SSP_TX_SLOT_VALID1       0x1c
6093 +#define    SSP_TX_SLOT_VALID2       0x20
6094 +#define    SSP_TX_SLOT_VALID3       0x24
6095 +#define    SSP_RX_SLOT_VALID0       0x28
6096 +#define    SSP_RX_SLOT_VALID1       0x2c
6097 +#define    SSP_RX_SLOT_VALID2       0x30
6098 +#define    SSP_RX_SLOT_VALID3       0x34
6099 +#define    SSP_SLOT_SIZE0           0x38
6100 +#define    SSP_SLOT_SIZE1           0x3c
6101 +#define    SSP_SLOT_SIZE2           0x40
6102 +#define    SSP_SLOT_SIZE3           0x44
6103 +#define    SSP_READ_PORT            0x48
6104 +#define    SSP_WRITE_PORT           0x4c
6105 +
6106 +
6107 +
6108 +#define SSP_I2S_INIT_BUF                       _IO  ('q', 0x00)
6109 +#define SSP_I2S_STOP_DMA                       _IO  ('q', 0x01)
6110 +#define SSP_I2S_FILE_LEN                       _IOW  ('q', 0x2, int)
6111 +/*
6112 +#define SSP_GET_HOOK_STATUS                    _IOR  ('q', 0xC0, int)
6113 +#define SSP_GET_LINEFEED                       _IOR  ('q', 0xC1, int)
6114 +#define SSP_SET_LINEFEED                       _IOW  ('q', 0xC2, int)
6115 +#define SSP_GET_REG                 _IOWR ('q', 0xC3, struct Ssp_reg *)
6116 +#define SSP_SET_REG                 _IOWR ('q', 0xC4, struct Ssp_reg *)
6117 +#define SSP_GEN_OFFHOOK_TONE           _IO   ('q', 0xC5)
6118 +#define SSP_GEN_BUSY_TONE                      _IO   ('q', 0xC6)
6119 +#define SSP_GEN_RINGBACK_TONE          _IO   ('q', 0xC7)
6120 +#define SSP_GEN_CONGESTION_TONE                _IO   ('q', 0xC8)
6121 +#define SSP_DISABLE_DIALTONE           _IO   ('q', 0xC9)
6122 +#define SSP_PHONE_RING_START           _IO   ('q', 0xCA)
6123 +*/
6124 +
6125 +
6126 +#endif //__GEMINI_I2S_H__
6127 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/gemini_ssp.h
6128 ===================================================================
6129 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
6130 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/gemini_ssp.h    2008-03-13 17:48:24.508798285 +0200
6131 @@ -0,0 +1,263 @@
6132 +/******************************************************************************
6133 + *    gemini_ssp.h
6134 + *
6135 + *
6136 + *****************************************************************************/
6137 +
6138 +#include <linux/types.h>
6139 +#include <asm/arch-sl2312/irqs.h>
6140 +#include <linux/phonedev.h>
6141 +#include <linux/telephony.h>
6142 +//#include "proslic.h"
6143 +
6144 +typedef __u16 UINT16;
6145 +typedef __u32 UINT32;
6146 +typedef __u8 UINT8;
6147 +typedef __u8 BOOL;
6148 +
6149 +#define TRUE 1
6150 +#define FALSE 0
6151 +
6152 +/***************************************/
6153 +/* define GPIO module base address     */
6154 +/***************************************/
6155 +#define DMA_CONTROL_PHY_BASE  (IO_ADDRESS(SL2312_GENERAL_DMA_BASE))
6156 +#define DMA_CONTROL_SSP_BASE  (IO_ADDRESS(SL2312_SSP_CTRL_BASE))
6157 +#define SSP_INT                                IRQ_SSP
6158 +#define GPIO_BASE_ADDR      (IO_ADDRESS(SL2312_GPIO_BASE))
6159 +#define GPIO_BASE_ADDR1      (IO_ADDRESS(SL2312_GPIO_BASE1))
6160 +#define GLOBAL_BASE      (IO_ADDRESS(SL2312_GLOBAL_BASE))
6161 +
6162 +/* define read/write register utility */
6163 +#define READ_SSP_REG(offset)                   (__raw_readl(offset+DMA_CONTROL_SSP_BASE))
6164 +#define WRITE_SSP_REG(offset,val)      (__raw_writel(val,offset+DMA_CONTROL_SSP_BASE))
6165 +
6166 +#define READ_GPIO_REG(offset)                  (__raw_readl(offset+GPIO_BASE_ADDR))
6167 +#define WRITE_GPIO_REG(offset,val)     (__raw_writel(val,offset+GPIO_BASE_ADDR))
6168 +
6169 +#define READ_GPIO1_REG(offset)                 (__raw_readl(offset+GPIO_BASE_ADDR1))
6170 +#define WRITE_GPIO1_REG(offset,val)    (__raw_writel(val,offset+GPIO_BASE_ADDR1))
6171 +
6172 +#define READ_DMA_REG(offset)                   (__raw_readl(offset+DMA_CONTROL_PHY_BASE))
6173 +#define WRITE_DMA_REG(offset,val)      (__raw_writel(val,offset+DMA_CONTROL_PHY_BASE))
6174 +
6175 +#define READ_GLOBAL_REG(offset)                        (__raw_readl(offset+GLOBAL_BASE))
6176 +#define WRITE_GLOBAL_REG(offset,val)   (__raw_writel(val,offset+GLOBAL_BASE))
6177 +
6178 +
6179 +#define SSP_GPIO_INT           IRQ_GPIO
6180 +
6181 +#ifndef CONFIG_SL3516_ASIC
6182 +#define SSP_GPIO_INT_BIT    0x00000400                         //GPIO[10] : SLIC interrupt pin
6183 +
6184 +#define GPIO_EECK           0x00000040         /*   SCK: GPIO[06]   */
6185 +#define GPIO_EECS           0x00000080                 /*   SCS: GPIO[07]   */
6186 +#define GPIO_MISO           0x00000200         /*   SDO: GPIO[09]   receive from 6996*/
6187 +#define GPIO_MOSI           0x00000100         /*   SDI: GPIO[08]   send to 6996*/
6188 +#define GPIO_MISO_BIT   9
6189 +#else
6190 +#define SSP_GPIO_INT_BIT    0x00000001                         //GPIO[0] : SLIC interrupt pin
6191 +
6192 +//#if 0
6193 +//#define GPIO_EECK         0x80000000         /*   SCK: GPIO1[31]   */
6194 +//#define GPIO_EECS         0x40000000                 /*   SCS: GPIO1[30]   */
6195 +//#define GPIO_MISO         0x20000000         /*   SDO: GPIO1[29]   receive from 6996*/
6196 +//#define GPIO_MOSI         0x10000000         /*   SDI: GPIO1[28]   send to 6996*/
6197 +//#define GPIO_MISO_BIT        29
6198 +//#else
6199 +//#define GPIO_EECK         0x00000100         /*   SCK: GPIO1[08]   */
6200 +//#define GPIO_EECS         0x08000000                 /*   SCS: GPIO1[27]   */
6201 +//#define GPIO_MISO         0x00000080         /*   SDO: GPIO1[07]   receive from 6996*/
6202 +//#define GPIO_MOSI         0x00000200         /*   SDI: GPIO1[09]   send to 6996*/
6203 +//#define GPIO_MISO_BIT        7
6204 +//#endif
6205 +#endif
6206 +
6207 +
6208 +enum GPIO_REG
6209 +{
6210 +       GPIO_DATA_OUT           = 0x00,
6211 +       GPIO_DATA_IN            = 0x04,
6212 +       GPIO_PIN_DIR            = 0x08,
6213 +       GPIO_BY_PASS            = 0x0c,
6214 +       GPIO_DATA_SET           = 0x10,
6215 +       GPIO_DATA_CLEAR         = 0x14,
6216 +       GPIO_INT_ENABLE     = 0x20,
6217 +       GPIO_INT_RAWSTATE   = 0x24,
6218 +       GPIO_INT_MASKSTATE  = 0x28,
6219 +       GPIO_INT_MASK       = 0x2C,
6220 +       GPIO_INT_CLEAR      = 0x30,
6221 +       GPIO_INT_TRIGGER    = 0x34,
6222 +       GPIO_INT_BOTH       = 0x38,
6223 +       GPIO_INT_POLARITY   = 0x3C
6224 +};
6225 +
6226 +
6227 +#define SPI_ADD_LEN         7                  // bits of Address
6228 +#define SPI_DAT_LEN         8                  // bits of Data
6229 +
6230 +
6231 +
6232 +//#ifdef MIDWAY_DIAG
6233 +#define        DAISY_MODE      1
6234 +#if (DAISY_MODE==1)
6235 +#define NUMBER_OF_CHAN 2
6236 +#else
6237 +#define NUMBER_OF_CHAN 1
6238 +#endif
6239 +#define LLP_SIZE   8
6240 +#define SBUF_SIZE  512 //0xff0 //2560
6241 +#define DBUF_SIZE  SBUF_SIZE*NUMBER_OF_CHAN //0xff0 //2560
6242 +#define TBUF_SIZE  (LLP_SIZE)*DBUF_SIZE
6243 +#define DESC_NUM   1
6244 +#define DTMF_NUM   20
6245 +
6246 +/* define owner bit of SSP */
6247 +//data into SSP and transfer to AP==> SSP_Rx
6248 +//data out of SSP and transfer to SLIC==> SSP_Tx
6249 +#define CPU            0
6250 +#define DMA            1
6251 +
6252 +#define DMA_DEMO   0
6253 +#define DMA_NDEMO  1
6254 +//#define DMA_NONE   2
6255 +
6256 +enum exceptions {
6257 +       PROSLICiNSANE,
6258 +       TIMEoUTpOWERuP,
6259 +       TIMEoUTpOWERdOWN,
6260 +       POWERlEAK,
6261 +       TIPoRrINGgROUNDsHORT,
6262 +       POWERaLARMQ1,
6263 +       POWERaLARMQ2,
6264 +       POWERaLARMQ3,
6265 +       POWERaLARMQ4,
6266 +       POWERaLARMQ5,
6267 +       OWERaLARMQ6,
6268 +       CM_CAL_ERR
6269 +};
6270 +
6271 +typedef struct
6272 +{
6273 +       UINT32 src_addr;
6274 +       UINT32 dst_addr;
6275 +       UINT32 llp;
6276 +       UINT32 ctrl_size;
6277 +}DMA_LLP_t;
6278 +
6279 +typedef struct {
6280 +       unsigned int own ;
6281 +       char  *tbuf;
6282 +       //UINT32 *LinkAddrT;
6283 +       DMA_LLP_t LLPT[LLP_SIZE];
6284 +}DMA_Tx_t;
6285 +
6286 +typedef struct {
6287 +       unsigned int own ;
6288 +       char  *rbuf;
6289 +       //UINT32 *LinkAddrR;
6290 +       DMA_LLP_t LLPR[LLP_SIZE];
6291 +}DMA_Rx_t;
6292 +
6293 +//typedef struct {
6294 +//     //UINT32 init_stat;
6295 +//     struct chipStruct chipData ; /* Represents a proslics state, cached information, and timers */
6296 +//     struct phone_device p;
6297 +//
6298 +//
6299 +//}SSP_SLIC;
6300 +
6301 +
6302 +
6303 +/* DMA Registers */
6304 +#define        DMA_INT                                 0x00000000
6305 +#define        DMA_INT_TC                              0x00000004
6306 +#define        DMA_CFG                                 0x00000024
6307 +#define        DMA_INT_TC_CLR                          0x00000008
6308 +#define        DMA_TC                                          0x00000014
6309 +#define        DMA_CSR                                         0x00000024
6310 +#define        DMA_SYNC                                        0x00000028
6311 +
6312 +#define        DMA_CH2_CSR                             0x00000140
6313 +#define        DMA_CH2_CFG                             0x00000144
6314 +#define        DMA_CH2_SRC_ADDR                0x00000148
6315 +#define        DMA_CH2_DST_ADDR                0x0000014c
6316 +#define        DMA_CH2_LLP                             0x00000150
6317 +#define        DMA_CH2_SIZE                            0x00000154
6318 +
6319 +#define        DMA_CH3_CSR                             0x00000160
6320 +#define        DMA_CH3_CFG                             0x00000164
6321 +#define        DMA_CH3_SRC_ADDR                0x00000168
6322 +#define        DMA_CH3_DST_ADDR                0x0000016c
6323 +#define        DMA_CH3_LLP                             0x00000170
6324 +#define        DMA_CH3_SIZE                            0x00000174
6325 +
6326 +#define    SSP_DEVICE_ID                       0x00
6327 +#define    SSP_CTRL_STATUS                     0x04
6328 +#define           SSP_FRAME_CTRL           0x08
6329 +#define    SSP_BAUD_RATE            0x0c
6330 +#define    SSP_FRAME_CTRL2          0x10
6331 +#define    SSP_FIFO_CTRL            0x14
6332 +#define    SSP_TX_SLOT_VALID0       0x18
6333 +#define    SSP_TX_SLOT_VALID1       0x1c
6334 +#define    SSP_TX_SLOT_VALID2       0x20
6335 +#define    SSP_TX_SLOT_VALID3       0x24
6336 +#define    SSP_RX_SLOT_VALID0       0x28
6337 +#define    SSP_RX_SLOT_VALID1       0x2c
6338 +#define    SSP_RX_SLOT_VALID2       0x30
6339 +#define    SSP_RX_SLOT_VALID3       0x34
6340 +#define    SSP_SLOT_SIZE0           0x38
6341 +#define    SSP_SLOT_SIZE1           0x3c
6342 +#define    SSP_SLOT_SIZE2           0x40
6343 +#define    SSP_SLOT_SIZE3           0x44
6344 +#define    SSP_READ_PORT            0x48
6345 +#define    SSP_WRITE_PORT           0x4c
6346 +
6347 +
6348 +void printFreq_Revision(int num);
6349 +void SLIC_SPI_write(int num, UINT8 ,UINT8);
6350 +UINT8 SLIC_SPI_read(int num, UINT8);
6351 +void SLIC_SPI_write_bit(char);
6352 +void SLIC_SPI_ind_write(int num, UINT8, UINT16);
6353 +UINT16 SLIC_SPI_ind_read(int num, UINT8);
6354 +void SLIC_SPI_CS_enable(UINT8);
6355 +unsigned int SLIC_SPI_read_bit(void);
6356 +void SLIC_SPI_pre_st(void);
6357 +UINT32 ssp_init(void);
6358 +UINT16 SLIC_SPI_get_identifier(int num);
6359 +int selfTest(int num);
6360 +void exception (int num, enum exceptions e);
6361 +int SLIC_init(int num);
6362 +UINT8 version(int num);
6363 +UINT8 chipType (int num);
6364 +void SLIC_init_ind_reg_set(int num);
6365 +UINT8 powerUp(int num);
6366 +UINT8 powerLeakTest(int num);
6367 +void SLIC_init_reg_set(int num);
6368 +int calibrate(int num);
6369 +void goActive(int num);
6370 +void clearInterrupts(int num);
6371 +void setState(int num, int);
6372 +UINT8 loopStatus(int num);
6373 +int verifyIndirectRegisters(int num);
6374 +int verifyIndirectReg(int num, UINT8 , UINT16);
6375 +void sendProSLICID(int num);
6376 +void disableOscillators(int num);
6377 +UINT8 checkSum(int num, char * string );
6378 +void fskInitialization (int num);
6379 +void fskByte(int num, UINT8 c);
6380 +void waitForInterrupt (int num);
6381 +//void findNumber(void);
6382 +UINT8 dtmfAction(int num);
6383 +UINT8 digit(int num);
6384 +void interrupt_init(void);
6385 +//void gemini_slic_isr (int );
6386 +int groundShort(int num);
6387 +void clearAlarmBits(int num);
6388 +void stopRinging(int num);
6389 +void activateRinging(int num);
6390 +void initializeLoopDebounceReg(int num);
6391 +void busyJapan(int num) ;
6392 +void ringBackJapan(int num) ;
6393 +void stateMachine(int num);
6394 +
6395 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/hardware.h
6396 ===================================================================
6397 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
6398 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/hardware.h      2008-03-14 12:48:02.872746442 +0200
6399 @@ -0,0 +1,47 @@
6400 +/*
6401 + *  linux/include/asm-arm/arch-epxa10/hardware.h
6402 + *
6403 + *  This file contains the hardware definitions of the Integrator.
6404 + *
6405 + *  Copyright (C) 1999 ARM Limited.
6406 + *  Copyright (C) 2001 Altera Corporation
6407 + *
6408 + * This program is free software; you can redistribute it and/or modify
6409 + * it under the terms of the GNU General Public License as published by
6410 + * the Free Software Foundation; either version 2 of the License, or
6411 + * (at your option) any later version.
6412 + *
6413 + * This program is distributed in the hope that it will be useful,
6414 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6415 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6416 + * GNU General Public License for more details.
6417 + *
6418 + * You should have received a copy of the GNU General Public License
6419 + * along with this program; if not, write to the Free Software
6420 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6421 + */
6422 +#ifndef __ASM_ARCH_HARDWARE_H
6423 +#define __ASM_ARCH_HARDWARE_H
6424 +
6425 +#include <asm/arch/platform.h>
6426 +
6427 +#define pcibios_assign_all_busses()    1
6428 +
6429 +/*
6430 + * Where in virtual memory the IO devices (timers, system controllers
6431 + * and so on)
6432 + *
6433 + * macro to get at IO space when running virtually
6434 +*/
6435 +
6436 +#define IO_ADDRESS(x)      (((x&0xfff00000)>>4)|(x & 0x000fffff)|0xF0000000)
6437 +#define FLASH_VBASE         0xFE000000
6438 +#define FLASH_SIZE 0x1000000// 8M
6439 +#define FLASH_START         SL2312_FLASH_BASE
6440 +#define FLASH_VADDR(x)      ((x & 0x00ffffff)|0xFE000000)       // flash virtual address
6441 +
6442 +#define PCIBIOS_MIN_IO                                 0x100           // 0x000-0x100 AHB reg and PCI config, data
6443 +#define PCIBIOS_MIN_MEM                                        0
6444 +
6445 +#endif
6446 +
6447 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/int_ctrl.h
6448 ===================================================================
6449 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
6450 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/int_ctrl.h      2008-03-13 17:48:24.508798285 +0200
6451 @@ -0,0 +1,171 @@
6452 +/*
6453 + *
6454 + *  This file contains the register definitions for the Excalibur
6455 + *  Timer TIMER00.
6456 + *
6457 + *  Copyright (C) 2001 Altera Corporation
6458 + *
6459 + * This program is free software; you can redistribute it and/or modify
6460 + * it under the terms of the GNU General Public License as published by
6461 + * the Free Software Foundation; either version 2 of the License, or
6462 + * (at your option) any later version.
6463 + *
6464 + * This program is distributed in the hope that it will be useful,
6465 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6466 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6467 + * GNU General Public License for more details.
6468 + *
6469 + * You should have received a copy of the GNU General Public License
6470 + * along with this program; if not, write to the Free Software
6471 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6472 + */
6473 +
6474 +#ifndef __INT_CTRL_H
6475 +#define __INT_CTRL_H
6476 +
6477 +#define PCI_IRQ_OFFSET                   64    /* PCI start IRQ number */
6478 +#define FIQ_OFFSET                32
6479 +
6480 +#define IRQ_SOURCE(base_addr)   (INT_CTRL_TYPE(base_addr  + 0x00))
6481 +#define IRQ_MASK(base_addr)     (INT_CTRL_TYPE (base_addr  + 0x04 ))
6482 +#define IRQ_CLEAR(base_addr)    (INT_CTRL_TYPE (base_addr  + 0x08 ))
6483 +#define IRQ_TMODE(base_addr)    (INT_CTRL_TYPE (base_addr  + 0x0C ))
6484 +#define IRQ_TLEVEL(base_addr)    (INT_CTRL_TYPE (base_addr  + 0x10 ))
6485 +#define IRQ_STATUS(base_addr)   (INT_CTRL_TYPE (base_addr  + 0x14 ))
6486 +#define FIQ_SOURCE(base_addr)   (INT_CTRL_TYPE (base_addr  + 0x20 ))
6487 +#define FIQ_MASK(base_addr)     (INT_CTRL_TYPE (base_addr  + 0x24 ))
6488 +#define FIQ_CLEAR(base_addr)    (INT_CTRL_TYPE (base_addr  + 0x28 ))
6489 +#define FIQ_TMODE(base_addr)    (INT_CTRL_TYPE (base_addr  + 0x2C ))
6490 +#define FIQ_LEVEL(base_addr)    (INT_CTRL_TYPE (base_addr  + 0x30 ))
6491 +#define FIQ_STATUS(base_addr)   (INT_CTRL_TYPE (base_addr  + 0x34 ))
6492 +
6493 +#ifdef CONFIG_SL3516_ASIC
6494 +#define        IRQ_SERIRQ0_OFFSET                      30
6495 +#define        IRQ_PCID_OFFSET                         29
6496 +#define        IRQ_PCIC_OFFSET                         28
6497 +#define        IRQ_PCIB_OFFSET                         27
6498 +#define IRQ_PWR_OFFSET                                 26
6499 +#define IRQ_CIR_OFFSET                                         25
6500 +#define        IRQ_GPIO2_OFFSET                        24
6501 +#define        IRQ_GPIO1_OFFSET                        23
6502 +#define        IRQ_GPIO_OFFSET                         22
6503 +#define        IRQ_SSP_OFFSET                          21
6504 +#define IRQ_LPC_OFFSET                      20
6505 +#define IRQ_LCD_OFFSET                      19
6506 +#define        IRQ_UART_OFFSET                         18
6507 +#define        IRQ_RTC_OFFSET                                  17
6508 +#define        IRQ_TIMER3_OFFSET                       16
6509 +#define        IRQ_TIMER2_OFFSET                       15
6510 +#define        IRQ_TIMER1_OFFSET                       14
6511 +#define IRQ_FLASH_OFFSET                                       12
6512 +#define        IRQ_USB1_OFFSET                         11
6513 +#define IRQ_USB0_OFFSET                                                10
6514 +#define        IRQ_DMA_OFFSET                          9
6515 +#define        IRQ_PCI_OFFSET                          8
6516 +#define        IRQ_IPSEC_OFFSET                        7
6517 +#define        IRQ_RAID_OFFSET                     6
6518 +#define        IRQ_IDE1_OFFSET                         5
6519 +#define        IRQ_IDE0_OFFSET                         4
6520 +#define        IRQ_WATCHDOG_OFFSET                 3
6521 +#define        IRQ_GMAC1_OFFSET                    2
6522 +#define IRQ_GMAC0_OFFSET                                       1
6523 +#define        IRQ_CPU0_IP_IRQ_OFFSET              0
6524 +
6525 +#define        IRQ_SERIRQ0_MASK                        (1<<30)
6526 +#define IRQ_PCID_MASK                                  (1<<29)
6527 +#define IRQ_PCIC_MASK                                  (1<<28)
6528 +#define IRQ_PCIB_MASK                                  (1<<27)
6529 +#define IRQ_PWR_MASK                                   (1<<26)
6530 +#define IRQ_CIR_MASK                                           (1<<25)
6531 +#define        IRQ_GPIO2_MASK                          (1<<24)
6532 +#define        IRQ_GPIO1_MASK                          (1<<23)
6533 +#define        IRQ_GPIO_MASK                       (1<<22)
6534 +#define        IRQ_SSP_MASK                        (1<<21)
6535 +#define IRQ_LPC_MASK                        (1<<20)
6536 +#define IRQ_LCD_MASK                        (1<<19)
6537 +#define        IRQ_UART_MASK                       (1<<18)
6538 +#define        IRQ_RTC_MASK                                (1<<17)
6539 +#define        IRQ_TIMER3_MASK                     (1<<16)
6540 +#define        IRQ_TIMER2_MASK                     (1<<15)
6541 +#define        IRQ_TIMER1_MASK                     (1<<14)
6542 +#define IRQ_FLASH_MASK                                     (1<<12)
6543 +#define        IRQ_USB1_MASK                       (1<<11)
6544 +#define IRQ_USB0_MASK                                      (1<<10)
6545 +#define        IRQ_DMA_MASK                        (1<< 9)
6546 +#define        IRQ_PCI_MASK                        (1<< 8)
6547 +#define        IRQ_IPSEC_MASK                              (1<< 7)
6548 +#define        IRQ_RAID_MASK                       (1<< 6)
6549 +#define        IRQ_IDE1_MASK                       (1<< 5)
6550 +#define        IRQ_IDE0_MASK                       (1<< 4)
6551 +#define        IRQ_WATCHDOG_MASK                   (1<< 3)
6552 +#define        IRQ_GMAC1_MASK                      (1<< 2)
6553 +#define IRQ_GMAC0_MASK                                     (1<< 1)
6554 +#define        IRQ_CPU0_IP_IRQ_MASK                (1<< 0)
6555 +#else
6556 +#define        IRQ_SERIRQ0_OFFSET                      30
6557 +#define        IRQ_PCID_OFFSET                         29
6558 +#define        IRQ_PCIC_OFFSET                         28
6559 +#define        IRQ_PCIB_OFFSET                         27
6560 +#define IRQ_PWR_OFFSET                                 26
6561 +#define IRQ_CIR_OFFSET                                         25
6562 +#define        IRQ_GPIO2_OFFSET                        24
6563 +#define        IRQ_GPIO1_OFFSET                        23
6564 +#define        IRQ_GPIO_OFFSET                         22
6565 +#define        IRQ_SSP_OFFSET                          21
6566 +#define IRQ_LPC_OFFSET                      20
6567 +#define IRQ_LCD_OFFSET                      19
6568 +#define        IRQ_UART_OFFSET                         18
6569 +#define        IRQ_RTC_OFFSET                                  17
6570 +#define        IRQ_TIMER3_OFFSET                       16
6571 +#define        IRQ_TIMER2_OFFSET                       15
6572 +#define        IRQ_TIMER1_OFFSET                       14
6573 +#define IRQ_FLASH_OFFSET                                       12
6574 +#define        IRQ_USB1_OFFSET                         11
6575 +#define IRQ_USB0_OFFSET                                                10
6576 +#define        IRQ_DMA_OFFSET                          9
6577 +#define        IRQ_PCI_OFFSET                          8
6578 +#define        IRQ_IPSEC_OFFSET                        7
6579 +#define        IRQ_RAID_OFFSET                     6
6580 +#define        IRQ_IDE1_OFFSET                         5
6581 +#define        IRQ_IDE0_OFFSET                         4
6582 +#define        IRQ_WATCHDOG_OFFSET                 3
6583 +#define        IRQ_GMAC1_OFFSET                    2
6584 +#define IRQ_GMAC0_OFFSET                                       1
6585 +#define        IRQ_CPU0_IP_IRQ_OFFSET              0
6586 +
6587 +#define        IRQ_SERIRQ0_MASK                        (1<<30)
6588 +#define IRQ_PCID_MASK                                  (1<<29)
6589 +#define IRQ_PCIC_MASK                                  (1<<28)
6590 +#define IRQ_PCIB_MASK                                  (1<<27)
6591 +#define IRQ_PWR_MASK                                   (1<<26)
6592 +#define IRQ_CIR_MASK                                           (1<<25)
6593 +#define        IRQ_GPIO2_MASK                          (1<<24)
6594 +#define        IRQ_GPIO1_MASK                          (1<<23)
6595 +#define        IRQ_GPIO_MASK                       (1<<22)
6596 +#define        IRQ_SSP_MASK                        (1<<21)
6597 +#define IRQ_LPC_MASK                        (1<<20)
6598 +#define IRQ_LCD_MASK                        (1<<19)
6599 +#define        IRQ_UART_MASK                       (1<<18)
6600 +#define        IRQ_RTC_MASK                                (1<<17)
6601 +#define        IRQ_TIMER3_MASK                     (1<<16)
6602 +#define        IRQ_TIMER2_MASK                     (1<<15)
6603 +#define        IRQ_TIMER1_MASK                     (1<<14)
6604 +#define IRQ_FLASH_MASK                                     (1<<12)
6605 +#define        IRQ_USB1_MASK                       (1<<11)
6606 +#define IRQ_USB0_MASK                                      (1<<10)
6607 +#define        IRQ_DMA_MASK                        (1<< 9)
6608 +#define        IRQ_PCI_MASK                        (1<< 8)
6609 +#define        IRQ_IPSEC_MASK                              (1<< 7)
6610 +#define        IRQ_RAID_MASK                       (1<< 6)
6611 +#define        IRQ_IDE1_MASK                       (1<< 5)
6612 +#define        IRQ_IDE0_MASK                       (1<< 4)
6613 +#define        IRQ_WATCHDOG_MASK                   (1<< 3)
6614 +#define        IRQ_GMAC1_MASK                      (1<< 2)
6615 +#define IRQ_GMAC0_MASK                                     (1<< 1)
6616 +#define        IRQ_CPU0_IP_IRQ_MASK                (1<< 0)
6617 +#endif
6618 +
6619 +
6620 +#endif /* __INT_CTRL_H */
6621 +
6622 +
6623 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/io.h
6624 ===================================================================
6625 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
6626 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/io.h    2008-03-13 17:48:24.508798285 +0200
6627 @@ -0,0 +1,50 @@
6628 +/*
6629 + *  linux/include/asm-arm/arch-epxa10db/io.h
6630 + *
6631 + *  Copyright (C) 1999 ARM Limited
6632 + *
6633 + * This program is free software; you can redistribute it and/or modify
6634 + * it under the terms of the GNU General Public License as published by
6635 + * the Free Software Foundation; either version 2 of the License, or
6636 + * (at your option) any later version.
6637 + *
6638 + * This program is distributed in the hope that it will be useful,
6639 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6640 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6641 + * GNU General Public License for more details.
6642 + *
6643 + * You should have received a copy of the GNU General Public License
6644 + * along with this program; if not, write to the Free Software
6645 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6646 + */
6647 +#ifndef __ASM_ARM_ARCH_IO_H
6648 +#define __ASM_ARM_ARCH_IO_H
6649 +
6650 +#define IO_SPACE_LIMIT 0xffffffff
6651 +
6652 +
6653 +/*
6654 + * Generic virtual read/write
6655 + */
6656 +/*
6657 +#define __arch_getw(a)         (*(volatile unsigned short *)(a))
6658 +#define __arch_putw(v,a)       (*(volatile unsigned short *)(a) = (v))
6659 +*/
6660 +/*#define outsw   __arch_writesw
6661 +#define outsl   __arch_writesl
6662 +#define outsb   __arch_writesb
6663 +#define insb    __arch_readsb
6664 +#define insw    __arch_readsw
6665 +#define insl    __arch_readsl*/
6666 +
6667 +#define __io(a)                        (a)
6668 +#define __mem_pci(a)            (a)
6669 +/*
6670 +#define __arch_getw(a)                 (*(volatile unsigned short  *)(a))
6671 +#define __arch_putw(v,a)               (*(volatile unsigned short *)(a) = (v))
6672 +*/
6673 +#define iomem_valid_addr(off,size) (1)
6674 +#define iomem_to_phys(off) (off)
6675 +
6676 +
6677 +#endif
6678 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/ipi.h
6679 ===================================================================
6680 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
6681 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/ipi.h   2008-03-13 17:48:24.508798285 +0200
6682 @@ -0,0 +1,189 @@
6683 +/*
6684 + *  linux/include/asm-arm/arch-sl2312/system.h
6685 + *
6686 + *  Copyright (C) 1999 ARM Limited
6687 + *  Copyright (C) 2000 Deep Blue Solutions Ltd
6688 + *  Copyright (C) 2001 Altera Corporation
6689 + *
6690 + * This program is free software; you can redistribute it and/or modify
6691 + * it under the terms of the GNU General Public License as published by
6692 + * the Free Software Foundation; either version 2 of the License, or
6693 + * (at your option) any later version.
6694 + *
6695 + * This program is distributed in the hope that it will be useful,
6696 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6697 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6698 + * GNU General Public License for more details.
6699 + *
6700 + * You should have received a copy of the GNU General Public License
6701 + * along with this program; if not, write to the Free Software
6702 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6703 + */
6704 +#ifndef __ASM_ARCH_IPI_H
6705 +#define __ASM_ARCH_IPI_H
6706 +#include <asm/io.h>
6707 +
6708 +//#define spin_lock(x) spin_lock_dt(x)
6709 +//#define spin_unlock(x)       spin_unlock_dt(x)
6710 +
6711 +#define SWAP_OFFSET                                                    0x400000
6712 +#define SWAP_SIZE                                                      0x400000
6713 +
6714 +#define SHARE_MEM_ADDR                                         0x2000000
6715 +#define SHARE_MEM_SIZE                                         1024*1024
6716 +
6717 +
6718 +//--> Add by jason for IPI testing
6719 +// memory layout for maste & slave bin
6720 +#define MASTERTEXT      0x8000
6721 +#define SLAVETEXT              0x108000
6722 +#define SHARESIZE              0x4000
6723 +#define SHAREADDR              SHARE_MEM_ADDR // starting 8M
6724 +
6725 +// CPU1 reset release
6726 +#define GLOBAL_BASE            IO_ADDRESS(0x40000000)
6727 +#define GLOBAL_SOFTRESET       (GLOBAL_BASE + 0x0C)
6728 +#define CPU1_RESET_BIT_MASK     0x40000000
6729 +
6730 +// IPI , need to redefine the folliwing,  bug
6731 +#define CPU0_STATUS                    (GLOBAL_BASE + 0x0038)
6732 +#define CPU1_STATUS                    (GLOBAL_BASE + 0x003C)
6733 +#define CPU_IPI_BIT_MASK    0x80000000
6734 +
6735 +/* Your basic SMP spinlocks, allowing only a single CPU anywhere
6736 +*/
6737 +typedef struct {
6738 +       volatile unsigned int lock;
6739 +} spinlock_dt;
6740 +
6741 +
6742 +#define         MASTER_BIT      0x01
6743 +#define         SLAVE_BIT       0x02
6744 +#define         HEART_BIT       0x04
6745 +#define         IPI0_IRQ_BIT    0x08
6746 +#define         IPI0_FIQ_BIT    0x10
6747 +#define         IPI1_IRQ_BIT    0x20
6748 +#define         IPI1_FIQ_BIT    0x40
6749 +
6750 +#define IRQ     0
6751 +#define FIQ     1
6752 +#define DONE    0xff
6753 +
6754 +#define         CPU0            0x0
6755 +#define         CPU1            0x1
6756 +
6757 +#define         MAXCHAR         128*1024
6758 +typedef struct  {
6759 +       int flag;
6760 +       int uart_flag;
6761 +       int cnt;
6762 +       spinlock_dt lk;
6763 +       char message[MAXCHAR];
6764 +}s_mailbox;
6765 +
6766 +// JScale proj definition
6767 +typedef struct {
6768 +       u16             type;                           // message Type
6769 +       u16             length;                         // message length, including message header
6770 +} IPC_MSG_HDR_T;
6771 +
6772 +typedef struct{
6773 +       IPC_MSG_HDR_T   hdr;
6774 +       u32                             input_location;
6775 +       u32                             input_size;
6776 +       u32                             output_location;
6777 +       u16                     ScaledImageWidth;
6778 +       u16                     ScaledImageHeight;
6779 +       u8                      ScaledImageQuality;
6780 +       u8                      MaintainResultionRatio;
6781 +       u8                      TwoStepScaling;
6782 +       u8                      InputFormat;
6783 +       u8                              verbose;
6784 +       u8                              reserved[3];
6785 +} JSCALE_REQ_T;
6786 +
6787 +typedef struct{
6788 +       IPC_MSG_HDR_T   hdr;
6789 +       u32                             status;
6790 +       u32                             code;
6791 +       u32                             output_size;
6792 +} JSCALE_RSP_T;
6793 +
6794 +#define IPC_JSCALE_REQ_MSG                     0       // JScale request from CPU-0 to CPU-1
6795 +#define IPC_JSCALE_RSP_MSG                     1       // JScale response from CPU-1 to CPU-0
6796 +
6797 +enum {
6798 +       JSCALE_STATUS_OK = 0,
6799 +       JSCALE_UNKNOWN_MSG_TYPE,
6800 +       JSCALE_FAILED_FILE_SIZE,
6801 +       JSCALE_FAILED_MALLOC,
6802 +       JSCALE_FAILED_FORMAT,
6803 +       JSCALE_DECODE_ERROR,
6804 +       JSCALE_BUSY,
6805 +};
6806 +// <-- JScale
6807 +
6808 +#define GEMINI_IPI_IOCTL_BASE  'Z'
6809 +#define GEMINI_IPI_JSCALE_REQ          _IOW (GEMINI_IPI_IOCTL_BASE,0,JSCALE_REQ_T)
6810 +#define GEMINI_IPI_JSCALE_STAT         _IOR (GEMINI_IPI_IOCTL_BASE,1,JSCALE_RSP_T)
6811 +
6812 +
6813 +/*
6814 +* Simple spin lock operations.
6815 +*
6816 +*/
6817 +
6818 +#define spin_is_locked_dt(x)((x)->lock != 0)
6819 +
6820 +static inline int test_and_set_dt(spinlock_dt *lock)
6821 +{
6822 +unsigned long tmp;
6823 +__asm__ __volatile__(
6824 +"swp     %0, %2, [%1]\n"
6825 +: "=&r" (tmp)
6826 +: "r" (&lock->lock), "r" (1)
6827 +: "cc", "memory");
6828 +
6829 +return tmp;
6830 +}
6831 +
6832 +static inline void spin_lock_dt(spinlock_dt *lock)
6833 +{
6834 +
6835 +unsigned long tmp;
6836 +__asm__ __volatile__(
6837 +"1:     ldr   %0, [%1]\n"
6838 +"teq     %0, #0\n"
6839 +"swpeq   %0, %2, [%1]\n"
6840 +"       teqeq   %0, #0\n"
6841 +"       bne     1b"
6842 +       : "=&r" (tmp)
6843 +       : "r" (&lock->lock), "r" (1)
6844 +       : "cc", "memory");
6845 +}
6846 +
6847 +static inline void spin_unlock_dt(spinlock_dt *lock)
6848 +{
6849 +       __asm__ __volatile__(
6850 +"       str     %1, [%0]"
6851 +       :
6852 +       : "r" (&lock->lock), "r" (0)
6853 +       : "cc", "memory");
6854 +}
6855 +
6856 +static inline int getcpuid(void)
6857 +{
6858 +       int cpuid;
6859 +
6860 +      __asm__(
6861 +"mrc p8, 0, r0, c0, c0, 0\n"
6862 +"mov %0, r0"
6863 +       :"=r"(cpuid)
6864 +       :
6865 +       :"r0");
6866 +       return (cpuid & 0x07);
6867 +}
6868 +
6869 +
6870 +
6871 +#endif
6872 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/irq.h
6873 ===================================================================
6874 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
6875 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/irq.h   2008-03-13 17:48:24.508798285 +0200
6876 @@ -0,0 +1,23 @@
6877 +/*
6878 + *  linux/include/asm-arm/arch-sl2312/irq.h
6879 + *
6880 + *  Copyright (C) 1999 ARM Limited
6881 + *
6882 + * This program is free software; you can redistribute it and/or modify
6883 + * it under the terms of the GNU General Public License as published by
6884 + * the Free Software Foundation; either version 2 of the License, or
6885 + * (at your option) any later version.
6886 + *
6887 + * This program is distributed in the hope that it will be useful,
6888 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6889 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6890 + * GNU General Public License for more details.
6891 + *
6892 + * You should have received a copy of the GNU General Public License
6893 + * along with this program; if not, write to the Free Software
6894 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6895 + */
6896 +
6897 + // Since we have PCI interrupt which the interrupt line is pseudo
6898 + // we need do some fixup
6899 +int fixup_irq(int irq);
6900 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/irqs.h
6901 ===================================================================
6902 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
6903 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/irqs.h  2008-03-13 17:48:24.508798285 +0200
6904 @@ -0,0 +1,102 @@
6905 +/*
6906 + *  linux/include/asm-arm/arch-camelot/irqs.h
6907 + *
6908 + *  Copyright (C) 2001 Altera Corporation
6909 + *
6910 + * This program is free software; you can redistribute it and/or modify
6911 + * it under the terms of the GNU General Public License as published by
6912 + * the Free Software Foundation; either version 2 of the License, or
6913 + * (at your option) any later version.
6914 + *
6915 + * This program is distributed in the hope that it will be useful,
6916 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6917 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6918 + * GNU General Public License for more details.
6919 + *
6920 + * You should have received a copy of the GNU General Public License
6921 + * along with this program; if not, write to the Free Software
6922 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
6923 + */
6924 +
6925 +/* Use the Excalibur chip definitions */
6926 +#define INT_CTRL_TYPE
6927 +#include "asm/arch/int_ctrl.h"
6928 +
6929 +#ifdef CONFIG_SL3516_ASIC
6930 +#define        IRQ_SERIRQ_MAX                                  31
6931 +#define        IRQ_SERIRQ1                                             31
6932 +#define        IRQ_SERIRQ0                     30
6933 +#define        IRQ_PCID                                29
6934 +#define        IRQ_PCIC                        28
6935 +#define        IRQ_PCIB                                27
6936 +#define IRQ_PWR                                                        26
6937 +#define IRQ_CIR                                                        25
6938 +#define        IRQ_GPIO2                       24
6939 +#define        IRQ_GPIO1                       23
6940 +#define        IRQ_GPIO                                22
6941 +#define        IRQ_SSP                         21
6942 +#define IRQ_LPC                         20
6943 +#define IRQ_LCD                         19
6944 +#define        IRQ_UART                                18
6945 +#define        IRQ_RTC                                 17
6946 +#define        IRQ_TIMER3                      16
6947 +#define        IRQ_TIMER2                      15
6948 +#define        IRQ_TIMER1                      14
6949 +#define IRQ_FLASH                                              12
6950 +#define        IRQ_USB1                        11
6951 +#define IRQ_USB0                                               10
6952 +#define        IRQ_DMA                         9
6953 +#define        IRQ_PCI                                 8
6954 +#define        IRQ_IPSEC                               7
6955 +#define        IRQ_RAID                        6
6956 +#define        IRQ_IDE1                        5
6957 +#define        IRQ_IDE0                                4
6958 +#define        IRQ_WATCHDOG                    3
6959 +#define        IRQ_GMAC1                       2
6960 +#define IRQ_GMAC0                                              1
6961 +#define        IRQ_CPU0_IP_IRQ                 0
6962 +#else
6963 +#define        IRQ_SERIRQ_MAX                                  31
6964 +#define        IRQ_SERIRQ1                                             31
6965 +#define        IRQ_SERIRQ0                     30
6966 +#define        IRQ_PCID                                29
6967 +#define        IRQ_PCIC                        28
6968 +#define        IRQ_PCIB                                27
6969 +#define IRQ_PWR                                                        26
6970 +#define IRQ_CIR                                                        25
6971 +#define        IRQ_GPIO2                       24
6972 +#define        IRQ_GPIO1                       23
6973 +#define        IRQ_GPIO                                22
6974 +#define        IRQ_SSP                         21
6975 +#define IRQ_LPC                         20
6976 +#define IRQ_LCD                         19
6977 +#define        IRQ_UART                                18
6978 +#define        IRQ_RTC                                 17
6979 +#define        IRQ_TIMER3                      16
6980 +#define        IRQ_TIMER2                      15
6981 +#define        IRQ_TIMER1                      14
6982 +#define IRQ_FLASH                                              12
6983 +#define        IRQ_USB1                        11
6984 +#define IRQ_USB0                                               10
6985 +#define        IRQ_DMA                         9
6986 +#define        IRQ_PCI                                 8
6987 +#define        IRQ_IPSEC                               7
6988 +#define        IRQ_RAID                        6
6989 +#define        IRQ_IDE1                        5
6990 +#define        IRQ_IDE0                                4
6991 +#define        IRQ_WATCHDOG                    3
6992 +#define        IRQ_GMAC1                       2
6993 +#define IRQ_GMAC0                                              1
6994 +#endif
6995 +
6996 +#define ARCH_TIMER_IRQ                        IRQ_TIMER2   /* for MV 4.0 */
6997 +
6998 +#define IRQ_PCI_INTA                                  PCI_IRQ_OFFSET + 0
6999 +#define IRQ_PCI_INTB                                  PCI_IRQ_OFFSET + 1
7000 +#define IRQ_PCI_INTC                                  PCI_IRQ_OFFSET + 2
7001 +#define IRQ_PCI_INTD                                  PCI_IRQ_OFFSET + 3
7002 +
7003 +#define NR_IRQS                           (IRQ_PCI_INTD + 4)
7004 +
7005 +
7006 +
7007 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/it8712.h
7008 ===================================================================
7009 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7010 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/it8712.h        2008-03-13 17:48:24.508798285 +0200
7011 @@ -0,0 +1,24 @@
7012 +
7013 +#ifndef __IT8712_H__
7014 +#define __IT8712_H__
7015 +
7016 +#include "asm/arch/sl2312.h"
7017 +
7018 +#define IT8712_IO_BASE                 SL2312_LPC_IO_BASE
7019 +// Device LDN
7020 +#define LDN_SERIAL1                            0x01
7021 +#define LDN_SERIAL2                            0x02
7022 +#define LDN_PARALLEL                   0x03
7023 +#define LDN_KEYBOARD                   0x05
7024 +#define LDN_MOUSE                              0x06
7025 +#define LDN_GPIO                               0x07
7026 +
7027 +#define IT8712_UART1_PORT              0x3F8
7028 +#define IT8712_UART2_PORT              0x2F8
7029 +
7030 +#define IT8712_GPIO_BASE               0x800   // 0x800-0x804 for GPIO set1-set5
7031 +
7032 +void LPCSetConfig(char LdnNumber, char Index, char data);
7033 +char LPCGetConfig(char LdnNumber, char Index);
7034 +
7035 +#endif
7036 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/memory.h
7037 ===================================================================
7038 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7039 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/memory.h        2008-03-13 17:48:24.508798285 +0200
7040 @@ -0,0 +1,38 @@
7041 +/*
7042 + *  linux/include/asm-arm/arch-sl2312/memory.h
7043 + *
7044 + *  Copyright (C) 2001 Altera Corporation
7045 + *
7046 + * This program is free software; you can redistribute it and/or modify
7047 + * it under the terms of the GNU General Public License as published by
7048 + * the Free Software Foundation; either version 2 of the License, or
7049 + * (at your option) any later version.
7050 + *
7051 + * This program is distributed in the hope that it will be useful,
7052 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7053 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7054 + * GNU General Public License for more details.
7055 + *
7056 + * You should have received a copy of the GNU General Public License
7057 + * along with this program; if not, write to the Free Software
7058 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
7059 + */
7060 +#ifndef __ASM_ARCH_MMU_H
7061 +#define __ASM_ARCH_MMU_H
7062 +
7063 +/*
7064 + * Physical DRAM offset.
7065 + */
7066 +#define PHYS_OFFSET    UL(0x00000000)
7067 +
7068 +/*
7069 + * Virtual view <-> DMA view memory address translations
7070 + * virt_to_bus: Used to translate the virtual address to an
7071 + *              address suitable to be passed to set_dma_addr
7072 + * bus_to_virt: Used to convert an address for DMA operations
7073 + *              to an address that the kernel can use.
7074 + */
7075 +#define __virt_to_bus(x)       (x - PAGE_OFFSET + /*SDRAM_BASE*/0)
7076 +#define __bus_to_virt(x)       (x - /*SDRAM_BASE*/0 + PAGE_OFFSET)
7077 +
7078 +#endif
7079 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/param.h
7080 ===================================================================
7081 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7082 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/param.h 2008-03-13 17:48:24.508798285 +0200
7083 @@ -0,0 +1,20 @@
7084 +/*
7085 + *  linux/include/asm-arm/arch-epxa10db/param.h
7086 + *
7087 + *  Copyright (C) 1999 ARM Limited
7088 + *
7089 + * This program is free software; you can redistribute it and/or modify
7090 + * it under the terms of the GNU General Public License as published by
7091 + * the Free Software Foundation; either version 2 of the License, or
7092 + * (at your option) any later version.
7093 + *
7094 + * This program is distributed in the hope that it will be useful,
7095 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
7096 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7097 + * GNU General Public License for more details.
7098 + *
7099 + * You should have received a copy of the GNU General Public License
7100 + * along with this program; if not, write to the Free Software
7101 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
7102 + */
7103 +
7104 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/pci.h
7105 ===================================================================
7106 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7107 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/pci.h   2008-03-13 17:48:24.508798285 +0200
7108 @@ -0,0 +1,18 @@
7109 +
7110 +#ifndef __SL2312_PCI_H__
7111 +#define __SL2312_PCI_H__
7112 +
7113 +#define SL2312_PCI_PMC                         0x40
7114 +#define SL2312_PCI_PMCSR                       0x44
7115 +#define SL2312_PCI_CTRL1                       0x48
7116 +#define SL2312_PCI_CTRL2                       0x4c
7117 +#define SL2312_PCI_MEM1_BASE_SIZE      0x50
7118 +#define SL2312_PCI_MEM2_BASE_SIZE      0x54
7119 +#define SL2312_PCI_MEM3_BASE_SIZE      0x58
7120 +
7121 +
7122 +void sl2312_pci_mask_irq(unsigned int irq);
7123 +void sl2312_pci_unmask_irq(unsigned int irq);
7124 +int sl2312_pci_get_int_src(void);
7125 +
7126 +#endif
7127 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/platform.h
7128 ===================================================================
7129 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7130 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/platform.h      2008-03-13 17:48:24.508798285 +0200
7131 @@ -0,0 +1,7 @@
7132 +#ifndef PLATFORM_H
7133 +#define PLATFORM_H
7134 +#include "sl2312.h"
7135 +
7136 +#define MAXIRQNUM 68
7137 +#endif
7138 +
7139 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/preempt.h
7140 ===================================================================
7141 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7142 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/preempt.h       2008-03-13 17:48:24.508798285 +0200
7143 @@ -0,0 +1,63 @@
7144 +/*
7145 + * include/asm-arm/arch-sl2312/preempt.h
7146 + *
7147 + * Timing support for preempt-stats, kfi, ilatency patches
7148 + *
7149 + * Author: dsingleton <dsingleton@mvista.com>
7150 + *
7151 + * 2001-2004 (c) MontaVista Software, Inc. This file is licensed under
7152 + * the terms of the GNU General Public License version 2. This program
7153 + * is licensed "as is" without any warranty of any kind, whether express
7154 + * or implied.
7155 + */
7156 +
7157 +#ifndef _ASM_ARCH_PREEMT_H
7158 +#define _ASM_ARCH_PREEMT_H
7159 +
7160 +#include <asm/arch/hardware.h>
7161 +#include <asm/arch/sl2312.h>
7162 +
7163 +static inline unsigned long clock_diff(unsigned long start, unsigned long stop)
7164 +{
7165 +        return (start - stop);
7166 +}
7167 +
7168 +static inline unsigned int readclock(void)
7169 +{
7170 +       unsigned int    x;
7171 +
7172 +       x = readl(IO_ADDRESS(SL2312_TIMER2_BASE));
7173 +       return x;
7174 +}
7175 +
7176 +static inline unsigned __ticks_per_usec(void)
7177 +{
7178 +#ifdef CONFIG_SL3516_ASIC
7179 +       unsigned int ahb_clock_rate_base=130;  /* unit = MHz*/
7180 +       unsigned int reg_v=0;
7181 +       unsigned int ticks_usec;
7182 +
7183 +       reg_v = readl(IO_ADDRESS((SL2312_GLOBAL_BASE+4)));
7184 +       reg_v >>=15;
7185 +       ticks_usec = (ahb_clock_rate_base + (reg_v & 0x07)*10)>>2;
7186 +
7187 +#else
7188 +       unsigned int ticks_usec=20;
7189 +#endif
7190 +
7191 +    return ticks_usec;
7192 +}
7193 +
7194 +/*
7195 + * timer 1 runs @ 6Mhz  6 ticks = 1 microsecond
7196 + * and is configed as a count down timer.
7197 + */
7198 +#define TICKS_PER_USEC             __ticks_per_usec()
7199 +#define ARCH_PREDEFINES_TICKS_PER_USEC
7200 +
7201 +#define clock_to_usecs(x)          ((x) / TICKS_PER_USEC)
7202 +
7203 +#define INTERRUPTS_ENABLED(x)   (!(x & PSR_I_BIT))
7204 +
7205 +#endif
7206 +
7207 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/sl2312.h
7208 ===================================================================
7209 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7210 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/sl2312.h        2008-03-13 17:48:24.508798285 +0200
7211 @@ -0,0 +1,254 @@
7212 +#ifndef __sl2312_h
7213 +#define __sl2312_h
7214 +
7215 +/****************************************************************************
7216 + * Copyright  Storlink Corp 2002-2003.  All rights reserved.                *
7217 + *--------------------------------------------------------------------------*
7218 + * Name:board.s                                                             *
7219 + * Description:  SL231x specfic define                                      *
7220 + * Author: Plus Chen                                                        *
7221 + * Version: 0.9 Create
7222 + ****************************************************************************/
7223 +
7224 +/*
7225 +  CPE address map;
7226 +
7227 +               +====================================================
7228 +    0x00000000 | FLASH
7229 +    0x0FFFFFFF |
7230 +               |====================================================
7231 +    0x10000000 | SDRAM
7232 +    0x1FFFFFFF |
7233 +               |====================================================
7234 +    0x20000000 | Global Registers        0x20000000-0x20FFFFFF
7235 +               | EMAC and DMA            0x21000000-0x21FFFFFF
7236 +               | UART Module             0x22000000-0x22FFFFFF
7237 +               | Timer Module            0x23000000-0x23FFFFFF
7238 +               | Interrupt Module        0x24000000-0x24FFFFFF
7239 +               | RTC Module              0x25000000-0x25FFFFFF
7240 +               | LPC Host Controller     0x26000000-0x26FFFFFF
7241 +               | LPC Peripherial IO      0x27000000-0x27FFFFFF
7242 +               | WatchDog Timer          0x28000000-0x28FFFFFF
7243 +    0x2FFFFFFF | Reserved                0x29000000-0x29FFFFFF
7244 +               |=====================================================
7245 +    0x30000000 | PCI IO, Configuration Registers
7246 +    0x3FFFFFFF |
7247 +               |=====================================================
7248 +    0x40000000 | PCI Memory
7249 +    0x4FFFFFFF |
7250 +               |=====================================================
7251 +    0x50000000 | Ethernet MAC and DMA    0x50000000-0x50FFFFFF
7252 +               | Security and DMA        0x51000000-0x51FFFFFF
7253 +               | IDE Channel 0 Register  0x52000000-0x527FFFFF
7254 +               | IDE Channel 1 Register  0x52800000-0x52FFFFFF
7255 +               | USB Register            0x53000000-0x53FFFFFF
7256 +               | Flash Controller        0x54000000-0x54FFFFFF
7257 +               | DRAM Controller         0x55000000-0x55FFFFFF
7258 +    0x5FFFFFFF | Reserved                0x56000000-0x5FFFFFFF
7259 +               |=====================================================
7260 +    0x60000000 | Reserved
7261 +    0x6FFFFFFF |
7262 +               |=====================================================
7263 +    0x70000000 | FLASH shadow Memory
7264 +    0x7FFFFFFF |
7265 +               |=====================================================
7266 +    0x80000000 | Big Endian of memory    0x00000000-0x7FFFFFFF
7267 +    0xFFFFFFFF |
7268 +               +=====================================================
7269 +*/
7270 +
7271 +
7272 +
7273 +/*-------------------------------------------------------------------------------
7274 + Memory Map definitions
7275 +-------------------------------------------------------------------------------- */
7276 +#define TEST           1
7277 +#if 0
7278 +
7279 +static inline int GETCPUID()
7280 +{
7281 +       int cpuid;
7282 +      __asm__(
7283 +"mrc p8, 0, r0, c0, c0, 0\n"
7284 +"mov %0, r0"
7285 +       :"=r"(cpuid)
7286 +       :
7287 +       :"r0");
7288 +       return (cpuid & 0x07);
7289 +}
7290 +#endif
7291 +#define SL2312_SRAM_BASE                0x70000000       //  SRAM base after remap
7292 +#define SL2312_DRAM_BASE                0x00000000       //  DRAM base after remap
7293 +#define SL2312_RAM_BASE                 0x10000000       //  RAM code base before remap
7294 +#define SL2312_FLASH_BASE                  0x30000000
7295 +#define SL2312_ROM_BASE                 0x30000000
7296 +#define SL2312_GLOBAL_BASE              0x40000000
7297 +#define SL2312_WAQTCHDOG_BASE           0x41000000
7298 +#define SL2312_UART_BASE                0x42000000
7299 +#define SL2312_TIMER_BASE               0x43000000
7300 +#define SL2312_LCD_BASE                 0x44000000
7301 +#define SL2312_RTC_BASE                 0x45000000
7302 +#define SL2312_SATA_BASE                0x46000000
7303 +#define SL2312_LPC_HOST_BASE            0x47000000
7304 +#define SL2312_LPC_IO_BASE              0x47800000
7305 +// #define SL2312_INTERRUPT_BASE           0x48000000
7306 +#define SL2312_INTERRUPT0_BASE          0x48000000
7307 +#define SL2312_INTERRUPT1_BASE          0x49000000
7308 +//#define SL2312_INTERRUPT_BASE                ((getcpuid()==0)?SL2312_INTERRUPT0_BASE:SL2312_INTERRUPT1_BASE)
7309 +#define SL2312_INTERRUPT_BASE              0x48000000
7310 +#define SL2312_SSP_CTRL_BASE            0x4A000000
7311 +#define SL2312_POWER_CTRL_BASE          0x4B000000
7312 +#define SL2312_CIR_BASE                 0x4C000000
7313 +#define SL2312_GPIO_BASE                0x4D000000
7314 +#define SL2312_GPIO_BASE1               0x4E000000
7315 +#define SL2312_GPIO_BASE2               0x4F000000
7316 +#define SL2312_PCI_IO_BASE              0x50000000
7317 +#define SL2312_PCI_MEM_BASE             0x58000000
7318 +#ifdef  CONFIG_NET_SL351X
7319 +#define SL2312_TOE_BASE                 0x60000000
7320 +#define SL2312_GMAC0_BASE               0x6000A000
7321 +#define SL2312_GMAC1_BASE               0x6000E000
7322 +#else
7323 +#define SL2312_GMAC0_BASE               0x60000000
7324 +#define SL2312_GMAC1_BASE               0x61000000
7325 +#endif
7326 +#define SL2312_SECURITY_BASE            0x62000000
7327 +#define SL2312_IDE0_BASE                0x63000000
7328 +#define SL2312_IDE1_BASE                       0x63400000
7329 +#define SL2312_RAID_BASE                0x64000000
7330 +#define SL2312_FLASH_CTRL_BASE          0x65000000
7331 +#define SL2312_DRAM_CTRL_BASE           0x66000000
7332 +#define SL2312_GENERAL_DMA_BASE         0x67000000
7333 +#define SL2312_USB_BASE                 0x68000000
7334 +#define SL2312_USB0_BASE                0x68000000
7335 +#define SL2312_USB1_BASE                0x69000000
7336 +#define SL2312_FLASH_SHADOW             0x30000000
7337 +#define SL2312_BIG_ENDIAN_BASE                 0x80000000
7338 +
7339 +#ifdef CONFIG_GEMINI_IPI
7340 +#define CPU_1_MEM_BASE                 0x4000000                               // 64 MB
7341 +#define CPU_1_DATA_OFFSET              0x4000000-0x300000              // Offset 61 MB
7342 +#endif
7343 +
7344 +#define SL2312_TIMER1_BASE              SL2312_TIMER_BASE
7345 +#define SL2312_TIMER2_BASE              (SL2312_TIMER_BASE + 0x10)
7346 +#define SL2312_TIMER3_BASE              (SL2312_TIMER_BASE + 0x20)
7347 +
7348 +#define SL2312_PCI_DMA_MEM1_BASE               0x00000000
7349 +#define SL2312_PCI_DMA_MEM2_BASE               0x00000000
7350 +#define SL2312_PCI_DMA_MEM3_BASE               0x00000000
7351 +#define SL2312_PCI_DMA_MEM1_SIZE               7
7352 +#define SL2312_PCI_DMA_MEM2_SIZE               6
7353 +#define SL2312_PCI_DMA_MEM3_SIZE               6
7354 +
7355 +/*-------------------------------------------------------------------------------
7356 + Global Module
7357 +---------------------------------------------------------------------------------*/
7358 +#define GLOBAL_ID                       0x00
7359 +#define GLOBAL_CHIP_ID                  0x002311
7360 +#define GLOBAL_CHIP_REV                 0xA0
7361 +#define GLOBAL_STATUS                   0x04
7362 +#define GLOBAL_CONTROL                  0x1C
7363 +#define GLOBAL_REMAP_BIT                0x01
7364 +#define GLOBAL_RESET_REG               0x0C
7365 +#define GLOBAL_MISC_REG                                        0x30
7366 +#define PFLASH_SHARE_BIT                               0x02
7367 +
7368 +#define GLOBAL_RESET           (1<<31)
7369 +#define RESET_CPU1                     (1<<30)
7370 +#define RESET_SATA1                    (1<<27)
7371 +#define RESET_SATA0                    (1<<26)
7372 +#define RESET_CIR                      (1<<25)
7373 +#define RESET_EXT_DEV          (1<<24)
7374 +#define RESET_WD                       (1<<23)
7375 +#define RESET_GPIO2                    (1<<22)
7376 +#define RESET_GPIO1                    (1<<21)
7377 +#define RESET_GPIO0                    (1<<20)
7378 +#define RESET_SSP                      (1<<19)
7379 +#define RESET_UART                     (1<<18)
7380 +#define RESET_TIMER                    (1<<17)
7381 +#define RESET_RTC                      (1<<16)
7382 +#define RESET_INT0                     (1<<15)
7383 +#define RESET_INT1                     (1<<14)
7384 +#define RESET_LCD                      (1<<13)
7385 +#define RESET_LPC                      (1<<12)
7386 +#define RESET_APB                      (1<<11)
7387 +#define RESET_DMA                      (1<<10)
7388 +#define RESET_USB1                     (1<<9 )
7389 +#define RESET_USB0                     (1<<8 )
7390 +#define RESET_PCI                      (1<<7 )
7391 +#define RESET_GMAC1                    (1<<6 )
7392 +#define RESET_GMAC0                    (1<<5 )
7393 +#define RESET_IPSEC                    (1<<4 )
7394 +#define RESET_RAID                     (1<<3 )
7395 +#define RESET_IDE                      (1<<2 )
7396 +#define RESET_FLASH                    (1<<1 )
7397 +#define RESET_DRAM                     (1<<0 )
7398 +
7399 +
7400 +
7401 +
7402 +
7403 +
7404 +
7405 +
7406 +/*-------------------------------------------------------------------------------
7407 + DRAM Module
7408 +---------------------------------------------------------------------------------*/
7409 +#define DRAM_SIZE_32M                   0x2000000
7410 +#define DRAM_SIZE_64M                   0x4000000
7411 +#define DRAM_SIZE_128M                  0x8000000
7412 +
7413 +#define DRAM_SIZE                       DRAM_SIZE_128M
7414 +
7415 +#define DRAM_SDRMR                      0x00
7416 +#define SDRMR_DISABLE_DLL               0x80010000
7417 +
7418 +/*------------------------------------------------------------------------------
7419 + Share Pin Flag
7420 +--------------------------------------------------------------------------------*/
7421 +#ifdef CONFIG_SL2312_SHARE_PIN
7422 +#define FLASH_SHARE_BIT                    0
7423 +#define UART_SHARE_BIT                     1
7424 +#define EMAC_SHARE_BIT                     2
7425 +#define IDE_RW_SHARE_BIT                   3
7426 +#define IDE_CMD_SHARE_BIT                  4
7427 +#endif
7428 +/*-------------------------------------------------------------------------------
7429 + System Clock
7430 +---------------------------------------------------------------------------------*/
7431 +
7432 +#ifndef SYS_CLK
7433 +#ifdef CONFIG_SL3516_ASIC
7434 +#define SYS_CLK                         150000000
7435 +#else
7436 +#define SYS_CLK                        20000000
7437 +#endif
7438 +#endif
7439 +
7440 +#define AHB_CLK                        SYS_CLK
7441 +#define MAX_TIMER                      3
7442 +#ifndef APB_CLK
7443 +#ifdef CONFIG_SL3516_ASIC
7444 +#define APB_CLK                        (SYS_CLK / 6)
7445 +#else
7446 +#define APB_CLK                                SYS_CLK
7447 +#endif
7448 +#endif
7449 +
7450 +#ifdef CONFIG_SL3516_ASIC
7451 +#define UART_CLK                        48000000       // 30000000 for GeminiA chip, else 48000000
7452 +#else
7453 +#define UART_CLK                       48000000
7454 +#endif
7455 +
7456 +#define SL2312_BAUD_115200              (UART_CLK / 1843200)
7457 +#define SL2312_BAUD_57600               (UART_CLK / 921600)
7458 +#define SL2312_BAUD_38400                      (UART_CLK / 614400)
7459 +#define SL2312_BAUD_19200               (UART_CLK / 307200)
7460 +#define SL2312_BAUD_14400               (UART_CLK / 230400)
7461 +#define SL2312_BAUD_9600                (UART_CLK / 153600)
7462 +
7463 +#endif
7464 +
7465 +
7466 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/sl2312_ipsec.h
7467 ===================================================================
7468 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
7469 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/sl2312_ipsec.h  2008-03-13 17:48:24.508798285 +0200
7470 @@ -0,0 +1,684 @@
7471 +#ifndef _IPSEC_DIAG_H
7472 +#define _IPSEC_DIAG_H
7473 +
7474 +#include <linux/scatterlist.h>
7475 +
7476 +#define BIG_ENDIAN    0
7477 +
7478 +#define IPSEC_TEST    0
7479 +#define ZERO_COPY     1
7480 +
7481 +#define UINT unsigned int
7482 +#define BYTE unsigned char
7483 +
7484 +/* define cipher algorithm */
7485 +enum CIPHER {
7486 +       DES_ECB_E       =20,
7487 +       TDES_ECB_E      =21,
7488 +       AES_ECB_E       =22,
7489 +       DES_CBC_E       =24,
7490 +       TDES_CBC_E      =25,
7491 +       AES_CBC_E       =26,
7492 +
7493 +       DES_ECB_D       =27,
7494 +       TDES_ECB_D      =28,
7495 +       AES_ECB_D       =29,
7496 +       DES_CBC_D       =31,
7497 +       TDES_CBC_D      =32,
7498 +       AES_CBC_D       =33,
7499 +       A_SHA1      =12,
7500 +       A_HMAC_SHA1 =13,
7501 +       A_MD5       =14,
7502 +       A_HMAC_MD5  =15,
7503 +};
7504 +
7505 +// opMode
7506 +#define CIPHER_ENC    0x1
7507 +#define CIPHER_DEC    0x3
7508 +#define AUTH          0x4
7509 +#define ENC_AUTH      0x5
7510 +#define AUTH_DEC      0x7
7511 +
7512 +// cipherAlgorithm
7513 +#define CBC_DES       0x4
7514 +#define CBC_3DES      0x5
7515 +#define CBC_AES       0x6
7516 +#define ECB_DES       0x0
7517 +#define ECB_3DES      0x1
7518 +#define ECB_AES       0x2
7519 +
7520 +// authAlgorithm
7521 +#define SHA1         0
7522 +#define MD5          1
7523 +#define HMAC_SHA1    2
7524 +#define HMAC_MD5     3
7525 +#define FCS          4
7526 +
7527 +//cipher mode
7528 +#define ECB          0
7529 +#define CBC          1
7530 +
7531 +// authMode
7532 +#define AUTH_APPEND  0
7533 +#define AUTH_CHKVAL  1
7534 +
7535 +/******************************************************/
7536 +/*          the offset of IPSEC DMA register          */
7537 +/******************************************************/
7538 +enum IPSEC_DMA_REGISTER {
7539 +       IPSEC_DMA_DEVICE_ID             = 0xff00,
7540 +       IPSEC_DMA_STATUS                = 0xff04,
7541 +       IPSEC_TXDMA_CTRL                = 0xff08,
7542 +       IPSEC_TXDMA_FIRST_DESC  = 0xff0c,
7543 +       IPSEC_TXDMA_CURR_DESC   = 0xff10,
7544 +       IPSEC_RXDMA_CTRL                = 0xff14,
7545 +       IPSEC_RXDMA_FIRST_DESC  = 0xff18,
7546 +       IPSEC_RXDMA_CURR_DESC   = 0xff1c,
7547 +       IPSEC_TXDMA_BUF_ADDR    = 0xff28,
7548 +       IPSEC_RXDMA_BUF_ADDR    = 0xff38,
7549 +       IPSEC_RXDMA_BUF_SIZE            = 0xff30,
7550 +};
7551 +
7552 +#define IPSEC_STATUS_REG    0x00a8
7553 +#define IPSEC_RAND_NUM_REG  0x00ac
7554 +
7555 +/******************************************************/
7556 +/* the field definition of IPSEC DMA Module Register  */
7557 +/******************************************************/
7558 +typedef union
7559 +{
7560 +       unsigned int bits32;
7561 +       struct bit2_ff00
7562 +       {
7563 +#if (BIG_ENDIAN==1)
7564 +               unsigned int p_wclk             :  4;   /* DMA_APB write clock period */
7565 +               unsigned int p_rclk             :  4;   /* DMA_APB read clock period */
7566 +               unsigned int                            :  8;
7567 +               unsigned int device_id          : 12;
7568 +               unsigned int revision_id        :  4;
7569 +#else
7570 +               unsigned int revision_id        :  4;
7571 +               unsigned int device_id          : 12;
7572 +               unsigned int                            :  8;
7573 +               unsigned int p_rclk             :  4;   /* DMA_APB read clock period */
7574 +               unsigned int p_wclk             :  4;   /* DMA_APB write clock period */
7575 +#endif
7576 +       } bits;
7577 +} IPSEC_DMA_DEVICE_ID_T;
7578 +
7579 +typedef union
7580 +{
7581 +       unsigned int bits32;
7582 +       struct bit2_ff04
7583 +       {
7584 +#if (BIG_ENDIAN==1)
7585 +               unsigned int ts_finish          :  1;   /* finished tx interrupt */
7586 +               unsigned int ts_derr            :  1;   /* AHB Bus Error while tx */
7587 +               unsigned int ts_perr            :  1;   /* Tx Descriptor protocol error */
7588 +               unsigned int ts_eodi            :  1;   /* TxDMA end of descriptor interrupt */
7589 +               unsigned int ts_eofi            :  1;   /* TxDMA end of frame interrupt */
7590 +               unsigned int rs_finish          :  1;   /* finished rx interrupt */
7591 +               unsigned int rs_derr            :  1;   /* AHB Bus Error while rx */
7592 +               unsigned int rs_perr            :  1;   /* Rx Descriptor protocol error */
7593 +               unsigned int rs_eodi            :  1;   /* RxDMA end of descriptor interrupt */
7594 +               unsigned int rs_eofi            :  1;   /* RxDMA end of frame interrupt */
7595 +        unsigned int intr           :  8;   /* Peripheral interrupt */
7596 +               unsigned int dma_reset          :  1;   /* write 1 to this bit will cause DMA HClk domain soft reset */
7597 +               unsigned int peri_reset         :  1;   /* write 1 to this bit will cause DMA PClk domain soft reset */
7598 +               unsigned int                            :  3;
7599 +               unsigned int loop_back          :  1;   /* loopback TxDMA to RxDMA */
7600 +        unsigned int intr_enable    :  8;   /* Peripheral Interrupt Enable */
7601 +#else
7602 +        unsigned int intr_enable    :  8;   /* Peripheral Interrupt Enable */
7603 +               unsigned int loop_back          :  1;   /* loopback TxDMA to RxDMA */
7604 +               unsigned int                            :  3;
7605 +               unsigned int peri_reset         :  1;   /* write 1 to this bit will cause DMA PClk domain soft reset */
7606 +               unsigned int dma_reset          :  1;   /* write 1 to this bit will cause DMA HClk domain soft reset */
7607 +        unsigned int intr           :  8;   /* Peripheral interrupt */
7608 +               unsigned int rs_eofi            :  1;   /* RxDMA end of frame interrupt */
7609 +               unsigned int rs_eodi            :  1;   /* RxDMA end of descriptor interrupt */
7610 +               unsigned int rs_perr            :  1;   /* Rx Descriptor protocol error */
7611 +               unsigned int rs_derr            :  1;   /* AHB Bus Error while rx */
7612 +               unsigned int rs_finish          :  1;   /* finished rx interrupt */
7613 +               unsigned int ts_eofi            :  1;   /* TxDMA end of frame interrupt */
7614 +               unsigned int ts_eodi            :  1;   /* TxDMA end of descriptor interrupt */
7615 +               unsigned int ts_perr            :  1;   /* Tx Descriptor protocol error */
7616 +               unsigned int ts_derr            :  1;   /* AHB Bus Error while tx */
7617 +               unsigned int ts_finish          :  1;   /* finished tx interrupt */
7618 +#endif
7619 +       } bits;
7620 +} IPSEC_DMA_STATUS_T;
7621 +
7622 +typedef union
7623 +{
7624 +       unsigned int bits32;
7625 +       struct bit2_ff08
7626 +       {
7627 +#if (BIG_ENDIAN==1)
7628 +               unsigned int td_start           :  1;   /* Start DMA transfer */
7629 +               unsigned int td_continue        :  1;   /* Continue DMA operation */
7630 +               unsigned int td_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
7631 +               unsigned int                            :  1;
7632 +               unsigned int td_prot            :  4;   /* TxDMA protection control */
7633 +               unsigned int td_burst_size  :  2;       /* TxDMA max burst size for every AHB request */
7634 +               unsigned int td_bus                 :  2;       /* peripheral bus width;0 - 8 bits;1 - 16 bits */
7635 +               unsigned int td_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
7636 +               unsigned int td_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
7637 +               unsigned int td_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
7638 +               unsigned int td_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
7639 +               unsigned int td_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
7640 +               unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
7641 +               unsigned int                            : 14;
7642 +#else
7643 +               unsigned int                            : 14;
7644 +               unsigned int td_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
7645 +               unsigned int td_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
7646 +               unsigned int td_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
7647 +               unsigned int td_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
7648 +               unsigned int td_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
7649 +               unsigned int td_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
7650 +               unsigned int td_bus                 :  2;       /* peripheral bus width;0 - 8 bits;1 - 16 bits */
7651 +               unsigned int td_burst_size  :  2;       /* TxDMA max burst size for every AHB request */
7652 +               unsigned int td_prot            :  4;   /* TxDMA protection control */
7653 +               unsigned int                            :  1;
7654 +               unsigned int td_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
7655 +               unsigned int td_continue        :  1;   /* Continue DMA operation */
7656 +               unsigned int td_start           :  1;   /* Start DMA transfer */
7657 +#endif
7658 +       } bits;
7659 +} IPSEC_TXDMA_CTRL_T;
7660 +
7661 +typedef union
7662 +{
7663 +       unsigned int bits32;
7664 +       struct bit2_ff0c
7665 +       {
7666 +#if (BIG_ENDIAN==1)
7667 +               unsigned int td_first_des_ptr   : 28;/* first descriptor address */
7668 +               unsigned int td_busy                    :  1;/* 1-TxDMA busy; 0-TxDMA idle */
7669 +               unsigned int                                    :  3;
7670 +#else
7671 +               unsigned int                                    :  3;
7672 +               unsigned int td_busy                    :  1;/* 1-TxDMA busy; 0-TxDMA idle */
7673 +               unsigned int td_first_des_ptr   : 28;/* first descriptor address */
7674 +#endif
7675 +       } bits;
7676 +} IPSEC_TXDMA_FIRST_DESC_T;
7677 +
7678 +typedef union
7679 +{
7680 +       unsigned int bits32;
7681 +       struct bit2_ff10
7682 +       {
7683 +#if (BIG_ENDIAN==1)
7684 +               unsigned int ndar                       : 28;   /* next descriptor address */
7685 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
7686 +               unsigned int dec                        :  1;   /* AHB bus address increment(0)/decrement(1) */
7687 +               unsigned int sof_eof            :  2;
7688 +#else
7689 +               unsigned int sof_eof            :  2;
7690 +               unsigned int dec                        :  1;   /* AHB bus address increment(0)/decrement(1) */
7691 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
7692 +               unsigned int ndar                       : 28;   /* next descriptor address */
7693 +#endif
7694 +       } bits;
7695 +} IPSEC_TXDMA_CURR_DESC_T;
7696 +
7697 +
7698 +typedef union
7699 +{
7700 +       unsigned int bits32;
7701 +       struct bit2_ff14
7702 +       {
7703 +#if (BIG_ENDIAN==1)
7704 +               unsigned int rd_start           :  1;   /* Start DMA transfer */
7705 +               unsigned int rd_continue        :  1;   /* Continue DMA operation */
7706 +               unsigned int rd_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
7707 +               unsigned int                            :  1;
7708 +               unsigned int rd_prot            :  4;   /* DMA protection control */
7709 +               unsigned int rd_burst_size  :  2;       /* DMA max burst size for every AHB request */
7710 +               unsigned int rd_bus                 :  2;       /* peripheral bus width;0 - 8 bits;1 - 16 bits */
7711 +               unsigned int rd_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
7712 +               unsigned int rd_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
7713 +               unsigned int rd_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
7714 +               unsigned int rd_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
7715 +               unsigned int rd_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
7716 +               unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
7717 +               unsigned int                            : 14;
7718 +#else
7719 +               unsigned int                            : 14;
7720 +               unsigned int rd_eof_en      :  1;   /* End of frame interrupt Enable;1-enable;0-mask */
7721 +               unsigned int rd_eod_en          :  1;   /* End of Descriptor interrupt Enable;1-enable;0-mask */
7722 +               unsigned int rd_perr_en         :  1;   /* Protocol Failure Interrupt Enable;1-enable;0-mask */
7723 +               unsigned int rd_fail_en         :  1;   /* DMA Fail Interrupt Enable;1-enable;0-mask */
7724 +               unsigned int rd_finish_en   :  1;       /* DMA Finish Event Interrupt Enable;1-enable;0-mask */
7725 +               unsigned int rd_endian          :  1;   /* AHB Endian. 0-little endian; 1-big endian */
7726 +               unsigned int rd_bus                 :  2;       /* peripheral bus width;0 - 8 bits;1 - 16 bits */
7727 +               unsigned int rd_burst_size  :  2;       /* DMA max burst size for every AHB request */
7728 +               unsigned int rd_prot            :  4;   /* DMA protection control */
7729 +               unsigned int                            :  1;
7730 +               unsigned int rd_chain_mode      :  1;   /* Descriptor Chain Mode;1-Descriptor Chain mode, 0-Direct DMA mode*/
7731 +               unsigned int rd_continue        :  1;   /* Continue DMA operation */
7732 +               unsigned int rd_start           :  1;   /* Start DMA transfer */
7733 +#endif
7734 +       } bits;
7735 +} IPSEC_RXDMA_CTRL_T;
7736 +
7737 +typedef union
7738 +{
7739 +       unsigned int bits32;
7740 +       struct bit2_ff18
7741 +       {
7742 +#if (BIG_ENDIAN==1)
7743 +               unsigned int rd_first_des_ptr   : 28;/* first descriptor address */
7744 +               unsigned int rd_busy                    :  1;/* 1-RxDMA busy; 0-RxDMA idle */
7745 +               unsigned int                                    :  3;
7746 +#else
7747 +               unsigned int                                    :  3;
7748 +               unsigned int rd_busy                    :  1;/* 1-RxDMA busy; 0-RxDMA idle */
7749 +               unsigned int rd_first_des_ptr   : 28;/* first descriptor address */
7750 +#endif
7751 +       } bits;
7752 +} IPSEC_RXDMA_FIRST_DESC_T;
7753 +
7754 +typedef union
7755 +{
7756 +       unsigned int bits32;
7757 +       struct bit2_ff1c
7758 +       {
7759 +#if (BIG_ENDIAN==1)
7760 +               unsigned int ndar                       : 28;   /* next descriptor address */
7761 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
7762 +               unsigned int dec                        :  1;   /* AHB bus address increment(0)/decrement(1) */
7763 +               unsigned int sof_eof            :  2;
7764 +#else
7765 +               unsigned int sof_eof            :  2;
7766 +               unsigned int dec                        :  1;   /* AHB bus address increment(0)/decrement(1) */
7767 +               unsigned int eofie                      :  1;   /* end of frame interrupt enable */
7768 +               unsigned int ndar                       : 28;   /* next descriptor address */
7769 +#endif
7770 +       } bits;
7771 +} IPSEC_RXDMA_CURR_DESC_T;
7772 +
7773 +
7774 +
7775 +/******************************************************/
7776 +/*    the field definition of IPSEC module Register   */
7777 +/******************************************************/
7778 +typedef union
7779 +{
7780 +       unsigned int id;
7781 +       struct bit_0000
7782 +       {
7783 +#if (BIG_ENDIAN==1)
7784 +               unsigned int device_id          : 28;
7785 +               unsigned int revision_id        :  4;
7786 +#else
7787 +               unsigned int revision_id        :  4;
7788 +               unsigned int device_id          : 28;
7789 +#endif
7790 +       } bits;
7791 +} IPSEC_ID_T;
7792 +
7793 +typedef union
7794 +{
7795 +    unsigned int control;
7796 +    struct bit_0004
7797 +    {
7798 +#if (BIG_ENDIAN==1)
7799 +        unsigned int op_mode            :  4; /* Operation Mode for the IPSec Module */
7800 +        unsigned int                    :  1;
7801 +        unsigned int cipher_algorithm   :  3;
7802 +        unsigned int aesnk              :  4; /* AES Key Size */
7803 +        unsigned int mix_key_sel        :  1; /* 0:use rCipherKey0-3  1:use Key Mixer */
7804 +        unsigned int                    :  2;
7805 +        unsigned int fcs_stream_copy    :  1; /* enable authentication stream copy */
7806 +        unsigned int auth_mode          :  1; /* 0-Append or 1-Check Authentication Result */
7807 +        unsigned int auth_algorithm     :  3;
7808 +        unsigned int                    :  1;
7809 +        unsigned int auth_check_len     :  3; /* Number of 32-bit words to be check or appended */
7810 +                                              /* by the authentication module */
7811 +        unsigned int process_id         :  8; /* Used to identify process.This number will be */
7812 +                                              /* copied to the descriptor status of received packet*/
7813 +#else
7814 +        unsigned int process_id         :  8; /* Used to identify process.This number will be */
7815 +                                              /* copied to the descriptor status of received packet*/
7816 +        unsigned int auth_check_len     :  3; /* Number of 32-bit words to be check or appended */
7817 +                                              /* by the authentication module */
7818 +        unsigned int                    :  1;
7819 +        unsigned int auth_algorithm     :  3;
7820 +        unsigned int auth_mode          :  1; /* 0-Append or 1-Check Authentication Result */
7821 +        unsigned int fcs_stream_copy    :  1; /* enable authentication stream copy */
7822 +        unsigned int                    :  2;
7823 +        unsigned int mix_key_sel        :  1; /* 0:use rCipherKey0-3  1:use Key Mixer */
7824 +        unsigned int aesnk              :  4; /* AES Key Size */
7825 +        unsigned int cipher_algorithm   :  3;
7826 +        unsigned int                    :  1;
7827 +        unsigned int op_mode            :  4; /* Operation Mode for the IPSec Module */
7828 +#endif
7829 +    } bits;
7830 +} IPSEC_CONTROL_T;
7831 +
7832 +
7833 +typedef union
7834 +{
7835 +    unsigned int cipher_packet;
7836 +    struct bit_0008
7837 +    {
7838 +#if (BIG_ENDIAN==1)
7839 +        unsigned int cipher_header_len    : 16; /* The header length to be skipped by the cipher */
7840 +        unsigned int cipher_algorithm_len : 16; /* The length of message body to be encrypted/decrypted */
7841 +#else
7842 +        unsigned int cipher_algorithm_len : 16; /* The length of message body to be encrypted/decrypted */
7843 +        unsigned int cipher_header_len    : 16; /* The header length to be skipped by the cipher */
7844 +#endif
7845 +    } bits;
7846 +} IPSEC_CIPHER_PACKET_T;
7847 +
7848 +typedef union
7849 +{
7850 +    unsigned int auth_packet;
7851 +    struct bit_000c
7852 +    {
7853 +#if (BIG_ENDIAN==1)
7854 +        unsigned int auth_header_len    : 16; /* The header length that is to be skipped by the authenticator */
7855 +        unsigned int auth_algorithm_len : 16; /* The length of message body that is to be authenticated */
7856 +#else
7857 +        unsigned int auth_algorithm_len : 16; /* The length of message body that is to be authenticated */
7858 +        unsigned int auth_header_len    : 16; /* The header length that is to be skipped by the authenticator */
7859 +#endif
7860 +    } bits;
7861 +} IPSEC_AUTH_PACKET_T;
7862 +
7863 +typedef union
7864 +{
7865 +    unsigned int status;
7866 +    struct bit_00a8
7867 +    {
7868 +#if (BIG_ENDIAN==1)
7869 +        unsigned int auth_cmp_rslt  :  1; /* Authentication Compare result */
7870 +        unsigned int wep_crc_ok     :  1; /* WEP ICV compare result */
7871 +        unsigned int tkip_mic_ok    :  1; /* TKIP Mic compare result */
7872 +        unsigned int ccm_mic_ok     :  1; /* CCM Mic compare result */
7873 +        unsigned int                : 16;
7874 +        unsigned int parser_err_code:  4; /* Authentication Compare result */
7875 +        unsigned int auth_err_code  :  4; /* Authentication module error code */
7876 +        unsigned int cipher_err_code:  4; /* Cipher module erroe code */
7877 +#else
7878 +        unsigned int cipher_err_code:  4; /* Cipher module erroe code */
7879 +        unsigned int auth_err_code  :  4; /* Authentication module error code */
7880 +        unsigned int parser_err_code:  4; /* Authentication Compare result */
7881 +        unsigned int                : 16;
7882 +        unsigned int ccm_mic_ok     :  1; /* CCM Mic compare result */
7883 +        unsigned int tkip_mic_ok    :  1; /* TKIP Mic compare result */
7884 +        unsigned int wep_crc_ok     :  1; /* WEP ICV compare result */
7885 +        unsigned int auth_cmp_rslt  :  1; /* Authentication Compare result */
7886 +#endif
7887 +    } bits;
7888 +} IPSEC_STATUS_T;
7889 +
7890 +
7891 +
7892 +/************************************************************************/
7893 +/*              IPSec Descriptor Format                                 */
7894 +/************************************************************************/
7895 +typedef struct descriptor_t
7896 +{
7897 +       union frame_control_t
7898 +       {
7899 +               unsigned int bits32;
7900 +               struct bits_0000
7901 +               {
7902 +#if (BIG_ENDIAN==1)
7903 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
7904 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
7905 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
7906 +                       unsigned int            : 1;    /* authentication compare result */
7907 +                       unsigned int            : 6;    /* checksum[15:8] */
7908 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
7909 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
7910 +#else
7911 +                       unsigned int buffer_size:16;    /* transfer buffer size associated with current description*/
7912 +                       unsigned int desc_count : 6;    /* number of descriptors used for the current frame */
7913 +                       unsigned int            : 6;    /* checksum[15:8] */
7914 +                       unsigned int            : 1;    /* authentication compare result */
7915 +                       unsigned int perr               : 1;    /* protocol error during processing this descriptor */
7916 +                       unsigned int derr               : 1;    /* data error during processing this descriptor */
7917 +                       unsigned int own                : 1;    /* owner bit. 0-CPU, 1-DMA */
7918 +#endif
7919 +               } bits;
7920 +       } frame_ctrl;
7921 +
7922 +       union flag_status_t
7923 +       {
7924 +               unsigned int bits32;
7925 +               struct bits_0004
7926 +               {
7927 +#if (BIG_ENDIAN==1)
7928 +//            unsigned int checksum   : 8; /* checksum[7:0] */
7929 +                       unsigned int            : 4;
7930 +                       unsigned int auth_result: 1;
7931 +                       unsigned int wep_crc_ok : 1;
7932 +                       unsigned int tkip_mic_ok: 1;
7933 +                       unsigned int ccmp_mic_ok: 1;
7934 +                       unsigned int process_id : 8;
7935 +                       unsigned int frame_count:16;
7936 +#else
7937 +                       unsigned int frame_count:16;
7938 +                       unsigned int process_id : 8;
7939 +                       unsigned int ccmp_mic_ok: 1;
7940 +                       unsigned int tkip_mic_ok: 1;
7941 +                       unsigned int wep_crc_ok : 1;
7942 +                       unsigned int auth_result: 1;
7943 +                       unsigned int            : 4;
7944 +//            unsigned int checksum   : 8; /* checksum[7:0] */
7945 +#endif
7946 +               } bits_rx_status;
7947 +
7948 +               struct bits_0005
7949 +               {
7950 +#if (BIG_ENDIAN==1)
7951 +            unsigned int            : 8;
7952 +                       unsigned int process_id : 8;
7953 +                       unsigned int frame_count:16;
7954 +#else
7955 +                       unsigned int frame_count:16;
7956 +                       unsigned int process_id : 8;
7957 +            unsigned int            : 8;
7958 +#endif
7959 +               } bits_tx_status;
7960 +
7961 +               struct bits_0006
7962 +               {
7963 +#if (BIG_ENDIAN==1)
7964 +                       unsigned int            :22;
7965 +                       unsigned int tqflag     :10;
7966 +#else
7967 +                       unsigned int tqflag     :10;
7968 +                       unsigned int            :22;
7969 +#endif
7970 +               } bits_tx_flag;
7971 +       } flag_status;
7972 +
7973 +       unsigned int buf_adr;   /* data buffer address */
7974 +
7975 +       union next_desc_t
7976 +       {
7977 +               unsigned int next_descriptor;
7978 +               struct bits_000c
7979 +               {
7980 +#if (BIG_ENDIAN==1)
7981 +                       unsigned int ndar               :28;    /* next descriptor address */
7982 +                       unsigned int eofie              : 1;    /* end of frame interrupt enable */
7983 +                       unsigned int dec                : 1;    /* AHB bus address. 0-increment; 1-decrement */
7984 +                       unsigned int sof_eof    : 2;    /* 00-the linking descriptor   01-the last descriptor of a frame*/
7985 +                                                       /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
7986 +#else
7987 +                       unsigned int sof_eof    : 2;    /* 00-the linking descriptor   01-the last descriptor of a frame*/
7988 +                                                       /* 10-the first descriptor of a frame    11-only one descriptor for a frame*/
7989 +                       unsigned int dec                : 1;    /* AHB bus address. 0-increment; 1-decrement */
7990 +                       unsigned int eofie              : 1;    /* end of frame interrupt enable */
7991 +                       unsigned int ndar               :28;    /* next descriptor address */
7992 +#endif
7993 +               } bits;
7994 +       } next_desc;
7995 +} IPSEC_DESCRIPTOR_T;
7996 +
7997 +
7998 +typedef struct IPSEC_S
7999 +{
8000 +    unsigned char       *tx_bufs;
8001 +    unsigned char       *rx_bufs;
8002 +       IPSEC_DESCRIPTOR_T      *tx_desc;           /* point to virtual TX descriptor address*/
8003 +       IPSEC_DESCRIPTOR_T      *rx_desc;           /* point to virtual RX descriptor address*/
8004 +       IPSEC_DESCRIPTOR_T      *tx_cur_desc;   /* point to current TX descriptor */
8005 +       IPSEC_DESCRIPTOR_T      *rx_cur_desc;   /* point to current RX descriptor */
8006 +       IPSEC_DESCRIPTOR_T  *tx_finished_desc;
8007 +       IPSEC_DESCRIPTOR_T  *rx_finished_desc;
8008 +       dma_addr_t          rx_desc_dma;        /* physical RX descriptor address */
8009 +       dma_addr_t          tx_desc_dma;    /* physical TX descriptor address */
8010 +       dma_addr_t          rx_bufs_dma;    /* physical RX descriptor address */
8011 +       dma_addr_t          tx_bufs_dma;    /* physical TX descriptor address */
8012 +} IPSEC_T;
8013 +
8014 +
8015 +/*=====================================================================================================*/
8016 +/*  Data Structure of IPSEC Control Packet  */
8017 +/*=====================================================================================================*/
8018 +typedef struct IPSEC_ECB_AUTH_S
8019 +{
8020 +    IPSEC_CONTROL_T         control; /* control parameter */
8021 +    IPSEC_CIPHER_PACKET_T   cipher; /* cipher packet parameter */
8022 +    IPSEC_AUTH_PACKET_T     auth;   /* authentication packet parameter */
8023 +    unsigned char           cipher_key[8*4];
8024 +    unsigned char           auth_check_val[5*4];
8025 +} IPSEC_ECB_AUTH_T;
8026 +
8027 +typedef struct IPSEC_CBC_AUTH_S
8028 +{
8029 +    IPSEC_CONTROL_T         control; /* control parameter */
8030 +    IPSEC_CIPHER_PACKET_T   cipher; /* cipher packet parameter */
8031 +    IPSEC_AUTH_PACKET_T     auth;   /* authentication packet parameter */
8032 +    unsigned char           cipher_iv[4*4];
8033 +    unsigned char           cipher_key[8*4];
8034 +    unsigned char           auth_check_val[5*4];
8035 +} IPSEC_CBC_AUTH_T;
8036 +
8037 +typedef struct IPSEC_ECB_HMAC_AUTH_S
8038 +{
8039 +    IPSEC_CONTROL_T         control; /* control parameter */
8040 +    IPSEC_CIPHER_PACKET_T   cipher; /* cipher packet parameter */
8041 +    IPSEC_AUTH_PACKET_T     auth;   /* authentication packet parameter */
8042 +    unsigned char           cipher_key[8*4];
8043 +    unsigned char           auth_key[16*4];
8044 +    unsigned char           auth_check_val[5*4];
8045 +} IPSEC_ECB_AUTH_HMAC_T;
8046 +
8047 +typedef struct IPSEC_CBC_HMAC_AUTH_S
8048 +{
8049 +    IPSEC_CONTROL_T         control; /* control parameter */
8050 +    IPSEC_CIPHER_PACKET_T   cipher; /* cipher packet parameter */
8051 +    IPSEC_AUTH_PACKET_T     auth;   /* authentication packet parameter */
8052 +    unsigned char           cipher_iv[4*4];
8053 +    unsigned char           cipher_key[8*4];
8054 +    unsigned char           auth_key[16*4];
8055 +    unsigned char           auth_check_val[5*4];
8056 +} IPSEC_CBC_AUTH_HMAC_T;
8057 +
8058 +typedef struct IPSEC_HMAC_AUTH_S
8059 +{
8060 +    IPSEC_CONTROL_T         control; /* control parameter */
8061 +    IPSEC_AUTH_PACKET_T     auth;   /* authentication packet parameter */
8062 +    unsigned char           auth_key[16*4];
8063 +    unsigned char           auth_check_val[5*4];
8064 +} IPSEC_HMAC_AUTH_T;
8065 +
8066 +typedef union
8067 +{
8068 +    unsigned char auth_pkt[28];
8069 +
8070 +    struct IPSEC_AUTH_S
8071 +    {
8072 +        IPSEC_CONTROL_T         control; /* control parameter(4-byte) */
8073 +        IPSEC_AUTH_PACKET_T     auth;   /* authentication packet parameter(4-byte) */
8074 +        unsigned char           auth_check_val[5*4];
8075 +    } var;
8076 +} IPSEC_AUTH_T;
8077 +
8078 +typedef struct IPSEC_CIPHER_CBC_S
8079 +{
8080 +    IPSEC_CONTROL_T         control; /* control parameter */
8081 +    IPSEC_CIPHER_PACKET_T   cipher; /* cipher packet parameter */
8082 +    unsigned char           cipher_iv[4*4];
8083 +    unsigned char           cipher_key[8*4];
8084 +} IPSEC_CIPHER_CBC_T;
8085 +
8086 +typedef struct IPSEC_CIPHER_ECB_S
8087 +{
8088 +    IPSEC_CONTROL_T         control; /* control parameter */
8089 +    IPSEC_CIPHER_PACKET_T   cipher; /* cipher packet parameter */
8090 +    unsigned char           cipher_key[8*4];
8091 +} IPSEC_CIPHER_ECB_T;
8092 +
8093 +
8094 +/****************************************************************************
8095 + *                          Structure Definition                            *
8096 + ****************************************************************************/
8097 +struct IPSEC_PACKET_S
8098 +{
8099 +    unsigned int    op_mode;            /* CIPHER_ENC(1),CIPHER_DEC(3),AUTH(4),ENC_AUTH(5),AUTH_DEC(7) */
8100 +    unsigned int    cipher_algorithm;   /* ECB_DES(0),ECB_3DES(1),ECB_AES(2),CBC_DES(4),CBC_3DES(5),CBC_AES(6) */
8101 +    unsigned int    auth_algorithm;     /* SHA1(0),MD5(1),HMAC_SHA1(2),HMAC_MD5(3),FCS(4) */
8102 +    unsigned int    auth_result_mode;   /* AUTH_APPEND(0),AUTH_CHKVAL(1) */
8103 +    unsigned int    process_id;         /* Used to identify the process */
8104 +    unsigned int    auth_header_len;    /* Header length to be skipped by the authenticator */
8105 +    unsigned int    auth_algorithm_len; /* Length of message body that is to be authenticated */
8106 +    unsigned int    cipher_header_len;  /* Header length to be skipped by the cipher */
8107 +    unsigned int    cipher_algorithm_len;   /* Length of message body to be encrypted or decrypted */
8108 +    unsigned char   iv[16];             /* Initial vector used for DES,3DES,AES */
8109 +    unsigned int    iv_size;            /* Initial vector size */
8110 +    unsigned char   auth_key[64];       /* authentication key */
8111 +    unsigned int    auth_key_size;      /* authentication key size */
8112 +    unsigned char   cipher_key[32];     /* cipher key */
8113 +    unsigned int    cipher_key_size;    /* cipher key size */
8114 +    struct scatterlist *in_packet;         /* input_packet buffer pointer */
8115 +    //unsigned char            *in_packet;         /* input_packet buffer pointer */
8116 +    unsigned int    pkt_len;            /* input total packet length */
8117 +    unsigned char   auth_checkval[20];  /* Authentication check value/FCS check value */
8118 +    struct IPSEC_PACKET_S *next,*prev;        /* pointer to next/previous operation to perform on buffer */
8119 +    void (*callback)(struct IPSEC_PACKET_S *); /* function to call when done authentication/cipher */
8120 +    unsigned char   *out_packet;        /* output_packet buffer pointer */
8121 +    //struct scatterlist *out_packet;        /* output_packet buffer pointer */
8122 +    unsigned int    out_pkt_len;        /* output total packet length */
8123 +    unsigned int    auth_cmp_result;    /* authentication compare result */
8124 +    unsigned int    checksum;           /* checksum value */
8125 +    unsigned int    status;             /* ipsec return status. 0:success, others:fail */
8126 +#if (IPSEC_TEST == 1)
8127 +    unsigned char    *sw_packet;         /* for test only */
8128 +    unsigned int    sw_pkt_len;         /* for test only */
8129 +#endif
8130 +} ;
8131 +
8132 +/*****************************************************************************
8133 + * Function    : ipsec_crypto_hw_process
8134 + * Description : This function processes H/W authentication and cipher.
8135 + *       Input : op_info - the authentication and cipher information for IPSec module.
8136 + *      Output : none.
8137 + *      Return : 0 - success, others - failure.
8138 + *****************************************************************************/
8139 +int ipsec_crypto_hw_process(struct IPSEC_PACKET_S  *op_info);
8140 +
8141 +int ipsec_get_cipher_algorithm(unsigned char *alg_name,unsigned int alg_mode);
8142 +int ipsec_get_auth_algorithm(unsigned char *alg_name,unsigned int alg_mode);
8143 +#if 0
8144 +void ipsec_sw_authentication(char *data,unsigned int data_len,char *authkey,char authAlgorithm,char *auth_result);
8145 +void ipsec_sw_cipher(unsigned char *pt,unsigned int pt_len, unsigned char *cipher_key, unsigned int key_size,
8146 +                            unsigned char *iv,unsigned int cipherAlgorithm,unsigned char *ct);
8147 +void ipsec_sw_auth_cipher(unsigned int op_mode,char *data,unsigned int data_len,
8148 +                                BYTE *auth_key,char authAlgorithm,char *auth_result,
8149 +                                char *pt, unsigned int pt_len,char *cipher_key, int key_size,
8150 +                                char *iv, char cipherAlgorithm,char *ct);
8151 +#endif
8152 +
8153 +
8154 +#endif
8155 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/sl_random.h
8156 ===================================================================
8157 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8158 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/sl_random.h     2008-03-13 17:48:24.508798285 +0200
8159 @@ -0,0 +1,2 @@
8160 +#define RANDOM_ADD             (IO_ADDRESS (0x051000000) + 0x0AC)
8161 +
8162 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/system.h
8163 ===================================================================
8164 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8165 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/system.h        2008-03-13 17:48:24.508798285 +0200
8166 @@ -0,0 +1,54 @@
8167 +/*
8168 + *  linux/include/asm-arm/arch-sl2312/system.h
8169 + *
8170 + *  Copyright (C) 1999 ARM Limited
8171 + *  Copyright (C) 2000 Deep Blue Solutions Ltd
8172 + *  Copyright (C) 2001 Altera Corporation
8173 + *
8174 + * This program is free software; you can redistribute it and/or modify
8175 + * it under the terms of the GNU General Public License as published by
8176 + * the Free Software Foundation; either version 2 of the License, or
8177 + * (at your option) any later version.
8178 + *
8179 + * This program is distributed in the hope that it will be useful,
8180 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8181 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8182 + * GNU General Public License for more details.
8183 + *
8184 + * You should have received a copy of the GNU General Public License
8185 + * along with this program; if not, write to the Free Software
8186 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8187 + */
8188 +#ifndef __ASM_ARCH_SYSTEM_H
8189 +#define __ASM_ARCH_SYSTEM_H
8190 +
8191 +#include <asm/arch/platform.h>
8192 +#include <asm/arch/hardware.h>
8193 +#include <asm/arch/it8712.h>
8194 +#include <asm/io.h>
8195 +
8196 +static void arch_idle(void)
8197 +{
8198 +       /*
8199 +        * This should do all the clock switching
8200 +        * and wait for interrupt tricks
8201 +        */
8202 +       cpu_do_idle();
8203 +}
8204 +
8205 +extern __inline__ void arch_reset(char mode)
8206 +{
8207 +       __raw_writel( (int) GLOBAL_RESET|RESET_CPU1, IO_ADDRESS(SL2312_GLOBAL_BASE) + GLOBAL_RESET_REG);
8208 +}
8209 +
8210 +
8211 +void (*pm_power_off)(void);
8212 +//{
8213 +//     printk("arch_power_off\n");
8214 +
8215 +       // Power off
8216 +//     __raw_writel( (int) 0x00000001, IO_ADDRESS(SL2312_POWER_CTRL_BASE) + 0x04);
8217 +
8218 +//}
8219 +
8220 +#endif
8221 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/timer.h
8222 ===================================================================
8223 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8224 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/timer.h 2008-03-13 17:48:24.508798285 +0200
8225 @@ -0,0 +1,53 @@
8226 +/*
8227 + *
8228 + *  This file contains the register definitions for the Excalibur
8229 + *  Timer TIMER00.
8230 + *
8231 + *  Copyright (C) 2001 Altera Corporation
8232 + *
8233 + * This program is free software; you can redistribute it and/or modify
8234 + * it under the terms of the GNU General Public License as published by
8235 + * the Free Software Foundation; either version 2 of the License, or
8236 + * (at your option) any later version.
8237 + *
8238 + * This program is distributed in the hope that it will be useful,
8239 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8240 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8241 + * GNU General Public License for more details.
8242 + *
8243 + * You should have received a copy of the GNU General Public License
8244 + * along with this program; if not, write to the Free Software
8245 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8246 + */
8247 +#ifndef __TIMER_H
8248 +#define __TIMER_H
8249 +
8250 +/*
8251 + * Register definitions for the timers
8252 + */
8253 +
8254 +#define TIMER_COUNT(BASE_ADDR)          (TIMER_TYPE (BASE_ADDR  + 0x00 ))
8255 +#define TIMER_LOAD(BASE_ADDR)           (TIMER_TYPE (BASE_ADDR  + 0x04 ))
8256 +#define TIMER_MATCH1(BASE_ADDR)         (TIMER_TYPE (BASE_ADDR  + 0x08 ))
8257 +#define TIMER_MATCH2(BASE_ADDR)         (TIMER_TYPE (BASE_ADDR  + 0x0C ))
8258 +#define TIMER_CR(BASE_ADDR)             (TIMER_TYPE (BASE_ADDR  + 0x30 ))
8259 +#define TIMER_1_CR_ENABLE_MSK              (0x00000001)
8260 +#define TIMER_1_CR_ENABLE_OFST                     (0)
8261 +#define TIMER_1_CR_CLOCK_MSK               (0x00000002)
8262 +#define TIMER_1_CR_CLOCK_OFST              (1)
8263 +#define TIMER_1_CR_INT_MSK                     (0x00000004)
8264 +#define TIMER_1_CR_INT_OFST                (2)
8265 +#define TIMER_2_CR_ENABLE_MSK              (0x00000008)
8266 +#define TIMER_2_CR_ENABLE_OFST                     (3)
8267 +#define TIMER_2_CR_CLOCK_MSK               (0x00000010)
8268 +#define TIMER_2_CR_CLOCK_OFST              (4)
8269 +#define TIMER_2_CR_INT_MSK                     (0x00000020)
8270 +#define TIMER_2_CR_INT_OFST                (5)
8271 +#define TIMER_3_CR_ENABLE_MSK              (0x00000040)
8272 +#define TIMER_3_CR_ENABLE_OFST                     (6)
8273 +#define TIMER_3_CR_CLOCK_MSK               (0x00000080)
8274 +#define TIMER_3_CR_CLOCK_OFST              (7)
8275 +#define TIMER_3_CR_INT_MSK                     (0x00000100)
8276 +#define TIMER_3_CR_INT_OFST                (8)
8277 +
8278 +#endif /* __TIMER00_H */
8279 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/timex.h
8280 ===================================================================
8281 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8282 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/timex.h 2008-03-13 17:48:24.508798285 +0200
8283 @@ -0,0 +1,29 @@
8284 +/*
8285 + *  linux/include/asm-arm/arch-epxa10db/timex.h
8286 + *
8287 + *  Excalibur timex specifications
8288 + *
8289 + *  Copyright (C) 2001 Altera Corporation
8290 + *
8291 + * This program is free software; you can redistribute it and/or modify
8292 + * it under the terms of the GNU General Public License as published by
8293 + * the Free Software Foundation; either version 2 of the License, or
8294 + * (at your option) any later version.
8295 + *
8296 + * This program is distributed in the hope that it will be useful,
8297 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8298 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8299 + * GNU General Public License for more details.
8300 + *
8301 + * You should have received a copy of the GNU General Public License
8302 + * along with this program; if not, write to the Free Software
8303 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8304 + */
8305 +
8306 +/*
8307 + * ??
8308 + */
8309 +#include <asm/arch/sl2312.h>
8310 +
8311 +#define CLOCK_TICK_RATE                APB_CLK
8312 +
8313 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/uart.h
8314 ===================================================================
8315 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8316 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/uart.h  2008-03-13 17:48:24.508798285 +0200
8317 @@ -0,0 +1,100 @@
8318 +/* *
8319 + *  Copyright (C) 2001 Altera Corporation
8320 + *
8321 + * This program is free software; you can redistribute it and/or modify
8322 + * it under the terms of the GNU General Public License as published by
8323 + * the Free Software Foundation; either version 2 of the License, or
8324 + * (at your option) any later version.
8325 + *
8326 + * This program is distributed in the hope that it will be useful,
8327 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8328 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8329 + * GNU General Public License for more details.
8330 + *
8331 + * You should have received a copy of the GNU General Public License
8332 + * along with this program; if not, write to the Free Software
8333 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8334 + */
8335 +#ifndef __UART_H
8336 +#define __UART_H
8337 +
8338 +/*
8339 + * Register definitions for the UART
8340 + */
8341 +
8342 +#define UART_TX_FIFO_SIZE      (15)
8343 +
8344 +#define UART_RBR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x00))  // read
8345 +#define UART_THR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x00))  // write
8346 +#define UART_IER(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x04))
8347 +#define UART_IER_MS                                 (0x08)
8348 +#define UART_IER_RLS                                (0x04)
8349 +#define UART_IER_TE                                 (0x02)
8350 +#define UART_IER_DR                                 (0x01)
8351 +#define UART_IIR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x08))   // read
8352 +#define UART_IIR_NONE                              (0x01)      /* No interrupt pending */
8353 +#define UART_IIR_RLS                               (0x06)      /* Receive Line Status */
8354 +#define UART_IIR_DR                                (0x04)      /* Receive Data Ready */
8355 +#define UART_IIR_TIMEOUT                           (0x0c)      /* Receive Time Out */
8356 +#define UART_IIR_TE                                (0x02)      /* THR Empty */
8357 +#define UART_IIR_MODEM                             (0x00)      /* Modem Status */
8358 +#define UART_FCR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x08))  // write
8359 +#define UART_FCR_FE                                (0x01)      /* FIFO Enable */
8360 +#define UART_FCR_RXFR                              (0x02)      /* Rx FIFO Reset */
8361 +#define UART_FCR_TXFR                              (0x04)      /* Tx FIFO Reset */
8362 +#define UART_FCR_FIFO_1C                            (0x00)
8363 +#define UART_FCR_FIFO_4C                            (0x40)
8364 +#define UART_FCR_FIFO_8C                            (0x80)
8365 +#define UART_FCR_FIFO_14C                           (0xC0)
8366 +#define UART_LCR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x0C))
8367 +#define UART_LCR_MSK                                (0x03)
8368 +#define UART_LCR_LEN5                              (0x00)
8369 +#define UART_LCR_LEN6                              (0x01)
8370 +#define UART_LCR_LEN7                              (0x02)
8371 +#define UART_LCR_LEN8                              (0x03)
8372 +#define UART_LCR_STOP                              (0x04)
8373 +#define UART_LCR_EVEN                              (0x18)      /* Even Parity */
8374 +#define UART_LCR_ODD                               (0x08)      /* Odd Parity */
8375 +#define UART_LCR_PE                                (0x08)      /* Parity Enable */
8376 +#define UART_LCR_SETBREAK                          (0x40)      /* Set Break condition */
8377 +#define UART_LCR_STICKPARITY                       (0x20)      /* Stick Parity Enable */
8378 +#define UART_LCR_DLAB                              (0x80)      /* Divisor Latch Access Bit */
8379 +#define UART_MCR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x10))
8380 +#define UART_MCR_DTR                               (0x1)       /* Data Terminal Ready */
8381 +#define UART_MCR_RTS                               (0x2)       /* Request to Send */
8382 +#define UART_MCR_OUT1                              (0x4)       /* output       1 */
8383 +#define UART_MCR_OUT2                              (0x8)       /* output2 or global interrupt enable */
8384 +#define UART_MCR_LPBK                              (0x10)      /* loopback mode */
8385 +#define UART_MCR_MASK                               (0xE3)
8386 +#define UART_LSR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x14))
8387 +#define UART_LSR_DR                                (0x01)      /* Data Ready */
8388 +#define UART_LSR_OE                                (0x02)      /* Overrun Error */
8389 +#define UART_LSR_PE                                (0x04)      /* Parity Error */
8390 +#define UART_LSR_FE                                (0x08)      /* Framing Error */
8391 +#define UART_LSR_BI                                 (0x10)             /* Break Interrupt */
8392 +#define UART_LSR_THRE                               (0x20)             /* THR Empty */
8393 +#define UART_LSR_TE                                 (0x40)             /* Transmitte Empty */
8394 +#define UART_LSR_DE                                 (0x80)             /* FIFO Data Error */
8395 +#define UART_MSR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x18))
8396 +#define UART_MSR_DELTACTS                          (0x01)      /* Delta CTS */
8397 +#define UART_MSR_DELTADSR                          (0x02)      /* Delta DSR */
8398 +#define UART_MSR_TERI                              (0x04)      /* Trailing Edge RI */
8399 +#define UART_MSR_DELTACD                           (0x08)      /* Delta CD */
8400 +#define UART_MSR_CTS                               (0x10)      /* Clear To Send */
8401 +#define UART_MSR_DSR                               (0x20)      /* Data Set Ready */
8402 +#define UART_MSR_RI                                (0x40)      /* Ring Indicator */
8403 +#define UART_MSR_DCD                               (0x80)      /* Data Carrier Detect */
8404 +#define UART_SPR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x1C))
8405 +#define UART_DIV_LO(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x0))
8406 +#define UART_DIV_HI(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x4))
8407 +#define UART_PSR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x8))
8408 +#define UART_MDR(BASE_ADDR) (UART_TYPE (BASE_ADDR  + 0x20))
8409 +#define UART_MDR_SERIAL                             (0x0)
8410 +
8411 +#define UART_MSR_DDCD  0x08    /* Delta DCD */
8412 +#define UART_MSR_DDSR  0x02    /* Delta DSR */
8413 +#define UART_MSR_DCTS  0x01    /* Delta CTS */
8414 +#define UART_MSR_ANY_DELTA 0x0F        /* Any of the delta bits! */
8415 +
8416 +
8417 +#endif /* __UART_H */
8418 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/uncompress.h
8419 ===================================================================
8420 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8421 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/uncompress.h    2008-03-13 17:48:24.508798285 +0200
8422 @@ -0,0 +1,94 @@
8423 +/*
8424 + *  linux/include/asm-arm/arch-epxa10db/uncompress.h
8425 + *
8426 + *  Copyright (C) 1999 ARM Limited
8427 + *  Copyright (C) 2001 Altera Corporation
8428 + *
8429 + * This program is free software; you can redistribute it and/or modify
8430 + * it under the terms of the GNU General Public License as published by
8431 + * the Free Software Foundation; either version 2 of the License, or
8432 + * (at your option) any later version.
8433 + *
8434 + * This program is distributed in the hope that it will be useful,
8435 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8436 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8437 + * GNU General Public License for more details.
8438 + *
8439 + * You should have received a copy of the GNU General Public License
8440 + * along with this program; if not, write to the Free Software
8441 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8442 + */
8443 +#include "asm/arch/platform.h"
8444 +#include "asm/arch/hardware.h"
8445 +#define UART_TYPE (volatile unsigned int*)
8446 +#ifndef CONFIG_SERIAL_IT8712
8447 +#include "asm/arch/uart.h"
8448 +#endif
8449 +extern unsigned int it8712_uart_base;
8450 +
8451 +/*
8452 + * This does not append a newline
8453 + */
8454 +static void putstr(const char *s)
8455 +{
8456 +
8457 +#ifdef CONFIG_SERIAL_IT8712
8458 +
8459 +       unsigned char *base,*status,stat;
8460 +       int i ;
8461 +
8462 +       status = (unsigned char*)it8712_uart_base + 5;
8463 +       base = (unsigned char*)it8712_uart_base ;
8464 +
8465 +       while (*s) {
8466 +
8467 +               stat = *status;
8468 +               while (!(stat&0x20)) {                          // check status
8469 +                       for(i=0;i<0x10;i++)     ;
8470 +                       status = (unsigned char*)it8712_uart_base + 5;
8471 +                       stat = *status ;
8472 +               }
8473 +
8474 +               *base = *s;
8475 +               barrier();
8476 +
8477 +               if (*s == '\n') {
8478 +                       stat = *status;
8479 +                       while (!(stat&0x20)) {                  // check status
8480 +                               for(i=0;i<0x10;i++)     ;
8481 +                               status = (unsigned char*)it8712_uart_base + 5;
8482 +                               stat = *status ;
8483 +               }
8484 +
8485 +                       barrier();
8486 +                       *base = '\r';
8487 +               }
8488 +               s++;
8489 +       }
8490 +
8491 +#else
8492 +       while (*s) {
8493 +               while (!(*UART_LSR(SL2312_UART_BASE) &
8494 +                        UART_LSR_THRE));
8495 +                      barrier();
8496 +
8497 +               *UART_THR(SL2312_UART_BASE) = *s;
8498 +
8499 +               if (*s == '\n') {
8500 +                       while (!(*UART_LSR(SL2312_UART_BASE) &
8501 +                                UART_LSR_THRE));
8502 +                               barrier();
8503 +
8504 +                       *UART_THR(SL2312_UART_BASE) = '\r';
8505 +               }
8506 +               s++;
8507 +       }
8508 +#endif
8509 +}
8510 +
8511 +/*
8512 + * nothing to do
8513 + */
8514 +#define arch_decomp_setup()
8515 +
8516 +#define arch_decomp_wdog()
8517 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/vmalloc.h
8518 ===================================================================
8519 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8520 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/vmalloc.h       2008-03-13 17:48:24.508798285 +0200
8521 @@ -0,0 +1,36 @@
8522 +/*
8523 + *  linux/include/asm-arm/arch-epxa10db/vmalloc.h
8524 + *
8525 + *  Copyright (C) 2000 Russell King.
8526 + *
8527 + * This program is free software; you can redistribute it and/or modify
8528 + * it under the terms of the GNU General Public License as published by
8529 + * the Free Software Foundation; either version 2 of the License, or
8530 + * (at your option) any later version.
8531 + *
8532 + * This program is distributed in the hope that it will be useful,
8533 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
8534 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
8535 + * GNU General Public License for more details.
8536 + *
8537 + * You should have received a copy of the GNU General Public License
8538 + * along with this program; if not, write to the Free Software
8539 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
8540 + */
8541 +
8542 +/*
8543 + * Just any arbitrary offset to the start of the vmalloc VM area: the
8544 + * current 8MB value just means that there will be a 8MB "hole" after the
8545 + * physical memory until the kernel virtual memory starts.  That means that
8546 + * any out-of-bounds memory accesses will hopefully be caught.
8547 + * The vmalloc() routines leaves a hole of 4kB between each vmalloced
8548 + * area for the same reason. ;)
8549 + */
8550 +#define VMALLOC_OFFSET   (8*1024*1024)
8551 +#define VMALLOC_START    (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
8552 +#define VMALLOC_VMADDR(x) ((unsigned long)(x))
8553 +#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
8554 +
8555 +//#define MODULE_START    (PAGE_OFFSET - 16*1048576)
8556 +//#define MODULE_END      (PAGE_OFFSET)
8557 +
8558 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/watchdog.h
8559 ===================================================================
8560 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8561 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/watchdog.h      2008-03-13 17:48:24.508798285 +0200
8562 @@ -0,0 +1,58 @@
8563 +#ifndef __WATCHDOG_H
8564 +#define __WATCHDOG_H
8565 +
8566 +#define WATCHDOG_BASE                    (IO_ADDRESS (SL2312_WAQTCHDOG_BASE))
8567 +#define WATCHDOG_COUNTER                  (WATCHDOG_BASE + 0x00)
8568 +#define WATCHDOG_LOAD                     (WATCHDOG_BASE + 0x04)
8569 +#define WATCHDOG_RESTART                  (WATCHDOG_BASE + 0x08)
8570 +#define WATCHDOG_CR                       (WATCHDOG_BASE + 0x0C)
8571 +#define WATCHDOG_STATUS                   (WATCHDOG_BASE + 0x10)
8572 +#define WATCHDOG_CLEAR                    (WATCHDOG_BASE + 0x14)
8573 +#define WATCHDOG_INTRLEN                  (WATCHDOG_BASE + 0x18)
8574 +
8575 +#define WATCHDOG_WDENABLE_MSK            (0x00000001)
8576 +#define WATCHDOG_WDENABLE_OFST                   (0)
8577 +#define WATCHDOG_WDRST_MSK               (0x00000002)
8578 +#define WATCHDOG_WDRST_OFST              (1)
8579 +#define WATCHDOG_WDINTR_MSK              (0x00000004)
8580 +#define WATCHDOG_WDINTR_OFST             (2)
8581 +#define WATCHDOG_WDEXT_MSK               (0x00000008)
8582 +#define WATCHDOG_WDEXT_OFST              (3)
8583 +#define WATCHDOG_WDCLOCK_MSK             (0x00000010)
8584 +#define WATCHDOG_WDCLOCK_OFST            (4)
8585 +#define WATCHDOG_CR_MASK                  (0x0000001F)
8586 +
8587 +#define WATCHDOG_CLEAR_STATUS             0x1
8588 +#define WATCHDOG_ENABLE                   1
8589 +#define WATCHDOG_DISABLE                  0
8590 +#define WATCHDOG_RESTART_VALUE            0x5AB9
8591 +
8592 +#define WATCHDOG_MINOR                   130
8593 +
8594 +#define WATCHDOG_IOCTRL_DISABLE                  0x01
8595 +#define WATCHDOG_IOCTRL_SETTIME                  0x02
8596 +#define WATCHDOG_IOCTRL_ENABLE           0x03
8597 +#define WATCHDOG_IOCTRL_RESTART                  0x04
8598 +
8599 +#define WATCHDOG_TIMEOUT_SCALE            APB_CLK
8600 +#define WATCHDOG_TIMEOUT_MARGIN           30
8601 +#define WATCHDOG_DRIVER_OPEN              1
8602 +#define WATCHDOG_DRIVER_CLOSE             0
8603 +
8604 +
8605 +static void     watchdog_disable(void);
8606 +static void     watchdog_enable(void);
8607 +static int      watchdog_open(struct inode *, struct file *);
8608 +static int      watchdog_release(struct inode *, struct file *);
8609 +static ssize_t  watchdog_read(struct file *, char *, size_t, loff_t *);
8610 +static ssize_t  watchdog_write(struct file *, const char *, size_t, loff_t *);
8611 +static int      watchdog_ioctl(struct inode *, struct file *, unsigned int, unsigned long);
8612 +#ifdef WATCHDOG_TEST
8613 +static void watchdog_fire(int, void *, struct pt_regs *);
8614 +#endif
8615 +
8616 +
8617 +
8618 +
8619 +
8620 +#endif
8621 Index: linux-2.6.23.16/include/asm-arm/arch-sl2312/xor.h
8622 ===================================================================
8623 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
8624 +++ linux-2.6.23.16/include/asm-arm/arch-sl2312/xor.h   2008-03-13 17:48:24.508798285 +0200
8625 @@ -0,0 +1,29 @@
8626 +/*
8627 + * include/asm-arm/arch-sl2312/xor.h
8628 + *
8629 + * Copyright (C) 2005 Storlink Corp.
8630 + *
8631 + * This program is free software; you can redistribute it and/or modify
8632 + * it under the terms of the GNU General Public License version 2 as
8633 + * published by the Free Software Foundation.
8634 + */
8635 +
8636 +#ifndef _ASM_ARCH_XOR_H
8637 +#define _ASM_ARCH_XOR_H
8638 +
8639 +/*
8640 + * Function prototypes
8641 + */
8642 +void xor_gemini_2(unsigned long bytes, unsigned long *p1, unsigned long *p2);
8643 +
8644 +void xor_gemini_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
8645 +                            unsigned long *p3);
8646 +
8647 +void xor_gemini_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
8648 +                            unsigned long *p3, unsigned long *p4);
8649 +
8650 +void xor_gemini_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
8651 +                            unsigned long *p3, unsigned long *p4, unsigned long *p5);
8652 +
8653 +#endif /* _ASM_ARCH_XOR_H */
8654 +
8655 Index: linux-2.6.23.16/include/asm-arm/cacheflush.h
8656 ===================================================================
8657 --- linux-2.6.23.16.orig/include/asm-arm/cacheflush.h   2008-03-13 17:46:04.500819685 +0200
8658 +++ linux-2.6.23.16/include/asm-arm/cacheflush.h        2008-03-13 17:48:24.508798285 +0200
8659 @@ -46,6 +46,18 @@
8660  # define MULTI_CACHE 1
8661  #endif
8662
8663 +/***********************************************************************
8664 + *             Storlink SoC -- Cache
8665 + ***********************************************************************/
8666 +#if defined(CONFIG_CPU_FA526)
8667 +# ifdef _CACHE
8668 +#  define MULTI_CACHE 1
8669 +# else
8670 +#  define _CACHE fa
8671 +# endif
8672 +#endif
8673 +/***********************************************************************/
8674 +
8675  #if defined(CONFIG_CPU_ARM926T)
8676  # ifdef _CACHE
8677  #  define MULTI_CACHE 1
8678 Index: linux-2.6.23.16/include/asm-arm/page.h
8679 ===================================================================
8680 --- linux-2.6.23.16.orig/include/asm-arm/page.h 2008-03-13 17:46:04.500819685 +0200
8681 +++ linux-2.6.23.16/include/asm-arm/page.h      2008-03-13 17:48:24.508798285 +0200
8682 @@ -74,6 +74,18 @@
8683  # endif
8684  #endif
8685
8686 +/***********************************************************************
8687 + *             Storlink SoC -- flash
8688 + ***********************************************************************/
8689 +#ifdef CONFIG_CPU_COPY_FA
8690 +# ifdef _USER
8691 +#  define MULTI_USER 1
8692 +# else
8693 +#  define _USER fa
8694 +# endif
8695 +#endif
8696 +/***********************************************************************/
8697 +
8698  #ifdef CONFIG_CPU_SA1100
8699  # ifdef _USER
8700  #  define MULTI_USER 1
8701 Index: linux-2.6.23.16/include/asm-arm/proc-fns.h
8702 ===================================================================
8703 --- linux-2.6.23.16.orig/include/asm-arm/proc-fns.h     2008-03-13 17:46:04.500819685 +0200
8704 +++ linux-2.6.23.16/include/asm-arm/proc-fns.h  2008-03-13 17:48:24.508798285 +0200
8705 @@ -89,6 +89,14 @@
8706  #   define CPU_NAME cpu_arm922
8707  #  endif
8708  # endif
8709 +# ifdef CONFIG_CPU_FA526
8710 +#  ifdef CPU_NAME
8711 +#   undef  MULTI_CPU
8712 +#   define MULTI_CPU
8713 +#  else
8714 +#   define CPU_NAME cpu_fa526
8715 +#  endif
8716 +# endif
8717  # ifdef CONFIG_CPU_ARM925T
8718  #  ifdef CPU_NAME
8719  #   undef  MULTI_CPU
8720 Index: linux-2.6.23.16/include/asm-arm/tlbflush.h
8721 ===================================================================
8722 --- linux-2.6.23.16.orig/include/asm-arm/tlbflush.h     2008-03-13 17:46:04.500819685 +0200
8723 +++ linux-2.6.23.16/include/asm-arm/tlbflush.h  2008-03-13 17:58:18.542650345 +0200
8724 @@ -39,6 +39,8 @@
8725  #define TLB_V6_D_ASID  (1 << 17)
8726  #define TLB_V6_I_ASID  (1 << 18)
8727
8728 +#define TLB_DINVAL      (1 << 28)
8729 +#define TLB_BTB         (1 << 29)
8730  #define TLB_DCLEAN     (1 << 30)
8731  #define TLB_WB         (1 << 31)
8732
8733 @@ -52,6 +54,7 @@
8734   *       v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
8735   *       v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
8736   *       v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
8737 + *    fa    - ARMv4 with write buffer with UTLB and branch target buffer (BTB)
8738   */
8739  #undef _TLB
8740  #undef MULTI_TLB
8741 @@ -86,6 +89,44 @@
8742  # define v4_always_flags       (-1UL)
8743  #endif
8744
8745 +#ifdef CONFIG_CPU_FA_BTB
8746 +#define __TLB_BTB      TLB_BTB
8747 +#else
8748 +#define __TLB_BTB      0
8749 +#endif
8750 +
8751 +#ifdef CONFIG_CPU_FA_WB_DISABLE
8752 +#define __TLB_WB       0
8753 +#else
8754 +#define __TLB_WB       TLB_WB
8755 +#endif
8756 +
8757 +/* Fix buggy CPU which doesn't invalidate Dcache properly */
8758 +#ifdef CONFIG_CPU_FA520
8759 +#define __TLB_DINVAL   TLB_DINVAL
8760 +#elif defined(CONFIG_CPU_FA526)
8761 +//#define __TLB_DINVAL   TLB_DINVAL
8762 +#define __TLB_DINVAL   0
8763 +#else
8764 +#define __TLB_DINVAL   0
8765 +#endif
8766 +
8767 +#define fa_tlb_flags   (__TLB_WB | __TLB_BTB | __TLB_DINVAL | TLB_DCLEAN | \
8768 +                         TLB_V4_U_FULL | TLB_V4_U_PAGE)
8769 +
8770 +#ifdef CONFIG_CPU_TLB_FA
8771 +# define fa_possible_flags     fa_tlb_flags
8772 +# define fa_always_flags       fa_tlb_flags
8773 +# ifdef _TLB
8774 +#  define MULTI_TLB 1
8775 +# else
8776 +#  define _TLB fa
8777 +# endif
8778 +#else
8779 +# define fa_possible_flags     0
8780 +# define fa_always_flags       (-1UL)
8781 +#endif
8782 +
8783  #define v4wbi_tlb_flags        (TLB_WB | TLB_DCLEAN | \
8784                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
8785                          TLB_V4_I_PAGE | TLB_V4_D_PAGE)
8786 @@ -246,12 +287,14 @@
8787                                  v4_possible_flags | \
8788                                  v4wbi_possible_flags | \
8789                                  v4wb_possible_flags | \
8790 +                 fa_possible_flags | \
8791                                  v6wbi_possible_flags)
8792
8793  #define always_tlb_flags       (v3_always_flags & \
8794                                  v4_always_flags & \
8795                                  v4wbi_always_flags & \
8796                                  v4wb_always_flags & \
8797 +                 fa_always_flags & \
8798                                  v6wbi_always_flags)
8799
8800  #define tlb_flag(f)    ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
8801 @@ -261,6 +304,9 @@
8802         const int zero = 0;
8803         const unsigned int __tlb_flag = __cpu_tlb_flags;
8804
8805 +       if (tlb_flag(TLB_DINVAL))
8806 +               asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero));
8807 +
8808         if (tlb_flag(TLB_WB))
8809                 dsb();
8810
8811 @@ -281,6 +327,13 @@
8812                 dsb();
8813                 isb();
8814         }
8815 +
8816 +       if (tlb_flag(TLB_BTB))
8817 +       {
8818 +        asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8819 +               asm("mov r0, r0" : : );
8820 +               asm("mov r0, r0" : : );
8821 +       }
8822  }
8823
8824  static inline void local_flush_tlb_mm(struct mm_struct *mm)
8825 @@ -289,6 +342,9 @@
8826         const int asid = ASID(mm);
8827         const unsigned int __tlb_flag = __cpu_tlb_flags;
8828
8829 +       if (tlb_flag(TLB_DINVAL))
8830 +               asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero));
8831 +
8832         if (tlb_flag(TLB_WB))
8833                 dsb();
8834
8835 @@ -317,6 +373,14 @@
8836                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
8837                 dsb();
8838         }
8839 +
8840 +       if (tlb_flag(TLB_BTB))
8841 +       {
8842 +        asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8843 +               asm("mov r0, r0" : : );
8844 +               asm("mov r0, r0" : : );
8845 +       }
8846 +
8847  }
8848
8849  static inline void
8850 @@ -327,6 +391,9 @@
8851
8852         uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
8853
8854 +       if (tlb_flag(TLB_DINVAL))
8855 +        asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero)); // clean & invalidate data cache all
8856 +
8857         if (tlb_flag(TLB_WB))
8858                 dsb();
8859
8860 @@ -357,6 +424,13 @@
8861                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
8862                 dsb();
8863         }
8864 +
8865 +       if (tlb_flag(TLB_BTB))
8866 +       {
8867 +        asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8868 +               asm("mov r0, r0" : : );
8869 +               asm("mov r0, r0" : : );
8870 +       }
8871  }
8872
8873  static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
8874 @@ -366,6 +440,9 @@
8875
8876         kaddr &= PAGE_MASK;
8877
8878 +       if (tlb_flag(TLB_DINVAL))
8879 +        asm("mcr%? p15, 0, %0, c7, c14, 0" : : "r" (zero));
8880 +
8881         if (tlb_flag(TLB_WB))
8882                 dsb();
8883
8884 @@ -386,6 +463,12 @@
8885                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
8886         if (tlb_flag(TLB_V6_I_PAGE))
8887                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
8888 +       if (tlb_flag(TLB_BTB))
8889 +       {
8890 +        asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8891 +               asm("mov r0, r0" : : );
8892 +               asm("mov r0, r0" : : );
8893 +       }
8894
8895         if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
8896                      TLB_V6_I_PAGE | TLB_V6_D_PAGE |
8897 @@ -412,6 +495,7 @@
8898   */
8899  static inline void flush_pmd_entry(pmd_t *pmd)
8900  {
8901 +       const unsigned int zero = 0;
8902         const unsigned int __tlb_flag = __cpu_tlb_flags;
8903
8904         if (tlb_flag(TLB_DCLEAN))
8905 @@ -419,15 +503,30 @@
8906                         : : "r" (pmd) : "cc");
8907         if (tlb_flag(TLB_WB))
8908                 dsb();
8909 +
8910 +       if (tlb_flag(TLB_BTB)) // Luke Lee 05/16/2005
8911 +       {
8912 +        asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8913 +               asm("mov r0, r0" : : );
8914 +               asm("mov r0, r0" : : );
8915 +       }
8916  }
8917
8918  static inline void clean_pmd_entry(pmd_t *pmd)
8919  {
8920 +    const unsigned int zero = 0; // Luke Lee 05/16/2005 ins 1
8921         const unsigned int __tlb_flag = __cpu_tlb_flags;
8922
8923         if (tlb_flag(TLB_DCLEAN))
8924                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
8925                         : : "r" (pmd) : "cc");
8926 +
8927 +       if (tlb_flag(TLB_BTB)) // Luke Lee 05/16/2005
8928 +       {
8929 +        asm("mcr%? p15, 0, %0, c7, c5, 6" : : "r" (zero));
8930 +               asm("mov r0, r0" : : );
8931 +               asm("mov r0, r0" : : );
8932 +       }
8933  }
8934
8935  #undef tlb_flag
8936 Index: linux-2.6.23.16/include/asm-arm/xor.h
8937 ===================================================================
8938 --- linux-2.6.23.16.orig/include/asm-arm/xor.h  2008-03-13 17:46:04.500819685 +0200
8939 +++ linux-2.6.23.16/include/asm-arm/xor.h       2008-03-13 17:48:24.508798285 +0200
8940 @@ -139,3 +139,18 @@
8941                 xor_speed(&xor_block_8regs);    \
8942                 xor_speed(&xor_block_32regs);   \
8943         } while (0)
8944 +
8945 +#ifdef CONFIG_GEMINI_XOR_ACCE
8946 +#include <asm/arch/xor.h>
8947 +static struct xor_block_template xor_block_gemini = {
8948 +       .name   = "gemini xor acceleration",
8949 +       .do_2   = xor_gemini_2,
8950 +       .do_3   = xor_gemini_3,
8951 +       .do_4   = xor_gemini_4,
8952 +       .do_5   = xor_gemini_5,};
8953 +#undef XOR_TRY_TEMPLATES
8954 +#define XOR_TRY_TEMPLATES                      \
8955 +       do {                                    \
8956 +       xor_speed(&xor_block_gemini); \
8957 +       } while (0)
8958 +#endif
8959 Index: linux-2.6.23.16/include/linux/apm_bios.h
8960 ===================================================================
8961 --- linux-2.6.23.16.orig/include/linux/apm_bios.h       2008-03-13 17:46:04.500819685 +0200
8962 +++ linux-2.6.23.16/include/linux/apm_bios.h    2008-03-13 17:48:24.508798285 +0200
8963 @@ -217,4 +217,24 @@
8964  #define APM_IOC_STANDBY                _IO('A', 1)
8965  #define APM_IOC_SUSPEND                _IO('A', 2)
8966
8967 +// add by jason for power control
8968 +struct pwc_ioctl_data {
8969 +       unsigned int action;    // sword struct
8970 +       unsigned int data;      // stand shutdown time for PWC_SET_SHUT_TIME
8971 +                               // stand shutdown source for PWC_WAIT_BTN
8972 +};
8973 +
8974 +#define POWEROFF               0x01
8975 +#define RESTORE_DEFAULT        0x02
8976 +#define SYSTEM_REBOOT  0x04
8977 +
8978 +#define PWR_SRC_CIR            0x10
8979 +#define PWR_SRC_RTC            0x20
8980 +#define PWR_SRC_BTN            0x40
8981 +
8982 +#define        PWC_IOCTL_BASE                  'A'                             // use linux APM ioctl
8983 +#define PWC_SET_SHUT_TIME              _IOW('A', 16, struct pwc_ioctl_data)
8984 +#define PWC_WAIT_BTN                   _IOR('A', 17, struct pwc_ioctl_data)
8985 +#define PWC_SHUTDOWN                   _IO ('A', 18)
8986 +
8987  #endif /* LINUX_APM_H */
8988 Index: linux-2.6.23.16/kernel/time.c
8989 ===================================================================
8990 --- linux-2.6.23.16.orig/kernel/time.c  2008-03-13 17:46:04.500819685 +0200
8991 +++ linux-2.6.23.16/kernel/time.c       2008-03-13 17:48:24.508798285 +0200
8992 @@ -76,6 +76,7 @@
8993   * why not move it into the appropriate arch directory (for those
8994   * architectures that need it).
8995   */
8996 +extern void rtc_set_time_second(unsigned int second);
8997
8998  asmlinkage long sys_stime(time_t __user *tptr)
8999  {
9000 @@ -87,6 +88,10 @@
9001
9002         tv.tv_nsec = 0;
9003
9004 +#ifdef CONFIG_SL2312_RTC
9005 +    rtc_set_time_second(tv.tv_sec);
9006 +#endif
9007 +
9008         err = security_settime(&tv, NULL);
9009         if (err)
9010                 return err;