target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-core.c

   1 /* Smedia Glamo 336x/337x driver
   2  *
   3  * (C) 2007 by Openmoko, Inc.
   4  * Author: Harald Welte <laforge@openmoko.org>
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/init.h>
  33 #include <linux/irq.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/wait.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/kernel_stat.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/glamofb.h>
  41 #include <linux/mmc/mmc.h>
  42 #include <linux/mmc/host.h>
  43
  44 #include <asm/io.h>
  45 #include <asm/uaccess.h>
  46 #include <asm/div64.h>
  47
  48 //#include <mach/regs-irq.h>
  49
  50 #ifdef CONFIG_PM
  51 #include <linux/pm.h>
  52 #endif
  53
  54 #include "glamo-regs.h"
  55 #include "glamo-core.h"
  56
  57 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
  58
  59 #define GLAMO_MEM_REFRESH_COUNT 0x100
  60
  61
  62 /*
  63  * Glamo internal settings
  64  *
  65  * We run the memory interface from the faster PLLB on 2.6.28 kernels and
  66  * above.  Couple of GTA02 users report trouble with memory bus when they
  67  * upgraded from 2.6.24.  So this parameter allows reversion to 2.6.24
  68  * scheme if their Glamo chip needs it.
  69  *
  70  * you can override the faster default on kernel commandline using
  71  *
  72  *   glamo3362.slow_memory=1
  73  *
  74  * for example
  75  */
  76
  77 static int slow_memory = 0;
  78 module_param(slow_memory, int, 0644);
  79
  80 struct reg_range {
  81         int start;
  82         int count;
  83         char *name;
  84         char dump;
  85 };
  86 struct reg_range reg_range[] = {
  87         { 0x0000, 0x76,         "General",      1 },
  88         { 0x0200, 0x16,         "Host Bus",     1 },
  89         { 0x0300, 0x38,         "Memory",       1 },
  90 /*      { 0x0400, 0x100,        "Sensor",       0 }, */
  91 /*              { 0x0500, 0x300,        "ISP",          0 }, */
  92 /*              { 0x0800, 0x400,        "JPEG",         0 }, */
  93 /*              { 0x0c00, 0xcc,         "MPEG",         0 }, */
  94         { 0x1100, 0xb2,         "LCD 1",        1 },
  95         { 0x1200, 0x64,         "LCD 2",        1 },
  96         { 0x1400, 0x40,         "MMC",          1 },
  97 /*              { 0x1500, 0x080,        "MPU 0",        0 },
  98         { 0x1580, 0x080,        "MPU 1",        0 },
  99         { 0x1600, 0x080,        "Cmd Queue",    0 },
 100         { 0x1680, 0x080,        "RISC CPU",     0 },
 101         { 0x1700, 0x400,        "2D Unit",      0 },
 102         { 0x1b00, 0x900,        "3D Unit",      0 }, */
 103 };
 104
 105 static struct glamo_core *glamo_handle;
 106
 107 static inline void __reg_write(struct glamo_core *glamo,
 108                                 u_int16_t reg, u_int16_t val)
 109 {
 110         writew(val, glamo->base + reg);
 111 }
 112
 113 static inline u_int16_t __reg_read(struct glamo_core *glamo,
 114                                    u_int16_t reg)
 115 {
 116         return readw(glamo->base + reg);
 117 }
 118
 119 static void __reg_set_bit_mask(struct glamo_core *glamo,
 120                                 u_int16_t reg, u_int16_t mask,
 121                                 u_int16_t val)
 122 {
 123         u_int16_t tmp;
 124
 125         val &= mask;
 126
 127         tmp = __reg_read(glamo, reg);
 128         tmp &= ~mask;
 129         tmp |= val;
 130         __reg_write(glamo, reg, tmp);
 131 }
 132
 133 static void reg_set_bit_mask(struct glamo_core *glamo,
 134                                 u_int16_t reg, u_int16_t mask,
 135                                 u_int16_t val)
 136 {
 137         spin_lock(&glamo->lock);
 138         __reg_set_bit_mask(glamo, reg, mask, val);
 139         spin_unlock(&glamo->lock);
 140 }
 141
 142 static inline void __reg_set_bit(struct glamo_core *glamo,
 143                                  u_int16_t reg, u_int16_t bit)
 144 {
 145         __reg_set_bit_mask(glamo, reg, bit, 0xffff);
 146 }
 147
 148 static inline void __reg_clear_bit(struct glamo_core *glamo,
 149                                    u_int16_t reg, u_int16_t bit)
 150 {
 151         __reg_set_bit_mask(glamo, reg, bit, 0);
 152 }
 153
 154 static inline void glamo_vmem_write(struct glamo_core *glamo, u_int32_t addr,
 155                                     u_int16_t *src, int len)
 156 {
 157         if (addr & 0x0001 || (unsigned long)src & 0x0001 || len & 0x0001) {
 158                 dev_err(&glamo->pdev->dev, "unaligned write(0x%08x, 0x%p, "
 159                         "0x%x)!!\n", addr, src, len);
 160         }
 161
 162 }
 163
 164 static inline void glamo_vmem_read(struct glamo_core *glamo, u_int16_t *buf,
 165                                    u_int32_t addr, int len)
 166 {
 167         if (addr & 0x0001 || (unsigned long) buf & 0x0001 || len & 0x0001) {
 168                 dev_err(&glamo->pdev->dev, "unaligned read(0x%p, 0x08%x, "
 169                         "0x%x)!!\n", buf, addr, len);
 170         }
 171
 172
 173 }
 174
 175 /***********************************************************************
 176  * resources of sibling devices
 177  ***********************************************************************/
 178
 179 #if 0
 180 static struct resource glamo_core_resources[] = {
 181         {
 182                 .start  = GLAMO_REGOFS_GENERIC,
 183                 .end    = GLAMO_REGOFS_GENERIC + 0x400,
 184                 .flags  = IORESOURCE_MEM,
 185         }, {
 186                 .start  = 0,
 187                 .end    = 0,
 188                 .flags  = IORESOURCE_IRQ,
 189         },
 190 };
 191
 192 static struct platform_device glamo_core_dev = {
 193         .name           = "glamo-core",
 194         .resource       = &glamo_core_resources,
 195         .num_resources  = ARRAY_SIZE(glamo_core_resources),
 196 };
 197 #endif
 198
 199 static struct resource glamo_jpeg_resources[] = {
 200         {
 201                 .start  = GLAMO_REGOFS_JPEG,
 202                 .end    = GLAMO_REGOFS_MPEG - 1,
 203                 .flags  = IORESOURCE_MEM,
 204         }, {
 205                 .start  = IRQ_GLAMO_JPEG,
 206                 .end    = IRQ_GLAMO_JPEG,
 207                 .flags  = IORESOURCE_IRQ,
 208         },
 209 };
 210
 211 static struct platform_device glamo_jpeg_dev = {
 212         .name           = "glamo-jpeg",
 213         .resource       = glamo_jpeg_resources,
 214         .num_resources  = ARRAY_SIZE(glamo_jpeg_resources),
 215 };
 216
 217 static struct resource glamo_mpeg_resources[] = {
 218         {
 219                 .start  = GLAMO_REGOFS_MPEG,
 220                 .end    = GLAMO_REGOFS_LCD - 1,
 221                 .flags  = IORESOURCE_MEM,
 222         }, {
 223                 .start  = IRQ_GLAMO_MPEG,
 224                 .end    = IRQ_GLAMO_MPEG,
 225                 .flags  = IORESOURCE_IRQ,
 226         },
 227 };
 228
 229 static struct platform_device glamo_mpeg_dev = {
 230         .name           = "glamo-mpeg",
 231         .resource       = glamo_mpeg_resources,
 232         .num_resources  = ARRAY_SIZE(glamo_mpeg_resources),
 233 };
 234
 235 static struct resource glamo_2d_resources[] = {
 236         {
 237                 .start  = GLAMO_REGOFS_2D,
 238                 .end    = GLAMO_REGOFS_3D - 1,
 239                 .flags  = IORESOURCE_MEM,
 240         }, {
 241                 .start  = IRQ_GLAMO_2D,
 242                 .end    = IRQ_GLAMO_2D,
 243                 .flags  = IORESOURCE_IRQ,
 244         },
 245 };
 246
 247 static struct platform_device glamo_2d_dev = {
 248         .name           = "glamo-2d",
 249         .resource       = glamo_2d_resources,
 250         .num_resources  = ARRAY_SIZE(glamo_2d_resources),
 251 };
 252
 253 static struct resource glamo_3d_resources[] = {
 254         {
 255                 .start  = GLAMO_REGOFS_3D,
 256                 .end    = GLAMO_REGOFS_END - 1,
 257                 .flags  = IORESOURCE_MEM,
 258         },
 259 };
 260
 261 static struct platform_device glamo_3d_dev = {
 262         .name           = "glamo-3d",
 263         .resource       = glamo_3d_resources,
 264         .num_resources  = ARRAY_SIZE(glamo_3d_resources),
 265 };
 266
 267 static struct platform_device glamo_spigpio_dev = {
 268         .name           = "glamo-spi-gpio",
 269 };
 270
 271 static struct resource glamo_fb_resources[] = {
 272         /* FIXME: those need to be incremented by parent base */
 273         {
 274                 .name   = "glamo-fb-regs",
 275                 .start  = GLAMO_REGOFS_LCD,
 276                 .end    = GLAMO_REGOFS_MMC - 1,
 277                 .flags  = IORESOURCE_MEM,
 278         }, {
 279                 .name   = "glamo-fb-mem",
 280                 .start  = GLAMO_OFFSET_FB,
 281                 .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
 282                 .flags  = IORESOURCE_MEM,
 283         },
 284 };
 285
 286 static struct platform_device glamo_fb_dev = {
 287         .name           = "glamo-fb",
 288         .resource       = glamo_fb_resources,
 289         .num_resources  = ARRAY_SIZE(glamo_fb_resources),
 290 };
 291
 292 static struct resource glamo_mmc_resources[] = {
 293         {
 294                 /* FIXME: those need to be incremented by parent base */
 295                 .start  = GLAMO_REGOFS_MMC,
 296                 .end    = GLAMO_REGOFS_MPROC0 - 1,
 297                 .flags  = IORESOURCE_MEM
 298         }, {
 299                 .start  = IRQ_GLAMO_MMC,
 300                 .end    = IRQ_GLAMO_MMC,
 301                 .flags  = IORESOURCE_IRQ,
 302         }, { /* our data buffer for MMC transfers */
 303                 .start  = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
 304                 .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
 305                                   GLAMO_MMC_BUFFER_SIZE - 1,
 306                 .flags  = IORESOURCE_MEM
 307         },
 308 };
 309
 310 struct glamo_mci_pdata glamo_mci_def_pdata = {
 311         .gpio_detect            = 0,
 312         .glamo_can_set_mci_power        = NULL, /* filled in from MFD platform data */
 313         .ocr_avail      = MMC_VDD_20_21 |
 314                           MMC_VDD_21_22 |
 315                           MMC_VDD_22_23 |
 316                           MMC_VDD_23_24 |
 317                           MMC_VDD_24_25 |
 318                           MMC_VDD_25_26 |
 319                           MMC_VDD_26_27 |
 320                           MMC_VDD_27_28 |
 321                           MMC_VDD_28_29 |
 322                           MMC_VDD_29_30 |
 323                           MMC_VDD_30_31 |
 324                           MMC_VDD_32_33,
 325         .glamo_irq_is_wired     = NULL, /* filled in from MFD platform data */
 326         .mci_suspending = NULL, /* filled in from MFD platform data */
 327         .mci_all_dependencies_resumed = NULL, /* filled in from MFD platform data */
 328 };
 329 EXPORT_SYMBOL_GPL(glamo_mci_def_pdata);
 330
 331
 332
 333 static void mangle_mem_resources(struct resource *res, int num_res,
 334                                  struct resource *parent)
 335 {
 336         int i;
 337
 338         for (i = 0; i < num_res; i++) {
 339                 if (res[i].flags != IORESOURCE_MEM)
 340                         continue;
 341                 res[i].start += parent->start;
 342                 res[i].end += parent->start;
 343                 res[i].parent = parent;
 344         }
 345 }
 346
 347 /***********************************************************************
 348  * IRQ demultiplexer
 349  ***********************************************************************/
 350 #define irq2glamo(x)    (x - IRQ_GLAMO(0))
 351
 352 static void glamo_ack_irq(unsigned int irq)
 353 {
 354         /* clear interrupt source */
 355         __reg_write(glamo_handle, GLAMO_REG_IRQ_CLEAR,
 356                     1 << irq2glamo(irq));
 357 }
 358
 359 static void glamo_mask_irq(unsigned int irq)
 360 {
 361         u_int16_t tmp;
 362
 363         /* clear bit in enable register */
 364         tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
 365         tmp &= ~(1 << irq2glamo(irq));
 366         __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
 367 }
 368
 369 static void glamo_unmask_irq(unsigned int irq)
 370 {
 371         u_int16_t tmp;
 372
 373         /* set bit in enable register */
 374         tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
 375         tmp |= (1 << irq2glamo(irq));
 376         __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
 377 }
 378
 379 static struct irq_chip glamo_irq_chip = {
 380         .ack    = glamo_ack_irq,
 381         .mask   = glamo_mask_irq,
 382         .unmask = glamo_unmask_irq,
 383 };
 384
 385 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
 386 {
 387         desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
 388
 389         if (unlikely(desc->status & IRQ_INPROGRESS)) {
 390                 desc->status |= (IRQ_PENDING | IRQ_MASKED);
 391                 desc->chip->mask(irq);
 392                 desc->chip->ack(irq);
 393                 return;
 394         }
 395     kstat_incr_irqs_this_cpu(irq, desc);
 396
 397         desc->chip->ack(irq);
 398         desc->status |= IRQ_INPROGRESS;
 399
 400         do {
 401                 u_int16_t irqstatus;
 402                 int i;
 403
 404                 if (unlikely((desc->status &
 405                                 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
 406                                 (IRQ_PENDING | IRQ_MASKED))) {
 407                         /* dealing with pending IRQ, unmasking */
 408                         desc->chip->unmask(irq);
 409                         desc->status &= ~IRQ_MASKED;
 410                 }
 411
 412                 desc->status &= ~IRQ_PENDING;
 413
 414                 /* read IRQ status register */
 415                 irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS);
 416                 for (i = 0; i < 9; i++)
 417                         if (irqstatus & (1 << i))
 418                                 desc_handle_irq(IRQ_GLAMO(i),
 419                                     irq_desc+IRQ_GLAMO(i));
 420
 421         } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
 422
 423         desc->status &= ~IRQ_INPROGRESS;
 424 }
 425
 426
 427 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
 428                            const char *buf, size_t count)
 429 {
 430         unsigned long reg = simple_strtoul(buf, NULL, 10);
 431         struct glamo_core *glamo = dev_get_drvdata(dev);
 432
 433         while (*buf && (*buf != ' '))
 434                 buf++;
 435         if (*buf != ' ')
 436                 return -EINVAL;
 437         while (*buf && (*buf == ' '))
 438                 buf++;
 439         if (!*buf)
 440                 return -EINVAL;
 441
 442         printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
 443                reg, simple_strtoul(buf, NULL, 10));
 444
 445         __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
 446
 447         return count;
 448 }
 449
 450 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
 451                         char *buf)
 452 {
 453         struct glamo_core *glamo = dev_get_drvdata(dev);
 454         int n, n1 = 0, r;
 455         char * end = buf;
 456
 457         spin_lock(&glamo->lock);
 458
 459         for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
 460                 if (!reg_range[r].dump)
 461                         continue;
 462                 n1 = 0;
 463                 end += sprintf(end, "\n%s\n", reg_range[r].name);
 464                 for (n = reg_range[r].start;
 465                      n < reg_range[r].start + reg_range[r].count; n += 2) {
 466                         if (((n1++) & 7) == 0)
 467                                 end += sprintf(end, "\n%04X:  ", n);
 468                         end += sprintf(end, "%04x ", __reg_read(glamo, n));
 469                 }
 470                 end += sprintf(end, "\n");
 471                 if (!attr) {
 472                         printk("%s", buf);
 473                         end = buf;
 474                 }
 475         }
 476         spin_unlock(&glamo->lock);
 477
 478         return end - buf;
 479 }
 480
 481 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
 482 static struct attribute *glamo_sysfs_entries[] = {
 483         &dev_attr_regs.attr,
 484         NULL
 485 };
 486 static struct attribute_group glamo_attr_group = {
 487         .name   = NULL,
 488         .attrs  = glamo_sysfs_entries,
 489 };
 490
 491
 492
 493 /***********************************************************************
 494  * 'engine' support
 495  ***********************************************************************/
 496
 497 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
 498 {
 499         switch (engine) {
 500         case GLAMO_ENGINE_LCD:
 501                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 502                                    GLAMO_HOSTBUS2_MMIO_EN_LCD,
 503                                    GLAMO_HOSTBUS2_MMIO_EN_LCD);
 504                 __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
 505                             GLAMO_CLOCK_LCD_EN_M5CLK |
 506                             GLAMO_CLOCK_LCD_EN_DHCLK |
 507                             GLAMO_CLOCK_LCD_EN_DMCLK |
 508                             GLAMO_CLOCK_LCD_EN_DCLK |
 509                             GLAMO_CLOCK_LCD_DG_M5CLK |
 510                             GLAMO_CLOCK_LCD_DG_DMCLK);
 511                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 512                             GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
 513                             GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
 514                             GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
 515                 break;
 516         case GLAMO_ENGINE_MMC:
 517                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 518                                    GLAMO_HOSTBUS2_MMIO_EN_MMC,
 519                                    GLAMO_HOSTBUS2_MMIO_EN_MMC);
 520                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
 521                                    GLAMO_CLOCK_MMC_EN_M9CLK |
 522                                    GLAMO_CLOCK_MMC_EN_TCLK |
 523                                    GLAMO_CLOCK_MMC_DG_M9CLK |
 524                                    GLAMO_CLOCK_MMC_DG_TCLK, 0xffff);
 525                 /* enable the TCLK divider clk input */
 526                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 527                                                  GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
 528                                                  GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
 529                 break;
 530         case GLAMO_ENGINE_2D:
 531                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 532                                    GLAMO_CLOCK_2D_EN_M7CLK |
 533                                    GLAMO_CLOCK_2D_EN_GCLK |
 534                                    GLAMO_CLOCK_2D_DG_M7CLK |
 535                                    GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
 536                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 537                                    GLAMO_HOSTBUS2_MMIO_EN_2D,
 538                                    GLAMO_HOSTBUS2_MMIO_EN_2D);
 539                 break;
 540         case GLAMO_ENGINE_CMDQ:
 541                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 542                                    GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
 543                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 544                                    GLAMO_HOSTBUS2_MMIO_EN_CQ,
 545                                    GLAMO_HOSTBUS2_MMIO_EN_CQ);
 546                 break;
 547         /* FIXME: Implementation */
 548         default:
 549                 break;
 550         }
 551
 552         glamo->engine_enabled_bitfield |= 1 << engine;
 553
 554         return 0;
 555 }
 556
 557 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
 558 {
 559         int ret;
 560
 561         spin_lock(&glamo->lock);
 562
 563         ret = __glamo_engine_enable(glamo, engine);
 564
 565         spin_unlock(&glamo->lock);
 566
 567         return ret;
 568 }
 569 EXPORT_SYMBOL_GPL(glamo_engine_enable);
 570
 571 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
 572 {
 573         switch (engine) {
 574         case GLAMO_ENGINE_LCD:
 575                 /* remove pixel clock to LCM */
 576                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
 577                             GLAMO_CLOCK_LCD_EN_DCLK, 0);
 578                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
 579                             GLAMO_CLOCK_LCD_EN_DHCLK |
 580                             GLAMO_CLOCK_LCD_EN_DMCLK, 0);
 581                 /* kill memory clock */
 582                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
 583                             GLAMO_CLOCK_LCD_EN_M5CLK, 0);
 584                 /* stop dividing the clocks */
 585                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 586                             GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
 587                             GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
 588                             GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
 589                 break;
 590
 591         case GLAMO_ENGINE_MMC:
 592 //              __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
 593 //                                                 GLAMO_CLOCK_MMC_EN_M9CLK |
 594 //                                                 GLAMO_CLOCK_MMC_EN_TCLK |
 595 //                                                 GLAMO_CLOCK_MMC_DG_M9CLK |
 596 //                                                 GLAMO_CLOCK_MMC_DG_TCLK, 0);
 597                 /* disable the TCLK divider clk input */
 598 //              __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 599 //                                      GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
 600
 601         default:
 602                 break;
 603         }
 604
 605         glamo->engine_enabled_bitfield &= ~(1 << engine);
 606
 607         return 0;
 608 }
 609 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
 610 {
 611         int ret;
 612
 613         spin_lock(&glamo->lock);
 614
 615         ret = __glamo_engine_disable(glamo, engine);
 616
 617         spin_unlock(&glamo->lock);
 618
 619         return ret;
 620 }
 621 EXPORT_SYMBOL_GPL(glamo_engine_disable);
 622
 623 static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
 624         [GLAMO_ENGINE_LCD]      = GLAMO_REG_CLOCK_LCD,
 625         [GLAMO_ENGINE_MMC]      = GLAMO_REG_CLOCK_MMC,
 626         [GLAMO_ENGINE_ISP]      = GLAMO_REG_CLOCK_ISP,
 627         [GLAMO_ENGINE_JPEG]     = GLAMO_REG_CLOCK_JPEG,
 628         [GLAMO_ENGINE_3D]       = GLAMO_REG_CLOCK_3D,
 629         [GLAMO_ENGINE_2D]       = GLAMO_REG_CLOCK_2D,
 630         [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
 631         [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
 632 };
 633
 634 void glamo_engine_clkreg_set(struct glamo_core *glamo,
 635                              enum glamo_engine engine,
 636                              u_int16_t mask, u_int16_t val)
 637 {
 638         reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
 639 }
 640 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
 641
 642 u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
 643                                   enum glamo_engine engine)
 644 {
 645         u_int16_t val;
 646
 647         spin_lock(&glamo->lock);
 648         val = __reg_read(glamo, engine_clock_regs[engine]);
 649         spin_unlock(&glamo->lock);
 650
 651         return val;
 652 }
 653 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
 654
 655 struct glamo_script reset_regs[] = {
 656         [GLAMO_ENGINE_LCD] = {
 657                 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
 658         },
 659 #if 0
 660         [GLAMO_ENGINE_HOST] = {
 661                 GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
 662         },
 663         [GLAMO_ENGINE_MEM] = {
 664                 GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
 665         },
 666 #endif
 667         [GLAMO_ENGINE_MMC] = {
 668                 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
 669         },
 670         [GLAMO_ENGINE_2D] = {
 671                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
 672         },
 673         [GLAMO_ENGINE_JPEG] = {
 674                 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
 675         },
 676 };
 677
 678 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
 679 {
 680         struct glamo_script *rst;
 681
 682         if (engine >= ARRAY_SIZE(reset_regs)) {
 683                 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
 684                 return;
 685         }
 686
 687         rst = &reset_regs[engine];
 688
 689         spin_lock(&glamo->lock);
 690         __reg_set_bit(glamo, rst->reg, rst->val);
 691         __reg_clear_bit(glamo, rst->reg, rst->val);
 692         spin_unlock(&glamo->lock);
 693 }
 694 EXPORT_SYMBOL_GPL(glamo_engine_reset);
 695
 696 void glamo_lcm_reset(int level)
 697 {
 698         if (!glamo_handle)
 699                 return;
 700
 701         glamo_gpio_setpin(glamo_handle, GLAMO_GPIO4, level);
 702         glamo_gpio_cfgpin(glamo_handle, GLAMO_GPIO4_OUTPUT);
 703
 704 }
 705 EXPORT_SYMBOL_GPL(glamo_lcm_reset);
 706
 707 enum glamo_pll {
 708         GLAMO_PLL1,
 709         GLAMO_PLL2,
 710 };
 711
 712 static int glamo_pll_rate(struct glamo_core *glamo,
 713                           enum glamo_pll pll)
 714 {
 715         u_int16_t reg;
 716         unsigned int div = 512;
 717         /* FIXME: move osci into platform_data */
 718         unsigned int osci = 32768;
 719
 720         if (osci == 32768)
 721                 div = 1;
 722
 723         switch (pll) {
 724         case GLAMO_PLL1:
 725                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
 726                 break;
 727         case GLAMO_PLL2:
 728                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
 729                 break;
 730         default:
 731                 return -EINVAL;
 732         }
 733         return (osci/div)*reg;
 734 }
 735
 736 int glamo_engine_reclock(struct glamo_core *glamo,
 737                          enum glamo_engine engine,
 738                          int ps)
 739 {
 740         int pll, khz;
 741         u_int16_t reg, mask, val = 0;
 742
 743         if (!ps)
 744                 return 0;
 745
 746         switch (engine) {
 747         case GLAMO_ENGINE_LCD:
 748                 pll = GLAMO_PLL1;
 749                 reg = GLAMO_REG_CLOCK_GEN7;
 750                 mask = 0xff;
 751                 break;
 752         default:
 753                 dev_warn(&glamo->pdev->dev,
 754                          "reclock of engine 0x%x not supported\n", engine);
 755                 return -EINVAL;
 756                 break;
 757         }
 758
 759         pll = glamo_pll_rate(glamo, pll);
 760         khz = 1000000000UL / ps;
 761
 762         if (khz)
 763                 val = (pll / khz) / 1000;
 764
 765         dev_dbg(&glamo->pdev->dev,
 766                         "PLL %d, kHZ %d, div %d\n", pll, khz, val);
 767
 768         if (val) {
 769                 val--;
 770                 reg_set_bit_mask(glamo, reg, mask, val);
 771                 mdelay(5); /* wait some time to stabilize */
 772
 773                 return 0;
 774         } else {
 775                 return -EINVAL;
 776         }
 777 }
 778 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
 779
 780 /***********************************************************************
 781  * script support
 782  ***********************************************************************/
 783
 784 int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
 785                      int len, int may_sleep)
 786 {
 787         int i;
 788
 789         for (i = 0; i < len; i++) {
 790                 struct glamo_script *line = &script[i];
 791
 792                 switch (line->reg) {
 793                 case 0xffff:
 794                         return 0;
 795                 case 0xfffe:
 796                         if (may_sleep)
 797                                 msleep(line->val);
 798                         else
 799                                 mdelay(line->val * 4);
 800                         break;
 801                 case 0xfffd:
 802                         /* spin until PLLs lock */
 803                         while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
 804                                 ;
 805                         break;
 806
 807                 /*
 808                  * couple of people reported artefacts with 2.6.28 changes, this
 809                  * allows reversion to 2.6.24 settings
 810                  */
 811
 812                 case 0x200:
 813                         switch (slow_memory) {
 814                         /* choice 1 is the most conservative */
 815                         case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
 816                                 __reg_write(glamo, script[i].reg, 0xef0);
 817                                 break;
 818                         case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
 819                                 __reg_write(glamo, script[i].reg, 0xea0);
 820                                 break;
 821                         case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
 822                                 __reg_write(glamo, script[i].reg, 0xe50);
 823                                 break;
 824                         case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
 825                                 __reg_write(glamo, script[i].reg, 0xe00);
 826                                 break;
 827
 828                         /* using PLL2 for memory bus increases CPU bandwidth significantly */
 829                         case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
 830                                 __reg_write(glamo, script[i].reg, 0xef3);
 831                                 break;
 832                         case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
 833                                 __reg_write(glamo, script[i].reg, 0xea3);
 834                                 break;
 835                         case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
 836                                 __reg_write(glamo, script[i].reg, 0xe53);
 837                                 break;
 838                         /* default of 0 or >7 is fastest */
 839                         default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
 840                                 __reg_write(glamo, script[i].reg, 0xe03);
 841                                 break;
 842                         }
 843                         break;
 844
 845                 default:
 846                         __reg_write(glamo, script[i].reg, script[i].val);
 847                         break;
 848                 }
 849         }
 850
 851         return 0;
 852 }
 853 EXPORT_SYMBOL(glamo_run_script);
 854
 855 static struct glamo_script glamo_init_script[] = {
 856         { GLAMO_REG_CLOCK_HOST,         0x1000 },
 857                 { 0xfffe, 2 },
 858         { GLAMO_REG_CLOCK_MEMORY,       0x1000 },
 859         { GLAMO_REG_CLOCK_MEMORY,       0x2000 },
 860         { GLAMO_REG_CLOCK_LCD,          0x1000 },
 861         { GLAMO_REG_CLOCK_MMC,          0x1000 },
 862         { GLAMO_REG_CLOCK_ISP,          0x1000 },
 863         { GLAMO_REG_CLOCK_ISP,          0x3000 },
 864         { GLAMO_REG_CLOCK_JPEG,         0x1000 },
 865         { GLAMO_REG_CLOCK_3D,           0x1000 },
 866         { GLAMO_REG_CLOCK_3D,           0x3000 },
 867         { GLAMO_REG_CLOCK_2D,           0x1000 },
 868         { GLAMO_REG_CLOCK_2D,           0x3000 },
 869         { GLAMO_REG_CLOCK_RISC1,        0x1000 },
 870         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
 871         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
 872         { GLAMO_REG_CLOCK_MPROC,        0x1000 /*0x100f*/ },
 873                 { 0xfffe, 2 },
 874         { GLAMO_REG_CLOCK_HOST,         0x0000 },
 875         { GLAMO_REG_CLOCK_MEMORY,       0x0000 },
 876         { GLAMO_REG_CLOCK_LCD,          0x0000 },
 877         { GLAMO_REG_CLOCK_MMC,          0x0000 },
 878 #if 0
 879 /* unused engines must be left in reset to stop MMC block read "blackouts" */
 880         { GLAMO_REG_CLOCK_ISP,          0x0000 },
 881         { GLAMO_REG_CLOCK_ISP,          0x0000 },
 882         { GLAMO_REG_CLOCK_JPEG,         0x0000 },
 883         { GLAMO_REG_CLOCK_3D,           0x0000 },
 884         { GLAMO_REG_CLOCK_3D,           0x0000 },
 885         { GLAMO_REG_CLOCK_2D,           0x0000 },
 886         { GLAMO_REG_CLOCK_2D,           0x0000 },
 887         { GLAMO_REG_CLOCK_RISC1,        0x0000 },
 888         { GLAMO_REG_CLOCK_MPEG,         0x0000 },
 889         { GLAMO_REG_CLOCK_MPEG,         0x0000 },
 890 #endif
 891         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
 892         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
 893         { 0xfffd, 0 },
 894         /*
 895          * b9 of this register MUST be zero to get any interrupts on INT#
 896          * the other set bits enable all the engine interrupt sources
 897          */
 898         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
 899         { GLAMO_REG_CLOCK_GEN6,         0x2000 },
 900         { GLAMO_REG_CLOCK_GEN7,         0x0101 },
 901         { GLAMO_REG_CLOCK_GEN8,         0x0100 },
 902         { GLAMO_REG_CLOCK_HOST,         0x000d },
 903         /*
 904          * b7..b4 = 0 = no wait states on read or write
 905          * b0 = 1 select PLL2 for Host interface, b1 = enable it
 906          */
 907         { 0x200,        0x0e03 /* this is replaced by script parser */ },
 908         { 0x202,        0x07ff },
 909         { 0x212,        0x0000 },
 910         { 0x214,        0x4000 },
 911         { 0x216,        0xf00e },
 912
 913         /* S-Media recommended "set tiling mode to 512 mode for memory access
 914          * more efficiency when 640x480" */
 915         { GLAMO_REG_MEM_TYPE,           0x0c74 }, /* 8MB, 16 word pg wr+rd */
 916         { GLAMO_REG_MEM_GEN,            0xafaf }, /* 63 grants min + max */
 917
 918         { GLAMO_REGOFS_HOSTBUS + 2,     0xffff }, /* enable  on MMIO*/
 919
 920         { GLAMO_REG_MEM_TIMING1,        0x0108 },
 921         { GLAMO_REG_MEM_TIMING2,        0x0010 }, /* Taa = 3 MCLK */
 922         { GLAMO_REG_MEM_TIMING3,        0x0000 },
 923         { GLAMO_REG_MEM_TIMING4,        0x0000 }, /* CE1# delay fall/rise */
 924         { GLAMO_REG_MEM_TIMING5,        0x0000 }, /* UB# LB# */
 925         { GLAMO_REG_MEM_TIMING6,        0x0000 }, /* OE# */
 926         { GLAMO_REG_MEM_TIMING7,        0x0000 }, /* WE# */
 927         { GLAMO_REG_MEM_TIMING8,        0x1002 }, /* MCLK delay, was 0x1000 */
 928         { GLAMO_REG_MEM_TIMING9,        0x6006 },
 929         { GLAMO_REG_MEM_TIMING10,       0x00ff },
 930         { GLAMO_REG_MEM_TIMING11,       0x0001 },
 931         { GLAMO_REG_MEM_POWER1,         0x0020 },
 932         { GLAMO_REG_MEM_POWER2,         0x0000 },
 933         { GLAMO_REG_MEM_DRAM1,          0x0000 },
 934                 { 0xfffe, 1 },
 935         { GLAMO_REG_MEM_DRAM1,          0xc100 },
 936                 { 0xfffe, 1 },
 937         { GLAMO_REG_MEM_DRAM1,          0xe100 },
 938         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
 939         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
 940         { GLAMO_REG_GPIO_GEN1,          0x000f },
 941         { GLAMO_REG_GPIO_GEN2,          0x111e },
 942         { GLAMO_REG_GPIO_GEN3,          0xccc3 },
 943         { GLAMO_REG_GPIO_GEN4,          0x111e },
 944         { GLAMO_REG_GPIO_GEN5,          0x000f },
 945 };
 946 #if 0
 947 static struct glamo_script glamo_resume_script[] = {
 948
 949         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
 950         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
 951         { GLAMO_REG_DFT_GEN6, 1 },
 952                 { 0xfffe, 100 },
 953                 { 0xfffd, 0 },
 954         { 0x200,        0x0e03 },
 955
 956         /*
 957          * b9 of this register MUST be zero to get any interrupts on INT#
 958          * the other set bits enable all the engine interrupt sources
 959          */
 960         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
 961         { GLAMO_REG_CLOCK_HOST,         0x0018 },
 962         { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
 963
 964         { GLAMO_REG_MEM_DRAM1,          0x0000 },
 965                 { 0xfffe, 1 },
 966         { GLAMO_REG_MEM_DRAM1,          0xc100 },
 967                 { 0xfffe, 1 },
 968         { GLAMO_REG_MEM_DRAM1,          0xe100 },
 969         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
 970         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
 971 };
 972 #endif
 973
 974 enum glamo_power {
 975         GLAMO_POWER_ON,
 976         GLAMO_POWER_SUSPEND,
 977 };
 978
 979 static void glamo_power(struct glamo_core *glamo,
 980                         enum glamo_power new_state)
 981 {
 982         int n;
 983         unsigned long flags;
 984
 985         spin_lock_irqsave(&glamo->lock, flags);
 986
 987         dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
 988
 989         /*
 990 Power management
 991 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
 992 {
 993     { REG_GEN_DFT6,     REG_BIT_ALL,    REG_DATA(1u << 0)           },
 994     { REG_GEN_PLL3,     0u,             REG_DATA(1u << 13)          },
 995     { REG_GEN_MEM_CLK,  REG_BIT_ALL,    REG_BIT_EN_MOCACLK          },
 996     { REG_MEM_DRAM2,    0u,             REG_BIT_EN_DEEP_POWER_DOWN  },
 997     { REG_MEM_DRAM1,    0u,             REG_BIT_SELF_REFRESH        }
 998 };
 999
1000 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
1001 {
1002     { REG_MEM_DRAM1,    REG_BIT_ALL,    REG_BIT_SELF_REFRESH    },
1003     { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK      },
1004     { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)      },
1005     { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)       }
1006 };
1007
1008 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
1009 {
1010     { REG_MEM_DRAM2,    REG_BIT_ALL,    REG_BIT_EN_DEEP_POWER_DOWN  },
1011     { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK          },
1012     { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)          },
1013     { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)           }
1014 };
1015 */
1016
1017         switch (new_state) {
1018         case GLAMO_POWER_ON:
1019
1020                 /*
1021                  * glamo state on resume is nondeterministic in some
1022                  * fundamental way, it has also been observed that the
1023                  * Glamo reset pin can get asserted by, eg, touching it with
1024                  * a scope probe.  So the only answer is to roll with it and
1025                  * force an external reset on the Glamo during resume.
1026                  */
1027
1028                 (glamo->pdata->glamo_external_reset)(0);
1029                 udelay(10);
1030                 (glamo->pdata->glamo_external_reset)(1);
1031                 mdelay(5);
1032
1033                 glamo_run_script(glamo, glamo_init_script,
1034                          ARRAY_SIZE(glamo_init_script), 0);
1035
1036                 break;
1037
1038         case GLAMO_POWER_SUSPEND:
1039
1040                 /* nuke interrupts */
1041                 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
1042
1043                 /* stash a copy of which engines were running */
1044                 glamo->engine_enabled_bitfield_suspend =
1045                                                  glamo->engine_enabled_bitfield;
1046
1047                 /* take down each engine before we kill mem and pll */
1048                 for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
1049                         if (glamo->engine_enabled_bitfield & (1 << n))
1050                                 __glamo_engine_disable(glamo, n);
1051
1052                 /* enable self-refresh */
1053
1054                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1055                                         GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1056                                         GLAMO_MEM_DRAM1_EN_GATE_CKE |
1057                                         GLAMO_MEM_DRAM1_SELF_REFRESH |
1058                                         GLAMO_MEM_REFRESH_COUNT);
1059                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1060                                         GLAMO_MEM_DRAM1_EN_MODEREG_SET |
1061                                         GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1062                                         GLAMO_MEM_DRAM1_EN_GATE_CKE |
1063                                         GLAMO_MEM_DRAM1_SELF_REFRESH |
1064                                         GLAMO_MEM_REFRESH_COUNT);
1065
1066                 /* force RAM into deep powerdown */
1067
1068                 __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
1069                                         GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
1070                                         (7 << 6) | /* tRC */
1071                                         (1 << 4) | /* tRP */
1072                                         (1 << 2) | /* tRCD */
1073                                         2); /* CAS latency */
1074
1075                 /* disable clocks to memory */
1076                 __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
1077
1078                 /* all dividers from OSCI */
1079                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
1080
1081                 /* PLL2 into bypass */
1082                 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
1083
1084                 __reg_write(glamo, 0x200, 0x0e00);
1085
1086
1087                 /* kill PLLS 1 then 2 */
1088                 __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1089                 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1090
1091                 break;
1092         }
1093
1094         spin_unlock_irqrestore(&glamo->lock, flags);
1095 }
1096
1097 #if 0
1098 #define MEMDETECT_RETRY 6
1099 static unsigned int detect_memsize(struct glamo_core *glamo)
1100 {
1101         int i;
1102
1103         /*static const u_int16_t pattern[] = {
1104                 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1105                 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1106                 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1107                 0x7777, 0x2a2a, 0x8888, 0x1a1a
1108         }; */
1109
1110         for (i = 0; i < MEMDETECT_RETRY; i++) {
1111                 switch (glamo->type) {
1112                 case 3600:
1113                         __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
1114                         __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1115                         break;
1116                 case 3650:
1117                         switch (glamo->revision) {
1118                         case GLAMO_CORE_REV_A0:
1119                                 if (i & 1)
1120                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1121                                                     0x097a);
1122                                 else
1123                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1124                                                     0x0173);
1125
1126                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1127                                 msleep(1);
1128                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1129                                 break;
1130                         default:
1131                                 if (i & 1)
1132                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1133                                                     0x0972);
1134                                 else
1135                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1136                                                     0x0872);
1137
1138                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1139                                 msleep(1);
1140                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
1141                                 break;
1142                         }
1143                         break;
1144                 case 3700:
1145                         /* FIXME */
1146                 default:
1147                         break;
1148                 }
1149
1150 #if 0
1151                 /* FIXME: finish implementation */
1152                 for (j = 0; j < 8; j++) {
1153                         __
1154 #endif
1155         }
1156
1157         return 0;
1158 }
1159 #endif
1160
1161 /* Find out if we can support this version of the Glamo chip */
1162 static int glamo_supported(struct glamo_core *glamo)
1163 {
1164         u_int16_t dev_id, rev_id; /*, memsize; */
1165
1166         dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
1167         rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
1168
1169         switch (dev_id) {
1170         case 0x3650:
1171                 switch (rev_id) {
1172                 case GLAMO_CORE_REV_A2:
1173                         break;
1174                 case GLAMO_CORE_REV_A0:
1175                 case GLAMO_CORE_REV_A1:
1176                 case GLAMO_CORE_REV_A3:
1177                         dev_warn(&glamo->pdev->dev, "untested core revision "
1178                                  "%04x, your mileage may vary\n", rev_id);
1179                         break;
1180                 default:
1181                         dev_warn(&glamo->pdev->dev, "unknown glamo revision "
1182                                  "%04x, your mileage may vary\n", rev_id);
1183                         /* maybe should abort ? */
1184                 }
1185                 break;
1186         case 0x3600:
1187         case 0x3700:
1188         default:
1189                 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
1190                         dev_id);
1191                 return 0;
1192         }
1193
1194         dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
1195                  "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
1196                  glamo_pll_rate(glamo, GLAMO_PLL1),
1197                  glamo_pll_rate(glamo, GLAMO_PLL2));
1198
1199         return 1;
1200 }
1201
1202 static int __init glamo_probe(struct platform_device *pdev)
1203 {
1204         int rc = 0, irq;
1205         struct glamo_core *glamo;
1206         struct platform_device *glamo_mmc_dev;
1207
1208         if (glamo_handle) {
1209                 dev_err(&pdev->dev,
1210                         "This driver supports only one instance\n");
1211                 return -EBUSY;
1212         }
1213
1214         glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
1215         if (!glamo)
1216                 return -ENOMEM;
1217
1218         spin_lock_init(&glamo->lock);
1219         glamo_handle = glamo;
1220         glamo->pdev = pdev;
1221         glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1222         glamo->irq = platform_get_irq(pdev, 0);
1223         glamo->pdata = pdev->dev.platform_data;
1224         if (!glamo->mem || !glamo->pdata) {
1225                 dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
1226                 rc = -ENOENT;
1227                 goto bail_free;
1228         }
1229
1230         /* register a number of sibling devices whoise IOMEM resources
1231          * are siblings of pdev's IOMEM resource */
1232 #if 0
1233         glamo_core_dev.dev.parent = &pdev.dev;
1234         mangle_mem_resources(glamo_core_dev.resources,
1235                              glamo_core_dev.num_resources, glamo->mem);
1236         glamo_core_dev.resources[1].start = glamo->irq;
1237         glamo_core_dev.resources[1].end = glamo->irq;
1238         platform_device_register(&glamo_core_dev);
1239 #endif
1240         /* only remap the generic, hostbus and memory controller registers */
1241         glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1242         if (!glamo->base) {
1243                 dev_err(&pdev->dev, "failed to ioremap() memory region\n");
1244                 goto bail_free;
1245         }
1246
1247         platform_set_drvdata(pdev, glamo);
1248
1249         (glamo->pdata->glamo_external_reset)(0);
1250         udelay(10);
1251         (glamo->pdata->glamo_external_reset)(1);
1252         mdelay(10);
1253
1254         /*
1255          * finally set the mfd interrupts up
1256          * can't do them earlier or sibling probes blow up
1257          */
1258
1259         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1260                 set_irq_chip(irq, &glamo_irq_chip);
1261                 set_irq_handler(irq, handle_level_irq);
1262                 set_irq_flags(irq, IRQF_VALID);
1263         }
1264
1265         if (glamo->pdata->glamo_irq_is_wired &&
1266             !glamo->pdata->glamo_irq_is_wired()) {
1267                 set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
1268                 set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
1269                 dev_info(&pdev->dev, "Glamo interrupt registered\n");
1270                 glamo->irq_works = 1;
1271         } else {
1272                 dev_err(&pdev->dev, "Glamo interrupt not used\n");
1273                 glamo->irq_works = 0;
1274         }
1275
1276
1277         /* confirm it isn't insane version */
1278         if (!glamo_supported(glamo)) {
1279                 dev_err(&pdev->dev, "This Glamo is not supported\n");
1280                 goto bail_irq;
1281         }
1282
1283         /* sysfs */
1284         rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
1285         if (rc < 0) {
1286                 dev_err(&pdev->dev, "cannot create sysfs group\n");
1287                 goto bail_irq;
1288         }
1289
1290         /* init the chip with canned register set */
1291
1292         dev_dbg(&glamo->pdev->dev, "running init script\n");
1293         glamo_run_script(glamo, glamo_init_script,
1294                          ARRAY_SIZE(glamo_init_script), 1);
1295
1296         dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1297                  glamo_pll_rate(glamo, GLAMO_PLL1),
1298                  glamo_pll_rate(glamo, GLAMO_PLL2));
1299
1300         /* bring MCI specific stuff over from our MFD platform data */
1301         glamo_mci_def_pdata.glamo_can_set_mci_power =
1302                                         glamo->pdata->glamo_can_set_mci_power;
1303         glamo_mci_def_pdata.glamo_mci_use_slow =
1304                                         glamo->pdata->glamo_mci_use_slow;
1305         glamo_mci_def_pdata.glamo_irq_is_wired =
1306                                         glamo->pdata->glamo_irq_is_wired;
1307
1308         /* start creating the siblings */
1309
1310         glamo_2d_dev.dev.parent = &pdev->dev;
1311         mangle_mem_resources(glamo_2d_dev.resource,
1312                              glamo_2d_dev.num_resources, glamo->mem);
1313         platform_device_register(&glamo_2d_dev);
1314
1315         glamo_3d_dev.dev.parent = &pdev->dev;
1316         mangle_mem_resources(glamo_3d_dev.resource,
1317                              glamo_3d_dev.num_resources, glamo->mem);
1318         platform_device_register(&glamo_3d_dev);
1319
1320         glamo_jpeg_dev.dev.parent = &pdev->dev;
1321         mangle_mem_resources(glamo_jpeg_dev.resource,
1322                              glamo_jpeg_dev.num_resources, glamo->mem);
1323         platform_device_register(&glamo_jpeg_dev);
1324
1325         glamo_mpeg_dev.dev.parent = &pdev->dev;
1326         mangle_mem_resources(glamo_mpeg_dev.resource,
1327                              glamo_mpeg_dev.num_resources, glamo->mem);
1328         platform_device_register(&glamo_mpeg_dev);
1329
1330         glamo->pdata->glamo = glamo;
1331         glamo_fb_dev.dev.parent = &pdev->dev;
1332         glamo_fb_dev.dev.platform_data = glamo->pdata;
1333         mangle_mem_resources(glamo_fb_dev.resource,
1334                              glamo_fb_dev.num_resources, glamo->mem);
1335         platform_device_register(&glamo_fb_dev);
1336
1337         glamo->pdata->spigpio_info->glamo = glamo;
1338         glamo_spigpio_dev.dev.parent = &pdev->dev;
1339         glamo_spigpio_dev.dev.platform_data = glamo->pdata->spigpio_info;
1340         platform_device_register(&glamo_spigpio_dev);
1341
1342         glamo_mmc_dev = glamo->pdata->mmc_dev;
1343         glamo_mmc_dev->name = "glamo-mci";
1344         glamo_mmc_dev->dev.parent = &pdev->dev;
1345         glamo_mmc_dev->resource = glamo_mmc_resources;
1346         glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
1347
1348         /* we need it later to give to the engine enable and disable */
1349         glamo_mci_def_pdata.pglamo = glamo;
1350         mangle_mem_resources(glamo_mmc_dev->resource,
1351                              glamo_mmc_dev->num_resources, glamo->mem);
1352         platform_device_register(glamo_mmc_dev);
1353
1354         /* only request the generic, hostbus and memory controller MMIO */
1355         glamo->mem = request_mem_region(glamo->mem->start,
1356                                         GLAMO_REGOFS_VIDCAP, "glamo-core");
1357         if (!glamo->mem) {
1358                 dev_err(&pdev->dev, "failed to request memory region\n");
1359                 goto bail_irq;
1360         }
1361
1362         return 0;
1363
1364 bail_irq:
1365         disable_irq(glamo->irq);
1366         set_irq_chained_handler(glamo->irq, NULL);
1367
1368         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1369                 set_irq_flags(irq, 0);
1370                 set_irq_chip(irq, NULL);
1371         }
1372
1373         iounmap(glamo->base);
1374 bail_free:
1375         platform_set_drvdata(pdev, NULL);
1376         glamo_handle = NULL;
1377         kfree(glamo);
1378
1379         return rc;
1380 }
1381
1382 static int glamo_remove(struct platform_device *pdev)
1383 {
1384         struct glamo_core *glamo = platform_get_drvdata(pdev);
1385         int irq;
1386
1387         disable_irq(glamo->irq);
1388         set_irq_chained_handler(glamo->irq, NULL);
1389
1390         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1391                 set_irq_flags(irq, 0);
1392                 set_irq_chip(irq, NULL);
1393         }
1394
1395         platform_set_drvdata(pdev, NULL);
1396         platform_device_unregister(&glamo_fb_dev);
1397         platform_device_unregister(glamo->pdata->mmc_dev);
1398         iounmap(glamo->base);
1399         release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
1400         glamo_handle = NULL;
1401         kfree(glamo);
1402
1403         return 0;
1404 }
1405
1406 #ifdef CONFIG_PM
1407
1408 static int glamo_suspend(struct platform_device *pdev, pm_message_t state)
1409 {
1410         glamo_handle->suspending = 1;
1411         glamo_power(glamo_handle, GLAMO_POWER_SUSPEND);
1412
1413         return 0;
1414 }
1415
1416 static int glamo_resume(struct platform_device *pdev)
1417 {
1418         glamo_power(glamo_handle, GLAMO_POWER_ON);
1419         glamo_handle->suspending = 0;
1420
1421         return 0;
1422 }
1423
1424 #else
1425 #define glamo_suspend NULL
1426 #define glamo_resume  NULL
1427 #endif
1428
1429 static struct platform_driver glamo_driver = {
1430         .probe          = glamo_probe,
1431         .remove         = glamo_remove,
1432         .suspend        = glamo_suspend,
1433         .resume = glamo_resume,
1434         .driver         = {
1435                 .name   = "glamo3362",
1436                 .owner  = THIS_MODULE,
1437         },
1438 };
1439
1440 static int __devinit glamo_init(void)
1441 {
1442         return platform_driver_register(&glamo_driver);
1443 }
1444
1445 static void __exit glamo_cleanup(void)
1446 {
1447         platform_driver_unregister(&glamo_driver);
1448 }
1449
1450 module_init(glamo_init);
1451 module_exit(glamo_cleanup);
1452
1453 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1454 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1455 MODULE_LICENSE("GPL");