target/linux/s3c24xx/files-2.6.30/drivers/mfd/glamo/glamo-core.c

   1 /* Smedia Glamo 336x/337x driver
   2  *
   3  * (C) 2007 by Openmoko, Inc.
   4  * Author: Harald Welte <laforge@openmoko.org>
   5  * All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/init.h>
  33 #include <linux/irq.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/workqueue.h>
  36 #include <linux/wait.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/kernel_stat.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/glamofb.h>
  41 #include <linux/mmc/mmc.h>
  42 #include <linux/mmc/host.h>
  43
  44 #include <asm/io.h>
  45 #include <asm/uaccess.h>
  46 #include <asm/div64.h>
  47
  48 //#include <mach/regs-irq.h>
  49
  50 #ifdef CONFIG_PM
  51 #include <linux/pm.h>
  52 #endif
  53
  54 #include "glamo-regs.h"
  55 #include "glamo-core.h"
  56
  57 #define RESSIZE(ressource) (((ressource)->end - (ressource)->start)+1)
  58
  59 #define GLAMO_MEM_REFRESH_COUNT 0x100
  60
  61
  62 /*
  63  * Glamo internal settings
  64  *
  65  * We run the memory interface from the faster PLLB on 2.6.28 kernels and
  66  * above.  Couple of GTA02 users report trouble with memory bus when they
  67  * upgraded from 2.6.24.  So this parameter allows reversion to 2.6.24
  68  * scheme if their Glamo chip needs it.
  69  *
  70  * you can override the faster default on kernel commandline using
  71  *
  72  *   glamo3362.slow_memory=1
  73  *
  74  * for example
  75  */
  76
  77 static int slow_memory = 0;
  78 module_param(slow_memory, int, 0644);
  79
  80 struct reg_range {
  81         int start;
  82         int count;
  83         char *name;
  84         char dump;
  85 };
  86 struct reg_range reg_range[] = {
  87         { 0x0000, 0x76,         "General",      1 },
  88         { 0x0200, 0x16,         "Host Bus",     1 },
  89         { 0x0300, 0x38,         "Memory",       1 },
  90 /*      { 0x0400, 0x100,        "Sensor",       0 }, */
  91 /*              { 0x0500, 0x300,        "ISP",          0 }, */
  92 /*              { 0x0800, 0x400,        "JPEG",         0 }, */
  93 /*              { 0x0c00, 0xcc,         "MPEG",         0 }, */
  94         { 0x1100, 0xb2,         "LCD 1",        1 },
  95         { 0x1200, 0x64,         "LCD 2",        1 },
  96         { 0x1400, 0x40,         "MMC",          1 },
  97 /*              { 0x1500, 0x080,        "MPU 0",        0 },
  98         { 0x1580, 0x080,        "MPU 1",        0 },
  99         { 0x1600, 0x080,        "Cmd Queue",    0 },
 100         { 0x1680, 0x080,        "RISC CPU",     0 },
 101         { 0x1700, 0x400,        "2D Unit",      0 },
 102         { 0x1b00, 0x900,        "3D Unit",      0 }, */
 103 };
 104
 105 static struct glamo_core *glamo_handle;
 106
 107 static inline void __reg_write(struct glamo_core *glamo,
 108                                 u_int16_t reg, u_int16_t val)
 109 {
 110         writew(val, glamo->base + reg);
 111 }
 112
 113 static inline u_int16_t __reg_read(struct glamo_core *glamo,
 114                                    u_int16_t reg)
 115 {
 116         return readw(glamo->base + reg);
 117 }
 118
 119 static void __reg_set_bit_mask(struct glamo_core *glamo,
 120                                 u_int16_t reg, u_int16_t mask,
 121                                 u_int16_t val)
 122 {
 123         u_int16_t tmp;
 124
 125         val &= mask;
 126
 127         tmp = __reg_read(glamo, reg);
 128         tmp &= ~mask;
 129         tmp |= val;
 130         __reg_write(glamo, reg, tmp);
 131 }
 132
 133 static void reg_set_bit_mask(struct glamo_core *glamo,
 134                                 u_int16_t reg, u_int16_t mask,
 135                                 u_int16_t val)
 136 {
 137         spin_lock(&glamo->lock);
 138         __reg_set_bit_mask(glamo, reg, mask, val);
 139         spin_unlock(&glamo->lock);
 140 }
 141
 142 static inline void __reg_set_bit(struct glamo_core *glamo,
 143                                  u_int16_t reg, u_int16_t bit)
 144 {
 145         __reg_set_bit_mask(glamo, reg, bit, 0xffff);
 146 }
 147
 148 static inline void __reg_clear_bit(struct glamo_core *glamo,
 149                                    u_int16_t reg, u_int16_t bit)
 150 {
 151         __reg_set_bit_mask(glamo, reg, bit, 0);
 152 }
 153
 154 static inline void glamo_vmem_write(struct glamo_core *glamo, u_int32_t addr,
 155                                     u_int16_t *src, int len)
 156 {
 157         if (addr & 0x0001 || (unsigned long)src & 0x0001 || len & 0x0001) {
 158                 dev_err(&glamo->pdev->dev, "unaligned write(0x%08x, 0x%p, "
 159                         "0x%x)!!\n", addr, src, len);
 160         }
 161
 162 }
 163
 164 static inline void glamo_vmem_read(struct glamo_core *glamo, u_int16_t *buf,
 165                                    u_int32_t addr, int len)
 166 {
 167         if (addr & 0x0001 || (unsigned long) buf & 0x0001 || len & 0x0001) {
 168                 dev_err(&glamo->pdev->dev, "unaligned read(0x%p, 0x08%x, "
 169                         "0x%x)!!\n", buf, addr, len);
 170         }
 171
 172
 173 }
 174
 175 /***********************************************************************
 176  * resources of sibling devices
 177  ***********************************************************************/
 178
 179 #if 0
 180 static struct resource glamo_core_resources[] = {
 181         {
 182                 .start  = GLAMO_REGOFS_GENERIC,
 183                 .end    = GLAMO_REGOFS_GENERIC + 0x400,
 184                 .flags  = IORESOURCE_MEM,
 185         }, {
 186                 .start  = 0,
 187                 .end    = 0,
 188                 .flags  = IORESOURCE_IRQ,
 189         },
 190 };
 191
 192 static struct platform_device glamo_core_dev = {
 193         .name           = "glamo-core",
 194         .resource       = &glamo_core_resources,
 195         .num_resources  = ARRAY_SIZE(glamo_core_resources),
 196 };
 197 #endif
 198
 199 static struct resource glamo_jpeg_resources[] = {
 200         {
 201                 .start  = GLAMO_REGOFS_JPEG,
 202                 .end    = GLAMO_REGOFS_MPEG - 1,
 203                 .flags  = IORESOURCE_MEM,
 204         }, {
 205                 .start  = IRQ_GLAMO_JPEG,
 206                 .end    = IRQ_GLAMO_JPEG,
 207                 .flags  = IORESOURCE_IRQ,
 208         },
 209 };
 210
 211 static struct platform_device glamo_jpeg_dev = {
 212         .name           = "glamo-jpeg",
 213         .resource       = glamo_jpeg_resources,
 214         .num_resources  = ARRAY_SIZE(glamo_jpeg_resources),
 215 };
 216
 217 static struct resource glamo_mpeg_resources[] = {
 218         {
 219                 .start  = GLAMO_REGOFS_MPEG,
 220                 .end    = GLAMO_REGOFS_LCD - 1,
 221                 .flags  = IORESOURCE_MEM,
 222         }, {
 223                 .start  = IRQ_GLAMO_MPEG,
 224                 .end    = IRQ_GLAMO_MPEG,
 225                 .flags  = IORESOURCE_IRQ,
 226         },
 227 };
 228
 229 static struct platform_device glamo_mpeg_dev = {
 230         .name           = "glamo-mpeg",
 231         .resource       = glamo_mpeg_resources,
 232         .num_resources  = ARRAY_SIZE(glamo_mpeg_resources),
 233 };
 234
 235 static struct resource glamo_2d_resources[] = {
 236         {
 237                 .start  = GLAMO_REGOFS_2D,
 238                 .end    = GLAMO_REGOFS_3D - 1,
 239                 .flags  = IORESOURCE_MEM,
 240         }, {
 241                 .start  = IRQ_GLAMO_2D,
 242                 .end    = IRQ_GLAMO_2D,
 243                 .flags  = IORESOURCE_IRQ,
 244         },
 245 };
 246
 247 static struct platform_device glamo_2d_dev = {
 248         .name           = "glamo-2d",
 249         .resource       = glamo_2d_resources,
 250         .num_resources  = ARRAY_SIZE(glamo_2d_resources),
 251 };
 252
 253 static struct resource glamo_3d_resources[] = {
 254         {
 255                 .start  = GLAMO_REGOFS_3D,
 256                 .end    = GLAMO_REGOFS_END - 1,
 257                 .flags  = IORESOURCE_MEM,
 258         },
 259 };
 260
 261 static struct platform_device glamo_3d_dev = {
 262         .name           = "glamo-3d",
 263         .resource       = glamo_3d_resources,
 264         .num_resources  = ARRAY_SIZE(glamo_3d_resources),
 265 };
 266
 267 static struct platform_device glamo_spigpio_dev = {
 268         .name           = "glamo-spi-gpio",
 269 };
 270
 271 static struct resource glamo_fb_resources[] = {
 272         /* FIXME: those need to be incremented by parent base */
 273         {
 274                 .name   = "glamo-fb-regs",
 275                 .start  = GLAMO_REGOFS_LCD,
 276                 .end    = GLAMO_REGOFS_MMC - 1,
 277                 .flags  = IORESOURCE_MEM,
 278         }, {
 279                 .name   = "glamo-fb-mem",
 280                 .start  = GLAMO_OFFSET_FB,
 281                 .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE - 1,
 282                 .flags  = IORESOURCE_MEM,
 283         },
 284 };
 285
 286 static struct platform_device glamo_fb_dev = {
 287         .name           = "glamo-fb",
 288         .resource       = glamo_fb_resources,
 289         .num_resources  = ARRAY_SIZE(glamo_fb_resources),
 290 };
 291
 292 static struct resource glamo_mmc_resources[] = {
 293         {
 294                 /* FIXME: those need to be incremented by parent base */
 295                 .start  = GLAMO_REGOFS_MMC,
 296                 .end    = GLAMO_REGOFS_MPROC0 - 1,
 297                 .flags  = IORESOURCE_MEM
 298         }, {
 299                 .start  = IRQ_GLAMO_MMC,
 300                 .end    = IRQ_GLAMO_MMC,
 301                 .flags  = IORESOURCE_IRQ,
 302         }, { /* our data buffer for MMC transfers */
 303                 .start  = GLAMO_OFFSET_FB + GLAMO_FB_SIZE,
 304                 .end    = GLAMO_OFFSET_FB + GLAMO_FB_SIZE +
 305                                   GLAMO_MMC_BUFFER_SIZE - 1,
 306                 .flags  = IORESOURCE_MEM
 307         },
 308 };
 309
 310 struct glamo_mci_pdata glamo_mci_def_pdata = {
 311         .gpio_detect            = 0,
 312         .glamo_can_set_mci_power        = NULL, /* filled in from MFD platform data */
 313         .ocr_avail      = MMC_VDD_20_21 |
 314                           MMC_VDD_21_22 |
 315                           MMC_VDD_22_23 |
 316                           MMC_VDD_23_24 |
 317                           MMC_VDD_24_25 |
 318                           MMC_VDD_25_26 |
 319                           MMC_VDD_26_27 |
 320                           MMC_VDD_27_28 |
 321                           MMC_VDD_28_29 |
 322                           MMC_VDD_29_30 |
 323                           MMC_VDD_30_31 |
 324                           MMC_VDD_32_33,
 325         .glamo_irq_is_wired     = NULL, /* filled in from MFD platform data */
 326         .mci_suspending = NULL, /* filled in from MFD platform data */
 327         .mci_all_dependencies_resumed = NULL, /* filled in from MFD platform data */
 328 };
 329 EXPORT_SYMBOL_GPL(glamo_mci_def_pdata);
 330
 331
 332
 333 static void mangle_mem_resources(struct resource *res, int num_res,
 334                                  struct resource *parent)
 335 {
 336         int i;
 337
 338         for (i = 0; i < num_res; i++) {
 339                 if (res[i].flags != IORESOURCE_MEM)
 340                         continue;
 341                 res[i].start += parent->start;
 342                 res[i].end += parent->start;
 343                 res[i].parent = parent;
 344         }
 345 }
 346
 347 /***********************************************************************
 348  * IRQ demultiplexer
 349  ***********************************************************************/
 350 #define irq2glamo(x)    (x - IRQ_GLAMO(0))
 351
 352 static void glamo_ack_irq(unsigned int irq)
 353 {
 354         /* clear interrupt source */
 355         __reg_write(glamo_handle, GLAMO_REG_IRQ_CLEAR,
 356                     1 << irq2glamo(irq));
 357 }
 358
 359 static void glamo_mask_irq(unsigned int irq)
 360 {
 361         u_int16_t tmp;
 362
 363         /* clear bit in enable register */
 364         tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
 365         tmp &= ~(1 << irq2glamo(irq));
 366         __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
 367 }
 368
 369 static void glamo_unmask_irq(unsigned int irq)
 370 {
 371         u_int16_t tmp;
 372
 373         /* set bit in enable register */
 374         tmp = __reg_read(glamo_handle, GLAMO_REG_IRQ_ENABLE);
 375         tmp |= (1 << irq2glamo(irq));
 376         __reg_write(glamo_handle, GLAMO_REG_IRQ_ENABLE, tmp);
 377 }
 378
 379 static struct irq_chip glamo_irq_chip = {
 380         .ack    = glamo_ack_irq,
 381         .mask   = glamo_mask_irq,
 382         .unmask = glamo_unmask_irq,
 383 };
 384
 385 static void glamo_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
 386 {
 387         desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
 388
 389         if (unlikely(desc->status & IRQ_INPROGRESS)) {
 390                 desc->status |= (IRQ_PENDING | IRQ_MASKED);
 391                 desc->chip->mask(irq);
 392                 desc->chip->ack(irq);
 393                 return;
 394         }
 395     kstat_incr_irqs_this_cpu(irq, desc);
 396
 397         desc->chip->ack(irq);
 398         desc->status |= IRQ_INPROGRESS;
 399
 400         do {
 401                 u_int16_t irqstatus;
 402                 int i;
 403
 404                 if (unlikely((desc->status &
 405                                 (IRQ_PENDING | IRQ_MASKED | IRQ_DISABLED)) ==
 406                                 (IRQ_PENDING | IRQ_MASKED))) {
 407                         /* dealing with pending IRQ, unmasking */
 408                         desc->chip->unmask(irq);
 409                         desc->status &= ~IRQ_MASKED;
 410                 }
 411
 412                 desc->status &= ~IRQ_PENDING;
 413
 414                 /* read IRQ status register */
 415                 irqstatus = __reg_read(glamo_handle, GLAMO_REG_IRQ_STATUS);
 416                 for (i = 0; i < 9; i++)
 417                         if (irqstatus & (1 << i))
 418                                 desc_handle_irq(IRQ_GLAMO(i),
 419                                     irq_desc+IRQ_GLAMO(i));
 420
 421         } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
 422
 423         desc->status &= ~IRQ_INPROGRESS;
 424 }
 425
 426
 427 static ssize_t regs_write(struct device *dev, struct device_attribute *attr,
 428                            const char *buf, size_t count)
 429 {
 430         unsigned long reg = simple_strtoul(buf, NULL, 10);
 431         struct glamo_core *glamo = dev_get_drvdata(dev);
 432
 433         while (*buf && (*buf != ' '))
 434                 buf++;
 435         if (*buf != ' ')
 436                 return -EINVAL;
 437         while (*buf && (*buf == ' '))
 438                 buf++;
 439         if (!*buf)
 440                 return -EINVAL;
 441
 442         printk(KERN_INFO"reg 0x%02lX <-- 0x%04lX\n",
 443                reg, simple_strtoul(buf, NULL, 10));
 444
 445         __reg_write(glamo, reg, simple_strtoul(buf, NULL, 10));
 446
 447         return count;
 448 }
 449
 450 static ssize_t regs_read(struct device *dev, struct device_attribute *attr,
 451                         char *buf)
 452 {
 453         struct glamo_core *glamo = dev_get_drvdata(dev);
 454         int n, n1 = 0, r;
 455         char * end = buf;
 456
 457         spin_lock(&glamo->lock);
 458
 459         for (r = 0; r < ARRAY_SIZE(reg_range); r++) {
 460                 if (!reg_range[r].dump)
 461                         continue;
 462                 n1 = 0;
 463                 end += sprintf(end, "\n%s\n", reg_range[r].name);
 464                 for (n = reg_range[r].start;
 465                      n < reg_range[r].start + reg_range[r].count; n += 2) {
 466                         if (((n1++) & 7) == 0)
 467                                 end += sprintf(end, "\n%04X:  ", n);
 468                         end += sprintf(end, "%04x ", __reg_read(glamo, n));
 469                 }
 470                 end += sprintf(end, "\n");
 471                 if (!attr) {
 472                         printk("%s", buf);
 473                         end = buf;
 474                 }
 475         }
 476         spin_unlock(&glamo->lock);
 477
 478         return end - buf;
 479 }
 480
 481 static DEVICE_ATTR(regs, 0644, regs_read, regs_write);
 482 static struct attribute *glamo_sysfs_entries[] = {
 483         &dev_attr_regs.attr,
 484         NULL
 485 };
 486 static struct attribute_group glamo_attr_group = {
 487         .name   = NULL,
 488         .attrs  = glamo_sysfs_entries,
 489 };
 490
 491
 492
 493 /***********************************************************************
 494  * 'engine' support
 495  ***********************************************************************/
 496
 497 int __glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
 498 {
 499         switch (engine) {
 500         case GLAMO_ENGINE_LCD:
 501                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 502                                    GLAMO_HOSTBUS2_MMIO_EN_LCD,
 503                                    GLAMO_HOSTBUS2_MMIO_EN_LCD);
 504                 __reg_write(glamo, GLAMO_REG_CLOCK_LCD,
 505                             GLAMO_CLOCK_LCD_EN_M5CLK |
 506                             GLAMO_CLOCK_LCD_EN_DHCLK |
 507                             GLAMO_CLOCK_LCD_EN_DMCLK |
 508                             GLAMO_CLOCK_LCD_EN_DCLK |
 509                             GLAMO_CLOCK_LCD_DG_M5CLK |
 510                             GLAMO_CLOCK_LCD_DG_DMCLK);
 511                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 512                             GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
 513                             GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
 514                             GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0xffff);
 515                 break;
 516         case GLAMO_ENGINE_MMC:
 517                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 518                                    GLAMO_HOSTBUS2_MMIO_EN_MMC,
 519                                    GLAMO_HOSTBUS2_MMIO_EN_MMC);
 520                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
 521                                    GLAMO_CLOCK_MMC_EN_M9CLK |
 522                                    GLAMO_CLOCK_MMC_EN_TCLK |
 523                                    GLAMO_CLOCK_MMC_DG_M9CLK |
 524                                    GLAMO_CLOCK_MMC_DG_TCLK, 0xffff);
 525                 /* enable the TCLK divider clk input */
 526                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 527                                                  GLAMO_CLOCK_GEN51_EN_DIV_TCLK,
 528                                                  GLAMO_CLOCK_GEN51_EN_DIV_TCLK);
 529                 break;
 530         case GLAMO_ENGINE_2D:
 531                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 532                                    GLAMO_CLOCK_2D_EN_M7CLK |
 533                                    GLAMO_CLOCK_2D_EN_GCLK |
 534                                    GLAMO_CLOCK_2D_DG_M7CLK |
 535                                    GLAMO_CLOCK_2D_DG_GCLK, 0xffff);
 536                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 537                                    GLAMO_HOSTBUS2_MMIO_EN_2D,
 538                                    GLAMO_HOSTBUS2_MMIO_EN_2D);
 539                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 540                                    GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
 541                                                    0xffff);
 542                 break;
 543         case GLAMO_ENGINE_CMDQ:
 544                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 545                                    GLAMO_CLOCK_2D_EN_M6CLK, 0xffff);
 546                 __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 547                                    GLAMO_HOSTBUS2_MMIO_EN_CQ,
 548                                    GLAMO_HOSTBUS2_MMIO_EN_CQ);
 549                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 550                                    GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
 551                                                    0xffff);
 552                 break;
 553         /* FIXME: Implementation */
 554         default:
 555                 return -EINVAL;
 556         }
 557
 558         glamo->engine_enabled_bitfield |= 1 << engine;
 559
 560         return 0;
 561 }
 562
 563 int glamo_engine_enable(struct glamo_core *glamo, enum glamo_engine engine)
 564 {
 565         int ret;
 566
 567         spin_lock(&glamo->lock);
 568
 569         ret = __glamo_engine_enable(glamo, engine);
 570
 571         spin_unlock(&glamo->lock);
 572
 573         return ret;
 574 }
 575 EXPORT_SYMBOL_GPL(glamo_engine_enable);
 576
 577 int __glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
 578 {
 579         switch (engine) {
 580         case GLAMO_ENGINE_LCD:
 581                 /* remove pixel clock to LCM */
 582                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
 583                             GLAMO_CLOCK_LCD_EN_DCLK, 0);
 584                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
 585                             GLAMO_CLOCK_LCD_EN_DHCLK |
 586                             GLAMO_CLOCK_LCD_EN_DMCLK, 0);
 587                 /* kill memory clock */
 588                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_LCD,
 589                             GLAMO_CLOCK_LCD_EN_M5CLK, 0);
 590                 /* stop dividing the clocks */
 591                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 592                             GLAMO_CLOCK_GEN51_EN_DIV_DHCLK |
 593                             GLAMO_CLOCK_GEN51_EN_DIV_DMCLK |
 594                             GLAMO_CLOCK_GEN51_EN_DIV_DCLK, 0);
 595                 break;
 596
 597         case GLAMO_ENGINE_MMC:
 598                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_MMC,
 599                                                    GLAMO_CLOCK_MMC_EN_M9CLK |
 600                                                    GLAMO_CLOCK_MMC_EN_TCLK |
 601                                                    GLAMO_CLOCK_MMC_DG_M9CLK |
 602                                                    GLAMO_CLOCK_MMC_DG_TCLK, 0);
 603                 /* disable the TCLK divider clk input */
 604                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 605                                         GLAMO_CLOCK_GEN51_EN_DIV_TCLK, 0);
 606         break;
 607         case GLAMO_ENGINE_CMDQ:
 608                         __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 609                                            GLAMO_CLOCK_2D_EN_M6CLK,
 610                                                            0);
 611                         __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 612                                            GLAMO_HOSTBUS2_MMIO_EN_CQ,
 613                                            GLAMO_HOSTBUS2_MMIO_EN_CQ);
 614 /*                      __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 615                                            GLAMO_CLOCK_GEN51_EN_DIV_MCLK,
 616                                                            0);*/
 617                 break;
 618         case GLAMO_ENGINE_2D:
 619                         __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_2D,
 620                                            GLAMO_CLOCK_2D_EN_M7CLK |
 621                                                            GLAMO_CLOCK_2D_EN_GCLK |
 622                                                            GLAMO_CLOCK_2D_DG_M7CLK |
 623                                                            GLAMO_CLOCK_2D_DG_GCLK,
 624                                                            0);
 625                         __reg_set_bit_mask(glamo, GLAMO_REG_HOSTBUS(2),
 626                                            GLAMO_HOSTBUS2_MMIO_EN_2D,
 627                                            GLAMO_HOSTBUS2_MMIO_EN_2D);
 628                         __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1,
 629                                            GLAMO_CLOCK_GEN51_EN_DIV_GCLK,
 630                                                            0);
 631                 break;
 632         default:
 633                 return -EINVAL;
 634         }
 635
 636         glamo->engine_enabled_bitfield &= ~(1 << engine);
 637
 638         return 0;
 639 }
 640 int glamo_engine_disable(struct glamo_core *glamo, enum glamo_engine engine)
 641 {
 642         int ret;
 643
 644         spin_lock(&glamo->lock);
 645
 646         ret = __glamo_engine_disable(glamo, engine);
 647
 648         spin_unlock(&glamo->lock);
 649
 650         return ret;
 651 }
 652 EXPORT_SYMBOL_GPL(glamo_engine_disable);
 653
 654 static const u_int16_t engine_clock_regs[__NUM_GLAMO_ENGINES] = {
 655         [GLAMO_ENGINE_LCD]      = GLAMO_REG_CLOCK_LCD,
 656         [GLAMO_ENGINE_MMC]      = GLAMO_REG_CLOCK_MMC,
 657         [GLAMO_ENGINE_ISP]      = GLAMO_REG_CLOCK_ISP,
 658         [GLAMO_ENGINE_JPEG]     = GLAMO_REG_CLOCK_JPEG,
 659         [GLAMO_ENGINE_3D]       = GLAMO_REG_CLOCK_3D,
 660         [GLAMO_ENGINE_2D]       = GLAMO_REG_CLOCK_2D,
 661         [GLAMO_ENGINE_MPEG_ENC] = GLAMO_REG_CLOCK_MPEG,
 662         [GLAMO_ENGINE_MPEG_DEC] = GLAMO_REG_CLOCK_MPEG,
 663 };
 664
 665 void glamo_engine_clkreg_set(struct glamo_core *glamo,
 666                              enum glamo_engine engine,
 667                              u_int16_t mask, u_int16_t val)
 668 {
 669         reg_set_bit_mask(glamo, engine_clock_regs[engine], mask, val);
 670 }
 671 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_set);
 672
 673 u_int16_t glamo_engine_clkreg_get(struct glamo_core *glamo,
 674                                   enum glamo_engine engine)
 675 {
 676         u_int16_t val;
 677
 678         spin_lock(&glamo->lock);
 679         val = __reg_read(glamo, engine_clock_regs[engine]);
 680         spin_unlock(&glamo->lock);
 681
 682         return val;
 683 }
 684 EXPORT_SYMBOL_GPL(glamo_engine_clkreg_get);
 685
 686 struct glamo_script reset_regs[] = {
 687         [GLAMO_ENGINE_LCD] = {
 688                 GLAMO_REG_CLOCK_LCD, GLAMO_CLOCK_LCD_RESET
 689         },
 690 #if 0
 691         [GLAMO_ENGINE_HOST] = {
 692                 GLAMO_REG_CLOCK_HOST, GLAMO_CLOCK_HOST_RESET
 693         },
 694         [GLAMO_ENGINE_MEM] = {
 695                 GLAMO_REG_CLOCK_MEM, GLAMO_CLOCK_MEM_RESET
 696         },
 697 #endif
 698         [GLAMO_ENGINE_MMC] = {
 699                 GLAMO_REG_CLOCK_MMC, GLAMO_CLOCK_MMC_RESET
 700         },
 701     [GLAMO_ENGINE_CMDQ] = {
 702         GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_CQ_RESET
 703     },
 704         [GLAMO_ENGINE_2D] = {
 705                 GLAMO_REG_CLOCK_2D, GLAMO_CLOCK_2D_RESET
 706         },
 707         [GLAMO_ENGINE_JPEG] = {
 708                 GLAMO_REG_CLOCK_JPEG, GLAMO_CLOCK_JPEG_RESET
 709         },
 710 };
 711
 712 void glamo_engine_reset(struct glamo_core *glamo, enum glamo_engine engine)
 713 {
 714         struct glamo_script *rst;
 715
 716         if (engine >= ARRAY_SIZE(reset_regs)) {
 717                 dev_warn(&glamo->pdev->dev, "unknown engine %u ", engine);
 718                 return;
 719         }
 720
 721         rst = &reset_regs[engine];
 722
 723         spin_lock(&glamo->lock);
 724         __reg_set_bit(glamo, rst->reg, rst->val);
 725         __reg_clear_bit(glamo, rst->reg, rst->val);
 726         spin_unlock(&glamo->lock);
 727 }
 728 EXPORT_SYMBOL_GPL(glamo_engine_reset);
 729
 730 void glamo_lcm_reset(int level)
 731 {
 732         if (!glamo_handle)
 733                 return;
 734
 735         glamo_gpio_setpin(glamo_handle, GLAMO_GPIO4, level);
 736         glamo_gpio_cfgpin(glamo_handle, GLAMO_GPIO4_OUTPUT);
 737
 738 }
 739 EXPORT_SYMBOL_GPL(glamo_lcm_reset);
 740
 741 enum glamo_pll {
 742         GLAMO_PLL1,
 743         GLAMO_PLL2,
 744 };
 745
 746 static int glamo_pll_rate(struct glamo_core *glamo,
 747                           enum glamo_pll pll)
 748 {
 749         u_int16_t reg;
 750         unsigned int div = 512;
 751         /* FIXME: move osci into platform_data */
 752         unsigned int osci = 32768;
 753
 754         if (osci == 32768)
 755                 div = 1;
 756
 757         switch (pll) {
 758         case GLAMO_PLL1:
 759                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN1);
 760                 break;
 761         case GLAMO_PLL2:
 762                 reg = __reg_read(glamo, GLAMO_REG_PLL_GEN3);
 763                 break;
 764         default:
 765                 return -EINVAL;
 766         }
 767         return (osci/div)*reg;
 768 }
 769
 770 int glamo_engine_reclock(struct glamo_core *glamo,
 771                          enum glamo_engine engine,
 772                          int ps)
 773 {
 774         int pll, khz;
 775         u_int16_t reg, mask, val = 0;
 776
 777         if (!ps)
 778                 return 0;
 779
 780         switch (engine) {
 781         case GLAMO_ENGINE_LCD:
 782                 pll = GLAMO_PLL1;
 783                 reg = GLAMO_REG_CLOCK_GEN7;
 784                 mask = 0xff;
 785                 break;
 786         default:
 787                 dev_warn(&glamo->pdev->dev,
 788                          "reclock of engine 0x%x not supported\n", engine);
 789                 return -EINVAL;
 790                 break;
 791         }
 792
 793         pll = glamo_pll_rate(glamo, pll);
 794         khz = 1000000000UL / ps;
 795
 796         if (khz)
 797                 val = (pll / khz) / 1000;
 798
 799         dev_dbg(&glamo->pdev->dev,
 800                         "PLL %d, kHZ %d, div %d\n", pll, khz, val);
 801
 802         if (val) {
 803                 val--;
 804                 reg_set_bit_mask(glamo, reg, mask, val);
 805                 mdelay(5); /* wait some time to stabilize */
 806
 807                 return 0;
 808         } else {
 809                 return -EINVAL;
 810         }
 811 }
 812 EXPORT_SYMBOL_GPL(glamo_engine_reclock);
 813
 814 /***********************************************************************
 815  * script support
 816  ***********************************************************************/
 817
 818 int glamo_run_script(struct glamo_core *glamo, struct glamo_script *script,
 819                      int len, int may_sleep)
 820 {
 821         int i;
 822
 823         for (i = 0; i < len; i++) {
 824                 struct glamo_script *line = &script[i];
 825
 826                 switch (line->reg) {
 827                 case 0xffff:
 828                         return 0;
 829                 case 0xfffe:
 830                         if (may_sleep)
 831                                 msleep(line->val);
 832                         else
 833                                 mdelay(line->val * 4);
 834                         break;
 835                 case 0xfffd:
 836                         /* spin until PLLs lock */
 837                         while ((__reg_read(glamo, GLAMO_REG_PLL_GEN5) & 3) != 3)
 838                                 ;
 839                         break;
 840
 841                 /*
 842                  * couple of people reported artefacts with 2.6.28 changes, this
 843                  * allows reversion to 2.6.24 settings
 844                  */
 845
 846                 case 0x200:
 847                         switch (slow_memory) {
 848                         /* choice 1 is the most conservative */
 849                         case 1: /* 3 waits on Async BB R & W, Use PLL 1 for mem bus */
 850                                 __reg_write(glamo, script[i].reg, 0xef0);
 851                                 break;
 852                         case 2: /* 2 waits on Async BB R & W, Use PLL 1 for mem bus */
 853                                 __reg_write(glamo, script[i].reg, 0xea0);
 854                                 break;
 855                         case 3: /* 1 waits on Async BB R & W, Use PLL 1 for mem bus */
 856                                 __reg_write(glamo, script[i].reg, 0xe50);
 857                                 break;
 858                         case 4: /* 0 waits on Async BB R & W, Use PLL 1 for mem bus */
 859                                 __reg_write(glamo, script[i].reg, 0xe00);
 860                                 break;
 861
 862                         /* using PLL2 for memory bus increases CPU bandwidth significantly */
 863                         case 5: /* 3 waits on Async BB R & W, Use PLL 2 for mem bus */
 864                                 __reg_write(glamo, script[i].reg, 0xef3);
 865                                 break;
 866                         case 6: /* 2 waits on Async BB R & W, Use PLL 2 for mem bus */
 867                                 __reg_write(glamo, script[i].reg, 0xea3);
 868                                 break;
 869                         case 7: /* 1 waits on Async BB R & W, Use PLL 2 for mem bus */
 870                                 __reg_write(glamo, script[i].reg, 0xe53);
 871                                 break;
 872                         /* default of 0 or >7 is fastest */
 873                         default: /* 0 waits on Async BB R & W, Use PLL 2 for mem bus */
 874                                 __reg_write(glamo, script[i].reg, 0xe03);
 875                                 break;
 876                         }
 877                         break;
 878
 879                 default:
 880                         __reg_write(glamo, script[i].reg, script[i].val);
 881                         break;
 882                 }
 883         }
 884
 885         return 0;
 886 }
 887 EXPORT_SYMBOL(glamo_run_script);
 888
 889 static struct glamo_script glamo_init_script[] = {
 890         { GLAMO_REG_CLOCK_HOST,         0x1000 },
 891                 { 0xfffe, 2 },
 892         { GLAMO_REG_CLOCK_MEMORY,       0x1000 },
 893         { GLAMO_REG_CLOCK_MEMORY,       0x2000 },
 894         { GLAMO_REG_CLOCK_LCD,          0x1000 },
 895         { GLAMO_REG_CLOCK_MMC,          0x1000 },
 896         { GLAMO_REG_CLOCK_ISP,          0x1000 },
 897         { GLAMO_REG_CLOCK_ISP,          0x3000 },
 898         { GLAMO_REG_CLOCK_JPEG,         0x1000 },
 899         { GLAMO_REG_CLOCK_3D,           0x1000 },
 900         { GLAMO_REG_CLOCK_3D,           0x3000 },
 901         { GLAMO_REG_CLOCK_2D,           0x1000 },
 902         { GLAMO_REG_CLOCK_2D,           0x3000 },
 903         { GLAMO_REG_CLOCK_RISC1,        0x1000 },
 904         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
 905         { GLAMO_REG_CLOCK_MPEG,         0x3000 },
 906         { GLAMO_REG_CLOCK_MPROC,        0x1000 /*0x100f*/ },
 907                 { 0xfffe, 2 },
 908         { GLAMO_REG_CLOCK_HOST,         0x0000 },
 909         { GLAMO_REG_CLOCK_MEMORY,       0x0000 },
 910         { GLAMO_REG_CLOCK_LCD,          0x0000 },
 911         { GLAMO_REG_CLOCK_MMC,          0x0000 },
 912 #if 0
 913 /* unused engines must be left in reset to stop MMC block read "blackouts" */
 914         { GLAMO_REG_CLOCK_ISP,          0x0000 },
 915         { GLAMO_REG_CLOCK_ISP,          0x0000 },
 916         { GLAMO_REG_CLOCK_JPEG,         0x0000 },
 917         { GLAMO_REG_CLOCK_3D,           0x0000 },
 918         { GLAMO_REG_CLOCK_3D,           0x0000 },
 919         { GLAMO_REG_CLOCK_2D,           0x0000 },
 920         { GLAMO_REG_CLOCK_2D,           0x0000 },
 921         { GLAMO_REG_CLOCK_RISC1,        0x0000 },
 922         { GLAMO_REG_CLOCK_MPEG,         0x0000 },
 923         { GLAMO_REG_CLOCK_MPEG,         0x0000 },
 924 #endif
 925         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
 926         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
 927         { 0xfffd, 0 },
 928         /*
 929          * b9 of this register MUST be zero to get any interrupts on INT#
 930          * the other set bits enable all the engine interrupt sources
 931          */
 932         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
 933         { GLAMO_REG_CLOCK_GEN6,         0x2000 },
 934         { GLAMO_REG_CLOCK_GEN7,         0x0101 },
 935         { GLAMO_REG_CLOCK_GEN8,         0x0100 },
 936         { GLAMO_REG_CLOCK_HOST,         0x000d },
 937         /*
 938          * b7..b4 = 0 = no wait states on read or write
 939          * b0 = 1 select PLL2 for Host interface, b1 = enable it
 940          */
 941         { 0x200,        0x0e03 /* this is replaced by script parser */ },
 942         { 0x202,        0x07ff },
 943         { 0x212,        0x0000 },
 944         { 0x214,        0x4000 },
 945         { 0x216,        0xf00e },
 946
 947         /* S-Media recommended "set tiling mode to 512 mode for memory access
 948          * more efficiency when 640x480" */
 949         { GLAMO_REG_MEM_TYPE,           0x0c74 }, /* 8MB, 16 word pg wr+rd */
 950         { GLAMO_REG_MEM_GEN,            0xafaf }, /* 63 grants min + max */
 951
 952         { GLAMO_REGOFS_HOSTBUS + 2,     0xffff }, /* enable  on MMIO*/
 953
 954         { GLAMO_REG_MEM_TIMING1,        0x0108 },
 955         { GLAMO_REG_MEM_TIMING2,        0x0010 }, /* Taa = 3 MCLK */
 956         { GLAMO_REG_MEM_TIMING3,        0x0000 },
 957         { GLAMO_REG_MEM_TIMING4,        0x0000 }, /* CE1# delay fall/rise */
 958         { GLAMO_REG_MEM_TIMING5,        0x0000 }, /* UB# LB# */
 959         { GLAMO_REG_MEM_TIMING6,        0x0000 }, /* OE# */
 960         { GLAMO_REG_MEM_TIMING7,        0x0000 }, /* WE# */
 961         { GLAMO_REG_MEM_TIMING8,        0x1002 }, /* MCLK delay, was 0x1000 */
 962         { GLAMO_REG_MEM_TIMING9,        0x6006 },
 963         { GLAMO_REG_MEM_TIMING10,       0x00ff },
 964         { GLAMO_REG_MEM_TIMING11,       0x0001 },
 965         { GLAMO_REG_MEM_POWER1,         0x0020 },
 966         { GLAMO_REG_MEM_POWER2,         0x0000 },
 967         { GLAMO_REG_MEM_DRAM1,          0x0000 },
 968                 { 0xfffe, 1 },
 969         { GLAMO_REG_MEM_DRAM1,          0xc100 },
 970                 { 0xfffe, 1 },
 971         { GLAMO_REG_MEM_DRAM1,          0xe100 },
 972         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
 973         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
 974         { GLAMO_REG_GPIO_GEN1,          0x000f },
 975         { GLAMO_REG_GPIO_GEN2,          0x111e },
 976         { GLAMO_REG_GPIO_GEN3,          0xccc3 },
 977         { GLAMO_REG_GPIO_GEN4,          0x111e },
 978         { GLAMO_REG_GPIO_GEN5,          0x000f },
 979 };
 980 #if 0
 981 static struct glamo_script glamo_resume_script[] = {
 982
 983         { GLAMO_REG_PLL_GEN1,           0x05db },       /* 48MHz */
 984         { GLAMO_REG_PLL_GEN3,           0x0aba },       /* 90MHz */
 985         { GLAMO_REG_DFT_GEN6, 1 },
 986                 { 0xfffe, 100 },
 987                 { 0xfffd, 0 },
 988         { 0x200,        0x0e03 },
 989
 990         /*
 991          * b9 of this register MUST be zero to get any interrupts on INT#
 992          * the other set bits enable all the engine interrupt sources
 993          */
 994         { GLAMO_REG_IRQ_ENABLE,         0x01ff },
 995         { GLAMO_REG_CLOCK_HOST,         0x0018 },
 996         { GLAMO_REG_CLOCK_GEN5_1, 0x18b1 },
 997
 998         { GLAMO_REG_MEM_DRAM1,          0x0000 },
 999                 { 0xfffe, 1 },
1000         { GLAMO_REG_MEM_DRAM1,          0xc100 },
1001                 { 0xfffe, 1 },
1002         { GLAMO_REG_MEM_DRAM1,          0xe100 },
1003         { GLAMO_REG_MEM_DRAM2,          0x01d6 },
1004         { GLAMO_REG_CLOCK_MEMORY,       0x000b },
1005 };
1006 #endif
1007
1008 enum glamo_power {
1009         GLAMO_POWER_ON,
1010         GLAMO_POWER_SUSPEND,
1011 };
1012
1013 static void glamo_power(struct glamo_core *glamo,
1014                         enum glamo_power new_state)
1015 {
1016         int n;
1017         unsigned long flags;
1018
1019         spin_lock_irqsave(&glamo->lock, flags);
1020
1021         dev_info(&glamo->pdev->dev, "***** glamo_power -> %d\n", new_state);
1022
1023         /*
1024 Power management
1025 static const REG_VALUE_MASK_TYPE reg_powerOn[] =
1026 {
1027     { REG_GEN_DFT6,     REG_BIT_ALL,    REG_DATA(1u << 0)           },
1028     { REG_GEN_PLL3,     0u,             REG_DATA(1u << 13)          },
1029     { REG_GEN_MEM_CLK,  REG_BIT_ALL,    REG_BIT_EN_MOCACLK          },
1030     { REG_MEM_DRAM2,    0u,             REG_BIT_EN_DEEP_POWER_DOWN  },
1031     { REG_MEM_DRAM1,    0u,             REG_BIT_SELF_REFRESH        }
1032 };
1033
1034 static const REG_VALUE_MASK_TYPE reg_powerStandby[] =
1035 {
1036     { REG_MEM_DRAM1,    REG_BIT_ALL,    REG_BIT_SELF_REFRESH    },
1037     { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK      },
1038     { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)      },
1039     { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)       }
1040 };
1041
1042 static const REG_VALUE_MASK_TYPE reg_powerSuspend[] =
1043 {
1044     { REG_MEM_DRAM2,    REG_BIT_ALL,    REG_BIT_EN_DEEP_POWER_DOWN  },
1045     { REG_GEN_MEM_CLK,  0u,             REG_BIT_EN_MOCACLK          },
1046     { REG_GEN_PLL3,     REG_BIT_ALL,    REG_DATA(1u << 13)          },
1047     { REG_GEN_DFT5,     REG_BIT_ALL,    REG_DATA(1u << 0)           }
1048 };
1049 */
1050
1051         switch (new_state) {
1052         case GLAMO_POWER_ON:
1053
1054                 /*
1055                  * glamo state on resume is nondeterministic in some
1056                  * fundamental way, it has also been observed that the
1057                  * Glamo reset pin can get asserted by, eg, touching it with
1058                  * a scope probe.  So the only answer is to roll with it and
1059                  * force an external reset on the Glamo during resume.
1060                  */
1061
1062                 (glamo->pdata->glamo_external_reset)(0);
1063                 udelay(10);
1064                 (glamo->pdata->glamo_external_reset)(1);
1065                 mdelay(5);
1066
1067                 glamo_run_script(glamo, glamo_init_script,
1068                          ARRAY_SIZE(glamo_init_script), 0);
1069
1070                 break;
1071
1072         case GLAMO_POWER_SUSPEND:
1073
1074                 /* nuke interrupts */
1075                 __reg_write(glamo, GLAMO_REG_IRQ_ENABLE, 0x200);
1076
1077                 /* stash a copy of which engines were running */
1078                 glamo->engine_enabled_bitfield_suspend =
1079                                                  glamo->engine_enabled_bitfield;
1080
1081                 /* take down each engine before we kill mem and pll */
1082                 for (n = 0; n < __NUM_GLAMO_ENGINES; n++)
1083                         if (glamo->engine_enabled_bitfield & (1 << n))
1084                                 __glamo_engine_disable(glamo, n);
1085
1086                 /* enable self-refresh */
1087
1088                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1089                                         GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1090                                         GLAMO_MEM_DRAM1_EN_GATE_CKE |
1091                                         GLAMO_MEM_DRAM1_SELF_REFRESH |
1092                                         GLAMO_MEM_REFRESH_COUNT);
1093                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1,
1094                                         GLAMO_MEM_DRAM1_EN_MODEREG_SET |
1095                                         GLAMO_MEM_DRAM1_EN_DRAM_REFRESH |
1096                                         GLAMO_MEM_DRAM1_EN_GATE_CKE |
1097                                         GLAMO_MEM_DRAM1_SELF_REFRESH |
1098                                         GLAMO_MEM_REFRESH_COUNT);
1099
1100                 /* force RAM into deep powerdown */
1101
1102                 __reg_write(glamo, GLAMO_REG_MEM_DRAM2,
1103                                         GLAMO_MEM_DRAM2_DEEP_PWRDOWN |
1104                                         (7 << 6) | /* tRC */
1105                                         (1 << 4) | /* tRP */
1106                                         (1 << 2) | /* tRCD */
1107                                         2); /* CAS latency */
1108
1109                 /* disable clocks to memory */
1110                 __reg_write(glamo, GLAMO_REG_CLOCK_MEMORY, 0);
1111
1112                 /* all dividers from OSCI */
1113                 __reg_set_bit_mask(glamo, GLAMO_REG_CLOCK_GEN5_1, 0x400, 0x400);
1114
1115                 /* PLL2 into bypass */
1116                 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 12, 1 << 12);
1117
1118                 __reg_write(glamo, 0x200, 0x0e00);
1119
1120
1121                 /* kill PLLS 1 then 2 */
1122                 __reg_write(glamo, GLAMO_REG_DFT_GEN5, 0x0001);
1123                 __reg_set_bit_mask(glamo, GLAMO_REG_PLL_GEN3, 1 << 13, 1 << 13);
1124
1125                 break;
1126         }
1127
1128         spin_unlock_irqrestore(&glamo->lock, flags);
1129 }
1130
1131 #if 0
1132 #define MEMDETECT_RETRY 6
1133 static unsigned int detect_memsize(struct glamo_core *glamo)
1134 {
1135         int i;
1136
1137         /*static const u_int16_t pattern[] = {
1138                 0x1111, 0x8a8a, 0x2222, 0x7a7a,
1139                 0x3333, 0x6a6a, 0x4444, 0x5a5a,
1140                 0x5555, 0x4a4a, 0x6666, 0x3a3a,
1141                 0x7777, 0x2a2a, 0x8888, 0x1a1a
1142         }; */
1143
1144         for (i = 0; i < MEMDETECT_RETRY; i++) {
1145                 switch (glamo->type) {
1146                 case 3600:
1147                         __reg_write(glamo, GLAMO_REG_MEM_TYPE, 0x0072);
1148                         __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1149                         break;
1150                 case 3650:
1151                         switch (glamo->revision) {
1152                         case GLAMO_CORE_REV_A0:
1153                                 if (i & 1)
1154                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1155                                                     0x097a);
1156                                 else
1157                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1158                                                     0x0173);
1159
1160                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1161                                 msleep(1);
1162                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xc100);
1163                                 break;
1164                         default:
1165                                 if (i & 1)
1166                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1167                                                     0x0972);
1168                                 else
1169                                         __reg_write(glamo, GLAMO_REG_MEM_TYPE,
1170                                                     0x0872);
1171
1172                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0x0000);
1173                                 msleep(1);
1174                                 __reg_write(glamo, GLAMO_REG_MEM_DRAM1, 0xe100);
1175                                 break;
1176                         }
1177                         break;
1178                 case 3700:
1179                         /* FIXME */
1180                 default:
1181                         break;
1182                 }
1183
1184 #if 0
1185                 /* FIXME: finish implementation */
1186                 for (j = 0; j < 8; j++) {
1187                         __
1188 #endif
1189         }
1190
1191         return 0;
1192 }
1193 #endif
1194
1195 /* Find out if we can support this version of the Glamo chip */
1196 static int glamo_supported(struct glamo_core *glamo)
1197 {
1198         u_int16_t dev_id, rev_id; /*, memsize; */
1199
1200         dev_id = __reg_read(glamo, GLAMO_REG_DEVICE_ID);
1201         rev_id = __reg_read(glamo, GLAMO_REG_REVISION_ID);
1202
1203         switch (dev_id) {
1204         case 0x3650:
1205                 switch (rev_id) {
1206                 case GLAMO_CORE_REV_A2:
1207                         break;
1208                 case GLAMO_CORE_REV_A0:
1209                 case GLAMO_CORE_REV_A1:
1210                 case GLAMO_CORE_REV_A3:
1211                         dev_warn(&glamo->pdev->dev, "untested core revision "
1212                                  "%04x, your mileage may vary\n", rev_id);
1213                         break;
1214                 default:
1215                         dev_warn(&glamo->pdev->dev, "unknown glamo revision "
1216                                  "%04x, your mileage may vary\n", rev_id);
1217                         /* maybe should abort ? */
1218                 }
1219                 break;
1220         case 0x3600:
1221         case 0x3700:
1222         default:
1223                 dev_err(&glamo->pdev->dev, "unsupported Glamo device %04x\n",
1224                         dev_id);
1225                 return 0;
1226         }
1227
1228         dev_dbg(&glamo->pdev->dev, "Detected Glamo core %04x Revision %04x "
1229                  "(%uHz CPU / %uHz Memory)\n", dev_id, rev_id,
1230                  glamo_pll_rate(glamo, GLAMO_PLL1),
1231                  glamo_pll_rate(glamo, GLAMO_PLL2));
1232
1233         return 1;
1234 }
1235
1236 static int __init glamo_probe(struct platform_device *pdev)
1237 {
1238         int rc = 0, irq;
1239         struct glamo_core *glamo;
1240         struct platform_device *glamo_mmc_dev;
1241
1242         if (glamo_handle) {
1243                 dev_err(&pdev->dev,
1244                         "This driver supports only one instance\n");
1245                 return -EBUSY;
1246         }
1247
1248         glamo = kmalloc(GFP_KERNEL, sizeof(*glamo));
1249         if (!glamo)
1250                 return -ENOMEM;
1251
1252         spin_lock_init(&glamo->lock);
1253         glamo_handle = glamo;
1254         glamo->pdev = pdev;
1255         glamo->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1256         glamo->irq = platform_get_irq(pdev, 0);
1257         glamo->pdata = pdev->dev.platform_data;
1258         if (!glamo->mem || !glamo->pdata) {
1259                 dev_err(&pdev->dev, "platform device with no MEM/PDATA ?\n");
1260                 rc = -ENOENT;
1261                 goto bail_free;
1262         }
1263
1264         /* register a number of sibling devices whoise IOMEM resources
1265          * are siblings of pdev's IOMEM resource */
1266 #if 0
1267         glamo_core_dev.dev.parent = &pdev.dev;
1268         mangle_mem_resources(glamo_core_dev.resources,
1269                              glamo_core_dev.num_resources, glamo->mem);
1270         glamo_core_dev.resources[1].start = glamo->irq;
1271         glamo_core_dev.resources[1].end = glamo->irq;
1272         platform_device_register(&glamo_core_dev);
1273 #endif
1274         /* only remap the generic, hostbus and memory controller registers */
1275         glamo->base = ioremap(glamo->mem->start, 0x4000 /*GLAMO_REGOFS_VIDCAP*/);
1276         if (!glamo->base) {
1277                 dev_err(&pdev->dev, "failed to ioremap() memory region\n");
1278                 goto bail_free;
1279         }
1280
1281         platform_set_drvdata(pdev, glamo);
1282
1283         (glamo->pdata->glamo_external_reset)(0);
1284         udelay(10);
1285         (glamo->pdata->glamo_external_reset)(1);
1286         mdelay(10);
1287
1288         /*
1289          * finally set the mfd interrupts up
1290          * can't do them earlier or sibling probes blow up
1291          */
1292
1293         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1294                 set_irq_chip(irq, &glamo_irq_chip);
1295                 set_irq_handler(irq, handle_level_irq);
1296                 set_irq_flags(irq, IRQF_VALID);
1297         }
1298
1299         if (glamo->pdata->glamo_irq_is_wired &&
1300             !glamo->pdata->glamo_irq_is_wired()) {
1301                 set_irq_chained_handler(glamo->irq, glamo_irq_demux_handler);
1302                 set_irq_type(glamo->irq, IRQ_TYPE_EDGE_FALLING);
1303                 dev_info(&pdev->dev, "Glamo interrupt registered\n");
1304                 glamo->irq_works = 1;
1305         } else {
1306                 dev_err(&pdev->dev, "Glamo interrupt not used\n");
1307                 glamo->irq_works = 0;
1308         }
1309
1310
1311         /* confirm it isn't insane version */
1312         if (!glamo_supported(glamo)) {
1313                 dev_err(&pdev->dev, "This Glamo is not supported\n");
1314                 goto bail_irq;
1315         }
1316
1317         /* sysfs */
1318         rc = sysfs_create_group(&pdev->dev.kobj, &glamo_attr_group);
1319         if (rc < 0) {
1320                 dev_err(&pdev->dev, "cannot create sysfs group\n");
1321                 goto bail_irq;
1322         }
1323
1324         /* init the chip with canned register set */
1325
1326         dev_dbg(&glamo->pdev->dev, "running init script\n");
1327         glamo_run_script(glamo, glamo_init_script,
1328                          ARRAY_SIZE(glamo_init_script), 1);
1329
1330         dev_info(&glamo->pdev->dev, "Glamo core PLL1: %uHz, PLL2: %uHz\n",
1331                  glamo_pll_rate(glamo, GLAMO_PLL1),
1332                  glamo_pll_rate(glamo, GLAMO_PLL2));
1333
1334         /* bring MCI specific stuff over from our MFD platform data */
1335         glamo_mci_def_pdata.glamo_can_set_mci_power =
1336                                         glamo->pdata->glamo_can_set_mci_power;
1337         glamo_mci_def_pdata.glamo_mci_use_slow =
1338                                         glamo->pdata->glamo_mci_use_slow;
1339         glamo_mci_def_pdata.glamo_irq_is_wired =
1340                                         glamo->pdata->glamo_irq_is_wired;
1341
1342         /* start creating the siblings */
1343
1344         glamo_2d_dev.dev.parent = &pdev->dev;
1345         mangle_mem_resources(glamo_2d_dev.resource,
1346                              glamo_2d_dev.num_resources, glamo->mem);
1347         platform_device_register(&glamo_2d_dev);
1348
1349         glamo_3d_dev.dev.parent = &pdev->dev;
1350         mangle_mem_resources(glamo_3d_dev.resource,
1351                              glamo_3d_dev.num_resources, glamo->mem);
1352         platform_device_register(&glamo_3d_dev);
1353
1354         glamo_jpeg_dev.dev.parent = &pdev->dev;
1355         mangle_mem_resources(glamo_jpeg_dev.resource,
1356                              glamo_jpeg_dev.num_resources, glamo->mem);
1357         platform_device_register(&glamo_jpeg_dev);
1358
1359         glamo_mpeg_dev.dev.parent = &pdev->dev;
1360         mangle_mem_resources(glamo_mpeg_dev.resource,
1361                              glamo_mpeg_dev.num_resources, glamo->mem);
1362         platform_device_register(&glamo_mpeg_dev);
1363
1364         glamo->pdata->glamo = glamo;
1365         glamo_fb_dev.dev.parent = &pdev->dev;
1366         glamo_fb_dev.dev.platform_data = glamo->pdata;
1367         mangle_mem_resources(glamo_fb_dev.resource,
1368                              glamo_fb_dev.num_resources, glamo->mem);
1369         platform_device_register(&glamo_fb_dev);
1370
1371         glamo->pdata->spigpio_info->glamo = glamo;
1372         glamo_spigpio_dev.dev.parent = &pdev->dev;
1373         glamo_spigpio_dev.dev.platform_data = glamo->pdata->spigpio_info;
1374         platform_device_register(&glamo_spigpio_dev);
1375
1376         glamo_mmc_dev = glamo->pdata->mmc_dev;
1377         glamo_mmc_dev->name = "glamo-mci";
1378         glamo_mmc_dev->dev.parent = &pdev->dev;
1379         glamo_mmc_dev->resource = glamo_mmc_resources;
1380         glamo_mmc_dev->num_resources = ARRAY_SIZE(glamo_mmc_resources);
1381
1382         /* we need it later to give to the engine enable and disable */
1383         glamo_mci_def_pdata.pglamo = glamo;
1384         mangle_mem_resources(glamo_mmc_dev->resource,
1385                              glamo_mmc_dev->num_resources, glamo->mem);
1386         platform_device_register(glamo_mmc_dev);
1387
1388         /* only request the generic, hostbus and memory controller MMIO */
1389         glamo->mem = request_mem_region(glamo->mem->start,
1390                                         GLAMO_REGOFS_VIDCAP, "glamo-core");
1391         if (!glamo->mem) {
1392                 dev_err(&pdev->dev, "failed to request memory region\n");
1393                 goto bail_irq;
1394         }
1395
1396         return 0;
1397
1398 bail_irq:
1399         disable_irq(glamo->irq);
1400         set_irq_chained_handler(glamo->irq, NULL);
1401
1402         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1403                 set_irq_flags(irq, 0);
1404                 set_irq_chip(irq, NULL);
1405         }
1406
1407         iounmap(glamo->base);
1408 bail_free:
1409         platform_set_drvdata(pdev, NULL);
1410         glamo_handle = NULL;
1411         kfree(glamo);
1412
1413         return rc;
1414 }
1415
1416 static int glamo_remove(struct platform_device *pdev)
1417 {
1418         struct glamo_core *glamo = platform_get_drvdata(pdev);
1419         int irq;
1420
1421         disable_irq(glamo->irq);
1422         set_irq_chained_handler(glamo->irq, NULL);
1423
1424         for (irq = IRQ_GLAMO(0); irq <= IRQ_GLAMO(8); irq++) {
1425                 set_irq_flags(irq, 0);
1426                 set_irq_chip(irq, NULL);
1427         }
1428
1429         platform_set_drvdata(pdev, NULL);
1430         platform_device_unregister(&glamo_fb_dev);
1431         platform_device_unregister(glamo->pdata->mmc_dev);
1432         iounmap(glamo->base);
1433         release_mem_region(glamo->mem->start, GLAMO_REGOFS_VIDCAP);
1434         glamo_handle = NULL;
1435         kfree(glamo);
1436
1437         return 0;
1438 }
1439
1440 #ifdef CONFIG_PM
1441
1442 static int glamo_suspend(struct platform_device *pdev, pm_message_t state)
1443 {
1444         glamo_handle->suspending = 1;
1445         glamo_power(glamo_handle, GLAMO_POWER_SUSPEND);
1446
1447         return 0;
1448 }
1449
1450 static int glamo_resume(struct platform_device *pdev)
1451 {
1452         glamo_power(glamo_handle, GLAMO_POWER_ON);
1453         glamo_handle->suspending = 0;
1454
1455         return 0;
1456 }
1457
1458 #else
1459 #define glamo_suspend NULL
1460 #define glamo_resume  NULL
1461 #endif
1462
1463 static struct platform_driver glamo_driver = {
1464         .probe          = glamo_probe,
1465         .remove         = glamo_remove,
1466         .suspend        = glamo_suspend,
1467         .resume = glamo_resume,
1468         .driver         = {
1469                 .name   = "glamo3362",
1470                 .owner  = THIS_MODULE,
1471         },
1472 };
1473
1474 static int __devinit glamo_init(void)
1475 {
1476         return platform_driver_register(&glamo_driver);
1477 }
1478
1479 static void __exit glamo_cleanup(void)
1480 {
1481         platform_driver_unregister(&glamo_driver);
1482 }
1483
1484 module_init(glamo_init);
1485 module_exit(glamo_cleanup);
1486
1487 MODULE_AUTHOR("Harald Welte <laforge@openmoko.org>");
1488 MODULE_DESCRIPTION("Smedia Glamo 336x/337x core/resource driver");
1489 MODULE_LICENSE("GPL");