target/linux/rb532-2.6/patches/100-rb5xx_support.patch

   1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
   2 --- linux.old/arch/mips/Kconfig 2006-11-29 22:57:37.000000000 +0100
   3 +++ linux.dev/arch/mips/Kconfig 2006-12-14 04:09:50.000000000 +0100
   4 @@ -728,6 +728,19 @@
   5         select SYS_SUPPORTS_BIG_ENDIAN
   6         select TOSHIBA_BOARDS
   7
   8 +config MIKROTIK_RB500
   9 +       bool "Support for RB5xx boards"
  10 +       select HW_HAS_PCI
  11 +       select IRQ_CPU
  12 +       select SYS_HAS_CPU_MIPS32_R1
  13 +       select SYS_SUPPORTS_LITTLE_ENDIAN
  14 +       select SYS_SUPPORTS_32BIT_KERNEL
  15 +       select SWAP_IO_SPACE
  16 +       select DMA_NONCOHERENT
  17 +       help
  18 +         Support the Mikrotik(tm) Routerboard 500 series,
  19 +         such as the RB532.
  20 +
  21  config TOSHIBA_RBTX4927
  22         bool "Toshiba TBTX49[23]7 board"
  23         select DMA_NONCOHERENT
  24 @@ -1015,7 +1028,7 @@
  25
  26  config MIPS_L1_CACHE_SHIFT
  27         int
  28 -       default "4" if MACH_DECSTATION
  29 +       default "4" if MACH_DECSTATION || MIKROTIK_RB500
  30         default "7" if SGI_IP27
  31         default "5"
  32
  33 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
  34 --- linux.old/arch/mips/Makefile        2006-12-14 03:13:55.000000000 +0100
  35 +++ linux.dev/arch/mips/Makefile        2006-12-14 04:09:50.000000000 +0100
  36 @@ -586,6 +586,13 @@
  37  load-$(CONFIG_TOSHIBA_JMR3927) += 0xffffffff80050000
  38
  39  #
  40 +# Routerboard 532 board
  41 +#
  42 +core-$(CONFIG_MIKROTIK_RB500)  += arch/mips/rb500/
  43 +cflags-$(CONFIG_MIKROTIK_RB500) += -Iinclude/asm-mips/rc32434
  44 +load-$(CONFIG_MIKROTIK_RB500)  += 0xffffffff80101000
  45 +
  46 +#
  47  # Toshiba RBTX4927 board or
  48  # Toshiba RBTX4937 board
  49  #
  50 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
  51 --- linux.old/arch/mips/mm/tlbex.c      2006-11-29 22:57:37.000000000 +0100
  52 +++ linux.dev/arch/mips/mm/tlbex.c      2006-12-14 04:09:50.000000000 +0100
  53 @@ -874,7 +874,6 @@
  54         case CPU_R10000:
  55         case CPU_R12000:
  56         case CPU_R14000:
  57 -       case CPU_4KC:
  58         case CPU_SB1:
  59         case CPU_SB1A:
  60         case CPU_4KSC:
  61 @@ -902,6 +901,7 @@
  62                 tlbw(p);
  63                 break;
  64
  65 +       case CPU_4KC:
  66         case CPU_4KEC:
  67         case CPU_24K:
  68         case CPU_34K:
  69 diff -urN linux.old/arch/mips/pci/fixup-rb500.c linux.dev/arch/mips/pci/fixup-rb500.c
  70 --- linux.old/arch/mips/pci/fixup-rb500.c       1970-01-01 01:00:00.000000000 +0100
  71 +++ linux.dev/arch/mips/pci/fixup-rb500.c       2006-12-14 04:09:50.000000000 +0100
  72 @@ -0,0 +1,49 @@
  73 +/*
  74 + * Copyright 2001 MontaVista Software Inc.
  75 + * Author: MontaVista Software, Inc.
  76 + *             stevel@mvista.com or source@mvista.com
  77 + *
  78 + *  This program is free software; you can redistribute  it and/or modify it
  79 + *  under  the terms of  the GNU General  Public License as published by the
  80 + *  Free Software Foundation;  either version 2 of the  License, or (at your
  81 + *  option) any later version.
  82 + *
  83 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  84 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  85 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  86 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  87 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  88 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  89 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  90 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  91 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  92 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  93 + *
  94 + *  You should have received a copy of the  GNU General Public License along
  95 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
  96 + *  675 Mass Ave, Cambridge, MA 02139, USA.
  97 + */
  98 +
  99 +#include <linux/autoconf.h>
 100 +#include <linux/types.h>
 101 +#include <linux/pci.h>
 102 +#include <linux/kernel.h>
 103 +#include <linux/init.h>
 104 +
 105 +#include <asm/rc32434/rc32434.h>
 106 +
 107 +static int __devinitdata irq_map[2][12] = {
 108 +       { 0, 0, 2, 3, 2, 3, 0, 0, 0, 0, 0, 1 },
 109 +       { 0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3 }
 110 +};
 111 +
 112 +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 113 +{
 114 +       int irq = 0;
 115 +
 116 +       if (dev->bus->number < 2 && PCI_SLOT(dev->devfn) < 12) {
 117 +               irq = irq_map[dev->bus->number][PCI_SLOT(dev->devfn)];
 118 +       }
 119 +       return irq + GROUP4_IRQ_BASE + 4;
 120 +}
 121 +
 122 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
 123 --- linux.old/arch/mips/pci/Makefile    2006-11-29 22:57:37.000000000 +0100
 124 +++ linux.dev/arch/mips/pci/Makefile    2006-12-14 04:09:50.000000000 +0100
 125 @@ -53,3 +53,4 @@
 126  obj-$(CONFIG_VICTOR_MPC30X)    += fixup-mpc30x.o
 127  obj-$(CONFIG_ZAO_CAPCELLA)     += fixup-capcella.o
 128  obj-$(CONFIG_WR_PPMC)          += fixup-wrppmc.o
 129 +obj-$(CONFIG_MIKROTIK_RB500)   += pci-rc32434.o ops-rc32434.o fixup-rb500.o
 130 diff -urN linux.old/arch/mips/pci/ops-rc32434.c linux.dev/arch/mips/pci/ops-rc32434.c
 131 --- linux.old/arch/mips/pci/ops-rc32434.c       1970-01-01 01:00:00.000000000 +0100
 132 +++ linux.dev/arch/mips/pci/ops-rc32434.c       2006-12-14 04:09:50.000000000 +0100
 133 @@ -0,0 +1,218 @@
 134 +/**************************************************************************
 135 + *
 136 + *  BRIEF MODULE DESCRIPTION
 137 + *     pci_ops for IDT EB434 board
 138 + *
 139 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 140 + *  Copyright 2006 Felix Fietkau <nbd@openwrt.org>
 141 + *
 142 + *  This program is free software; you can redistribute  it and/or modify it
 143 + *  under  the terms of  the GNU General  Public License as published by the
 144 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 145 + *  option) any later version.
 146 + *
 147 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 148 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 149 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 150 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 151 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 152 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 153 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 154 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 155 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 156 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 157 + *
 158 + *  You should have received a copy of the  GNU General Public License along
 159 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 160 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 161 + *
 162 + *
 163 + **************************************************************************
 164 + * May 2004 rkt, neb
 165 + *
 166 + * Initial Release
 167 + *
 168 + *
 169 + *
 170 + **************************************************************************
 171 + */
 172 +
 173 +#include <linux/autoconf.h>
 174 +#include <linux/init.h>
 175 +#include <linux/pci.h>
 176 +#include <linux/types.h>
 177 +#include <linux/delay.h>
 178 +
 179 +#include <asm/cpu.h>
 180 +#include <asm/io.h>
 181 +
 182 +#include <asm/rc32434/rc32434.h>
 183 +#include <asm/rc32434/pci.h>
 184 +
 185 +#define PCI_ACCESS_READ  0
 186 +#define PCI_ACCESS_WRITE 1
 187 +
 188 +
 189 +#define PCI_CFG_SET(bus,slot,func,off) \
 190 +       (rc32434_pci->pcicfga = (0x80000000 | \
 191 +                               ((bus) << 16) | ((slot)<<11) | \
 192 +                               ((func)<<8) | (off)))
 193 +
 194 +static inline int config_access(unsigned char access_type, struct pci_bus *bus,
 195 +                         unsigned int devfn, unsigned char where,
 196 +                         u32 * data)
 197 +{
 198 +       unsigned int slot = PCI_SLOT(devfn);
 199 +       u8 func = PCI_FUNC(devfn);
 200 +
 201 +       /* Setup address */
 202 +       PCI_CFG_SET(bus->number, slot, func, where);
 203 +       rc32434_sync();
 204 +
 205 +       if (access_type == PCI_ACCESS_WRITE)
 206 +               rc32434_pci->pcicfgd = *data;
 207 +       else
 208 +               *data = rc32434_pci->pcicfgd;
 209 +
 210 +       rc32434_sync();
 211 +
 212 +       return 0;
 213 +}
 214 +
 215 +
 216 +/*
 217 + * We can't address 8 and 16 bit words directly.  Instead we have to
 218 + * read/write a 32bit word and mask/modify the data we actually want.
 219 + */
 220 +static int read_config_byte(struct pci_bus *bus, unsigned int devfn,
 221 +                            int where, u8 * val)
 222 +{
 223 +       u32 data;
 224 +       int ret;
 225 +
 226 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 227 +       *val = (data >> ((where & 3) << 3)) & 0xff;
 228 +       return ret;
 229 +}
 230 +
 231 +static int read_config_word(struct pci_bus *bus, unsigned int devfn,
 232 +                            int where, u16 * val)
 233 +{
 234 +       u32 data;
 235 +       int ret;
 236 +
 237 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data);
 238 +       *val = (data >> ((where & 3) << 3)) & 0xffff;
 239 +       return ret;
 240 +}
 241 +
 242 +static int read_config_dword(struct pci_bus *bus, unsigned int devfn,
 243 +                             int where, u32 * val)
 244 +{
 245 +       int ret;
 246 +       int delay = 1;
 247 +
 248 +       if (bus->number == 0 && PCI_SLOT(devfn) > 21)
 249 +               return 0;
 250 +
 251 +retry:
 252 +       ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val);
 253 +
 254 +       /* PCI scan: check for invalid values, device may not have
 255 +        * finished initializing */
 256 +
 257 +       if (where == PCI_VENDOR_ID) {
 258 +               if (ret == 0xffffffff || ret == 0x00000000 ||
 259 +                       ret == 0x0000ffff || ret == 0xffff0000) {
 260 +
 261 +                       if (delay > 4)
 262 +                               return 0;
 263 +
 264 +                       delay *= 2;
 265 +                       msleep(delay);
 266 +                       goto retry;
 267 +               }
 268 +       }
 269 +
 270 +       return ret;
 271 +}
 272 +
 273 +static int
 274 +write_config_byte(struct pci_bus *bus, unsigned int devfn, int where,
 275 +                  u8 val)
 276 +{
 277 +       u32 data = 0;
 278 +
 279 +       if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 280 +               return -1;
 281 +
 282 +       data = (data & ~(0xff << ((where & 3) << 3))) |
 283 +               (val << ((where & 3) << 3));
 284 +
 285 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 286 +               return -1;
 287 +
 288 +       return PCIBIOS_SUCCESSFUL;
 289 +}
 290 +
 291 +
 292 +static int
 293 +write_config_word(struct pci_bus *bus, unsigned int devfn, int where,
 294 +                  u16 val)
 295 +{
 296 +       u32 data = 0;
 297 +
 298 +       if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data))
 299 +               return -1;
 300 +
 301 +       data = (data & ~(0xffff << ((where & 3) << 3))) |
 302 +               (val << ((where & 3) << 3));
 303 +
 304 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data))
 305 +               return -1;
 306 +
 307 +
 308 +       return PCIBIOS_SUCCESSFUL;
 309 +}
 310 +
 311 +
 312 +static int
 313 +write_config_dword(struct pci_bus *bus, unsigned int devfn, int where,
 314 +                   u32 val)
 315 +{
 316 +       if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val))
 317 +               return -1;
 318 +
 319 +       return PCIBIOS_SUCCESSFUL;
 320 +}
 321 +
 322 +static int pci_config_read(struct pci_bus *bus, unsigned int devfn,
 323 +                          int where, int size, u32 * val)
 324 +{
 325 +       switch (size) {
 326 +       case 1:
 327 +               return read_config_byte(bus, devfn, where, (u8 *) val);
 328 +       case 2:
 329 +               return read_config_word(bus, devfn, where, (u16 *) val);
 330 +       default:
 331 +               return read_config_dword(bus, devfn, where, val);
 332 +       }
 333 +}
 334 +
 335 +static int pci_config_write(struct pci_bus *bus, unsigned int devfn,
 336 +                           int where, int size, u32 val)
 337 +{
 338 +       switch (size) {
 339 +       case 1:
 340 +               return write_config_byte(bus, devfn, where, (u8) val);
 341 +       case 2:
 342 +               return write_config_word(bus, devfn, where, (u16) val);
 343 +       default:
 344 +               return write_config_dword(bus, devfn, where, val);
 345 +       }
 346 +}
 347 +
 348 +struct pci_ops rc32434_pci_ops = {
 349 +       .read =  pci_config_read,
 350 +       .write = pci_config_write,
 351 +};
 352 diff -urN linux.old/arch/mips/pci/pci-rc32434.c linux.dev/arch/mips/pci/pci-rc32434.c
 353 --- linux.old/arch/mips/pci/pci-rc32434.c       1970-01-01 01:00:00.000000000 +0100
 354 +++ linux.dev/arch/mips/pci/pci-rc32434.c       2006-12-14 04:09:50.000000000 +0100
 355 @@ -0,0 +1,234 @@
 356 +/**************************************************************************
 357 + *
 358 + *  BRIEF MODULE DESCRIPTION
 359 + *     PCI initialization for IDT EB434 board
 360 + *
 361 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
 362 + *
 363 + *  This program is free software; you can redistribute  it and/or modify it
 364 + *  under  the terms of  the GNU General  Public License as published by the
 365 + *  Free Software Foundation;  either version 2 of the  License, or (at your
 366 + *  option) any later version.
 367 + *
 368 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 369 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 370 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 371 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 372 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 373 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 374 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 375 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 376 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 377 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 378 + *
 379 + *  You should have received a copy of the  GNU General Public License along
 380 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 381 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 382 + *
 383 + *
 384 + **************************************************************************
 385 + * May 2004 rkt, neb
 386 + *
 387 + * Initial Release
 388 + *
 389 + *
 390 + *
 391 + **************************************************************************
 392 + */
 393 +
 394 +#include <linux/autoconf.h>
 395 +#include <linux/types.h>
 396 +#include <linux/pci.h>
 397 +#include <linux/kernel.h>
 398 +#include <linux/init.h>
 399 +
 400 +#include <asm/rc32434/rc32434.h>
 401 +#include <asm/rc32434/pci.h>
 402 +
 403 +#define PCI_ACCESS_READ  0
 404 +#define PCI_ACCESS_WRITE 1
 405 +
 406 +/* define an unsigned array for the PCI registers */
 407 +unsigned int korinaCnfgRegs[25] = {
 408 +       KORINA_CNFG1,    KORINA_CNFG2,  KORINA_CNFG3,  KORINA_CNFG4,
 409 +       KORINA_CNFG5,    KORINA_CNFG6,  KORINA_CNFG7,  KORINA_CNFG8,
 410 +       KORINA_CNFG9,    KORINA_CNFG10, KORINA_CNFG11, KORINA_CNFG12,
 411 +       KORINA_CNFG13, KORINA_CNFG14, KORINA_CNFG15, KORINA_CNFG16,
 412 +       KORINA_CNFG17, KORINA_CNFG18, KORINA_CNFG19, KORINA_CNFG20,
 413 +       KORINA_CNFG21, KORINA_CNFG22, KORINA_CNFG23, KORINA_CNFG24
 414 +};
 415 +static struct resource rc32434_res_pci_mem1;
 416 +static struct resource rc32434_res_pci_mem2;
 417 +
 418 +static struct resource rc32434_res_pci_mem1 = {
 419 +       .name = "PCI MEM1",
 420 +       .start = 0x50000000,
 421 +       .end = 0x5FFFFFFF,
 422 +       .flags = IORESOURCE_MEM,
 423 +       .parent = &rc32434_res_pci_mem1,
 424 +       .sibling = NULL,
 425 +       .child = &rc32434_res_pci_mem2
 426 +};
 427 +
 428 +static struct resource rc32434_res_pci_mem2 = {
 429 +       .name = "PCI Mem2",
 430 +       .start = 0x60000000,
 431 +       .end = 0x6FFFFFFF,
 432 +       .flags = IORESOURCE_MEM,
 433 +       .parent = &rc32434_res_pci_mem1,
 434 +       .sibling = NULL,
 435 +       .child = NULL
 436 +};
 437 +
 438 +static struct resource rc32434_res_pci_io1 = {
 439 +       .name = "PCI I/O1",
 440 +       .start = 0x18800000,
 441 +       .end = 0x188FFFFF,
 442 +       .flags = IORESOURCE_IO,
 443 +};
 444 +
 445 +extern struct pci_ops rc32434_pci_ops;
 446 +
 447 +#define PCI_MEM1_START PCI_ADDR_START
 448 +#define PCI_MEM1_END   PCI_ADDR_START + CPUTOPCI_MEM_WIN - 1
 449 +#define PCI_MEM2_START PCI_ADDR_START + CPUTOPCI_MEM_WIN
 450 +#define PCI_MEM2_END   PCI_ADDR_START + ( 2* CPUTOPCI_MEM_WIN)  - 1
 451 +#define PCI_IO1_START  PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN)
 452 +#define PCI_IO1_END    PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN -1
 453 +#define PCI_IO2_START  PCI_ADDR_START + (2 * CPUTOPCI_MEM_WIN) + CPUTOPCI_IO_WIN
 454 +#define PCI_IO2_END    PCI_ADDR_START + (2* CPUTOPCI_MEM_WIN) + (2 * CPUTOPCI_IO_WIN) -1
 455 +
 456 +
 457 +struct pci_controller rc32434_controller2;
 458 +
 459 +struct pci_controller rc32434_controller = {
 460 +       .pci_ops        = &rc32434_pci_ops,
 461 +       .mem_resource   = &rc32434_res_pci_mem1,
 462 +       .io_resource    = &rc32434_res_pci_io1,
 463 +       .mem_offset     = 0,
 464 +       .io_offset      = 0,
 465 +
 466 +};
 467 +
 468 +#ifdef __MIPSEB__
 469 +#define PCI_ENDIAN_FLAG PCILBAC_sb_m
 470 +#else
 471 +#define PCI_ENDIAN_FLAG 0
 472 +#endif
 473 +
 474 +static int __init rc32434_pcibridge_init(void)
 475 +{
 476 +       unsigned int pcicValue, pcicData = 0;
 477 +       unsigned int dummyRead, pciCntlVal;
 478 +       int loopCount;
 479 +       unsigned int pciConfigAddr;
 480 +
 481 +       pcicValue = rc32434_pci->pcic;
 482 +       pcicValue = (pcicValue >> PCIM_SHFT) & PCIM_BIT_LEN;
 483 +       if (!((pcicValue == PCIM_H_EA) ||
 484 +                (pcicValue == PCIM_H_IA_FIX) ||
 485 +               (pcicValue == PCIM_H_IA_RR))) {
 486 +               printk("PCI init error!!!\n");
 487 +               /* Not in Host Mode, return ERROR */
 488 +               return -1;
 489 +       }
 490 +       /* Enables the Idle Grant mode, Arbiter Parking */
 491 +       pcicData |=(PCIC_igm_m|PCIC_eap_m|PCIC_en_m);
 492 +       rc32434_pci->pcic = pcicData; /* Enable the PCI bus Interface */
 493 +       /* Zero out the PCI status & PCI Status Mask */
 494 +       for(;;)
 495 +       {
 496 +          pcicData = rc32434_pci->pcis;
 497 +          if (!(pcicData & PCIS_rip_m))
 498 +                   break;
 499 +       }
 500 +
 501 +       rc32434_pci->pcis = 0;
 502 +       rc32434_pci->pcism = 0xFFFFFFFF;
 503 +       /* Zero out the PCI decoupled registers */
 504 +       rc32434_pci->pcidac=0; /* disable PCI decoupled accesses at initialization */
 505 +       rc32434_pci->pcidas=0; /* clear the status */
 506 +       rc32434_pci->pcidasm=0x0000007F; /* Mask all the interrupts */
 507 +       /* Mask PCI Messaging Interrupts */
 508 +       rc32434_pci_msg->pciiic = 0;
 509 +       rc32434_pci_msg->pciiim = 0xFFFFFFFF;
 510 +       rc32434_pci_msg->pciioic = 0;
 511 +       rc32434_pci_msg->pciioim = 0;
 512 +
 513 +
 514 +       /* Setup PCILB0 as Memory Window */
 515 +       rc32434_pci->pcilba[0].a = (unsigned int) (PCI_ADDR_START);
 516 +
 517 +       /* setup the PCI map address as same as the local address */
 518 +
 519 +       rc32434_pci->pcilba[0].m = (unsigned int) (PCI_ADDR_START);
 520 +
 521 +
 522 +       /* Setup PCILBA1 as MEM */
 523 +       rc32434_pci->pcilba[0].c = ( ((SIZE_256MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG);
 524 +       dummyRead = rc32434_pci->pcilba[0].c; /* flush the CPU write Buffers */
 525 +       rc32434_pci->pcilba[1].a = 0x60000000;
 526 +       rc32434_pci->pcilba[1].m = 0x60000000;
 527 +
 528 +       /* setup PCILBA2 as IO Window*/
 529 +       rc32434_pci->pcilba[1].c = (((SIZE_256MB & 0x1f) << PCILBAC_size_b )| PCI_ENDIAN_FLAG);
 530 +       dummyRead = rc32434_pci->pcilba[1].c; /* flush the CPU write Buffers */
 531 +       rc32434_pci->pcilba[2].a = 0x18C00000;
 532 +       rc32434_pci->pcilba[2].m = 0x18FFFFFF;
 533 +
 534 +       /* setup PCILBA2 as IO Window*/
 535 +       rc32434_pci->pcilba[2].c = (((SIZE_4MB & 0x1f) << PCILBAC_size_b) | PCI_ENDIAN_FLAG );
 536 +       dummyRead = rc32434_pci->pcilba[2].c; /* flush the CPU write Buffers */
 537 +
 538 +       /* Setup PCILBA3 as IO Window */
 539 +       rc32434_pci->pcilba[3].a = 0x18800000;
 540 +       rc32434_pci->pcilba[3].m = 0x18800000;
 541 +       rc32434_pci->pcilba[3].c = ( (((SIZE_1MB & 0x1ff) << PCILBAC_size_b) | PCILBAC_msi_m) | PCI_ENDIAN_FLAG);
 542 +       dummyRead = rc32434_pci->pcilba[3].c; /* flush the CPU write Buffers */
 543 +
 544 +       pciConfigAddr=(unsigned int)(0x80000004);
 545 +       for(loopCount=0;loopCount<24;loopCount++){
 546 +               rc32434_pci->pcicfga=pciConfigAddr;
 547 +               dummyRead=rc32434_pci->pcicfga;
 548 +               rc32434_pci->pcicfgd = korinaCnfgRegs[loopCount];
 549 +               dummyRead=rc32434_pci->pcicfgd;
 550 +               pciConfigAddr += 4;
 551 +       }
 552 +       rc32434_pci->pcitc = (unsigned int)((PCITC_RTIMER_VAL&0xff) << PCITC_rtimer_b)
 553 +               | ((PCITC_DTIMER_VAL&0xff) << PCITC_dtimer_b);
 554 +
 555 +       pciCntlVal=rc32434_pci->pcic;
 556 +       pciCntlVal &=~(PCIC_tnr_m);
 557 +       rc32434_pci->pcic = pciCntlVal;
 558 +       pciCntlVal=rc32434_pci->pcic;
 559 +       return 0;
 560 +}
 561 +
 562 +/* Do platform specific device initialization at pci_enable_device() time */
 563 +int pcibios_plat_dev_init(struct pci_dev *dev)
 564 +{
 565 +       if (PCI_SLOT(dev->devfn) == 6 && dev->bus->number == 0) {
 566 +               /* disable prefetched memory range */
 567 +               pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
 568 +               pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0x10);
 569 +
 570 +               pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 4);
 571 +       }
 572 +       return 0;
 573 +}
 574 +
 575 +static int __init rc32434_pci_init(void)
 576 +{
 577 +       printk("PCI: Initializing PCI\n");
 578 +
 579 +       ioport_resource.start = rc32434_res_pci_io1.start;
 580 +       ioport_resource.end = rc32434_res_pci_io1.end;
 581 +
 582 +       rc32434_pcibridge_init();
 583 +
 584 +       register_pci_controller(&rc32434_controller);
 585 +       rc32434_sync();
 586 +}
 587 +
 588 +arch_initcall(rc32434_pci_init);
 589 +
 590 diff -urN linux.old/arch/mips/rb500/devices.c linux.dev/arch/mips/rb500/devices.c
 591 --- linux.old/arch/mips/rb500/devices.c 1970-01-01 01:00:00.000000000 +0100
 592 +++ linux.dev/arch/mips/rb500/devices.c 2006-12-14 04:09:50.000000000 +0100
 593 @@ -0,0 +1,210 @@
 594 +/*
 595 + *  RouterBoard 500 Platform devices
 596 + *
 597 + *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
 598 + *
 599 + *  This program is free software; you can redistribute it and/or modify
 600 + *  it under the terms of the GNU General Public License as published by
 601 + *  the Free Software Foundation; either version 2 of the License, or
 602 + *  (at your option) any later version.
 603 + *
 604 + *  This program is distributed in the hope that it will be useful,
 605 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 606 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 607 + *  GNU General Public License for more details.
 608 + *
 609 + *  $Id$
 610 + */
 611 +#include <linux/kernel.h>
 612 +#include <linux/init.h>
 613 +#include <linux/module.h>
 614 +#include <linux/ctype.h>
 615 +#include <linux/string.h>
 616 +#include <linux/platform_device.h>
 617 +#include <asm/unaligned.h>
 618 +#include <asm/io.h>
 619 +
 620 +#include <asm/rc32434/rc32434.h>
 621 +#include <asm/rc32434/dma.h>
 622 +#include <asm/rc32434/dma_v.h>
 623 +#include <asm/rc32434/eth.h>
 624 +#include <asm/rc32434/rb.h>
 625 +
 626 +#define ETH0_DMA_RX_IRQ        GROUP1_IRQ_BASE + 0
 627 +#define ETH0_DMA_TX_IRQ        GROUP1_IRQ_BASE + 1
 628 +#define ETH0_RX_OVR_IRQ        GROUP3_IRQ_BASE + 9
 629 +#define ETH0_TX_UND_IRQ        GROUP3_IRQ_BASE + 10
 630 +
 631 +#define ETH0_RX_DMA_ADDR  (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
 632 +#define ETH0_TX_DMA_ADDR  (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
 633 +
 634 +static struct resource korina_dev0_res[] = {
 635 +       {
 636 +               .name  = "korina_regs",
 637 +               .start = ETH0_PhysicalAddress,
 638 +               .end   = ETH0_PhysicalAddress + sizeof(ETH_t),
 639 +               .flags = IORESOURCE_MEM,
 640 +       },
 641 +       {
 642 +               .name  = "korina_rx",
 643 +               .start = ETH0_DMA_RX_IRQ,
 644 +               .end   = ETH0_DMA_RX_IRQ,
 645 +               .flags = IORESOURCE_IRQ
 646 +       },
 647 +       {
 648 +               .name  = "korina_tx",
 649 +               .start = ETH0_DMA_TX_IRQ,
 650 +               .end   = ETH0_DMA_TX_IRQ,
 651 +               .flags = IORESOURCE_IRQ
 652 +       },
 653 +       {
 654 +               .name  = "korina_ovr",
 655 +               .start = ETH0_RX_OVR_IRQ,
 656 +               .end   = ETH0_RX_OVR_IRQ,
 657 +               .flags = IORESOURCE_IRQ
 658 +       },
 659 +       {
 660 +               .name  = "korina_und",
 661 +               .start = ETH0_TX_UND_IRQ,
 662 +               .end   = ETH0_TX_UND_IRQ,
 663 +               .flags = IORESOURCE_IRQ
 664 +       },
 665 +       {
 666 +               .name  = "korina_dma_rx",
 667 +               .start = ETH0_RX_DMA_ADDR,
 668 +               .end   = ETH0_RX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
 669 +               .flags = IORESOURCE_MEM,
 670 +       },
 671 +       {
 672 +               .name  = "korina_dma_tx",
 673 +               .start = ETH0_TX_DMA_ADDR,
 674 +               .end   = ETH0_TX_DMA_ADDR + DMA_CHAN_OFFSET - 1,
 675 +               .flags = IORESOURCE_MEM,
 676 +       }
 677 +};
 678 +
 679 +static struct korina_device korina_dev0_data = {
 680 +       .name = "korina0",
 681 +       .mac = { 0xde, 0xca, 0xff, 0xc0, 0xff, 0xee }
 682 +};
 683 +
 684 +static struct platform_device korina_dev0 = {
 685 +       .id = 0,
 686 +       .name = "korina",
 687 +       .dev.platform_data = &korina_dev0_data,
 688 +       .resource = korina_dev0_res,
 689 +       .num_resources = ARRAY_SIZE(korina_dev0_res),
 690 +};
 691 +
 692 +
 693 +#define CF_GPIO_NUM 13
 694 +
 695 +static struct resource cf_slot0_res[] = {
 696 +       {
 697 +               .name  = "cf_membase",
 698 +               .flags = IORESOURCE_MEM
 699 +       },
 700 +       {
 701 +               .name  = "cf_irq",
 702 +               .start = (8 + 4 * 32 + CF_GPIO_NUM),  /* 149 */
 703 +               .end   = (8 + 4 * 32 + CF_GPIO_NUM),
 704 +               .flags = IORESOURCE_IRQ
 705 +       }
 706 +};
 707 +
 708 +static struct cf_device cf_slot0_data = {
 709 +       .gpio_pin = 13
 710 +};
 711 +
 712 +static struct platform_device cf_slot0 = {
 713 +       .id = 0,
 714 +       .name = "rb500-cf",
 715 +       .dev.platform_data = &cf_slot0_data,
 716 +       .resource = cf_slot0_res,
 717 +       .num_resources = ARRAY_SIZE(cf_slot0_res),
 718 +};
 719 +
 720 +/* Resources and device for NAND.  There is no data needed and no irqs, so just define the memory used. */
 721 +static struct resource nand_slot0_res[] = {
 722 +       {
 723 +               .name = "nand_membase",
 724 +               .flags = IORESOURCE_MEM
 725 +       }
 726 +};
 727 +
 728 +static struct platform_device nand_slot0 = {
 729 +       .id = 0,
 730 +       .name = "rb500-nand",
 731 +       .resource = nand_slot0_res,
 732 +       .num_resources = ARRAY_SIZE(nand_slot0_res),
 733 +};
 734 +
 735 +
 736 +static struct platform_device *rb500_devs[] = {
 737 +       &korina_dev0,
 738 +       &nand_slot0,
 739 +       &cf_slot0
 740 +};
 741 +
 742 +static void __init parse_mac_addr(char* macstr)
 743 +{
 744 +       int i, j;
 745 +       unsigned char result, value;
 746 +
 747 +       for (i=0; i<6; i++) {
 748 +               result = 0;
 749 +               if (i != 5 && *(macstr+2) != ':') {
 750 +                       return;
 751 +               }
 752 +               for (j=0; j<2; j++) {
 753 +                       if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
 754 +                                                 toupper(*macstr)-'A'+10) < 16) {
 755 +                               result = result*16 + value;
 756 +                               macstr++;
 757 +                       }
 758 +                       else return;
 759 +               }
 760 +
 761 +               macstr++;
 762 +               korina_dev0_data.mac[i] = result;
 763 +       }
 764 +}
 765 +
 766 +
 767 +/* DEVICE CONTROLLER 1 */
 768 +#define CFG_DC_DEV1 (void*)0xb8010010
 769 +#define CFG_DC_DEV2 (void*)0xb8010020
 770 +#define CFG_DC_DEVBASE    0x0
 771 +#define CFG_DC_DEVMASK    0x4
 772 +#define CFG_DC_DEVC       0x8
 773 +#define CFG_DC_DEVTC      0xC
 774 +
 775 +
 776 +static int __init plat_setup_devices(void)
 777 +{
 778 +       /* Look for the CF card reader */
 779 +       if (!readl(CFG_DC_DEV1 + CFG_DC_DEVMASK))
 780 +               rb500_devs[1] = NULL;
 781 +       else {
 782 +               cf_slot0_res[0].start = readl(CFG_DC_DEV1 + CFG_DC_DEVBASE);
 783 +               cf_slot0_res[0].end = cf_slot0_res[0].start + 0x1000;
 784 +       }
 785 +
 786 +       /* There is always a NAND device */
 787 +       nand_slot0_res[0].start = readl( CFG_DC_DEV2 + CFG_DC_DEVBASE);
 788 +       nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000;
 789 +
 790 +       return platform_add_devices(rb500_devs, ARRAY_SIZE(rb500_devs));
 791 +}
 792 +
 793 +static int __init setup_kmac(char *s)
 794 +{
 795 +    printk("korina mac = %s\n",s);
 796 +       parse_mac_addr(s);
 797 +    return 0;
 798 +}
 799 +
 800 +__setup("kmac=", setup_kmac);
 801 +arch_initcall(plat_setup_devices);
 802 +
 803 +
 804 diff -urN linux.old/arch/mips/rb500/irq.c linux.dev/arch/mips/rb500/irq.c
 805 --- linux.old/arch/mips/rb500/irq.c     1970-01-01 01:00:00.000000000 +0100
 806 +++ linux.dev/arch/mips/rb500/irq.c     2006-12-14 04:14:16.000000000 +0100
 807 @@ -0,0 +1,264 @@
 808 +/*
 809 + * BRIEF MODULE DESCRIPTION
 810 + *     RC32434 interrupt routines.
 811 + *
 812 + * Copyright 2002 MontaVista Software Inc.
 813 + * Author: MontaVista Software, Inc.
 814 + *             stevel@mvista.com or source@mvista.com
 815 + *
 816 + *  This program is free software; you can redistribute         it and/or modify it
 817 + *  under  the terms of         the GNU General  Public License as published by the
 818 + *  Free Software Foundation;  either version 2 of the License, or (at your
 819 + *  option) any later version.
 820 + *
 821 + *  THIS  SOFTWARE  IS PROVIDED          ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 822 + *  WARRANTIES,          INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 823 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 824 + *  NO EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 825 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 826 + *  NOT LIMITED          TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 827 + *  USE, DATA, OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 828 + *  ANY THEORY OF LIABILITY, WHETHER IN         CONTRACT, STRICT LIABILITY, OR TORT
 829 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 830 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 831 + *
 832 + *  You should have received a copy of the  GNU General Public License along
 833 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
 834 + *  675 Mass Ave, Cambridge, MA 02139, USA.
 835 + */
 836 +
 837 +#include <linux/errno.h>
 838 +#include <linux/init.h>
 839 +#include <linux/kernel_stat.h>
 840 +#include <linux/module.h>
 841 +#include <linux/signal.h>
 842 +#include <linux/sched.h>
 843 +#include <linux/types.h>
 844 +#include <linux/interrupt.h>
 845 +#include <linux/ioport.h>
 846 +#include <linux/timex.h>
 847 +#include <linux/slab.h>
 848 +#include <linux/random.h>
 849 +#include <linux/delay.h>
 850 +
 851 +#include <asm/bitops.h>
 852 +#include <asm/bootinfo.h>
 853 +#include <asm/io.h>
 854 +#include <asm/irq.h>
 855 +#include <asm/time.h>
 856 +#include <asm/mipsregs.h>
 857 +#include <asm/system.h>
 858 +#include <asm/rc32434/rc32434.h>
 859 +#include <asm/rc32434/gpio.h>
 860 +
 861 +extern void set_debug_traps(void);
 862 +extern irq_cpustat_t irq_stat [NR_CPUS];
 863 +unsigned int local_bh_count[NR_CPUS];
 864 +unsigned int local_irq_count[NR_CPUS];
 865 +
 866 +static unsigned int startup_irq(unsigned int irq);
 867 +static void rb500_end_irq(unsigned int irq_nr);
 868 +static void mask_and_ack_irq(unsigned int irq_nr);
 869 +static void rb500_enable_irq(unsigned int irq_nr);
 870 +static void rb500_disable_irq(unsigned int irq_nr);
 871 +
 872 +extern void __init init_generic_irq(void);
 873 +
 874 +typedef struct {
 875 +  u32 mask;       /* mask of valid bits in pending/mask registers */
 876 +  volatile u32 *base_addr;
 877 +} intr_group_t;
 878 +
 879 +#define RC32434_NR_IRQS  (GROUP4_IRQ_BASE + 32)
 880 +
 881 +#if (NR_IRQS < RC32434_NR_IRQS)
 882 +#error Too little irqs defined. Did you override <asm/irq.h> ?
 883 +#endif
 884 +
 885 +static const intr_group_t intr_group[NUM_INTR_GROUPS] = {
 886 +  { 0x0000efff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 0 * IC_GROUP_OFFSET) },
 887 +  { 0x00001fff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 1 * IC_GROUP_OFFSET) },
 888 +  { 0x00000007, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 2 * IC_GROUP_OFFSET) },
 889 +  { 0x0003ffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 3 * IC_GROUP_OFFSET) },
 890 +  { 0xffffffff, (u32 *)KSEG1ADDR(IC_GROUP0_PEND + 4 * IC_GROUP_OFFSET) }
 891 +};
 892 +
 893 +#define READ_PEND(base) (*(base))
 894 +#define READ_MASK(base) (*(base + 2))
 895 +#define WRITE_MASK(base, val) (*(base + 2) = (val))
 896 +
 897 +static inline int irq_to_group(unsigned int irq_nr)
 898 +{
 899 +  return ((irq_nr - GROUP0_IRQ_BASE) >> 5);
 900 +}
 901 +
 902 +static inline int group_to_ip(unsigned int group)
 903 +{
 904 +  return group + 2;
 905 +}
 906 +
 907 +static inline void enable_local_irq(unsigned int ip)
 908 +{
 909 +  int ipnum = 0x100 << ip;
 910 +  clear_c0_cause(ipnum);
 911 +  set_c0_status(ipnum);
 912 +}
 913 +
 914 +static inline void disable_local_irq(unsigned int ip)
 915 +{
 916 +  int ipnum = 0x100 << ip;
 917 +  clear_c0_status(ipnum);
 918 +}
 919 +
 920 +static inline void ack_local_irq(unsigned int ip)
 921 +{
 922 +  int ipnum = 0x100 << ip;
 923 +  clear_c0_cause(ipnum);
 924 +}
 925 +
 926 +static void rb500_enable_irq(unsigned int irq_nr)
 927 +{
 928 +  int           ip = irq_nr - GROUP0_IRQ_BASE;
 929 +  unsigned int  group, intr_bit;
 930 +  volatile unsigned int  *addr;
 931 +
 932 +
 933 +  if (ip < 0)
 934 +    enable_local_irq(irq_nr);
 935 +  else {
 936 +    group = ip >> 5;
 937 +
 938 +    ip &= (1<<5)-1;
 939 +    intr_bit = 1 << ip;
 940 +
 941 +    enable_local_irq(group_to_ip(group));
 942 +
 943 +    addr = intr_group[group].base_addr;
 944 +    WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
 945 +  }
 946 +}
 947 +
 948 +static void rb500_disable_irq(unsigned int irq_nr)
 949 +{
 950 +  int           ip = irq_nr - GROUP0_IRQ_BASE;
 951 +  unsigned int  group, intr_bit, mask;
 952 +  volatile unsigned int  *addr;
 953 +
 954 +  if (ip < 0) {
 955 +       disable_local_irq(irq_nr);
 956 +    }else{
 957 +    group = ip >> 5;
 958 +
 959 +    ip &= (1<<5) -1;
 960 +    intr_bit = 1 << ip;
 961 +    addr = intr_group[group].base_addr;
 962 +    mask = READ_MASK(addr);
 963 +    mask |= intr_bit;
 964 +    WRITE_MASK(addr,mask);
 965 +
 966 +    /*
 967 +     * if there are no more interrupts enabled in this
 968 +     * group, disable corresponding IP
 969 +     */
 970 +    if (mask == intr_group[group].mask)
 971 +      disable_local_irq(group_to_ip(group));
 972 +  }
 973 +}
 974 +
 975 +static unsigned int startup_irq(unsigned int irq_nr)
 976 +{
 977 +  rb500_enable_irq(irq_nr);
 978 +  return 0;
 979 +}
 980 +
 981 +static void shutdown_irq(unsigned int irq_nr)
 982 +{
 983 +  rb500_disable_irq(irq_nr);
 984 +  return;
 985 +}
 986 +
 987 +static void mask_and_ack_irq(unsigned int irq_nr)
 988 +{
 989 +  rb500_disable_irq(irq_nr);
 990 +  ack_local_irq(group_to_ip(irq_to_group(irq_nr)));
 991 +}
 992 +
 993 +static void rb500_end_irq(unsigned int irq_nr)
 994 +{
 995 +
 996 +  int ip = irq_nr - GROUP0_IRQ_BASE;
 997 +  unsigned int intr_bit, group;
 998 +  volatile unsigned int *addr;
 999 +
1000 +       if ((irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
1001 +               printk("warning: end_irq %d did not enable (%x)\n",
1002 +                       irq_nr, irq_desc[irq_nr].status);
1003 +               return;
1004 +       }
1005 +
1006 +       if (ip < 0) {
1007 +               enable_local_irq(irq_nr);
1008 +       } else {
1009 +               group = ip >> 5;
1010 +
1011 +               ip &= (1 << 5) - 1;
1012 +               intr_bit = 1 << ip;
1013 +
1014 +               if (irq_nr >= GROUP4_IRQ_BASE && irq_nr <= (GROUP4_IRQ_BASE + 13)) {
1015 +                       gpio->gpioistat = gpio->gpioistat & ~intr_bit;
1016 +               }
1017 +
1018 +               enable_local_irq(group_to_ip(group));
1019 +
1020 +               addr = intr_group[group].base_addr;
1021 +               WRITE_MASK(addr, READ_MASK(addr) & ~intr_bit);
1022 +       }
1023 +}
1024 +
1025 +static struct hw_interrupt_type rc32434_irq_type = {
1026 +  .typename = "RB500",
1027 +  .startup = startup_irq,
1028 +  .shutdown = shutdown_irq,
1029 +  .enable = rb500_enable_irq,
1030 +  .disable = rb500_disable_irq,
1031 +  .ack = mask_and_ack_irq,
1032 +  .end = rb500_end_irq,
1033 +};
1034 +
1035 +
1036 +void __init arch_init_irq(void)
1037 +{
1038 +       int i;
1039 +
1040 +       printk("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
1041 +       memset(irq_desc, 0, sizeof(irq_desc));
1042 +
1043 +       for (i = 0; i < RC32434_NR_IRQS; i++) {
1044 +               irq_desc[i].status = IRQ_DISABLED;
1045 +               irq_desc[i].action = NULL;
1046 +               irq_desc[i].depth = 1;
1047 +               irq_desc[i].chip = &rc32434_irq_type;
1048 +               spin_lock_init(&irq_desc[i].lock);
1049 +       }
1050 +}
1051 +
1052 +/* Main Interrupt dispatcher */
1053 +asmlinkage void plat_irq_dispatch(void)
1054 +{
1055 +       unsigned int ip, pend, group;
1056 +       volatile unsigned int *addr;
1057 +       unsigned int cp0_cause = read_c0_cause() & read_c0_status();
1058 +
1059 +       if (cp0_cause & CAUSEF_IP7) {
1060 +               ll_timer_interrupt(7);
1061 +       } else if ((ip = (cp0_cause & 0x7c00))) {
1062 +               group = 21 - rc32434_clz(ip);
1063 +
1064 +               addr = intr_group[group].base_addr;
1065 +
1066 +               pend = READ_PEND(addr);
1067 +               pend &= ~READ_MASK(addr); // only unmasked interrupts
1068 +               pend = 39 - rc32434_clz(pend);
1069 +               do_IRQ((group << 5) + pend);
1070 +       }
1071 +}
1072 diff -urN linux.old/arch/mips/rb500/Makefile linux.dev/arch/mips/rb500/Makefile
1073 --- linux.old/arch/mips/rb500/Makefile  1970-01-01 01:00:00.000000000 +0100
1074 +++ linux.dev/arch/mips/rb500/Makefile  2006-12-14 04:09:50.000000000 +0100
1075 @@ -0,0 +1,5 @@
1076 +#
1077 +# Makefile for the RB500 board specific parts of the kernel
1078 +#
1079 +
1080 +obj-y   += irq.o time.o setup.o serial.o prom.o misc.o devices.o
1081 diff -urN linux.old/arch/mips/rb500/misc.c linux.dev/arch/mips/rb500/misc.c
1082 --- linux.old/arch/mips/rb500/misc.c    1970-01-01 01:00:00.000000000 +0100
1083 +++ linux.dev/arch/mips/rb500/misc.c    2006-12-14 04:09:50.000000000 +0100
1084 @@ -0,0 +1,56 @@
1085 +#include <linux/module.h>
1086 +#include <linux/kernel.h>   /* printk() */
1087 +#include <linux/types.h>    /* size_t */
1088 +#include <linux/pci.h>
1089 +#include <linux/spinlock.h>
1090 +#include <asm/rc32434/rb.h>
1091 +
1092 +#define GPIO_BADDR  0xb8050000
1093 +
1094 +
1095 +static volatile unsigned char *devCtl3Base = 0;
1096 +static unsigned char latchU5State = 0;
1097 +static spinlock_t clu5Lock = SPIN_LOCK_UNLOCKED;
1098 +
1099 +void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val) {
1100 +    unsigned flags, data;
1101 +    unsigned i = 0;
1102 +    spin_lock_irqsave(&clu5Lock, flags);
1103 +    data = *(volatile unsigned *) (IDT434_REG_BASE + regOffs);
1104 +    for (i = 0; i != len; ++i) {
1105 +       if (val & (1 << i)) data |= (1 << (i + bit));
1106 +       else data &= ~(1 << (i + bit));
1107 +    }
1108 +    *(volatile unsigned *) (IDT434_REG_BASE + regOffs) = data;
1109 +    spin_unlock_irqrestore(&clu5Lock, flags);
1110 +}
1111 +
1112 +void changeLatchU5(unsigned char orMask, unsigned char nandMask) {
1113 +    unsigned flags;
1114 +    spin_lock_irqsave(&clu5Lock, flags);
1115 +    latchU5State = (latchU5State | orMask) & ~nandMask;
1116 +    if( !devCtl3Base) devCtl3Base = (volatile unsigned char *)
1117 +               KSEG1ADDR(*(volatile unsigned *) KSEG1ADDR(0x18010030));
1118 +    *devCtl3Base = latchU5State;
1119 +    spin_unlock_irqrestore(&clu5Lock, flags);
1120 +}
1121 +
1122 +u32 gpio_get(gpio_func func)
1123 +{
1124 +       return readl((void *) GPIO_BADDR + func);
1125 +}
1126 +
1127 +void gpio_set(gpio_func func, u32 mask, u32 value)
1128 +{
1129 +       u32 val = readl((void *) GPIO_BADDR + func);
1130 +
1131 +       val &= ~mask;
1132 +       val |= value & mask;
1133 +
1134 +       writel(val, (void *) GPIO_BADDR + func);
1135 +}
1136 +
1137 +EXPORT_SYMBOL(gpio_set);
1138 +EXPORT_SYMBOL(gpio_get);
1139 +EXPORT_SYMBOL(set434Reg);
1140 +EXPORT_SYMBOL(changeLatchU5);
1141 diff -urN linux.old/arch/mips/rb500/prom.c linux.dev/arch/mips/rb500/prom.c
1142 --- linux.old/arch/mips/rb500/prom.c    1970-01-01 01:00:00.000000000 +0100
1143 +++ linux.dev/arch/mips/rb500/prom.c    2006-12-14 05:15:05.000000000 +0100
1144 @@ -0,0 +1,161 @@
1145 +/*
1146 +* prom.c
1147 +**********************************************************************
1148 +* P . Sadik Oct 10, 2003
1149 +*
1150 +* Started change log
1151 +* idt_cpu_freq is make a kernel configuration parameter
1152 +* idt_cpu_freq is exported so that other modules can use it.
1153 +* Code cleanup
1154 +**********************************************************************
1155 +* P. Sadik Oct 20, 2003
1156 +*
1157 +* Removed NVRAM code from here, since they are already available under
1158 +* nvram directory.
1159 +* Added serial port initialisation.
1160 +**********************************************************************
1161 +**********************************************************************
1162 +* P. Sadik Oct 30, 2003
1163 +*
1164 +* Added reset_cons_port
1165 +**********************************************************************
1166 +
1167 +  P.Christeas, 2005-2006
1168 +  Port to 2.6, add 2.6 cmdline parsing
1169 +
1170 +*/
1171 +
1172 +#include <linux/autoconf.h>
1173 +#include <linux/init.h>
1174 +#include <linux/mm.h>
1175 +#include <linux/module.h>
1176 +#include <linux/string.h>
1177 +#include <linux/console.h>
1178 +#include <asm/bootinfo.h>
1179 +#include <linux/bootmem.h>
1180 +#include <linux/ioport.h>
1181 +#include <linux/blkdev.h>
1182 +#include <asm/rc32434/ddr.h>
1183 +
1184 +#define PROM_ENTRY(x)   (0xbfc00000+((x)*8))
1185 +extern void __init setup_serial_port(void);
1186 +
1187 +unsigned int idt_cpu_freq = 132000000;
1188 +EXPORT_SYMBOL(idt_cpu_freq);
1189 +unsigned int board_type = 500;
1190 +EXPORT_SYMBOL(board_type);
1191 +unsigned int gpio_bootup_state = 0;
1192 +EXPORT_SYMBOL(gpio_bootup_state);
1193 +
1194 +
1195 +char mips_mac_address[18] = "08:00:06:05:40:01";
1196 +EXPORT_SYMBOL(mips_mac_address);
1197 +
1198 +/* what to append to cmdline when button is [not] pressed */
1199 +#define GPIO_INIT_NOBUTTON ""
1200 +#define GPIO_INIT_BUTTON   " 2"
1201 +
1202 +#ifdef CONFIG_MIKROTIK_RB500
1203 +unsigned soft_reboot = 0;
1204 +EXPORT_SYMBOL(soft_reboot);
1205 +#endif
1206 +
1207 +#define SR_NMI                 0x00180000      /* NMI */
1208 +#define SERIAL_SPEED_ENTRY     0x00000001
1209 +
1210 +#ifdef CONFIG_REMOTE_DEBUG
1211 +extern int remote_debug;
1212 +#endif
1213 +
1214 +extern unsigned long mips_machgroup;
1215 +extern unsigned long mips_machtype;
1216 +
1217 +#define FREQ_TAG   "HZ="
1218 +#define GPIO_TAG   "gpio="
1219 +#define KMAC_TAG   "kmac="
1220 +#define MEM_TAG           "mem="
1221 +#define BOARD_TAG  "board="
1222 +#define IGNORE_CMDLINE_MEM 1
1223 +#define DEBUG_DDR
1224 +
1225 +void parse_soft_settings(unsigned *ptr, unsigned size);
1226 +void parse_hard_settings(unsigned *ptr, unsigned size);
1227 +
1228 +void __init prom_setup_cmdline(void);
1229 +
1230 +void __init prom_init(void)
1231 +{
1232 +       DDR_t ddr = (DDR_t) DDR_VirtualAddress; /* define the pointer to the DDR registers */
1233 +       phys_t memsize = 0-ddr->ddrmask;
1234 +
1235 +       /* this should be the very first message, even before serial is properly initialized */
1236 +       prom_setup_cmdline();
1237 +       setup_serial_port();
1238 +
1239 +       mips_machgroup = MACH_GROUP_MIKROTIK;
1240 +       soft_reboot = read_c0_status() & SR_NMI;
1241 +       pm_power_off = NULL;
1242 +
1243 +       /*
1244 +        * give all RAM to boot allocator,
1245 +        * except for the first 0x400 and the last 0x200 bytes
1246 +        */
1247 +       add_memory_region(ddr->ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
1248 +}
1249 +
1250 +void prom_free_prom_memory(void)
1251 +{
1252 +       /* FIXME: STUB */
1253 +}
1254 +
1255 +void __init prom_setup_cmdline(void){
1256 +       char cmd_line[CL_SIZE];
1257 +       char *cp;
1258 +       int prom_argc;
1259 +       char **prom_argv, **prom_envp;
1260 +       int i;
1261 +
1262 +       prom_argc = fw_arg0;
1263 +       prom_argv = (char **) fw_arg1;
1264 +       prom_envp = (char **) fw_arg2;
1265 +
1266 +       cp=cmd_line;
1267 +               /* Note: it is common that parameters start at argv[1] and not argv[0],
1268 +               however, our elf loader starts at [0] */
1269 +       for(i=0;i<prom_argc;i++){
1270 +               if (strncmp(prom_argv[i], FREQ_TAG, sizeof(FREQ_TAG) - 1) == 0) {
1271 +                       idt_cpu_freq = simple_strtoul(prom_argv[i] + sizeof(FREQ_TAG) - 1, 0, 10);
1272 +                       continue;
1273 +               }
1274 +#ifdef IGNORE_CMDLINE_MEM
1275 +               /* parses out the "mem=xx" arg */
1276 +               if (strncmp(prom_argv[i], MEM_TAG, sizeof(MEM_TAG) - 1) == 0) {
1277 +                       continue;
1278 +               }
1279 +#endif
1280 +               if (i>0) *(cp++) = ' ';
1281 +               if (strncmp(prom_argv[i], BOARD_TAG, sizeof(BOARD_TAG) - 1) == 0) {
1282 +                       board_type =  simple_strtoul(prom_argv[i] + sizeof(BOARD_TAG) - 1, 0, 10);
1283 +               }
1284 +               if (strncmp(prom_argv[i], GPIO_TAG, sizeof(GPIO_TAG) - 1) == 0) {
1285 +                       gpio_bootup_state =  simple_strtoul(prom_argv[i] + sizeof(GPIO_TAG) - 1, 0, 10);
1286 +               }
1287 +               strcpy(cp,prom_argv[i]);
1288 +               cp+=strlen(prom_argv[i]);
1289 +       }
1290 +
1291 +       i=strlen(arcs_cmdline);
1292 +       if (i>0){
1293 +               *(cp++) = ' ';
1294 +               strcpy(cp,arcs_cmdline);
1295 +               cp+=strlen(arcs_cmdline);
1296 +       }
1297 +       if (gpio_bootup_state&0x02)
1298 +               strcpy(cp,GPIO_INIT_NOBUTTON);
1299 +       else
1300 +               strcpy(cp,GPIO_INIT_BUTTON);
1301 +       cmd_line[CL_SIZE-1] = '\0';
1302 +
1303 +       strcpy(arcs_cmdline,cmd_line);
1304 +}
1305 +
1306 diff -urN linux.old/arch/mips/rb500/serial.c linux.dev/arch/mips/rb500/serial.c
1307 --- linux.old/arch/mips/rb500/serial.c  1970-01-01 01:00:00.000000000 +0100
1308 +++ linux.dev/arch/mips/rb500/serial.c  2006-12-14 04:09:50.000000000 +0100
1309 @@ -0,0 +1,77 @@
1310 +/**************************************************************************
1311 + *
1312 + *  BRIEF MODULE DESCRIPTION
1313 + *     Serial port initialisation.
1314 + *
1315 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
1316 + *
1317 + *  This program is free software; you can redistribute  it and/or modify it
1318 + *  under  the terms of  the GNU General  Public License as published by the
1319 + *  Free Software Foundation;  either version 2 of the  License, or (at your
1320 + *  option) any later version.
1321 + *
1322 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
1323 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
1324 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
1325 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
1326 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1327 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
1328 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1329 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
1330 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1331 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1332 + *
1333 + *  You should have received a copy of the  GNU General Public License along
1334 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
1335 + *  675 Mass Ave, Cambridge, MA 02139, USA.
1336 + *
1337 + *
1338 + **************************************************************************
1339 + * May 2004 rkt, neb
1340 + *
1341 + * Initial Release
1342 + *
1343 + *
1344 + *
1345 + **************************************************************************
1346 + */
1347 +
1348 +
1349 +#include <linux/autoconf.h>
1350 +#include <linux/init.h>
1351 +#include <linux/sched.h>
1352 +#include <linux/pci.h>
1353 +#include <linux/interrupt.h>
1354 +#include <linux/tty.h>
1355 +#include <linux/serial.h>
1356 +#include <linux/serial_core.h>
1357 +
1358 +#include <asm/time.h>
1359 +#include <asm/cpu.h>
1360 +#include <asm/bootinfo.h>
1361 +#include <asm/irq.h>
1362 +#include <asm/serial.h>
1363 +#include <asm/rc32434/rc32434.h>
1364 +
1365 +extern unsigned int idt_cpu_freq;
1366 +
1367 +static struct uart_port serial_req = {
1368 +       .type = PORT_16550A,
1369 +       .line = 0,
1370 +       .irq = RC32434_UART0_IRQ,
1371 +       .flags = STD_COM_FLAGS,
1372 +       .iotype = UPIO_MEM,
1373 +       .membase = (char *) KSEG1ADDR(RC32434_UART0_BASE),
1374 +//     .fifosize = 14
1375 +       .regshift = 2
1376 +};
1377 +
1378 +int __init setup_serial_port(void)
1379 +{
1380 +       serial_req.uartclk = idt_cpu_freq;
1381 +
1382 +       if (early_serial_setup(&serial_req))
1383 +               return -ENODEV;
1384 +
1385 +       return(0);
1386 +}
1387 diff -urN linux.old/arch/mips/rb500/setup.c linux.dev/arch/mips/rb500/setup.c
1388 --- linux.old/arch/mips/rb500/setup.c   1970-01-01 01:00:00.000000000 +0100
1389 +++ linux.dev/arch/mips/rb500/setup.c   2006-12-14 04:51:12.000000000 +0100
1390 @@ -0,0 +1,81 @@
1391 +/*
1392 + * setup.c - boot time setup code
1393 + */
1394 +
1395 +#include <linux/init.h>
1396 +#include <linux/mm.h>
1397 +#include <linux/sched.h>
1398 +#include <linux/irq.h>
1399 +#include <linux/ioport.h>
1400 +#include <linux/pm.h>
1401 +#include <asm/bootinfo.h>
1402 +#include <asm/mipsregs.h>
1403 +#include <asm/pgtable.h>
1404 +#include <asm/reboot.h>
1405 +#include <asm/addrspace.h>     /* for KSEG1ADDR() */
1406 +#include <asm/time.h>
1407 +#include <asm/io.h>
1408 +#include <asm/rc32434/rc32434.h>
1409 +#include <asm/rc32434/pci.h>
1410 +
1411 +#ifdef CONFIG_PCI
1412 +extern void *rc32434_time_init(void);
1413 +extern int __init rc32434_pcibridge_init(void);
1414 +#endif
1415 +
1416 +#define epldMask ((volatile unsigned char *)0xB900000d)
1417 +
1418 +static void rb_machine_restart(char *command)
1419 +{
1420 +       /* just jump to the reset vector */
1421 +       * (volatile unsigned *) KSEG1ADDR(0x18008000) = 0x80000001;
1422 +       ((void (*)(void))KSEG1ADDR(0x1FC00000u))();
1423 +}
1424 +
1425 +static void rb_machine_halt(void)
1426 +{
1427 +       for(;;) continue;
1428 +}
1429 +
1430 +#ifdef CONFIG_CPU_HAS_WB
1431 +void (*__wbflush) (void);
1432 +
1433 +static void rb_write_buffer_flush(void)
1434 +{
1435 +       __asm__ __volatile__
1436 +           ("sync\n\t" "nop\n\t" "loop: bc0f loop\n\t" "nop\n\t");
1437 +}
1438 +#endif
1439 +
1440 +void __init plat_mem_setup(void)
1441 +{
1442 +       unsigned int pciCntlVal;
1443 +
1444 +       board_time_init = rc32434_time_init;
1445 +
1446 +#ifdef CONFIG_CPU_HAS_WB
1447 +       __wbflush = rb_write_buffer_flush;
1448 +#endif
1449 +       _machine_restart = rb_machine_restart;
1450 +       _machine_halt = rb_machine_halt;
1451 +       /*_machine_power_off = rb_machine_power_halt;*/
1452 +       pm_power_off = rb_machine_halt;
1453 +
1454 +       set_io_port_base(KSEG1);
1455 +
1456 +       pciCntlVal=rc32434_pci->pcic;
1457 +       pciCntlVal &= 0xFFFFFF7;
1458 +       rc32434_pci->pcic = pciCntlVal;
1459 +
1460 +#ifdef CONFIG_PCI
1461 +       /* Enable PCI interrupts in EPLD Mask register */
1462 +       *epldMask = 0x0;
1463 +       *(epldMask + 1) = 0x0;
1464 +#endif
1465 +       write_c0_wired(0);
1466 +}
1467 +
1468 +const char *get_system_type(void)
1469 +{
1470 +       return "MIPS RB500";
1471 +}
1472 diff -urN linux.old/arch/mips/rb500/time.c linux.dev/arch/mips/rb500/time.c
1473 --- linux.old/arch/mips/rb500/time.c    1970-01-01 01:00:00.000000000 +0100
1474 +++ linux.dev/arch/mips/rb500/time.c    2006-12-14 04:48:33.000000000 +0100
1475 @@ -0,0 +1,93 @@
1476 +/*
1477 +****************************************************************************
1478 +* Carsten Langgaard, carstenl@mips.com
1479 +* Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
1480 +*
1481 +***************************************************************************
1482 +*
1483 +*  This program is free software; you can distribute it and/or modify it
1484 +*  under the terms of the GNU General Public License (Version 2) as
1485 +*  published by the Free Software Foundation.
1486 +*
1487 +*  This program is distributed in the hope it will be useful, but WITHOUT
1488 +*  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1489 +*  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
1490 +*  for more details.
1491 +*
1492 +*  You should have received a copy of the GNU General Public License along
1493 +*  with this program; if not, write to the Free Software Foundation, Inc.,
1494 +*  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1495 +*
1496 +****************************************************************************
1497 +*
1498 +* Setting up the clock on the MIPS boards.
1499 +*
1500 +****************************************************************************
1501 +* P. Sadik Oct 10, 2003
1502 +*
1503 +* Started change log.
1504 +* mips_counter_frequency is now calculated at run time, based on idt_cpu_freq.
1505 +* Code cleanup
1506 +****************************************************************************
1507 +*/
1508 +
1509 +#include <linux/autoconf.h>
1510 +#include <linux/init.h>
1511 +#include <linux/kernel_stat.h>
1512 +#include <linux/sched.h>
1513 +#include <linux/spinlock.h>
1514 +#include <linux/mc146818rtc.h>
1515 +#include <linux/irq.h>
1516 +#include <linux/timex.h>
1517 +
1518 +#include <asm/mipsregs.h>
1519 +#include <asm/ptrace.h>
1520 +#include <asm/debug.h>
1521 +#include <asm/rc32434/rc32434.h>
1522 +
1523 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
1524 +static unsigned long r4k_cur;    /* What counter should be at next timer irq */
1525 +extern unsigned int mips_hpt_frequency;
1526 +extern unsigned int idt_cpu_freq;
1527 +
1528 +/*
1529 + * Figure out the r4k offset, the amount to increment the compare
1530 + * register for each time tick. There is no RTC available.
1531 + *
1532 + * The RC32434 counts at half the CPU *core* speed.
1533 + */
1534 +static unsigned long __init cal_r4koff(void)
1535 +{
1536 +       mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
1537 +       return (mips_hpt_frequency / HZ);
1538 +}
1539 +
1540 +
1541 +void __init rc32434_time_init(void)
1542 +{
1543 +       unsigned int est_freq, flags;
1544 +
1545 +       local_irq_save(flags);
1546 +
1547 +       printk("calculating r4koff... ");
1548 +       r4k_offset = cal_r4koff();
1549 +       printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
1550 +
1551 +       est_freq = 2*r4k_offset*HZ;
1552 +       est_freq += 5000;       /* round */
1553 +       est_freq -= est_freq%10000;
1554 +       printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
1555 +              (est_freq%1000000)*100/1000000);
1556 +       local_irq_restore(flags);
1557 +}
1558 +
1559 +void __init plat_timer_setup(struct irqaction *irq)
1560 +{
1561 +       /* we are using the cpu counter for timer interrupts */
1562 +       setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1563 +
1564 +       /* to generate the first timer interrupt */
1565 +       r4k_cur = (read_c0_count() + r4k_offset);
1566 +       write_c0_compare(r4k_cur);
1567 +}
1568 +
1569 diff -urN linux.old/drivers/pci/Makefile linux.dev/drivers/pci/Makefile
1570 --- linux.old/drivers/pci/Makefile      2006-11-29 22:57:37.000000000 +0100
1571 +++ linux.dev/drivers/pci/Makefile      2006-12-14 04:09:50.000000000 +0100
1572 @@ -16,6 +16,7 @@
1573
1574  # Build the PCI MSI interrupt support
1575  obj-$(CONFIG_PCI_MSI) += msi.o
1576 +obj-$(CONFIG_MIKROTIK_RB500) += setup-irq.o
1577
1578  # Build the Hypertransport interrupt support
1579  obj-$(CONFIG_HT_IRQ) += htirq.o
1580 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
1581 --- linux.old/include/asm-mips/bootinfo.h       2006-11-29 22:57:37.000000000 +0100
1582 +++ linux.dev/include/asm-mips/bootinfo.h       2006-12-14 04:09:50.000000000 +0100
1583 @@ -212,6 +212,8 @@
1584  #define MACH_GROUP_NEC_EMMA2RH 25      /* NEC EMMA2RH (was 23)         */
1585  #define  MACH_NEC_MARKEINS     0       /* NEC EMMA2RH Mark-eins        */
1586
1587 +#define MACH_GROUP_MIKROTIK    24 /* Mikrotik Boards                       */
1588 +
1589  #define CL_SIZE                        COMMAND_LINE_SIZE
1590
1591  const char *get_system_type(void);
1592 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
1593 --- linux.old/include/asm-mips/cpu.h    2006-11-29 22:57:37.000000000 +0100
1594 +++ linux.dev/include/asm-mips/cpu.h    2006-12-14 04:09:50.000000000 +0100
1595 @@ -200,7 +200,8 @@
1596  #define CPU_SB1A               62
1597  #define CPU_74K                        63
1598  #define CPU_R14000             64
1599 -#define CPU_LAST               64
1600 +#define CPU_RC32300            65
1601 +#define CPU_LAST               65
1602
1603  /*
1604   * ISA Level encodings
1605 diff -urN linux.old/include/asm-mips/rc32434/ddr.h linux.dev/include/asm-mips/rc32434/ddr.h
1606 --- linux.old/include/asm-mips/rc32434/ddr.h    1970-01-01 01:00:00.000000000 +0100
1607 +++ linux.dev/include/asm-mips/rc32434/ddr.h    2006-12-14 04:09:50.000000000 +0100
1608 @@ -0,0 +1,173 @@
1609 +#ifndef __IDT_DDR_H__
1610 +#define __IDT_DDR_H__
1611 +
1612 +/*******************************************************************************
1613 + *
1614 + * Copyright 2002 Integrated Device Technology, Inc.
1615 + *             All rights reserved.
1616 + *
1617 + * DDR register definition.
1618 + *
1619 + * File   : $Id: ddr.h,v 1.2 2002/06/06 18:34:03 astichte Exp $
1620 + *
1621 + * Author : ryan.holmQVist@idt.com
1622 + * Date   : 20011005
1623 + * Update :
1624 + *          $Log: ddr.h,v $
1625 + *          Revision 1.2  2002/06/06 18:34:03  astichte
1626 + *          Added XXX_PhysicalAddress and XXX_VirtualAddress
1627 + *
1628 + *          Revision 1.1  2002/05/29 17:33:21  sysarch
1629 + *          jba File moved from vcode/include/idt/acacia
1630 + *
1631 + *
1632 + ******************************************************************************/
1633 +
1634 +enum
1635 +{
1636 +       DDR0_PhysicalAddress    = 0x18018000,
1637 +       DDR_PhysicalAddress     = DDR0_PhysicalAddress,         // Default
1638 +
1639 +       DDR0_VirtualAddress     = 0xb8018000,
1640 +       DDR_VirtualAddress      = DDR0_VirtualAddress,          // Default
1641 +} ;
1642 +
1643 +typedef struct DDR_s
1644 +{
1645 +       u32     ddrbase ;
1646 +       u32     ddrmask ;
1647 +       u32     res1;
1648 +       u32     res2;
1649 +       u32     ddrc ;
1650 +       u32     ddrabase ;
1651 +       u32     ddramask ;
1652 +       u32     ddramap ;
1653 +       u32     ddrcust;
1654 +       u32     ddrrdc;
1655 +       u32     ddrspare;
1656 +} volatile *DDR_t ;
1657 +
1658 +enum
1659 +{
1660 +       DDR0BASE_baseaddr_b     = 16,
1661 +       DDR0BASE_baseaddr_m     = 0xffff0000,
1662 +
1663 +       DDR0MASK_mask_b         = 16,
1664 +       DDR0MASK_mask_m         = 0xffff0000,
1665 +
1666 +       DDR1BASE_baseaddr_b     = 16,
1667 +       DDR1BASE_baseaddr_m     = 0xffff0000,
1668 +
1669 +       DDR1MASK_mask_b         = 16,
1670 +       DDR1MASK_mask_m         = 0xffff0000,
1671 +
1672 +       DDRC_ata_b              = 5,
1673 +       DDRC_ata_m              = 0x000000E0,
1674 +       DDRC_dbw_b              = 8,
1675 +       DDRC_dbw_m              = 0x00000100,
1676 +       DDRC_wr_b               = 9,
1677 +       DDRC_wr_m               = 0x00000600,
1678 +       DDRC_ps_b               = 11,
1679 +       DDRC_ps_m               = 0x00001800,
1680 +       DDRC_dtype_b            = 13,
1681 +       DDRC_dtype_m            = 0x0000e000,
1682 +       DDRC_rfc_b              = 16,
1683 +       DDRC_rfc_m              = 0x000f0000,
1684 +       DDRC_rp_b               = 20,
1685 +       DDRC_rp_m               = 0x00300000,
1686 +       DDRC_ap_b               = 22,
1687 +       DDRC_ap_m               = 0x00400000,
1688 +       DDRC_rcd_b              = 23,
1689 +       DDRC_rcd_m              = 0x01800000,
1690 +       DDRC_cl_b               = 25,
1691 +       DDRC_cl_m               = 0x06000000,
1692 +       DDRC_dbm_b              = 27,
1693 +       DDRC_dbm_m              = 0x08000000,
1694 +       DDRC_sds_b              = 28,
1695 +       DDRC_sds_m              = 0x10000000,
1696 +       DDRC_atp_b              = 29,
1697 +       DDRC_atp_m              = 0x60000000,
1698 +       DDRC_re_b               = 31,
1699 +       DDRC_re_m               = 0x80000000,
1700 +
1701 +       DDRRDC_ces_b            = 0,
1702 +       DDRRDC_ces_m            = 0x00000001,
1703 +       DDRRDC_ace_b            = 1,
1704 +       DDRRDC_ace_m            = 0x00000002,
1705 +
1706 +       DDRABASE_baseaddr_b     = 16,
1707 +       DDRABASE_baseaddr_m     = 0xffff0000,
1708 +
1709 +       DDRAMASK_mask_b         = 16,
1710 +       DDRAMASK_mask_m         = 0xffff0000,
1711 +
1712 +       DDRAMAP_map_b           = 16,
1713 +       DDRAMAP_map_m           = 0xffff0000,
1714 +
1715 +       DDRCUST_cs_b            = 0,
1716 +       DDRCUST_cs_m            = 0x00000003,
1717 +       DDRCUST_we_b            = 2,
1718 +       DDRCUST_we_m            = 0x00000004,
1719 +       DDRCUST_ras_b           = 3,
1720 +       DDRCUST_ras_m           = 0x00000008,
1721 +       DDRCUST_cas_b           = 4,
1722 +       DDRCUST_cas_m           = 0x00000010,
1723 +       DDRCUST_cke_b           = 5,
1724 +       DDRCUST_cke_m           = 0x00000020,
1725 +       DDRCUST_ba_b            = 6,
1726 +       DDRCUST_ba_m            = 0x000000c0,
1727 +
1728 +       RCOUNT_rcount_b         = 0,
1729 +       RCOUNT_rcount_m         = 0x0000ffff,
1730 +
1731 +       RCOMPARE_rcompare_b     = 0,
1732 +       RCOMPARE_rcompare_m     = 0x0000ffff,
1733 +
1734 +       RTC_ce_b                = 0,
1735 +       RTC_ce_m                = 0x00000001,
1736 +       RTC_to_b                = 1,
1737 +       RTC_to_m                = 0x00000002,
1738 +       RTC_rqe_b               = 2,
1739 +       RTC_rqe_m               = 0x00000004,
1740 +
1741 +       DDRDQSC_dm_b            = 0,
1742 +       DDRDQSC_dm_m            = 0x00000003,
1743 +       DDRDQSC_dqsbs_b         = 2,
1744 +       DDRDQSC_dqsbs_m         = 0x000000fc,
1745 +       DDRDQSC_db_b            = 8,
1746 +       DDRDQSC_db_m            = 0x00000100,
1747 +       DDRDQSC_dbsp_b          = 9,
1748 +       DDRDQSC_dbsp_m          = 0x01fffe00,
1749 +       DDRDQSC_bdp_b           = 25,
1750 +       DDRDQSC_bdp_m           = 0x7e000000,
1751 +
1752 +       DDRDLLC_eao_b           = 0,
1753 +       DDRDLLC_eao_m           = 0x00000001,
1754 +       DDRDLLC_eo_b            = 1,
1755 +       DDRDLLC_eo_m            = 0x0000003e,
1756 +       DDRDLLC_fs_b            = 6,
1757 +       DDRDLLC_fs_m            = 0x000000c0,
1758 +       DDRDLLC_as_b            = 8,
1759 +       DDRDLLC_as_m            = 0x00000700,
1760 +       DDRDLLC_sp_b            = 11,
1761 +       DDRDLLC_sp_m            = 0x001ff800,
1762 +
1763 +       DDRDLLFC_men_b          = 0,
1764 +       DDRDLLFC_men_m          = 0x00000001,
1765 +       DDRDLLFC_aen_b          = 1,
1766 +       DDRDLLFC_aen_m          = 0x00000002,
1767 +       DDRDLLFC_ff_b           = 2,
1768 +       DDRDLLFC_ff_m           = 0x00000004,
1769 +
1770 +       DDRDLLTA_addr_b         = 2,
1771 +       DDRDLLTA_addr_m         = 0xfffffffc,
1772 +
1773 +       DDRDLLED_dbe_b          = 0,
1774 +       DDRDLLED_dbe_m          = 0x00000001,
1775 +       DDRDLLED_dte_b          = 1,
1776 +       DDRDLLED_dte_m          = 0x00000002,
1777 +
1778 +
1779 +} ;
1780 +
1781 +#endif // __IDT_DDR_H__
1782 diff -urN linux.old/include/asm-mips/rc32434/dma.h linux.dev/include/asm-mips/rc32434/dma.h
1783 --- linux.old/include/asm-mips/rc32434/dma.h    1970-01-01 01:00:00.000000000 +0100
1784 +++ linux.dev/include/asm-mips/rc32434/dma.h    2006-12-14 04:09:50.000000000 +0100
1785 @@ -0,0 +1,168 @@
1786 +#ifndef __IDT_DMA_H__
1787 +#define __IDT_DMA_H__
1788 +
1789 +/*******************************************************************************
1790 + *
1791 + * Copyright 2002 Integrated Device Technology, Inc.
1792 + *             All rights reserved.
1793 + *
1794 + * DMA register definition.
1795 + *
1796 + * File   : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
1797 + *
1798 + * Author : ryan.holmQVist@idt.com
1799 + * Date   : 20011005
1800 + * Update :
1801 + *         $Log: dma.h,v $
1802 + *         Revision 1.3  2002/06/06 18:34:03  astichte
1803 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
1804 + *
1805 + *         Revision 1.2  2002/06/05 18:30:46  astichte
1806 + *         Removed IDTField
1807 + *
1808 + *         Revision 1.1  2002/05/29 17:33:21  sysarch
1809 + *         jba File moved from vcode/include/idt/acacia
1810 + *
1811 + *
1812 + ******************************************************************************/
1813 +
1814 +enum
1815 +{
1816 +       DMA0_PhysicalAddress    = 0x18040000,
1817 +       DMA_PhysicalAddress     = DMA0_PhysicalAddress,         // Default
1818 +
1819 +       DMA0_VirtualAddress     = 0xb8040000,
1820 +       DMA_VirtualAddress      = DMA0_VirtualAddress,          // Default
1821 +} ;
1822 +
1823 +/*
1824 + * DMA descriptor (in physical memory).
1825 + */
1826 +
1827 +typedef struct DMAD_s
1828 +{
1829 +       u32                     control ;       // Control. use DMAD_*
1830 +       u32                     ca ;            // Current Address.
1831 +       u32                     devcs ;         // Device control and status.
1832 +       u32                     link ;          // Next descriptor in chain.
1833 +} volatile *DMAD_t ;
1834 +
1835 +enum
1836 +{
1837 +       DMAD_size               = sizeof (struct DMAD_s),
1838 +       DMAD_count_b            = 0,            // in DMAD_t -> control
1839 +       DMAD_count_m            = 0x0003ffff,   // in DMAD_t -> control
1840 +       DMAD_ds_b               = 20,           // in DMAD_t -> control
1841 +       DMAD_ds_m               = 0x00300000,   // in DMAD_t -> control
1842 +               DMAD_ds_ethRcv_v        = 0,
1843 +               DMAD_ds_ethXmt_v        = 0,
1844 +               DMAD_ds_memToFifo_v     = 0,
1845 +               DMAD_ds_fifoToMem_v     = 0,
1846 +               DMAD_ds_pciToMem_v      = 0,
1847 +               DMAD_ds_memToPci_v      = 0,
1848 +
1849 +       DMAD_devcmd_b           = 22,           // in DMAD_t -> control
1850 +       DMAD_devcmd_m           = 0x01c00000,   // in DMAD_t -> control
1851 +               DMAD_devcmd_byte_v      = 0,    //memory-to-memory
1852 +               DMAD_devcmd_halfword_v  = 1,    //memory-to-memory
1853 +               DMAD_devcmd_word_v      = 2,    //memory-to-memory
1854 +               DMAD_devcmd_2words_v    = 3,    //memory-to-memory
1855 +               DMAD_devcmd_4words_v    = 4,    //memory-to-memory
1856 +               DMAD_devcmd_6words_v    = 5,    //memory-to-memory
1857 +               DMAD_devcmd_8words_v    = 6,    //memory-to-memory
1858 +               DMAD_devcmd_16words_v   = 7,    //memory-to-memory
1859 +       DMAD_cof_b              = 25,           // chain on finished
1860 +       DMAD_cof_m              = 0x02000000,   //
1861 +       DMAD_cod_b              = 26,           // chain on done
1862 +       DMAD_cod_m              = 0x04000000,   //
1863 +       DMAD_iof_b              = 27,           // interrupt on finished
1864 +       DMAD_iof_m              = 0x08000000,   //
1865 +       DMAD_iod_b              = 28,           // interrupt on done
1866 +       DMAD_iod_m              = 0x10000000,   //
1867 +       DMAD_t_b                = 29,           // terminated
1868 +       DMAD_t_m                = 0x20000000,   //
1869 +       DMAD_d_b                = 30,           // done
1870 +       DMAD_d_m                = 0x40000000,   //
1871 +       DMAD_f_b                = 31,           // finished
1872 +       DMAD_f_m                = 0x80000000,   //
1873 +} ;
1874 +
1875 +/*
1876 + * DMA register (within Internal Register Map).
1877 + */
1878 +
1879 +struct DMA_Chan_s
1880 +{
1881 +       u32             dmac ;          // Control.
1882 +       u32             dmas ;          // Status.
1883 +       u32             dmasm ;         // Mask.
1884 +       u32             dmadptr ;       // Descriptor pointer.
1885 +       u32             dmandptr ;      // Next descriptor pointer.
1886 +};
1887 +
1888 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
1889 +
1890 +//DMA_Channels   use DMACH_count instead
1891 +
1892 +enum
1893 +{
1894 +       DMAC_run_b      = 0,            //
1895 +       DMAC_run_m      = 0x00000001,   //
1896 +       DMAC_dm_b       = 1,            // done mask
1897 +       DMAC_dm_m       = 0x00000002,   //
1898 +       DMAC_mode_b     = 2,            //
1899 +       DMAC_mode_m     = 0x0000000c,   //
1900 +               DMAC_mode_auto_v        = 0,
1901 +               DMAC_mode_burst_v       = 1,
1902 +               DMAC_mode_transfer_v    = 2, //usually used
1903 +               DMAC_mode_reserved_v    = 3,
1904 +       DMAC_a_b        = 4,            //
1905 +       DMAC_a_m        = 0x00000010,   //
1906 +
1907 +       DMAS_f_b        = 0,            // finished (sticky)
1908 +       DMAS_f_m        = 0x00000001,   //
1909 +       DMAS_d_b        = 1,            // done (sticky)
1910 +       DMAS_d_m        = 0x00000002,   //
1911 +       DMAS_c_b        = 2,            // chain (sticky)
1912 +       DMAS_c_m        = 0x00000004,   //
1913 +       DMAS_e_b        = 3,            // error (sticky)
1914 +       DMAS_e_m        = 0x00000008,   //
1915 +       DMAS_h_b        = 4,            // halt (sticky)
1916 +       DMAS_h_m        = 0x00000010,   //
1917 +
1918 +       DMASM_f_b       = 0,            // finished (1=mask)
1919 +       DMASM_f_m       = 0x00000001,   //
1920 +       DMASM_d_b       = 1,            // done (1=mask)
1921 +       DMASM_d_m       = 0x00000002,   //
1922 +       DMASM_c_b       = 2,            // chain (1=mask)
1923 +       DMASM_c_m       = 0x00000004,   //
1924 +       DMASM_e_b       = 3,            // error (1=mask)
1925 +       DMASM_e_m       = 0x00000008,   //
1926 +       DMASM_h_b       = 4,            // halt (1=mask)
1927 +       DMASM_h_m       = 0x00000010,   //
1928 +} ;
1929 +
1930 +/*
1931 + * DMA channel definitions
1932 + */
1933 +
1934 +enum
1935 +{
1936 +       DMACH_ethRcv = 0,
1937 +       DMACH_ethXmt = 1,
1938 +       DMACH_memToFifo = 2,
1939 +       DMACH_fifoToMem = 3,
1940 +       DMACH_pciToMem = 4,
1941 +       DMACH_memToPci = 5,
1942 +
1943 +       DMACH_count //must be last
1944 +};
1945 +
1946 +
1947 +typedef struct DMAC_s
1948 +{
1949 +       struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
1950 +} volatile *DMA_t ;
1951 +
1952 +#endif // __IDT_DMA_H__
1953 +
1954 diff -urN linux.old/include/asm-mips/rc32434/dma_v.h linux.dev/include/asm-mips/rc32434/dma_v.h
1955 --- linux.old/include/asm-mips/rc32434/dma_v.h  1970-01-01 01:00:00.000000000 +0100
1956 +++ linux.dev/include/asm-mips/rc32434/dma_v.h  2006-12-14 04:09:50.000000000 +0100
1957 @@ -0,0 +1,72 @@
1958 +#ifndef __IDT_DMA_V_H__
1959 +#define __IDT_DMA_V_H__
1960 +
1961 +/*******************************************************************************
1962 + *
1963 + * Copyright 2002 Integrated Device Technology, Inc.
1964 + *             All rights reserved.
1965 + *
1966 + * DMA register definition.
1967 + *
1968 + * File   : $Id: dma.h,v 1.3 2002/06/06 18:34:03 astichte Exp $
1969 + *
1970 + * Author : ryan.holmQVist@idt.com
1971 + * Date   : 20011005
1972 + * Update :
1973 + *         $Log: dma.h,v $
1974 + *         Revision 1.3  2002/06/06 18:34:03  astichte
1975 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
1976 + *
1977 + *         Revision 1.2  2002/06/05 18:30:46  astichte
1978 + *         Removed IDTField
1979 + *
1980 + *         Revision 1.1  2002/05/29 17:33:21  sysarch
1981 + *         jba File moved from vcode/include/idt/acacia
1982 + *
1983 + *
1984 + ******************************************************************************/
1985 +#include  <asm/rc32434/dma.h>
1986 +#include  <asm/rc32434/rc32434.h>
1987 +#define DMA_CHAN_OFFSET  0x14
1988 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
1989 +#define DMA_COUNT(count)   \
1990 +  ((count) & DMAD_count_m)
1991 +
1992 +#define DMA_HALT_TIMEOUT 500
1993 +
1994 +
1995 +static inline int rc32434_halt_dma(DMA_Chan_t ch)
1996 +{
1997 +       int timeout=1;
1998 +       if (local_readl(&ch->dmac) & DMAC_run_m) {
1999 +               local_writel(0, &ch->dmac);
2000 +               for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
2001 +                       if (local_readl(&ch->dmas) & DMAS_h_m) {
2002 +                               local_writel(0, &ch->dmas);
2003 +                               break;
2004 +                       }
2005 +               }
2006 +       }
2007 +
2008 +       return timeout ? 0 : 1;
2009 +}
2010 +
2011 +static inline void rc32434_start_dma(DMA_Chan_t ch, u32 dma_addr)
2012 +{
2013 +       local_writel(0, &ch->dmandptr);
2014 +       local_writel(dma_addr, &ch->dmadptr);
2015 +}
2016 +
2017 +static inline void rc32434_chain_dma(DMA_Chan_t ch, u32 dma_addr)
2018 +{
2019 +       local_writel(dma_addr, &ch->dmandptr);
2020 +}
2021 +
2022 +#endif // __IDT_DMA_V_H__
2023 +
2024 +
2025 +
2026 +
2027 +
2028 +
2029 +
2030 diff -urN linux.old/include/asm-mips/rc32434/eth.h linux.dev/include/asm-mips/rc32434/eth.h
2031 --- linux.old/include/asm-mips/rc32434/eth.h    1970-01-01 01:00:00.000000000 +0100
2032 +++ linux.dev/include/asm-mips/rc32434/eth.h    2006-12-14 04:09:50.000000000 +0100
2033 @@ -0,0 +1,320 @@
2034 +#ifndef        __IDT_ETH_H__
2035 +#define        __IDT_ETH_H__
2036 +
2037 +/*******************************************************************************
2038 + *
2039 + * Copyright 2002 Integrated Device Technology, Inc.
2040 + *             All rights reserved.
2041 + *
2042 + * Ethernet register definition.
2043 + *
2044 + * File   : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2045 + *
2046 + * Author : Allen.Stichter@idt.com
2047 + * Date   : 20020605
2048 + * Update :
2049 + *         $Log: eth.h,v $
2050 + *         Revision 1.3  2002/06/06 18:34:04  astichte
2051 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2052 + *
2053 + *         Revision 1.2  2002/06/05 18:19:46  astichte
2054 + *         Added
2055 + *
2056 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
2057 + *         jba File moved from vcode/include/idt/acacia
2058 + *
2059 + ******************************************************************************/
2060 +
2061 +enum
2062 +{
2063 +       ETH0_PhysicalAddress    = 0x18060000,
2064 +       ETH_PhysicalAddress     = ETH0_PhysicalAddress,         // Default
2065 +
2066 +       ETH0_VirtualAddress     = 0xb8060000,
2067 +       ETH_VirtualAddress      = ETH0_VirtualAddress,          // Default
2068 +} ;
2069 +
2070 +typedef struct
2071 +{
2072 +       u32 ethintfc            ;
2073 +       u32 ethfifott           ;
2074 +       u32 etharc              ;
2075 +       u32 ethhash0            ;
2076 +       u32 ethhash1            ;
2077 +       u32 ethu0 [4]           ;       // Reserved.
2078 +       u32 ethpfs              ;
2079 +       u32 ethmcp              ;
2080 +       u32 eth_u1 [10]         ;       // Reserved.
2081 +       u32 ethspare            ;
2082 +       u32 eth_u2 [42]         ;       // Reserved.
2083 +       u32 ethsal0             ;
2084 +       u32 ethsah0             ;
2085 +       u32 ethsal1             ;
2086 +       u32 ethsah1             ;
2087 +       u32 ethsal2             ;
2088 +       u32 ethsah2             ;
2089 +       u32 ethsal3             ;
2090 +       u32 ethsah3             ;
2091 +       u32 ethrbc              ;
2092 +       u32 ethrpc              ;
2093 +       u32 ethrupc             ;
2094 +       u32 ethrfc              ;
2095 +       u32 ethtbc              ;
2096 +       u32 ethgpf              ;
2097 +       u32 eth_u9 [50]         ;       // Reserved.
2098 +       u32 ethmac1             ;
2099 +       u32 ethmac2             ;
2100 +       u32 ethipgt             ;
2101 +       u32 ethipgr             ;
2102 +       u32 ethclrt             ;
2103 +       u32 ethmaxf             ;
2104 +       u32 eth_u10             ;       // Reserved.
2105 +       u32 ethmtest            ;
2106 +       u32 miimcfg             ;
2107 +       u32 miimcmd             ;
2108 +       u32 miimaddr            ;
2109 +       u32 miimwtd             ;
2110 +       u32 miimrdd             ;
2111 +       u32 miimind             ;
2112 +       u32 eth_u11             ;       // Reserved.
2113 +       u32 eth_u12             ;       // Reserved.
2114 +       u32 ethcfsa0            ;
2115 +       u32 ethcfsa1            ;
2116 +       u32 ethcfsa2            ;
2117 +} volatile *ETH_t;
2118 +
2119 +enum
2120 +{
2121 +       ETHINTFC_en_b           = 0,
2122 +       ETHINTFC_en_m           = 0x00000001,
2123 +       ETHINTFC_its_b          = 1,
2124 +       ETHINTFC_its_m          = 0x00000002,
2125 +       ETHINTFC_rip_b          = 2,
2126 +       ETHINTFC_rip_m          = 0x00000004,
2127 +       ETHINTFC_jam_b          = 3,
2128 +       ETHINTFC_jam_m          = 0x00000008,
2129 +       ETHINTFC_ovr_b          = 4,
2130 +       ETHINTFC_ovr_m          = 0x00000010,
2131 +       ETHINTFC_und_b          = 5,
2132 +       ETHINTFC_und_m          = 0x00000020,
2133 +       ETHINTFC_iom_b          = 6,
2134 +       ETHINTFC_iom_m          = 0x000000c0,
2135 +
2136 +       ETHFIFOTT_tth_b         = 0,
2137 +       ETHFIFOTT_tth_m         = 0x0000007f,
2138 +
2139 +       ETHARC_pro_b            = 0,
2140 +       ETHARC_pro_m            = 0x00000001,
2141 +       ETHARC_am_b             = 1,
2142 +       ETHARC_am_m             = 0x00000002,
2143 +       ETHARC_afm_b            = 2,
2144 +       ETHARC_afm_m            = 0x00000004,
2145 +       ETHARC_ab_b             = 3,
2146 +       ETHARC_ab_m             = 0x00000008,
2147 +
2148 +       ETHSAL_byte5_b          = 0,
2149 +       ETHSAL_byte5_m          = 0x000000ff,
2150 +       ETHSAL_byte4_b          = 8,
2151 +       ETHSAL_byte4_m          = 0x0000ff00,
2152 +       ETHSAL_byte3_b          = 16,
2153 +       ETHSAL_byte3_m          = 0x00ff0000,
2154 +       ETHSAL_byte2_b          = 24,
2155 +       ETHSAL_byte2_m          = 0xff000000,
2156 +
2157 +       ETHSAH_byte1_b          = 0,
2158 +       ETHSAH_byte1_m          = 0x000000ff,
2159 +       ETHSAH_byte0_b          = 8,
2160 +       ETHSAH_byte0_m          = 0x0000ff00,
2161 +
2162 +       ETHGPF_ptv_b            = 0,
2163 +       ETHGPF_ptv_m            = 0x0000ffff,
2164 +
2165 +       ETHPFS_pfd_b            = 0,
2166 +       ETHPFS_pfd_m            = 0x00000001,
2167 +
2168 +       ETHCFSA0_cfsa4_b        = 0,
2169 +       ETHCFSA0_cfsa4_m        = 0x000000ff,
2170 +       ETHCFSA0_cfsa5_b        = 8,
2171 +       ETHCFSA0_cfsa5_m        = 0x0000ff00,
2172 +
2173 +       ETHCFSA1_cfsa2_b        = 0,
2174 +       ETHCFSA1_cfsa2_m        = 0x000000ff,
2175 +       ETHCFSA1_cfsa3_b        = 8,
2176 +       ETHCFSA1_cfsa3_m        = 0x0000ff00,
2177 +
2178 +       ETHCFSA2_cfsa0_b        = 0,
2179 +       ETHCFSA2_cfsa0_m        = 0x000000ff,
2180 +       ETHCFSA2_cfsa1_b        = 8,
2181 +       ETHCFSA2_cfsa1_m        = 0x0000ff00,
2182 +
2183 +       ETHMAC1_re_b            = 0,
2184 +       ETHMAC1_re_m            = 0x00000001,
2185 +       ETHMAC1_paf_b           = 1,
2186 +       ETHMAC1_paf_m           = 0x00000002,
2187 +       ETHMAC1_rfc_b           = 2,
2188 +       ETHMAC1_rfc_m           = 0x00000004,
2189 +       ETHMAC1_tfc_b           = 3,
2190 +       ETHMAC1_tfc_m           = 0x00000008,
2191 +       ETHMAC1_lb_b            = 4,
2192 +       ETHMAC1_lb_m            = 0x00000010,
2193 +       ETHMAC1_mr_b            = 31,
2194 +       ETHMAC1_mr_m            = 0x80000000,
2195 +
2196 +       ETHMAC2_fd_b            = 0,
2197 +       ETHMAC2_fd_m            = 0x00000001,
2198 +       ETHMAC2_flc_b           = 1,
2199 +       ETHMAC2_flc_m           = 0x00000002,
2200 +       ETHMAC2_hfe_b           = 2,
2201 +       ETHMAC2_hfe_m           = 0x00000004,
2202 +       ETHMAC2_dc_b            = 3,
2203 +       ETHMAC2_dc_m            = 0x00000008,
2204 +       ETHMAC2_cen_b           = 4,
2205 +       ETHMAC2_cen_m           = 0x00000010,
2206 +       ETHMAC2_pe_b            = 5,
2207 +       ETHMAC2_pe_m            = 0x00000020,
2208 +       ETHMAC2_vpe_b           = 6,
2209 +       ETHMAC2_vpe_m           = 0x00000040,
2210 +       ETHMAC2_ape_b           = 7,
2211 +       ETHMAC2_ape_m           = 0x00000080,
2212 +       ETHMAC2_ppe_b           = 8,
2213 +       ETHMAC2_ppe_m           = 0x00000100,
2214 +       ETHMAC2_lpe_b           = 9,
2215 +       ETHMAC2_lpe_m           = 0x00000200,
2216 +       ETHMAC2_nb_b            = 12,
2217 +       ETHMAC2_nb_m            = 0x00001000,
2218 +       ETHMAC2_bp_b            = 13,
2219 +       ETHMAC2_bp_m            = 0x00002000,
2220 +       ETHMAC2_ed_b            = 14,
2221 +       ETHMAC2_ed_m            = 0x00004000,
2222 +
2223 +       ETHIPGT_ipgt_b          = 0,
2224 +       ETHIPGT_ipgt_m          = 0x0000007f,
2225 +
2226 +       ETHIPGR_ipgr2_b         = 0,
2227 +       ETHIPGR_ipgr2_m         = 0x0000007f,
2228 +       ETHIPGR_ipgr1_b         = 8,
2229 +       ETHIPGR_ipgr1_m         = 0x00007f00,
2230 +
2231 +       ETHCLRT_maxret_b        = 0,
2232 +       ETHCLRT_maxret_m        = 0x0000000f,
2233 +       ETHCLRT_colwin_b        = 8,
2234 +       ETHCLRT_colwin_m        = 0x00003f00,
2235 +
2236 +       ETHMAXF_maxf_b          = 0,
2237 +       ETHMAXF_maxf_m          = 0x0000ffff,
2238 +
2239 +       ETHMTEST_tb_b           = 2,
2240 +       ETHMTEST_tb_m           = 0x00000004,
2241 +
2242 +       ETHMCP_div_b            = 0,
2243 +       ETHMCP_div_m            = 0x000000ff,
2244 +
2245 +       MIIMCFG_rsv_b           = 0,
2246 +       MIIMCFG_rsv_m           = 0x0000000c,
2247 +
2248 +       MIIMCMD_rd_b            = 0,
2249 +       MIIMCMD_rd_m            = 0x00000001,
2250 +       MIIMCMD_scn_b           = 1,
2251 +       MIIMCMD_scn_m           = 0x00000002,
2252 +
2253 +       MIIMADDR_regaddr_b      = 0,
2254 +       MIIMADDR_regaddr_m      = 0x0000001f,
2255 +       MIIMADDR_phyaddr_b      = 8,
2256 +       MIIMADDR_phyaddr_m      = 0x00001f00,
2257 +
2258 +       MIIMWTD_wdata_b         = 0,
2259 +       MIIMWTD_wdata_m         = 0x0000ffff,
2260 +
2261 +       MIIMRDD_rdata_b         = 0,
2262 +       MIIMRDD_rdata_m         = 0x0000ffff,
2263 +
2264 +       MIIMIND_bsy_b           = 0,
2265 +       MIIMIND_bsy_m           = 0x00000001,
2266 +       MIIMIND_scn_b           = 1,
2267 +       MIIMIND_scn_m           = 0x00000002,
2268 +       MIIMIND_nv_b            = 2,
2269 +       MIIMIND_nv_m            = 0x00000004,
2270 +
2271 +} ;
2272 +
2273 +/*
2274 + * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
2275 + */
2276 +enum
2277 +{
2278 +       ETHRX_fd_b              = 0,
2279 +       ETHRX_fd_m              = 0x00000001,
2280 +       ETHRX_ld_b              = 1,
2281 +       ETHRX_ld_m              = 0x00000002,
2282 +       ETHRX_rok_b             = 2,
2283 +       ETHRX_rok_m             = 0x00000004,
2284 +       ETHRX_fm_b              = 3,
2285 +       ETHRX_fm_m              = 0x00000008,
2286 +       ETHRX_mp_b              = 4,
2287 +       ETHRX_mp_m              = 0x00000010,
2288 +       ETHRX_bp_b              = 5,
2289 +       ETHRX_bp_m              = 0x00000020,
2290 +       ETHRX_vlt_b             = 6,
2291 +       ETHRX_vlt_m             = 0x00000040,
2292 +       ETHRX_cf_b              = 7,
2293 +       ETHRX_cf_m              = 0x00000080,
2294 +       ETHRX_ovr_b             = 8,
2295 +       ETHRX_ovr_m             = 0x00000100,
2296 +       ETHRX_crc_b             = 9,
2297 +       ETHRX_crc_m             = 0x00000200,
2298 +       ETHRX_cv_b              = 10,
2299 +       ETHRX_cv_m              = 0x00000400,
2300 +       ETHRX_db_b              = 11,
2301 +       ETHRX_db_m              = 0x00000800,
2302 +       ETHRX_le_b              = 12,
2303 +       ETHRX_le_m              = 0x00001000,
2304 +       ETHRX_lor_b             = 13,
2305 +       ETHRX_lor_m             = 0x00002000,
2306 +       ETHRX_ces_b             = 14,
2307 +       ETHRX_ces_m             = 0x00004000,
2308 +       ETHRX_length_b          = 16,
2309 +       ETHRX_length_m          = 0xffff0000,
2310 +
2311 +       ETHTX_fd_b              = 0,
2312 +       ETHTX_fd_m              = 0x00000001,
2313 +       ETHTX_ld_b              = 1,
2314 +       ETHTX_ld_m              = 0x00000002,
2315 +       ETHTX_oen_b             = 2,
2316 +       ETHTX_oen_m             = 0x00000004,
2317 +       ETHTX_pen_b             = 3,
2318 +       ETHTX_pen_m             = 0x00000008,
2319 +       ETHTX_cen_b             = 4,
2320 +       ETHTX_cen_m             = 0x00000010,
2321 +       ETHTX_hen_b             = 5,
2322 +       ETHTX_hen_m             = 0x00000020,
2323 +       ETHTX_tok_b             = 6,
2324 +       ETHTX_tok_m             = 0x00000040,
2325 +       ETHTX_mp_b              = 7,
2326 +       ETHTX_mp_m              = 0x00000080,
2327 +       ETHTX_bp_b              = 8,
2328 +       ETHTX_bp_m              = 0x00000100,
2329 +       ETHTX_und_b             = 9,
2330 +       ETHTX_und_m             = 0x00000200,
2331 +       ETHTX_of_b              = 10,
2332 +       ETHTX_of_m              = 0x00000400,
2333 +       ETHTX_ed_b              = 11,
2334 +       ETHTX_ed_m              = 0x00000800,
2335 +       ETHTX_ec_b              = 12,
2336 +       ETHTX_ec_m              = 0x00001000,
2337 +       ETHTX_lc_b              = 13,
2338 +       ETHTX_lc_m              = 0x00002000,
2339 +       ETHTX_td_b              = 14,
2340 +       ETHTX_td_m              = 0x00004000,
2341 +       ETHTX_crc_b             = 15,
2342 +       ETHTX_crc_m             = 0x00008000,
2343 +       ETHTX_le_b              = 16,
2344 +       ETHTX_le_m              = 0x00010000,
2345 +       ETHTX_cc_b              = 17,
2346 +       ETHTX_cc_m              = 0x001E0000,
2347 +} ;
2348 +
2349 +#endif // __IDT_ETH_H__
2350 +
2351 +
2352 +
2353 +
2354 diff -urN linux.old/include/asm-mips/rc32434/eth_v.h linux.dev/include/asm-mips/rc32434/eth_v.h
2355 --- linux.old/include/asm-mips/rc32434/eth_v.h  1970-01-01 01:00:00.000000000 +0100
2356 +++ linux.dev/include/asm-mips/rc32434/eth_v.h  2006-12-14 04:09:50.000000000 +0100
2357 @@ -0,0 +1,63 @@
2358 +#ifndef        __IDT_ETH_V_H__
2359 +#define        __IDT_ETH_V_H__
2360 +
2361 +/*******************************************************************************
2362 + *
2363 + * Copyright 2002 Integrated Device Technology, Inc.
2364 + *             All rights reserved.
2365 + *
2366 + * Ethernet register definition.
2367 + *
2368 + * File   : $Id: eth.h,v 1.3 2002/06/06 18:34:04 astichte Exp $
2369 + *
2370 + * Author : Allen.Stichter@idt.com
2371 + * Date   : 20020605
2372 + * Update :
2373 + *         $Log: eth.h,v $
2374 + *         Revision 1.3  2002/06/06 18:34:04  astichte
2375 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2376 + *
2377 + *         Revision 1.2  2002/06/05 18:19:46  astichte
2378 + *         Added
2379 + *
2380 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
2381 + *         jba File moved from vcode/include/idt/acacia
2382 + *
2383 + ******************************************************************************/
2384 +
2385 +#include  <asm/rc32434/eth.h>
2386 +
2387 +#define IS_TX_TOK(X)         (((X) & (1<<ETHTX_tok_b)) >> ETHTX_tok_b )   /* Transmit Okay    */
2388 +#define IS_TX_MP(X)          (((X) & (1<<ETHTX_mp_b))  >> ETHTX_mp_b )    /* Multicast        */
2389 +#define IS_TX_BP(X)          (((X) & (1<<ETHTX_bp_b))  >> ETHTX_bp_b )    /* Broadcast        */
2390 +#define IS_TX_UND_ERR(X)     (((X) & (1<<ETHTX_und_b)) >> ETHTX_und_b )   /* Transmit FIFO Underflow */
2391 +#define IS_TX_OF_ERR(X)      (((X) & (1<<ETHTX_of_b))  >> ETHTX_of_b )    /* Oversized frame  */
2392 +#define IS_TX_ED_ERR(X)      (((X) & (1<<ETHTX_ed_b))  >> ETHTX_ed_b )    /* Excessive deferral  */
2393 +#define IS_TX_EC_ERR(X)      (((X) & (1<<ETHTX_ec_b))  >> ETHTX_ec_b)     /* Excessive collisions  */
2394 +#define IS_TX_LC_ERR(X)      (((X) & (1<<ETHTX_lc_b))  >> ETHTX_lc_b )    /* Late Collision   */
2395 +#define IS_TX_TD_ERR(X)      (((X) & (1<<ETHTX_td_b))  >> ETHTX_td_b )    /* Transmit deferred*/
2396 +#define IS_TX_CRC_ERR(X)     (((X) & (1<<ETHTX_crc_b)) >> ETHTX_crc_b )   /* CRC Error        */
2397 +#define IS_TX_LE_ERR(X)      (((X) & (1<<ETHTX_le_b))  >>  ETHTX_le_b )    /* Length Error     */
2398 +
2399 +#define TX_COLLISION_COUNT(X) (((X) & ETHTX_cc_m)>>ETHTX_cc_b)  /* Collision Count  */
2400 +
2401 +#define IS_RCV_ROK(X)        (((X) & (1<<ETHRX_rok_b)) >> ETHRX_rok_b)    /* Receive Okay     */
2402 +#define IS_RCV_FM(X)         (((X) & (1<<ETHRX_fm_b))  >> ETHRX_fm_b)     /* Is Filter Match  */
2403 +#define IS_RCV_MP(X)         (((X) & (1<<ETHRX_mp_b))  >> ETHRX_mp_b)     /* Is it MP         */
2404 +#define IS_RCV_BP(X)         (((X) & (1<<ETHRX_bp_b))  >> ETHRX_bp_b)     /* Is it BP         */
2405 +#define IS_RCV_VLT(X)        (((X) & (1<<ETHRX_vlt_b)) >> ETHRX_vlt_b)    /* VLAN Tag Detect  */
2406 +#define IS_RCV_CF(X)         (((X) & (1<<ETHRX_cf_b))  >> ETHRX_cf_b)     /* Control Frame    */
2407 +#define IS_RCV_OVR_ERR(X)    (((X) & (1<<ETHRX_ovr_b)) >> ETHRX_ovr_b)    /* Receive Overflow */
2408 +#define IS_RCV_CRC_ERR(X)    (((X) & (1<<ETHRX_crc_b)) >> ETHRX_crc_b)    /* CRC Error        */
2409 +#define IS_RCV_CV_ERR(X)     (((X) & (1<<ETHRX_cv_b))  >> ETHRX_cv_b)     /* Code Violation   */
2410 +#define IS_RCV_DB_ERR(X)     (((X) & (1<<ETHRX_db_b))  >> ETHRX_db_b)     /* Dribble Bits     */
2411 +#define IS_RCV_LE_ERR(X)     (((X) & (1<<ETHRX_le_b))  >> ETHRX_le_b)     /* Length error     */
2412 +#define IS_RCV_LOR_ERR(X)    (((X) & (1<<ETHRX_lor_b)) >> ETHRX_lor_b)    /* Length Out of Range */
2413 +#define IS_RCV_CES_ERR(X)    (((X) & (1<<ETHRX_ces_b)) >> ETHRX_ces_b)  /* Preamble error   */
2414 +#define RCVPKT_LENGTH(X)     (((X) & ETHRX_length_m) >> ETHRX_length_b)   /* Length of the received packet */
2415 +#endif // __IDT_ETH_V_H__
2416 +
2417 +
2418 +
2419 +
2420 +
2421 diff -urN linux.old/include/asm-mips/rc32434/gpio.h linux.dev/include/asm-mips/rc32434/gpio.h
2422 --- linux.old/include/asm-mips/rc32434/gpio.h   1970-01-01 01:00:00.000000000 +0100
2423 +++ linux.dev/include/asm-mips/rc32434/gpio.h   2006-12-14 04:09:50.000000000 +0100
2424 @@ -0,0 +1,181 @@
2425 +#ifndef __IDT_GPIO_H__
2426 +#define __IDT_GPIO_H__
2427 +
2428 +/*******************************************************************************
2429 + *
2430 + * Copyright 2002 Integrated Device Technology, Inc.
2431 + *             All rights reserved.
2432 + *
2433 + * GPIO register definition.
2434 + *
2435 + * File   : $Id: gpio.h,v 1.2 2002/06/06 18:34:04 astichte Exp $
2436 + *
2437 + * Author : ryan.holmQVist@idt.com
2438 + * Date   : 20011005
2439 + * Update :
2440 + *         $Log: gpio.h,v $
2441 + *         Revision 1.2  2002/06/06 18:34:04  astichte
2442 + *         Added XXX_PhysicalAddress and XXX_VirtualAddress
2443 + *
2444 + *         Revision 1.1  2002/05/29 17:33:22  sysarch
2445 + *         jba File moved from vcode/include/idt/acacia
2446 + *
2447 + *
2448 + ******************************************************************************/
2449 +
2450 +enum
2451 +{
2452 +       GPIO0_PhysicalAddress   = 0x18050000,
2453 +       GPIO_PhysicalAddress    = GPIO0_PhysicalAddress,        // Default
2454 +
2455 +       GPIO0_VirtualAddress    = 0xb8050000,
2456 +       GPIO_VirtualAddress     = GPIO0_VirtualAddress,         // Default
2457 +} ;
2458 +
2459 +typedef struct
2460 +{
2461 +       u32   gpiofunc;   /* GPIO Function Register
2462 +                          * gpiofunc[x]==0 bit = gpio
2463 +                          * func[x]==1  bit = altfunc
2464 +                          */
2465 +       u32   gpiocfg;    /* GPIO Configuration Register
2466 +                          * gpiocfg[x]==0 bit = input
2467 +                          * gpiocfg[x]==1 bit = output
2468 +                          */
2469 +       u32   gpiod;      /* GPIO Data Register
2470 +                          * gpiod[x] read/write gpio pinX status
2471 +                          */
2472 +       u32   gpioilevel; /* GPIO Interrupt Status Register
2473 +                          * interrupt level (see gpioistat)
2474 +                          */
2475 +       u32   gpioistat;  /* Gpio Interrupt Status Register
2476 +                          * istat[x] = (gpiod[x] == level[x])
2477 +                          * cleared in ISR (STICKY bits)
2478 +                          */
2479 +       u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
2480 +} volatile * GPIO_t ;
2481 +
2482 +typedef enum
2483 +{
2484 +       GPIO_gpio_v             = 0,            // gpiofunc use pin as GPIO.
2485 +       GPIO_alt_v              = 1,            // gpiofunc use pin as alt.
2486 +       GPIO_input_v            = 0,            // gpiocfg use pin as input.
2487 +       GPIO_output_v           = 1,            // gpiocfg use pin as output.
2488 +       GPIO_pin0_b             = 0,
2489 +       GPIO_pin0_m             = 0x00000001,
2490 +       GPIO_pin1_b             = 1,
2491 +       GPIO_pin1_m             = 0x00000002,
2492 +       GPIO_pin2_b             = 2,
2493 +       GPIO_pin2_m             = 0x00000004,
2494 +       GPIO_pin3_b             = 3,
2495 +       GPIO_pin3_m             = 0x00000008,
2496 +       GPIO_pin4_b             = 4,
2497 +       GPIO_pin4_m             = 0x00000010,
2498 +       GPIO_pin5_b             = 5,
2499 +       GPIO_pin5_m             = 0x00000020,
2500 +       GPIO_pin6_b             = 6,
2501 +       GPIO_pin6_m             = 0x00000040,
2502 +       GPIO_pin7_b             = 7,
2503 +       GPIO_pin7_m             = 0x00000080,
2504 +       GPIO_pin8_b             = 8,
2505 +       GPIO_pin8_m             = 0x00000100,
2506 +       GPIO_pin9_b             = 9,
2507 +       GPIO_pin9_m             = 0x00000200,
2508 +       GPIO_pin10_b            = 10,
2509 +       GPIO_pin10_m            = 0x00000400,
2510 +       GPIO_pin11_b            = 11,
2511 +       GPIO_pin11_m            = 0x00000800,
2512 +       GPIO_pin12_b            = 12,
2513 +       GPIO_pin12_m            = 0x00001000,
2514 +       GPIO_pin13_b            = 13,
2515 +       GPIO_pin13_m            = 0x00002000,
2516 +       GPIO_pin14_b            = 14,
2517 +       GPIO_pin14_m            = 0x00004000,
2518 +       GPIO_pin15_b            = 15,
2519 +       GPIO_pin15_m            = 0x00008000,
2520 +       GPIO_pin16_b            = 16,
2521 +       GPIO_pin16_m            = 0x00010000,
2522 +       GPIO_pin17_b            = 17,
2523 +       GPIO_pin17_m            = 0x00020000,
2524 +       GPIO_pin18_b            = 18,
2525 +       GPIO_pin18_m            = 0x00040000,
2526 +       GPIO_pin19_b            = 19,
2527 +       GPIO_pin19_m            = 0x00080000,
2528 +       GPIO_pin20_b            = 20,
2529 +       GPIO_pin20_m            = 0x00100000,
2530 +       GPIO_pin21_b            = 21,
2531 +       GPIO_pin21_m            = 0x00200000,
2532 +       GPIO_pin22_b            = 22,
2533 +       GPIO_pin22_m            = 0x00400000,
2534 +       GPIO_pin23_b            = 23,
2535 +       GPIO_pin23_m            = 0x00800000,
2536 +       GPIO_pin24_b            = 24,
2537 +       GPIO_pin24_m            = 0x01000000,
2538 +       GPIO_pin25_b            = 25,
2539 +       GPIO_pin25_m            = 0x02000000,
2540 +       GPIO_pin26_b            = 26,
2541 +       GPIO_pin26_m            = 0x04000000,
2542 +       GPIO_pin27_b            = 27,
2543 +       GPIO_pin27_m            = 0x08000000,
2544 +       GPIO_pin28_b            = 28,
2545 +       GPIO_pin28_m            = 0x10000000,
2546 +       GPIO_pin29_b            = 29,
2547 +       GPIO_pin29_m            = 0x20000000,
2548 +       GPIO_pin30_b            = 30,
2549 +       GPIO_pin30_m            = 0x40000000,
2550 +       GPIO_pin31_b            = 31,
2551 +       GPIO_pin31_m            = 0x80000000,
2552 +
2553 +// Alternate function pins.  Corrsponding gpiofunc bit set to GPIO_alt_v.
2554 +
2555 +       GPIO_u0sout_b           = GPIO_pin0_b,          // UART 0 serial out.
2556 +       GPIO_u0sout_m           = GPIO_pin0_m,
2557 +               GPIO_u0sout_cfg_v       = GPIO_output_v,
2558 +       GPIO_u0sinp_b   = GPIO_pin1_b,                  // UART 0 serial in.
2559 +       GPIO_u0sinp_m   = GPIO_pin1_m,
2560 +               GPIO_u0sinp_cfg_v       = GPIO_input_v,
2561 +       GPIO_u0rtsn_b   = GPIO_pin2_b,                  // UART 0 req. to send.
2562 +       GPIO_u0rtsn_m   = GPIO_pin2_m,
2563 +               GPIO_u0rtsn_cfg_v       = GPIO_output_v,
2564 +       GPIO_u0ctsn_b   = GPIO_pin3_b,                  // UART 0 clear to send.
2565 +       GPIO_u0ctsn_m   = GPIO_pin3_m,
2566 +               GPIO_u0ctsn_cfg_v       = GPIO_input_v,
2567 +       GPIO_maddr22_b          = GPIO_pin4_b,  // M&P bus bit 22.
2568 +       GPIO_maddr22_m          = GPIO_pin4_m,
2569 +               GPIO_maddr22_cfg_v      = GPIO_output_v,
2570 +
2571 +       GPIO_maddr23_b          = GPIO_pin5_b,  // M&P bus bit 23.
2572 +       GPIO_maddr23_m          = GPIO_pin5_m,
2573 +               GPIO_maddr23_cfg_v      = GPIO_output_v,
2574 +
2575 +       GPIO_maddr24_b          = GPIO_pin6_b,  // M&P bus bit 24.
2576 +       GPIO_maddr24_m          = GPIO_pin6_m,
2577 +               GPIO_maddr24_cfg_v      = GPIO_output_v,
2578 +
2579 +       GPIO_maddr25_b          = GPIO_pin7_b,  // M&P bus bit 25.
2580 +       GPIO_maddr25_m          = GPIO_pin7_m,
2581 +               GPIO_maddr25_cfg_v      = GPIO_output_v,
2582 +
2583 +       GPIO_cpu_b              = GPIO_pin8_b,  // M&P bus bit 25.
2584 +       GPIO_cpu_m              = GPIO_pin8_m,
2585 +               GPIO_cpu_cfg_v  = GPIO_output_v,
2586 +       GPIO_afspare6_b         = GPIO_pin9_b,  // reserved.
2587 +       GPIO_afspare6_m         = GPIO_pin9_m,
2588 +               GPIO_afspare6_cfg_v     = GPIO_input_v,
2589 +       GPIO_afspare4_b         = GPIO_pin10_b,         // reserved.
2590 +       GPIO_afspare4_m         = GPIO_pin10_m,
2591 +               GPIO_afspare4_cfg_v     = GPIO_input_v,
2592 +       GPIO_afspare3_b         = GPIO_pin11_b,         // reserved.
2593 +       GPIO_afspare3_m         = GPIO_pin11_m,
2594 +               GPIO_afspare3_cfg_v     = GPIO_input_v,
2595 +       GPIO_afspare2_b         = GPIO_pin12_b,         // reserved.
2596 +       GPIO_afspare2_m         = GPIO_pin12_m,
2597 +               GPIO_afspare2_cfg_v     = GPIO_input_v,
2598 +       GPIO_pcimuintn_b        = GPIO_pin13_b,         // PCI messaging int.
2599 +       GPIO_pcimuintn_m        = GPIO_pin13_m,
2600 +               GPIO_pcimuintn_cfg_v    = GPIO_output_v,
2601 +
2602 +} GPIO_DEFS_t;
2603 +
2604 +#endif // __IDT_GPIO_H__
2605 +
2606 diff -urN linux.old/include/asm-mips/rc32434/irq.h linux.dev/include/asm-mips/rc32434/irq.h
2607 --- linux.old/include/asm-mips/rc32434/irq.h    1970-01-01 01:00:00.000000000 +0100
2608 +++ linux.dev/include/asm-mips/rc32434/irq.h    2006-12-14 04:09:50.000000000 +0100
2609 @@ -0,0 +1,8 @@
2610 +#ifndef __ASM_MACH_MIPS_IRQ_H
2611 +#define __ASM_MACH_MIPS_IRQ_H
2612 +
2613 +#include <linux/autoconf.h>
2614 +
2615 +#define NR_IRQS        256
2616 +
2617 +#endif /* __ASM_MACH_MIPS_IRQ_H */
2618 diff -urN linux.old/include/asm-mips/rc32434/pci.h linux.dev/include/asm-mips/rc32434/pci.h
2619 --- linux.old/include/asm-mips/rc32434/pci.h    1970-01-01 01:00:00.000000000 +0100
2620 +++ linux.dev/include/asm-mips/rc32434/pci.h    2006-12-14 04:09:50.000000000 +0100
2621 @@ -0,0 +1,692 @@
2622 +/**************************************************************************
2623 + *
2624 + *  BRIEF MODULE DESCRIPTION
2625 + *   PCI register definitio
2626 + *
2627 + *  Copyright 2004 IDT Inc. (rischelp@idt.com)
2628 + *
2629 + *  This program is free software; you can redistribute  it and/or modify it
2630 + *  under  the terms of  the GNU General  Public License as published by the
2631 + *  Free Software Foundation;  either version 2 of the  License, or (at your
2632 + *  option) any later version.
2633 + *
2634 + *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
2635 + *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
2636 + *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
2637 + *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
2638 + *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2639 + *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
2640 + *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2641 + *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
2642 + *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2643 + *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2644 + *
2645 + *  You should have received a copy of the  GNU General Public License along
2646 + *  with this program; if not, write  to the Free Software Foundation, Inc.,
2647 + *  675 Mass Ave, Cambridge, MA 02139, USA.
2648 + *
2649 + *
2650 + **************************************************************************
2651 + * May 2004 rkt, neb.
2652 + *
2653 + * Initial Release
2654 + *
2655 + *
2656 + *
2657 + **************************************************************************
2658 + */
2659 +
2660 +#ifndef __IDT_PCI_H__
2661 +#define __IDT_PCI_H__
2662 +
2663 +enum
2664 +{
2665 +       PCI0_PhysicalAddress    = 0x18080000,
2666 +       PCI_PhysicalAddress     = PCI0_PhysicalAddress,
2667 +
2668 +       PCI0_VirtualAddress     = 0xB8080000,
2669 +       PCI_VirtualAddress      = PCI0_VirtualAddress,
2670 +} ;
2671 +
2672 +enum
2673 +{
2674 +       PCI_LbaCount    = 4,            // Local base addresses.
2675 +} ;
2676 +
2677 +typedef struct
2678 +{
2679 +       u32     a ;             // Address.
2680 +       u32     c ;             // Control.
2681 +       u32     m ;             // mapping.
2682 +} PCI_Map_s ;
2683 +
2684 +typedef struct
2685 +{
2686 +       u32             pcic ;
2687 +       u32             pcis ;
2688 +       u32             pcism ;
2689 +       u32             pcicfga ;
2690 +       u32             pcicfgd ;
2691 +       PCI_Map_s       pcilba [PCI_LbaCount] ;
2692 +       u32             pcidac ;
2693 +       u32             pcidas ;
2694 +       u32             pcidasm ;
2695 +       u32             pcidad ;
2696 +       u32             pcidma8c ;
2697 +       u32             pcidma9c ;
2698 +       u32             pcitc ;
2699 +} volatile *PCI_t ;
2700 +
2701 +// PCI messaging unit.
2702 +enum
2703 +{
2704 +       PCIM_Count      = 2,
2705 +} ;
2706 +typedef struct
2707 +{
2708 +       u32             pciim [PCIM_Count] ;
2709 +       u32             pciom [PCIM_Count] ;
2710 +       u32             pciid ;
2711 +       u32             pciiic ;
2712 +       u32             pciiim ;
2713 +       u32             pciiod ;
2714 +       u32             pciioic ;
2715 +       u32             pciioim ;
2716 +} volatile *PCIM_t ;
2717 +
2718 +/*******************************************************************************
2719 + *
2720 + * PCI Control Register
2721 + *
2722 + ******************************************************************************/
2723 +enum
2724 +{
2725 +       PCIC_en_b       = 0,
2726 +       PCIC_en_m       = 0x00000001,
2727 +       PCIC_tnr_b      = 1,
2728 +       PCIC_tnr_m      = 0x00000002,
2729 +       PCIC_sce_b      = 2,
2730 +       PCIC_sce_m      = 0x00000004,
2731 +       PCIC_ien_b      = 3,
2732 +       PCIC_ien_m      = 0x00000008,
2733 +       PCIC_aaa_b      = 4,
2734 +       PCIC_aaa_m      = 0x00000010,
2735 +       PCIC_eap_b      = 5,
2736 +       PCIC_eap_m      = 0x00000020,
2737 +       PCIC_pcim_b     = 6,
2738 +       PCIC_pcim_m     = 0x000001c0,
2739 +               PCIC_pcim_disabled_v    = 0,
2740 +               PCIC_pcim_tnr_v         = 1,    // Satellite - target not ready
2741 +               PCIC_pcim_suspend_v     = 2,    // Satellite - suspended CPU.
2742 +               PCIC_pcim_extern_v      = 3,    // Host - external arbiter.
2743 +               PCIC_pcim_fixed_v       = 4,    // Host - fixed priority arb.
2744 +               PCIC_pcim_roundrobin_v  = 5,    // Host - round robin priority.
2745 +               PCIC_pcim_reserved6_v   = 6,
2746 +               PCIC_pcim_reserved7_v   = 7,
2747 +       PCIC_igm_b      = 9,
2748 +       PCIC_igm_m      = 0x00000200,
2749 +} ;
2750 +
2751 +/*******************************************************************************
2752 + *
2753 + * PCI Status Register
2754 + *
2755 + ******************************************************************************/
2756 +enum {
2757 +       PCIS_eed_b      = 0,
2758 +       PCIS_eed_m      = 0x00000001,
2759 +       PCIS_wr_b       = 1,
2760 +       PCIS_wr_m       = 0x00000002,
2761 +       PCIS_nmi_b      = 2,
2762 +       PCIS_nmi_m      = 0x00000004,
2763 +       PCIS_ii_b       = 3,
2764 +       PCIS_ii_m       = 0x00000008,
2765 +       PCIS_cwe_b      = 4,
2766 +       PCIS_cwe_m      = 0x00000010,
2767 +       PCIS_cre_b      = 5,
2768 +       PCIS_cre_m      = 0x00000020,
2769 +       PCIS_mdpe_b     = 6,
2770 +       PCIS_mdpe_m     = 0x00000040,
2771 +       PCIS_sta_b      = 7,
2772 +       PCIS_sta_m      = 0x00000080,
2773 +       PCIS_rta_b      = 8,
2774 +       PCIS_rta_m      = 0x00000100,
2775 +       PCIS_rma_b      = 9,
2776 +       PCIS_rma_m      = 0x00000200,
2777 +       PCIS_sse_b      = 10,
2778 +       PCIS_sse_m      = 0x00000400,
2779 +       PCIS_ose_b      = 11,
2780 +       PCIS_ose_m      = 0x00000800,
2781 +       PCIS_pe_b       = 12,
2782 +       PCIS_pe_m       = 0x00001000,
2783 +       PCIS_tae_b      = 13,
2784 +       PCIS_tae_m      = 0x00002000,
2785 +       PCIS_rle_b      = 14,
2786 +       PCIS_rle_m      = 0x00004000,
2787 +       PCIS_bme_b      = 15,
2788 +       PCIS_bme_m      = 0x00008000,
2789 +       PCIS_prd_b      = 16,
2790 +       PCIS_prd_m      = 0x00010000,
2791 +       PCIS_rip_b      = 17,
2792 +       PCIS_rip_m      = 0x00020000,
2793 +} ;
2794 +
2795 +/*******************************************************************************
2796 + *
2797 + * PCI Status Mask Register
2798 + *
2799 + ******************************************************************************/
2800 +enum {
2801 +       PCISM_eed_b             = 0,
2802 +       PCISM_eed_m             = 0x00000001,
2803 +       PCISM_wr_b              = 1,
2804 +       PCISM_wr_m              = 0x00000002,
2805 +       PCISM_nmi_b             = 2,
2806 +       PCISM_nmi_m             = 0x00000004,
2807 +       PCISM_ii_b              = 3,
2808 +       PCISM_ii_m              = 0x00000008,
2809 +       PCISM_cwe_b             = 4,
2810 +       PCISM_cwe_m             = 0x00000010,
2811 +       PCISM_cre_b             = 5,
2812 +       PCISM_cre_m             = 0x00000020,
2813 +       PCISM_mdpe_b            = 6,
2814 +       PCISM_mdpe_m            = 0x00000040,
2815 +       PCISM_sta_b             = 7,
2816 +       PCISM_sta_m             = 0x00000080,
2817 +       PCISM_rta_b             = 8,
2818 +       PCISM_rta_m             = 0x00000100,
2819 +       PCISM_rma_b             = 9,
2820 +       PCISM_rma_m             = 0x00000200,
2821 +       PCISM_sse_b             = 10,
2822 +       PCISM_sse_m             = 0x00000400,
2823 +       PCISM_ose_b             = 11,
2824 +       PCISM_ose_m             = 0x00000800,
2825 +       PCISM_pe_b              = 12,
2826 +       PCISM_pe_m              = 0x00001000,
2827 +       PCISM_tae_b             = 13,
2828 +       PCISM_tae_m             = 0x00002000,
2829 +       PCISM_rle_b             = 14,
2830 +       PCISM_rle_m             = 0x00004000,
2831 +       PCISM_bme_b             = 15,
2832 +       PCISM_bme_m             = 0x00008000,
2833 +       PCISM_prd_b             = 16,
2834 +       PCISM_prd_m             = 0x00010000,
2835 +       PCISM_rip_b             = 17,
2836 +       PCISM_rip_m             = 0x00020000,
2837 +} ;
2838 +
2839 +/*******************************************************************************
2840 + *
2841 + * PCI Configuration Address Register
2842 + *
2843 + ******************************************************************************/
2844 +enum {
2845 +       PCICFGA_reg_b           = 2,
2846 +       PCICFGA_reg_m           = 0x000000fc,
2847 +               PCICFGA_reg_id_v        = 0x00>>2, //use PCFGID_
2848 +               PCICFGA_reg_04_v        = 0x04>>2, //use PCFG04_
2849 +               PCICFGA_reg_08_v        = 0x08>>2, //use PCFG08_
2850 +               PCICFGA_reg_0C_v        = 0x0C>>2, //use PCFG0C_
2851 +               PCICFGA_reg_pba0_v      = 0x10>>2, //use PCIPBA_
2852 +               PCICFGA_reg_pba1_v      = 0x14>>2, //use PCIPBA_
2853 +               PCICFGA_reg_pba2_v      = 0x18>>2, //use PCIPBA_
2854 +               PCICFGA_reg_pba3_v      = 0x1c>>2, //use PCIPBA_
2855 +               PCICFGA_reg_subsystem_v = 0x2c>>2, //use PCFGSS_
2856 +               PCICFGA_reg_3C_v        = 0x3C>>2, //use PCFG3C_
2857 +               PCICFGA_reg_pba0c_v     = 0x44>>2, //use PCIPBAC_
2858 +               PCICFGA_reg_pba0m_v     = 0x48>>2,
2859 +               PCICFGA_reg_pba1c_v     = 0x4c>>2, //use PCIPBAC_
2860 +               PCICFGA_reg_pba1m_v     = 0x50>>2,
2861 +               PCICFGA_reg_pba2c_v     = 0x54>>2, //use PCIPBAC_
2862 +               PCICFGA_reg_pba2m_v     = 0x58>>2,
2863 +               PCICFGA_reg_pba3c_v     = 0x5c>>2, //use PCIPBAC_
2864 +               PCICFGA_reg_pba3m_v     = 0x60>>2,
2865 +               PCICFGA_reg_pmgt_v      = 0x64>>2,
2866 +       PCICFGA_func_b          = 8,
2867 +       PCICFGA_func_m          = 0x00000700,
2868 +       PCICFGA_dev_b           = 11,
2869 +       PCICFGA_dev_m           = 0x0000f800,
2870 +               PCICFGA_dev_internal_v  = 0,
2871 +       PCICFGA_bus_b           = 16,
2872 +       PCICFGA_bus_m           = 0x00ff0000,
2873 +               PCICFGA_bus_type0_v     = 0,    //local bus
2874 +       PCICFGA_en_b            = 31,           // read only
2875 +       PCICFGA_en_m            = 0x80000000,
2876 +} ;
2877 +
2878 +enum {
2879 +       PCFGID_vendor_b         = 0,
2880 +       PCFGID_vendor_m         = 0x0000ffff,
2881 +               PCFGID_vendor_IDT_v             = 0x111d,
2882 +       PCFGID_device_b         = 16,
2883 +       PCFGID_device_m         = 0xffff0000,
2884 +               PCFGID_device_Korinade_v        = 0x0214,
2885 +
2886 +       PCFG04_command_ioena_b          = 1,
2887 +       PCFG04_command_ioena_m          = 0x00000001,
2888 +       PCFG04_command_memena_b         = 2,
2889 +       PCFG04_command_memena_m         = 0x00000002,
2890 +       PCFG04_command_bmena_b          = 3,
2891 +       PCFG04_command_bmena_m          = 0x00000004,
2892 +       PCFG04_command_mwinv_b          = 5,
2893 +       PCFG04_command_mwinv_m          = 0x00000010,
2894 +       PCFG04_command_parena_b         = 7,
2895 +       PCFG04_command_parena_m         = 0x00000040,
2896 +       PCFG04_command_serrena_b        = 9,
2897 +       PCFG04_command_serrena_m        = 0x00000100,
2898 +       PCFG04_command_fastbbena_b      = 10,
2899 +       PCFG04_command_fastbbena_m      = 0x00000200,
2900 +       PCFG04_status_b                 = 16,
2901 +       PCFG04_status_m                 = 0xffff0000,
2902 +       PCFG04_status_66MHz_b           = 21,   // 66 MHz enable
2903 +       PCFG04_status_66MHz_m           = 0x00200000,
2904 +       PCFG04_status_fbb_b             = 23,
2905 +       PCFG04_status_fbb_m             = 0x00800000,
2906 +       PCFG04_status_mdpe_b            = 24,
2907 +       PCFG04_status_mdpe_m            = 0x01000000,
2908 +       PCFG04_status_dst_b             = 25,
2909 +       PCFG04_status_dst_m             = 0x06000000,
2910 +       PCFG04_status_sta_b             = 27,
2911 +       PCFG04_status_sta_m             = 0x08000000,
2912 +       PCFG04_status_rta_b             = 28,
2913 +       PCFG04_status_rta_m             = 0x10000000,
2914 +       PCFG04_status_rma_b             = 29,
2915 +       PCFG04_status_rma_m             = 0x20000000,
2916 +       PCFG04_status_sse_b             = 30,
2917 +       PCFG04_status_sse_m             = 0x40000000,
2918 +       PCFG04_status_pe_b              = 31,
2919 +       PCFG04_status_pe_m              = 0x40000000,
2920 +
2921 +       PCFG08_revId_b                  = 0,
2922 +       PCFG08_revId_m                  = 0x000000ff,
2923 +       PCFG08_classCode_b              = 0,
2924 +       PCFG08_classCode_m              = 0xffffff00,
2925 +               PCFG08_classCode_bridge_v       = 06,
2926 +               PCFG08_classCode_proc_v         = 0x0b3000, // processor-MIPS
2927 +       PCFG0C_cacheline_b              = 0,
2928 +       PCFG0C_cacheline_m              = 0x000000ff,
2929 +       PCFG0C_masterLatency_b          = 8,
2930 +       PCFG0C_masterLatency_m          = 0x0000ff00,
2931 +       PCFG0C_headerType_b             = 16,
2932 +       PCFG0C_headerType_m             = 0x00ff0000,
2933 +       PCFG0C_bist_b                   = 24,
2934 +       PCFG0C_bist_m                   = 0xff000000,
2935 +
2936 +       PCIPBA_msi_b                    = 0,
2937 +       PCIPBA_msi_m                    = 0x00000001,
2938 +       PCIPBA_p_b                      = 3,
2939 +       PCIPBA_p_m                      = 0x00000004,
2940 +       PCIPBA_baddr_b                  = 8,
2941 +       PCIPBA_baddr_m                  = 0xffffff00,
2942 +
2943 +       PCFGSS_vendorId_b               = 0,
2944 +       PCFGSS_vendorId_m               = 0x0000ffff,
2945 +       PCFGSS_id_b                     = 16,
2946 +       PCFGSS_id_m                     = 0xffff0000,
2947 +
2948 +       PCFG3C_interruptLine_b          = 0,
2949 +       PCFG3C_interruptLine_m          = 0x000000ff,
2950 +       PCFG3C_interruptPin_b           = 8,
2951 +       PCFG3C_interruptPin_m           = 0x0000ff00,
2952 +       PCFG3C_minGrant_b               = 16,
2953 +       PCFG3C_minGrant_m               = 0x00ff0000,
2954 +       PCFG3C_maxLat_b                 = 24,
2955 +       PCFG3C_maxLat_m                 = 0xff000000,
2956 +
2957 +       PCIPBAC_msi_b                   = 0,
2958 +       PCIPBAC_msi_m                   = 0x00000001,
2959 +       PCIPBAC_p_b                     = 1,
2960 +       PCIPBAC_p_m                     = 0x00000002,
2961 +       PCIPBAC_size_b                  = 2,
2962 +       PCIPBAC_size_m                  = 0x0000007c,
2963 +       PCIPBAC_sb_b                    = 7,
2964 +       PCIPBAC_sb_m                    = 0x00000080,
2965 +       PCIPBAC_pp_b                    = 8,
2966 +       PCIPBAC_pp_m                    = 0x00000100,
2967 +       PCIPBAC_mr_b                    = 9,
2968 +       PCIPBAC_mr_m                    = 0x00000600,
2969 +               PCIPBAC_mr_read_v       =0,     //no prefetching
2970 +               PCIPBAC_mr_readLine_v   =1,
2971 +               PCIPBAC_mr_readMult_v   =2,
2972 +       PCIPBAC_mrl_b                   = 11,
2973 +       PCIPBAC_mrl_m                   = 0x00000800,
2974 +       PCIPBAC_mrm_b                   = 12,
2975 +       PCIPBAC_mrm_m                   = 0x00001000,
2976 +       PCIPBAC_trp_b                   = 13,
2977 +       PCIPBAC_trp_m                   = 0x00002000,
2978 +
2979 +       PCFG40_trdyTimeout_b            = 0,
2980 +       PCFG40_trdyTimeout_m            = 0x000000ff,
2981 +       PCFG40_retryLim_b               = 8,
2982 +       PCFG40_retryLim_m               = 0x0000ff00,
2983 +};
2984 +
2985 +/*******************************************************************************
2986 + *
2987 + * PCI Local Base Address [0|1|2|3] Register
2988 + *
2989 + ******************************************************************************/
2990 +enum {
2991 +       PCILBA_baddr_b          = 0,            // In PCI_t -> pcilba [] .a
2992 +       PCILBA_baddr_m          = 0xffffff00,
2993 +} ;
2994 +/*******************************************************************************
2995 + *
2996 + * PCI Local Base Address Control Register
2997 + *
2998 + ******************************************************************************/
2999 +enum {
3000 +       PCILBAC_msi_b           = 0,            // In pPci->pcilba[i].c
3001 +       PCILBAC_msi_m           = 0x00000001,
3002 +               PCILBAC_msi_mem_v       = 0,
3003 +               PCILBAC_msi_io_v        = 1,
3004 +       PCILBAC_size_b          = 2,    // In pPci->pcilba[i].c
3005 +       PCILBAC_size_m          = 0x0000007c,
3006 +       PCILBAC_sb_b            = 7,    // In pPci->pcilba[i].c
3007 +       PCILBAC_sb_m            = 0x00000080,
3008 +       PCILBAC_rt_b            = 8,    // In pPci->pcilba[i].c
3009 +       PCILBAC_rt_m            = 0x00000100,
3010 +               PCILBAC_rt_noprefetch_v = 0, // mem read
3011 +               PCILBAC_rt_prefetch_v   = 1, // mem readline
3012 +} ;
3013 +
3014 +/*******************************************************************************
3015 + *
3016 + * PCI Local Base Address [0|1|2|3] Mapping Register
3017 + *
3018 + ******************************************************************************/
3019 +enum {
3020 +       PCILBAM_maddr_b         = 8,
3021 +       PCILBAM_maddr_m         = 0xffffff00,
3022 +} ;
3023 +
3024 +/*******************************************************************************
3025 + *
3026 + * PCI Decoupled Access Control Register
3027 + *
3028 + ******************************************************************************/
3029 +enum {
3030 +       PCIDAC_den_b            = 0,
3031 +       PCIDAC_den_m            = 0x00000001,
3032 +} ;
3033 +
3034 +/*******************************************************************************
3035 + *
3036 + * PCI Decoupled Access Status Register
3037 + *
3038 + ******************************************************************************/
3039 +enum {
3040 +       PCIDAS_d_b      = 0,
3041 +       PCIDAS_d_m      = 0x00000001,
3042 +       PCIDAS_b_b      = 1,
3043 +       PCIDAS_b_m      = 0x00000002,
3044 +       PCIDAS_e_b      = 2,
3045 +       PCIDAS_e_m      = 0x00000004,
3046 +       PCIDAS_ofe_b    = 3,
3047 +       PCIDAS_ofe_m    = 0x00000008,
3048 +       PCIDAS_off_b    = 4,
3049 +       PCIDAS_off_m    = 0x00000010,
3050 +       PCIDAS_ife_b    = 5,
3051 +       PCIDAS_ife_m    = 0x00000020,
3052 +       PCIDAS_iff_b    = 6,
3053 +       PCIDAS_iff_m    = 0x00000040,
3054 +} ;
3055 +
3056 +/*******************************************************************************
3057 + *
3058 + * PCI DMA Channel 8 Configuration Register
3059 + *
3060 + ******************************************************************************/
3061 +enum
3062 +{
3063 +       PCIDMA8C_mbs_b  = 0,            // Maximum Burst Size.
3064 +       PCIDMA8C_mbs_m  = 0x00000fff,   // { pcidma8c }
3065 +       PCIDMA8C_our_b  = 12,           // Optimize Unaligned Burst Reads.
3066 +       PCIDMA8C_our_m  = 0x00001000,   // { pcidma8c }
3067 +} ;
3068 +
3069 +/*******************************************************************************
3070 + *
3071 + * PCI DMA Channel 9 Configuration Register
3072 + *
3073 + ******************************************************************************/
3074 +enum
3075 +{
3076 +       PCIDMA9C_mbs_b  = 0,            // Maximum Burst Size.
3077 +       PCIDMA9C_mbs_m  = 0x00000fff, // { pcidma9c }
3078 +} ;
3079 +
3080 +/*******************************************************************************
3081 + *
3082 + * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
3083 + *
3084 + ******************************************************************************/
3085 +enum {
3086 +       PCIDMAD_pt_b            = 22,           // in DEVCMD field (descriptor)
3087 +       PCIDMAD_pt_m            = 0x00c00000,   // preferred transaction field
3088 +               // These are for reads (DMA channel 8)
3089 +               PCIDMAD_devcmd_mr_v     = 0,    //memory read
3090 +               PCIDMAD_devcmd_mrl_v    = 1,    //memory read line
3091 +               PCIDMAD_devcmd_mrm_v    = 2,    //memory read multiple
3092 +               PCIDMAD_devcmd_ior_v    = 3,    //I/O read
3093 +               // These are for writes (DMA channel 9)
3094 +               PCIDMAD_devcmd_mw_v     = 0,    //memory write
3095 +               PCIDMAD_devcmd_mwi_v    = 1,    //memory write invalidate
3096 +               PCIDMAD_devcmd_iow_v    = 3,    //I/O write
3097 +
3098 +       // Swap byte field applies to both DMA channel 8 and 9
3099 +       PCIDMAD_sb_b            = 24,           // in DEVCMD field (descriptor)
3100 +       PCIDMAD_sb_m            = 0x01000000,   // swap byte field
3101 +} ;
3102 +
3103 +
3104 +/*******************************************************************************
3105 + *
3106 + * PCI Target Control Register
3107 + *
3108 + ******************************************************************************/
3109 +enum
3110 +{
3111 +       PCITC_rtimer_b          = 0,            // In PCITC_t -> pcitc
3112 +       PCITC_rtimer_m          = 0x000000ff,
3113 +       PCITC_dtimer_b          = 8,            // In PCITC_t -> pcitc
3114 +       PCITC_dtimer_m          = 0x0000ff00,
3115 +       PCITC_rdr_b             = 18,           // In PCITC_t -> pcitc
3116 +       PCITC_rdr_m             = 0x00040000,
3117 +       PCITC_ddt_b             = 19,           // In PCITC_t -> pcitc
3118 +       PCITC_ddt_m             = 0x00080000,
3119 +} ;
3120 +/*******************************************************************************
3121 + *
3122 + * PCI messaging unit [applies to both inbound and outbound registers ]
3123 + *
3124 + ******************************************************************************/
3125 +enum
3126 +{
3127 +       PCIM_m0_b       = 0,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3128 +       PCIM_m0_m       = 0x00000001,   // inbound or outbound message 0
3129 +       PCIM_m1_b       = 1,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3130 +       PCIM_m1_m       = 0x00000002,   // inbound or outbound message 1
3131 +       PCIM_db_b       = 2,            // In PCIM_t -> {pci{iic,iim,ioic,ioim}}
3132 +       PCIM_db_m       = 0x00000004,   // inbound or outbound doorbell
3133 +};
3134 +
3135 +
3136 +
3137 +
3138 +
3139 +
3140 +#define PCI_MSG_VirtualAddress      0xB8088010
3141 +#define rc32434_pci ((volatile PCI_t) PCI0_VirtualAddress)
3142 +#define rc32434_pci_msg ((volatile PCIM_t) PCI_MSG_VirtualAddress)
3143 +
3144 +#define PCIM_SHFT              0x6
3145 +#define PCIM_BIT_LEN           0x7
3146 +#define PCIM_H_EA              0x3
3147 +#define PCIM_H_IA_FIX          0x4
3148 +#define PCIM_H_IA_RR           0x5
3149 +
3150 +#define PCI_ADDR_START         0x50000000
3151 +
3152 +#define CPUTOPCI_MEM_WIN       0x02000000
3153 +#define CPUTOPCI_IO_WIN                0x00100000
3154 +#define PCILBA_SIZE_SHFT       2
3155 +#define PCILBA_SIZE_MASK       0x1F
3156 +#define SIZE_256MB             0x1C
3157 +#define SIZE_128MB             0x1B
3158 +#define SIZE_64MB               0x1A
3159 +#define SIZE_32MB              0x19
3160 +#define SIZE_16MB               0x18
3161 +#define SIZE_4MB               0x16
3162 +#define SIZE_2MB               0x15
3163 +#define SIZE_1MB               0x14
3164 +#define KORINA_CONFIG0_ADDR    0x80000000
3165 +#define KORINA_CONFIG1_ADDR    0x80000004
3166 +#define KORINA_CONFIG2_ADDR    0x80000008
3167 +#define KORINA_CONFIG3_ADDR    0x8000000C
3168 +#define KORINA_CONFIG4_ADDR    0x80000010
3169 +#define KORINA_CONFIG5_ADDR    0x80000014
3170 +#define KORINA_CONFIG6_ADDR    0x80000018
3171 +#define KORINA_CONFIG7_ADDR    0x8000001C
3172 +#define KORINA_CONFIG8_ADDR    0x80000020
3173 +#define KORINA_CONFIG9_ADDR    0x80000024
3174 +#define KORINA_CONFIG10_ADDR   0x80000028
3175 +#define KORINA_CONFIG11_ADDR   0x8000002C
3176 +#define KORINA_CONFIG12_ADDR   0x80000030
3177 +#define KORINA_CONFIG13_ADDR   0x80000034
3178 +#define KORINA_CONFIG14_ADDR   0x80000038
3179 +#define KORINA_CONFIG15_ADDR   0x8000003C
3180 +#define KORINA_CONFIG16_ADDR   0x80000040
3181 +#define KORINA_CONFIG17_ADDR   0x80000044
3182 +#define KORINA_CONFIG18_ADDR   0x80000048
3183 +#define KORINA_CONFIG19_ADDR   0x8000004C
3184 +#define KORINA_CONFIG20_ADDR   0x80000050
3185 +#define KORINA_CONFIG21_ADDR   0x80000054
3186 +#define KORINA_CONFIG22_ADDR   0x80000058
3187 +#define KORINA_CONFIG23_ADDR   0x8000005C
3188 +#define KORINA_CONFIG24_ADDR   0x80000060
3189 +#define KORINA_CONFIG25_ADDR   0x80000064
3190 +#define KORINA_CMD             (PCFG04_command_ioena_m | \
3191 +                                PCFG04_command_memena_m | \
3192 +                                PCFG04_command_bmena_m | \
3193 +                                PCFG04_command_mwinv_m | \
3194 +                                PCFG04_command_parena_m | \
3195 +                                PCFG04_command_serrena_m )
3196 +
3197 +#define KORINA_STAT            (PCFG04_status_mdpe_m | \
3198 +                                PCFG04_status_sta_m  | \
3199 +                                PCFG04_status_rta_m  | \
3200 +                                PCFG04_status_rma_m  | \
3201 +                                PCFG04_status_sse_m  | \
3202 +                                PCFG04_status_pe_m)
3203 +
3204 +#define KORINA_CNFG1           ((KORINA_STAT<<16)|KORINA_CMD)
3205 +
3206 +#define KORINA_REVID           0
3207 +#define KORINA_CLASS_CODE      0
3208 +#define KORINA_CNFG2           ((KORINA_CLASS_CODE<<8) | \
3209 +                                 KORINA_REVID)
3210 +
3211 +#define KORINA_CACHE_LINE_SIZE 4
3212 +#define KORINA_MASTER_LAT      0x3c
3213 +#define KORINA_HEADER_TYPE     0
3214 +#define KORINA_BIST            0
3215 +
3216 +#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
3217 +                     (KORINA_HEADER_TYPE<<16) | \
3218 +                     (KORINA_MASTER_LAT<<8) | \
3219 +                     KORINA_CACHE_LINE_SIZE )
3220 +
3221 +#define KORINA_BAR0    0x00000008 /* 128 MB Memory */
3222 +#define KORINA_BAR1    0x18800001 /* 1 MB IO */
3223 +#define KORINA_BAR2    0x18000001 /* 2 MB IO window for Korina
3224 +                                       internal Registers */
3225 +#define KORINA_BAR3    0x48000008 /* Spare 128 MB Memory */
3226 +
3227 +#define KORINA_CNFG4   KORINA_BAR0
3228 +#define KORINA_CNFG5    KORINA_BAR1
3229 +#define KORINA_CNFG6   KORINA_BAR2
3230 +#define KORINA_CNFG7   KORINA_BAR3
3231 +
3232 +#define KORINA_SUBSYS_VENDOR_ID 0x011d
3233 +#define KORINA_SUBSYSTEM_ID    0x0214
3234 +#define KORINA_CNFG8           0
3235 +#define KORINA_CNFG9           0
3236 +#define KORINA_CNFG10          0
3237 +#define KORINA_CNFG11  ((KORINA_SUBSYS_VENDOR_ID<<16) | \
3238 +                         KORINA_SUBSYSTEM_ID)
3239 +#define KORINA_INT_LINE                1
3240 +#define KORINA_INT_PIN         1
3241 +#define KORINA_MIN_GNT         8
3242 +#define KORINA_MAX_LAT         0x38
3243 +#define KORINA_CNFG12          0
3244 +#define KORINA_CNFG13          0
3245 +#define KORINA_CNFG14          0
3246 +#define KORINA_CNFG15  ((KORINA_MAX_LAT<<24) | \
3247 +                        (KORINA_MIN_GNT<<16) | \
3248 +                        (KORINA_INT_PIN<<8)  | \
3249 +                         KORINA_INT_LINE)
3250 +#define        KORINA_RETRY_LIMIT      0x80
3251 +#define KORINA_TRDY_LIMIT      0x80
3252 +#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
3253 +                       KORINA_TRDY_LIMIT)
3254 +#define PCI_PBAxC_R            0x0
3255 +#define PCI_PBAxC_RL           0x1
3256 +#define PCI_PBAxC_RM           0x2
3257 +#define SIZE_SHFT              2
3258 +
3259 +#if defined(__MIPSEB__)
3260 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | PCIPBAC_sb_m | \
3261 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
3262 +                         PCIPBAC_pp_m | \
3263 +                         (SIZE_128MB<<SIZE_SHFT) | \
3264 +                          PCIPBAC_p_m)
3265 +#else
3266 +#define KORINA_PBA0C   ( PCIPBAC_mrl_m | \
3267 +                         ((PCI_PBAxC_RM &0x3) << PCIPBAC_mr_b) | \
3268 +                         PCIPBAC_pp_m | \
3269 +                         (SIZE_128MB<<SIZE_SHFT) | \
3270 +                          PCIPBAC_p_m)
3271 +#endif
3272 +#define KORINA_CNFG17  KORINA_PBA0C
3273 +#define KORINA_PBA0M   0x0
3274 +#define KORINA_CNFG18  KORINA_PBA0M
3275 +
3276 +#if defined(__MIPSEB__)
3277 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
3278 +                         PCIPBAC_msi_m)
3279 +#else
3280 +#define KORINA_PBA1C   ((SIZE_1MB<<SIZE_SHFT) | \
3281 +                         PCIPBAC_msi_m)
3282 +#endif
3283 +#define KORINA_CNFG19  KORINA_PBA1C
3284 +#define KORINA_PBA1M   0x0
3285 +#define KORINA_CNFG20  KORINA_PBA1M
3286 +
3287 +#if defined(__MIPSEB__)
3288 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | PCIPBAC_sb_m | \
3289 +                         PCIPBAC_msi_m)
3290 +#else
3291 +#define KORINA_PBA2C   ((SIZE_2MB<<SIZE_SHFT) | \
3292 +                         PCIPBAC_msi_m)
3293 +#endif
3294 +#define KORINA_CNFG21  KORINA_PBA2C
3295 +#define KORINA_PBA2M   0x18000000
3296 +#define KORINA_CNFG22  KORINA_PBA2M
3297 +#define KORINA_PBA3C   0
3298 +#define KORINA_CNFG23  KORINA_PBA3C
3299 +#define KORINA_PBA3M   0
3300 +#define KORINA_CNFG24  KORINA_PBA3M
3301 +
3302 +
3303 +
3304 +#define        PCITC_DTIMER_VAL        8
3305 +#define PCITC_RTIMER_VAL       0x10
3306 +
3307 +
3308 +
3309 +
3310 +#endif // __IDT_PCI_H__
3311 +
3312 +
3313 +
3314 diff -urN linux.old/include/asm-mips/rc32434/rb.h linux.dev/include/asm-mips/rc32434/rb.h
3315 --- linux.old/include/asm-mips/rc32434/rb.h     1970-01-01 01:00:00.000000000 +0100
3316 +++ linux.dev/include/asm-mips/rc32434/rb.h     2006-12-14 04:09:50.000000000 +0100
3317 @@ -0,0 +1,84 @@
3318 +/*
3319 + *  Copyright (C) 2004 IDT Inc.
3320 + *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
3321 + *
3322 + *  This program is free software; you can redistribute it and/or modify
3323 + *  it under the terms of the GNU General Public License as published by
3324 + *  the Free Software Foundation; either version 2 of the License, or
3325 + *  (at your option) any later version.
3326 + *
3327 + *  This program is distributed in the hope that it will be useful,
3328 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
3329 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3330 + *  GNU General Public License for more details.
3331 + *
3332 + */
3333 +#ifndef __MIPS_RB_H__
3334 +#define __MIPS_RB_H__
3335 +#include <linux/genhd.h>
3336 +
3337 +#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
3338 +#define DEV0BASE 0x010000
3339 +#define DEV0MASK 0x010004
3340 +#define DEV0C 0x010008
3341 +#define DEV0TC 0x01000C
3342 +#define DEV1BASE 0x010010
3343 +#define DEV1MASK 0x010014
3344 +#define DEV1C 0x010018
3345 +#define DEV1TC 0x01001C
3346 +#define DEV2BASE 0x010020
3347 +#define DEV2MASK 0x010024
3348 +#define DEV2C 0x010028
3349 +#define DEV2TC 0x01002C
3350 +#define DEV3BASE 0x010030
3351 +#define DEV3MASK 0x010034
3352 +#define DEV3C 0x010038
3353 +#define DEV3TC 0x01003C
3354 +#define BTCS 0x010040
3355 +#define BTCOMPARE 0x010044
3356 +#define GPIOFUNC 0x050000
3357 +#define GPIOCFG 0x050004
3358 +#define GPIOD 0x050008
3359 +#define GPIOILEVEL 0x05000C
3360 +#define GPIOISTAT 0x050010
3361 +#define GPIONMIEN 0x050014
3362 +#define IMASK6 0x038038
3363 +
3364 +#define LO_WPX (1 << 0)
3365 +#define LO_ALE (1 << 1)
3366 +#define LO_CLE (1 << 2)
3367 +#define LO_CEX (1 << 3)
3368 +#define LO_FOFF (1 << 5)
3369 +#define LO_SPICS (1 << 6)
3370 +#define LO_ULED (1 << 7)
3371 +
3372 +typedef enum {
3373 +       FUNC = 0x00,
3374 +       CFG = 0x04,
3375 +       DATA = 0x08,
3376 +       ILEVEL = 0x0c,
3377 +       ISTAT = 0x10,
3378 +       NMIEN = 0x14
3379 +} gpio_func;
3380 +
3381 +extern void changeLatchU5(unsigned char orMask, unsigned char nandMask);
3382 +extern unsigned get434Reg(unsigned regOffs);
3383 +extern void set434Reg(unsigned regOffs, unsigned bit, unsigned len, unsigned val);
3384 +extern void gpio_set(gpio_func func, u32 mask, u32 value);
3385 +extern u32 gpio_get(gpio_func func);
3386 +
3387 +#define get434Reg(x) (*(volatile unsigned *) (IDT434_REG_BASE + (x)))
3388 +
3389 +struct korina_device {
3390 +       char *name;
3391 +       unsigned char mac[6];
3392 +       struct net_device *dev;
3393 +};
3394 +
3395 +struct cf_device {
3396 +       int gpio_pin;
3397 +       void *dev;
3398 +       struct gendisk *gd;
3399 +};
3400 +
3401 +#endif
3402 diff -urN linux.old/include/asm-mips/rc32434/rc32434.h linux.dev/include/asm-mips/rc32434/rc32434.h
3403 --- linux.old/include/asm-mips/rc32434/rc32434.h        1970-01-01 01:00:00.000000000 +0100
3404 +++ linux.dev/include/asm-mips/rc32434/rc32434.h        2006-12-14 04:09:50.000000000 +0100
3405 @@ -0,0 +1,122 @@
3406 +/*
3407 + ***************************************************************************
3408 + * Definitions for IDT RC323434 CPU.
3409 + *
3410 + ****************************************************************************
3411 + * Kiran Rao
3412 + *
3413 + * Original form
3414 + ****************************************************************************
3415 + * P. Sadik   Oct 08, 2003
3416 + *
3417 + * Started revision history
3418 + * Made IDT_BUS_FREQ a kernel configuration parameter
3419 + ****************************************************************************
3420 + * P. Sadik   Oct 10, 2003
3421 + *
3422 + * Removed IDT_BUS_FREQ, since this parameter is no longer required. Instead
3423 + * idt_cpu_freq is used everywhere
3424 + ****************************************************************************
3425 + * P. Sadik   Oct 20, 2003
3426 + *
3427 + * Removed RC32434_BASE_BAUD
3428 + ****************************************************************************
3429 +*/
3430 +#ifndef _RC32434_H_
3431 +#define _RC32434_H_
3432 +
3433 +#include <linux/autoconf.h>
3434 +#include <linux/delay.h>
3435 +#include <asm/io.h>
3436 +
3437 +#define RC32434_REG_BASE   0x18000000
3438 +
3439 +#define interrupt ((volatile INT_t ) INT0_VirtualAddress)
3440 +#define gpio     ((volatile GPIO_t) GPIO0_VirtualAddress)
3441 +
3442 +
3443 +#define IDT_CLOCK_MULT 2
3444 +#define MIPS_CPU_TIMER_IRQ 7
3445 +/* Interrupt Controller */
3446 +#define IC_GROUP0_PEND     (RC32434_REG_BASE + 0x38000)
3447 +#define IC_GROUP0_MASK     (RC32434_REG_BASE + 0x38008)
3448 +#define IC_GROUP_OFFSET    0x0C
3449 +
3450 +#define NUM_INTR_GROUPS    5
3451 +/* 16550 UARTs */
3452 +
3453 +#define GROUP0_IRQ_BASE 8              /* GRP2 IRQ numbers start here */
3454 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) /* GRP3 IRQ numbers start here */
3455 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) /* GRP4 IRQ numbers start here */
3456 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) /* GRP5 IRQ numbers start here */
3457 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32)
3458 +
3459 +
3460 +#ifdef __MIPSEB__
3461 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58003)
3462 +#else
3463 +#define RC32434_UART0_BASE (RC32434_REG_BASE + 0x58000)
3464 +#endif
3465 +
3466 +#define RC32434_UART0_IRQ  GROUP3_IRQ_BASE + 0
3467 +// #define EB434_UART1_IRQ    GROUP4_IRQ_BASE + 11
3468 +
3469 +#define local_readl(addr) __raw_readl(addr)
3470 +#define local_writel(l,addr) __raw_writel(l,addr)
3471 +
3472 +/* cpu pipeline flush */
3473 +static inline void rc32434_sync(void)
3474 +{
3475 +        __asm__ volatile ("sync");
3476 +}
3477 +
3478 +static inline void rc32434_sync_udelay(int us)
3479 +{
3480 +        __asm__ volatile ("sync");
3481 +        udelay(us);
3482 +}
3483 +
3484 +static inline void rc32434_sync_delay(int ms)
3485 +{
3486 +        __asm__ volatile ("sync");
3487 +        mdelay(ms);
3488 +}
3489 +
3490 +/*
3491 + * C access to CLZ and CLO instructions
3492 + * (count leading zeroes/ones).
3493 + */
3494 +static inline int rc32434_clz(unsigned long val)
3495 +{
3496 +       int ret;
3497 +        __asm__ volatile (
3498 +               ".set\tnoreorder\n\t"
3499 +               ".set\tnoat\n\t"
3500 +               ".set\tmips32\n\t"
3501 +               "clz\t%0,%1\n\t"
3502 +                ".set\tmips0\n\t"
3503 +                ".set\tat\n\t"
3504 +                ".set\treorder"
3505 +                : "=r" (ret)
3506 +               : "r" (val));
3507 +
3508 +       return ret;
3509 +}
3510 +static inline int rc32434_clo(unsigned long val)
3511 +{
3512 +       int ret;
3513 +        __asm__ volatile (
3514 +               ".set\tnoreorder\n\t"
3515 +               ".set\tnoat\n\t"
3516 +               ".set\tmips32\n\t"
3517 +               "clo\t%0,%1\n\t"
3518 +                ".set\tmips0\n\t"
3519 +                ".set\tat\n\t"
3520 +                ".set\treorder"
3521 +                : "=r" (ret)
3522 +               : "r" (val));
3523 +
3524 +       return ret;
3525 +}
3526 +
3527 +#endif /* _RC32434_H_ */
3528