kernel: bump 4.14 to 4.14.180
[oweals/openwrt.git] / target / linux / ramips / patches-5.4 / 0301-dt-bindings-add-documentation-for-mt7621-nand-driver.patch
1 From 3d5f4da8296b23eb3abf8b13122b0d06a215e79c Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Wed, 1 Apr 2020 02:07:59 +0800
4 Subject: [PATCH 2/2] dt-bindings: add documentation for mt7621-nand driver
5
6 This patch adds documentation for MediaTek MT7621 NAND flash controller
7 driver.
8
9 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
10 ---
11  .../bindings/mtd/mediatek,mt7621-nfc.yaml          | 68 ++++++++++++++++++++++
12  1 file changed, 68 insertions(+)
13  create mode 100644 Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
14
15 --- /dev/null
16 +++ b/Documentation/devicetree/bindings/mtd/mediatek,mt7621-nfc.yaml
17 @@ -0,0 +1,68 @@
18 +# SPDX-License-Identifier: GPL-2.0
19 +%YAML 1.2
20 +---
21 +$id: http://devicetree.org/schemas/mtd/mediatek,mt7621-nfc.yaml#
22 +$schema: http://devicetree.org/meta-schemas/core.yaml#
23 +
24 +title: MediaTek MT7621 SoC NAND Flash Controller (NFC) DT binding
25 +
26 +maintainers:
27 +  - Weijie Gao <weijie.gao@mediatek.com>
28 +
29 +description: |
30 +  This driver uses a single node to describe both NAND Flash controller
31 +  interface (NFI) and ECC engine for MT7621 SoC.
32 +  MT7621 supports only one chip select.
33 +
34 +properties:
35 +  "#address-cells": false
36 +  "#size-cells": false
37 +
38 +  compatible:
39 +    enum:
40 +      - mediatek,mt7621-nfc
41 +
42 +  reg:
43 +    items:
44 +      - description: Register base of NFI core
45 +      - description: Register base of ECC engine
46 +
47 +  reg-names:
48 +    items:
49 +      - const: nfi
50 +      - const: ecc
51 +
52 +  clocks:
53 +    items:
54 +      - description: Source clock for NFI core, fixed 125MHz
55 +
56 +  clock-names:
57 +    items:
58 +      - const: nfi_clk
59 +
60 +required:
61 +  - compatible
62 +  - reg
63 +  - reg-names
64 +  - clocks
65 +  - clock-names
66 +
67 +examples:
68 +  - |
69 +    nficlock: nficlock {
70 +       #clock-cells = <0>;
71 +       compatible = "fixed-clock";
72 +
73 +       clock-frequency = <125000000>;
74 +    };
75 +
76 +    nand@1e003000 {
77 +       compatible = "mediatek,mt7621-nfc";
78 +
79 +       reg = <0x1e003000 0x800
80 +              0x1e003800 0x800>;
81 +       reg-names = "nfi", "ecc";
82 +
83 +       clocks = <&nficlock>;
84 +       clock-names = "nfi_clk";
85 +    };