target/linux/ramips/patches-4.9/101-mt7621-timer.patch

   1 Index: linux-4.9.44/arch/mips/ralink/mt7621.c
   2 ===================================================================
   3 --- linux-4.9.44.orig/arch/mips/ralink/mt7621.c
   4 +++ linux-4.9.44/arch/mips/ralink/mt7621.c
   5 @@ -18,6 +18,7 @@
   6  #include <asm/mach-ralink/ralink_regs.h>
   7  #include <asm/mach-ralink/mt7621.h>
   8  #include <asm/mips-boards/launch.h>
   9 +#include <asm/delay.h>
  10
  11  #include <pinmux.h>
  12
  13 @@ -179,6 +180,58 @@ bool plat_cpu_core_present(int core)
  14         return true;
  15  }
  16
  17 +#define LPS_PREC 8
  18 +/*
  19 +*  Re-calibration lpj(loop-per-jiffy).
  20 +*  (derived from kernel/calibrate.c)
  21 +*/
  22 +static int udelay_recal(void)
  23 +{
  24 +       unsigned int i, lpj = 0;
  25 +       unsigned long ticks, loopbit;
  26 +       int lps_precision = LPS_PREC;
  27 +
  28 +       lpj = (1<<12);
  29 +
  30 +       while ((lpj <<= 1) != 0) {
  31 +               /* wait for "start of" clock tick */
  32 +               ticks = jiffies;
  33 +               while (ticks == jiffies)
  34 +                       /* nothing */;
  35 +
  36 +               /* Go .. */
  37 +               ticks = jiffies;
  38 +               __delay(lpj);
  39 +               ticks = jiffies - ticks;
  40 +               if (ticks)
  41 +                       break;
  42 +       }
  43 +
  44 +       /*
  45 +        * Do a binary approximation to get lpj set to
  46 +        * equal one clock (up to lps_precision bits)
  47 +        */
  48 +       lpj >>= 1;
  49 +       loopbit = lpj;
  50 +       while (lps_precision-- && (loopbit >>= 1)) {
  51 +               lpj |= loopbit;
  52 +               ticks = jiffies;
  53 +               while (ticks == jiffies)
  54 +                       /* nothing */;
  55 +               ticks = jiffies;
  56 +               __delay(lpj);
  57 +               if (jiffies != ticks)   /* longer than 1 tick */
  58 +                       lpj &= ~loopbit;
  59 +       }
  60 +       printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
  61 +
  62 +       for(i=0; i< NR_CPUS; i++)
  63 +               cpu_data[i].udelay_val = lpj;
  64 +
  65 +       return 0;
  66 +}
  67 +device_initcall(udelay_recal);
  68 +
  69  void prom_soc_init(struct ralink_soc_info *soc_info)
  70  {
  71         void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
  72 Index: linux-4.9.44/arch/mips/ralink/Kconfig
  73 ===================================================================
  74 --- linux-4.9.44.orig/arch/mips/ralink/Kconfig
  75 +++ linux-4.9.44/arch/mips/ralink/Kconfig
  76 @@ -57,6 +57,7 @@ choice
  77                 select CLKSRC_MIPS_GIC
  78                 select HW_HAS_PCI
  79                 select WEAK_REORDERING_BEYOND_LLSC
  80 +               select GENERIC_CLOCKEVENTS_BROADCAST
  81  endchoice
  82
  83  choice
  84 Index: linux-4.9.44/arch/mips/ralink/timer-gic.c
  85 ===================================================================
  86 --- linux-4.9.44.orig/arch/mips/ralink/timer-gic.c
  87 +++ linux-4.9.44/arch/mips/ralink/timer-gic.c
  88 @@ -12,6 +12,7 @@
  89  #include <linux/of.h>
  90  #include <linux/clk-provider.h>
  91  #include <linux/clocksource.h>
  92 +#include <asm/time.h>
  93
  94  #include "common.h"
  95
  96 @@ -19,6 +20,8 @@ void __init plat_time_init(void)
  97  {
  98         ralink_of_remap();
  99
 100 +       mips_hpt_frequency = 880000000 / 2;
 101 +
 102         of_clk_init(NULL);
 103         clocksource_probe();
 104  }