target/linux/ramips/patches-4.9/0039-mtd-add-mt7621-nand-support.patch

   1 From 0e1c4e3c97b83b4e7da65b1c56f0a7d40736ac53 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 27 Jul 2014 11:05:17 +0100
   4 Subject: [PATCH 39/53] mtd: add mt7621 nand support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/mtd/nand/Kconfig            |    6 +
   9  drivers/mtd/nand/Makefile           |    1 +
  10  drivers/mtd/nand/bmt.c              |  750 ++++++++++++
  11  drivers/mtd/nand/bmt.h              |   80 ++
  12  drivers/mtd/nand/dev-nand.c         |   63 +
  13  drivers/mtd/nand/mt6575_typedefs.h  |  340 ++++++
  14  drivers/mtd/nand/mtk_nand2.c         | 2304 +++++++++++++++++++++++++++++++++++
  15  drivers/mtd/nand/mtk_nand2.h         |  452 +++++++
  16  drivers/mtd/nand/nand_base.c        |    6 +-
  17  drivers/mtd/nand/nand_bbt.c         |   19 +
  18  drivers/mtd/nand/nand_def.h         |  123 ++
  19  drivers/mtd/nand/nand_device_list.h |   55 +
  20  drivers/mtd/nand/partition.h        |  115 ++
  21  13 files changed, 4311 insertions(+), 3 deletions(-)
  22  create mode 100644 drivers/mtd/nand/bmt.c
  23  create mode 100644 drivers/mtd/nand/bmt.h
  24  create mode 100644 drivers/mtd/nand/dev-nand.c
  25  create mode 100644 drivers/mtd/nand/mt6575_typedefs.h
  26  create mode 100644 drivers/mtd/nand/mtk_nand2.c
  27  create mode 100644 drivers/mtd/nand/mtk_nand2.h
  28  create mode 100644 drivers/mtd/nand/nand_def.h
  29  create mode 100644 drivers/mtd/nand/nand_device_list.h
  30  create mode 100644 drivers/mtd/nand/partition.h
  31
  32 --- a/drivers/mtd/nand/Kconfig
  33 +++ b/drivers/mtd/nand/Kconfig
  34 @@ -569,4 +569,10 @@ config MTD_NAND_MTK
  35           Enables support for NAND controller on MTK SoCs.
  36           This controller is found on mt27xx, mt81xx, mt65xx SoCs.
  37
  38 +config MTK_MTD_NAND
  39 +       tristate "Support for MTK SoC NAND controller"
  40 +       depends on SOC_MT7621
  41 +       select MTD_NAND_IDS
  42 +       select MTD_NAND_ECC
  43 +
  44  endif # MTD_NAND
  45 --- a/drivers/mtd/nand/Makefile
  46 +++ b/drivers/mtd/nand/Makefile
  47 @@ -58,5 +58,6 @@ obj-$(CONFIG_MTD_NAND_HISI504)                +
  48  obj-$(CONFIG_MTD_NAND_BRCMNAND)                += brcmnand/
  49  obj-$(CONFIG_MTD_NAND_QCOM)            += qcom_nandc.o
  50  obj-$(CONFIG_MTD_NAND_MTK)             += mtk_nand.o mtk_ecc.o
  51 +obj-$(CONFIG_MTK_MTD_NAND)             += mtk_nand2.o bmt.o
  52
  53  nand-objs := nand_base.o nand_bbt.o nand_timings.o
  54 --- /dev/null
  55 +++ b/drivers/mtd/nand/bmt.c
  56 @@ -0,0 +1,750 @@
  57 +#include "bmt.h"
  58 +
  59 +typedef struct
  60 +{
  61 +    char signature[3];
  62 +    u8 version;
  63 +    u8 bad_count;               // bad block count in pool
  64 +    u8 mapped_count;            // mapped block count in pool
  65 +    u8 checksum;
  66 +    u8 reseverd[13];
  67 +} phys_bmt_header;
  68 +
  69 +typedef struct
  70 +{
  71 +    phys_bmt_header header;
  72 +    bmt_entry table[MAX_BMT_SIZE];
  73 +} phys_bmt_struct;
  74 +
  75 +typedef struct
  76 +{
  77 +    char signature[3];
  78 +} bmt_oob_data;
  79 +
  80 +static char MAIN_SIGNATURE[] = "BMT";
  81 +static char OOB_SIGNATURE[] = "bmt";
  82 +#define SIGNATURE_SIZE      (3)
  83 +
  84 +#define MAX_DAT_SIZE        0x1000
  85 +#define MAX_OOB_SIZE        0x80
  86 +
  87 +static struct mtd_info *mtd_bmt;
  88 +static struct nand_chip *nand_chip_bmt;
  89 +#define BLOCK_SIZE_BMT          (1 << nand_chip_bmt->phys_erase_shift)
  90 +#define PAGE_SIZE_BMT           (1 << nand_chip_bmt->page_shift)
  91 +
  92 +#define OFFSET(block)       ((block) * BLOCK_SIZE_BMT)
  93 +#define PAGE_ADDR(block)    ((block) * BLOCK_SIZE_BMT / PAGE_SIZE_BMT)
  94 +
  95 +/*********************************************************************
  96 +* Flash is splited into 2 parts, system part is for normal system    *
  97 +* system usage, size is system_block_count, another is replace pool  *
  98 +*    +-------------------------------------------------+             *
  99 +*    |     system_block_count     |   bmt_block_count  |             *
 100 +*    +-------------------------------------------------+             *
 101 +*********************************************************************/
 102 +static u32 total_block_count;   // block number in flash
 103 +static u32 system_block_count;
 104 +static int bmt_block_count;     // bmt table size
 105 +// static int bmt_count;               // block used in bmt
 106 +static int page_per_block;      // page per count
 107 +
 108 +static u32 bmt_block_index;     // bmt block index
 109 +static bmt_struct bmt;          // dynamic created global bmt table
 110 +
 111 +static u8 dat_buf[MAX_DAT_SIZE];
 112 +static u8 oob_buf[MAX_OOB_SIZE];
 113 +static bool pool_erased;
 114 +
 115 +/***************************************************************
 116 +*
 117 +* Interface adaptor for preloader/uboot/kernel
 118 +*    These interfaces operate on physical address, read/write
 119 +*       physical data.
 120 +*
 121 +***************************************************************/
 122 +int nand_read_page_bmt(u32 page, u8 * dat, u8 * oob)
 123 +{
 124 +    return mtk_nand_exec_read_page(mtd_bmt, page, PAGE_SIZE_BMT, dat, oob);
 125 +}
 126 +
 127 +bool nand_block_bad_bmt(u32 offset)
 128 +{
 129 +    return mtk_nand_block_bad_hw(mtd_bmt, offset);
 130 +}
 131 +
 132 +bool nand_erase_bmt(u32 offset)
 133 +{
 134 +    int status;
 135 +    if (offset < 0x20000)
 136 +    {
 137 +        MSG(INIT, "erase offset: 0x%x\n", offset);
 138 +    }
 139 +
 140 +    status = mtk_nand_erase_hw(mtd_bmt, offset / PAGE_SIZE_BMT); // as nand_chip structure doesn't have a erase function defined
 141 +    if (status & NAND_STATUS_FAIL)
 142 +        return false;
 143 +    else
 144 +        return true;
 145 +}
 146 +
 147 +int mark_block_bad_bmt(u32 offset)
 148 +{
 149 +    return mtk_nand_block_markbad_hw(mtd_bmt, offset);   //mark_block_bad_hw(offset);
 150 +}
 151 +
 152 +bool nand_write_page_bmt(u32 page, u8 * dat, u8 * oob)
 153 +{
 154 +    if (mtk_nand_exec_write_page(mtd_bmt, page, PAGE_SIZE_BMT, dat, oob))
 155 +        return false;
 156 +    else
 157 +        return true;
 158 +}
 159 +
 160 +/***************************************************************
 161 +*                                                              *
 162 +* static internal function                                     *
 163 +*                                                              *
 164 +***************************************************************/
 165 +static void dump_bmt_info(bmt_struct * bmt)
 166 +{
 167 +    int i;
 168 +
 169 +    MSG(INIT, "BMT v%d. total %d mapping:\n", bmt->version, bmt->mapped_count);
 170 +    for (i = 0; i < bmt->mapped_count; i++)
 171 +    {
 172 +        MSG(INIT, "\t0x%x -> 0x%x\n", bmt->table[i].bad_index, bmt->table[i].mapped_index);
 173 +    }
 174 +}
 175 +
 176 +static bool match_bmt_signature(u8 * dat, u8 * oob)
 177 +{
 178 +
 179 +    if (memcmp(dat + MAIN_SIGNATURE_OFFSET, MAIN_SIGNATURE, SIGNATURE_SIZE))
 180 +    {
 181 +        return false;
 182 +    }
 183 +
 184 +    if (memcmp(oob + OOB_SIGNATURE_OFFSET, OOB_SIGNATURE, SIGNATURE_SIZE))
 185 +    {
 186 +        MSG(INIT, "main signature match, oob signature doesn't match, but ignore\n");
 187 +    }
 188 +    return true;
 189 +}
 190 +
 191 +static u8 cal_bmt_checksum(phys_bmt_struct * phys_table, int bmt_size)
 192 +{
 193 +    int i;
 194 +    u8 checksum = 0;
 195 +    u8 *dat = (u8 *) phys_table;
 196 +
 197 +    checksum += phys_table->header.version;
 198 +    checksum += phys_table->header.mapped_count;
 199 +
 200 +    dat += sizeof(phys_bmt_header);
 201 +    for (i = 0; i < bmt_size * sizeof(bmt_entry); i++)
 202 +    {
 203 +        checksum += dat[i];
 204 +    }
 205 +
 206 +    return checksum;
 207 +}
 208 +
 209 +
 210 +static int is_block_mapped(int index)
 211 +{
 212 +    int i;
 213 +    for (i = 0; i < bmt.mapped_count; i++)
 214 +    {
 215 +        if (index == bmt.table[i].mapped_index)
 216 +            return i;
 217 +    }
 218 +    return -1;
 219 +}
 220 +
 221 +static bool is_page_used(u8 * dat, u8 * oob)
 222 +{
 223 +    return ((oob[OOB_INDEX_OFFSET] != 0xFF) || (oob[OOB_INDEX_OFFSET + 1] != 0xFF));
 224 +}
 225 +
 226 +static bool valid_bmt_data(phys_bmt_struct * phys_table)
 227 +{
 228 +    int i;
 229 +    u8 checksum = cal_bmt_checksum(phys_table, bmt_block_count);
 230 +
 231 +    // checksum correct?
 232 +    if (phys_table->header.checksum != checksum)
 233 +    {
 234 +        MSG(INIT, "BMT Data checksum error: %x %x\n", phys_table->header.checksum, checksum);
 235 +        return false;
 236 +    }
 237 +
 238 +    MSG(INIT, "BMT Checksum is: 0x%x\n", phys_table->header.checksum);
 239 +
 240 +    // block index correct?
 241 +    for (i = 0; i < phys_table->header.mapped_count; i++)
 242 +    {
 243 +        if (phys_table->table[i].bad_index >= total_block_count || phys_table->table[i].mapped_index >= total_block_count || phys_table->table[i].mapped_index < system_block_count)
 244 +        {
 245 +            MSG(INIT, "index error: bad_index: %d, mapped_index: %d\n", phys_table->table[i].bad_index, phys_table->table[i].mapped_index);
 246 +            return false;
 247 +        }
 248 +    }
 249 +
 250 +    // pass check, valid bmt.
 251 +    MSG(INIT, "Valid BMT, version v%d\n", phys_table->header.version);
 252 +    return true;
 253 +}
 254 +
 255 +static void fill_nand_bmt_buffer(bmt_struct * bmt, u8 * dat, u8 * oob)
 256 +{
 257 +    phys_bmt_struct phys_bmt;
 258 +
 259 +    dump_bmt_info(bmt);
 260 +
 261 +    // fill phys_bmt_struct structure with bmt_struct
 262 +    memset(&phys_bmt, 0xFF, sizeof(phys_bmt));
 263 +
 264 +    memcpy(phys_bmt.header.signature, MAIN_SIGNATURE, SIGNATURE_SIZE);
 265 +    phys_bmt.header.version = BMT_VERSION;
 266 +    // phys_bmt.header.bad_count = bmt->bad_count;
 267 +    phys_bmt.header.mapped_count = bmt->mapped_count;
 268 +    memcpy(phys_bmt.table, bmt->table, sizeof(bmt_entry) * bmt_block_count);
 269 +
 270 +    phys_bmt.header.checksum = cal_bmt_checksum(&phys_bmt, bmt_block_count);
 271 +
 272 +    memcpy(dat + MAIN_SIGNATURE_OFFSET, &phys_bmt, sizeof(phys_bmt));
 273 +    memcpy(oob + OOB_SIGNATURE_OFFSET, OOB_SIGNATURE, SIGNATURE_SIZE);
 274 +}
 275 +
 276 +// return valid index if found BMT, else return 0
 277 +static int load_bmt_data(int start, int pool_size)
 278 +{
 279 +    int bmt_index = start + pool_size - 1;  // find from the end
 280 +    phys_bmt_struct phys_table;
 281 +    int i;
 282 +
 283 +    MSG(INIT, "[%s]: begin to search BMT from block 0x%x\n", __FUNCTION__, bmt_index);
 284 +
 285 +    for (bmt_index = start + pool_size - 1; bmt_index >= start; bmt_index--)
 286 +    {
 287 +        if (nand_block_bad_bmt(OFFSET(bmt_index)))
 288 +        {
 289 +            MSG(INIT, "Skip bad block: %d\n", bmt_index);
 290 +            continue;
 291 +        }
 292 +
 293 +        if (!nand_read_page_bmt(PAGE_ADDR(bmt_index), dat_buf, oob_buf))
 294 +        {
 295 +            MSG(INIT, "Error found when read block %d\n", bmt_index);
 296 +            continue;
 297 +        }
 298 +
 299 +        if (!match_bmt_signature(dat_buf, oob_buf))
 300 +        {
 301 +            continue;
 302 +        }
 303 +
 304 +        MSG(INIT, "Match bmt signature @ block: 0x%x\n", bmt_index);
 305 +
 306 +        memcpy(&phys_table, dat_buf + MAIN_SIGNATURE_OFFSET, sizeof(phys_table));
 307 +
 308 +        if (!valid_bmt_data(&phys_table))
 309 +        {
 310 +            MSG(INIT, "BMT data is not correct %d\n", bmt_index);
 311 +            continue;
 312 +        } else
 313 +        {
 314 +            bmt.mapped_count = phys_table.header.mapped_count;
 315 +            bmt.version = phys_table.header.version;
 316 +            // bmt.bad_count = phys_table.header.bad_count;
 317 +            memcpy(bmt.table, phys_table.table, bmt.mapped_count * sizeof(bmt_entry));
 318 +
 319 +            MSG(INIT, "bmt found at block: %d, mapped block: %d\n", bmt_index, bmt.mapped_count);
 320 +
 321 +            for (i = 0; i < bmt.mapped_count; i++)
 322 +            {
 323 +                if (!nand_block_bad_bmt(OFFSET(bmt.table[i].bad_index)))
 324 +                {
 325 +                    MSG(INIT, "block 0x%x is not mark bad, should be power lost last time\n", bmt.table[i].bad_index);
 326 +                    mark_block_bad_bmt(OFFSET(bmt.table[i].bad_index));
 327 +                }
 328 +            }
 329 +
 330 +            return bmt_index;
 331 +        }
 332 +    }
 333 +
 334 +    MSG(INIT, "bmt block not found!\n");
 335 +    return 0;
 336 +}
 337 +
 338 +/*************************************************************************
 339 +* Find an available block and erase.                                     *
 340 +* start_from_end: if true, find available block from end of flash.       *
 341 +*                 else, find from the beginning of the pool              *
 342 +* need_erase: if true, all unmapped blocks in the pool will be erased    *
 343 +*************************************************************************/
 344 +static int find_available_block(bool start_from_end)
 345 +{
 346 +    int i;                      // , j;
 347 +    int block = system_block_count;
 348 +    int direction;
 349 +    // int avail_index = 0;
 350 +    MSG(INIT, "Try to find_available_block, pool_erase: %d\n", pool_erased);
 351 +
 352 +    // erase all un-mapped blocks in pool when finding avaliable block
 353 +    if (!pool_erased)
 354 +    {
 355 +        MSG(INIT, "Erase all un-mapped blocks in pool\n");
 356 +        for (i = 0; i < bmt_block_count; i++)
 357 +        {
 358 +            if (block == bmt_block_index)
 359 +            {
 360 +                MSG(INIT, "Skip bmt block 0x%x\n", block);
 361 +                continue;
 362 +            }
 363 +
 364 +            if (nand_block_bad_bmt(OFFSET(block + i)))
 365 +            {
 366 +                MSG(INIT, "Skip bad block 0x%x\n", block + i);
 367 +                continue;
 368 +            }
 369 +//if(block==4095)
 370 +//{
 371 +//  continue;
 372 +//}
 373 +
 374 +            if (is_block_mapped(block + i) >= 0)
 375 +            {
 376 +                MSG(INIT, "Skip mapped block 0x%x\n", block + i);
 377 +                continue;
 378 +            }
 379 +
 380 +            if (!nand_erase_bmt(OFFSET(block + i)))
 381 +            {
 382 +                MSG(INIT, "Erase block 0x%x failed\n", block + i);
 383 +                mark_block_bad_bmt(OFFSET(block + i));
 384 +            }
 385 +        }
 386 +
 387 +        pool_erased = 1;
 388 +    }
 389 +
 390 +    if (start_from_end)
 391 +    {
 392 +        block = total_block_count - 1;
 393 +        direction = -1;
 394 +    } else
 395 +    {
 396 +        block = system_block_count;
 397 +        direction = 1;
 398 +    }
 399 +
 400 +    for (i = 0; i < bmt_block_count; i++, block += direction)
 401 +    {
 402 +        if (block == bmt_block_index)
 403 +        {
 404 +            MSG(INIT, "Skip bmt block 0x%x\n", block);
 405 +            continue;
 406 +        }
 407 +
 408 +        if (nand_block_bad_bmt(OFFSET(block)))
 409 +        {
 410 +            MSG(INIT, "Skip bad block 0x%x\n", block);
 411 +            continue;
 412 +        }
 413 +
 414 +        if (is_block_mapped(block) >= 0)
 415 +        {
 416 +            MSG(INIT, "Skip mapped block 0x%x\n", block);
 417 +            continue;
 418 +        }
 419 +
 420 +        MSG(INIT, "Find block 0x%x available\n", block);
 421 +        return block;
 422 +    }
 423 +
 424 +    return 0;
 425 +}
 426 +
 427 +static unsigned short get_bad_index_from_oob(u8 * oob_buf)
 428 +{
 429 +    unsigned short index;
 430 +    memcpy(&index, oob_buf + OOB_INDEX_OFFSET, OOB_INDEX_SIZE);
 431 +
 432 +    return index;
 433 +}
 434 +
 435 +void set_bad_index_to_oob(u8 * oob, u16 index)
 436 +{
 437 +    memcpy(oob + OOB_INDEX_OFFSET, &index, sizeof(index));
 438 +}
 439 +
 440 +static int migrate_from_bad(int offset, u8 * write_dat, u8 * write_oob)
 441 +{
 442 +    int page;
 443 +    int error_block = offset / BLOCK_SIZE_BMT;
 444 +    int error_page = (offset / PAGE_SIZE_BMT) % page_per_block;
 445 +    int to_index;
 446 +
 447 +    memcpy(oob_buf, write_oob, MAX_OOB_SIZE);
 448 +
 449 +    to_index = find_available_block(false);
 450 +
 451 +    if (!to_index)
 452 +    {
 453 +        MSG(INIT, "Cannot find an available block for BMT\n");
 454 +        return 0;
 455 +    }
 456 +
 457 +    {                           // migrate error page first
 458 +        MSG(INIT, "Write error page: 0x%x\n", error_page);
 459 +        if (!write_dat)
 460 +        {
 461 +            nand_read_page_bmt(PAGE_ADDR(error_block) + error_page, dat_buf, NULL);
 462 +            write_dat = dat_buf;
 463 +        }
 464 +        // memcpy(oob_buf, write_oob, MAX_OOB_SIZE);
 465 +
 466 +        if (error_block < system_block_count)
 467 +            set_bad_index_to_oob(oob_buf, error_block); // if error_block is already a mapped block, original mapping index is in OOB.
 468 +
 469 +        if (!nand_write_page_bmt(PAGE_ADDR(to_index) + error_page, write_dat, oob_buf))
 470 +        {
 471 +            MSG(INIT, "Write to page 0x%x fail\n", PAGE_ADDR(to_index) + error_page);
 472 +            mark_block_bad_bmt(to_index);
 473 +            return migrate_from_bad(offset, write_dat, write_oob);
 474 +        }
 475 +    }
 476 +
 477 +    for (page = 0; page < page_per_block; page++)
 478 +    {
 479 +        if (page != error_page)
 480 +        {
 481 +            nand_read_page_bmt(PAGE_ADDR(error_block) + page, dat_buf, oob_buf);
 482 +            if (is_page_used(dat_buf, oob_buf))
 483 +            {
 484 +                if (error_block < system_block_count)
 485 +                {
 486 +                    set_bad_index_to_oob(oob_buf, error_block);
 487 +                }
 488 +                MSG(INIT, "\tmigrate page 0x%x to page 0x%x\n", PAGE_ADDR(error_block) + page, PAGE_ADDR(to_index) + page);
 489 +                if (!nand_write_page_bmt(PAGE_ADDR(to_index) + page, dat_buf, oob_buf))
 490 +                {
 491 +                    MSG(INIT, "Write to page 0x%x fail\n", PAGE_ADDR(to_index) + page);
 492 +                    mark_block_bad_bmt(to_index);
 493 +                    return migrate_from_bad(offset, write_dat, write_oob);
 494 +                }
 495 +            }
 496 +        }
 497 +    }
 498 +
 499 +    MSG(INIT, "Migrate from 0x%x to 0x%x done!\n", error_block, to_index);
 500 +
 501 +    return to_index;
 502 +}
 503 +
 504 +static bool write_bmt_to_flash(u8 * dat, u8 * oob)
 505 +{
 506 +    bool need_erase = true;
 507 +    MSG(INIT, "Try to write BMT\n");
 508 +
 509 +    if (bmt_block_index == 0)
 510 +    {
 511 +        // if we don't have index, we don't need to erase found block as it has been erased in find_available_block()
 512 +        need_erase = false;
 513 +        if (!(bmt_block_index = find_available_block(true)))
 514 +        {
 515 +            MSG(INIT, "Cannot find an available block for BMT\n");
 516 +            return false;
 517 +        }
 518 +    }
 519 +
 520 +    MSG(INIT, "Find BMT block: 0x%x\n", bmt_block_index);
 521 +
 522 +    // write bmt to flash
 523 +    if (need_erase)
 524 +    {
 525 +        if (!nand_erase_bmt(OFFSET(bmt_block_index)))
 526 +        {
 527 +            MSG(INIT, "BMT block erase fail, mark bad: 0x%x\n", bmt_block_index);
 528 +            mark_block_bad_bmt(OFFSET(bmt_block_index));
 529 +            // bmt.bad_count++;
 530 +
 531 +            bmt_block_index = 0;
 532 +            return write_bmt_to_flash(dat, oob);    // recursive call
 533 +        }
 534 +    }
 535 +
 536 +    if (!nand_write_page_bmt(PAGE_ADDR(bmt_block_index), dat, oob))
 537 +    {
 538 +        MSG(INIT, "Write BMT data fail, need to write again\n");
 539 +        mark_block_bad_bmt(OFFSET(bmt_block_index));
 540 +        // bmt.bad_count++;
 541 +
 542 +        bmt_block_index = 0;
 543 +        return write_bmt_to_flash(dat, oob);    // recursive call
 544 +    }
 545 +
 546 +    MSG(INIT, "Write BMT data to block 0x%x success\n", bmt_block_index);
 547 +    return true;
 548 +}
 549 +
 550 +/*******************************************************************
 551 +* Reconstruct bmt, called when found bmt info doesn't match bad
 552 +* block info in flash.
 553 +*
 554 +* Return NULL for failure
 555 +*******************************************************************/
 556 +bmt_struct *reconstruct_bmt(bmt_struct * bmt)
 557 +{
 558 +    int i;
 559 +    int index = system_block_count;
 560 +    unsigned short bad_index;
 561 +    int mapped;
 562 +
 563 +    // init everything in BMT struct
 564 +    bmt->version = BMT_VERSION;
 565 +    bmt->bad_count = 0;
 566 +    bmt->mapped_count = 0;
 567 +
 568 +    memset(bmt->table, 0, bmt_block_count * sizeof(bmt_entry));
 569 +
 570 +    for (i = 0; i < bmt_block_count; i++, index++)
 571 +    {
 572 +        if (nand_block_bad_bmt(OFFSET(index)))
 573 +        {
 574 +            MSG(INIT, "Skip bad block: 0x%x\n", index);
 575 +            // bmt->bad_count++;
 576 +            continue;
 577 +        }
 578 +
 579 +        MSG(INIT, "read page: 0x%x\n", PAGE_ADDR(index));
 580 +        nand_read_page_bmt(PAGE_ADDR(index), dat_buf, oob_buf);
 581 +        /* if (mtk_nand_read_page_hw(PAGE_ADDR(index), dat_buf))
 582 +           {
 583 +           MSG(INIT,  "Error when read block %d\n", bmt_block_index);
 584 +           continue;
 585 +           } */
 586 +
 587 +        if ((bad_index = get_bad_index_from_oob(oob_buf)) >= system_block_count)
 588 +        {
 589 +            MSG(INIT, "get bad index: 0x%x\n", bad_index);
 590 +            if (bad_index != 0xFFFF)
 591 +                MSG(INIT, "Invalid bad index found in block 0x%x, bad index 0x%x\n", index, bad_index);
 592 +            continue;
 593 +        }
 594 +
 595 +        MSG(INIT, "Block 0x%x is mapped to bad block: 0x%x\n", index, bad_index);
 596 +
 597 +        if (!nand_block_bad_bmt(OFFSET(bad_index)))
 598 +        {
 599 +            MSG(INIT, "\tbut block 0x%x is not marked as bad, invalid mapping\n", bad_index);
 600 +            continue;           // no need to erase here, it will be erased later when trying to write BMT
 601 +        }
 602 +
 603 +        if ((mapped = is_block_mapped(bad_index)) >= 0)
 604 +        {
 605 +            MSG(INIT, "bad block 0x%x is mapped to 0x%x, should be caused by power lost, replace with one\n", bmt->table[mapped].bad_index, bmt->table[mapped].mapped_index);
 606 +            bmt->table[mapped].mapped_index = index;    // use new one instead.
 607 +        } else
 608 +        {
 609 +            // add mapping to BMT
 610 +            bmt->table[bmt->mapped_count].bad_index = bad_index;
 611 +            bmt->table[bmt->mapped_count].mapped_index = index;
 612 +            bmt->mapped_count++;
 613 +        }
 614 +
 615 +        MSG(INIT, "Add mapping: 0x%x -> 0x%x to BMT\n", bad_index, index);
 616 +
 617 +    }
 618 +
 619 +    MSG(INIT, "Scan replace pool done, mapped block: %d\n", bmt->mapped_count);
 620 +    // dump_bmt_info(bmt);
 621 +
 622 +    // fill NAND BMT buffer
 623 +    memset(oob_buf, 0xFF, sizeof(oob_buf));
 624 +    fill_nand_bmt_buffer(bmt, dat_buf, oob_buf);
 625 +
 626 +    // write BMT back
 627 +    if (!write_bmt_to_flash(dat_buf, oob_buf))
 628 +    {
 629 +        MSG(INIT, "TRAGEDY: cannot find a place to write BMT!!!!\n");
 630 +    }
 631 +
 632 +    return bmt;
 633 +}
 634 +
 635 +/*******************************************************************
 636 +* [BMT Interface]
 637 +*
 638 +* Description:
 639 +*   Init bmt from nand. Reconstruct if not found or data error
 640 +*
 641 +* Parameter:
 642 +*   size: size of bmt and replace pool
 643 +*
 644 +* Return:
 645 +*   NULL for failure, and a bmt struct for success
 646 +*******************************************************************/
 647 +bmt_struct *init_bmt(struct nand_chip * chip, int size)
 648 +{
 649 +    struct mtk_nand_host *host;
 650 +
 651 +    if (size > 0 && size < MAX_BMT_SIZE)
 652 +    {
 653 +        MSG(INIT, "Init bmt table, size: %d\n", size);
 654 +        bmt_block_count = size;
 655 +    } else
 656 +    {
 657 +        MSG(INIT, "Invalid bmt table size: %d\n", size);
 658 +        return NULL;
 659 +    }
 660 +    nand_chip_bmt = chip;
 661 +    system_block_count = chip->chipsize >> chip->phys_erase_shift;
 662 +    total_block_count = bmt_block_count + system_block_count;
 663 +    page_per_block = BLOCK_SIZE_BMT / PAGE_SIZE_BMT;
 664 +    host = (struct mtk_nand_host *)chip->priv;
 665 +    mtd_bmt = host->mtd;
 666 +
 667 +    MSG(INIT, "mtd_bmt: %p, nand_chip_bmt: %p\n", mtd_bmt, nand_chip_bmt);
 668 +    MSG(INIT, "bmt count: %d, system count: %d\n", bmt_block_count, system_block_count);
 669 +
 670 +    // set this flag, and unmapped block in pool will be erased.
 671 +    pool_erased = 0;
 672 +    memset(bmt.table, 0, size * sizeof(bmt_entry));
 673 +    if ((bmt_block_index = load_bmt_data(system_block_count, size)))
 674 +    {
 675 +        MSG(INIT, "Load bmt data success @ block 0x%x\n", bmt_block_index);
 676 +        dump_bmt_info(&bmt);
 677 +        return &bmt;
 678 +    } else
 679 +    {
 680 +        MSG(INIT, "Load bmt data fail, need re-construct!\n");
 681 +#ifndef __UBOOT_NAND__            // BMT is not re-constructed in UBOOT.
 682 +        if (reconstruct_bmt(&bmt))
 683 +            return &bmt;
 684 +        else
 685 +#endif
 686 +            return NULL;
 687 +    }
 688 +}
 689 +
 690 +/*******************************************************************
 691 +* [BMT Interface]
 692 +*
 693 +* Description:
 694 +*   Update BMT.
 695 +*
 696 +* Parameter:
 697 +*   offset: update block/page offset.
 698 +*   reason: update reason, see update_reason_t for reason.
 699 +*   dat/oob: data and oob buffer for write fail.
 700 +*
 701 +* Return:
 702 +*   Return true for success, and false for failure.
 703 +*******************************************************************/
 704 +bool update_bmt(u32 offset, update_reason_t reason, u8 * dat, u8 * oob)
 705 +{
 706 +    int map_index;
 707 +    int orig_bad_block = -1;
 708 +    // int bmt_update_index;
 709 +    int i;
 710 +    int bad_index = offset / BLOCK_SIZE_BMT;
 711 +
 712 +#ifndef MTK_NAND_BMT
 713 +       return false;
 714 +#endif
 715 +    if (reason == UPDATE_WRITE_FAIL)
 716 +    {
 717 +        MSG(INIT, "Write fail, need to migrate\n");
 718 +        if (!(map_index = migrate_from_bad(offset, dat, oob)))
 719 +        {
 720 +            MSG(INIT, "migrate fail\n");
 721 +            return false;
 722 +        }
 723 +    } else
 724 +    {
 725 +        if (!(map_index = find_available_block(false)))
 726 +        {
 727 +            MSG(INIT, "Cannot find block in pool\n");
 728 +            return false;
 729 +        }
 730 +    }
 731 +
 732 +    // now let's update BMT
 733 +    if (bad_index >= system_block_count)    // mapped block become bad, find original bad block
 734 +    {
 735 +        for (i = 0; i < bmt_block_count; i++)
 736 +        {
 737 +            if (bmt.table[i].mapped_index == bad_index)
 738 +            {
 739 +                orig_bad_block = bmt.table[i].bad_index;
 740 +                break;
 741 +            }
 742 +        }
 743 +        // bmt.bad_count++;
 744 +        MSG(INIT, "Mapped block becomes bad, orig bad block is 0x%x\n", orig_bad_block);
 745 +
 746 +        bmt.table[i].mapped_index = map_index;
 747 +    } else
 748 +    {
 749 +        bmt.table[bmt.mapped_count].mapped_index = map_index;
 750 +        bmt.table[bmt.mapped_count].bad_index = bad_index;
 751 +        bmt.mapped_count++;
 752 +    }
 753 +
 754 +    memset(oob_buf, 0xFF, sizeof(oob_buf));
 755 +    fill_nand_bmt_buffer(&bmt, dat_buf, oob_buf);
 756 +    if (!write_bmt_to_flash(dat_buf, oob_buf))
 757 +        return false;
 758 +
 759 +    mark_block_bad_bmt(offset);
 760 +
 761 +    return true;
 762 +}
 763 +
 764 +/*******************************************************************
 765 +* [BMT Interface]
 766 +*
 767 +* Description:
 768 +*   Given an block index, return mapped index if it's mapped, else
 769 +*   return given index.
 770 +*
 771 +* Parameter:
 772 +*   index: given an block index. This value cannot exceed
 773 +*   system_block_count.
 774 +*
 775 +* Return NULL for failure
 776 +*******************************************************************/
 777 +u16 get_mapping_block_index(int index)
 778 +{
 779 +    int i;
 780 +#ifndef MTK_NAND_BMT
 781 +       return index;
 782 +#endif
 783 +    if (index > system_block_count)
 784 +    {
 785 +        return index;
 786 +    }
 787 +
 788 +    for (i = 0; i < bmt.mapped_count; i++)
 789 +    {
 790 +        if (bmt.table[i].bad_index == index)
 791 +        {
 792 +            return bmt.table[i].mapped_index;
 793 +        }
 794 +    }
 795 +
 796 +    return index;
 797 +}
 798 +#ifdef __KERNEL_NAND__
 799 +EXPORT_SYMBOL_GPL(init_bmt);
 800 +EXPORT_SYMBOL_GPL(update_bmt);
 801 +EXPORT_SYMBOL_GPL(get_mapping_block_index);
 802 +
 803 +MODULE_LICENSE("GPL");
 804 +MODULE_AUTHOR("MediaTek");
 805 +MODULE_DESCRIPTION("Bad Block mapping management for MediaTek NAND Flash Driver");
 806 +#endif
 807 --- /dev/null
 808 +++ b/drivers/mtd/nand/bmt.h
 809 @@ -0,0 +1,80 @@
 810 +#ifndef __BMT_H__
 811 +#define __BMT_H__
 812 +
 813 +#include "nand_def.h"
 814 +
 815 +#if defined(__PRELOADER_NAND__)
 816 +
 817 +#include "nand.h"
 818 +
 819 +#elif defined(__UBOOT_NAND__)
 820 +
 821 +#include <linux/mtd/nand.h>
 822 +#include "mtk_nand2.h"
 823 +
 824 +#elif defined(__KERNEL_NAND__)
 825 +
 826 +#include <linux/mtd/mtd.h>
 827 +#include <linux/mtd/nand.h>
 828 +#include <linux/module.h>
 829 +#include "mtk_nand2.h"
 830 +
 831 +#endif
 832 +
 833 +
 834 +#define MAX_BMT_SIZE        (0x80)
 835 +#define BMT_VERSION         (1) // initial version
 836 +
 837 +#define MAIN_SIGNATURE_OFFSET   (0)
 838 +#define OOB_SIGNATURE_OFFSET    (1)
 839 +#define OOB_INDEX_OFFSET        (29)
 840 +#define OOB_INDEX_SIZE          (2)
 841 +#define FAKE_INDEX              (0xAAAA)
 842 +
 843 +typedef struct _bmt_entry_
 844 +{
 845 +    u16 bad_index;              // bad block index
 846 +    u16 mapped_index;           // mapping block index in the replace pool
 847 +} bmt_entry;
 848 +
 849 +typedef enum
 850 +{
 851 +    UPDATE_ERASE_FAIL,
 852 +    UPDATE_WRITE_FAIL,
 853 +    UPDATE_UNMAPPED_BLOCK,
 854 +    UPDATE_REASON_COUNT,
 855 +} update_reason_t;
 856 +
 857 +typedef struct
 858 +{
 859 +    bmt_entry table[MAX_BMT_SIZE];
 860 +    u8 version;
 861 +    u8 mapped_count;            // mapped block count in pool
 862 +    u8 bad_count;               // bad block count in pool. Not used in V1
 863 +} bmt_struct;
 864 +
 865 +/***************************************************************
 866 +*                                                              *
 867 +* Interface BMT need to use                                    *
 868 +*                                                              *
 869 +***************************************************************/
 870 +extern bool mtk_nand_exec_read_page(struct mtd_info *mtd, u32 row, u32 page_size, u8 * dat, u8 * oob);
 871 +extern int mtk_nand_block_bad_hw(struct mtd_info *mtd, loff_t ofs);
 872 +extern int mtk_nand_erase_hw(struct mtd_info *mtd, int page);
 873 +extern int mtk_nand_block_markbad_hw(struct mtd_info *mtd, loff_t ofs);
 874 +extern int mtk_nand_exec_write_page(struct mtd_info *mtd, u32 row, u32 page_size, u8 * dat, u8 * oob);
 875 +
 876 +
 877 +/***************************************************************
 878 +*                                                              *
 879 +* Different function interface for preloader/uboot/kernel      *
 880 +*                                                              *
 881 +***************************************************************/
 882 +void set_bad_index_to_oob(u8 * oob, u16 index);
 883 +
 884 +
 885 +bmt_struct *init_bmt(struct nand_chip *nand, int size);
 886 +bool update_bmt(u32 offset, update_reason_t reason, u8 * dat, u8 * oob);
 887 +unsigned short get_mapping_block_index(int index);
 888 +
 889 +#endif                          // #ifndef __BMT_H__
 890 --- /dev/null
 891 +++ b/drivers/mtd/nand/dev-nand.c
 892 @@ -0,0 +1,63 @@
 893 +#include <linux/init.h>
 894 +#include <linux/kernel.h>
 895 +#include <linux/platform_device.h>
 896 +
 897 +#include "mt6575_typedefs.h"
 898 +
 899 +#define RALINK_NAND_CTRL_BASE               0xBE003000
 900 +#define NFI_base    RALINK_NAND_CTRL_BASE
 901 +#define RALINK_NANDECC_CTRL_BASE    0xBE003800
 902 +#define NFIECC_base RALINK_NANDECC_CTRL_BASE
 903 +#define MT7621_NFI_IRQ_ID              SURFBOARDINT_NAND
 904 +#define MT7621_NFIECC_IRQ_ID   SURFBOARDINT_NAND_ECC
 905 +
 906 +#define SURFBOARDINT_NAND 22
 907 +#define SURFBOARDINT_NAND_ECC 23
 908 +
 909 +static struct resource MT7621_resource_nand[] = {
 910 +        {
 911 +                .start          = NFI_base,
 912 +                .end            = NFI_base + 0x1A0,
 913 +                .flags          = IORESOURCE_MEM,
 914 +        },
 915 +        {
 916 +                .start          = NFIECC_base,
 917 +                .end            = NFIECC_base + 0x150,
 918 +                .flags          = IORESOURCE_MEM,
 919 +        },
 920 +        {
 921 +                .start          = MT7621_NFI_IRQ_ID,
 922 +                .flags          = IORESOURCE_IRQ,
 923 +        },
 924 +        {
 925 +                .start          = MT7621_NFIECC_IRQ_ID,
 926 +                .flags          = IORESOURCE_IRQ,
 927 +        },
 928 +};
 929 +
 930 +static struct platform_device MT7621_nand_dev = {
 931 +    .name = "MT7621-NAND",
 932 +    .id   = 0,
 933 +        .num_resources  = ARRAY_SIZE(MT7621_resource_nand),
 934 +        .resource               = MT7621_resource_nand,
 935 +    .dev            = {
 936 +        .platform_data = &mt7621_nand_hw,
 937 +    },
 938 +};
 939 +
 940 +
 941 +int __init mtk_nand_register(void)
 942 +{
 943 +
 944 +       int retval = 0;
 945 +
 946 +       retval = platform_device_register(&MT7621_nand_dev);
 947 +       if (retval != 0) {
 948 +               printk(KERN_ERR "register nand device fail\n");
 949 +               return retval;
 950 +       }
 951 +
 952 +
 953 +       return retval;
 954 +}
 955 +arch_initcall(mtk_nand_register);
 956 --- /dev/null
 957 +++ b/drivers/mtd/nand/mt6575_typedefs.h
 958 @@ -0,0 +1,340 @@
 959 +/* Copyright Statement:
 960 + *
 961 + * This software/firmware and related documentation ("MediaTek Software") are
 962 + * protected under relevant copyright laws. The information contained herein
 963 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
 964 + * Without the prior written permission of MediaTek inc. and/or its licensors,
 965 + * any reproduction, modification, use or disclosure of MediaTek Software,
 966 + * and information contained herein, in whole or in part, shall be strictly prohibited.
 967 + */
 968 +/* MediaTek Inc. (C) 2010. All rights reserved.
 969 + *
 970 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
 971 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
 972 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
 973 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
 974 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
 975 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
 976 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
 977 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
 978 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
 979 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
 980 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
 981 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
 982 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
 983 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
 984 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
 985 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
 986 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
 987 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
 988 + *
 989 + * The following software/firmware and/or related documentation ("MediaTek Software")
 990 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
 991 + * applicable license agreements with MediaTek Inc.
 992 + */
 993 +
 994 +/*****************************************************************************
 995 +*  Copyright Statement:
 996 +*  --------------------
 997 +*  This software is protected by Copyright and the information contained
 998 +*  herein is confidential. The software may not be copied and the information
 999 +*  contained herein may not be used or disclosed except with the written
1000 +*  permission of MediaTek Inc. (C) 2008
1001 +*
1002 +*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
1003 +*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
1004 +*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
1005 +*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
1006 +*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
1007 +*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
1008 +*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
1009 +*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
1010 +*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
1011 +*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
1012 +*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
1013 +*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
1014 +*
1015 +*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
1016 +*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
1017 +*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
1018 +*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
1019 +*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
1020 +*
1021 +*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
1022 +*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
1023 +*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
1024 +*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
1025 +*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
1026 +*
1027 +*****************************************************************************/
1028 +
1029 +#ifndef _MT6575_TYPEDEFS_H
1030 +#define _MT6575_TYPEDEFS_H
1031 +
1032 +#if defined (__KERNEL_NAND__)
1033 +#include <linux/bug.h>
1034 +#else
1035 +#define true           1
1036 +#define false          0
1037 +#define bool           u8
1038 +#endif
1039 +
1040 +// ---------------------------------------------------------------------------
1041 +//  Basic Type Definitions
1042 +// ---------------------------------------------------------------------------
1043 +
1044 +typedef volatile unsigned char  *P_kal_uint8;
1045 +typedef volatile unsigned short *P_kal_uint16;
1046 +typedef volatile unsigned int   *P_kal_uint32;
1047 +
1048 +typedef long            LONG;
1049 +typedef unsigned char   UBYTE;
1050 +typedef short           SHORT;
1051 +
1052 +typedef signed char     kal_int8;
1053 +typedef signed short    kal_int16;
1054 +typedef signed int      kal_int32;
1055 +typedef long long       kal_int64;
1056 +typedef unsigned char   kal_uint8;
1057 +typedef unsigned short  kal_uint16;
1058 +typedef unsigned int    kal_uint32;
1059 +typedef unsigned long long  kal_uint64;
1060 +typedef char            kal_char;
1061 +
1062 +typedef unsigned int            *UINT32P;
1063 +typedef volatile unsigned short *UINT16P;
1064 +typedef volatile unsigned char  *UINT8P;
1065 +typedef unsigned char           *U8P;
1066 +
1067 +typedef volatile unsigned char  *P_U8;
1068 +typedef volatile signed char    *P_S8;
1069 +typedef volatile unsigned short *P_U16;
1070 +typedef volatile signed short   *P_S16;
1071 +typedef volatile unsigned int   *P_U32;
1072 +typedef volatile signed int     *P_S32;
1073 +typedef unsigned long long      *P_U64;
1074 +typedef signed long long        *P_S64;
1075 +
1076 +typedef unsigned char       U8;
1077 +typedef signed char         S8;
1078 +typedef unsigned short      U16;
1079 +typedef signed short        S16;
1080 +typedef unsigned int        U32;
1081 +typedef signed int          S32;
1082 +typedef unsigned long long  U64;
1083 +typedef signed long long    S64;
1084 +//typedef unsigned char       bool;
1085 +
1086 +typedef unsigned char   UINT8;
1087 +typedef unsigned short  UINT16;
1088 +typedef unsigned int    UINT32;
1089 +typedef unsigned short  USHORT;
1090 +typedef signed char     INT8;
1091 +typedef signed short    INT16;
1092 +typedef signed int      INT32;
1093 +typedef unsigned int    DWORD;
1094 +typedef void            VOID;
1095 +typedef unsigned char   BYTE;
1096 +typedef float           FLOAT;
1097 +
1098 +typedef char           *LPCSTR;
1099 +typedef short          *LPWSTR;
1100 +
1101 +
1102 +// ---------------------------------------------------------------------------
1103 +//  Constants
1104 +// ---------------------------------------------------------------------------
1105 +
1106 +#define IMPORT  EXTERN
1107 +#ifndef __cplusplus
1108 +  #define EXTERN  extern
1109 +#else
1110 +  #define EXTERN  extern "C"
1111 +#endif
1112 +#define LOCAL     static
1113 +#define GLOBAL
1114 +#define EXPORT    GLOBAL
1115 +
1116 +#define EQ        ==
1117 +#define NEQ       !=
1118 +#define AND       &&
1119 +#define OR        ||
1120 +#define XOR(A,B)  ((!(A) AND (B)) OR ((A) AND !(B)))
1121 +
1122 +#ifndef FALSE
1123 +  #define FALSE (0)
1124 +#endif
1125 +
1126 +#ifndef TRUE
1127 +  #define TRUE  (1)
1128 +#endif
1129 +
1130 +#ifndef NULL
1131 +  #define NULL  (0)
1132 +#endif
1133 +
1134 +//enum boolean {false, true};
1135 +enum {RX, TX, NONE};
1136 +
1137 +#ifndef BOOL
1138 +typedef unsigned char  BOOL;
1139 +#endif
1140 +
1141 +typedef enum {
1142 +   KAL_FALSE = 0,
1143 +   KAL_TRUE  = 1,
1144 +} kal_bool;
1145 +
1146 +
1147 +// ---------------------------------------------------------------------------
1148 +//  Type Casting
1149 +// ---------------------------------------------------------------------------
1150 +
1151 +#define AS_INT32(x)     (*(INT32 *)((void*)x))
1152 +#define AS_INT16(x)     (*(INT16 *)((void*)x))
1153 +#define AS_INT8(x)      (*(INT8  *)((void*)x))
1154 +
1155 +#define AS_UINT32(x)    (*(UINT32 *)((void*)x))
1156 +#define AS_UINT16(x)    (*(UINT16 *)((void*)x))
1157 +#define AS_UINT8(x)     (*(UINT8  *)((void*)x))
1158 +
1159 +
1160 +// ---------------------------------------------------------------------------
1161 +//  Register Manipulations
1162 +// ---------------------------------------------------------------------------
1163 +
1164 +#define READ_REGISTER_UINT32(reg) \
1165 +    (*(volatile UINT32 * const)(reg))
1166 +
1167 +#define WRITE_REGISTER_UINT32(reg, val) \
1168 +    (*(volatile UINT32 * const)(reg)) = (val)
1169 +
1170 +#define READ_REGISTER_UINT16(reg) \
1171 +    (*(volatile UINT16 * const)(reg))
1172 +
1173 +#define WRITE_REGISTER_UINT16(reg, val) \
1174 +    (*(volatile UINT16 * const)(reg)) = (val)
1175 +
1176 +#define READ_REGISTER_UINT8(reg) \
1177 +    (*(volatile UINT8 * const)(reg))
1178 +
1179 +#define WRITE_REGISTER_UINT8(reg, val) \
1180 +    (*(volatile UINT8 * const)(reg)) = (val)
1181 +
1182 +#define INREG8(x)           READ_REGISTER_UINT8((UINT8*)((void*)(x)))
1183 +#define OUTREG8(x, y)       WRITE_REGISTER_UINT8((UINT8*)((void*)(x)), (UINT8)(y))
1184 +#define SETREG8(x, y)       OUTREG8(x, INREG8(x)|(y))
1185 +#define CLRREG8(x, y)       OUTREG8(x, INREG8(x)&~(y))
1186 +#define MASKREG8(x, y, z)   OUTREG8(x, (INREG8(x)&~(y))|(z))
1187 +
1188 +#define INREG16(x)          READ_REGISTER_UINT16((UINT16*)((void*)(x)))
1189 +#define OUTREG16(x, y)      WRITE_REGISTER_UINT16((UINT16*)((void*)(x)),(UINT16)(y))
1190 +#define SETREG16(x, y)      OUTREG16(x, INREG16(x)|(y))
1191 +#define CLRREG16(x, y)      OUTREG16(x, INREG16(x)&~(y))
1192 +#define MASKREG16(x, y, z)  OUTREG16(x, (INREG16(x)&~(y))|(z))
1193 +
1194 +#define INREG32(x)          READ_REGISTER_UINT32((UINT32*)((void*)(x)))
1195 +#define OUTREG32(x, y)      WRITE_REGISTER_UINT32((UINT32*)((void*)(x)), (UINT32)(y))
1196 +#define SETREG32(x, y)      OUTREG32(x, INREG32(x)|(y))
1197 +#define CLRREG32(x, y)      OUTREG32(x, INREG32(x)&~(y))
1198 +#define MASKREG32(x, y, z)  OUTREG32(x, (INREG32(x)&~(y))|(z))
1199 +
1200 +
1201 +#define DRV_Reg8(addr)              INREG8(addr)
1202 +#define DRV_WriteReg8(addr, data)   OUTREG8(addr, data)
1203 +#define DRV_SetReg8(addr, data)     SETREG8(addr, data)
1204 +#define DRV_ClrReg8(addr, data)     CLRREG8(addr, data)
1205 +
1206 +#define DRV_Reg16(addr)             INREG16(addr)
1207 +#define DRV_WriteReg16(addr, data)  OUTREG16(addr, data)
1208 +#define DRV_SetReg16(addr, data)    SETREG16(addr, data)
1209 +#define DRV_ClrReg16(addr, data)    CLRREG16(addr, data)
1210 +
1211 +#define DRV_Reg32(addr)             INREG32(addr)
1212 +#define DRV_WriteReg32(addr, data)  OUTREG32(addr, data)
1213 +#define DRV_SetReg32(addr, data)    SETREG32(addr, data)
1214 +#define DRV_ClrReg32(addr, data)    CLRREG32(addr, data)
1215 +
1216 +// !!! DEPRECATED, WILL BE REMOVED LATER !!!
1217 +#define DRV_Reg(addr)               DRV_Reg16(addr)
1218 +#define DRV_WriteReg(addr, data)    DRV_WriteReg16(addr, data)
1219 +#define DRV_SetReg(addr, data)      DRV_SetReg16(addr, data)
1220 +#define DRV_ClrReg(addr, data)      DRV_ClrReg16(addr, data)
1221 +
1222 +
1223 +// ---------------------------------------------------------------------------
1224 +//  Compiler Time Deduction Macros
1225 +// ---------------------------------------------------------------------------
1226 +
1227 +#define _MASK_OFFSET_1(x, n)  ((x) & 0x1) ? (n) :
1228 +#define _MASK_OFFSET_2(x, n)  _MASK_OFFSET_1((x), (n)) _MASK_OFFSET_1((x) >> 1, (n) + 1)
1229 +#define _MASK_OFFSET_4(x, n)  _MASK_OFFSET_2((x), (n)) _MASK_OFFSET_2((x) >> 2, (n) + 2)
1230 +#define _MASK_OFFSET_8(x, n)  _MASK_OFFSET_4((x), (n)) _MASK_OFFSET_4((x) >> 4, (n) + 4)
1231 +#define _MASK_OFFSET_16(x, n) _MASK_OFFSET_8((x), (n)) _MASK_OFFSET_8((x) >> 8, (n) + 8)
1232 +#define _MASK_OFFSET_32(x, n) _MASK_OFFSET_16((x), (n)) _MASK_OFFSET_16((x) >> 16, (n) + 16)
1233 +
1234 +#define MASK_OFFSET_ERROR (0xFFFFFFFF)
1235 +
1236 +#define MASK_OFFSET(x) (_MASK_OFFSET_32(x, 0) MASK_OFFSET_ERROR)
1237 +
1238 +
1239 +// ---------------------------------------------------------------------------
1240 +//  Assertions
1241 +// ---------------------------------------------------------------------------
1242 +
1243 +#ifndef ASSERT
1244 +    #define ASSERT(expr)        BUG_ON(!(expr))
1245 +#endif
1246 +
1247 +#ifndef NOT_IMPLEMENTED
1248 +    #define NOT_IMPLEMENTED()   BUG_ON(1)
1249 +#endif
1250 +
1251 +#define STATIC_ASSERT(pred)         STATIC_ASSERT_X(pred, __LINE__)
1252 +#define STATIC_ASSERT_X(pred, line) STATIC_ASSERT_XX(pred, line)
1253 +#define STATIC_ASSERT_XX(pred, line) \
1254 +    extern char assertion_failed_at_##line[(pred) ? 1 : -1]
1255 +
1256 +// ---------------------------------------------------------------------------
1257 +//  Resolve Compiler Warnings
1258 +// ---------------------------------------------------------------------------
1259 +
1260 +#define NOT_REFERENCED(x)   { (x) = (x); }
1261 +
1262 +
1263 +// ---------------------------------------------------------------------------
1264 +//  Utilities
1265 +// ---------------------------------------------------------------------------
1266 +
1267 +#define MAXIMUM(A,B)       (((A)>(B))?(A):(B))
1268 +#define MINIMUM(A,B)       (((A)<(B))?(A):(B))
1269 +
1270 +#define ARY_SIZE(x) (sizeof((x)) / sizeof((x[0])))
1271 +#define DVT_DELAYMACRO(u4Num)                                            \
1272 +{                                                                        \
1273 +    UINT32 u4Count = 0 ;                                                 \
1274 +    for (u4Count = 0; u4Count < u4Num; u4Count++ );                      \
1275 +}                                                                        \
1276 +
1277 +#define    A68351B      0
1278 +#define    B68351B      1
1279 +#define    B68351D      2
1280 +#define    B68351E      3
1281 +#define    UNKNOWN_IC_VERSION   0xFF
1282 +
1283 +/* NAND driver */
1284 +struct mtk_nand_host_hw {
1285 +    unsigned int nfi_bus_width;                    /* NFI_BUS_WIDTH */
1286 +       unsigned int nfi_access_timing;         /* NFI_ACCESS_TIMING */
1287 +       unsigned int nfi_cs_num;                        /* NFI_CS_NUM */
1288 +       unsigned int nand_sec_size;                     /* NAND_SECTOR_SIZE */
1289 +       unsigned int nand_sec_shift;            /* NAND_SECTOR_SHIFT */
1290 +       unsigned int nand_ecc_size;
1291 +       unsigned int nand_ecc_bytes;
1292 +       unsigned int nand_ecc_mode;
1293 +};
1294 +extern struct mtk_nand_host_hw mt7621_nand_hw;
1295 +extern unsigned int    CFG_BLOCKSIZE;
1296 +
1297 +#endif  // _MT6575_TYPEDEFS_H
1298 +
1299 --- /dev/null
1300 +++ b/drivers/mtd/nand/mtk_nand2.c
1301 @@ -0,0 +1,2363 @@
1302 +/******************************************************************************
1303 +* mtk_nand2.c - MTK NAND Flash Device Driver
1304 + *
1305 +* Copyright 2009-2012 MediaTek Co.,Ltd.
1306 + *
1307 +* DESCRIPTION:
1308 +*      This file provid the other drivers nand relative functions
1309 + *
1310 +* modification history
1311 +* ----------------------------------------
1312 +* v3.0, 11 Feb 2010, mtk
1313 +* ----------------------------------------
1314 +******************************************************************************/
1315 +#include "nand_def.h"
1316 +#include <linux/slab.h>
1317 +#include <linux/init.h>
1318 +#include <linux/module.h>
1319 +#include <linux/delay.h>
1320 +#include <linux/errno.h>
1321 +#include <linux/sched.h>
1322 +#include <linux/types.h>
1323 +#include <linux/wait.h>
1324 +#include <linux/spinlock.h>
1325 +#include <linux/interrupt.h>
1326 +#include <linux/mtd/mtd.h>
1327 +#include <linux/mtd/nand.h>
1328 +#include <linux/mtd/partitions.h>
1329 +#include <linux/mtd/nand_ecc.h>
1330 +#include <linux/dma-mapping.h>
1331 +#include <linux/jiffies.h>
1332 +#include <linux/platform_device.h>
1333 +#include <linux/proc_fs.h>
1334 +#include <linux/time.h>
1335 +#include <linux/mm.h>
1336 +#include <asm/io.h>
1337 +#include <asm/cacheflush.h>
1338 +#include <asm/uaccess.h>
1339 +#include <linux/miscdevice.h>
1340 +#include "mtk_nand2.h"
1341 +#include "nand_device_list.h"
1342 +
1343 +#include "bmt.h"
1344 +#include "partition.h"
1345 +
1346 +unsigned int CFG_BLOCKSIZE;
1347 +
1348 +static int shift_on_bbt = 0;
1349 +extern void nand_bbt_set(struct mtd_info *mtd, int page, int flag);
1350 +extern int nand_bbt_get(struct mtd_info *mtd, int page);
1351 +int mtk_nand_read_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page);
1352 +
1353 +static const char * const probe_types[] = { "cmdlinepart", "ofpart", NULL };
1354 +
1355 +#define NAND_CMD_STATUS_MULTI  0x71
1356 +
1357 +void show_stack(struct task_struct *tsk, unsigned long *sp);
1358 +extern void mt_irq_set_sens(unsigned int irq, unsigned int sens);
1359 +extern void mt_irq_set_polarity(unsigned int irq,unsigned int polarity);
1360 +
1361 +struct mtk_nand_host   mtk_nand_host;  /* include mtd_info and nand_chip structs */
1362 +struct mtk_nand_host_hw mt7621_nand_hw = {
1363 +    .nfi_bus_width          = 8,
1364 +    .nfi_access_timing      = NFI_DEFAULT_ACCESS_TIMING,
1365 +    .nfi_cs_num             = NFI_CS_NUM,
1366 +    .nand_sec_size          = 512,
1367 +    .nand_sec_shift         = 9,
1368 +    .nand_ecc_size          = 2048,
1369 +    .nand_ecc_bytes         = 32,
1370 +    .nand_ecc_mode          = NAND_ECC_HW,
1371 +};
1372 +
1373 +
1374 +/*******************************************************************************
1375 + * Gloable Varible Definition
1376 + *******************************************************************************/
1377 +
1378 +#define NFI_ISSUE_COMMAND(cmd, col_addr, row_addr, col_num, row_num) \
1379 +   do { \
1380 +      DRV_WriteReg(NFI_CMD_REG16,cmd);\
1381 +      while (DRV_Reg32(NFI_STA_REG32) & STA_CMD_STATE);\
1382 +      DRV_WriteReg32(NFI_COLADDR_REG32, col_addr);\
1383 +      DRV_WriteReg32(NFI_ROWADDR_REG32, row_addr);\
1384 +      DRV_WriteReg(NFI_ADDRNOB_REG16, col_num | (row_num<<ADDR_ROW_NOB_SHIFT));\
1385 +      while (DRV_Reg32(NFI_STA_REG32) & STA_ADDR_STATE);\
1386 +   }while(0);
1387 +
1388 +//-------------------------------------------------------------------------------
1389 +static struct NAND_CMD g_kCMD;
1390 +static u32 g_u4ChipVer;
1391 +bool g_bInitDone;
1392 +static bool g_bcmdstatus;
1393 +static u32 g_value = 0;
1394 +static int g_page_size;
1395 +
1396 +BOOL g_bHwEcc = true;
1397 +
1398 +
1399 +static u8 *local_buffer_16_align;   // 16 byte aligned buffer, for HW issue
1400 +static u8 local_buffer[4096 + 512];
1401 +
1402 +extern void nand_release_device(struct mtd_info *mtd);
1403 +extern int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state);
1404 +
1405 +#if defined(MTK_NAND_BMT)
1406 +static bmt_struct *g_bmt;
1407 +#endif
1408 +struct mtk_nand_host *host;
1409 +extern struct mtd_partition g_pasStatic_Partition[];
1410 +int part_num = NUM_PARTITIONS;
1411 +int manu_id;
1412 +int dev_id;
1413 +
1414 +/* this constant was taken from linux/nand/nand.h v 3.14
1415 + * in later versions it seems it was removed in order to save a bit of space
1416 + */
1417 +#define NAND_MAX_OOBSIZE 774
1418 +static u8 local_oob_buf[NAND_MAX_OOBSIZE];
1419 +
1420 +static u8 nand_badblock_offset = 0;
1421 +
1422 +void nand_enable_clock(void)
1423 +{
1424 +    //enable_clock(MT65XX_PDN_PERI_NFI, "NAND");
1425 +}
1426 +
1427 +void nand_disable_clock(void)
1428 +{
1429 +    //disable_clock(MT65XX_PDN_PERI_NFI, "NAND");
1430 +}
1431 +
1432 +struct nand_ecclayout {
1433 +       __u32 eccbytes;
1434 +       __u32 eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE];
1435 +       __u32 oobavail;
1436 +       struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE];
1437 +};
1438 +
1439 +static struct nand_ecclayout *layout;
1440 +
1441 +static struct nand_ecclayout nand_oob_16 = {
1442 +       .eccbytes = 8,
1443 +       .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
1444 +       .oobfree = {{1, 6}, {0, 0}}
1445 +};
1446 +
1447 +struct nand_ecclayout nand_oob_64 = {
1448 +       .eccbytes = 32,
1449 +       .eccpos = {32, 33, 34, 35, 36, 37, 38, 39,
1450 +               40, 41, 42, 43, 44, 45, 46, 47,
1451 +               48, 49, 50, 51, 52, 53, 54, 55,
1452 +               56, 57, 58, 59, 60, 61, 62, 63},
1453 +       .oobfree = {{1, 7}, {9, 7}, {17, 7}, {25, 6}, {0, 0}}
1454 +};
1455 +
1456 +struct nand_ecclayout nand_oob_128 = {
1457 +       .eccbytes = 64,
1458 +       .eccpos = {
1459 +               64, 65, 66, 67, 68, 69, 70, 71,
1460 +               72, 73, 74, 75, 76, 77, 78, 79,
1461 +               80, 81, 82, 83, 84, 85, 86, 86,
1462 +               88, 89, 90, 91, 92, 93, 94, 95,
1463 +               96, 97, 98, 99, 100, 101, 102, 103,
1464 +               104, 105, 106, 107, 108, 109, 110, 111,
1465 +               112, 113, 114, 115, 116, 117, 118, 119,
1466 +               120, 121, 122, 123, 124, 125, 126, 127},
1467 +       .oobfree = {{1, 7}, {9, 7}, {17, 7}, {25, 7}, {33, 7}, {41, 7}, {49, 7}, {57, 6}}
1468 +};
1469 +
1470 +flashdev_info devinfo;
1471 +
1472 +void dump_nfi(void)
1473 +{
1474 +}
1475 +
1476 +void dump_ecc(void)
1477 +{
1478 +}
1479 +
1480 +u32
1481 +nand_virt_to_phys_add(u32 va)
1482 +{
1483 +       u32 pageOffset = (va & (PAGE_SIZE - 1));
1484 +       pgd_t *pgd;
1485 +       pmd_t *pmd;
1486 +       pte_t *pte;
1487 +       u32 pa;
1488 +
1489 +       if (virt_addr_valid(va))
1490 +               return __virt_to_phys(va);
1491 +
1492 +       if (NULL == current) {
1493 +               printk(KERN_ERR "[nand_virt_to_phys_add] ERROR ,current is NULL! \n");
1494 +               return 0;
1495 +       }
1496 +
1497 +       if (NULL == current->mm) {
1498 +               printk(KERN_ERR "[nand_virt_to_phys_add] ERROR current->mm is NULL! tgid=0x%x, name=%s \n", current->tgid, current->comm);
1499 +               return 0;
1500 +       }
1501 +
1502 +       pgd = pgd_offset(current->mm, va);  /* what is tsk->mm */
1503 +       if (pgd_none(*pgd) || pgd_bad(*pgd)) {
1504 +               printk(KERN_ERR "[nand_virt_to_phys_add] ERROR, va=0x%x, pgd invalid! \n", va);
1505 +               return 0;
1506 +       }
1507 +
1508 +       pmd = pmd_offset((pud_t *)pgd, va);
1509 +       if (pmd_none(*pmd) || pmd_bad(*pmd)) {
1510 +               printk(KERN_ERR "[nand_virt_to_phys_add] ERROR, va=0x%x, pmd invalid! \n", va);
1511 +               return 0;
1512 +       }
1513 +
1514 +       pte = pte_offset_map(pmd, va);
1515 +       if (pte_present(*pte)) {
1516 +               pa = (pte_val(*pte) & (PAGE_MASK)) | pageOffset;
1517 +               return pa;
1518 +       }
1519 +
1520 +       printk(KERN_ERR "[nand_virt_to_phys_add] ERROR va=0x%x, pte invalid! \n", va);
1521 +       return 0;
1522 +}
1523 +EXPORT_SYMBOL(nand_virt_to_phys_add);
1524 +
1525 +bool
1526 +get_device_info(u16 id, u32 ext_id, flashdev_info * pdevinfo)
1527 +{
1528 +       u32 index;
1529 +       for (index = 0; gen_FlashTable[index].id != 0; index++) {
1530 +               if (id == gen_FlashTable[index].id && ext_id == gen_FlashTable[index].ext_id) {
1531 +                       pdevinfo->id = gen_FlashTable[index].id;
1532 +                       pdevinfo->ext_id = gen_FlashTable[index].ext_id;
1533 +                       pdevinfo->blocksize = gen_FlashTable[index].blocksize;
1534 +                       pdevinfo->addr_cycle = gen_FlashTable[index].addr_cycle;
1535 +                       pdevinfo->iowidth = gen_FlashTable[index].iowidth;
1536 +                       pdevinfo->timmingsetting = gen_FlashTable[index].timmingsetting;
1537 +                       pdevinfo->advancedmode = gen_FlashTable[index].advancedmode;
1538 +                       pdevinfo->pagesize = gen_FlashTable[index].pagesize;
1539 +                       pdevinfo->sparesize = gen_FlashTable[index].sparesize;
1540 +                       pdevinfo->totalsize = gen_FlashTable[index].totalsize;
1541 +                       memcpy(pdevinfo->devciename, gen_FlashTable[index].devciename, sizeof(pdevinfo->devciename));
1542 +                       printk(KERN_INFO "Device found in MTK table, ID: %x, EXT_ID: %x\n", id, ext_id);
1543 +
1544 +                       goto find;
1545 +               }
1546 +       }
1547 +
1548 +find:
1549 +       if (0 == pdevinfo->id) {
1550 +               printk(KERN_INFO "Device not found, ID: %x\n", id);
1551 +               return false;
1552 +       } else {
1553 +               return true;
1554 +       }
1555 +}
1556 +
1557 +static void
1558 +ECC_Config(struct mtk_nand_host_hw *hw,u32 ecc_bit)
1559 +{
1560 +       u32 u4ENCODESize;
1561 +       u32 u4DECODESize;
1562 +       u32 ecc_bit_cfg = ECC_CNFG_ECC4;
1563 +
1564 +       switch(ecc_bit){
1565 +       case 4:
1566 +               ecc_bit_cfg = ECC_CNFG_ECC4;
1567 +               break;
1568 +       case 8:
1569 +               ecc_bit_cfg = ECC_CNFG_ECC8;
1570 +               break;
1571 +       case 10:
1572 +               ecc_bit_cfg = ECC_CNFG_ECC10;
1573 +               break;
1574 +       case 12:
1575 +               ecc_bit_cfg = ECC_CNFG_ECC12;
1576 +               break;
1577 +       default:
1578 +               break;
1579 +       }
1580 +       DRV_WriteReg16(ECC_DECCON_REG16, DEC_DE);
1581 +       do {
1582 +       } while (!DRV_Reg16(ECC_DECIDLE_REG16));
1583 +
1584 +       DRV_WriteReg16(ECC_ENCCON_REG16, ENC_DE);
1585 +       do {
1586 +       } while (!DRV_Reg32(ECC_ENCIDLE_REG32));
1587 +
1588 +       /* setup FDM register base */
1589 +       DRV_WriteReg32(ECC_FDMADDR_REG32, NFI_FDM0L_REG32);
1590 +
1591 +       /* Sector + FDM */
1592 +       u4ENCODESize = (hw->nand_sec_size + 8) << 3;
1593 +       /* Sector + FDM + YAFFS2 meta data bits */
1594 +       u4DECODESize = ((hw->nand_sec_size + 8) << 3) + ecc_bit * 13;
1595 +
1596 +       /* configure ECC decoder && encoder */
1597 +       DRV_WriteReg32(ECC_DECCNFG_REG32, ecc_bit_cfg | DEC_CNFG_NFI | DEC_CNFG_EMPTY_EN | (u4DECODESize << DEC_CNFG_CODE_SHIFT));
1598 +
1599 +       DRV_WriteReg32(ECC_ENCCNFG_REG32, ecc_bit_cfg | ENC_CNFG_NFI | (u4ENCODESize << ENC_CNFG_MSG_SHIFT));
1600 +       NFI_SET_REG32(ECC_DECCNFG_REG32, DEC_CNFG_EL);
1601 +}
1602 +
1603 +static void
1604 +ECC_Decode_Start(void)
1605 +{
1606 +       while (!(DRV_Reg16(ECC_DECIDLE_REG16) & DEC_IDLE))
1607 +               ;
1608 +       DRV_WriteReg16(ECC_DECCON_REG16, DEC_EN);
1609 +}
1610 +
1611 +static void
1612 +ECC_Decode_End(void)
1613 +{
1614 +       while (!(DRV_Reg16(ECC_DECIDLE_REG16) & DEC_IDLE))
1615 +               ;
1616 +       DRV_WriteReg16(ECC_DECCON_REG16, DEC_DE);
1617 +}
1618 +
1619 +static void
1620 +ECC_Encode_Start(void)
1621 +{
1622 +       while (!(DRV_Reg32(ECC_ENCIDLE_REG32) & ENC_IDLE))
1623 +               ;
1624 +       mb();
1625 +       DRV_WriteReg16(ECC_ENCCON_REG16, ENC_EN);
1626 +}
1627 +
1628 +static void
1629 +ECC_Encode_End(void)
1630 +{
1631 +       /* wait for device returning idle */
1632 +       while (!(DRV_Reg32(ECC_ENCIDLE_REG32) & ENC_IDLE)) ;
1633 +       mb();
1634 +       DRV_WriteReg16(ECC_ENCCON_REG16, ENC_DE);
1635 +}
1636 +
1637 +static bool
1638 +mtk_nand_check_bch_error(struct mtd_info *mtd, u8 * pDataBuf, u32 u4SecIndex, u32 u4PageAddr)
1639 +{
1640 +       bool bRet = true;
1641 +       u16 u2SectorDoneMask = 1 << u4SecIndex;
1642 +       u32 u4ErrorNumDebug, i, u4ErrNum;
1643 +       u32 timeout = 0xFFFF;
1644 +       // int el;
1645 +       u32 au4ErrBitLoc[6];
1646 +       u32 u4ErrByteLoc, u4BitOffset;
1647 +       u32 u4ErrBitLoc1th, u4ErrBitLoc2nd;
1648 +
1649 +       //4 // Wait for Decode Done
1650 +       while (0 == (u2SectorDoneMask & DRV_Reg16(ECC_DECDONE_REG16))) {
1651 +               timeout--;
1652 +               if (0 == timeout)
1653 +                       return false;
1654 +       }
1655 +       /* We will manually correct the error bits in the last sector, not all the sectors of the page! */
1656 +       memset(au4ErrBitLoc, 0x0, sizeof(au4ErrBitLoc));
1657 +       u4ErrorNumDebug = DRV_Reg32(ECC_DECENUM_REG32);
1658 +       u4ErrNum = DRV_Reg32(ECC_DECENUM_REG32) >> (u4SecIndex << 2);
1659 +       u4ErrNum &= 0xF;
1660 +
1661 +       if (u4ErrNum) {
1662 +               if (0xF == u4ErrNum) {
1663 +                       mtd->ecc_stats.failed++;
1664 +                       bRet = false;
1665 +                       printk(KERN_ERR"mtk_nand: UnCorrectable at PageAddr=%d\n", u4PageAddr);
1666 +               } else {
1667 +                       for (i = 0; i < ((u4ErrNum + 1) >> 1); ++i) {
1668 +                               au4ErrBitLoc[i] = DRV_Reg32(ECC_DECEL0_REG32 + i);
1669 +                               u4ErrBitLoc1th = au4ErrBitLoc[i] & 0x1FFF;
1670 +                               if (u4ErrBitLoc1th < 0x1000) {
1671 +                                       u4ErrByteLoc = u4ErrBitLoc1th / 8;
1672 +                                       u4BitOffset = u4ErrBitLoc1th % 8;
1673 +                                       pDataBuf[u4ErrByteLoc] = pDataBuf[u4ErrByteLoc] ^ (1 << u4BitOffset);
1674 +                                       mtd->ecc_stats.corrected++;
1675 +                               } else {
1676 +                                       mtd->ecc_stats.failed++;
1677 +                               }
1678 +                               u4ErrBitLoc2nd = (au4ErrBitLoc[i] >> 16) & 0x1FFF;
1679 +                               if (0 != u4ErrBitLoc2nd) {
1680 +                                       if (u4ErrBitLoc2nd < 0x1000) {
1681 +                                               u4ErrByteLoc = u4ErrBitLoc2nd / 8;
1682 +                                               u4BitOffset = u4ErrBitLoc2nd % 8;
1683 +                                               pDataBuf[u4ErrByteLoc] = pDataBuf[u4ErrByteLoc] ^ (1 << u4BitOffset);
1684 +                                               mtd->ecc_stats.corrected++;
1685 +                                       } else {
1686 +                                               mtd->ecc_stats.failed++;
1687 +                                               //printk(KERN_ERR"UnCorrectable High ErrLoc=%d\n", au4ErrBitLoc[i]);
1688 +                                       }
1689 +                               }
1690 +                       }
1691 +               }
1692 +               if (0 == (DRV_Reg16(ECC_DECFER_REG16) & (1 << u4SecIndex)))
1693 +                       bRet = false;
1694 +       }
1695 +       return bRet;
1696 +}
1697 +
1698 +static bool
1699 +mtk_nand_RFIFOValidSize(u16 u2Size)
1700 +{
1701 +       u32 timeout = 0xFFFF;
1702 +       while (FIFO_RD_REMAIN(DRV_Reg16(NFI_FIFOSTA_REG16)) < u2Size) {
1703 +               timeout--;
1704 +               if (0 == timeout)
1705 +                       return false;
1706 +       }
1707 +       return true;
1708 +}
1709 +
1710 +static bool
1711 +mtk_nand_WFIFOValidSize(u16 u2Size)
1712 +{
1713 +       u32 timeout = 0xFFFF;
1714 +
1715 +       while (FIFO_WR_REMAIN(DRV_Reg16(NFI_FIFOSTA_REG16)) > u2Size) {
1716 +               timeout--;
1717 +               if (0 == timeout)
1718 +                       return false;
1719 +       }
1720 +       return true;
1721 +}
1722 +
1723 +static bool
1724 +mtk_nand_status_ready(u32 u4Status)
1725 +{
1726 +       u32 timeout = 0xFFFF;
1727 +
1728 +       while ((DRV_Reg32(NFI_STA_REG32) & u4Status) != 0) {
1729 +               timeout--;
1730 +               if (0 == timeout)
1731 +                       return false;
1732 +       }
1733 +       return true;
1734 +}
1735 +
1736 +static bool
1737 +mtk_nand_reset(void)
1738 +{
1739 +       int timeout = 0xFFFF;
1740 +       if (DRV_Reg16(NFI_MASTERSTA_REG16)) {
1741 +               mb();
1742 +               DRV_WriteReg16(NFI_CON_REG16, CON_FIFO_FLUSH | CON_NFI_RST);
1743 +               while (DRV_Reg16(NFI_MASTERSTA_REG16)) {
1744 +                       timeout--;
1745 +                       if (!timeout)
1746 +                               MSG(INIT, "Wait for NFI_MASTERSTA timeout\n");
1747 +               }
1748 +       }
1749 +       /* issue reset operation */
1750 +       mb();
1751 +       DRV_WriteReg16(NFI_CON_REG16, CON_FIFO_FLUSH | CON_NFI_RST);
1752 +
1753 +       return mtk_nand_status_ready(STA_NFI_FSM_MASK | STA_NAND_BUSY) && mtk_nand_RFIFOValidSize(0) && mtk_nand_WFIFOValidSize(0);
1754 +}
1755 +
1756 +static void
1757 +mtk_nand_set_mode(u16 u2OpMode)
1758 +{
1759 +       u16 u2Mode = DRV_Reg16(NFI_CNFG_REG16);
1760 +       u2Mode &= ~CNFG_OP_MODE_MASK;
1761 +       u2Mode |= u2OpMode;
1762 +       DRV_WriteReg16(NFI_CNFG_REG16, u2Mode);
1763 +}
1764 +
1765 +static void
1766 +mtk_nand_set_autoformat(bool bEnable)
1767 +{
1768 +       if (bEnable)
1769 +               NFI_SET_REG16(NFI_CNFG_REG16, CNFG_AUTO_FMT_EN);
1770 +       else
1771 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AUTO_FMT_EN);
1772 +}
1773 +
1774 +static void
1775 +mtk_nand_configure_fdm(u16 u2FDMSize)
1776 +{
1777 +       NFI_CLN_REG16(NFI_PAGEFMT_REG16, PAGEFMT_FDM_MASK | PAGEFMT_FDM_ECC_MASK);
1778 +       NFI_SET_REG16(NFI_PAGEFMT_REG16, u2FDMSize << PAGEFMT_FDM_SHIFT);
1779 +       NFI_SET_REG16(NFI_PAGEFMT_REG16, u2FDMSize << PAGEFMT_FDM_ECC_SHIFT);
1780 +}
1781 +
1782 +static void
1783 +mtk_nand_configure_lock(void)
1784 +{
1785 +       u32 u4WriteColNOB = 2;
1786 +       u32 u4WriteRowNOB = 3;
1787 +       u32 u4EraseColNOB = 0;
1788 +       u32 u4EraseRowNOB = 3;
1789 +       DRV_WriteReg16(NFI_LOCKANOB_REG16,
1790 +               (u4WriteColNOB << PROG_CADD_NOB_SHIFT) | (u4WriteRowNOB << PROG_RADD_NOB_SHIFT) | (u4EraseColNOB << ERASE_CADD_NOB_SHIFT) | (u4EraseRowNOB << ERASE_RADD_NOB_SHIFT));
1791 +
1792 +       if (CHIPVER_ECO_1 == g_u4ChipVer) {
1793 +               int i;
1794 +               for (i = 0; i < 16; ++i) {
1795 +                       DRV_WriteReg32(NFI_LOCK00ADD_REG32 + (i << 1), 0xFFFFFFFF);
1796 +                       DRV_WriteReg32(NFI_LOCK00FMT_REG32 + (i << 1), 0xFFFFFFFF);
1797 +               }
1798 +               //DRV_WriteReg16(NFI_LOCKANOB_REG16, 0x0);
1799 +               DRV_WriteReg32(NFI_LOCKCON_REG32, 0xFFFFFFFF);
1800 +               DRV_WriteReg16(NFI_LOCK_REG16, NFI_LOCK_ON);
1801 +       }
1802 +}
1803 +
1804 +static bool
1805 +mtk_nand_pio_ready(void)
1806 +{
1807 +       int count = 0;
1808 +       while (!(DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1)) {
1809 +               count++;
1810 +               if (count > 0xffff) {
1811 +                       printk("PIO_DIRDY timeout\n");
1812 +                       return false;
1813 +               }
1814 +       }
1815 +
1816 +       return true;
1817 +}
1818 +
1819 +static bool
1820 +mtk_nand_set_command(u16 command)
1821 +{
1822 +       mb();
1823 +       DRV_WriteReg16(NFI_CMD_REG16, command);
1824 +       return mtk_nand_status_ready(STA_CMD_STATE);
1825 +}
1826 +
1827 +static bool
1828 +mtk_nand_set_address(u32 u4ColAddr, u32 u4RowAddr, u16 u2ColNOB, u16 u2RowNOB)
1829 +{
1830 +       mb();
1831 +       DRV_WriteReg32(NFI_COLADDR_REG32, u4ColAddr);
1832 +       DRV_WriteReg32(NFI_ROWADDR_REG32, u4RowAddr);
1833 +       DRV_WriteReg16(NFI_ADDRNOB_REG16, u2ColNOB | (u2RowNOB << ADDR_ROW_NOB_SHIFT));
1834 +       return mtk_nand_status_ready(STA_ADDR_STATE);
1835 +}
1836 +
1837 +static void mtk_nfc_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
1838 +{
1839 +       if (ctrl & NAND_ALE) {
1840 +               mtk_nand_set_address(dat, 0, 1, 0);
1841 +       } else if (ctrl & NAND_CLE) {
1842 +               mtk_nand_reset();
1843 +                mtk_nand_set_mode(0x6000);
1844 +               mtk_nand_set_command(dat);
1845 +       }
1846 +}
1847 +
1848 +static bool
1849 +mtk_nand_check_RW_count(u16 u2WriteSize)
1850 +{
1851 +       u32 timeout = 0xFFFF;
1852 +       u16 u2SecNum = u2WriteSize >> 9;
1853 +
1854 +       while (ADDRCNTR_CNTR(DRV_Reg16(NFI_ADDRCNTR_REG16)) < u2SecNum) {
1855 +               timeout--;
1856 +               if (0 == timeout) {
1857 +                       printk(KERN_INFO "[%s] timeout\n", __FUNCTION__);
1858 +                       return false;
1859 +               }
1860 +       }
1861 +       return true;
1862 +}
1863 +
1864 +static bool
1865 +mtk_nand_ready_for_read(struct nand_chip *nand, u32 u4RowAddr, u32 u4ColAddr, bool full, u8 * buf)
1866 +{
1867 +       /* Reset NFI HW internal state machine and flush NFI in/out FIFO */
1868 +       bool bRet = false;
1869 +       u16 sec_num = 1 << (nand->page_shift - 9);
1870 +       u32 col_addr = u4ColAddr;
1871 +       u32 colnob = 2, rownob = devinfo.addr_cycle - 2;
1872 +       if (nand->options & NAND_BUSWIDTH_16)
1873 +               col_addr /= 2;
1874 +
1875 +       if (!mtk_nand_reset())
1876 +               goto cleanup;
1877 +       if (g_bHwEcc)   {
1878 +               NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1879 +       } else  {
1880 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1881 +       }
1882 +
1883 +       mtk_nand_set_mode(CNFG_OP_READ);
1884 +       NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
1885 +       DRV_WriteReg16(NFI_CON_REG16, sec_num << CON_NFI_SEC_SHIFT);
1886 +
1887 +       if (full) {
1888 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
1889 +
1890 +               if (g_bHwEcc)
1891 +                       NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1892 +               else
1893 +                       NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1894 +       } else {
1895 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1896 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
1897 +       }
1898 +
1899 +       mtk_nand_set_autoformat(full);
1900 +       if (full)
1901 +               if (g_bHwEcc)
1902 +                       ECC_Decode_Start();
1903 +       if (!mtk_nand_set_command(NAND_CMD_READ0))
1904 +               goto cleanup;
1905 +       if (!mtk_nand_set_address(col_addr, u4RowAddr, colnob, rownob))
1906 +               goto cleanup;
1907 +       if (!mtk_nand_set_command(NAND_CMD_READSTART))
1908 +               goto cleanup;
1909 +       if (!mtk_nand_status_ready(STA_NAND_BUSY))
1910 +               goto cleanup;
1911 +
1912 +       bRet = true;
1913 +
1914 +cleanup:
1915 +       return bRet;
1916 +}
1917 +
1918 +static bool
1919 +mtk_nand_ready_for_write(struct nand_chip *nand, u32 u4RowAddr, u32 col_addr, bool full, u8 * buf)
1920 +{
1921 +       bool bRet = false;
1922 +       u32 sec_num = 1 << (nand->page_shift - 9);
1923 +       u32 colnob = 2, rownob = devinfo.addr_cycle - 2;
1924 +       if (nand->options & NAND_BUSWIDTH_16)
1925 +               col_addr /= 2;
1926 +
1927 +       /* Reset NFI HW internal state machine and flush NFI in/out FIFO */
1928 +       if (!mtk_nand_reset())
1929 +               return false;
1930 +
1931 +       mtk_nand_set_mode(CNFG_OP_PRGM);
1932 +
1933 +       NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
1934 +
1935 +       DRV_WriteReg16(NFI_CON_REG16, sec_num << CON_NFI_SEC_SHIFT);
1936 +
1937 +       if (full) {
1938 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
1939 +               if (g_bHwEcc)
1940 +                       NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1941 +               else
1942 +                       NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1943 +       } else {
1944 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
1945 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
1946 +       }
1947 +
1948 +       mtk_nand_set_autoformat(full);
1949 +
1950 +       if (full)
1951 +               if (g_bHwEcc)
1952 +                       ECC_Encode_Start();
1953 +
1954 +       if (!mtk_nand_set_command(NAND_CMD_SEQIN))
1955 +               goto cleanup;
1956 +       //1 FIXED ME: For Any Kind of AddrCycle
1957 +       if (!mtk_nand_set_address(col_addr, u4RowAddr, colnob, rownob))
1958 +               goto cleanup;
1959 +
1960 +       if (!mtk_nand_status_ready(STA_NAND_BUSY))
1961 +               goto cleanup;
1962 +
1963 +       bRet = true;
1964 +
1965 +cleanup:
1966 +       return bRet;
1967 +}
1968 +
1969 +static bool
1970 +mtk_nand_check_dececc_done(u32 u4SecNum)
1971 +{
1972 +       u32 timeout, dec_mask;
1973 +
1974 +       timeout = 0xffff;
1975 +       dec_mask = (1 << u4SecNum) - 1;
1976 +       while ((dec_mask != DRV_Reg(ECC_DECDONE_REG16)) && timeout > 0)
1977 +               timeout--;
1978 +       if (timeout == 0) {
1979 +               MSG(VERIFY, "ECC_DECDONE: timeout\n");
1980 +               return false;
1981 +       }
1982 +       return true;
1983 +}
1984 +
1985 +static bool
1986 +mtk_nand_mcu_read_data(u8 * buf, u32 length)
1987 +{
1988 +       int timeout = 0xffff;
1989 +       u32 i;
1990 +       u32 *buf32 = (u32 *) buf;
1991 +       if ((u32) buf % 4 || length % 4)
1992 +               NFI_SET_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
1993 +       else
1994 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
1995 +
1996 +       //DRV_WriteReg32(NFI_STRADDR_REG32, 0);
1997 +       mb();
1998 +       NFI_SET_REG16(NFI_CON_REG16, CON_NFI_BRD);
1999 +
2000 +       if ((u32) buf % 4 || length % 4) {
2001 +               for (i = 0; (i < (length)) && (timeout > 0);) {
2002 +                       if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
2003 +                               *buf++ = (u8) DRV_Reg32(NFI_DATAR_REG32);
2004 +                               i++;
2005 +                       } else {
2006 +                               timeout--;
2007 +                       }
2008 +                       if (0 == timeout) {
2009 +                               printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
2010 +                               dump_nfi();
2011 +                               return false;
2012 +                       }
2013 +               }
2014 +       } else {
2015 +               for (i = 0; (i < (length >> 2)) && (timeout > 0);) {
2016 +                       if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
2017 +                               *buf32++ = DRV_Reg32(NFI_DATAR_REG32);
2018 +                               i++;
2019 +                       } else {
2020 +                               timeout--;
2021 +                       }
2022 +                       if (0 == timeout) {
2023 +                               printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
2024 +                               dump_nfi();
2025 +                               return false;
2026 +                       }
2027 +               }
2028 +       }
2029 +       return true;
2030 +}
2031 +
2032 +static bool
2033 +mtk_nand_read_page_data(struct mtd_info *mtd, u8 * pDataBuf, u32 u4Size)
2034 +{
2035 +       return mtk_nand_mcu_read_data(pDataBuf, u4Size);
2036 +}
2037 +
2038 +static bool
2039 +mtk_nand_mcu_write_data(struct mtd_info *mtd, const u8 * buf, u32 length)
2040 +{
2041 +       u32 timeout = 0xFFFF;
2042 +       u32 i;
2043 +       u32 *pBuf32;
2044 +       NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
2045 +       mb();
2046 +       NFI_SET_REG16(NFI_CON_REG16, CON_NFI_BWR);
2047 +       pBuf32 = (u32 *) buf;
2048 +
2049 +       if ((u32) buf % 4 || length % 4)
2050 +               NFI_SET_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
2051 +       else
2052 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
2053 +
2054 +       if ((u32) buf % 4 || length % 4) {
2055 +               for (i = 0; (i < (length)) && (timeout > 0);) {
2056 +                       if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
2057 +                               DRV_WriteReg32(NFI_DATAW_REG32, *buf++);
2058 +                               i++;
2059 +                       } else {
2060 +                               timeout--;
2061 +                       }
2062 +                       if (0 == timeout) {
2063 +                               printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
2064 +                               dump_nfi();
2065 +                               return false;
2066 +                       }
2067 +               }
2068 +       } else {
2069 +               for (i = 0; (i < (length >> 2)) && (timeout > 0);) {
2070 +                       if (DRV_Reg16(NFI_PIO_DIRDY_REG16) & 1) {
2071 +                               DRV_WriteReg32(NFI_DATAW_REG32, *pBuf32++);
2072 +                               i++;
2073 +                       } else {
2074 +                               timeout--;
2075 +                       }
2076 +                       if (0 == timeout) {
2077 +                               printk(KERN_ERR "[%s] timeout\n", __FUNCTION__);
2078 +                               dump_nfi();
2079 +                               return false;
2080 +                       }
2081 +               }
2082 +       }
2083 +
2084 +       return true;
2085 +}
2086 +
2087 +static bool
2088 +mtk_nand_write_page_data(struct mtd_info *mtd, u8 * buf, u32 size)
2089 +{
2090 +       return mtk_nand_mcu_write_data(mtd, buf, size);
2091 +}
2092 +
2093 +static void
2094 +mtk_nand_read_fdm_data(u8 * pDataBuf, u32 u4SecNum)
2095 +{
2096 +       u32 i;
2097 +       u32 *pBuf32 = (u32 *) pDataBuf;
2098 +
2099 +       if (pBuf32) {
2100 +               for (i = 0; i < u4SecNum; ++i) {
2101 +                       *pBuf32++ = DRV_Reg32(NFI_FDM0L_REG32 + (i << 1));
2102 +                       *pBuf32++ = DRV_Reg32(NFI_FDM0M_REG32 + (i << 1));
2103 +               }
2104 +       }
2105 +}
2106 +
2107 +static u8 fdm_buf[64];
2108 +static void
2109 +mtk_nand_write_fdm_data(struct nand_chip *chip, u8 * pDataBuf, u32 u4SecNum)
2110 +{
2111 +       u32 i, j;
2112 +       u8 checksum = 0;
2113 +       bool empty = true;
2114 +       struct nand_oobfree *free_entry;
2115 +       u32 *pBuf32;
2116 +
2117 +       memcpy(fdm_buf, pDataBuf, u4SecNum * 8);
2118 +
2119 +       free_entry = layout->oobfree;
2120 +       for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free_entry[i].length; i++) {
2121 +               for (j = 0; j < free_entry[i].length; j++) {
2122 +                       if (pDataBuf[free_entry[i].offset + j] != 0xFF)
2123 +                               empty = false;
2124 +                       checksum ^= pDataBuf[free_entry[i].offset + j];
2125 +               }
2126 +       }
2127 +
2128 +       if (!empty) {
2129 +               fdm_buf[free_entry[i - 1].offset + free_entry[i - 1].length] = checksum;
2130 +       }
2131 +
2132 +       pBuf32 = (u32 *) fdm_buf;
2133 +       for (i = 0; i < u4SecNum; ++i) {
2134 +               DRV_WriteReg32(NFI_FDM0L_REG32 + (i << 1), *pBuf32++);
2135 +               DRV_WriteReg32(NFI_FDM0M_REG32 + (i << 1), *pBuf32++);
2136 +       }
2137 +}
2138 +
2139 +static void
2140 +mtk_nand_stop_read(void)
2141 +{
2142 +       NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BRD);
2143 +       mtk_nand_reset();
2144 +       if (g_bHwEcc)
2145 +               ECC_Decode_End();
2146 +       DRV_WriteReg16(NFI_INTR_EN_REG16, 0);
2147 +}
2148 +
2149 +static void
2150 +mtk_nand_stop_write(void)
2151 +{
2152 +       NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BWR);
2153 +       if (g_bHwEcc)
2154 +               ECC_Encode_End();
2155 +       DRV_WriteReg16(NFI_INTR_EN_REG16, 0);
2156 +}
2157 +
2158 +bool
2159 +mtk_nand_exec_read_page(struct mtd_info *mtd, u32 u4RowAddr, u32 u4PageSize, u8 * pPageBuf, u8 * pFDMBuf)
2160 +{
2161 +       u8 *buf;
2162 +       bool bRet = true;
2163 +       struct nand_chip *nand = mtd->priv;
2164 +       u32 u4SecNum = u4PageSize >> 9;
2165 +
2166 +       if (((u32) pPageBuf % 16) && local_buffer_16_align)
2167 +               buf = local_buffer_16_align;
2168 +       else
2169 +               buf = pPageBuf;
2170 +       if (mtk_nand_ready_for_read(nand, u4RowAddr, 0, true, buf)) {
2171 +               int j;
2172 +               for (j = 0 ; j < u4SecNum; j++) {
2173 +                       if (!mtk_nand_read_page_data(mtd, buf+j*512, 512))
2174 +                               bRet = false;
2175 +                       if(g_bHwEcc && !mtk_nand_check_dececc_done(j+1))
2176 +                               bRet = false;
2177 +                       if(g_bHwEcc && !mtk_nand_check_bch_error(mtd, buf+j*512, j, u4RowAddr))
2178 +                               bRet = false;
2179 +               }
2180 +               if (!mtk_nand_status_ready(STA_NAND_BUSY))
2181 +                       bRet = false;
2182 +
2183 +               mtk_nand_read_fdm_data(pFDMBuf, u4SecNum);
2184 +               mtk_nand_stop_read();
2185 +       }
2186 +
2187 +       if (buf == local_buffer_16_align)
2188 +               memcpy(pPageBuf, buf, u4PageSize);
2189 +
2190 +       return bRet;
2191 +}
2192 +
2193 +int
2194 +mtk_nand_exec_write_page(struct mtd_info *mtd, u32 u4RowAddr, u32 u4PageSize, u8 * pPageBuf, u8 * pFDMBuf)
2195 +{
2196 +       struct nand_chip *chip = mtd->priv;
2197 +       u32 u4SecNum = u4PageSize >> 9;
2198 +       u8 *buf;
2199 +       u8 status;
2200 +
2201 +       MSG(WRITE, "mtk_nand_exec_write_page, page: 0x%x\n", u4RowAddr);
2202 +
2203 +       if (((u32) pPageBuf % 16) && local_buffer_16_align) {
2204 +               printk(KERN_INFO "Data buffer not 16 bytes aligned: %p\n", pPageBuf);
2205 +               memcpy(local_buffer_16_align, pPageBuf, mtd->writesize);
2206 +               buf = local_buffer_16_align;
2207 +       } else
2208 +               buf = pPageBuf;
2209 +
2210 +       if (mtk_nand_ready_for_write(chip, u4RowAddr, 0, true, buf)) {
2211 +               mtk_nand_write_fdm_data(chip, pFDMBuf, u4SecNum);
2212 +               (void)mtk_nand_write_page_data(mtd, buf, u4PageSize);
2213 +               (void)mtk_nand_check_RW_count(u4PageSize);
2214 +               mtk_nand_stop_write();
2215 +               (void)mtk_nand_set_command(NAND_CMD_PAGEPROG);
2216 +               while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY) ;
2217 +       }
2218 +
2219 +       status = chip->waitfunc(mtd, chip);
2220 +       if (status & NAND_STATUS_FAIL)
2221 +               return -EIO;
2222 +       return 0;
2223 +}
2224 +
2225 +static int
2226 +get_start_end_block(struct mtd_info *mtd, int block, int *start_blk, int *end_blk)
2227 +{
2228 +       struct nand_chip *chip = mtd->priv;
2229 +       int i;
2230 +
2231 +       *start_blk = 0;
2232 +        for (i = 0; i <= part_num; i++)
2233 +        {
2234 +               if (i == part_num)
2235 +               {
2236 +                       // try the last reset partition
2237 +                       *end_blk = (chip->chipsize >> chip->phys_erase_shift) - 1;
2238 +                       if (*start_blk <= *end_blk)
2239 +                       {
2240 +                               if ((block >= *start_blk) && (block <= *end_blk))
2241 +                                       break;
2242 +                       }
2243 +               }
2244 +               // skip All partition entry
2245 +               else if (g_pasStatic_Partition[i].size == MTDPART_SIZ_FULL)
2246 +               {
2247 +                       continue;
2248 +               }
2249 +                *end_blk = *start_blk + (g_pasStatic_Partition[i].size >> chip->phys_erase_shift) - 1;
2250 +                if ((block >= *start_blk) && (block <= *end_blk))
2251 +                        break;
2252 +                *start_blk = *end_blk + 1;
2253 +        }
2254 +        if (*start_blk > *end_blk)
2255 +       {
2256 +                return -1;
2257 +       }
2258 +       return 0;
2259 +}
2260 +
2261 +static int
2262 +block_remap(struct mtd_info *mtd, int block)
2263 +{
2264 +       struct nand_chip *chip = mtd->priv;
2265 +       int start_blk, end_blk;
2266 +       int j, block_offset;
2267 +       int bad_block = 0;
2268 +
2269 +       if (chip->bbt == NULL) {
2270 +               printk("ERROR!! no bbt table for block_remap\n");
2271 +               return -1;
2272 +       }
2273 +
2274 +       if (get_start_end_block(mtd, block, &start_blk, &end_blk) < 0) {
2275 +               printk("ERROR!! can not find start_blk and end_blk\n");
2276 +               return -1;
2277 +       }
2278 +
2279 +       block_offset = block - start_blk;
2280 +       for (j = start_blk; j <= end_blk;j++) {
2281 +               if (((chip->bbt[j >> 2] >> ((j<<1) & 0x6)) & 0x3) == 0x0) {
2282 +                       if (!block_offset)
2283 +                               break;
2284 +                       block_offset--;
2285 +               } else {
2286 +                       bad_block++;
2287 +               }
2288 +       }
2289 +       if (j <= end_blk) {
2290 +               return j;
2291 +       } else {
2292 +               // remap to the bad block
2293 +               for (j = end_blk; bad_block > 0; j--)
2294 +               {
2295 +                       if (((chip->bbt[j >> 2] >> ((j<<1) & 0x6)) & 0x3) != 0x0)
2296 +                       {
2297 +                               bad_block--;
2298 +                               if (bad_block <= block_offset)
2299 +                                       return j;
2300 +                       }
2301 +               }
2302 +       }
2303 +
2304 +       printk("Error!! block_remap error\n");
2305 +       return -1;
2306 +}
2307 +
2308 +int
2309 +check_block_remap(struct mtd_info *mtd, int block)
2310 +{
2311 +       if (shift_on_bbt)
2312 +               return  block_remap(mtd, block);
2313 +       else
2314 +               return block;
2315 +}
2316 +EXPORT_SYMBOL(check_block_remap);
2317 +
2318 +
2319 +static int
2320 +write_next_on_fail(struct mtd_info *mtd, char *write_buf, int page, int * to_blk)
2321 +{
2322 +       struct nand_chip *chip = mtd->priv;
2323 +       int i, j, to_page = 0, first_page;
2324 +       char *buf, *oob;
2325 +       int start_blk = 0, end_blk;
2326 +       int mapped_block;
2327 +       int page_per_block_bit = chip->phys_erase_shift - chip->page_shift;
2328 +       int block = page >> page_per_block_bit;
2329 +
2330 +       // find next available block in the same MTD partition
2331 +       mapped_block = block_remap(mtd, block);
2332 +       if (mapped_block == -1)
2333 +               return NAND_STATUS_FAIL;
2334 +
2335 +       get_start_end_block(mtd, block, &start_blk, &end_blk);
2336 +
2337 +       buf = kzalloc(mtd->writesize + mtd->oobsize, GFP_KERNEL | GFP_DMA);
2338 +       if (buf == NULL)
2339 +               return -1;
2340 +
2341 +       oob = buf + mtd->writesize;
2342 +       for ((*to_blk) = block + 1; (*to_blk) <= end_blk ; (*to_blk)++) {
2343 +               if (nand_bbt_get(mtd, (*to_blk) << page_per_block_bit) == 0) {
2344 +                       int status;
2345 +                       status = mtk_nand_erase_hw(mtd, (*to_blk) << page_per_block_bit);
2346 +                       if (status & NAND_STATUS_FAIL)  {
2347 +                               mtk_nand_block_markbad_hw(mtd, (*to_blk) << chip->phys_erase_shift);
2348 +                               nand_bbt_set(mtd, (*to_blk) << page_per_block_bit, 0x3);
2349 +                       } else {
2350 +                               /* good block */
2351 +                               to_page = (*to_blk) << page_per_block_bit;
2352 +                               break;
2353 +                       }
2354 +               }
2355 +       }
2356 +
2357 +       if (!to_page) {
2358 +               kfree(buf);
2359 +               return -1;
2360 +       }
2361 +
2362 +       first_page = (page >> page_per_block_bit) << page_per_block_bit;
2363 +       for (i = 0; i < (1 << page_per_block_bit); i++) {
2364 +               if ((first_page + i) != page) {
2365 +                       mtk_nand_read_oob_hw(mtd, chip, (first_page+i));
2366 +                       for (j = 0; j < mtd->oobsize; j++)
2367 +                               if (chip->oob_poi[j] != (unsigned char)0xff)
2368 +                                       break;
2369 +                       if (j < mtd->oobsize)   {
2370 +                               mtk_nand_exec_read_page(mtd, (first_page+i), mtd->writesize, buf, oob);
2371 +                               memset(oob, 0xff, mtd->oobsize);
2372 +                               if (mtk_nand_exec_write_page(mtd, to_page + i, mtd->writesize, (u8 *)buf, oob) != 0) {
2373 +                                       int ret, new_blk = 0;
2374 +                                       nand_bbt_set(mtd, to_page, 0x3);
2375 +                                       ret =  write_next_on_fail(mtd, buf, to_page + i, &new_blk);
2376 +                                       if (ret) {
2377 +                                               kfree(buf);
2378 +                                               mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
2379 +                                               return ret;
2380 +                                       }
2381 +                                       mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
2382 +                                       *to_blk = new_blk;
2383 +                                       to_page = ((*to_blk) <<  page_per_block_bit);
2384 +                               }
2385 +                       }
2386 +               } else {
2387 +                       memset(chip->oob_poi, 0xff, mtd->oobsize);
2388 +                       if (mtk_nand_exec_write_page(mtd, to_page + i, mtd->writesize, (u8 *)write_buf, chip->oob_poi) != 0) {
2389 +                               int ret, new_blk = 0;
2390 +                               nand_bbt_set(mtd, to_page, 0x3);
2391 +                               ret =  write_next_on_fail(mtd, write_buf, to_page + i, &new_blk);
2392 +                               if (ret) {
2393 +                                       kfree(buf);
2394 +                                       mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
2395 +                                       return ret;
2396 +                               }
2397 +                               mtk_nand_block_markbad_hw(mtd, to_page << chip->page_shift);
2398 +                               *to_blk = new_blk;
2399 +                               to_page = ((*to_blk) <<  page_per_block_bit);
2400 +                       }
2401 +               }
2402 +       }
2403 +
2404 +       kfree(buf);
2405 +
2406 +       return 0;
2407 +}
2408 +
2409 +static int
2410 +mtk_nand_write_page(struct mtd_info *mtd, struct nand_chip *chip, uint32_t offset,
2411 +               int data_len, const u8 * buf, int oob_required, int page, int cached, int raw)
2412 +{
2413 +       int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2414 +       int block = page / page_per_block;
2415 +       u16 page_in_block = page % page_per_block;
2416 +       int mapped_block = block;
2417 +
2418 +#if defined(MTK_NAND_BMT)
2419 +       mapped_block = get_mapping_block_index(block);
2420 +       // write bad index into oob
2421 +       if (mapped_block != block)
2422 +               set_bad_index_to_oob(chip->oob_poi, block);
2423 +       else
2424 +               set_bad_index_to_oob(chip->oob_poi, FAKE_INDEX);
2425 +#else
2426 +       if (shift_on_bbt) {
2427 +               mapped_block = block_remap(mtd, block);
2428 +               if (mapped_block == -1)
2429 +                       return NAND_STATUS_FAIL;
2430 +               if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2431 +                       return NAND_STATUS_FAIL;
2432 +       }
2433 +#endif
2434 +       do {
2435 +               if (mtk_nand_exec_write_page(mtd, page_in_block + mapped_block * page_per_block, mtd->writesize, (u8 *)buf, chip->oob_poi)) {
2436 +                       MSG(INIT, "write fail at block: 0x%x, page: 0x%x\n", mapped_block, page_in_block);
2437 +#if defined(MTK_NAND_BMT)
2438 +                       if (update_bmt((page_in_block + mapped_block * page_per_block) << chip->page_shift, UPDATE_WRITE_FAIL, (u8 *) buf, chip->oob_poi)) {
2439 +                               MSG(INIT, "Update BMT success\n");
2440 +                               return 0;
2441 +                       } else {
2442 +                               MSG(INIT, "Update BMT fail\n");
2443 +                               return -EIO;
2444 +                       }
2445 +#else
2446 +                       {
2447 +                               int new_blk;
2448 +                               nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
2449 +                               if (write_next_on_fail(mtd, (char *)buf, page_in_block + mapped_block * page_per_block, &new_blk) != 0)
2450 +                               {
2451 +                               mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
2452 +                               return NAND_STATUS_FAIL;
2453 +                               }
2454 +                               mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
2455 +                               break;
2456 +                       }
2457 +#endif
2458 +               } else
2459 +                       break;
2460 +       } while(1);
2461 +
2462 +       return 0;
2463 +}
2464 +
2465 +static void
2466 +mtk_nand_command_bp(struct mtd_info *mtd, unsigned int command, int column, int page_addr)
2467 +{
2468 +       struct nand_chip *nand = mtd->priv;
2469 +
2470 +       switch (command) {
2471 +       case NAND_CMD_SEQIN:
2472 +               memset(g_kCMD.au1OOB, 0xFF, sizeof(g_kCMD.au1OOB));
2473 +               g_kCMD.pDataBuf = NULL;
2474 +               g_kCMD.u4RowAddr = page_addr;
2475 +               g_kCMD.u4ColAddr = column;
2476 +               break;
2477 +
2478 +       case NAND_CMD_PAGEPROG:
2479 +               if (g_kCMD.pDataBuf || (0xFF != g_kCMD.au1OOB[nand_badblock_offset])) {
2480 +                       u8 *pDataBuf = g_kCMD.pDataBuf ? g_kCMD.pDataBuf : nand->buffers->databuf;
2481 +                       mtk_nand_exec_write_page(mtd, g_kCMD.u4RowAddr, mtd->writesize, pDataBuf, g_kCMD.au1OOB);
2482 +                       g_kCMD.u4RowAddr = (u32) - 1;
2483 +                       g_kCMD.u4OOBRowAddr = (u32) - 1;
2484 +               }
2485 +               break;
2486 +
2487 +       case NAND_CMD_READOOB:
2488 +               g_kCMD.u4RowAddr = page_addr;
2489 +               g_kCMD.u4ColAddr = column + mtd->writesize;
2490 +               break;
2491 +
2492 +       case NAND_CMD_READ0:
2493 +               g_kCMD.u4RowAddr = page_addr;
2494 +               g_kCMD.u4ColAddr = column;
2495 +               break;
2496 +
2497 +       case NAND_CMD_ERASE1:
2498 +               nand->state=FL_ERASING;
2499 +               (void)mtk_nand_reset();
2500 +               mtk_nand_set_mode(CNFG_OP_ERASE);
2501 +               (void)mtk_nand_set_command(NAND_CMD_ERASE1);
2502 +               (void)mtk_nand_set_address(0, page_addr, 0, devinfo.addr_cycle - 2);
2503 +               break;
2504 +
2505 +       case NAND_CMD_ERASE2:
2506 +               (void)mtk_nand_set_command(NAND_CMD_ERASE2);
2507 +               while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY)
2508 +                       ;
2509 +               break;
2510 +
2511 +       case NAND_CMD_STATUS:
2512 +               (void)mtk_nand_reset();
2513 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_BYTE_RW);
2514 +               mtk_nand_set_mode(CNFG_OP_SRD);
2515 +               mtk_nand_set_mode(CNFG_READ_EN);
2516 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
2517 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2518 +               (void)mtk_nand_set_command(NAND_CMD_STATUS);
2519 +               NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_NOB_MASK);
2520 +               mb();
2521 +               DRV_WriteReg16(NFI_CON_REG16, CON_NFI_SRD | (1 << CON_NFI_NOB_SHIFT));
2522 +               g_bcmdstatus = true;
2523 +               break;
2524 +
2525 +       case NAND_CMD_RESET:
2526 +               (void)mtk_nand_reset();
2527 +               DRV_WriteReg16(NFI_INTR_EN_REG16, INTR_RST_DONE_EN);
2528 +               (void)mtk_nand_set_command(NAND_CMD_RESET);
2529 +               DRV_WriteReg16(NFI_BASE+0x44, 0xF1);
2530 +               while(!(DRV_Reg16(NFI_INTR_REG16)&INTR_RST_DONE_EN))
2531 +                       ;
2532 +               break;
2533 +
2534 +       case NAND_CMD_READID:
2535 +               mtk_nand_reset();
2536 +               /* Disable HW ECC */
2537 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2538 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
2539 +               NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN | CNFG_BYTE_RW);
2540 +               (void)mtk_nand_reset();
2541 +               mb();
2542 +               mtk_nand_set_mode(CNFG_OP_SRD);
2543 +               (void)mtk_nand_set_command(NAND_CMD_READID);
2544 +               (void)mtk_nand_set_address(0, 0, 1, 0);
2545 +               DRV_WriteReg16(NFI_CON_REG16, CON_NFI_SRD);
2546 +               while (DRV_Reg32(NFI_STA_REG32) & STA_DATAR_STATE)
2547 +                       ;
2548 +               break;
2549 +
2550 +       default:
2551 +               BUG();
2552 +               break;
2553 +       }
2554 +}
2555 +
2556 +static void
2557 +mtk_nand_select_chip(struct mtd_info *mtd, int chip)
2558 +{
2559 +       if ((chip == -1) && (false == g_bInitDone)) {
2560 +               struct nand_chip *nand = mtd->priv;
2561 +               struct mtk_nand_host *host = nand->priv;
2562 +               struct mtk_nand_host_hw *hw = host->hw;
2563 +               u32 spare_per_sector = mtd->oobsize / (mtd->writesize / 512);
2564 +               u32 ecc_bit = 4;
2565 +               u32 spare_bit = PAGEFMT_SPARE_16;
2566 +
2567 +               if (spare_per_sector >= 28) {
2568 +                       spare_bit = PAGEFMT_SPARE_28;
2569 +                       ecc_bit = 12;
2570 +                       spare_per_sector = 28;
2571 +               } else if (spare_per_sector >= 27) {
2572 +                       spare_bit = PAGEFMT_SPARE_27;
2573 +                       ecc_bit = 8;
2574 +                       spare_per_sector = 27;
2575 +               } else if (spare_per_sector >= 26) {
2576 +                       spare_bit = PAGEFMT_SPARE_26;
2577 +                       ecc_bit = 8;
2578 +                       spare_per_sector = 26;
2579 +               } else if (spare_per_sector >= 16) {
2580 +                       spare_bit = PAGEFMT_SPARE_16;
2581 +                       ecc_bit = 4;
2582 +                       spare_per_sector = 16;
2583 +               } else {
2584 +                       MSG(INIT, "[NAND]: NFI not support oobsize: %x\n", spare_per_sector);
2585 +                       ASSERT(0);
2586 +               }
2587 +               mtd->oobsize = spare_per_sector*(mtd->writesize/512);
2588 +               MSG(INIT, "[NAND]select ecc bit:%d, sparesize :%d spare_per_sector=%d\n",ecc_bit,mtd->oobsize,spare_per_sector);
2589 +               /* Setup PageFormat */
2590 +               if (4096 == mtd->writesize) {
2591 +                       NFI_SET_REG16(NFI_PAGEFMT_REG16, (spare_bit << PAGEFMT_SPARE_SHIFT) | PAGEFMT_4K);
2592 +                       nand->cmdfunc = mtk_nand_command_bp;
2593 +               } else if (2048 == mtd->writesize) {
2594 +                       NFI_SET_REG16(NFI_PAGEFMT_REG16, (spare_bit << PAGEFMT_SPARE_SHIFT) | PAGEFMT_2K);
2595 +                       nand->cmdfunc = mtk_nand_command_bp;
2596 +               }
2597 +               ECC_Config(hw,ecc_bit);
2598 +               g_bInitDone = true;
2599 +       }
2600 +       switch (chip) {
2601 +       case -1:
2602 +               break;
2603 +       case 0:
2604 +       case 1:
2605 +               /*  Jun Shen, 2011.04.13  */
2606 +               /* Note: MT6577 EVB NAND  is mounted on CS0, but FPGA is CS1  */
2607 +               DRV_WriteReg16(NFI_CSEL_REG16, chip);
2608 +               /*  Jun Shen, 2011.04.13 */
2609 +               break;
2610 +       }
2611 +}
2612 +
2613 +static uint8_t
2614 +mtk_nand_read_byte(struct mtd_info *mtd)
2615 +{
2616 +       uint8_t retval = 0;
2617 +
2618 +       if (!mtk_nand_pio_ready()) {
2619 +               printk("pio ready timeout\n");
2620 +               retval = false;
2621 +       }
2622 +
2623 +       if (g_bcmdstatus) {
2624 +               retval = DRV_Reg8(NFI_DATAR_REG32);
2625 +               NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_NOB_MASK);
2626 +               mtk_nand_reset();
2627 +               if (g_bHwEcc) {
2628 +                       NFI_SET_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2629 +               } else {
2630 +                       NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2631 +               }
2632 +               g_bcmdstatus = false;
2633 +       } else
2634 +               retval = DRV_Reg8(NFI_DATAR_REG32);
2635 +
2636 +       return retval;
2637 +}
2638 +
2639 +static void
2640 +mtk_nand_read_buf(struct mtd_info *mtd, uint8_t * buf, int len)
2641 +{
2642 +       struct nand_chip *nand = (struct nand_chip *)mtd->priv;
2643 +       struct NAND_CMD *pkCMD = &g_kCMD;
2644 +       u32 u4ColAddr = pkCMD->u4ColAddr;
2645 +       u32 u4PageSize = mtd->writesize;
2646 +
2647 +       if (u4ColAddr < u4PageSize) {
2648 +               if ((u4ColAddr == 0) && (len >= u4PageSize)) {
2649 +                       mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, buf, pkCMD->au1OOB);
2650 +                       if (len > u4PageSize) {
2651 +                               u32 u4Size = min(len - u4PageSize, sizeof(pkCMD->au1OOB));
2652 +                               memcpy(buf + u4PageSize, pkCMD->au1OOB, u4Size);
2653 +                       }
2654 +               } else {
2655 +                       mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, nand->buffers->databuf, pkCMD->au1OOB);
2656 +                       memcpy(buf, nand->buffers->databuf + u4ColAddr, len);
2657 +               }
2658 +               pkCMD->u4OOBRowAddr = pkCMD->u4RowAddr;
2659 +       } else {
2660 +               u32 u4Offset = u4ColAddr - u4PageSize;
2661 +               u32 u4Size = min(len - u4Offset, sizeof(pkCMD->au1OOB));
2662 +               if (pkCMD->u4OOBRowAddr != pkCMD->u4RowAddr) {
2663 +                       mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, nand->buffers->databuf, pkCMD->au1OOB);
2664 +                       pkCMD->u4OOBRowAddr = pkCMD->u4RowAddr;
2665 +               }
2666 +               memcpy(buf, pkCMD->au1OOB + u4Offset, u4Size);
2667 +       }
2668 +       pkCMD->u4ColAddr += len;
2669 +}
2670 +
2671 +static void
2672 +mtk_nand_write_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
2673 +{
2674 +       struct NAND_CMD *pkCMD = &g_kCMD;
2675 +       u32 u4ColAddr = pkCMD->u4ColAddr;
2676 +       u32 u4PageSize = mtd->writesize;
2677 +       int i4Size, i;
2678 +
2679 +       if (u4ColAddr >= u4PageSize) {
2680 +               u32 u4Offset = u4ColAddr - u4PageSize;
2681 +               u8 *pOOB = pkCMD->au1OOB + u4Offset;
2682 +               i4Size = min(len, (int)(sizeof(pkCMD->au1OOB) - u4Offset));
2683 +               for (i = 0; i < i4Size; i++) {
2684 +                       pOOB[i] &= buf[i];
2685 +               }
2686 +       } else {
2687 +               pkCMD->pDataBuf = (u8 *) buf;
2688 +       }
2689 +
2690 +       pkCMD->u4ColAddr += len;
2691 +}
2692 +
2693 +static int
2694 +mtk_nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, const uint8_t * buf, int oob_required, int page)
2695 +{
2696 +       mtk_nand_write_buf(mtd, buf, mtd->writesize);
2697 +       mtk_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
2698 +       return 0;
2699 +}
2700 +
2701 +static int
2702 +mtk_nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, uint8_t * buf, int oob_required, int page)
2703 +{
2704 +       struct NAND_CMD *pkCMD = &g_kCMD;
2705 +       u32 u4ColAddr = pkCMD->u4ColAddr;
2706 +       u32 u4PageSize = mtd->writesize;
2707 +
2708 +       if (u4ColAddr == 0) {
2709 +               mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, buf, chip->oob_poi);
2710 +               pkCMD->u4ColAddr += u4PageSize + mtd->oobsize;
2711 +       }
2712 +
2713 +       return 0;
2714 +}
2715 +
2716 +static int
2717 +mtk_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip, u8 * buf, int page)
2718 +{
2719 +       int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2720 +       int block = page / page_per_block;
2721 +       u16 page_in_block = page % page_per_block;
2722 +       int mapped_block = block;
2723 +
2724 +#if defined (MTK_NAND_BMT)
2725 +       mapped_block = get_mapping_block_index(block);
2726 +       if (mtk_nand_exec_read_page(mtd, page_in_block + mapped_block * page_per_block,
2727 +                       mtd->writesize, buf, chip->oob_poi))
2728 +               return 0;
2729 +#else
2730 +       if (shift_on_bbt) {
2731 +               mapped_block = block_remap(mtd, block);
2732 +               if (mapped_block == -1)
2733 +                       return NAND_STATUS_FAIL;
2734 +               if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2735 +                       return NAND_STATUS_FAIL;
2736 +       }
2737 +
2738 +       if (mtk_nand_exec_read_page(mtd, page_in_block + mapped_block * page_per_block, mtd->writesize, buf, chip->oob_poi))
2739 +               return 0;
2740 +       else
2741 +               return -EIO;
2742 +#endif
2743 +}
2744 +
2745 +int
2746 +mtk_nand_erase_hw(struct mtd_info *mtd, int page)
2747 +{
2748 +       struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2749 +
2750 +       chip->erase(mtd, page);
2751 +
2752 +       return chip->waitfunc(mtd, chip);
2753 +}
2754 +
2755 +static int
2756 +mtk_nand_erase(struct mtd_info *mtd, int page)
2757 +{
2758 +       // get mapping
2759 +       struct nand_chip *chip = mtd->priv;
2760 +       int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2761 +       int page_in_block = page % page_per_block;
2762 +       int block = page / page_per_block;
2763 +       int mapped_block = block;
2764 +
2765 +#if defined(MTK_NAND_BMT)
2766 +       mapped_block = get_mapping_block_index(block);
2767 +#else
2768 +       if (shift_on_bbt) {
2769 +               mapped_block = block_remap(mtd, block);
2770 +               if (mapped_block == -1)
2771 +                       return NAND_STATUS_FAIL;
2772 +               if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2773 +                       return NAND_STATUS_FAIL;
2774 +       }
2775 +#endif
2776 +
2777 +       do {
2778 +               int status = mtk_nand_erase_hw(mtd, page_in_block + page_per_block * mapped_block);
2779 +
2780 +               if (status & NAND_STATUS_FAIL) {
2781 +#if defined (MTK_NAND_BMT)
2782 +                       if (update_bmt( (page_in_block + mapped_block * page_per_block) << chip->page_shift,
2783 +                                       UPDATE_ERASE_FAIL, NULL, NULL))
2784 +                       {
2785 +                               MSG(INIT, "Erase fail at block: 0x%x, update BMT success\n", mapped_block);
2786 +                               return 0;
2787 +                       } else {
2788 +                               MSG(INIT, "Erase fail at block: 0x%x, update BMT fail\n", mapped_block);
2789 +                               return NAND_STATUS_FAIL;
2790 +                       }
2791 +#else
2792 +                       mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
2793 +                       nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
2794 +                       if (shift_on_bbt) {
2795 +                               mapped_block = block_remap(mtd, block);
2796 +                               if (mapped_block == -1)
2797 +                                       return NAND_STATUS_FAIL;
2798 +                               if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2799 +                                       return NAND_STATUS_FAIL;
2800 +                       } else
2801 +                               return NAND_STATUS_FAIL;
2802 +#endif
2803 +               } else
2804 +                       break;
2805 +       } while(1);
2806 +
2807 +       return 0;
2808 +}
2809 +
2810 +static int
2811 +mtk_nand_read_oob_raw(struct mtd_info *mtd, uint8_t * buf, int page_addr, int len)
2812 +{
2813 +       struct nand_chip *chip = (struct nand_chip *)mtd->priv;
2814 +       u32 col_addr = 0;
2815 +       u32 sector = 0;
2816 +       int res = 0;
2817 +       u32 colnob = 2, rawnob = devinfo.addr_cycle - 2;
2818 +       int randomread = 0;
2819 +       int read_len = 0;
2820 +       int sec_num = 1<<(chip->page_shift-9);
2821 +       int spare_per_sector = mtd->oobsize/sec_num;
2822 +
2823 +       if (len >  NAND_MAX_OOBSIZE || len % OOB_AVAI_PER_SECTOR || !buf) {
2824 +               printk(KERN_WARNING "[%s] invalid parameter, len: %d, buf: %p\n", __FUNCTION__, len, buf);
2825 +               return -EINVAL;
2826 +       }
2827 +       if (len > spare_per_sector)
2828 +               randomread = 1;
2829 +       if (!randomread || !(devinfo.advancedmode & RAMDOM_READ)) {
2830 +               while (len > 0) {
2831 +                       read_len = min(len, spare_per_sector);
2832 +                       col_addr = NAND_SECTOR_SIZE + sector * (NAND_SECTOR_SIZE + spare_per_sector); // TODO: Fix this hard-code 16
2833 +                       if (!mtk_nand_ready_for_read(chip, page_addr, col_addr, false, NULL)) {
2834 +                               printk(KERN_WARNING "mtk_nand_ready_for_read return failed\n");
2835 +                               res = -EIO;
2836 +                               goto error;
2837 +                       }
2838 +                       if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
2839 +                               printk(KERN_WARNING "mtk_nand_mcu_read_data return failed\n");
2840 +                               res = -EIO;
2841 +                               goto error;
2842 +                       }
2843 +                       mtk_nand_check_RW_count(read_len);
2844 +                       mtk_nand_stop_read();
2845 +                       sector++;
2846 +                       len -= read_len;
2847 +               }
2848 +       } else {
2849 +               col_addr = NAND_SECTOR_SIZE;
2850 +               if (chip->options & NAND_BUSWIDTH_16)
2851 +                       col_addr /= 2;
2852 +               if (!mtk_nand_reset())
2853 +                       goto error;
2854 +               mtk_nand_set_mode(0x6000);
2855 +               NFI_SET_REG16(NFI_CNFG_REG16, CNFG_READ_EN);
2856 +               DRV_WriteReg16(NFI_CON_REG16, 4 << CON_NFI_SEC_SHIFT);
2857 +
2858 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_AHB);
2859 +               NFI_CLN_REG16(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
2860 +
2861 +               mtk_nand_set_autoformat(false);
2862 +
2863 +               if (!mtk_nand_set_command(NAND_CMD_READ0))
2864 +                       goto error;
2865 +               //1 FIXED ME: For Any Kind of AddrCycle
2866 +               if (!mtk_nand_set_address(col_addr, page_addr, colnob, rawnob))
2867 +                       goto error;
2868 +               if (!mtk_nand_set_command(NAND_CMD_READSTART))
2869 +                       goto error;
2870 +               if (!mtk_nand_status_ready(STA_NAND_BUSY))
2871 +                       goto error;
2872 +               read_len = min(len, spare_per_sector);
2873 +               if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
2874 +                       printk(KERN_WARNING "mtk_nand_mcu_read_data return failed first 16\n");
2875 +                       res = -EIO;
2876 +                       goto error;
2877 +               }
2878 +               sector++;
2879 +               len -= read_len;
2880 +               mtk_nand_stop_read();
2881 +               while (len > 0) {
2882 +                       read_len = min(len,  spare_per_sector);
2883 +                       if (!mtk_nand_set_command(0x05))
2884 +                               goto error;
2885 +                       col_addr = NAND_SECTOR_SIZE + sector * (NAND_SECTOR_SIZE + spare_per_sector);
2886 +                       if (chip->options & NAND_BUSWIDTH_16)
2887 +                               col_addr /= 2;
2888 +                       DRV_WriteReg32(NFI_COLADDR_REG32, col_addr);
2889 +                       DRV_WriteReg16(NFI_ADDRNOB_REG16, 2);
2890 +                       DRV_WriteReg16(NFI_CON_REG16, 4 << CON_NFI_SEC_SHIFT);
2891 +                       if (!mtk_nand_status_ready(STA_ADDR_STATE))
2892 +                               goto error;
2893 +                       if (!mtk_nand_set_command(0xE0))
2894 +                               goto error;
2895 +                       if (!mtk_nand_status_ready(STA_NAND_BUSY))
2896 +                               goto error;
2897 +                       if (!mtk_nand_mcu_read_data(buf + spare_per_sector * sector, read_len)) {
2898 +                               printk(KERN_WARNING "mtk_nand_mcu_read_data return failed first 16\n");
2899 +                               res = -EIO;
2900 +                               goto error;
2901 +                       }
2902 +                       mtk_nand_stop_read();
2903 +                       sector++;
2904 +                       len -= read_len;
2905 +               }
2906 +       }
2907 +error:
2908 +       NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BRD);
2909 +       return res;
2910 +}
2911 +
2912 +static int
2913 +mtk_nand_write_oob_raw(struct mtd_info *mtd, const uint8_t * buf, int page_addr, int len)
2914 +{
2915 +       struct nand_chip *chip = mtd->priv;
2916 +       u32 col_addr = 0;
2917 +       u32 sector = 0;
2918 +       int write_len = 0;
2919 +       int status;
2920 +       int sec_num = 1<<(chip->page_shift-9);
2921 +       int spare_per_sector = mtd->oobsize/sec_num;
2922 +
2923 +       if (len >  NAND_MAX_OOBSIZE || len % OOB_AVAI_PER_SECTOR || !buf) {
2924 +               printk(KERN_WARNING "[%s] invalid parameter, len: %d, buf: %p\n", __FUNCTION__, len, buf);
2925 +               return -EINVAL;
2926 +       }
2927 +
2928 +       while (len > 0) {
2929 +               write_len = min(len,  spare_per_sector);
2930 +               col_addr = sector * (NAND_SECTOR_SIZE +  spare_per_sector) + NAND_SECTOR_SIZE;
2931 +               if (!mtk_nand_ready_for_write(chip, page_addr, col_addr, false, NULL))
2932 +                       return -EIO;
2933 +               if (!mtk_nand_mcu_write_data(mtd, buf + sector * spare_per_sector, write_len))
2934 +                       return -EIO;
2935 +               (void)mtk_nand_check_RW_count(write_len);
2936 +               NFI_CLN_REG16(NFI_CON_REG16, CON_NFI_BWR);
2937 +               (void)mtk_nand_set_command(NAND_CMD_PAGEPROG);
2938 +               while (DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY)
2939 +                       ;
2940 +               status = chip->waitfunc(mtd, chip);
2941 +               if (status & NAND_STATUS_FAIL) {
2942 +                       printk(KERN_INFO "status: %d\n", status);
2943 +                       return -EIO;
2944 +               }
2945 +               len -= write_len;
2946 +               sector++;
2947 +       }
2948 +
2949 +       return 0;
2950 +}
2951 +
2952 +static int
2953 +mtk_nand_write_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page)
2954 +{
2955 +       int i, iter;
2956 +       int sec_num = 1<<(chip->page_shift-9);
2957 +       int spare_per_sector = mtd->oobsize/sec_num;
2958 +
2959 +       memcpy(local_oob_buf, chip->oob_poi, mtd->oobsize);
2960 +
2961 +       // copy ecc data
2962 +       for (i = 0; i < layout->eccbytes; i++) {
2963 +               iter = (i / (spare_per_sector-OOB_AVAI_PER_SECTOR)) *  spare_per_sector + OOB_AVAI_PER_SECTOR + i % (spare_per_sector-OOB_AVAI_PER_SECTOR);
2964 +               local_oob_buf[iter] = chip->oob_poi[layout->eccpos[i]];
2965 +       }
2966 +
2967 +       // copy FDM data
2968 +       for (i = 0; i < sec_num; i++)
2969 +               memcpy(&local_oob_buf[i * spare_per_sector], &chip->oob_poi[i * OOB_AVAI_PER_SECTOR], OOB_AVAI_PER_SECTOR);
2970 +
2971 +       return mtk_nand_write_oob_raw(mtd, local_oob_buf, page, mtd->oobsize);
2972 +}
2973 +
2974 +static int mtk_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
2975 +{
2976 +       int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
2977 +       int block = page / page_per_block;
2978 +       u16 page_in_block = page % page_per_block;
2979 +       int mapped_block = block;
2980 +
2981 +#if defined(MTK_NAND_BMT)
2982 +       mapped_block = get_mapping_block_index(block);
2983 +       // write bad index into oob
2984 +       if (mapped_block != block)
2985 +               set_bad_index_to_oob(chip->oob_poi, block);
2986 +       else
2987 +               set_bad_index_to_oob(chip->oob_poi, FAKE_INDEX);
2988 +#else
2989 +       if (shift_on_bbt)
2990 +       {
2991 +               mapped_block = block_remap(mtd, block);
2992 +               if (mapped_block == -1)
2993 +                       return NAND_STATUS_FAIL;
2994 +               if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
2995 +                       return NAND_STATUS_FAIL;
2996 +       }
2997 +#endif
2998 +       do {
2999 +               if (mtk_nand_write_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block /* page */)) {
3000 +                       MSG(INIT, "write oob fail at block: 0x%x, page: 0x%x\n", mapped_block, page_in_block);
3001 +#if defined(MTK_NAND_BMT)
3002 +                       if (update_bmt((page_in_block + mapped_block * page_per_block) << chip->page_shift,
3003 +                                       UPDATE_WRITE_FAIL, NULL, chip->oob_poi))
3004 +                       {
3005 +                               MSG(INIT, "Update BMT success\n");
3006 +                               return 0;
3007 +                       } else {
3008 +                               MSG(INIT, "Update BMT fail\n");
3009 +                               return -EIO;
3010 +                       }
3011 +#else
3012 +                       mtk_nand_block_markbad_hw(mtd, (page_in_block + mapped_block * page_per_block) << chip->page_shift);
3013 +                       nand_bbt_set(mtd, page_in_block + mapped_block * page_per_block, 0x3);
3014 +                       if (shift_on_bbt) {
3015 +                               mapped_block = block_remap(mtd, mapped_block);
3016 +                               if (mapped_block == -1)
3017 +                                       return NAND_STATUS_FAIL;
3018 +                               if (nand_bbt_get(mtd, mapped_block << (chip->phys_erase_shift - chip->page_shift)) != 0x0)
3019 +                                       return NAND_STATUS_FAIL;
3020 +                       } else {
3021 +                               return NAND_STATUS_FAIL;
3022 +                       }
3023 +#endif
3024 +               } else
3025 +                       break;
3026 +       } while (1);
3027 +
3028 +       return 0;
3029 +}
3030 +
3031 +int
3032 +mtk_nand_block_markbad_hw(struct mtd_info *mtd, loff_t offset)
3033 +{
3034 +       struct nand_chip *chip = mtd->priv;
3035 +       int block = (int)offset >> chip->phys_erase_shift;
3036 +       int page = block * (1 << (chip->phys_erase_shift - chip->page_shift));
3037 +       u8 buf[8];
3038 +
3039 +       memset(buf, 0xFF, 8);
3040 +       buf[0] = 0;
3041 +       return  mtk_nand_write_oob_raw(mtd, buf, page, 8);
3042 +}
3043 +
3044 +static int
3045 +mtk_nand_block_markbad(struct mtd_info *mtd, loff_t offset)
3046 +{
3047 +       struct nand_chip *chip = mtd->priv;
3048 +       int block = (int)offset >> chip->phys_erase_shift;
3049 +       int ret;
3050 +       int mapped_block = block;
3051 +
3052 +       nand_get_device(chip, mtd, FL_WRITING);
3053 +
3054 +#if defined(MTK_NAND_BMT)
3055 +       mapped_block = get_mapping_block_index(block);
3056 +       ret = mtk_nand_block_markbad_hw(mtd, mapped_block << chip->phys_erase_shift);
3057 +#else
3058 +       if (shift_on_bbt) {
3059 +               mapped_block = block_remap(mtd, block);
3060 +               if (mapped_block == -1) {
3061 +                       printk("NAND mark bad failed\n");
3062 +                       nand_release_device(mtd);
3063 +                       return NAND_STATUS_FAIL;
3064 +               }
3065 +       }
3066 +       ret = mtk_nand_block_markbad_hw(mtd, mapped_block << chip->phys_erase_shift);
3067 +#endif
3068 +       nand_release_device(mtd);
3069 +
3070 +       return ret;
3071 +}
3072 +
3073 +int
3074 +mtk_nand_read_oob_hw(struct mtd_info *mtd, struct nand_chip *chip, int page)
3075 +{
3076 +       int i;
3077 +       u8 iter = 0;
3078 +
3079 +       int sec_num = 1<<(chip->page_shift-9);
3080 +       int spare_per_sector = mtd->oobsize/sec_num;
3081 +
3082 +       if (mtk_nand_read_oob_raw(mtd, chip->oob_poi, page, mtd->oobsize)) {
3083 +               printk(KERN_ERR "[%s]mtk_nand_read_oob_raw return failed\n", __FUNCTION__);
3084 +               return -EIO;
3085 +       }
3086 +
3087 +       // adjust to ecc physical layout to memory layout
3088 +       /*********************************************************/
3089 +       /* FDM0 | ECC0 | FDM1 | ECC1 | FDM2 | ECC2 | FDM3 | ECC3 */
3090 +       /*  8B  |  8B  |  8B  |  8B  |  8B  |  8B  |  8B  |  8B  */
3091 +       /*********************************************************/
3092 +
3093 +       memcpy(local_oob_buf, chip->oob_poi, mtd->oobsize);
3094 +       // copy ecc data
3095 +       for (i = 0; i < layout->eccbytes; i++) {
3096 +               iter = (i / (spare_per_sector-OOB_AVAI_PER_SECTOR)) *  spare_per_sector + OOB_AVAI_PER_SECTOR + i % (spare_per_sector-OOB_AVAI_PER_SECTOR);
3097 +               chip->oob_poi[layout->eccpos[i]] = local_oob_buf[iter];
3098 +       }
3099 +
3100 +       // copy FDM data
3101 +       for (i = 0; i < sec_num; i++) {
3102 +               memcpy(&chip->oob_poi[i * OOB_AVAI_PER_SECTOR], &local_oob_buf[i *  spare_per_sector], OOB_AVAI_PER_SECTOR);
3103 +       }
3104 +
3105 +       return 0;
3106 +}
3107 +
3108 +static int
3109 +mtk_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
3110 +{
3111 +       int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
3112 +       int block = page / page_per_block;
3113 +       u16 page_in_block = page % page_per_block;
3114 +       int mapped_block = block;
3115 +
3116 +#if defined (MTK_NAND_BMT)
3117 +       mapped_block = get_mapping_block_index(block);
3118 +       mtk_nand_read_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block);
3119 +#else
3120 +       if (shift_on_bbt) {
3121 +               mapped_block = block_remap(mtd, block);
3122 +               if (mapped_block == -1)
3123 +                       return NAND_STATUS_FAIL;
3124 +               // allow to read oob even if the block is bad
3125 +       }
3126 +       if (mtk_nand_read_oob_hw(mtd, chip, page_in_block + mapped_block * page_per_block)!=0)
3127 +               return -1;
3128 +#endif
3129 +       return 0;
3130 +}
3131 +
3132 +int
3133 +mtk_nand_block_bad_hw(struct mtd_info *mtd, loff_t ofs)
3134 +{
3135 +       struct nand_chip *chip = (struct nand_chip *)mtd->priv;
3136 +       int page_addr = (int)(ofs >> chip->page_shift);
3137 +       unsigned int page_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
3138 +       unsigned char oob_buf[8];
3139 +
3140 +       page_addr &= ~(page_per_block - 1);
3141 +       if (mtk_nand_read_oob_raw(mtd, oob_buf, page_addr, sizeof(oob_buf))) {
3142 +               printk(KERN_WARNING "mtk_nand_read_oob_raw return error\n");
3143 +               return 1;
3144 +       }
3145 +
3146 +       if (oob_buf[0] != 0xff) {
3147 +               printk(KERN_WARNING "Bad block detected at 0x%x, oob_buf[0] is 0x%x\n", page_addr, oob_buf[0]);
3148 +               // dump_nfi();
3149 +               return 1;
3150 +       }
3151 +
3152 +       return 0;
3153 +}
3154 +
3155 +static int
3156 +mtk_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
3157 +{
3158 +       struct nand_chip *chip = (struct nand_chip *)mtd->priv;
3159 +       int block = (int)ofs >> chip->phys_erase_shift;
3160 +       int mapped_block = block;
3161 +       int ret;
3162 +
3163 +#if defined(MTK_NAND_BMT)
3164 +       mapped_block = get_mapping_block_index(block);
3165 +#else
3166 +       if (shift_on_bbt) {
3167 +               mapped_block = block_remap(mtd, block);
3168 +       }
3169 +#endif
3170 +
3171 +       ret = mtk_nand_block_bad_hw(mtd, mapped_block << chip->phys_erase_shift);
3172 +#if defined (MTK_NAND_BMT)
3173 +       if (ret) {
3174 +               MSG(INIT, "Unmapped bad block: 0x%x\n", mapped_block);
3175 +               if (update_bmt(mapped_block << chip->phys_erase_shift, UPDATE_UNMAPPED_BLOCK, NULL, NULL)) {
3176 +                       MSG(INIT, "Update BMT success\n");
3177 +                       ret = 0;
3178 +               } else {
3179 +                       MSG(INIT, "Update BMT fail\n");
3180 +                       ret = 1;
3181 +               }
3182 +       }
3183 +#endif
3184 +
3185 +       return ret;
3186 +}
3187 +
3188 +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
3189 +char gacBuf[4096 + 288];
3190 +
3191 +static int
3192 +mtk_nand_verify_buf(struct mtd_info *mtd, const uint8_t * buf, int len)
3193 +{
3194 +       struct nand_chip *chip = (struct nand_chip *)mtd->priv;
3195 +       struct NAND_CMD *pkCMD = &g_kCMD;
3196 +       u32 u4PageSize = mtd->writesize;
3197 +       u32 *pSrc, *pDst;
3198 +       int i;
3199 +
3200 +       mtk_nand_exec_read_page(mtd, pkCMD->u4RowAddr, u4PageSize, gacBuf, gacBuf + u4PageSize);
3201 +
3202 +       pSrc = (u32 *) buf;
3203 +       pDst = (u32 *) gacBuf;
3204 +       len = len / sizeof(u32);
3205 +       for (i = 0; i < len; ++i) {
3206 +               if (*pSrc != *pDst) {
3207 +                       MSG(VERIFY, "mtk_nand_verify_buf page fail at page %d\n", pkCMD->u4RowAddr);
3208 +                       return -1;
3209 +               }
3210 +               pSrc++;
3211 +               pDst++;
3212 +       }
3213 +
3214 +       pSrc = (u32 *) chip->oob_poi;
3215 +       pDst = (u32 *) (gacBuf + u4PageSize);
3216 +
3217 +       if ((pSrc[0] != pDst[0]) || (pSrc[1] != pDst[1]) || (pSrc[2] != pDst[2]) || (pSrc[3] != pDst[3]) || (pSrc[4] != pDst[4]) || (pSrc[5] != pDst[5])) {
3218 +       // TODO: Ask Designer Why?
3219 +       //(pSrc[6] != pDst[6]) || (pSrc[7] != pDst[7]))
3220 +               MSG(VERIFY, "mtk_nand_verify_buf oob fail at page %d\n", pkCMD->u4RowAddr);
3221 +               MSG(VERIFY, "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", pSrc[0], pSrc[1], pSrc[2], pSrc[3], pSrc[4], pSrc[5], pSrc[6], pSrc[7]);
3222 +               MSG(VERIFY, "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", pDst[0], pDst[1], pDst[2], pDst[3], pDst[4], pDst[5], pDst[6], pDst[7]);
3223 +               return -1;
3224 +       }
3225 +       return 0;
3226 +}
3227 +#endif
3228 +
3229 +static void
3230 +mtk_nand_init_hw(struct mtk_nand_host *host) {
3231 +       struct mtk_nand_host_hw *hw = host->hw;
3232 +       u32 data;
3233 +
3234 +       data = DRV_Reg32(RALINK_SYSCTL_BASE+0x60);
3235 +       data &= ~((0x3<<18)|(0x3<<16));
3236 +       data |= ((0x2<<18) |(0x2<<16));
3237 +       DRV_WriteReg32(RALINK_SYSCTL_BASE+0x60, data);
3238 +
3239 +       MSG(INIT, "Enable NFI Clock\n");
3240 +       nand_enable_clock();
3241 +
3242 +       g_bInitDone = false;
3243 +       g_kCMD.u4OOBRowAddr = (u32) - 1;
3244 +
3245 +       /* Set default NFI access timing control */
3246 +       DRV_WriteReg32(NFI_ACCCON_REG32, hw->nfi_access_timing);
3247 +       DRV_WriteReg16(NFI_CNFG_REG16, 0);
3248 +       DRV_WriteReg16(NFI_PAGEFMT_REG16, 0);
3249 +
3250 +       /* Reset the state machine and data FIFO, because flushing FIFO */
3251 +       (void)mtk_nand_reset();
3252 +
3253 +       /* Set the ECC engine */
3254 +       if (hw->nand_ecc_mode == NAND_ECC_HW) {
3255 +               MSG(INIT, "%s : Use HW ECC\n", MODULE_NAME);
3256 +               if (g_bHwEcc)
3257 +                       NFI_SET_REG32(NFI_CNFG_REG16, CNFG_HW_ECC_EN);
3258 +               ECC_Config(host->hw,4);
3259 +               mtk_nand_configure_fdm(8);
3260 +               mtk_nand_configure_lock();
3261 +       }
3262 +
3263 +       NFI_SET_REG16(NFI_IOCON_REG16, 0x47);
3264 +}
3265 +
3266 +static int mtk_nand_dev_ready(struct mtd_info *mtd)
3267 +{
3268 +       return !(DRV_Reg32(NFI_STA_REG32) & STA_NAND_BUSY);
3269 +}
3270 +
3271 +#define FACT_BBT_BLOCK_NUM  32 // use the latest 32 BLOCK for factory bbt table
3272 +#define FACT_BBT_OOB_SIGNATURE  1
3273 +#define FACT_BBT_SIGNATURE_LEN  7
3274 +const u8 oob_signature[] = "mtknand";
3275 +static u8 *fact_bbt = 0;
3276 +static u32 bbt_size = 0;
3277 +
3278 +static int
3279 +read_fact_bbt(struct mtd_info *mtd, unsigned int page)
3280 +{
3281 +       struct nand_chip *chip = mtd->priv;
3282 +
3283 +       // read oob
3284 +       if (mtk_nand_read_oob_hw(mtd, chip, page)==0)
3285 +       {
3286 +               if (chip->oob_poi[nand_badblock_offset] != 0xFF)
3287 +               {
3288 +                       printk("Bad Block on Page %x\n", page);
3289 +                       return -1;
3290 +               }
3291 +               if (memcmp(&chip->oob_poi[FACT_BBT_OOB_SIGNATURE], oob_signature, FACT_BBT_SIGNATURE_LEN) != 0)
3292 +               {
3293 +                       printk("compare signature failed %x\n", page);
3294 +                       return -1;
3295 +               }
3296 +               if (mtk_nand_exec_read_page(mtd, page, mtd->writesize, chip->buffers->databuf, chip->oob_poi))
3297 +               {
3298 +                       printk("Signature matched and data read!\n");
3299 +                       memcpy(fact_bbt, chip->buffers->databuf, (bbt_size <= mtd->writesize)? bbt_size:mtd->writesize);
3300 +                       return 0;
3301 +               }
3302 +
3303 +       }
3304 +       printk("failed at page %x\n", page);
3305 +       return -1;
3306 +}
3307 +
3308 +static int
3309 +load_fact_bbt(struct mtd_info *mtd)
3310 +{
3311 +       struct nand_chip *chip = mtd->priv;
3312 +       int i;
3313 +       u32 total_block;
3314 +
3315 +       total_block = 1 << (chip->chip_shift - chip->phys_erase_shift);
3316 +       bbt_size = total_block >> 2;
3317 +
3318 +       if ((!fact_bbt) && (bbt_size))
3319 +               fact_bbt = (u8 *)kmalloc(bbt_size, GFP_KERNEL);
3320 +       if (!fact_bbt)
3321 +               return -1;
3322 +
3323 +       for (i = total_block - 1; i >= (total_block - FACT_BBT_BLOCK_NUM); i--)
3324 +       {
3325 +               if (read_fact_bbt(mtd, i << (chip->phys_erase_shift - chip->page_shift)) == 0)
3326 +               {
3327 +                       printk("load_fact_bbt success %d\n", i);
3328 +                       return 0;
3329 +               }
3330 +
3331 +       }
3332 +       printk("load_fact_bbt failed\n");
3333 +       return -1;
3334 +}
3335 +
3336 +static int oob_mtk_ooblayout_ecc(struct mtd_info *mtd, int section,
3337 +                               struct mtd_oob_region *oobregion)
3338 +{
3339 +       oobregion->length = 8;
3340 +       oobregion->offset = layout->eccpos[section * 8];
3341 +
3342 +       return 0;
3343 +}
3344 +
3345 +static int oob_mtk_ooblayout_free(struct mtd_info *mtd, int section,
3346 +                                struct mtd_oob_region *oobregion)
3347 +{
3348 +       if (section >= (layout->eccbytes / 8)) {
3349 +               return -ERANGE;
3350 +       }
3351 +       oobregion->offset = layout->oobfree[section].offset;
3352 +       oobregion->length = layout->oobfree[section].length;
3353 +
3354 +       return 0;
3355 +}
3356 +
3357 +
3358 +static const struct mtd_ooblayout_ops oob_mtk_ops = {
3359 +       .ecc = oob_mtk_ooblayout_ecc,
3360 +       .free = oob_mtk_ooblayout_free,
3361 +};
3362 +
3363 +static int
3364 +mtk_nand_probe(struct platform_device *pdev)
3365 +{
3366 +       struct mtd_part_parser_data ppdata;
3367 +       struct mtk_nand_host_hw *hw;
3368 +       struct nand_chip *nand_chip;
3369 +       struct mtd_info *mtd;
3370 +       u8 ext_id1, ext_id2, ext_id3;
3371 +       int err = 0;
3372 +       int id;
3373 +       u32 ext_id;
3374 +       int i;
3375 +       u32 data;
3376 +
3377 +       data = DRV_Reg32(RALINK_SYSCTL_BASE+0x60);
3378 +       data &= ~((0x3<<18)|(0x3<<16));
3379 +       data |= ((0x2<<18) |(0x2<<16));
3380 +       DRV_WriteReg32(RALINK_SYSCTL_BASE+0x60, data);
3381 +
3382 +       hw = &mt7621_nand_hw;
3383 +       BUG_ON(!hw);
3384 +       /* Allocate memory for the device structure (and zero it) */
3385 +       host = kzalloc(sizeof(struct mtk_nand_host), GFP_KERNEL);
3386 +       if (!host) {
3387 +               MSG(INIT, "mtk_nand: failed to allocate device structure.\n");
3388 +               return -ENOMEM;
3389 +       }
3390 +
3391 +       /* Allocate memory for 16 byte aligned buffer */
3392 +       local_buffer_16_align = local_buffer + 16 - ((u32) local_buffer % 16);
3393 +       printk(KERN_INFO "Allocate 16 byte aligned buffer: %p\n", local_buffer_16_align);
3394 +       host->hw = hw;
3395 +
3396 +       /* init mtd data structure */
3397 +       nand_chip = &host->nand_chip;
3398 +       nand_chip->priv = host;     /* link the private data structures */
3399 +
3400 +       mtd = host->mtd = &nand_chip->mtd;
3401 +       mtd->priv = nand_chip;
3402 +       mtd->owner = THIS_MODULE;
3403 +       mtd->name  = "MT7621-NAND";
3404 +
3405 +       hw->nand_ecc_mode = NAND_ECC_HW;
3406 +
3407 +       /* Set address of NAND IO lines */
3408 +       nand_chip->IO_ADDR_R = (void __iomem *)NFI_DATAR_REG32;
3409 +       nand_chip->IO_ADDR_W = (void __iomem *)NFI_DATAW_REG32;
3410 +       nand_chip->chip_delay = 20; /* 20us command delay time */
3411 +       nand_chip->ecc.mode = hw->nand_ecc_mode;    /* enable ECC */
3412 +       nand_chip->ecc.strength = 1;
3413 +       nand_chip->read_byte = mtk_nand_read_byte;
3414 +       nand_chip->read_buf = mtk_nand_read_buf;
3415 +       nand_chip->write_buf = mtk_nand_write_buf;
3416 +#ifdef CONFIG_MTD_NAND_VERIFY_WRITE
3417 +       nand_chip->verify_buf = mtk_nand_verify_buf;
3418 +#endif
3419 +       nand_chip->select_chip = mtk_nand_select_chip;
3420 +       nand_chip->dev_ready = mtk_nand_dev_ready;
3421 +       nand_chip->cmdfunc = mtk_nand_command_bp;
3422 +       nand_chip->ecc.read_page = mtk_nand_read_page_hwecc;
3423 +       nand_chip->ecc.write_page = mtk_nand_write_page_hwecc;
3424 +
3425 +       mtd_set_ooblayout(mtd, &oob_mtk_ops);
3426 +       nand_chip->ecc.size = hw->nand_ecc_size;    //2048
3427 +       nand_chip->ecc.bytes = hw->nand_ecc_bytes;  //32
3428 +
3429 +       // For BMT, we need to revise driver architecture
3430 +       nand_chip->write_page = mtk_nand_write_page;
3431 +       nand_chip->ecc.write_oob = mtk_nand_write_oob;
3432 +       nand_chip->block_markbad = mtk_nand_block_markbad;   // need to add nand_get_device()/nand_release_device().
3433 +       nand_chip->erase_mtk = mtk_nand_erase;
3434 +       nand_chip->read_page = mtk_nand_read_page;
3435 +       nand_chip->ecc.read_oob = mtk_nand_read_oob;
3436 +       nand_chip->block_bad = mtk_nand_block_bad;
3437 +        nand_chip->cmd_ctrl = mtk_nfc_cmd_ctrl;
3438 +
3439 +       //Qwert:Add for Uboot
3440 +       mtk_nand_init_hw(host);
3441 +       /* Select the device */
3442 +       nand_chip->select_chip(mtd, NFI_DEFAULT_CS);
3443 +
3444 +       /*
3445 +       * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
3446 +       * after power-up
3447 +       */
3448 +       nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
3449 +
3450 +       memset(&devinfo, 0 , sizeof(flashdev_info));
3451 +
3452 +       /* Send the command for reading device ID */
3453 +
3454 +       nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
3455 +
3456 +       /* Read manufacturer and device IDs */
3457 +       manu_id = nand_chip->read_byte(mtd);
3458 +       dev_id = nand_chip->read_byte(mtd);
3459 +       id = dev_id | (manu_id << 8);
3460 +               ext_id1 = nand_chip->read_byte(mtd);
3461 +                   ext_id2 = nand_chip->read_byte(mtd);
3462 +                       ext_id3 = nand_chip->read_byte(mtd);
3463 +                           ext_id = ext_id1 << 16 | ext_id2 << 8 | ext_id3;
3464 +       if (!get_device_info(id, ext_id, &devinfo)) {
3465 +               u32 chip_mode = RALINK_REG(RALINK_SYSCTL_BASE+0x010)&0x0F;
3466 +               MSG(INIT, "Not Support this Device! \r\n");
3467 +               memset(&devinfo, 0 , sizeof(flashdev_info));
3468 +               MSG(INIT, "chip_mode=%08X\n",chip_mode);
3469 +
3470 +               /* apply bootstrap first */
3471 +               devinfo.addr_cycle = 5;
3472 +               devinfo.iowidth = 8;
3473 +
3474 +               switch (chip_mode) {
3475 +               case 10:
3476 +                       devinfo.pagesize = 2048;
3477 +                       devinfo.sparesize = 128;
3478 +                       devinfo.totalsize = 128;
3479 +                       devinfo.blocksize = 128;
3480 +                       break;
3481 +               case 11:
3482 +                       devinfo.pagesize = 4096;
3483 +                       devinfo.sparesize = 128;
3484 +                       devinfo.totalsize = 1024;
3485 +                       devinfo.blocksize = 256;
3486 +                       break;
3487 +               case 12:
3488 +                       devinfo.pagesize = 4096;
3489 +                       devinfo.sparesize = 224;
3490 +                       devinfo.totalsize = 2048;
3491 +                       devinfo.blocksize = 512;
3492 +                       break;
3493 +               default:
3494 +               case 1:
3495 +                       devinfo.pagesize = 2048;
3496 +                       devinfo.sparesize = 64;
3497 +                       devinfo.totalsize = 128;
3498 +                       devinfo.blocksize = 128;
3499 +                       break;
3500 +               }
3501 +
3502 +               devinfo.timmingsetting = NFI_DEFAULT_ACCESS_TIMING;
3503 +               devinfo.devciename[0] = 'U';
3504 +               devinfo.advancedmode = 0;
3505 +       }
3506 +       mtd->writesize = devinfo.pagesize;
3507 +       mtd->erasesize = (devinfo.blocksize<<10);
3508 +       mtd->oobsize = devinfo.sparesize;
3509 +
3510 +       nand_chip->chipsize = (devinfo.totalsize<<20);
3511 +       nand_chip->page_shift = ffs(mtd->writesize) - 1;
3512 +       nand_chip->pagemask = (nand_chip->chipsize >> nand_chip->page_shift) - 1;
3513 +       nand_chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
3514 +       nand_chip->chip_shift = ffs(nand_chip->chipsize) - 1;//0x1C;//ffs(nand_chip->chipsize) - 1;
3515 +        nand_chip->cmd_ctrl = mtk_nfc_cmd_ctrl;
3516 +
3517 +       /* allocate buffers or call select_chip here or a bit earlier*/
3518 +       {
3519 +               struct nand_buffers *nbuf = kzalloc(sizeof(*nbuf) + mtd->writesize + mtd->oobsize * 3, GFP_KERNEL);
3520 +               if (!nbuf) {
3521 +                       return -ENOMEM;
3522 +               }
3523 +               nbuf->ecccalc = (uint8_t *)(nbuf + 1);
3524 +               nbuf->ecccode = nbuf->ecccalc + mtd->oobsize;
3525 +               nbuf->databuf = nbuf->ecccode + mtd->oobsize;
3526 +
3527 +               nand_chip->buffers = nbuf;
3528 +               nand_chip->options |= NAND_OWN_BUFFERS;
3529 +       }
3530 +
3531 +       nand_chip->oob_poi = nand_chip->buffers->databuf + mtd->writesize;
3532 +       nand_chip->badblockpos = 0;
3533 +
3534 +       if (devinfo.pagesize == 4096)
3535 +               layout = &nand_oob_128;
3536 +       else if (devinfo.pagesize == 2048)
3537 +               layout = &nand_oob_64;
3538 +       else if (devinfo.pagesize == 512)
3539 +               layout = &nand_oob_16;
3540 +
3541 +       layout->eccbytes = devinfo.sparesize-OOB_AVAI_PER_SECTOR*(devinfo.pagesize/NAND_SECTOR_SIZE);
3542 +       for (i = 0; i < layout->eccbytes; i++)
3543 +               layout->eccpos[i]=OOB_AVAI_PER_SECTOR*(devinfo.pagesize/NAND_SECTOR_SIZE)+i;
3544 +
3545 +       MSG(INIT, "Support this Device in MTK table! %x \r\n", id);
3546 +       hw->nfi_bus_width = devinfo.iowidth;
3547 +       DRV_WriteReg32(NFI_ACCCON_REG32, devinfo.timmingsetting);
3548 +
3549 +       /* 16-bit bus width */
3550 +       if (hw->nfi_bus_width == 16) {
3551 +               MSG(INIT, "%s : Set the 16-bit I/O settings!\n", MODULE_NAME);
3552 +               nand_chip->options |= NAND_BUSWIDTH_16;
3553 +       }
3554 +       mtd->oobsize = devinfo.sparesize;
3555 +       hw->nfi_cs_num = 1;
3556 +
3557 +       /* Scan to find existance of the device */
3558 +       if (nand_scan(mtd, hw->nfi_cs_num)) {
3559 +               MSG(INIT, "%s : nand_scan fail.\n", MODULE_NAME);
3560 +               err = -ENXIO;
3561 +               goto out;
3562 +       }
3563 +
3564 +       g_page_size = mtd->writesize;
3565 +       platform_set_drvdata(pdev, host);
3566 +       if (hw->nfi_bus_width == 16) {
3567 +               NFI_SET_REG16(NFI_PAGEFMT_REG16, PAGEFMT_DBYTE_EN);
3568 +       }
3569 +
3570 +       nand_chip->select_chip(mtd, 0);
3571 +#if defined(MTK_NAND_BMT)
3572 +       nand_chip->chipsize -= (BMT_POOL_SIZE) << nand_chip->phys_erase_shift;
3573 +#endif
3574 +       mtd->size = nand_chip->chipsize;
3575 +
3576 +       CFG_BLOCKSIZE = mtd->erasesize;
3577 +
3578 +#if defined(MTK_NAND_BMT)
3579 +       if (!g_bmt) {
3580 +               if (!(g_bmt = init_bmt(nand_chip, BMT_POOL_SIZE))) {
3581 +                       MSG(INIT, "Error: init bmt failed\n");
3582 +                       return 0;
3583 +               }
3584 +       }
3585 +#endif
3586 +
3587 +       nand_set_flash_node(nand_chip, pdev->dev.of_node);
3588 +       err = mtd_device_parse_register(mtd, probe_types, &ppdata,
3589 +                                       NULL, 0);
3590 +       if (!err) {
3591 +               MSG(INIT, "[mtk_nand] probe successfully!\n");
3592 +               nand_disable_clock();
3593 +               shift_on_bbt = 1;
3594 +               if (load_fact_bbt(mtd) == 0) {
3595 +                       int i;
3596 +                       for (i = 0; i < 0x100; i++)
3597 +                               nand_chip->bbt[i] |= fact_bbt[i];
3598 +               }
3599 +
3600 +               return err;
3601 +       }
3602 +
3603 +out:
3604 +       MSG(INIT, "[NFI] mtk_nand_probe fail, err = %d!\n", err);
3605 +       nand_release(mtd);
3606 +       platform_set_drvdata(pdev, NULL);
3607 +       if ( NULL != nand_chip->buffers) {
3608 +               kfree(nand_chip->buffers);
3609 +       }
3610 +       kfree(host);
3611 +       nand_disable_clock();
3612 +       return err;
3613 +}
3614 +
3615 +static int
3616 +mtk_nand_remove(struct platform_device *pdev)
3617 +{
3618 +       struct mtk_nand_host *host = platform_get_drvdata(pdev);
3619 +       struct mtd_info *mtd = host->mtd;
3620 +       struct nand_chip *nand_chip = &host->nand_chip;
3621 +
3622 +       nand_release(mtd);
3623 +       if ( NULL != nand_chip->buffers) {
3624 +               kfree(nand_chip->buffers);
3625 +       }
3626 +       kfree(host);
3627 +       nand_disable_clock();
3628 +
3629 +       return 0;
3630 +}
3631 +
3632 +static const struct of_device_id mt7621_nand_match[] = {
3633 +       { .compatible = "mtk,mt7621-nand" },
3634 +       {},
3635 +};
3636 +MODULE_DEVICE_TABLE(of, mt7621_nand_match);
3637 +
3638 +static struct platform_driver mtk_nand_driver = {
3639 +       .probe = mtk_nand_probe,
3640 +       .remove = mtk_nand_remove,
3641 +       .driver = {
3642 +               .name = "MT7621-NAND",
3643 +               .owner = THIS_MODULE,
3644 +               .of_match_table = mt7621_nand_match,
3645 +       },
3646 +};
3647 +
3648 +static int __init
3649 +mtk_nand_init(void)
3650 +{
3651 +       printk("MediaTek Nand driver init, version %s\n", VERSION);
3652 +
3653 +       return platform_driver_register(&mtk_nand_driver);
3654 +}
3655 +
3656 +static void __exit
3657 +mtk_nand_exit(void)
3658 +{
3659 +       platform_driver_unregister(&mtk_nand_driver);
3660 +}
3661 +
3662 +module_init(mtk_nand_init);
3663 +module_exit(mtk_nand_exit);
3664 +MODULE_LICENSE("GPL");
3665 --- /dev/null
3666 +++ b/drivers/mtd/nand/mtk_nand2.h
3667 @@ -0,0 +1,452 @@
3668 +#ifndef __MTK_NAND_H
3669 +#define __MTK_NAND_H
3670 +
3671 +#define RALINK_NAND_CTRL_BASE         0xBE003000
3672 +#define RALINK_SYSCTL_BASE            0xBE000000
3673 +#define RALINK_NANDECC_CTRL_BASE      0xBE003800
3674 +/*******************************************************************************
3675 + * NFI Register Definition
3676 + *******************************************************************************/
3677 +
3678 +#define NFI_CNFG_REG16         ((volatile P_U16)(NFI_BASE+0x0000))
3679 +#define NFI_PAGEFMT_REG16   ((volatile P_U16)(NFI_BASE+0x0004))
3680 +#define NFI_CON_REG16          ((volatile P_U16)(NFI_BASE+0x0008))
3681 +#define NFI_ACCCON_REG32       ((volatile P_U32)(NFI_BASE+0x000C))
3682 +#define NFI_INTR_EN_REG16   ((volatile P_U16)(NFI_BASE+0x0010))
3683 +#define NFI_INTR_REG16      ((volatile P_U16)(NFI_BASE+0x0014))
3684 +
3685 +#define NFI_CMD_REG16          ((volatile P_U16)(NFI_BASE+0x0020))
3686 +
3687 +#define NFI_ADDRNOB_REG16   ((volatile P_U16)(NFI_BASE+0x0030))
3688 +#define NFI_COLADDR_REG32      ((volatile P_U32)(NFI_BASE+0x0034))
3689 +#define NFI_ROWADDR_REG32      ((volatile P_U32)(NFI_BASE+0x0038))
3690 +
3691 +#define NFI_STRDATA_REG16   ((volatile P_U16)(NFI_BASE+0x0040))
3692 +
3693 +#define NFI_DATAW_REG32        ((volatile P_U32)(NFI_BASE+0x0050))
3694 +#define NFI_DATAR_REG32        ((volatile P_U32)(NFI_BASE+0x0054))
3695 +#define NFI_PIO_DIRDY_REG16 ((volatile P_U16)(NFI_BASE+0x0058))
3696 +
3697 +#define NFI_STA_REG32          ((volatile P_U32)(NFI_BASE+0x0060))
3698 +#define NFI_FIFOSTA_REG16   ((volatile P_U16)(NFI_BASE+0x0064))
3699 +#define NFI_LOCKSTA_REG16   ((volatile P_U16)(NFI_BASE+0x0068))
3700 +
3701 +#define NFI_ADDRCNTR_REG16  ((volatile P_U16)(NFI_BASE+0x0070))
3702 +
3703 +#define NFI_STRADDR_REG32      ((volatile P_U32)(NFI_BASE+0x0080))
3704 +#define NFI_BYTELEN_REG16   ((volatile P_U16)(NFI_BASE+0x0084))
3705 +
3706 +#define NFI_CSEL_REG16      ((volatile P_U16)(NFI_BASE+0x0090))
3707 +#define NFI_IOCON_REG16     ((volatile P_U16)(NFI_BASE+0x0094))
3708 +
3709 +#define NFI_FDM0L_REG32        ((volatile P_U32)(NFI_BASE+0x00A0))
3710 +#define NFI_FDM0M_REG32        ((volatile P_U32)(NFI_BASE+0x00A4))
3711 +
3712 +#define NFI_LOCK_REG16         ((volatile P_U16)(NFI_BASE+0x0100))
3713 +#define NFI_LOCKCON_REG32      ((volatile P_U32)(NFI_BASE+0x0104))
3714 +#define NFI_LOCKANOB_REG16  ((volatile P_U16)(NFI_BASE+0x0108))
3715 +#define NFI_LOCK00ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0110))
3716 +#define NFI_LOCK00FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0114))
3717 +#define NFI_LOCK01ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0118))
3718 +#define NFI_LOCK01FMT_REG32 ((volatile P_U32)(NFI_BASE+0x011C))
3719 +#define NFI_LOCK02ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0120))
3720 +#define NFI_LOCK02FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0124))
3721 +#define NFI_LOCK03ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0128))
3722 +#define NFI_LOCK03FMT_REG32 ((volatile P_U32)(NFI_BASE+0x012C))
3723 +#define NFI_LOCK04ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0130))
3724 +#define NFI_LOCK04FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0134))
3725 +#define NFI_LOCK05ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0138))
3726 +#define NFI_LOCK05FMT_REG32 ((volatile P_U32)(NFI_BASE+0x013C))
3727 +#define NFI_LOCK06ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0140))
3728 +#define NFI_LOCK06FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0144))
3729 +#define NFI_LOCK07ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0148))
3730 +#define NFI_LOCK07FMT_REG32 ((volatile P_U32)(NFI_BASE+0x014C))
3731 +#define NFI_LOCK08ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0150))
3732 +#define NFI_LOCK08FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0154))
3733 +#define NFI_LOCK09ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0158))
3734 +#define NFI_LOCK09FMT_REG32 ((volatile P_U32)(NFI_BASE+0x015C))
3735 +#define NFI_LOCK10ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0160))
3736 +#define NFI_LOCK10FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0164))
3737 +#define NFI_LOCK11ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0168))
3738 +#define NFI_LOCK11FMT_REG32 ((volatile P_U32)(NFI_BASE+0x016C))
3739 +#define NFI_LOCK12ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0170))
3740 +#define NFI_LOCK12FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0174))
3741 +#define NFI_LOCK13ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0178))
3742 +#define NFI_LOCK13FMT_REG32 ((volatile P_U32)(NFI_BASE+0x017C))
3743 +#define NFI_LOCK14ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0180))
3744 +#define NFI_LOCK14FMT_REG32 ((volatile P_U32)(NFI_BASE+0x0184))
3745 +#define NFI_LOCK15ADD_REG32 ((volatile P_U32)(NFI_BASE+0x0188))
3746 +#define NFI_LOCK15FMT_REG32 ((volatile P_U32)(NFI_BASE+0x018C))
3747 +
3748 +#define NFI_FIFODATA0_REG32 ((volatile P_U32)(NFI_BASE+0x0190))
3749 +#define NFI_FIFODATA1_REG32 ((volatile P_U32)(NFI_BASE+0x0194))
3750 +#define NFI_FIFODATA2_REG32 ((volatile P_U32)(NFI_BASE+0x0198))
3751 +#define NFI_FIFODATA3_REG32 ((volatile P_U32)(NFI_BASE+0x019C))
3752 +#define NFI_MASTERSTA_REG16 ((volatile P_U16)(NFI_BASE+0x0210))
3753 +
3754 +
3755 +/*******************************************************************************
3756 + * NFI Register Field Definition
3757 + *******************************************************************************/
3758 +
3759 +/* NFI_CNFG */
3760 +#define CNFG_AHB             (0x0001)
3761 +#define CNFG_READ_EN         (0x0002)
3762 +#define CNFG_DMA_BURST_EN    (0x0004)
3763 +#define CNFG_BYTE_RW         (0x0040)
3764 +#define CNFG_HW_ECC_EN       (0x0100)
3765 +#define CNFG_AUTO_FMT_EN     (0x0200)
3766 +#define CNFG_OP_IDLE         (0x0000)
3767 +#define CNFG_OP_READ         (0x1000)
3768 +#define CNFG_OP_SRD          (0x2000)
3769 +#define CNFG_OP_PRGM         (0x3000)
3770 +#define CNFG_OP_ERASE        (0x4000)
3771 +#define CNFG_OP_RESET        (0x5000)
3772 +#define CNFG_OP_CUST         (0x6000)
3773 +#define CNFG_OP_MODE_MASK    (0x7000)
3774 +#define CNFG_OP_MODE_SHIFT   (12)
3775 +
3776 +/* NFI_PAGEFMT */
3777 +#define PAGEFMT_512          (0x0000)
3778 +#define PAGEFMT_2K           (0x0001)
3779 +#define PAGEFMT_4K           (0x0002)
3780 +
3781 +#define PAGEFMT_PAGE_MASK    (0x0003)
3782 +
3783 +#define PAGEFMT_DBYTE_EN     (0x0008)
3784 +
3785 +#define PAGEFMT_SPARE_16     (0x0000)
3786 +#define PAGEFMT_SPARE_26     (0x0001)
3787 +#define PAGEFMT_SPARE_27     (0x0002)
3788 +#define PAGEFMT_SPARE_28     (0x0003)
3789 +#define PAGEFMT_SPARE_MASK   (0x0030)
3790 +#define PAGEFMT_SPARE_SHIFT  (4)
3791 +
3792 +#define PAGEFMT_FDM_MASK     (0x0F00)
3793 +#define PAGEFMT_FDM_SHIFT    (8)
3794 +
3795 +#define PAGEFMT_FDM_ECC_MASK  (0xF000)
3796 +#define PAGEFMT_FDM_ECC_SHIFT (12)
3797 +
3798 +/* NFI_CON */
3799 +#define CON_FIFO_FLUSH       (0x0001)
3800 +#define CON_NFI_RST          (0x0002)
3801 +#define CON_NFI_SRD          (0x0010)
3802 +
3803 +#define CON_NFI_NOB_MASK     (0x0060)
3804 +#define CON_NFI_NOB_SHIFT    (5)
3805 +
3806 +#define CON_NFI_BRD          (0x0100)
3807 +#define CON_NFI_BWR          (0x0200)
3808 +
3809 +#define CON_NFI_SEC_MASK     (0xF000)
3810 +#define CON_NFI_SEC_SHIFT    (12)
3811 +
3812 +/* NFI_ACCCON */
3813 +#define ACCCON_SETTING       ()
3814 +
3815 +/* NFI_INTR_EN */
3816 +#define INTR_RD_DONE_EN      (0x0001)
3817 +#define INTR_WR_DONE_EN      (0x0002)
3818 +#define INTR_RST_DONE_EN     (0x0004)
3819 +#define INTR_ERASE_DONE_EN   (0x0008)
3820 +#define INTR_BSY_RTN_EN      (0x0010)
3821 +#define INTR_ACC_LOCK_EN     (0x0020)
3822 +#define INTR_AHB_DONE_EN     (0x0040)
3823 +#define INTR_ALL_INTR_DE     (0x0000)
3824 +#define INTR_ALL_INTR_EN     (0x007F)
3825 +
3826 +/* NFI_INTR */
3827 +#define INTR_RD_DONE         (0x0001)
3828 +#define INTR_WR_DONE         (0x0002)
3829 +#define INTR_RST_DONE        (0x0004)
3830 +#define INTR_ERASE_DONE      (0x0008)
3831 +#define INTR_BSY_RTN         (0x0010)
3832 +#define INTR_ACC_LOCK        (0x0020)
3833 +#define INTR_AHB_DONE        (0x0040)
3834 +
3835 +/* NFI_ADDRNOB */
3836 +#define ADDR_COL_NOB_MASK    (0x0003)
3837 +#define ADDR_COL_NOB_SHIFT   (0)
3838 +#define ADDR_ROW_NOB_MASK    (0x0030)
3839 +#define ADDR_ROW_NOB_SHIFT   (4)
3840 +
3841 +/* NFI_STA */
3842 +#define STA_READ_EMPTY       (0x00001000)
3843 +#define STA_ACC_LOCK         (0x00000010)
3844 +#define STA_CMD_STATE        (0x00000001)
3845 +#define STA_ADDR_STATE       (0x00000002)
3846 +#define STA_DATAR_STATE      (0x00000004)
3847 +#define STA_DATAW_STATE      (0x00000008)
3848 +
3849 +#define STA_NAND_FSM_MASK    (0x1F000000)
3850 +#define STA_NAND_BUSY        (0x00000100)
3851 +#define STA_NAND_BUSY_RETURN (0x00000200)
3852 +#define STA_NFI_FSM_MASK     (0x000F0000)
3853 +#define STA_NFI_OP_MASK      (0x0000000F)
3854 +
3855 +/* NFI_FIFOSTA */
3856 +#define FIFO_RD_EMPTY        (0x0040)
3857 +#define FIFO_RD_FULL         (0x0080)
3858 +#define FIFO_WR_FULL         (0x8000)
3859 +#define FIFO_WR_EMPTY        (0x4000)
3860 +#define FIFO_RD_REMAIN(x)    (0x1F&(x))
3861 +#define FIFO_WR_REMAIN(x)    ((0x1F00&(x))>>8)
3862 +
3863 +/* NFI_ADDRCNTR */
3864 +#define ADDRCNTR_CNTR(x)     ((0xF000&(x))>>12)
3865 +#define ADDRCNTR_OFFSET(x)   (0x03FF&(x))
3866 +
3867 +/* NFI_LOCK */
3868 +#define NFI_LOCK_ON          (0x0001)
3869 +
3870 +/* NFI_LOCKANOB */
3871 +#define PROG_RADD_NOB_MASK   (0x7000)
3872 +#define PROG_RADD_NOB_SHIFT  (12)
3873 +#define PROG_CADD_NOB_MASK   (0x0300)
3874 +#define PROG_CADD_NOB_SHIFT  (8)
3875 +#define ERASE_RADD_NOB_MASK   (0x0070)
3876 +#define ERASE_RADD_NOB_SHIFT  (4)
3877 +#define ERASE_CADD_NOB_MASK   (0x0007)
3878 +#define ERASE_CADD_NOB_SHIFT  (0)
3879 +
3880 +/*******************************************************************************
3881 + * ECC Register Definition
3882 + *******************************************************************************/
3883 +
3884 +#define ECC_ENCCON_REG16       ((volatile P_U16)(NFIECC_BASE+0x0000))
3885 +#define ECC_ENCCNFG_REG32      ((volatile P_U32)(NFIECC_BASE+0x0004))
3886 +#define ECC_ENCDIADDR_REG32    ((volatile P_U32)(NFIECC_BASE+0x0008))
3887 +#define ECC_ENCIDLE_REG32      ((volatile P_U32)(NFIECC_BASE+0x000C))
3888 +#define ECC_ENCPAR0_REG32   ((volatile P_U32)(NFIECC_BASE+0x0010))
3889 +#define ECC_ENCPAR1_REG32   ((volatile P_U32)(NFIECC_BASE+0x0014))
3890 +#define ECC_ENCPAR2_REG32   ((volatile P_U32)(NFIECC_BASE+0x0018))
3891 +#define ECC_ENCPAR3_REG32   ((volatile P_U32)(NFIECC_BASE+0x001C))
3892 +#define ECC_ENCPAR4_REG32   ((volatile P_U32)(NFIECC_BASE+0x0020))
3893 +#define ECC_ENCSTA_REG32    ((volatile P_U32)(NFIECC_BASE+0x0024))
3894 +#define ECC_ENCIRQEN_REG16  ((volatile P_U16)(NFIECC_BASE+0x0028))
3895 +#define ECC_ENCIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x002C))
3896 +
3897 +#define ECC_DECCON_REG16    ((volatile P_U16)(NFIECC_BASE+0x0100))
3898 +#define ECC_DECCNFG_REG32   ((volatile P_U32)(NFIECC_BASE+0x0104))
3899 +#define ECC_DECDIADDR_REG32 ((volatile P_U32)(NFIECC_BASE+0x0108))
3900 +#define ECC_DECIDLE_REG16   ((volatile P_U16)(NFIECC_BASE+0x010C))
3901 +#define ECC_DECFER_REG16    ((volatile P_U16)(NFIECC_BASE+0x0110))
3902 +#define ECC_DECENUM_REG32   ((volatile P_U32)(NFIECC_BASE+0x0114))
3903 +#define ECC_DECDONE_REG16   ((volatile P_U16)(NFIECC_BASE+0x0118))
3904 +#define ECC_DECEL0_REG32    ((volatile P_U32)(NFIECC_BASE+0x011C))
3905 +#define ECC_DECEL1_REG32    ((volatile P_U32)(NFIECC_BASE+0x0120))
3906 +#define ECC_DECEL2_REG32    ((volatile P_U32)(NFIECC_BASE+0x0124))
3907 +#define ECC_DECEL3_REG32    ((volatile P_U32)(NFIECC_BASE+0x0128))
3908 +#define ECC_DECEL4_REG32    ((volatile P_U32)(NFIECC_BASE+0x012C))
3909 +#define ECC_DECEL5_REG32    ((volatile P_U32)(NFIECC_BASE+0x0130))
3910 +#define ECC_DECIRQEN_REG16  ((volatile P_U16)(NFIECC_BASE+0x0134))
3911 +#define ECC_DECIRQSTA_REG16 ((volatile P_U16)(NFIECC_BASE+0x0138))
3912 +#define ECC_FDMADDR_REG32   ((volatile P_U32)(NFIECC_BASE+0x013C))
3913 +#define ECC_DECFSM_REG32    ((volatile P_U32)(NFIECC_BASE+0x0140))
3914 +#define ECC_SYNSTA_REG32    ((volatile P_U32)(NFIECC_BASE+0x0144))
3915 +#define ECC_DECNFIDI_REG32  ((volatile P_U32)(NFIECC_BASE+0x0148))
3916 +#define ECC_SYN0_REG32      ((volatile P_U32)(NFIECC_BASE+0x014C))
3917 +
3918 +/*******************************************************************************
3919 + * ECC register definition
3920 + *******************************************************************************/
3921 +/* ECC_ENCON */
3922 +#define ENC_EN                         (0x0001)
3923 +#define ENC_DE                         (0x0000)
3924 +
3925 +/* ECC_ENCCNFG */
3926 +#define ECC_CNFG_ECC4                  (0x0000)
3927 +#define ECC_CNFG_ECC6                  (0x0001)
3928 +#define ECC_CNFG_ECC8                  (0x0002)
3929 +#define ECC_CNFG_ECC10                 (0x0003)
3930 +#define ECC_CNFG_ECC12                 (0x0004)
3931 +#define ECC_CNFG_ECC_MASK              (0x00000007)
3932 +
3933 +#define ENC_CNFG_NFI                   (0x0010)
3934 +#define ENC_CNFG_MODE_MASK             (0x0010)
3935 +
3936 +#define ENC_CNFG_META6                 (0x10300000)
3937 +#define ENC_CNFG_META8                 (0x10400000)
3938 +
3939 +#define ENC_CNFG_MSG_MASK              (0x1FFF0000)
3940 +#define ENC_CNFG_MSG_SHIFT             (0x10)
3941 +
3942 +/* ECC_ENCIDLE */
3943 +#define ENC_IDLE                       (0x0001)
3944 +
3945 +/* ECC_ENCSTA */
3946 +#define STA_FSM                        (0x001F)
3947 +#define STA_COUNT_PS                   (0xFF10)
3948 +#define STA_COUNT_MS                   (0x3FFF0000)
3949 +
3950 +/* ECC_ENCIRQEN */
3951 +#define ENC_IRQEN                      (0x0001)
3952 +
3953 +/* ECC_ENCIRQSTA */
3954 +#define ENC_IRQSTA                     (0x0001)
3955 +
3956 +/* ECC_DECCON */
3957 +#define DEC_EN                         (0x0001)
3958 +#define DEC_DE                         (0x0000)
3959 +
3960 +/* ECC_ENCCNFG */
3961 +#define DEC_CNFG_ECC4          (0x0000)
3962 +//#define DEC_CNFG_ECC6          (0x0001)
3963 +//#define DEC_CNFG_ECC12         (0x0002)
3964 +#define DEC_CNFG_NFI           (0x0010)
3965 +//#define DEC_CNFG_META6         (0x10300000)
3966 +//#define DEC_CNFG_META8         (0x10400000)
3967 +
3968 +#define DEC_CNFG_FER           (0x01000)
3969 +#define DEC_CNFG_EL            (0x02000)
3970 +#define DEC_CNFG_CORRECT       (0x03000)
3971 +#define DEC_CNFG_TYPE_MASK     (0x03000)
3972 +
3973 +#define DEC_CNFG_EMPTY_EN      (0x80000000)
3974 +
3975 +#define DEC_CNFG_CODE_MASK     (0x1FFF0000)
3976 +#define DEC_CNFG_CODE_SHIFT    (0x10)
3977 +
3978 +/* ECC_DECIDLE */
3979 +#define DEC_IDLE                       (0x0001)
3980 +
3981 +/* ECC_DECFER */
3982 +#define DEC_FER0               (0x0001)
3983 +#define DEC_FER1               (0x0002)
3984 +#define DEC_FER2               (0x0004)
3985 +#define DEC_FER3               (0x0008)
3986 +#define DEC_FER4               (0x0010)
3987 +#define DEC_FER5               (0x0020)
3988 +#define DEC_FER6               (0x0040)
3989 +#define DEC_FER7               (0x0080)
3990 +
3991 +/* ECC_DECENUM */
3992 +#define ERR_NUM0               (0x0000000F)
3993 +#define ERR_NUM1               (0x000000F0)
3994 +#define ERR_NUM2               (0x00000F00)
3995 +#define ERR_NUM3               (0x0000F000)
3996 +#define ERR_NUM4               (0x000F0000)
3997 +#define ERR_NUM5               (0x00F00000)
3998 +#define ERR_NUM6               (0x0F000000)
3999 +#define ERR_NUM7               (0xF0000000)
4000 +
4001 +/* ECC_DECDONE */
4002 +#define DEC_DONE0               (0x0001)
4003 +#define DEC_DONE1               (0x0002)
4004 +#define DEC_DONE2               (0x0004)
4005 +#define DEC_DONE3               (0x0008)
4006 +#define DEC_DONE4               (0x0010)
4007 +#define DEC_DONE5               (0x0020)
4008 +#define DEC_DONE6               (0x0040)
4009 +#define DEC_DONE7               (0x0080)
4010 +
4011 +/* ECC_DECIRQEN */
4012 +#define DEC_IRQEN                      (0x0001)
4013 +
4014 +/* ECC_DECIRQSTA */
4015 +#define DEC_IRQSTA                     (0x0001)
4016 +
4017 +#define CHIPVER_ECO_1           (0x8a00)
4018 +#define CHIPVER_ECO_2           (0x8a01)
4019 +
4020 +//#define NAND_PFM
4021 +
4022 +/*******************************************************************************
4023 + * Data Structure Definition
4024 + *******************************************************************************/
4025 +struct mtk_nand_host
4026 +{
4027 +       struct nand_chip                nand_chip;
4028 +       struct mtd_info                 *mtd;
4029 +       struct mtk_nand_host_hw *hw;
4030 +};
4031 +
4032 +struct NAND_CMD
4033 +{
4034 +       u32     u4ColAddr;
4035 +       u32 u4RowAddr;
4036 +       u32 u4OOBRowAddr;
4037 +       u8      au1OOB[288];
4038 +       u8*     pDataBuf;
4039 +#ifdef NAND_PFM
4040 +       u32 pureReadOOB;
4041 +       u32 pureReadOOBNum;
4042 +#endif
4043 +};
4044 +
4045 +/*
4046 + *     ECC layout control structure. Exported to userspace for
4047 + *  diagnosis and to allow creation of raw images
4048 +struct nand_ecclayout {
4049 +       uint32_t eccbytes;
4050 +       uint32_t eccpos[64];
4051 +       uint32_t oobavail;
4052 +       struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES];
4053 +};
4054 +*/
4055 +#define __DEBUG_NAND           1                       /* Debug information on/off */
4056 +
4057 +/* Debug message event */
4058 +#define DBG_EVT_NONE           0x00000000      /* No event */
4059 +#define DBG_EVT_INIT           0x00000001      /* Initial related event */
4060 +#define DBG_EVT_VERIFY         0x00000002      /* Verify buffer related event */
4061 +#define DBG_EVT_PERFORMANCE    0x00000004      /* Performance related event */
4062 +#define DBG_EVT_READ           0x00000008      /* Read related event */
4063 +#define DBG_EVT_WRITE          0x00000010      /* Write related event */
4064 +#define DBG_EVT_ERASE          0x00000020      /* Erase related event */
4065 +#define DBG_EVT_BADBLOCK       0x00000040      /* Badblock related event */
4066 +#define DBG_EVT_POWERCTL       0x00000080      /* Suspend/Resume related event */
4067 +
4068 +#define DBG_EVT_ALL                    0xffffffff
4069 +
4070 +#define DBG_EVT_MASK           (DBG_EVT_INIT)
4071 +
4072 +#if __DEBUG_NAND
4073 +#define MSG(evt, fmt, args...) \
4074 +do {   \
4075 +       if ((DBG_EVT_##evt) & DBG_EVT_MASK) { \
4076 +               printk(fmt, ##args); \
4077 +       } \
4078 +} while(0)
4079 +
4080 +#define MSG_FUNC_ENTRY(f)      MSG(FUC, "<FUN_ENT>: %s\n", __FUNCTION__)
4081 +#else
4082 +#define MSG(evt, fmt, args...) do{}while(0)
4083 +#define MSG_FUNC_ENTRY(f)         do{}while(0)
4084 +#endif
4085 +
4086 +#define RAMDOM_READ 1<<0
4087 +#define CACHE_READ  1<<1
4088 +
4089 +typedef struct
4090 +{
4091 +   u16 id;          //deviceid+menuid
4092 +   u32 ext_id;
4093 +   u8  addr_cycle;
4094 +   u8  iowidth;
4095 +   u16 totalsize;
4096 +   u16 blocksize;
4097 +   u16 pagesize;
4098 +   u16 sparesize;
4099 +   u32 timmingsetting;
4100 +   char devciename[14];
4101 +   u32 advancedmode;   //
4102 +}flashdev_info,*pflashdev_info;
4103 +
4104 +/* NAND driver */
4105 +#if 0
4106 +struct mtk_nand_host_hw {
4107 +    unsigned int nfi_bus_width;                    /* NFI_BUS_WIDTH */
4108 +       unsigned int nfi_access_timing;         /* NFI_ACCESS_TIMING */
4109 +       unsigned int nfi_cs_num;                        /* NFI_CS_NUM */
4110 +       unsigned int nand_sec_size;                     /* NAND_SECTOR_SIZE */
4111 +       unsigned int nand_sec_shift;            /* NAND_SECTOR_SHIFT */
4112 +       unsigned int nand_ecc_size;
4113 +       unsigned int nand_ecc_bytes;
4114 +       unsigned int nand_ecc_mode;
4115 +};
4116 +extern struct mtk_nand_host_hw mt7621_nand_hw;
4117 +extern u32     CFG_BLOCKSIZE;
4118 +#endif
4119 +#endif
4120 --- a/drivers/mtd/nand/nand_base.c
4121 +++ b/drivers/mtd/nand/nand_base.c
4122 @@ -47,7 +47,7 @@
4123  #include <linux/mtd/partitions.h>
4124  #include <linux/of.h>
4125
4126 -static int nand_get_device(struct mtd_info *mtd, int new_state);
4127 +int nand_get_device(struct mtd_info *mtd, int new_state);
4128
4129  static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
4130                              struct mtd_oob_ops *ops);
4131 @@ -239,7 +239,7 @@ static int check_offs_len(struct mtd_inf
4132   *
4133   * Release chip lock and wake up anyone waiting on the device.
4134   */
4135 -static void nand_release_device(struct mtd_info *mtd)
4136 +void nand_release_device(struct mtd_info *mtd)
4137  {
4138         struct nand_chip *chip = mtd_to_nand(mtd);
4139
4140 @@ -921,7 +921,7 @@ static void panic_nand_get_device(struct
4141   *
4142   * Get the device and lock it for exclusive access
4143   */
4144 -static int
4145 +int
4146  nand_get_device(struct mtd_info *mtd, int new_state)
4147  {
4148         struct nand_chip *chip = mtd_to_nand(mtd);
4149 --- a/drivers/mtd/nand/nand_bbt.c
4150 +++ b/drivers/mtd/nand/nand_bbt.c
4151 @@ -1215,6 +1215,25 @@ err:
4152         return res;
4153  }
4154
4155 +void nand_bbt_set(struct mtd_info *mtd, int page, int flag)
4156 +{
4157 +       struct nand_chip *this = mtd->priv;
4158 +       int block;
4159 +
4160 +       block = (int)(page >> (this->bbt_erase_shift - this->page_shift - 1));
4161 +       this->bbt[block >> 3] &= ~(0x03 << (block & 0x6));
4162 +       this->bbt[block >> 3] |= (flag & 0x3) << (block & 0x6);
4163 +}
4164 +
4165 +int nand_bbt_get(struct mtd_info *mtd, int page)
4166 +{
4167 +       struct nand_chip *this = mtd->priv;
4168 +       int block;
4169 +
4170 +       block = (int)(page >> (this->bbt_erase_shift - this->page_shift - 1));
4171 +       return (this->bbt[block >> 3] >> (block & 0x06)) & 0x03;
4172 +}
4173 +
4174  /**
4175   * nand_update_bbt - update bad block table(s)
4176   * @mtd: MTD device structure
4177 --- /dev/null
4178 +++ b/drivers/mtd/nand/nand_def.h
4179 @@ -0,0 +1,123 @@
4180 +#ifndef __NAND_DEF_H__
4181 +#define __NAND_DEF_H__
4182 +
4183 +#define VERSION        "v2.1 Fix AHB virt2phys error"
4184 +#define MODULE_NAME    "# MTK NAND #"
4185 +#define PROCNAME    "driver/nand"
4186 +
4187 +#undef TESTTIME
4188 +//#define __UBOOT_NAND__                       1
4189 +#define __KERNEL_NAND__                1
4190 +//#define __PRELOADER_NAND__   1
4191 +//#define PMT 1
4192 +//#define _MTK_NAND_DUMMY_DRIVER
4193 +//#define CONFIG_BADBLOCK_CHECK        1
4194 +//#ifdef CONFIG_BADBLOCK_CHECK
4195 +//#define MTK_NAND_BMT 1
4196 +//#endif
4197 +#define ECC_ENABLE             1
4198 +#define MANUAL_CORRECT 1
4199 +//#define __INTERNAL_USE_AHB_MODE__    (0)
4200 +#define SKIP_BAD_BLOCK
4201 +#define FACT_BBT
4202 +
4203 +#ifndef NAND_OTP_SUPPORT
4204 +#define NAND_OTP_SUPPORT 0
4205 +#endif
4206 +
4207 +/*******************************************************************************
4208 + * Macro definition
4209 + *******************************************************************************/
4210 +//#define NFI_SET_REG32(reg, value)   (DRV_WriteReg32(reg, DRV_Reg32(reg) | (value)))
4211 +//#define NFI_SET_REG16(reg, value)   (DRV_WriteReg16(reg, DRV_Reg16(reg) | (value)))
4212 +//#define NFI_CLN_REG32(reg, value)   (DRV_WriteReg32(reg, DRV_Reg32(reg) & (~(value))))
4213 +//#define NFI_CLN_REG16(reg, value)   (DRV_WriteReg16(reg, DRV_Reg16(reg) & (~(value))))
4214 +
4215 +#if defined (__KERNEL_NAND__)
4216 +#define NFI_SET_REG32(reg, value) \
4217 +do {   \
4218 +       g_value = (DRV_Reg32(reg) | (value));\
4219 +       DRV_WriteReg32(reg, g_value); \
4220 +} while(0)
4221 +
4222 +#define NFI_SET_REG16(reg, value) \
4223 +do {   \
4224 +       g_value = (DRV_Reg16(reg) | (value));\
4225 +       DRV_WriteReg16(reg, g_value); \
4226 +} while(0)
4227 +
4228 +#define NFI_CLN_REG32(reg, value) \
4229 +do {   \
4230 +       g_value = (DRV_Reg32(reg) & (~(value)));\
4231 +       DRV_WriteReg32(reg, g_value); \
4232 +} while(0)
4233 +
4234 +#define NFI_CLN_REG16(reg, value) \
4235 +do {   \
4236 +       g_value = (DRV_Reg16(reg) & (~(value)));\
4237 +       DRV_WriteReg16(reg, g_value); \
4238 +} while(0)
4239 +#endif
4240 +
4241 +#define NFI_WAIT_STATE_DONE(state) do{;}while (__raw_readl(NFI_STA_REG32) & state)
4242 +#define NFI_WAIT_TO_READY()  do{;}while (!(__raw_readl(NFI_STA_REG32) & STA_BUSY2READY))
4243 +
4244 +
4245 +#define NAND_SECTOR_SIZE (512)
4246 +#define OOB_PER_SECTOR      (16)
4247 +#define OOB_AVAI_PER_SECTOR (8)
4248 +
4249 +#ifndef PART_SIZE_BMTPOOL
4250 +#define BMT_POOL_SIZE       (80)
4251 +#else
4252 +#define BMT_POOL_SIZE (PART_SIZE_BMTPOOL)
4253 +#endif
4254 +
4255 +#define PMT_POOL_SIZE  (2)
4256 +
4257 +#define TIMEOUT_1   0x1fff
4258 +#define TIMEOUT_2   0x8ff
4259 +#define TIMEOUT_3   0xffff
4260 +#define TIMEOUT_4   0xffff//5000   //PIO
4261 +
4262 +
4263 +/* temporarity definiation */
4264 +#if !defined (__KERNEL_NAND__)
4265 +#define KERN_INFO
4266 +#define KERN_WARNING
4267 +#define KERN_ERR
4268 +#define PAGE_SIZE      (4096)
4269 +#endif
4270 +#define AddStorageTrace                                //AddStorageTrace
4271 +#define STORAGE_LOGGER_MSG_NAND                0
4272 +#define NFI_BASE                                       RALINK_NAND_CTRL_BASE
4273 +#define NFIECC_BASE                            RALINK_NANDECC_CTRL_BASE
4274 +
4275 +#ifdef __INTERNAL_USE_AHB_MODE__
4276 +#define MT65xx_POLARITY_LOW   0
4277 +#define MT65XX_PDN_PERI_NFI   0
4278 +#define MT65xx_EDGE_SENSITIVE 0
4279 +#define MT6575_NFI_IRQ_ID                    (58)
4280 +#endif
4281 +
4282 +#if defined (__KERNEL_NAND__)
4283 +#define RALINK_REG(x)          (*((volatile u32 *)(x)))
4284 +#define __virt_to_phys(x)      virt_to_phys((volatile void*)x)
4285 +#else
4286 +#define CONFIG_MTD_NAND_VERIFY_WRITE   (1)
4287 +#define printk printf
4288 +#define ra_dbg printf
4289 +#define BUG()                                                  //BUG()
4290 +#define BUG_ON(x)                                              //BUG_ON()
4291 +#define NUM_PARTITIONS                                 1
4292 +#endif
4293 +
4294 +#define NFI_DEFAULT_ACCESS_TIMING        (0x30C77fff)  //(0x44333)
4295 +
4296 +//uboot only support 1 cs
4297 +#define NFI_CS_NUM                  (1)
4298 +#define NFI_DEFAULT_CS              (0)
4299 +
4300 +#include "mt6575_typedefs.h"
4301 +
4302 +#endif /* __NAND_DEF_H__ */
4303 --- /dev/null
4304 +++ b/drivers/mtd/nand/nand_device_list.h
4305 @@ -0,0 +1,56 @@
4306 +/* Copyright Statement:
4307 + *
4308 + * This software/firmware and related documentation ("MediaTek Software") are
4309 + * protected under relevant copyright laws. The information contained herein
4310 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
4311 + * Without the prior written permission of MediaTek inc. and/or its licensors,
4312 + * any reproduction, modification, use or disclosure of MediaTek Software,
4313 + * and information contained herein, in whole or in part, shall be strictly prohibited.
4314 + */
4315 +/* MediaTek Inc. (C) 2010. All rights reserved.
4316 + *
4317 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
4318 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
4319 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
4320 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
4321 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
4322 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
4323 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
4324 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
4325 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
4326 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
4327 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
4328 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
4329 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
4330 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
4331 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
4332 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
4333 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
4334 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
4335 + *
4336 + * The following software/firmware and/or related documentation ("MediaTek Software")
4337 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
4338 + * applicable license agreements with MediaTek Inc.
4339 + */
4340 +
4341 +#ifndef __NAND_DEVICE_LIST_H__
4342 +#define __NAND_DEVICE_LIST_H__
4343 +
4344 +static const flashdev_info gen_FlashTable[]={
4345 +       {0x20BC, 0x105554, 5, 16, 512, 128, 2048, 64, 0x1123, "EHD013151MA_5", 0},
4346 +       {0xECBC, 0x005554, 5, 16, 512, 128, 2048, 64, 0x1123, "K524G2GACB_A0", 0},
4347 +       {0x2CBC, 0x905556, 5, 16, 512, 128, 2048, 64, 0x21044333, "MT29C4G96MAZA", 0},
4348 +       {0x2CDA, 0x909506, 5, 8,  256, 128, 2048, 64, 0x30C77fff, "MT29F2G08ABAE", 0},
4349 +       {0xADBC, 0x905554, 5, 16, 512, 128, 2048, 64, 0x10801011, "H9DA4GH4JJAMC", 0},
4350 +    {0x01F1, 0x801D01, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "S34ML01G100TF", 0},
4351 +    {0x92F1, 0x8095FF, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "F59L1G81A", 0},
4352 +       {0xECD3, 0x519558, 5, 8, 1024, 128, 2048, 64, 0x44333, "K9K8G8000", 0},
4353 +    {0xC2F1, 0x801DC2, 4, 8, 128, 128, 2048, 64, 0x30C77fff, "MX30LF1G08AA", 0},
4354 +    {0x98D3, 0x902676, 5, 8, 1024, 256, 4096, 224, 0x00C25332, "TC58NVG3S0F", 0},
4355 +    {0x01DA, 0x909546, 5, 8, 256, 128, 2048, 128, 0x30C77fff, "S34ML02G200TF", 0},
4356 +    {0x01DC, 0x909556, 5, 8, 512, 128, 2048, 128, 0x30C77fff, "S34ML04G200TF", 0},
4357 +       {0x0000, 0x000000, 0, 0, 0, 0, 0, 0, 0, "xxxxxxxxxx", 0},
4358 +};
4359 +
4360 +
4361 +#endif
4362 --- /dev/null
4363 +++ b/drivers/mtd/nand/partition.h
4364 @@ -0,0 +1,115 @@
4365 +/* Copyright Statement:
4366 + *
4367 + * This software/firmware and related documentation ("MediaTek Software") are
4368 + * protected under relevant copyright laws. The information contained herein
4369 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
4370 + * Without the prior written permission of MediaTek inc. and/or its licensors,
4371 + * any reproduction, modification, use or disclosure of MediaTek Software,
4372 + * and information contained herein, in whole or in part, shall be strictly prohibited.
4373 + */
4374 +/* MediaTek Inc. (C) 2010. All rights reserved.
4375 + *
4376 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
4377 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
4378 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
4379 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
4380 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
4381 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
4382 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
4383 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
4384 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
4385 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
4386 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
4387 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
4388 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
4389 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
4390 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
4391 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
4392 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
4393 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
4394 + *
4395 + * The following software/firmware and/or related documentation ("MediaTek Software")
4396 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
4397 + * applicable license agreements with MediaTek Inc.
4398 + */
4399 +
4400 +#include <linux/mtd/mtd.h>
4401 +#include <linux/mtd/nand.h>
4402 +#include <linux/mtd/partitions.h>
4403 +
4404 +#define RECONFIG_PARTITION_SIZE 1
4405 +
4406 +#define MTD_BOOT_PART_SIZE  0x80000
4407 +#define MTD_CONFIG_PART_SIZE    0x20000
4408 +#define MTD_FACTORY_PART_SIZE   0x20000
4409 +
4410 +extern unsigned int  CFG_BLOCKSIZE;
4411 +#define LARGE_MTD_BOOT_PART_SIZE       (CFG_BLOCKSIZE<<2)
4412 +#define LARGE_MTD_CONFIG_PART_SIZE     (CFG_BLOCKSIZE<<2)
4413 +#define LARGE_MTD_FACTORY_PART_SIZE    (CFG_BLOCKSIZE<<1)
4414 +
4415 +/*=======================================================================*/
4416 +/* NAND PARTITION Mapping                                                  */
4417 +/*=======================================================================*/
4418 +//#ifdef CONFIG_MTD_PARTITIONS
4419 +static struct mtd_partition g_pasStatic_Partition[] = {
4420 +       {
4421 +                name:           "ALL",
4422 +                size:           MTDPART_SIZ_FULL,
4423 +                offset:         0,
4424 +        },
4425 +        /* Put your own partition definitions here */
4426 +        {
4427 +                name:           "Bootloader",
4428 +                size:           MTD_BOOT_PART_SIZE,
4429 +                offset:         0,
4430 +        }, {
4431 +                name:           "Config",
4432 +                size:           MTD_CONFIG_PART_SIZE,
4433 +                offset:         MTDPART_OFS_APPEND
4434 +        }, {
4435 +                name:           "Factory",
4436 +                size:           MTD_FACTORY_PART_SIZE,
4437 +                offset:         MTDPART_OFS_APPEND
4438 +#ifdef CONFIG_RT2880_ROOTFS_IN_FLASH
4439 +        }, {
4440 +                name:           "Kernel",
4441 +                size:           MTD_KERN_PART_SIZE,
4442 +                offset:         MTDPART_OFS_APPEND,
4443 +        }, {
4444 +                name:           "RootFS",
4445 +                size:           MTD_ROOTFS_PART_SIZE,
4446 +                offset:         MTDPART_OFS_APPEND,
4447 +#ifdef CONFIG_ROOTFS_IN_FLASH_NO_PADDING
4448 +        }, {
4449 +                name:           "Kernel_RootFS",
4450 +                size:           MTD_KERN_PART_SIZE + MTD_ROOTFS_PART_SIZE,
4451 +                offset:         MTD_BOOT_PART_SIZE + MTD_CONFIG_PART_SIZE + MTD_FACTORY_PART_SIZE,
4452 +#endif
4453 +#else //CONFIG_RT2880_ROOTFS_IN_RAM
4454 +        }, {
4455 +                name:           "Kernel",
4456 +                size:           0x10000,
4457 +                offset:         MTDPART_OFS_APPEND,
4458 +#endif
4459 +#ifdef CONFIG_DUAL_IMAGE
4460 +        }, {
4461 +                name:           "Kernel2",
4462 +                size:           MTD_KERN2_PART_SIZE,
4463 +                offset:         MTD_KERN2_PART_OFFSET,
4464 +#ifdef CONFIG_RT2880_ROOTFS_IN_FLASH
4465 +        }, {
4466 +                name:           "RootFS2",
4467 +                size:           MTD_ROOTFS2_PART_SIZE,
4468 +                offset:         MTD_ROOTFS2_PART_OFFSET,
4469 +#endif
4470 +#endif
4471 +        }
4472 +
4473 +};
4474 +
4475 +#define NUM_PARTITIONS ARRAY_SIZE(g_pasStatic_Partition)
4476 +extern int part_num;   // = NUM_PARTITIONS;
4477 +//#endif
4478 +#undef RECONFIG_PARTITION_SIZE
4479 +