1 --- a/arch/mips/ralink/mt7621.c
2 +++ b/arch/mips/ralink/mt7621.c
4 #include <asm/mach-ralink/ralink_regs.h>
5 #include <asm/mach-ralink/mt7621.h>
6 #include <asm/mips-boards/launch.h>
7 +#include <asm/delay.h>
11 @@ -177,6 +178,58 @@ bool plat_cpu_core_present(int core)
17 +* Re-calibration lpj(loop-per-jiffy).
18 +* (derived from kernel/calibrate.c)
20 +static int udelay_recal(void)
22 + unsigned int i, lpj = 0;
23 + unsigned long ticks, loopbit;
24 + int lps_precision = LPS_PREC;
28 + while ((lpj <<= 1) != 0) {
29 + /* wait for "start of" clock tick */
31 + while (ticks == jiffies)
37 + ticks = jiffies - ticks;
43 + * Do a binary approximation to get lpj set to
44 + * equal one clock (up to lps_precision bits)
48 + while (lps_precision-- && (loopbit >>= 1)) {
51 + while (ticks == jiffies)
55 + if (jiffies != ticks) /* longer than 1 tick */
58 + printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
60 + for(i=0; i< NR_CPUS; i++)
61 + cpu_data[i].udelay_val = lpj;
65 +device_initcall(udelay_recal);
67 void prom_soc_init(struct ralink_soc_info *soc_info)
69 void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
70 --- a/arch/mips/ralink/Kconfig
71 +++ b/arch/mips/ralink/Kconfig
72 @@ -58,6 +58,7 @@ choice
73 select CLKSRC_MIPS_GIC
75 select WEAK_REORDERING_BEYOND_LLSC
76 + select GENERIC_CLOCKEVENTS_BROADCAST
80 --- a/arch/mips/ralink/timer-gic.c
81 +++ b/arch/mips/ralink/timer-gic.c
84 #include <linux/clk-provider.h>
85 #include <linux/clocksource.h>
86 +#include <asm/time.h>
90 @@ -19,6 +20,8 @@ void __init plat_time_init(void)
94 + mips_hpt_frequency = 880000000 / 2;