target/linux/ramips/patches-4.14/101-mt7621-timer.patch

   1 --- a/arch/mips/ralink/mt7621.c
   2 +++ b/arch/mips/ralink/mt7621.c
   3 @@ -9,6 +9,7 @@
   4
   5  #include <linux/kernel.h>
   6  #include <linux/init.h>
   7 +#include <linux/jiffies.h>
   8
   9  #include <asm/mipsregs.h>
  10  #include <asm/smp-ops.h>
  11 @@ -16,6 +17,7 @@
  12  #include <asm/mach-ralink/ralink_regs.h>
  13  #include <asm/mach-ralink/mt7621.h>
  14  #include <asm/mips-boards/launch.h>
  15 +#include <asm/delay.h>
  16
  17  #include <pinmux.h>
  18
  19 @@ -177,6 +179,58 @@ bool plat_cpu_core_present(int core)
  20         return true;
  21  }
  22
  23 +#define LPS_PREC 8
  24 +/*
  25 +*  Re-calibration lpj(loop-per-jiffy).
  26 +*  (derived from kernel/calibrate.c)
  27 +*/
  28 +static int udelay_recal(void)
  29 +{
  30 +       unsigned int i, lpj = 0;
  31 +       unsigned long ticks, loopbit;
  32 +       int lps_precision = LPS_PREC;
  33 +
  34 +       lpj = (1<<12);
  35 +
  36 +       while ((lpj <<= 1) != 0) {
  37 +               /* wait for "start of" clock tick */
  38 +               ticks = jiffies;
  39 +               while (ticks == jiffies)
  40 +                       /* nothing */;
  41 +
  42 +               /* Go .. */
  43 +               ticks = jiffies;
  44 +               __delay(lpj);
  45 +               ticks = jiffies - ticks;
  46 +               if (ticks)
  47 +                       break;
  48 +       }
  49 +
  50 +       /*
  51 +        * Do a binary approximation to get lpj set to
  52 +        * equal one clock (up to lps_precision bits)
  53 +        */
  54 +       lpj >>= 1;
  55 +       loopbit = lpj;
  56 +       while (lps_precision-- && (loopbit >>= 1)) {
  57 +               lpj |= loopbit;
  58 +               ticks = jiffies;
  59 +               while (ticks == jiffies)
  60 +                       /* nothing */;
  61 +               ticks = jiffies;
  62 +               __delay(lpj);
  63 +               if (jiffies != ticks)   /* longer than 1 tick */
  64 +                       lpj &= ~loopbit;
  65 +       }
  66 +       printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj);
  67 +
  68 +       for(i=0; i< NR_CPUS; i++)
  69 +               cpu_data[i].udelay_val = lpj;
  70 +
  71 +       return 0;
  72 +}
  73 +device_initcall(udelay_recal);
  74 +
  75  void prom_soc_init(struct ralink_soc_info *soc_info)
  76  {
  77         void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE);
  78 --- a/arch/mips/ralink/Kconfig
  79 +++ b/arch/mips/ralink/Kconfig
  80 @@ -59,6 +59,7 @@ choice
  81                 select CLKSRC_MIPS_GIC
  82                 select HW_HAS_PCI
  83                 select WEAK_REORDERING_BEYOND_LLSC
  84 +               select GENERIC_CLOCKEVENTS_BROADCAST
  85  endchoice
  86
  87  choice