1 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
2 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
5 #define SYSC_REG_CHIP_NAME0 0x00
6 #define SYSC_REG_CHIP_NAME1 0x04
7 +#define SYSC_REG_EFUSE_CFG 0x08
8 #define SYSC_REG_CHIP_REV 0x0c
9 #define SYSC_REG_SYSTEM_CONFIG0 0x10
10 #define SYSC_REG_SYSTEM_CONFIG1 0x14
11 --- a/arch/mips/ralink/mt7620.c
12 +++ b/arch/mips/ralink/mt7620.c
14 #define CLKCFG_FFRAC_MASK 0x001f
15 #define CLKCFG_FFRAC_USB_VAL 0x0003
18 +#define EFUSE_MT7688 0x100000
20 /* does the board have sdram or ddram */
23 @@ -391,7 +394,7 @@ void __init ralink_clk_init(void)
24 #define RINT(x) ((x) / 1000000)
25 #define RFRAC(x) (((x) / 1000) % 1000)
27 - if (ralink_soc == MT762X_SOC_MT7628AN) {
28 + if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
29 if (xtal_rate == MHZ(40))
32 @@ -436,7 +439,8 @@ void __init ralink_clk_init(void)
33 ralink_clk_add("10000e00.uart2", periph_rate);
34 ralink_clk_add("10180000.wmac", xtal_rate);
36 - if (IS_ENABLED(CONFIG_USB) && ralink_soc != MT762X_SOC_MT7628AN) {
37 + if (IS_ENABLED(CONFIG_USB) &&
38 + (ralink_soc == MT762X_SOC_MT7620A || ralink_soc == MT762X_SOC_MT7620N)) {
40 * When the CPU goes into sleep mode, the BUS clock will be too low for
41 * USB to function properly
42 @@ -533,8 +537,15 @@ void prom_soc_init(struct ralink_soc_inf
43 soc_info->compatible = "ralink,mt7620n-soc";
45 } else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
46 - ralink_soc = MT762X_SOC_MT7628AN;
48 + u32 efuse = __raw_readl(sysc + SYSC_REG_EFUSE_CFG);
50 + if (efuse & EFUSE_MT7688) {
51 + ralink_soc = MT762X_SOC_MT7688;
54 + ralink_soc = MT762X_SOC_MT7628AN;
57 soc_info->compatible = "ralink,mt7628an-soc";
59 panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
60 @@ -548,13 +559,13 @@ void prom_soc_init(struct ralink_soc_inf
62 cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
64 - if (ralink_soc == MT762X_SOC_MT7628AN)
65 + if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688)
66 dram_type = ((cfg0&0x00000001) == 0x00000001)?SYSCFG0_DRAM_TYPE_DDR1_MT7628:SYSCFG0_DRAM_TYPE_DDR2_MT7628;
68 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
70 soc_info->mem_base = MT7620_DRAM_BASE;
71 - if (ralink_soc == MT762X_SOC_MT7628AN)
72 + if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688)
73 mt7628_dram_init(soc_info);
75 mt7620_dram_init(soc_info);
76 @@ -567,7 +578,7 @@ void prom_soc_init(struct ralink_soc_inf
77 pr_info("Digital PMU set to %s control\n",
78 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
80 - if (ralink_soc == MT762X_SOC_MT7628AN)
81 + if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688)
82 rt2880_pinmux_data = mt7628an_pinmux_data;
84 rt2880_pinmux_data = mt7620a_pinmux_data;
85 --- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
86 +++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
87 @@ -24,6 +24,7 @@ enum ralink_soc_type {
93 extern enum ralink_soc_type ralink_soc;
95 --- a/drivers/net/ethernet/ralink/esw_rt3052.c
96 +++ b/drivers/net/ethernet/ralink/esw_rt3052.c
97 @@ -611,7 +611,7 @@ static void esw_hw_init(struct rt305x_es
98 rt305x_mii_write(esw, 0, 29, 0x598b);
99 /* select local register */
100 rt305x_mii_write(esw, 0, 31, 0x8000);
101 - } else if (ralink_soc == MT762X_SOC_MT7628AN) {
102 + } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
106 @@ -1042,7 +1042,7 @@ esw_get_port_tr_badgood(struct switch_de
107 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
110 - if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN))
111 + if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
114 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)