1 From 8481cdf6f96dc16cbcc129d046c021d17a891274 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 27 Jul 2014 11:00:32 +0100
4 Subject: [PATCH 48/57] GPIO: ralink: add mt7621 gpio controller
6 Signed-off-by: John Crispin <blogic@openwrt.org>
8 arch/mips/Kconfig | 3 +
9 drivers/gpio/Kconfig | 6 ++
10 drivers/gpio/Makefile | 1 +
11 drivers/gpio/gpio-mt7621.c | 177 ++++++++++++++++++++++++++++++++++++++++++++
12 4 files changed, 187 insertions(+)
13 create mode 100644 drivers/gpio/gpio-mt7621.c
15 --- a/arch/mips/Kconfig
16 +++ b/arch/mips/Kconfig
17 @@ -455,6 +455,9 @@ config RALINK
18 select RESET_CONTROLLER
21 + select ARCH_HAS_RESET_CONTROLLER
22 + select RESET_CONTROLLER
23 + select ARCH_REQUIRE_GPIOLIB
26 bool "SGI IP22 (Indy/Indigo2)"
27 --- a/drivers/gpio/Kconfig
28 +++ b/drivers/gpio/Kconfig
29 @@ -898,6 +898,12 @@ config GPIO_BCM_KONA
31 Turn on GPIO support for Broadcom "Kona" chips.
34 + bool "Mediatek GPIO Support"
35 + depends on SOC_MT7620 || SOC_MT7621
37 + Say yes here to support the Mediatek SoC GPIO device
39 comment "USB GPIO expanders:"
41 config GPIO_VIPERBOARD
42 --- a/drivers/gpio/Makefile
43 +++ b/drivers/gpio/Makefile
44 @@ -107,3 +107,5 @@ obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx
45 obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
46 obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
47 obj-$(CONFIG_GPIO_ZYNQ) += gpio-zynq.o
48 +obj-$(CONFIG_GPIO_MT7621) += gpio-mt7621.o
51 +++ b/drivers/gpio/gpio-mt7621.c
54 + * This program is free software; you can redistribute it and/or modify it
55 + * under the terms of the GNU General Public License version 2 as published
56 + * by the Free Software Foundation.
58 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
59 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
62 +#include <linux/io.h>
63 +#include <linux/err.h>
64 +#include <linux/gpio.h>
65 +#include <linux/module.h>
66 +#include <linux/of_irq.h>
67 +#include <linux/spinlock.h>
68 +#include <linux/irqdomain.h>
69 +#include <linux/interrupt.h>
70 +#include <linux/platform_device.h>
72 +#define MTK_BANK_WIDTH 32
74 +enum mediatek_gpio_reg {
82 +static void __iomem *mtk_gc_membase;
85 + struct gpio_chip chip;
90 +static inline struct mtk_gc
91 +*to_mediatek_gpio(struct gpio_chip *chip)
95 + mgc = container_of(chip, struct mtk_gc, chip);
101 +mtk_gpio_w32(struct mtk_gc *rg, u8 reg, u32 val)
103 + iowrite32(val, mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
107 +mtk_gpio_r32(struct mtk_gc *rg, u8 reg)
109 + return ioread32(mtk_gc_membase + (reg * 0x10) + (rg->bank * 0x4));
113 +mediatek_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
115 + struct mtk_gc *rg = to_mediatek_gpio(chip);
117 + mtk_gpio_w32(rg, (value) ? GPIO_REG_DSET : GPIO_REG_DCLR, BIT(offset));
121 +mediatek_gpio_get(struct gpio_chip *chip, unsigned offset)
123 + struct mtk_gc *rg = to_mediatek_gpio(chip);
125 + return !!(mtk_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
129 +mediatek_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
131 + struct mtk_gc *rg = to_mediatek_gpio(chip);
132 + unsigned long flags;
135 + spin_lock_irqsave(&rg->lock, flags);
136 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
138 + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
139 + spin_unlock_irqrestore(&rg->lock, flags);
145 +mediatek_gpio_direction_output(struct gpio_chip *chip,
146 + unsigned offset, int value)
148 + struct mtk_gc *rg = to_mediatek_gpio(chip);
149 + unsigned long flags;
152 + spin_lock_irqsave(&rg->lock, flags);
153 + t = mtk_gpio_r32(rg, GPIO_REG_CTRL);
155 + mtk_gpio_w32(rg, GPIO_REG_CTRL, t);
156 + mediatek_gpio_set(chip, offset, value);
157 + spin_unlock_irqrestore(&rg->lock, flags);
163 +mediatek_gpio_bank_probe(struct platform_device *pdev, struct device_node *bank)
165 + const __be32 *id = of_get_property(bank, "reg", NULL);
166 + struct mtk_gc *rg = devm_kzalloc(&pdev->dev,
167 + sizeof(struct mtk_gc), GFP_KERNEL);
171 + spin_lock_init(&rg->lock);
173 + rg->chip.dev = &pdev->dev;
174 + rg->chip.label = dev_name(&pdev->dev);
175 + rg->chip.of_node = bank;
176 + rg->chip.base = MTK_BANK_WIDTH * be32_to_cpu(*id);
177 + rg->chip.ngpio = MTK_BANK_WIDTH;
178 + rg->chip.direction_input = mediatek_gpio_direction_input;
179 + rg->chip.direction_output = mediatek_gpio_direction_output;
180 + rg->chip.get = mediatek_gpio_get;
181 + rg->chip.set = mediatek_gpio_set;
182 + rg->bank = be32_to_cpu(*id);
184 + /* set polarity to low for all gpios */
185 + mtk_gpio_w32(rg, GPIO_REG_POL, 0);
187 + dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
189 + return gpiochip_add(&rg->chip);
193 +mediatek_gpio_probe(struct platform_device *pdev)
195 + struct device_node *bank, *np = pdev->dev.of_node;
196 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
198 + mtk_gc_membase = devm_ioremap_resource(&pdev->dev, res);
199 + if (IS_ERR(mtk_gc_membase))
200 + return PTR_ERR(mtk_gc_membase);
202 + for_each_child_of_node(np, bank)
203 + if (of_device_is_compatible(bank, "mtk,mt7621-gpio-bank"))
204 + mediatek_gpio_bank_probe(pdev, bank);
209 +static const struct of_device_id mediatek_gpio_match[] = {
210 + { .compatible = "mtk,mt7621-gpio" },
213 +MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
215 +static struct platform_driver mediatek_gpio_driver = {
216 + .probe = mediatek_gpio_probe,
218 + .name = "mt7621_gpio",
219 + .owner = THIS_MODULE,
220 + .of_match_table = mediatek_gpio_match,
225 +mediatek_gpio_init(void)
227 + return platform_driver_register(&mediatek_gpio_driver);
230 +subsys_initcall(mediatek_gpio_init);