target/linux/ramips/patches-3.14/0051-SPI-MIPS-ralink-add-mt7621-support.patch

   1 From 27b11d4f1888e1a3d6d75b46d4d5a4d86fc03891 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Wed, 6 Aug 2014 10:53:40 +0200
   4 Subject: [PATCH 51/57] SPI: MIPS: ralink: add mt7621 support
   5
   6 Signed-off-by: John Crispin <blogic@openwrt.org>
   7 ---
   8  drivers/spi/spi-rt2880.c |  218 +++++++++++++++++++++++++++++++++++++++++++---
   9  1 file changed, 205 insertions(+), 13 deletions(-)
  10
  11 diff --git a/drivers/spi/spi-rt2880.c b/drivers/spi/spi-rt2880.c
  12 index ac9de67..1c6b72d 100644
  13 --- a/drivers/spi/spi-rt2880.c
  14 +++ b/drivers/spi/spi-rt2880.c
  15 @@ -21,8 +21,13 @@
  16  #include <linux/io.h>
  17  #include <linux/reset.h>
  18  #include <linux/spi/spi.h>
  19 +#include <linux/of_device.h>
  20  #include <linux/platform_device.h>
  21
  22 +#include <ralink_regs.h>
  23 +
  24 +#define SPI_BPW_MASK(bits) BIT((bits) - 1)
  25 +
  26  #define DRIVER_NAME                    "spi-rt2880"
  27  /* only one slave is supported*/
  28  #define RALINK_NUM_CHIPSELECTS         1
  29 @@ -63,6 +68,25 @@
  30  /* SPIFIFOSTAT register bit field */
  31  #define SPIFIFOSTAT_TXFULL             BIT(17)
  32
  33 +#define MT7621_SPI_TRANS       0x00
  34 +#define SPITRANS_BUSY          BIT(16)
  35 +#define MT7621_SPI_OPCODE      0x04
  36 +#define MT7621_SPI_DATA0       0x08
  37 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
  38 +#define SPI_CTL_START          BIT(8)
  39 +#define MT7621_SPI_POLAR       0x38
  40 +#define MT7621_SPI_MASTER      0x28
  41 +#define MT7621_SPI_SPACE       0x3c
  42 +
  43 +struct rt2880_spi;
  44 +
  45 +struct rt2880_spi_ops {
  46 +       void (*init_hw)(struct rt2880_spi *rs);
  47 +       void (*set_cs)(struct rt2880_spi *rs, int enable);
  48 +       int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
  49 +       unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
  50 +};
  51 +
  52  struct rt2880_spi {
  53         struct spi_master       *master;
  54         void __iomem            *base;
  55 @@ -70,6 +94,8 @@ struct rt2880_spi {
  56         unsigned int            speed;
  57         struct clk              *clk;
  58         spinlock_t              lock;
  59 +
  60 +       struct rt2880_spi_ops   *ops;
  61  };
  62
  63  static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
  64 @@ -149,6 +175,17 @@ static int rt2880_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
  65         return 0;
  66  }
  67
  68 +static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
  69 +{
  70 +/*     u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
  71 +
  72 +       // set default clock to hclk/5
  73 +       master &= ~(0xfff << 16);
  74 +       master |= 0x3 << 16;
  75 +*/
  76 +       return 0;
  77 +}
  78 +
  79  /*
  80   * called only when no transfer is active on the bus
  81   */
  82 @@ -164,7 +201,7 @@ rt2880_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
  83
  84         if (rs->speed != speed) {
  85                 dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
  86 -               rc = rt2880_spi_baudrate_set(spi, speed);
  87 +               rc = rs->ops->baudrate_set(spi, speed);
  88                 if (rc)
  89                         return rc;
  90         }
  91 @@ -180,6 +217,17 @@ static void rt2880_spi_set_cs(struct rt2880_spi *rs, int enable)
  92                 rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
  93  }
  94
  95 +static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
  96 +{
  97 +       u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
  98 +
  99 +       if (enable)
 100 +               polar |= 1;
 101 +       else
 102 +               polar &= ~1;
 103 +       rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
 104 +}
 105 +
 106  static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
 107  {
 108         int i;
 109 @@ -198,8 +246,26 @@ static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
 110         return -ETIMEDOUT;
 111  }
 112
 113 +static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
 114 +{
 115 +       int i;
 116 +
 117 +       for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
 118 +               u32 status;
 119 +
 120 +               status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
 121 +               if ((status & SPITRANS_BUSY) == 0) {
 122 +                       return 0;
 123 +               }
 124 +               cpu_relax();
 125 +               udelay(1);
 126 +       }
 127 +
 128 +       return -ETIMEDOUT;
 129 +}
 130 +
 131  static unsigned int
 132 -rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
 133 +rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
 134  {
 135         struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 136         unsigned count = 0;
 137 @@ -239,6 +305,100 @@ out:
 138         return count;
 139  }
 140
 141 +static unsigned int
 142 +mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
 143 +{
 144 +       struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
 145 +       struct spi_transfer *next = NULL;
 146 +       const u8 *tx = xfer->tx_buf;
 147 +       u8 *rx = NULL;
 148 +       u32 trans;
 149 +       int len = xfer->len;
 150 +
 151 +       if (!tx)
 152 +               return 0;
 153 +
 154 +       if (!list_is_last(&xfer->transfer_list, list)) {
 155 +               next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
 156 +               rx = next->rx_buf;
 157 +       }
 158 +
 159 +       trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
 160 +       trans &= ~SPI_CTL_TX_RX_CNT_MASK;
 161 +
 162 +       if (tx) {
 163 +               u32 data0 = 0, opcode = 0;
 164 +
 165 +               switch (xfer->len) {
 166 +               case 8:
 167 +                       data0 |= tx[7] << 24;
 168 +               case 7:
 169 +                       data0 |= tx[6] << 16;
 170 +               case 6:
 171 +                       data0 |= tx[5] << 8;
 172 +               case 5:
 173 +                       data0 |= tx[4];
 174 +               case 4:
 175 +                       opcode |= tx[3] << 8;
 176 +               case 3:
 177 +                       opcode |= tx[2] << 16;
 178 +               case 2:
 179 +                       opcode |= tx[1] << 24;
 180 +               case 1:
 181 +                       opcode |= tx[0];
 182 +                       break;
 183 +
 184 +               default:
 185 +                       dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
 186 +                       return -EINVAL;
 187 +               }
 188 +
 189 +               rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
 190 +               rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
 191 +               trans |= xfer->len;
 192 +       }
 193 +
 194 +       if (rx)
 195 +               trans |= (next->len << 4);
 196 +       rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
 197 +       trans |= SPI_CTL_START;
 198 +       rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
 199 +
 200 +       mt7621_spi_wait_till_ready(rs);
 201 +
 202 +       if (rx) {
 203 +               u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
 204 +               u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
 205 +
 206 +               switch (next->len) {
 207 +               case 8:
 208 +                       rx[7] = (opcode >> 24) & 0xff;
 209 +               case 7:
 210 +                       rx[6] = (opcode >> 16) & 0xff;
 211 +               case 6:
 212 +                       rx[5] = (opcode >> 8) & 0xff;
 213 +               case 5:
 214 +                       rx[4] = opcode & 0xff;
 215 +               case 4:
 216 +                       rx[3] = (data0 >> 24) & 0xff;
 217 +               case 3:
 218 +                       rx[2] = (data0 >> 16) & 0xff;
 219 +               case 2:
 220 +                       rx[1] = (data0 >> 8) & 0xff;
 221 +               case 1:
 222 +                       rx[0] = data0 & 0xff;
 223 +                       break;
 224 +
 225 +               default:
 226 +                       dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
 227 +                       return -EINVAL;
 228 +               }
 229 +               len += next->len;
 230 +       }
 231 +
 232 +       return len;
 233 +}
 234 +
 235  static int rt2880_spi_transfer_one_message(struct spi_master *master,
 236                                            struct spi_message *m)
 237  {
 238 @@ -280,25 +440,25 @@ static int rt2880_spi_transfer_one_message(struct spi_master *master,
 239                 }
 240
 241                 if (!cs_active) {
 242 -                       rt2880_spi_set_cs(rs, 1);
 243 +                       rs->ops->set_cs(rs, 1);
 244                         cs_active = 1;
 245                 }
 246
 247                 if (t->len)
 248 -                       m->actual_length += rt2880_spi_write_read(spi, t);
 249 +                       m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
 250
 251                 if (t->delay_usecs)
 252                         udelay(t->delay_usecs);
 253
 254                 if (t->cs_change) {
 255 -                       rt2880_spi_set_cs(rs, 0);
 256 +                       rs->ops->set_cs(rs, 0);
 257                         cs_active = 0;
 258                 }
 259         }
 260
 261  msg_done:
 262         if (cs_active)
 263 -               rt2880_spi_set_cs(rs, 0);
 264 +               rs->ops->set_cs(rs, 0);
 265
 266         m->status = status;
 267         spi_finalize_current_message(master);
 268 @@ -334,8 +494,41 @@ static void rt2880_spi_reset(struct rt2880_spi *rs)
 269         rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
 270  }
 271
 272 +static void mt7621_spi_reset(struct rt2880_spi *rs)
 273 +{
 274 +       u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
 275 +
 276 +       master &= ~(0xfff << 16);
 277 +       master |= 3 << 16;
 278 +
 279 +       master |= 7 << 29;
 280 +       rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
 281 +}
 282 +
 283 +static struct rt2880_spi_ops spi_ops[] = {
 284 +       {
 285 +               .init_hw = rt2880_spi_reset,
 286 +               .set_cs = rt2880_spi_set_cs,
 287 +               .baudrate_set = rt2880_spi_baudrate_set,
 288 +               .write_read = rt2880_spi_write_read,
 289 +       }, {
 290 +               .init_hw = mt7621_spi_reset,
 291 +               .set_cs = mt7621_spi_set_cs,
 292 +               .baudrate_set = mt7621_spi_baudrate_set,
 293 +               .write_read = mt7621_spi_write_read,
 294 +       },
 295 +};
 296 +
 297 +static const struct of_device_id rt2880_spi_match[] = {
 298 +       { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
 299 +       { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
 300 +       {},
 301 +};
 302 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 303 +
 304  static int rt2880_spi_probe(struct platform_device *pdev)
 305  {
 306 +        const struct of_device_id *match;
 307         struct spi_master *master;
 308         struct rt2880_spi *rs;
 309         unsigned long flags;
 310 @@ -344,6 +537,10 @@ static int rt2880_spi_probe(struct platform_device *pdev)
 311         int status = 0;
 312         struct clk *clk;
 313
 314 +        match = of_match_device(rt2880_spi_match, &pdev->dev);
 315 +       if (!match)
 316 +               return -EINVAL;
 317 +
 318         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 319         base = devm_ioremap_resource(&pdev->dev, r);
 320         if (IS_ERR(base))
 321 @@ -382,12 +579,13 @@ static int rt2880_spi_probe(struct platform_device *pdev)
 322         rs->clk = clk;
 323         rs->master = master;
 324         rs->sys_freq = clk_get_rate(rs->clk);
 325 +       rs->ops = (struct rt2880_spi_ops *) match->data;
 326         dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
 327         spin_lock_irqsave(&rs->lock, flags);
 328
 329         device_reset(&pdev->dev);
 330
 331 -       rt2880_spi_reset(rs);
 332 +       rs->ops->init_hw(rs);
 333
 334         return spi_register_master(master);
 335  }
 336 @@ -408,12 +606,6 @@ static int rt2880_spi_remove(struct platform_device *pdev)
 337
 338  MODULE_ALIAS("platform:" DRIVER_NAME);
 339
 340 -static const struct of_device_id rt2880_spi_match[] = {
 341 -       { .compatible = "ralink,rt2880-spi" },
 342 -       {},
 343 -};
 344 -MODULE_DEVICE_TABLE(of, rt2880_spi_match);
 345 -
 346  static struct platform_driver rt2880_spi_driver = {
 347         .driver = {
 348                 .name = DRIVER_NAME,
 349 --
 350 1.7.10.4
 351