1 From 810c2afe0c7e1be9352ad512b337110b100bfe3a Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Sun, 16 Mar 2014 08:51:14 +0000
4 Subject: [PATCH 36/57] NET: add mt7621 ethernet driver
7 arch/mips/include/asm/rt2880/board-custom.h | 153 +++
8 arch/mips/include/asm/rt2880/eureka_ep430.h | 204 ++++
9 arch/mips/include/asm/rt2880/generic.h | 42 +
10 arch/mips/include/asm/rt2880/lm.h | 32 +
11 arch/mips/include/asm/rt2880/prom.h | 50 +
12 arch/mips/include/asm/rt2880/rt_mmap.h | 796 ++++++++++++++++
13 arch/mips/include/asm/rt2880/serial_rt2880.h | 443 +++++++++
14 arch/mips/include/asm/rt2880/sizes.h | 52 +
15 arch/mips/include/asm/rt2880/surfboard.h | 70 ++
16 arch/mips/include/asm/rt2880/surfboardint.h | 190 ++++
17 arch/mips/include/asm/rt2880/war.h | 25 +
18 drivers/net/ethernet/Kconfig | 1 +
19 drivers/net/ethernet/Makefile | 1 +
20 drivers/net/ethernet/raeth/Kconfig | 344 +++++++
21 drivers/net/ethernet/raeth/Makefile | 7 +
22 drivers/net/ethernet/raeth/ethtool_readme.txt | 44 +
23 drivers/net/ethernet/raeth/mii_mgr.c | 166 ++++
24 drivers/net/ethernet/raeth/ra2882ethreg.h | 1268 +++++++++++++++++++++++++
25 drivers/net/ethernet/raeth/ra_ioctl.h | 92 ++
26 drivers/net/ethernet/raeth/ra_mac.c | 98 ++
27 drivers/net/ethernet/raeth/ra_mac.h | 35 +
28 drivers/net/ethernet/raeth/raether.c | 693 ++++++++++++++
29 drivers/net/ethernet/raeth/raether.h | 92 ++
30 drivers/net/ethernet/raeth/raether_pdma.c | 212 +++++
31 drivers/net/ethernet/raeth/raether_qdma.c | 805 ++++++++++++++++
32 25 files changed, 5915 insertions(+)
33 create mode 100644 arch/mips/include/asm/rt2880/board-custom.h
34 create mode 100644 arch/mips/include/asm/rt2880/eureka_ep430.h
35 create mode 100644 arch/mips/include/asm/rt2880/generic.h
36 create mode 100644 arch/mips/include/asm/rt2880/lm.h
37 create mode 100644 arch/mips/include/asm/rt2880/prom.h
38 create mode 100644 arch/mips/include/asm/rt2880/rt_mmap.h
39 create mode 100644 arch/mips/include/asm/rt2880/serial_rt2880.h
40 create mode 100644 arch/mips/include/asm/rt2880/sizes.h
41 create mode 100644 arch/mips/include/asm/rt2880/surfboard.h
42 create mode 100644 arch/mips/include/asm/rt2880/surfboardint.h
43 create mode 100644 arch/mips/include/asm/rt2880/war.h
44 create mode 100644 drivers/net/ethernet/raeth/Kconfig
45 create mode 100644 drivers/net/ethernet/raeth/Makefile
46 create mode 100644 drivers/net/ethernet/raeth/ethtool_readme.txt
47 create mode 100644 drivers/net/ethernet/raeth/mii_mgr.c
48 create mode 100644 drivers/net/ethernet/raeth/ra2882ethreg.h
49 create mode 100644 drivers/net/ethernet/raeth/ra_ioctl.h
50 create mode 100644 drivers/net/ethernet/raeth/ra_mac.c
51 create mode 100644 drivers/net/ethernet/raeth/ra_mac.h
52 create mode 100644 drivers/net/ethernet/raeth/raether.c
53 create mode 100644 drivers/net/ethernet/raeth/raether.h
54 create mode 100644 drivers/net/ethernet/raeth/raether_pdma.c
55 create mode 100644 drivers/net/ethernet/raeth/raether_qdma.c
57 diff --git a/arch/mips/include/asm/rt2880/board-custom.h b/arch/mips/include/asm/rt2880/board-custom.h
59 index 0000000..120e846
61 +++ b/arch/mips/include/asm/rt2880/board-custom.h
63 +/* Copyright Statement:
65 + * This software/firmware and related documentation ("MediaTek Software") are
66 + * protected under relevant copyright laws. The information contained herein
67 + * is confidential and proprietary to MediaTek Inc. and/or its licensors.
68 + * Without the prior written permission of MediaTek inc. and/or its licensors,
69 + * any reproduction, modification, use or disclosure of MediaTek Software,
70 + * and information contained herein, in whole or in part, shall be strictly prohibited.
72 +/* MediaTek Inc. (C) 2010. All rights reserved.
74 + * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
75 + * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
76 + * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
77 + * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
78 + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
79 + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
80 + * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
81 + * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
82 + * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
83 + * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
84 + * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
85 + * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
86 + * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
87 + * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
88 + * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
89 + * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
90 + * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
91 + * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
93 + * The following software/firmware and/or related documentation ("MediaTek Software")
94 + * have been modified by MediaTek Inc. All revisions are subject to any receiver's
95 + * applicable license agreements with MediaTek Inc.
98 +#ifndef __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
99 +#define __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H
101 +#include <linux/autoconf.h>
103 +/*=======================================================================*/
105 +/*=======================================================================*/
106 +#ifdef MTK_EMMC_SUPPORT
107 +#define CFG_DEV_MSDC0
109 +#define CFG_DEV_MSDC1
110 +#define CFG_DEV_MSDC2
111 +#define CFG_DEV_MSDC3
112 +#if defined(CONFIG_MTK_COMBO) || defined(CONFIG_MTK_COMBO_MODULE)
114 +SDIO slot index number used by connectivity combo chip:
115 +0: invalid (used by memory card)
119 +#define CONFIG_MTK_WCN_CMB_SDIO_SLOT (2) /* MSDC2 */
121 +#undef CONFIG_MTK_WCN_CMB_SDIO_SLOT
125 +/*=======================================================================*/
127 +/*=======================================================================*/
128 +#define CFG_DEV_UART1
129 +#define CFG_DEV_UART2
130 +#define CFG_DEV_UART3
131 +#define CFG_DEV_UART4
133 +#define CFG_UART_PORTS (4)
135 +/*=======================================================================*/
137 +/*=======================================================================*/
139 +//#define CFG_I2C_HIGH_SPEED_MODE
140 +//#define CFG_I2C_DMA_MODE
142 +/*=======================================================================*/
144 +/*=======================================================================*/
145 +#define ADB_SERIAL "E1K"
149 +/*=======================================================================*/
150 +/* MT6575 NAND FLASH */
151 +/*=======================================================================*/
153 +#define RAMDOM_READ 1<<0
154 +#define CACHE_READ 1<<1
155 +/*******************************************************************************
156 + * NFI & ECC Configuration
157 + *******************************************************************************/
160 + u16 id; //deviceid+menuid
166 + u32 timmingsetting;
167 + char devciename[14];
168 + u32 advancedmode; //
169 +}flashdev_info,*pflashdev_info;
171 +static const flashdev_info g_FlashTable[]={
173 + {0xAA2C, 5, 8, 256, 128, 2048, 0x01113, "MT29F2G08ABD", 0},
174 + {0xB12C, 4, 16, 128, 128, 2048, 0x01113, "MT29F1G16ABC", 0},
175 + {0xBA2C, 5, 16, 256, 128, 2048, 0x01113, "MT29F2G16ABD", 0},
176 + {0xAC2C, 5, 8, 512, 128, 2048, 0x01113, "MT29F4G08ABC", 0},
177 + {0xBC2C, 5, 16, 512, 128, 2048, 0x44333, "MT29F4G16ABD", 0},
179 + {0xBAEC, 5, 16, 256, 128, 2048, 0x01123, "K522H1GACE", 0},
180 + {0xBCEC, 5, 16, 512, 128, 2048, 0x01123, "K524G2GACB", 0},
181 + {0xDAEC, 5, 8, 256, 128, 2048, 0x33222, "K9F2G08U0A", RAMDOM_READ},
182 + {0xF1EC, 4, 8, 128, 128, 2048, 0x01123, "K9F1G08U0A", RAMDOM_READ},
183 + {0xAAEC, 5, 8, 256, 128, 2048, 0x01123, "K9F2G08R0A", 0},
185 + {0xD3AD, 5, 8, 1024, 256, 2048, 0x44333, "HY27UT088G2A", 0},
186 + {0xA1AD, 4, 8, 128, 128, 2048, 0x01123, "H8BCSOPJOMCP", 0},
187 + {0xBCAD, 5, 16, 512, 128, 2048, 0x01123, "H8BCSOUNOMCR", 0},
188 + {0xBAAD, 5, 16, 256, 128, 2048, 0x01123, "H8BCSOSNOMCR", 0},
190 + {0x9598, 5, 16, 816, 128, 2048, 0x00113, "TY9C000000CMG", 0},
191 + {0x9498, 5, 16, 375, 128, 2048, 0x00113, "TY9C000000CMG", 0},
192 + {0xC198, 4, 16, 128, 128, 2048, 0x44333, "TC58NWGOS8C", 0},
193 + {0xBA98, 5, 16, 256, 128, 2048, 0x02113, "TC58NYG1S8C", 0},
195 + {0xBA20, 5, 16, 256, 128, 2048, 0x01123, "ND02CGR4B2DI6", 0},
198 + {0xBC20, 5, 16, 512, 128, 2048, 0x01123, "04GR4B2DDI6", 0},
199 + {0x0000, 0, 0, 0, 0, 0, 0, "xxxxxxxxxxxxx", 0}
204 +#define NFI_DEFAULT_ACCESS_TIMING (0x44333)
206 +//uboot only support 1 cs
207 +#define NFI_CS_NUM (2)
208 +#define NFI_DEFAULT_CS (0)
210 +#define USE_AHB_MODE (1)
212 +#define PLATFORM_EVB (1)
214 +#endif /* __ARCH_ARM_MACH_MT6575_CUSTOM_BOARD_H */
216 diff --git a/arch/mips/include/asm/rt2880/eureka_ep430.h b/arch/mips/include/asm/rt2880/eureka_ep430.h
218 index 0000000..e42a992
220 +++ b/arch/mips/include/asm/rt2880/eureka_ep430.h
222 +/**************************************************************************
224 + * This program is free software; you can redistribute it and/or modify it
225 + * under the terms of the GNU General Public License as published by the
226 + * Free Software Foundation; either version 2 of the License, or (at your
227 + * option) any later version.
229 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
230 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
231 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
232 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
233 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
234 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
235 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
236 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
237 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
238 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
240 + * You should have received a copy of the GNU General Public License along
241 + * with this program; if not, write to the Free Software Foundation, Inc.,
242 + * 675 Mass Ave, Cambridge, MA 02139, USA.
245 + **************************************************************************
248 +#ifndef _EUREKA_EP430_H
249 +#define _EUREKA_EP430_H
252 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
253 +#include <asm/byteorder.h> /* for cpu_to_le32() */
254 +#include <asm/mach-ralink/rt_mmap.h>
258 + * Because of an error/peculiarity in the Galileo chip, we need to swap the
259 + * bytes when running bigendian.
262 +#define MV_WRITE(ofs, data) \
263 + *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
264 +#define MV_READ(ofs, data) \
265 + *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
266 +#define MV_READ_DATA(ofs) \
267 + le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
269 +#define MV_WRITE_16(ofs, data) \
270 + *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
271 +#define MV_READ_16(ofs, data) \
272 + *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
274 +#define MV_WRITE_8(ofs, data) \
275 + *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
276 +#define MV_READ_8(ofs, data) \
277 + *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
279 +#define MV_SET_REG_BITS(ofs,bits) \
280 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) |= ((u32)cpu_to_le32(bits))
281 +#define MV_RESET_REG_BITS(ofs,bits) \
282 + (*((volatile u32 *)(RALINK_PCI_BASE+(ofs)))) &= ~((u32)cpu_to_le32(bits))
284 +#define RALINK_PCI_CONFIG_ADDR 0x20
285 +#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
287 +#if defined(CONFIG_RALINK_RT2880) || defined(CONFIG_RALINK_RT2883)
288 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
289 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
290 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
291 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
292 +#define RALINK_PCI_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0010)
293 +#define RALINK_PCI_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0018)
294 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
295 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
296 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
297 +#define RALINK_PCI_ID *(volatile u32 *)(RALINK_PCI_BASE + 0x0030)
298 +#define RALINK_PCI_CLASS *(volatile u32 *)(RALINK_PCI_BASE + 0x0034)
299 +#define RALINK_PCI_SUBID *(volatile u32 *)(RALINK_PCI_BASE + 0x0038)
300 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
301 +#define RALINK_PCI_STATUS *(volatile u32 *)(RALINK_PCI_BASE + 0x0050)
303 +#elif defined(CONFIG_RALINK_RT3883)
305 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
306 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
307 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
308 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
309 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
310 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
311 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
312 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
318 +#define RT3883_PCI_OFFSET 0x1000
319 +#define RT3883_PCIE_OFFSET 0x2000
321 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0010)
322 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0018)
323 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0030)
324 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0034)
325 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCI_OFFSET + 0x0038)
327 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0010)
328 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0018)
329 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0030)
330 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0034)
331 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0038)
332 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT3883_PCIE_OFFSET + 0x0050)
334 +#elif defined(CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7628)
336 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
337 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
338 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
339 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
340 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
341 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
342 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
343 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
349 +#define RT6855_PCIE0_OFFSET 0x2000
350 +#define RT6855_PCIE1_OFFSET 0x3000
352 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
353 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
354 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
355 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
356 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
357 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
358 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
359 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
361 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
362 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
363 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
364 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
365 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
366 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
367 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
368 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
370 +#elif defined (CONFIG_RALINK_MT7621)
372 +#define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
373 +#define RALINK_PCI_PCIRAW_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0004)
374 +#define RALINK_PCI_PCIINT_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0008)
375 +#define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
376 +#define RALINK_PCI_IMBASEBAR1_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x001C)
377 +#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
378 +#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
379 +#define RALINK_PCI_ARBCTL *(volatile u32 *)(RALINK_PCI_BASE + 0x0080)
386 +#define RT6855_PCIE0_OFFSET 0x2000
387 +#define RT6855_PCIE1_OFFSET 0x3000
388 +#define RT6855_PCIE2_OFFSET 0x4000
390 +#define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
391 +#define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
392 +#define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
393 +#define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
394 +#define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
395 +#define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
396 +#define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
397 +#define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
399 +#define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
400 +#define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
401 +#define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
402 +#define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
403 +#define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
404 +#define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
405 +#define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
406 +#define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
408 +#define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
409 +#define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
410 +#define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
411 +#define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
412 +#define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
413 +#define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
414 +#define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
415 +#define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
417 +#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
418 +#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
420 +#elif defined(CONFIG_RALINK_RT3052) || defined(CONFIG_RALINK_RT3352) || defined(CONFIG_RALINK_RT5350)
422 +#error "undefined in PCI"
426 diff --git a/arch/mips/include/asm/rt2880/generic.h b/arch/mips/include/asm/rt2880/generic.h
428 index 0000000..4128f91
430 +++ b/arch/mips/include/asm/rt2880/generic.h
433 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
435 + * This program is free software; you can distribute it and/or modify it
436 + * under the terms of the GNU General Public License (Version 2) as
437 + * published by the Free Software Foundation.
439 + * This program is distributed in the hope it will be useful, but WITHOUT
440 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
441 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
442 + * for more details.
444 + * You should have received a copy of the GNU General Public License along
445 + * with this program; if not, write to the Free Software Foundation, Inc.,
446 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
448 + * Defines of the Palmchip boards specific address-MAP, registers, etc.
450 +#ifndef __ASM_SURFBOARD_GENERIC_H
451 +#define __ASM_SURFBOARD_GENERIC_H
453 +#include <asm/addrspace.h>
454 +#include <asm/byteorder.h>
455 +#include <asm/mach-ralink/rt_mmap.h>
460 +#define SOFTRES_REG (KSEG1ADDR(RALINK_SYSCTL_BASE+0x34))
461 +#define GORESET (0x1)
464 + * Power-off register
466 +#define POWER_DIR_REG (KSEG1ADDR(RALINK_PIO_BASE+0x24))
467 +#define POWER_DIR_OUTPUT (0x80) /* GPIO 7 */
468 +#define POWER_POL_REG (KSEG1ADDR(RALINK_PIO_BASE+0x28))
469 +#define POWEROFF_REG (KSEG1ADDR(RALINK_PIO_BASE+0x20))
470 +#define POWEROFF (0x0) /* drive low */
473 +#endif /* __ASM_SURFBOARD_GENERIC_H */
474 diff --git a/arch/mips/include/asm/rt2880/lm.h b/arch/mips/include/asm/rt2880/lm.h
476 index 0000000..25e2930
478 +++ b/arch/mips/include/asm/rt2880/lm.h
480 +#include <linux/version.h>
484 + struct resource resource;
487 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
493 + struct device_driver drv;
494 + int (*probe)(struct lm_device *);
495 + void (*remove)(struct lm_device *);
496 + int (*suspend)(struct lm_device *, u32);
497 + int (*resume)(struct lm_device *);
500 +int lm_driver_register(struct lm_driver *drv);
501 +void lm_driver_unregister(struct lm_driver *drv);
503 +int lm_device_register(struct lm_device *dev);
505 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20)
506 +# define lm_get_drvdata(lm) ((lm)->lm_drvdata)
507 +# define lm_set_drvdata(lm,d) do { (lm)->lm_drvdata = (d); } while (0)
509 +# define lm_get_drvdata(lm) dev_get_drvdata(&(lm)->dev)
510 +# define lm_set_drvdata(lm,d) dev_set_drvdata(&(lm)->dev, d)
512 diff --git a/arch/mips/include/asm/rt2880/prom.h b/arch/mips/include/asm/rt2880/prom.h
514 index 0000000..51be9b0
516 +++ b/arch/mips/include/asm/rt2880/prom.h
519 + * Carsten Langgaard, carstenl@mips.com
520 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
522 + * ########################################################################
524 + * This program is free software; you can distribute it and/or modify it
525 + * under the terms of the GNU General Public License (Version 2) as
526 + * published by the Free Software Foundation.
528 + * This program is distributed in the hope it will be useful, but WITHOUT
529 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
530 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
531 + * for more details.
533 + * You should have received a copy of the GNU General Public License along
534 + * with this program; if not, write to the Free Software Foundation, Inc.,
535 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
537 + * ########################################################################
539 + * MIPS boards bootprom interface for the Linux kernel.
543 +#ifndef _MIPS_PROM_H
544 +#define _MIPS_PROM_H
546 +extern char *prom_getcmdline(void);
547 +extern char *prom_getenv(char *name);
548 +extern void setup_prom_printf(int tty_no);
549 +extern void prom_setup_printf(int tty_no);
550 +extern void prom_printf(char *fmt, ...);
551 +extern void prom_init_cmdline(void);
552 +extern void prom_meminit(void);
553 +extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
554 +extern void prom_free_prom_memory (void);
555 +extern void mips_display_message(const char *str);
556 +extern void mips_display_word(unsigned int num);
557 +extern int get_ethernet_addr(char *ethernet_addr);
559 +/* Memory descriptor management. */
560 +#define PROM_MAX_PMEMBLOCKS 32
561 +struct prom_pmemblock {
562 + unsigned long base; /* Within KSEG0. */
563 + unsigned int size; /* In bytes. */
564 + unsigned int type; /* free or prom memory */
567 +#endif /* !(_MIPS_PROM_H) */
568 diff --git a/arch/mips/include/asm/rt2880/rt_mmap.h b/arch/mips/include/asm/rt2880/rt_mmap.h
570 index 0000000..0e8f051
572 +++ b/arch/mips/include/asm/rt2880/rt_mmap.h
574 +/**************************************************************************
576 + * BRIEF MODULE DESCRIPTION
577 + * register definition for Ralink RT-series SoC
579 + * Copyright 2007 Ralink Inc.
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
602 + **************************************************************************
605 +#ifndef __RALINK_MMAP__
606 +#define __RALINK_MMAP__
608 +#if defined (CONFIG_RALINK_RT2880_SHUTTLE)
610 +#define RALINK_SYSCTL_BASE 0xA0300000
611 +#define RALINK_TIMER_BASE 0xA0300100
612 +#define RALINK_INTCL_BASE 0xA0300200
613 +#define RALINK_MEMCTRL_BASE 0xA0300300
614 +#define RALINK_UART_BASE 0xA0300500
615 +#define RALINK_PIO_BASE 0xA0300600
616 +#define RALINK_I2C_BASE 0xA0300900
617 +#define RALINK_SPI_BASE 0xA0300B00
618 +#define RALINK_UART_LITE_BASE 0xA0300C00
619 +#define RALINK_FRAME_ENGINE_BASE 0xA0310000
620 +#define RALINK_EMBEDD_ROM_BASE 0xA0400000
621 +#define RALINK_PCI_BASE 0xA0500000
622 +#define RALINK_11N_MAC_BASE 0xA0600000
624 +//Interrupt Controller
625 +#define RALINK_INTCTL_TIMER0 (1<<0)
626 +#define RALINK_INTCTL_WDTIMER (1<<1)
627 +#define RALINK_INTCTL_UART (1<<2)
628 +#define RALINK_INTCTL_PIO (1<<3)
629 +#define RALINK_INTCTL_PCM (1<<4)
630 +#define RALINK_INTCTL_UARTLITE (1<<8)
631 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
633 +//Reset Control Register
634 +#define RALINK_TIMER_RST (1<<1)
635 +#define RALINK_INTC_RST (1<<2)
636 +#define RALINK_MC_RST (1<<3)
637 +#define RALINK_CPU_RST (1<<4)
638 +#define RALINK_UART_RST (1<<5)
639 +#define RALINK_PIO_RST (1<<6)
640 +#define RALINK_I2C_RST (1<<9)
641 +#define RALINK_SPI_RST (1<<11)
642 +#define RALINK_UART2_RST (1<<12)
643 +#define RALINK_PCI_RST (1<<16)
644 +#define RALINK_2860_RST (1<<17)
645 +#define RALINK_FE_RST (1<<18)
646 +#define RALINK_PCM_RST (1<<19)
649 +#elif defined (CONFIG_RALINK_RT2880_MP)
651 +#define RALINK_SYSCTL_BASE 0xA0300000
652 +#define RALINK_TIMER_BASE 0xA0300100
653 +#define RALINK_INTCL_BASE 0xA0300200
654 +#define RALINK_MEMCTRL_BASE 0xA0300300
655 +#define RALINK_UART_BASE 0xA0300500
656 +#define RALINK_PIO_BASE 0xA0300600
657 +#define RALINK_I2C_BASE 0xA0300900
658 +#define RALINK_SPI_BASE 0xA0300B00
659 +#define RALINK_UART_LITE_BASE 0x00300C00
660 +#define RALINK_FRAME_ENGINE_BASE 0xA0400000
661 +#define RALINK_EMBEDD_ROM_BASE 0xA0410000
662 +#define RALINK_PCI_BASE 0xA0440000
663 +#define RALINK_11N_MAC_BASE 0xA0480000
665 +//Interrupt Controller
666 +#define RALINK_INTCTL_TIMER0 (1<<0)
667 +#define RALINK_INTCTL_WDTIMER (1<<1)
668 +#define RALINK_INTCTL_UART (1<<2)
669 +#define RALINK_INTCTL_PIO (1<<3)
670 +#define RALINK_INTCTL_PCM (1<<4)
671 +#define RALINK_INTCTL_UARTLITE (1<<8)
672 +#define RALINK_INTCTL_ILL_ACCESS (1<<23)
674 +//Reset Control Register
675 +#define RALINK_TIMER_RST (1<<1)
676 +#define RALINK_INTC_RST (1<<2)
677 +#define RALINK_MC_RST (1<<3)
678 +#define RALINK_CPU_RST (1<<4)
679 +#define RALINK_UART_RST (1<<5)
680 +#define RALINK_PIO_RST (1<<6)
681 +#define RALINK_I2C_RST (1<<9)
682 +#define RALINK_SPI_RST (1<<11)
683 +#define RALINK_UART2_RST (1<<12)
684 +#define RALINK_PCI_RST (1<<16)
685 +#define RALINK_2860_RST (1<<17)
686 +#define RALINK_FE_RST (1<<18)
687 +#define RALINK_PCM_RST (1<<19)
689 +#elif defined (CONFIG_RALINK_RT3052)
691 +#define RALINK_SYSCTL_BASE 0xB0000000
692 +#define RALINK_TIMER_BASE 0xB0000100
693 +#define RALINK_INTCL_BASE 0xB0000200
694 +#define RALINK_MEMCTRL_BASE 0xB0000300
695 +#define RALINK_PCM_BASE 0xB0000400
696 +#define RALINK_UART_BASE 0x10000500
697 +#define RALINK_PIO_BASE 0xB0000600
698 +#define RALINK_GDMA_BASE 0xB0000700
699 +#define RALINK_NAND_CTRL_BASE 0xB0000800
700 +#define RALINK_I2C_BASE 0xB0000900
701 +#define RALINK_I2S_BASE 0xB0000A00
702 +#define RALINK_SPI_BASE 0xB0000B00
703 +#define RALINK_UART_LITE_BASE 0x10000C00
704 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
705 +#define RALINK_ETH_SW_BASE 0xB0110000
706 +#define RALINK_11N_MAC_BASE 0xB0180000
707 +#define RALINK_USB_OTG_BASE 0x101C0000
709 +//Interrupt Controller
710 +#define RALINK_INTCTL_SYSCTL (1<<0)
711 +#define RALINK_INTCTL_TIMER0 (1<<1)
712 +#define RALINK_INTCTL_WDTIMER (1<<2)
713 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
714 +#define RALINK_INTCTL_PCM (1<<4)
715 +#define RALINK_INTCTL_UART (1<<5)
716 +#define RALINK_INTCTL_PIO (1<<6)
717 +#define RALINK_INTCTL_DMA (1<<7)
718 +#define RALINK_INTCTL_NAND (1<<8)
719 +#define RALINK_INTCTL_PC (1<<9)
720 +#define RALINK_INTCTL_I2S (1<<10)
721 +#define RALINK_INTCTL_UARTLITE (1<<12)
722 +#define RALINK_INTCTL_ESW (1<<17)
723 +#define RALINK_INTCTL_OTG (1<<18)
724 +#define RALINK_INTCTL_OTG_IRQN 18
725 +#define RALINK_INTCTL_GLOBAL (1<<31)
727 +//Reset Control Register
728 +#define RALINK_SYS_RST (1<<0)
729 +#define RALINK_CPU_RST (1<<1)
730 +#define RALINK_TIMER_RST (1<<8)
731 +#define RALINK_INTC_RST (1<<9)
732 +#define RALINK_MC_RST (1<<10)
733 +#define RALINK_PCM_RST (1<<11)
734 +#define RALINK_UART_RST (1<<12)
735 +#define RALINK_PIO_RST (1<<13)
736 +#define RALINK_DMA_RST (1<<14)
737 +#define RALINK_I2C_RST (1<<16)
738 +#define RALINK_I2S_RST (1<<17)
739 +#define RALINK_SPI_RST (1<<18)
740 +#define RALINK_UARTL_RST (1<<19)
741 +#define RALINK_RT2872_RST (1<<20)
742 +#define RALINK_FE_RST (1<<21)
743 +#define RALINK_OTG_RST (1<<22)
744 +#define RALINK_SW_RST (1<<23)
745 +#define RALINK_EPHY_RST (1<<24)
747 +#elif defined (CONFIG_RALINK_RT3352)
749 +#define RALINK_SYSCTL_BASE 0xB0000000
750 +#define RALINK_TIMER_BASE 0xB0000100
751 +#define RALINK_INTCL_BASE 0xB0000200
752 +#define RALINK_MEMCTRL_BASE 0xB0000300
753 +#define RALINK_UART_BASE 0x10000500
754 +#define RALINK_PIO_BASE 0xB0000600
755 +#define RALINK_I2C_BASE 0xB0000900
756 +#define RALINK_I2S_BASE 0xB0000A00
757 +#define RALINK_SPI_BASE 0xB0000B00
758 +#define RALINK_NAND_CTRL_BASE 0xB0000800
759 +#define RALINK_UART_LITE_BASE 0x10000C00
760 +#define RALINK_PCM_BASE 0xB0002000
761 +#define RALINK_GDMA_BASE 0xB0002800
762 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
763 +#define RALINK_ETH_SW_BASE 0xB0110000
764 +#define RALINK_USB_DEV_BASE 0x10120000
765 +#define RALINK_11N_MAC_BASE 0xB0180000
766 +#define RALINK_USB_HOST_BASE 0x101C0000
768 +#define RALINK_MCNT_CFG 0xB0000D00
769 +#define RALINK_COMPARE 0xB0000D04
770 +#define RALINK_COUNT 0xB0000D08
772 +//Interrupt Controller
773 +#define RALINK_INTCTL_SYSCTL (1<<0)
774 +#define RALINK_INTCTL_TIMER0 (1<<1)
775 +#define RALINK_INTCTL_WDTIMER (1<<2)
776 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
777 +#define RALINK_INTCTL_PCM (1<<4)
778 +#define RALINK_INTCTL_UART (1<<5)
779 +#define RALINK_INTCTL_PIO (1<<6)
780 +#define RALINK_INTCTL_DMA (1<<7)
781 +#define RALINK_INTCTL_PC (1<<9)
782 +#define RALINK_INTCTL_I2S (1<<10)
783 +#define RALINK_INTCTL_UARTLITE (1<<12)
784 +#define RALINK_INTCTL_ESW (1<<17)
785 +#define RALINK_INTCTL_OTG (1<<18)
786 +#define RALINK_INTCTL_GLOBAL (1<<31)
788 +//Reset Control Register
789 +#define RALINK_SYS_RST (1<<0)
790 +#define RALINK_TIMER_RST (1<<8)
791 +#define RALINK_INTC_RST (1<<9)
792 +#define RALINK_MC_RST (1<<10)
793 +#define RALINK_PCM_RST (1<<11)
794 +#define RALINK_UART_RST (1<<12)
795 +#define RALINK_PIO_RST (1<<13)
796 +#define RALINK_DMA_RST (1<<14)
797 +#define RALINK_I2C_RST (1<<16)
798 +#define RALINK_I2S_RST (1<<17)
799 +#define RALINK_SPI_RST (1<<18)
800 +#define RALINK_UARTL_RST (1<<19)
801 +#define RALINK_WLAN_RST (1<<20)
802 +#define RALINK_FE_RST (1<<21)
803 +#define RALINK_UHST_RST (1<<22)
804 +#define RALINK_ESW_RST (1<<23)
805 +#define RALINK_EPHY_RST (1<<24)
806 +#define RALINK_UDEV_RST (1<<25)
809 +//Clock Conf Register
810 +#define RALINK_UPHY1_CLK_EN (1<<20)
811 +#define RALINK_UPHY0_CLK_EN (1<<18)
812 +#define RALINK_GE1_CLK_EN (1<<16)
815 +#elif defined (CONFIG_RALINK_RT5350)
817 +#define RALINK_SYSCTL_BASE 0xB0000000
818 +#define RALINK_TIMER_BASE 0xB0000100
819 +#define RALINK_INTCL_BASE 0xB0000200
820 +#define RALINK_MEMCTRL_BASE 0xB0000300
821 +#define RALINK_UART_BASE 0x10000500
822 +#define RALINK_PIO_BASE 0xB0000600
823 +#define RALINK_I2C_BASE 0xB0000900
824 +#define RALINK_I2S_BASE 0xB0000A00
825 +#define RALINK_SPI_BASE 0xB0000B00
826 +#define RALINK_UART_LITE_BASE 0x10000C00
827 +#define RALINK_PCM_BASE 0xB0002000
828 +#define RALINK_GDMA_BASE 0xB0002800
829 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
830 +#define RALINK_ETH_SW_BASE 0xB0110000
831 +#define RALINK_USB_DEV_BASE 0x10120000
832 +#define RALINK_11N_MAC_BASE 0xB0180000
833 +#define RALINK_USB_HOST_BASE 0x101C0000
835 +#define RALINK_MCNT_CFG 0xB0000D00
836 +#define RALINK_COMPARE 0xB0000D04
837 +#define RALINK_COUNT 0xB0000D08
839 +//Interrupt Controller
840 +#define RALINK_INTCTL_SYSCTL (1<<0)
841 +#define RALINK_INTCTL_TIMER0 (1<<1)
842 +#define RALINK_INTCTL_WDTIMER (1<<2)
843 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
844 +#define RALINK_INTCTL_PCM (1<<4)
845 +#define RALINK_INTCTL_UART (1<<5)
846 +#define RALINK_INTCTL_PIO (1<<6)
847 +#define RALINK_INTCTL_DMA (1<<7)
848 +#define RALINK_INTCTL_PC (1<<9)
849 +#define RALINK_INTCTL_I2S (1<<10)
850 +#define RALINK_INTCTL_UARTLITE (1<<12)
851 +#define RALINK_INTCTL_ESW (1<<17)
852 +#define RALINK_INTCTL_USB_HOST (1<<18)
853 +#define RALINK_INTCTL_USB_DEV (1<<19)
854 +#define RALINK_INTCTL_GLOBAL (1<<31)
856 +//Reset Control Register
857 +#define RALINK_SYS_RST (1<<0)
858 +#define RALINK_TIMER_RST (1<<8)
859 +#define RALINK_INTC_RST (1<<9)
860 +#define RALINK_MC_RST (1<<10)
861 +#define RALINK_PCM_RST (1<<11)
862 +#define RALINK_UART_RST (1<<12)
863 +#define RALINK_PIO_RST (1<<13)
864 +#define RALINK_DMA_RST (1<<14)
865 +#define RALINK_I2C_RST (1<<16)
866 +#define RALINK_I2S_RST (1<<17)
867 +#define RALINK_SPI_RST (1<<18)
868 +#define RALINK_UARTL_RST (1<<19)
869 +#define RALINK_WLAN_RST (1<<20)
870 +#define RALINK_FE_RST (1<<21)
871 +#define RALINK_UHST_RST (1<<22)
872 +#define RALINK_ESW_RST (1<<23)
873 +#define RALINK_EPHY_RST (1<<24)
874 +#define RALINK_UDEV_RST (1<<25)
875 +#define RALINK_MIPSC_RST (1<<28)
877 +//Clock Conf Register
878 +#define RALINK_UPHY0_CLK_EN (1<<18)
879 +#define RALINK_GE1_CLK_EN (1<<16)
881 +#elif defined (CONFIG_RALINK_RT2883)
883 +#define RALINK_SYSCTL_BASE 0xB0000000
884 +#define RALINK_TIMER_BASE 0xB0000100
885 +#define RALINK_INTCL_BASE 0xB0000200
886 +#define RALINK_MEMCTRL_BASE 0xB0000300
887 +#define RALINK_PCM_BASE 0xB0000400
888 +#define RALINK_UART_BASE 0x10000500
889 +#define RALINK_PIO_BASE 0xB0000600
890 +#define RALINK_GDMA_BASE 0xB0000700
891 +#define RALINK_NAND_CTRL_BASE 0xB0000800
892 +#define RALINK_I2C_BASE 0xB0000900
893 +#define RALINK_I2S_BASE 0xB0000A00
894 +#define RALINK_SPI_BASE 0xB0000B00
895 +#define RALINK_UART_LITE_BASE 0x10000C00
896 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
897 +#define RALINK_PCI_BASE 0xB0140000
898 +#define RALINK_11N_MAC_BASE 0xB0180000
899 +#define RALINK_USB_OTG_BASE 0x101C0000
901 +//Interrupt Controller
902 +#define RALINK_INTCTL_SYSCTL (1<<0)
903 +#define RALINK_INTCTL_TIMER0 (1<<1)
904 +#define RALINK_INTCTL_WDTIMER (1<<2)
905 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
906 +#define RALINK_INTCTL_PCM (1<<4)
907 +#define RALINK_INTCTL_UART (1<<5)
908 +#define RALINK_INTCTL_PIO (1<<6)
909 +#define RALINK_INTCTL_DMA (1<<7)
910 +#define RALINK_INTCTL_NAND (1<<8)
911 +#define RALINK_INTCTL_PC (1<<9)
912 +#define RALINK_INTCTL_I2S (1<<10)
913 +#define RALINK_INTCTL_UARTLITE (1<<12)
914 +#define RALINK_INTCTL_OTG (1<<18)
915 +#define RALINK_INTCTL_OTG_IRQN 18
916 +#define RALINK_INTCTL_GLOBAL (1<<31)
918 +//Reset Control Register
919 +#define RALINK_SYS_RST (1<<0)
920 +#define RALINK_CPU_RST (1<<1)
921 +#define RALINK_TIMER_RST (1<<8)
922 +#define RALINK_INTC_RST (1<<9)
923 +#define RALINK_MC_RST (1<<10)
924 +#define RALINK_PCM_RST (1<<11)
925 +#define RALINK_UART_RST (1<<12)
926 +#define RALINK_PIO_RST (1<<13)
927 +#define RALINK_DMA_RST (1<<14)
928 +#define RALINK_I2C_RST (1<<16)
929 +#define RALINK_I2S_RST (1<<17)
930 +#define RALINK_SPI_RST (1<<18)
931 +#define RALINK_UARTL_RST (1<<19)
932 +#define RALINK_WLAN_RST (1<<20)
933 +#define RALINK_FE_RST (1<<21)
934 +#define RALINK_OTG_RST (1<<22)
935 +#define RALINK_PCIE_RST (1<<23)
937 +#elif defined (CONFIG_RALINK_RT3883)
939 +#define RALINK_SYSCTL_BASE 0xB0000000
940 +#define RALINK_TIMER_BASE 0xB0000100
941 +#define RALINK_INTCL_BASE 0xB0000200
942 +#define RALINK_MEMCTRL_BASE 0xB0000300
943 +#define RALINK_UART_BASE 0x10000500
944 +#define RALINK_PIO_BASE 0xB0000600
945 +#define RALINK_NOR_CTRL_BASE 0xB0000700
946 +#define RALINK_NAND_CTRL_BASE 0xB0000810
947 +#define RALINK_I2C_BASE 0xB0000900
948 +#define RALINK_I2S_BASE 0xB0000A00
949 +#define RALINK_SPI_BASE 0xB0000B00
950 +#define RALINK_UART_LITE_BASE 0x10000C00
951 +#define RALINK_PCM_BASE 0xB0002000
952 +#define RALINK_GDMA_BASE 0xB0002800
953 +#define RALINK_CODEC1_BASE 0xB0003000
954 +#define RALINK_CODEC2_BASE 0xB0003800
955 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
956 +#define RALINK_USB_DEV_BASE 0x10120000
957 +#define RALINK_PCI_BASE 0xB0140000
958 +#define RALINK_11N_MAC_BASE 0xB0180000
959 +#define RALINK_USB_HOST_BASE 0x101C0000
960 +#define RALINK_PCIE_BASE 0xB0200000
962 +//Interrupt Controller
963 +#define RALINK_INTCTL_SYSCTL (1<<0)
964 +#define RALINK_INTCTL_TIMER0 (1<<1)
965 +#define RALINK_INTCTL_WDTIMER (1<<2)
966 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
967 +#define RALINK_INTCTL_PCM (1<<4)
968 +#define RALINK_INTCTL_UART (1<<5)
969 +#define RALINK_INTCTL_PIO (1<<6)
970 +#define RALINK_INTCTL_DMA (1<<7)
971 +#define RALINK_INTCTL_NAND (1<<8)
972 +#define RALINK_INTCTL_PC (1<<9)
973 +#define RALINK_INTCTL_I2S (1<<10)
974 +#define RALINK_INTCTL_UARTLITE (1<<12)
975 +#define RALINK_INTCTL_UHST (1<<18)
976 +#define RALINK_INTCTL_UDEV (1<<19)
978 +//Reset Control Register
979 +#define RALINK_SYS_RST (1<<0)
980 +#define RALINK_TIMER_RST (1<<8)
981 +#define RALINK_INTC_RST (1<<9)
982 +#define RALINK_MC_RST (1<<10)
983 +#define RALINK_PCM_RST (1<<11)
984 +#define RALINK_UART_RST (1<<12)
985 +#define RALINK_PIO_RST (1<<13)
986 +#define RALINK_DMA_RST (1<<14)
987 +#define RALINK_NAND_RST (1<<15)
988 +#define RALINK_I2C_RST (1<<16)
989 +#define RALINK_I2S_RST (1<<17)
990 +#define RALINK_SPI_RST (1<<18)
991 +#define RALINK_UARTL_RST (1<<19)
992 +#define RALINK_WLAN_RST (1<<20)
993 +#define RALINK_FE_RST (1<<21)
994 +#define RALINK_UHST_RST (1<<22)
995 +#define RALINK_PCIE_RST (1<<23)
996 +#define RALINK_PCI_RST (1<<24)
997 +#define RALINK_UDEV_RST (1<<25)
998 +#define RALINK_FLASH_RST (1<<26)
1000 +//Clock Conf Register
1001 +#define RALINK_UPHY1_CLK_EN (1<<20)
1002 +#define RALINK_UPHY0_CLK_EN (1<<18)
1003 +#define RALINK_GE1_CLK_EN (1<<16)
1005 +#elif defined (CONFIG_RALINK_RT6855)
1007 +#define RALINK_SYSCTL_BASE 0xB0000000
1008 +#define RALINK_TIMER_BASE 0xB0000100
1009 +#define RALINK_INTCL_BASE 0xB0000200
1010 +#define RALINK_MEMCTRL_BASE 0xB0000300
1011 +#define RALINK_UART_BASE 0x10000500
1012 +#define RALINK_PIO_BASE 0xB0000600
1013 +#define RALINK_I2C_BASE 0xB0000900
1014 +#define RALINK_I2S_BASE 0xB0000A00
1015 +#define RALINK_SPI_BASE 0xB0000B00
1016 +#define RALINK_NAND_CTRL_BASE 0xB0000800
1017 +#define RALINK_UART_LITE_BASE 0x10000C00
1018 +#define RALINK_PCM_BASE 0xB0002000
1019 +#define RALINK_GDMA_BASE 0xB0002800
1020 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1021 +#define RALINK_ETH_SW_BASE 0xB0110000
1022 +#define RALINK_PCI_BASE 0xB0140000
1023 +#define RALINK_USB_DEV_BASE 0x10120000
1024 +#define RALINK_11N_MAC_BASE 0xB0180000
1025 +#define RALINK_USB_HOST_BASE 0x101C0000
1027 +#define RALINK_MCNT_CFG 0xB0000D00
1028 +#define RALINK_COMPARE 0xB0000D04
1029 +#define RALINK_COUNT 0xB0000D08
1031 +//Interrupt Controller
1032 +#define RALINK_INTCTL_SYSCTL (1<<0)
1033 +#define RALINK_INTCTL_TIMER0 (1<<1)
1034 +#define RALINK_INTCTL_WDTIMER (1<<2)
1035 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1036 +#define RALINK_INTCTL_PCM (1<<4)
1037 +#define RALINK_INTCTL_UART (1<<5)
1038 +#define RALINK_INTCTL_PIO (1<<6)
1039 +#define RALINK_INTCTL_DMA (1<<7)
1040 +#define RALINK_INTCTL_PC (1<<9)
1041 +#define RALINK_INTCTL_I2S (1<<10)
1042 +#define RALINK_INTCTL_UARTLITE (1<<12)
1043 +#define RALINK_INTCTL_ESW (1<<17)
1044 +#define RALINK_INTCTL_OTG (1<<18)
1045 +#define RALINK_INTCTL_GLOBAL (1<<31)
1047 +//Reset Control Register
1048 +#define RALINK_SYS_RST (1<<0)
1049 +#define RALINK_TIMER_RST (1<<8)
1050 +#define RALINK_INTC_RST (1<<9)
1051 +#define RALINK_MC_RST (1<<10)
1052 +#define RALINK_PCM_RST (1<<11)
1053 +#define RALINK_UART_RST (1<<12)
1054 +#define RALINK_PIO_RST (1<<13)
1055 +#define RALINK_DMA_RST (1<<14)
1056 +#define RALINK_I2C_RST (1<<16)
1057 +#define RALINK_I2S_RST (1<<17)
1058 +#define RALINK_SPI_RST (1<<18)
1059 +#define RALINK_UARTL_RST (1<<19)
1060 +#define RALINK_FE_RST (1<<21)
1061 +#define RALINK_UHST_RST (1<<22)
1062 +#define RALINK_ESW_RST (1<<23)
1063 +#define RALINK_EPHY_RST (1<<24)
1064 +#define RALINK_UDEV_RST (1<<25)
1065 +#define RALINK_PCIE0_RST (1<<26)
1066 +#define RALINK_PCIE1_RST (1<<27)
1068 +//Clock Conf Register
1069 +#define RALINK_UPHY0_CLK_EN (1<<25)
1070 +#define RALINK_PCIE0_CLK_EN (1<<26)
1071 +#define RALINK_PCIE1_CLK_EN (1<<27)
1074 +#elif defined (CONFIG_RALINK_MT7620)
1076 +#define RALINK_SYSCTL_BASE 0xB0000000
1077 +#define RALINK_TIMER_BASE 0xB0000100
1078 +#define RALINK_INTCL_BASE 0xB0000200
1079 +#define RALINK_MEMCTRL_BASE 0xB0000300
1080 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1081 +#define RALINK_UART_BASE 0x10000500
1082 +#define RALINK_PIO_BASE 0xB0000600
1083 +#define RALINK_NAND_CTRL_BASE 0xB0000810
1084 +#define RALINK_I2C_BASE 0xB0000900
1085 +#define RALINK_I2S_BASE 0xB0000A00
1086 +#define RALINK_SPI_BASE 0xB0000B00
1087 +#define RALINK_UART_LITE_BASE 0x10000C00
1088 +#define RALINK_MIPS_CNT_BASE 0x10000D00
1089 +#define RALINK_PCM_BASE 0xB0002000
1090 +#define RALINK_GDMA_BASE 0xB0002800
1091 +#define RALINK_CRYPTO_ENGINE_BASE 0xB0004000
1092 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1093 +#define RALINK_PPE_BASE 0xB0100C00
1094 +#define RALINK_ETH_SW_BASE 0xB0110000
1095 +#define RALINK_USB_DEV_BASE 0x10120000
1096 +#define RALINK_MSDC_BASE 0xB0130000
1097 +#define RALINK_PCI_BASE 0xB0140000
1098 +#define RALINK_11N_MAC_BASE 0xB0180000
1099 +#define RALINK_USB_HOST_BASE 0x101C0000
1101 +#define RALINK_MCNT_CFG 0xB0000D00
1102 +#define RALINK_COMPARE 0xB0000D04
1103 +#define RALINK_COUNT 0xB0000D08
1105 +//Interrupt Controller
1106 +#define RALINK_INTCTL_SYSCTL (1<<0)
1107 +#define RALINK_INTCTL_TIMER0 (1<<1)
1108 +#define RALINK_INTCTL_WDTIMER (1<<2)
1109 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1110 +#define RALINK_INTCTL_PCM (1<<4)
1111 +#define RALINK_INTCTL_UART (1<<5)
1112 +#define RALINK_INTCTL_PIO (1<<6)
1113 +#define RALINK_INTCTL_DMA (1<<7)
1114 +#define RALINK_INTCTL_PC (1<<9)
1115 +#define RALINK_INTCTL_I2S (1<<10)
1116 +#define RALINK_INTCTL_SPI (1<<11)
1117 +#define RALINK_INTCTL_UARTLITE (1<<12)
1118 +#define RALINK_INTCTL_CRYPTO (1<<13)
1119 +#define RALINK_INTCTL_ESW (1<<17)
1120 +#define RALINK_INTCTL_UHST (1<<18)
1121 +#define RALINK_INTCTL_UDEV (1<<19)
1122 +#define RALINK_INTCTL_GLOBAL (1<<31)
1124 +//Reset Control Register
1125 +#define RALINK_SYS_RST (1<<0)
1126 +#define RALINK_TIMER_RST (1<<8)
1127 +#define RALINK_INTC_RST (1<<9)
1128 +#define RALINK_MC_RST (1<<10)
1129 +#define RALINK_PCM_RST (1<<11)
1130 +#define RALINK_UART_RST (1<<12)
1131 +#define RALINK_PIO_RST (1<<13)
1132 +#define RALINK_DMA_RST (1<<14)
1133 +#define RALINK_I2C_RST (1<<16)
1134 +#define RALINK_I2S_RST (1<<17)
1135 +#define RALINK_SPI_RST (1<<18)
1136 +#define RALINK_UARTL_RST (1<<19)
1137 +#define RALINK_FE_RST (1<<21)
1138 +#define RALINK_UHST_RST (1<<22)
1139 +#define RALINK_ESW_RST (1<<23)
1140 +#define RALINK_EPHY_RST (1<<24)
1141 +#define RALINK_UDEV_RST (1<<25)
1142 +#define RALINK_PCIE0_RST (1<<26)
1143 +#define RALINK_PCIE1_RST (1<<27)
1144 +#define RALINK_MIPS_CNT_RST (1<<28)
1145 +#define RALINK_CRYPTO_RST (1<<29)
1147 +//Clock Conf Register
1148 +#define RALINK_UPHY0_CLK_EN (1<<25)
1149 +#define RALINK_UPHY1_CLK_EN (1<<22)
1150 +#define RALINK_PCIE0_CLK_EN (1<<26)
1151 +#define RALINK_PCIE1_CLK_EN (1<<27)
1153 +//CPU PLL CFG Register
1154 +#define CPLL_SW_CONFIG (0x1UL << 31)
1155 +#define CPLL_MULT_RATIO_SHIFT 16
1156 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1157 +#define CPLL_DIV_RATIO_SHIFT 10
1158 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1159 +#define BASE_CLOCK 40 /* Mhz */
1161 +#elif defined (CONFIG_RALINK_MT7621)
1163 +#define RALINK_SYSCTL_BASE 0xBE000000
1164 +#define RALINK_TIMER_BASE 0xBE000100
1165 +#define RALINK_INTCL_BASE 0xBE000200
1166 +#define RALINK_RBUS_MATRIXCTL_BASE 0xBE000400
1167 +#define RALINK_MIPS_CNT_BASE 0x1E000500
1168 +#define RALINK_PIO_BASE 0xBE000600
1169 +#define RALINK_SPDIF_BASE 0xBE000700
1170 +#define RALINK_I2C_BASE 0xBE000900
1171 +#define RALINK_I2S_BASE 0xBE000A00
1172 +#define RALINK_SPI_BASE 0xBE000B00
1173 +#define RALINK_UART_LITE1_BASE 0x1E000C00
1174 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1175 +#define RALINK_UART_LITE2_BASE 0x1E000D00
1176 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1177 +#define RALINK_UART_LITE3_BASE 0x1E000E00
1178 +#define RALINK_ANA_CTRL_BASE 0xBE000F00
1179 +#define RALINK_PCM_BASE 0xBE002000
1180 +#define RALINK_GDMA_BASE 0xBE002800
1181 +#define RALINK_NAND_CTRL_BASE 0xBE003000
1182 +#define RALINK_NANDECC_CTRL_BASE 0xBE003800
1183 +#define RALINK_CRYPTO_ENGINE_BASE 0xBE004000
1184 +#define RALINK_MEMCTRL_BASE 0xBE005000
1185 +#define RALINK_EXT_MC_ARB_BASE 0xBE006000
1186 +#define RALINK_HS_DMA_BASE 0xBE007000
1187 +#define RALINK_FRAME_ENGINE_BASE 0xBE100000
1188 +#define RALINK_PPE_BASE 0xBE100C00
1189 +#define RALINK_ETH_SW_BASE 0xBE110000
1190 +#define RALINK_ROM_BASE 0xBE118000
1191 +#define RALINK_MSDC_BASE 0xBE130000
1192 +#define RALINK_PCI_BASE 0xBE140000
1193 +#define RALINK_USB_HOST_BASE 0x1E1C0000
1194 +#define RALINK_11N_MAC_BASE 0xBE180000 //Unused
1196 +#define RALINK_MCNT_CFG 0xBE000500
1197 +#define RALINK_COMPARE 0xBE000504
1198 +#define RALINK_COUNT 0xBE000508
1200 +//Interrupt Controller
1201 +#define RALINK_INTCTL_FE (1<<3)
1202 +#define RALINK_INTCTL_PCIE0 (1<<4)
1203 +#define RALINK_INTCTL_SYSCTL (1<<6)
1204 +#define RALINK_INTCTL_I2C (1<<8)
1205 +#define RALINK_INTCTL_DRAMC (1<<9)
1206 +#define RALINK_INTCTL_PCM (1<<10)
1207 +#define RALINK_INTCTL_HSDMA (1<<11)
1208 +#define RALINK_INTCTL_PIO (1<<12)
1209 +#define RALINK_INTCTL_DMA (1<<13)
1210 +#define RALINK_INTCTL_NFI (1<<14)
1211 +#define RALINK_INTCTL_NFIECC (1<<15)
1212 +#define RALINK_INTCTL_I2S (1<<16)
1213 +#define RALINK_INTCTL_SPI (1<<17)
1214 +#define RALINK_INTCTL_SPDIF (1<<18)
1215 +#define RALINK_INTCTL_CRYPTO (1<<19)
1216 +#define RALINK_INTCTL_SDXC (1<<20)
1217 +#define RALINK_INTCTL_PCTRL (1<<21)
1218 +#define RALINK_INTCTL_USB (1<<22)
1219 +#define RALINK_INTCTL_SWITCH (1<<23)
1220 +#define RALINK_INTCTL_PCIE1 (1<<24)
1221 +#define RALINK_INTCTL_PCIE2 (1<<25)
1222 +#define RALINK_INTCTL_UART1 (1<<26)
1223 +#define RALINK_INTCTL_UART2 (1<<27)
1224 +#define RALINK_INTCTL_UART3 (1<<28)
1225 +#define RALINK_INTCTL_WDTIMER (1<<29)
1226 +#define RALINK_INTCTL_TIMER0 (1<<30)
1227 +#define RALINK_INTCTL_TIMER1 (1<<31)
1230 +//Reset Control Register
1231 +#define RALINK_SYS_RST (1<<0)
1232 +#define RALINK_MCM_RST (1<<1)
1233 +#define RALINK_HSDMA_RST (1<<2)
1234 +#define RALINK_FE_RST (1<<6)
1235 +#define RALINK_SPDIF_RST (1<<7)
1236 +#define RALINK_TIMER_RST (1<<8)
1237 +#define RALINK_INTC_RST (1<<9)
1238 +#define RALINK_MC_RST (1<<10)
1239 +#define RALINK_PCM_RST (1<<11)
1240 +#define RALINK_PIO_RST (1<<13)
1241 +#define RALINK_DMA_RST (1<<14)
1242 +#define RALINK_NAND_RST (1<<15)
1243 +#define RALINK_I2C_RST (1<<16)
1244 +#define RALINK_I2S_RST (1<<17)
1245 +#define RALINK_SPI_RST (1<<18)
1246 +#define RALINK_UART1_RST (1<<19)
1247 +#define RALINK_UART2_RST (1<<20)
1248 +#define RALINK_UART3_RST (1<<21)
1249 +#define RALINK_ETH_RST (1<<23)
1250 +#define RALINK_PCIE0_RST (1<<24)
1251 +#define RALINK_PCIE1_RST (1<<25)
1252 +#define RALINK_PCIE2_RST (1<<26)
1253 +#define RALINK_AUX_STCK_RST (1<<28)
1254 +#define RALINK_CRYPTO_RST (1<<29)
1255 +#define RALINK_SDXC_RST (1<<30)
1256 +#define RALINK_PPE_RST (1<<31)
1258 +//Clock Conf Register
1259 +#define RALINK_PCIE0_CLK_EN (1<<24)
1260 +#define RALINK_PCIE1_CLK_EN (1<<25)
1261 +#define RALINK_PCIE2_CLK_EN (1<<26)
1262 +//#define RALINK_UPHY0_CLK_EN (1<<27)
1263 +//#define RALINK_UPHY1_CLK_EN (1<<28)
1265 +//CPU PLL CFG Register
1266 +#define CPLL_SW_CONFIG (0x1UL << 31)
1267 +#define CPLL_MULT_RATIO_SHIFT 16
1268 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1269 +#define CPLL_DIV_RATIO_SHIFT 10
1270 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1271 +#define BASE_CLOCK 40 /* Mhz */
1273 +#define RALINK_TESTSTAT 0xBE000018
1274 +#define RALINK_TESTSTAT2 0xBE00001C
1276 +#elif defined (CONFIG_RALINK_MT7628)
1278 +#define RALINK_SYSCTL_BASE 0xB0000000
1279 +#define RALINK_TIMER_BASE 0xB0000100
1280 +#define RALINK_INTCL_BASE 0xB0000200
1281 +#define RALINK_MEMCTRL_BASE 0xB0000300
1282 +#define RALINK_RBUS_MATRIXCTL_BASE 0xB0000400
1283 +#define RALINK_MIPS_CNT_BASE 0x10000500
1284 +#define RALINK_PIO_BASE 0xB0000600
1285 +#define RALINK_SPI_SLAVE_BASE 0xB0000700
1286 +#define RALINK_I2C_BASE 0xB0000900
1287 +#define RALINK_I2S_BASE 0xB0000A00
1288 +#define RALINK_SPI_BASE 0xB0000B00
1289 +#define RALINK_UART_LITE1_BASE 0x10000C00
1290 +#define RALINK_UART_LITE_BASE RALINK_UART_LITE1_BASE
1291 +#define RALINK_UART_LITE2_BASE 0x10000D00
1292 +#define RALINK_UART_BASE RALINK_UART_LITE2_BASE
1293 +#define RALINK_UART_LITE3_BASE 0x10000E00
1294 +#define RALINK_PCM_BASE 0xB0002000
1295 +#define RALINK_GDMA_BASE 0xB0002800
1296 +#define RALINK_AES_ENGINE_BASE 0xB0004000
1297 +#define RALINK_CRYPTO_ENGINE_BASE RALINK_AES_ENGINE_BASE
1298 +#define RALINK_FRAME_ENGINE_BASE 0xB0100000
1299 +#define RALINK_PPE_BASE 0xB0100C00
1300 +#define RALINK_ETH_SW_BASE 0xB0110000
1301 +#define RALINK_USB_DEV_BASE 0xB0120000
1302 +#define RALINK_MSDC_BASE 0xB0130000
1303 +#define RALINK_PCI_BASE 0xB0140000
1304 +#define RALINK_11N_MAC_BASE 0xB0180000
1305 +#define RALINK_USB_HOST_BASE 0x101C0000
1307 +#define RALINK_MCNT_CFG 0xB0000500
1308 +#define RALINK_COMPARE 0xB0000504
1309 +#define RALINK_COUNT 0xB0000508
1312 +//Interrupt Controller
1313 +#define RALINK_INTCTL_SYSCTL (1<<0)
1314 +#define RALINK_INTCTL_TIMER0 (1<<1)
1315 +#define RALINK_INTCTL_WDTIMER (1<<2)
1316 +#define RALINK_INTCTL_ILL_ACCESS (1<<3)
1317 +#define RALINK_INTCTL_PCM (1<<4)
1318 +#define RALINK_INTCTL_UART (1<<5)
1319 +#define RALINK_INTCTL_PIO (1<<6)
1320 +#define RALINK_INTCTL_DMA (1<<7)
1321 +#define RALINK_INTCTL_PC (1<<9)
1322 +#define RALINK_INTCTL_I2S (1<<10)
1323 +#define RALINK_INTCTL_SPI (1<<11)
1324 +#define RALINK_INTCTL_UARTLITE (1<<12)
1325 +#define RALINK_INTCTL_CRYPTO (1<<13)
1326 +#define RALINK_INTCTL_ESW (1<<17)
1327 +#define RALINK_INTCTL_UHST (1<<18)
1328 +#define RALINK_INTCTL_UDEV (1<<19)
1329 +#define RALINK_INTCTL_GLOBAL (1<<31)
1331 +//Reset Control Register
1332 +#define RALINK_SYS_RST (1<<0)
1333 +#define RALINK_TIMER_RST (1<<8)
1334 +#define RALINK_INTC_RST (1<<9)
1335 +#define RALINK_MC_RST (1<<10)
1336 +#define RALINK_PCM_RST (1<<11)
1337 +#define RALINK_UART_RST (1<<12)
1338 +#define RALINK_PIO_RST (1<<13)
1339 +#define RALINK_DMA_RST (1<<14)
1340 +#define RALINK_I2C_RST (1<<16)
1341 +#define RALINK_I2S_RST (1<<17)
1342 +#define RALINK_SPI_RST (1<<18)
1343 +#define RALINK_UARTL_RST (1<<19)
1344 +#define RALINK_FE_RST (1<<21)
1345 +#define RALINK_UHST_RST (1<<22)
1346 +#define RALINK_ESW_RST (1<<23)
1347 +#define RALINK_EPHY_RST (1<<24)
1348 +#define RALINK_UDEV_RST (1<<25)
1349 +#define RALINK_PCIE0_RST (1<<26)
1350 +#define RALINK_PCIE1_RST (1<<27)
1351 +#define RALINK_MIPS_CNT_RST (1<<28)
1352 +#define RALINK_CRYPTO_RST (1<<29)
1354 +//Clock Conf Register
1355 +#define RALINK_UPHY0_CLK_EN (1<<25)
1356 +#define RALINK_UPHY1_CLK_EN (1<<22)
1357 +#define RALINK_PCIE0_CLK_EN (1<<26)
1358 +#define RALINK_PCIE1_CLK_EN (1<<27)
1360 +//CPU PLL CFG Register
1361 +#define CPLL_SW_CONFIG (0x1UL << 31)
1362 +#define CPLL_MULT_RATIO_SHIFT 16
1363 +#define CPLL_MULT_RATIO (0x7UL << CPLL_MULT_RATIO_SHIFT)
1364 +#define CPLL_DIV_RATIO_SHIFT 10
1365 +#define CPLL_DIV_RATIO (0x3UL << CPLL_DIV_RATIO_SHIFT)
1366 +#define BASE_CLOCK 40 /* Mhz */
1370 diff --git a/arch/mips/include/asm/rt2880/serial_rt2880.h b/arch/mips/include/asm/rt2880/serial_rt2880.h
1371 new file mode 100644
1372 index 0000000..74f024f
1374 +++ b/arch/mips/include/asm/rt2880/serial_rt2880.h
1376 +/**************************************************************************
1378 + * BRIEF MODULE DESCRIPTION
1379 + * serial port definition for Ralink RT2880 solution
1381 + * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
1383 + * This program is free software; you can redistribute it and/or modify it
1384 + * under the terms of the GNU General Public License as published by the
1385 + * Free Software Foundation; either version 2 of the License, or (at your
1386 + * option) any later version.
1388 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1389 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1390 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1391 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1392 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1393 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1394 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1395 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1396 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1397 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1399 + * You should have received a copy of the GNU General Public License along
1400 + * with this program; if not, write to the Free Software Foundation, Inc.,
1401 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1404 + **************************************************************************
1405 + * May 2007 Bruce Chang
1411 + **************************************************************************
1414 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
1415 +#define RT2880_UART_RBR_OFFSET 0x00
1416 +#define RT2880_UART_TBR_OFFSET 0x00
1417 +#define RT2880_UART_IER_OFFSET 0x04
1418 +#define RT2880_UART_IIR_OFFSET 0x08
1419 +#define RT2880_UART_FCR_OFFSET 0x08
1420 +#define RT2880_UART_LCR_OFFSET 0x0C
1421 +#define RT2880_UART_MCR_OFFSET 0x10
1422 +#define RT2880_UART_LSR_OFFSET 0x14
1423 +#define RT2880_UART_DLL_OFFSET 0x00
1424 +#define RT2880_UART_DLM_OFFSET 0x04
1426 +#define RT2880_UART_RBR_OFFSET 0x00
1427 +#define RT2880_UART_TBR_OFFSET 0x04
1428 +#define RT2880_UART_IER_OFFSET 0x08
1429 +#define RT2880_UART_IIR_OFFSET 0x0C
1430 +#define RT2880_UART_FCR_OFFSET 0x10
1431 +#define RT2880_UART_LCR_OFFSET 0x14
1432 +#define RT2880_UART_MCR_OFFSET 0x18
1433 +#define RT2880_UART_LSR_OFFSET 0x1C
1434 +#define RT2880_UART_DLL_OFFSET 0x2C
1435 +#define RT2880_UART_DLM_OFFSET 0x30
1438 +#define RBR(x) *(volatile u32 *)((x)+RT2880_UART_RBR_OFFSET)
1439 +#define TBR(x) *(volatile u32 *)((x)+RT2880_UART_TBR_OFFSET)
1440 +#define IER(x) *(volatile u32 *)((x)+RT2880_UART_IER_OFFSET)
1441 +#define IIR(x) *(volatile u32 *)((x)+RT2880_UART_IIR_OFFSET)
1442 +#define FCR(x) *(volatile u32 *)((x)+RT2880_UART_FCR_OFFSET)
1443 +#define LCR(x) *(volatile u32 *)((x)+RT2880_UART_LCR_OFFSET)
1444 +#define MCR(x) *(volatile u32 *)((x)+RT2880_UART_MCR_OFFSET)
1445 +#define LSR(x) *(volatile u32 *)((x)+RT2880_UART_LSR_OFFSET)
1446 +#define DLL(x) *(volatile u32 *)((x)+RT2880_UART_DLL_OFFSET)
1447 +#define DLM(x) *(volatile u32 *)((x)+RT2880_UART_DLM_OFFSET)
1450 +#if defined (CONFIG_RALINK_RT2880) || \
1451 + defined (CONFIG_RALINK_RT2883) || \
1452 + defined (CONFIG_RALINK_RT3883) || \
1453 + defined (CONFIG_RALINK_RT3352) || \
1454 + defined (CONFIG_RALINK_RT5350) || \
1455 + defined (CONFIG_RALINK_RT6855) || \
1456 + defined (CONFIG_RALINK_MT7620) || \
1457 + defined (CONFIG_RALINK_RT3052)
1459 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
1461 +#define UART_TX 4 /* Out: Transmit buffer (DLAB=0) */
1462 +#define UART_TRG 4 /* (LCR=BF) FCTR bit 7 selects Rx or Tx
1464 + * Out: Fifo custom trigger levels
1468 +#define UART_IER 8 /* Out: Interrupt Enable Register */
1469 +#define UART_FCTR 8 /* (LCR=BF) Feature Control Register
1473 +#define UART_IIR 12 /* In: Interrupt ID Register */
1474 +#define UART_EFR 12 /* I/O: Extended Features Register */
1475 + /* (DLAB=1, 16C660 only) */
1477 +#define UART_FCR 16 /* Out: FIFO Control Register */
1478 +#define UART_LCR 20 /* Out: Line Control Register */
1479 +#define UART_MCR 24 /* Out: Modem Control Register */
1480 +#define UART_LSR 28 /* In: Line Status Register */
1481 +#define UART_MSR 32 /* In: Modem Status Register */
1482 +#define UART_SCR 36 /* I/O: Scratch Register */
1483 +#define UART_DLL 44 /* Out: Divisor Latch Low (DLAB=1) */
1484 +/* Since surfboard uart cannot be accessed by byte, using UART_DLM will cause
1485 + * unpredictable values to be written to the Divisor Latch
1487 +#define UART_DLM 48 /* Out: Divisor Latch High (DLAB=1) */
1491 +#define UART_RX 0 /* In: Receive buffer */
1492 +#define UART_TX 0 /* Out: Transmit buffer */
1493 +#define UART_DLL 0 /* Out: Divisor Latch Low */
1494 +#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1496 + * Out: Fifo custom trigger levels */
1498 +#define UART_DLM 4 /* Out: Divisor Latch High */
1499 +#define UART_IER 4 /* Out: Interrupt Enable Register */
1500 +#define UART_FCTR 4 /* Feature Control Register */
1502 +#define UART_IIR 8 /* In: Interrupt ID Register */
1503 +#define UART_FCR 8 /* Out: FIFO Control Register */
1504 +#define UART_EFR 8 /* I/O: Extended Features Register */
1506 +#define UART_LCR 12 /* Out: Line Control Register */
1507 +#define UART_MCR 16 /* Out: Modem Control Register */
1508 +#define UART_LSR 20 /* In: Line Status Register */
1509 +#define UART_MSR 24 /* In: Modem Status Register */
1510 +#define UART_SCR 28 /* I/O: Scratch Register */
1511 +#define UART_EMSR 28 /* Extended Mode Select Register */
1517 +//#define UART_IER 1 /* Out: Interrupt Enable Register */
1518 +#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
1519 +#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
1520 +#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
1521 +#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
1523 + * Sleep mode for ST16650 and TI16750. For the ST16650, EFR[4]=1
1525 +#define UART_IERX_SLEEP 0x10 /* Enable sleep mode */
1527 +//#define UART_IIR 2 /* In: Interrupt ID Register */
1528 +#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
1529 +#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
1530 +#define UART_IIR_MSI 0x00 /* Modem status interrupt */
1531 +#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
1532 +#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
1533 +#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
1535 +//#define UART_FCR 2 /* Out: FIFO Control Register */
1536 +#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
1537 +#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
1538 +#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
1539 +#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
1541 + * Note: The FIFO trigger levels are chip specific:
1542 + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
1543 + * PC16550D: 1 4 8 14 xx xx xx xx
1544 + * TI16C550A: 1 4 8 14 xx xx xx xx
1545 + * TI16C550C: 1 4 8 14 xx xx xx xx
1546 + * ST16C550: 1 4 8 14 xx xx xx xx
1547 + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
1548 + * NS16C552: 1 4 8 14 xx xx xx xx
1549 + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
1550 + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
1551 + * TI16C752: 8 16 56 60 8 16 32 56
1553 +#define UART_FCR_R_TRIG_00 0x00
1554 +#define UART_FCR_R_TRIG_01 0x40
1555 +#define UART_FCR_R_TRIG_10 0x80
1556 +#define UART_FCR_R_TRIG_11 0xc0
1557 +#define UART_FCR_T_TRIG_00 0x00
1558 +#define UART_FCR_T_TRIG_01 0x10
1559 +#define UART_FCR_T_TRIG_10 0x20
1560 +#define UART_FCR_T_TRIG_11 0x30
1562 +#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
1563 +#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
1564 +#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
1565 +#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
1566 +#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
1567 +/* 16650 definitions */
1568 +#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */
1569 +#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */
1570 +#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */
1571 +#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */
1572 +#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */
1573 +#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
1574 +#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
1575 +#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
1576 +#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */
1578 +//#define UART_LCR 3 /* Out: Line Control Register */
1580 + * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
1581 + * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
1583 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
1584 +#define UART_LCR_SBC 0x40 /* Set break control */
1585 +#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
1586 +#define UART_LCR_EPAR 0x10 /* Even parity select */
1587 +#define UART_LCR_PARITY 0x08 /* Parity Enable */
1588 +#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 bit, 1=2 bits */
1589 +#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
1590 +#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
1591 +#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
1592 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
1594 +//#define UART_MCR 4 /* Out: Modem Control Register */
1595 +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
1596 +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
1597 +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
1598 +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */
1599 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
1600 +#define UART_MCR_OUT2 0x08 /* Out2 complement */
1601 +#define UART_MCR_OUT1 0x04 /* Out1 complement */
1602 +#define UART_MCR_RTS 0x02 /* RTS complement */
1603 +#define UART_MCR_DTR 0x01 /* DTR complement */
1605 +//#define UART_LSR 5 /* In: Line Status Register */
1606 +#define UART_LSR_TEMT 0x40 /* Transmitter empty */
1607 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
1608 +#define UART_LSR_BI 0x10 /* Break interrupt indicator */
1609 +#define UART_LSR_FE 0x08 /* Frame error indicator */
1610 +#define UART_LSR_PE 0x04 /* Parity error indicator */
1611 +#define UART_LSR_OE 0x02 /* Overrun error indicator */
1612 +#define UART_LSR_DR 0x01 /* Receiver data ready */
1614 +//#define UART_MSR 6 /* In: Modem Status Register */
1615 +#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
1616 +#define UART_MSR_RI 0x40 /* Ring Indicator */
1617 +#define UART_MSR_DSR 0x20 /* Data Set Ready */
1618 +#define UART_MSR_CTS 0x10 /* Clear to Send */
1619 +#define UART_MSR_DDCD 0x08 /* Delta DCD */
1620 +#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
1621 +#define UART_MSR_DDSR 0x02 /* Delta DSR */
1622 +#define UART_MSR_DCTS 0x01 /* Delta CTS */
1623 +#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
1625 +//#define UART_SCR 7 /* I/O: Scratch Register */
1630 +//#define UART_DLL 0 /* Out: Divisor Latch Low */
1631 +//#define UART_DLM 1 /* Out: Divisor Latch High */
1634 + * LCR=0xBF (or DLAB=1 for 16C660)
1636 +//#define UART_EFR 2 /* I/O: Extended Features Register */
1637 +#define UART_EFR_CTS 0x80 /* CTS flow control */
1638 +#define UART_EFR_RTS 0x40 /* RTS flow control */
1639 +#define UART_EFR_SCD 0x20 /* Special character detect */
1640 +#define UART_EFR_ECB 0x10 /* Enhanced control bit */
1642 + * the low four bits control software flow control
1646 + * LCR=0xBF, TI16C752, ST16650, ST16650A, ST16654
1648 +#define UART_XON1 4 /* I/O: Xon character 1 */
1649 +#define UART_XON2 5 /* I/O: Xon character 2 */
1650 +#define UART_XOFF1 6 /* I/O: Xoff character 1 */
1651 +#define UART_XOFF2 7 /* I/O: Xoff character 2 */
1654 + * EFR[4]=1 MCR[6]=1, TI16C752
1656 +#define UART_TI752_TCR 6 /* I/O: transmission control register */
1657 +#define UART_TI752_TLR 7 /* I/O: trigger level register */
1660 + * LCR=0xBF, XR16C85x
1662 +//#define UART_TRG 0 /* FCTR bit 7 selects Rx or Tx
1663 +// * In: Fifo count
1664 +// * Out: Fifo custom trigger levels */
1666 + * These are the definitions for the Programmable Trigger Register
1668 +#define UART_TRG_1 0x01
1669 +#define UART_TRG_4 0x04
1670 +#define UART_TRG_8 0x08
1671 +#define UART_TRG_16 0x10
1672 +#define UART_TRG_32 0x20
1673 +#define UART_TRG_64 0x40
1674 +#define UART_TRG_96 0x60
1675 +#define UART_TRG_120 0x78
1676 +#define UART_TRG_128 0x80
1678 +//#define UART_FCTR 1 /* Feature Control Register */
1679 +#define UART_FCTR_RTS_NODELAY 0x00 /* RTS flow control delay */
1680 +#define UART_FCTR_RTS_4DELAY 0x01
1681 +#define UART_FCTR_RTS_6DELAY 0x02
1682 +#define UART_FCTR_RTS_8DELAY 0x03
1683 +#define UART_FCTR_IRDA 0x04 /* IrDa data encode select */
1684 +#define UART_FCTR_TX_INT 0x08 /* Tx interrupt type select */
1685 +#define UART_FCTR_TRGA 0x00 /* Tx/Rx 550 trigger table select */
1686 +#define UART_FCTR_TRGB 0x10 /* Tx/Rx 650 trigger table select */
1687 +#define UART_FCTR_TRGC 0x20 /* Tx/Rx 654 trigger table select */
1688 +#define UART_FCTR_TRGD 0x30 /* Tx/Rx 850 programmable trigger select */
1689 +#define UART_FCTR_SCR_SWAP 0x40 /* Scratch pad register swap */
1690 +#define UART_FCTR_RX 0x00 /* Programmable trigger mode select */
1691 +#define UART_FCTR_TX 0x80 /* Programmable trigger mode select */
1694 + * LCR=0xBF, FCTR[6]=1
1696 +//#define UART_EMSR 7 /* Extended Mode Select Register */
1697 +#define UART_EMSR_FIFO_COUNT 0x01 /* Rx/Tx select */
1698 +#define UART_EMSR_ALT_COUNT 0x02 /* Alternating count select */
1701 + * The Intel XScale on-chip UARTs define these bits
1703 +#define UART_IER_DMAE 0x80 /* DMA Requests Enable */
1704 +#define UART_IER_UUE 0x40 /* UART Unit Enable */
1705 +#define UART_IER_NRZE 0x20 /* NRZ coding Enable */
1706 +#define UART_IER_RTOIE 0x10 /* Receiver Time Out Interrupt Enable */
1708 +#define UART_IIR_TOD 0x08 /* Character Timeout Indication Detected */
1710 +#define UART_FCR_PXAR1 0x00 /* receive FIFO treshold = 1 */
1711 +#define UART_FCR_PXAR8 0x40 /* receive FIFO treshold = 8 */
1712 +#define UART_FCR_PXAR16 0x80 /* receive FIFO treshold = 16 */
1713 +#define UART_FCR_PXAR32 0xc0 /* receive FIFO treshold = 32 */
1719 + * These register definitions are for the 16C950
1721 +#define UART_ASR 0x01 /* Additional Status Register */
1722 +#define UART_RFL 0x03 /* Receiver FIFO level */
1723 +#define UART_TFL 0x04 /* Transmitter FIFO level */
1724 +#define UART_ICR 0x05 /* Index Control Register */
1726 +/* The 16950 ICR registers */
1727 +#define UART_ACR 0x00 /* Additional Control Register */
1728 +#define UART_CPR 0x01 /* Clock Prescalar Register */
1729 +#define UART_TCR 0x02 /* Times Clock Register */
1730 +#define UART_CKS 0x03 /* Clock Select Register */
1731 +#define UART_TTL 0x04 /* Transmitter Interrupt Trigger Level */
1732 +#define UART_RTL 0x05 /* Receiver Interrupt Trigger Level */
1733 +#define UART_FCL 0x06 /* Flow Control Level Lower */
1734 +#define UART_FCH 0x07 /* Flow Control Level Higher */
1735 +#define UART_ID1 0x08 /* ID #1 */
1736 +#define UART_ID2 0x09 /* ID #2 */
1737 +#define UART_ID3 0x0A /* ID #3 */
1738 +#define UART_REV 0x0B /* Revision */
1739 +#define UART_CSR 0x0C /* Channel Software Reset */
1740 +#define UART_NMR 0x0D /* Nine-bit Mode Register */
1741 +#define UART_CTR 0xFF
1744 + * The 16C950 Additional Control Reigster
1746 +#define UART_ACR_RXDIS 0x01 /* Receiver disable */
1747 +#define UART_ACR_TXDIS 0x02 /* Receiver disable */
1748 +#define UART_ACR_DSRFC 0x04 /* DSR Flow Control */
1749 +#define UART_ACR_TLENB 0x20 /* 950 trigger levels enable */
1750 +#define UART_ACR_ICRRD 0x40 /* ICR Read enable */
1751 +#define UART_ACR_ASREN 0x80 /* Additional status enable */
1756 + * These definitions are for the RSA-DV II/S card, from
1758 + * Kiyokazu SUTO <suto@ks-and-ks.ne.jp>
1761 +#define UART_RSA_BASE (-8)
1763 +#define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
1765 +#define UART_RSA_MSR_SWAP (1 << 0) /* Swap low/high 8 bytes in I/O port addr */
1766 +#define UART_RSA_MSR_FIFO (1 << 2) /* Enable the external FIFO */
1767 +#define UART_RSA_MSR_FLOW (1 << 3) /* Enable the auto RTS/CTS flow control */
1768 +#define UART_RSA_MSR_ITYP (1 << 4) /* Level (1) / Edge triger (0) */
1770 +#define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
1772 +#define UART_RSA_IER_Rx_FIFO_H (1 << 0) /* Enable Rx FIFO half full int. */
1773 +#define UART_RSA_IER_Tx_FIFO_H (1 << 1) /* Enable Tx FIFO half full int. */
1774 +#define UART_RSA_IER_Tx_FIFO_E (1 << 2) /* Enable Tx FIFO empty int. */
1775 +#define UART_RSA_IER_Rx_TOUT (1 << 3) /* Enable char receive timeout int */
1776 +#define UART_RSA_IER_TIMER (1 << 4) /* Enable timer interrupt */
1778 +#define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
1780 +#define UART_RSA_SRR_Tx_FIFO_NEMP (1 << 0) /* Tx FIFO is not empty (1) */
1781 +#define UART_RSA_SRR_Tx_FIFO_NHFL (1 << 1) /* Tx FIFO is not half full (1) */
1782 +#define UART_RSA_SRR_Tx_FIFO_NFUL (1 << 2) /* Tx FIFO is not full (1) */
1783 +#define UART_RSA_SRR_Rx_FIFO_NEMP (1 << 3) /* Rx FIFO is not empty (1) */
1784 +#define UART_RSA_SRR_Rx_FIFO_NHFL (1 << 4) /* Rx FIFO is not half full (1) */
1785 +#define UART_RSA_SRR_Rx_FIFO_NFUL (1 << 5) /* Rx FIFO is not full (1) */
1786 +#define UART_RSA_SRR_Rx_TOUT (1 << 6) /* Character reception timeout occurred (1) */
1787 +#define UART_RSA_SRR_TIMER (1 << 7) /* Timer interrupt occurred */
1789 +#define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
1791 +#define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
1793 +#define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
1795 +#define UART_RSA_TCR_SWITCH (1 << 0) /* Timer on */
1798 + * The RSA DSV/II board has two fixed clock frequencies. One is the
1799 + * standard rate, and the other is 8 times faster.
1801 +#define SERIAL_RSA_BAUD_BASE (921600)
1802 +#define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8)
1805 + * Extra serial register definitions for the internal UARTs
1806 + * in TI OMAP processors.
1808 +#define UART_OMAP_MDR1 0x08 /* Mode definition register */
1809 +#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */
1810 +#define UART_OMAP_SCR 0x10 /* Supplementary control register */
1811 +#define UART_OMAP_SSR 0x11 /* Supplementary status register */
1812 +#define UART_OMAP_EBLR 0x12 /* BOF length register */
1813 +#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */
1814 +#define UART_OMAP_MVER 0x14 /* Module version register */
1815 +#define UART_OMAP_SYSC 0x15 /* System configuration register */
1816 +#define UART_OMAP_SYSS 0x16 /* System status register */
1819 diff --git a/arch/mips/include/asm/rt2880/sizes.h b/arch/mips/include/asm/rt2880/sizes.h
1820 new file mode 100644
1821 index 0000000..7f50ae0
1823 +++ b/arch/mips/include/asm/rt2880/sizes.h
1826 + * This program is free software; you can redistribute it and/or modify
1827 + * it under the terms of the GNU General Public License as published by
1828 + * the Free Software Foundation; either version 2 of the License, or
1829 + * (at your option) any later version.
1831 + * This program is distributed in the hope that it will be useful,
1832 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1833 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1834 + * GNU General Public License for more details.
1836 + * You should have received a copy of the GNU General Public License
1837 + * along with this program; if not, write to the Free Software
1838 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1840 +/* DO NOT EDIT!! - this file automatically generated
1841 + * from .s file by awk -f s2h.awk
1843 +/* Size definitions
1844 + * Copyright (C) ARM Limited 1998. All rights reserved.
1848 +#define __sizes_h 1
1851 +#define SZ_1K 0x00000400
1852 +#define SZ_4K 0x00001000
1853 +#define SZ_8K 0x00002000
1854 +#define SZ_16K 0x00004000
1855 +#define SZ_64K 0x00010000
1856 +#define SZ_128K 0x00020000
1857 +#define SZ_256K 0x00040000
1858 +#define SZ_512K 0x00080000
1860 +#define SZ_1M 0x00100000
1861 +#define SZ_2M 0x00200000
1862 +#define SZ_4M 0x00400000
1863 +#define SZ_8M 0x00800000
1864 +#define SZ_16M 0x01000000
1865 +#define SZ_32M 0x02000000
1866 +#define SZ_64M 0x04000000
1867 +#define SZ_128M 0x08000000
1868 +#define SZ_256M 0x10000000
1869 +#define SZ_512M 0x20000000
1871 +#define SZ_1G 0x40000000
1872 +#define SZ_2G 0x80000000
1877 diff --git a/arch/mips/include/asm/rt2880/surfboard.h b/arch/mips/include/asm/rt2880/surfboard.h
1878 new file mode 100644
1879 index 0000000..373da34
1881 +++ b/arch/mips/include/asm/rt2880/surfboard.h
1884 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1886 + * ########################################################################
1888 + * This program is free software; you can distribute it and/or modify it
1889 + * under the terms of the GNU General Public License (Version 2) as
1890 + * published by the Free Software Foundation.
1892 + * This program is distributed in the hope it will be useful, but WITHOUT
1893 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1894 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1895 + * for more details.
1897 + * You should have received a copy of the GNU General Public License along
1898 + * with this program; if not, write to the Free Software Foundation, Inc.,
1899 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1901 + * ########################################################################
1904 +#ifndef _SURFBOARD_H
1905 +#define _SURFBOARD_H
1907 +#include <asm/addrspace.h>
1912 + * Surfboard system clock.
1913 + * This is the default value and maybe overidden by System Clock passed on the
1914 + * command line (sysclk=).
1916 +#define SURFBOARD_SYSTEM_CLOCK (125000000)
1919 + * Surfboard UART base baud rate = System Clock / 16.
1920 + * Ex. (14.7456 MHZ / 16) = 921600
1921 + * (32.0000 MHZ / 16) = 2000000
1923 +#define SURFBOARD_BAUD_DIV (16)
1924 +#define SURFBOARD_BASE_BAUD (SURFBOARD_SYSTEM_CLOCK / SURFBOARD_BAUD_DIV)
1927 + * Maximum number of IDE Controllers
1928 + * Surfboard only has one ide (ide0), so only 2 drives are
1929 + * possible. (no need to check for more hwifs.)
1931 +//#define MAX_IDE_HWIFS (1) /* Surfboard/Wakeboard */
1932 +#define MAX_IDE_HWIFS (2) /* Graphite board */
1934 +#define GCMP_BASE_ADDR 0x1fbf8000
1935 +#define GCMP_ADDRSPACE_SZ (256 * 1024)
1938 + * * GIC Specific definitions
1940 +#define GIC_BASE_ADDR 0x1fbc0000
1941 +#define GIC_ADDRSPACE_SZ (128 * 1024)
1942 +#define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE)
1944 +/* GIC's Nomenclature for Core Interrupt Pins */
1945 +#define GIC_CPU_INT0 0 /* Core Interrupt 2 */
1946 +#define GIC_CPU_INT1 1 /* . */
1947 +#define GIC_CPU_INT2 2 /* . */
1948 +#define GIC_CPU_INT3 3 /* . */
1949 +#define GIC_CPU_INT4 4 /* . */
1950 +#define GIC_CPU_INT5 5 /* Core Interrupt 5 */
1952 +#endif /* !(_SURFBOARD_H) */
1953 diff --git a/arch/mips/include/asm/rt2880/surfboardint.h b/arch/mips/include/asm/rt2880/surfboardint.h
1954 new file mode 100644
1955 index 0000000..671cca5
1957 +++ b/arch/mips/include/asm/rt2880/surfboardint.h
1960 + * Copyright (C) 2001 Palmchip Corporation. All rights reserved.
1962 + * ########################################################################
1964 + * This program is free software; you can distribute it and/or modify it
1965 + * under the terms of the GNU General Public License (Version 2) as
1966 + * published by the Free Software Foundation.
1968 + * This program is distributed in the hope it will be useful, but WITHOUT
1969 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1970 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
1971 + * for more details.
1973 + * You should have received a copy of the GNU General Public License along
1974 + * with this program; if not, write to the Free Software Foundation, Inc.,
1975 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
1977 + * ########################################################################
1979 + * Defines for the Surfboard interrupt controller.
1982 +#ifndef _SURFBOARDINT_H
1983 +#define _SURFBOARDINT_H
1985 +/* Number of IRQ supported on hw interrupt 0. */
1986 +#if defined (CONFIG_RALINK_RT2880)
1987 +#define RALINK_CPU_TIMER_IRQ 6 /* mips timer */
1988 +#define SURFBOARDINT_GPIO 7 /* GPIO */
1989 +#define SURFBOARDINT_UART1 8 /* UART Lite */
1990 +#define SURFBOARDINT_UART 9 /* UART */
1991 +#define SURFBOARDINT_TIMER0 10 /* timer0 */
1992 +#elif defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT2883) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined (CONFIG_RALINK_MT7620)
1993 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
1994 +#define SURFBOARDINT_GPIO 6 /* GPIO */
1995 +#define SURFBOARDINT_DMA 7 /* DMA */
1996 +#define SURFBOARDINT_NAND 8 /* NAND */
1997 +#define SURFBOARDINT_PC 9 /* Performance counter */
1998 +#define SURFBOARDINT_I2S 10 /* I2S */
1999 +#define SURFBOARDINT_SDXC 14 /* SDXC */
2000 +#define SURFBOARDINT_ESW 17 /* ESW */
2001 +#define SURFBOARDINT_UART1 12 /* UART Lite */
2002 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
2003 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
2004 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
2005 +#define SURFBOARDINT_WDG 34 /* watch dog */
2006 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2007 +#define SURFBOARDINT_PCM 36 /* PCM */
2008 +#define SURFBOARDINT_UART 37 /* UART */
2009 +#define RALINK_INT_PCIE0 13 /* PCIE0 */
2010 +#define RALINK_INT_PCIE1 14 /* PCIE1 */
2013 +#elif defined (CONFIG_RALINK_MT7628)
2014 +#define SURFBOARDINT_SYSCTL 0 /* SYSCTL */
2015 +#define SURFBOARDINT_PCM 4 /* PCM */
2016 +#define SURFBOARDINT_GPIO 6 /* GPIO */
2017 +#define SURFBOARDINT_DMA 7 /* DMA */
2018 +#define SURFBOARDINT_PC 9 /* Performance counter */
2019 +#define SURFBOARDINT_I2S 10 /* I2S */
2020 +#define SURFBOARDINT_SPI 11 /* SPI */
2021 +#define SURFBOARDINT_AES 13 /* AES */
2022 +#define SURFBOARDINT_CRYPTO 13 /* CryptoEngine */
2023 +#define SURFBOARDINT_SDXC 14 /* SDXC */
2024 +#define SURFBOARDINT_ESW 17 /* ESW */
2025 +#define SURFBOARDINT_USB 18 /* USB */
2026 +#define SURFBOARDINT_UART_LITE1 20 /* UART Lite */
2027 +#define SURFBOARDINT_UART_LITE2 21 /* UART Lite */
2028 +#define SURFBOARDINT_UART_LITE3 22 /* UART Lite */
2029 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1
2030 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2
2031 +#define SURFBOARDINT_WDG 23 /* WDG timer */
2032 +#define SURFBOARDINT_TIMER0 24 /* Timer0 */
2033 +#define SURFBOARDINT_TIMER1 25 /* Timer1 */
2034 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2035 +#define RALINK_INT_PCIE0 2 /* PCIE0 */
2038 +#elif defined (CONFIG_RALINK_MT7621)
2040 +#define SURFBOARDINT_FE 3 /* FE */
2041 +#define SURFBOARDINT_PCIE0 4 /* PCIE0 */
2042 +#define SURFBOARDINT_SYSCTL 6 /* SYSCTL */
2043 +#define SURFBOARDINT_I2C 8 /* I2C */
2044 +#define SURFBOARDINT_DRAMC 9 /* DRAMC */
2045 +#define SURFBOARDINT_PCM 10 /* PCM */
2046 +#define SURFBOARDINT_HSGDMA 11 /* HSGDMA */
2047 +#define SURFBOARDINT_GPIO 12 /* GPIO */
2048 +#define SURFBOARDINT_DMA 13 /* GDMA */
2049 +#define SURFBOARDINT_NAND 14 /* NAND */
2050 +#define SURFBOARDINT_NAND_ECC 15 /* NFI ECC */
2051 +#define SURFBOARDINT_I2S 16 /* I2S */
2052 +#define SURFBOARDINT_SPI 17 /* SPI */
2053 +#define SURFBOARDINT_SPDIF 18 /* SPDIF */
2054 +#define SURFBOARDINT_CRYPTO 19 /* CryptoEngine */
2055 +#define SURFBOARDINT_SDXC 20 /* SDXC */
2056 +#define SURFBOARDINT_PCTRL 21 /* Performance counter */
2057 +#define SURFBOARDINT_USB 22 /* USB */
2058 +#define SURFBOARDINT_ESW 31 /* Switch */
2059 +#define SURFBOARDINT_PCIE1 24 /* PCIE1 */
2060 +#define SURFBOARDINT_PCIE2 25 /* PCIE2 */
2061 +#define SURFBOARDINT_UART_LITE1 26 /* UART Lite */
2062 +#define SURFBOARDINT_UART_LITE2 27 /* UART Lite */
2063 +#define SURFBOARDINT_UART_LITE3 28 /* UART Lite */
2064 +#define SURFBOARDINT_UART SURFBOARDINT_UART_LITE2 //ttyS0
2065 +#define SURFBOARDINT_UART1 SURFBOARDINT_UART_LITE1 //ttyS1
2067 +#define SURFBOARDINT_WDG 29 /* WDG timer */
2068 +#define SURFBOARDINT_TIMER0 30 /* Timer0 */
2069 +#define SURFBOARDINT_TIMER1 31 /* Timer1 */
2071 +#define RALINK_INT_PCIE0 SURFBOARDINT_PCIE0
2072 +#define RALINK_INT_PCIE1 SURFBOARDINT_PCIE1
2073 +#define RALINK_INT_PCIE2 SURFBOARDINT_PCIE2
2075 +#elif defined (CONFIG_RALINK_RT3883)
2076 +#define RALINK_CPU_TIMER_IRQ 5 /* mips timer */
2077 +#define SURFBOARDINT_GPIO 6 /* GPIO */
2078 +#define SURFBOARDINT_DMA 7 /* DMA */
2079 +#define SURFBOARDINT_NAND 8 /* NAND */
2080 +#define SURFBOARDINT_PC 9 /* Performance counter */
2081 +#define SURFBOARDINT_I2S 10 /* I2S */
2082 +#define SURFBOARDINT_UART1 12 /* UART Lite */
2083 +#define SURFBOARDINT_PCI 18 /* PCI */
2084 +#define SURFBOARDINT_UDEV 19 /* USB Device */
2085 +#define SURFBOARDINT_UHST 20 /* USB Host */
2086 +#define SURFBOARDINT_SYSCTL 32 /* SYSCTL */
2087 +#define SURFBOARDINT_TIMER0 33 /* timer0 */
2088 +#define SURFBOARDINT_ILL_ACC 35 /* illegal access */
2089 +#define SURFBOARDINT_PCM 36 /* PCM */
2090 +#define SURFBOARDINT_UART 37 /* UART */
2093 +#define SURFBOARDINT_END 64
2094 +#define RT2880_INTERINT_START 40
2096 +/* Global interrupt bit definitions */
2097 +#define C_SURFBOARD_GLOBAL_INT 31
2098 +#define M_SURFBOARD_GLOBAL_INT (1 << C_SURFBOARD_GLOBAL_INT)
2101 +#define RALINK_SDRAM_ILL_ACC_ADDR *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x310)
2102 +#define RALINK_SDRAM_ILL_ACC_TYPE *(volatile u32 *)(RALINK_SYSCTL_BASE + 0x314)
2103 +/* end of added, bobtseng */
2106 + * Surfboard registers are memory mapped on 32-bit aligned boundaries and
2107 + * only word access are allowed.
2109 +#if defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2110 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x9C) //IRQ_STAT
2111 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0xA0) //FIQ_STAT
2112 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x6C) //FIQ_SEL
2113 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0xA4) //INT_PURE
2114 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x80) //IRQ_MASK_SET
2115 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x78) //IRQ_MASK_CLR
2117 +#define RALINK_IRQ0STAT (RALINK_INTCL_BASE + 0x0)
2118 +#define RALINK_IRQ1STAT (RALINK_INTCL_BASE + 0x4)
2119 +#define RALINK_INTTYPE (RALINK_INTCL_BASE + 0x20)
2120 +#define RALINK_INTRAW (RALINK_INTCL_BASE + 0x30)
2121 +#define RALINK_INTENA (RALINK_INTCL_BASE + 0x34)
2122 +#define RALINK_INTDIS (RALINK_INTCL_BASE + 0x38)
2125 +/* bobtseng added ++, 2006.3.6. */
2126 +#define read_32bit_cp0_register(source) \
2128 + __asm__ __volatile__( \
2129 + ".set\tpush\n\t" \
2130 + ".set\treorder\n\t" \
2131 + "mfc0\t%0,"STR(source)"\n\t" \
2133 + : "=r" (__res)); \
2136 +#define write_32bit_cp0_register(register,value) \
2137 + __asm__ __volatile__( \
2138 + "mtc0\t%0,"STR(register)"\n\t" \
2142 +/* bobtseng added --, 2006.3.6. */
2144 +void surfboardint_init(void);
2145 +u32 get_surfboard_sysclk(void);
2148 +#endif /* !(_SURFBOARDINT_H) */
2149 diff --git a/arch/mips/include/asm/rt2880/war.h b/arch/mips/include/asm/rt2880/war.h
2150 new file mode 100644
2151 index 0000000..7c6931d
2153 +++ b/arch/mips/include/asm/rt2880/war.h
2156 + * This file is subject to the terms and conditions of the GNU General Public
2157 + * License. See the file "COPYING" in the main directory of this archive
2158 + * for more details.
2160 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
2162 +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
2163 +#define __ASM_MIPS_MACH_MIPS_WAR_H
2165 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
2166 +#define R4600_V1_HIT_CACHEOP_WAR 0
2167 +#define R4600_V2_HIT_CACHEOP_WAR 0
2168 +#define R5432_CP0_INTERRUPT_WAR 0
2169 +#define BCM1250_M3_WAR 0
2170 +#define SIBYTE_1956_WAR 0
2171 +#define MIPS4K_ICACHE_REFILL_WAR 1
2172 +#define MIPS_CACHE_SYNC_WAR 1
2173 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
2174 +#define RM9000_CDEX_SMP_WAR 0
2175 +#define ICACHE_REFILLS_WORKAROUND_WAR 1
2176 +#define R10000_LLSC_WAR 0
2177 +#define MIPS34K_MISSED_ITLB_WAR 0
2179 +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
2180 diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
2181 index ef6a274..1b9b3b2 100644
2182 --- a/drivers/net/ethernet/Kconfig
2183 +++ b/drivers/net/ethernet/Kconfig
2184 @@ -135,6 +135,7 @@ source "drivers/net/ethernet/packetengines/Kconfig"
2185 source "drivers/net/ethernet/pasemi/Kconfig"
2186 source "drivers/net/ethernet/qlogic/Kconfig"
2187 source "drivers/net/ethernet/ralink/Kconfig"
2188 +source "drivers/net/ethernet/raeth/Kconfig"
2189 source "drivers/net/ethernet/realtek/Kconfig"
2190 source "drivers/net/ethernet/renesas/Kconfig"
2191 source "drivers/net/ethernet/rdc/Kconfig"
2192 diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
2193 index 7c3eb7b..e66b3bb 100644
2194 --- a/drivers/net/ethernet/Makefile
2195 +++ b/drivers/net/ethernet/Makefile
2196 @@ -57,6 +57,7 @@ obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
2197 obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
2198 obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
2199 obj-$(CONFIG_NET_RALINK) += ralink/
2200 +obj-$(CONFIG_RAETH) += raeth/
2201 obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
2202 obj-$(CONFIG_SH_ETH) += renesas/
2203 obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
2204 diff --git a/drivers/net/ethernet/raeth/Kconfig b/drivers/net/ethernet/raeth/Kconfig
2205 new file mode 100644
2206 index 0000000..e24b52c
2208 +++ b/drivers/net/ethernet/raeth/Kconfig
2219 + depends on SOC_MT7621
2221 +config RALINK_MT7621
2224 + depends on SOC_MT7621
2227 + tristate "Ralink GMAC"
2228 + depends on SOC_MT7621
2230 + This driver supports Ralink gigabit ethernet family of
2235 + default y if (RALINK_MT7620 || RALINK_MT7621)
2238 +config RAETH_SCATTER_GATHER_RX_DMA
2240 + default y if (RALINK_MT7620 || RALINK_MT7621)
2245 + prompt "Network BottomHalves"
2247 + default RA_NETWORK_WORKQUEUE_BH
2249 + config RA_NETWORK_TASKLET_BH
2252 + config RA_NETWORK_WORKQUEUE_BH
2260 +#config TASKLET_WORKQUEUE_SW
2261 +# bool "Tasklet and Workqueue switch"
2262 +# depends on RA_NETWORK_TASKLET_BH
2264 +config RAETH_SKB_RECYCLE_2K
2265 + bool "SKB Recycling"
2268 +config RAETH_SPECIAL_TAG
2269 + bool "Ralink Special Tag (0x810x)"
2270 + depends on RAETH && RT_3052_ESW
2272 +#config RAETH_JUMBOFRAME
2273 +# bool "Jumbo Frame up to 4K bytes"
2274 +# depends on RAETH && !(RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_MT7628)
2276 +config RAETH_CHECKSUM_OFFLOAD
2277 + bool "TCP/UDP/IP checksum offload"
2279 + depends on RAETH && !RALINK_RT2880
2281 +#config RAETH_SW_FC
2282 +# bool "When TX ring is full, inform kernel stop transmit and stop RX handler"
2287 + bool "32bytes TX/RX description"
2289 + depends on RAETH && (RALINK_MT7620 || RALINK_MT7621)
2291 + At this moment, you cannot enable 32B description with Multiple RX ring at the same time.
2294 + bool "LRO (Large Receive Offload )"
2296 + depends on RAETH && (RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621)
2298 +config RAETH_HW_VLAN_TX
2299 + bool "Transmit VLAN HW (DoubleVLAN is not supported)"
2300 + depends on RAETH && !(RALINK_RT5350 || RALINK_MT7628)
2302 + Please disable HW_VLAN_TX if you need double vlan
2304 +config RAETH_HW_VLAN_RX
2305 + bool "Receive VLAN HW (DoubleVLAN is not supported)"
2306 + depends on RAETH && RALINK_MT7621
2308 + Please disable HW_VLAN_RX if you need double vlan
2311 + bool "TSOV4 (Tcp Segmentaton Offload)"
2312 + depends on (RAETH_HW_VLAN_TX && (RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)) || RALINK_MT7621
2315 + bool "TSOV6 (Tcp Segmentaton Offload)"
2316 + depends on RAETH_TSO
2318 +config RAETH_RW_PDMAPTR_FROM_VAR
2320 + default y if RALINK_RT6855A || RALINK_MT7620
2324 +# bool "QoS Feature"
2325 +# depends on RAETH && !RALINK_RT2880 && !RALINK_MT7620 && !RALINK_MT7621 && !RAETH_TSO
2329 + depends on RAETH_QOS
2330 + default DSCP_QOS_DSCP
2332 +config RAETH_QOS_DSCP_BASED
2334 + depends on RAETH_QOS
2336 +config RAETH_QOS_VPRI_BASED
2338 + depends on RAETH_QOS
2343 + bool "Choose QDMA instead PDMA"
2345 + depends on RAETH && RALINK_MT7621
2348 + prompt "GMAC is connected to"
2350 + default GE1_RGMII_FORCE_1000
2352 +config GE1_MII_FORCE_100
2353 + bool "MII_FORCE_100 (10/100M Switch)"
2354 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2357 + bool "MII_AN (100Phy)"
2358 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2360 +config GE1_RVMII_FORCE_100
2361 + bool "RvMII_FORCE_100 (CPU)"
2362 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2364 +config GE1_RGMII_FORCE_1000
2365 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2366 + depends on (RALINK_RT2880 || RALINK_RT3883)
2369 +config GE1_RGMII_FORCE_1000
2370 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2371 + depends on (RALINK_MT7621)
2372 + select RT_3052_ESW
2374 +config GE1_TRGMII_FORCE_1200
2375 + bool "TRGMII_FORCE_1200 (GigaSW, CPU)"
2376 + depends on (RALINK_MT7621)
2377 + select RT_3052_ESW
2379 +config GE1_RGMII_AN
2380 + bool "RGMII_AN (GigaPhy)"
2381 + depends on (RALINK_RT2880 || RALINK_RT3883 || RALINK_MT7621)
2383 +config GE1_RGMII_NONE
2384 + bool "NONE (NO CONNECT)"
2385 + depends on (RALINK_MT7621)
2390 + bool "Ralink Embedded Switch"
2392 + depends on (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT5350 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620 || RALINK_MT7621 || RALINK_MT7628)
2394 +config LAN_WAN_SUPPORT
2395 + bool "LAN/WAN Partition"
2396 + depends on RAETH_ROUTER || RT_3052_ESW
2399 + prompt "Switch Board Layout Type"
2400 + depends on LAN_WAN_SUPPORT || P5_RGMII_TO_MAC_MODE || GE1_RGMII_FORCE_1000 || GE1_TRGMII_FORCE_1200 || GE2_RGMII_FORCE_1000
2410 +config RALINK_VISTA_BASIC
2411 + bool 'Vista Basic Logo for IC+ 175C'
2412 + depends on LAN_WAN_SUPPORT && (RALINK_RT2880 || RALINK_RT3883)
2414 +config ESW_DOUBLE_VLAN_TAG
2416 + default y if RT_3052_ESW
2418 +config RAETH_HAS_PORT4
2419 + bool "Port 4 Support"
2420 + depends on RAETH && RALINK_MT7620
2422 + prompt "Target Mode"
2423 + depends on RAETH_HAS_PORT4
2424 + default P4_RGMII_TO_MAC_MODE
2426 + config P4_MAC_TO_PHY_MODE
2427 + bool "Giga_Phy (RGMII)"
2428 + config GE_RGMII_MT7530_P0_AN
2429 + bool "GE_RGMII_MT7530_P0_AN (MT7530 Internal GigaPhy)"
2430 + config GE_RGMII_MT7530_P4_AN
2431 + bool "GE_RGMII_MT7530_P4_AN (MT7530 Internal GigaPhy)"
2432 + config P4_RGMII_TO_MAC_MODE
2433 + bool "Giga_SW/iNIC (RGMII)"
2434 + config P4_MII_TO_MAC_MODE
2435 + bool "External_CPU (MII_RvMII)"
2436 + config P4_RMII_TO_MAC_MODE
2437 + bool "External_CPU (RvMII_MII)"
2440 +config MAC_TO_GIGAPHY_MODE_ADDR2
2441 + hex "Port4 Phy Address"
2443 + depends on P4_MAC_TO_PHY_MODE
2445 +config RAETH_HAS_PORT5
2446 + bool "Port 5 Support"
2447 + depends on RAETH && (RALINK_RT3052 || RALINK_RT3352 || RALINK_RT6855 || RALINK_RT6855A || RALINK_MT7620)
2449 + prompt "Target Mode"
2450 + depends on RAETH_HAS_PORT5
2451 + default P5_RGMII_TO_MAC_MODE
2453 + config P5_MAC_TO_PHY_MODE
2454 + bool "Giga_Phy (RGMII)"
2455 + config P5_RGMII_TO_MAC_MODE
2456 + bool "Giga_SW/iNIC (RGMII)"
2457 + config P5_RGMII_TO_MT7530_MODE
2458 + bool "MT7530 Giga_SW (RGMII)"
2459 + depends on RALINK_MT7620
2460 + config P5_MII_TO_MAC_MODE
2461 + bool "External_CPU (MII_RvMII)"
2462 + config P5_RMII_TO_MAC_MODE
2463 + bool "External_CPU (RvMII_MII)"
2466 +config MAC_TO_GIGAPHY_MODE_ADDR
2467 + hex "GE1 Phy Address"
2469 + depends on GE1_MII_AN || GE1_RGMII_AN
2471 +config MAC_TO_GIGAPHY_MODE_ADDR
2472 + hex "Port5 Phy Address"
2474 + depends on P5_MAC_TO_PHY_MODE
2477 + bool "GMAC2 Support"
2478 + depends on RAETH && (RALINK_RT3883 || RALINK_MT7621)
2481 + prompt "GMAC2 is connected to"
2482 + depends on RAETH_GMAC2
2483 + default GE2_RGMII_AN
2485 +config GE2_MII_FORCE_100
2486 + bool "MII_FORCE_100 (10/100M Switch)"
2487 + depends on RAETH_GMAC2
2490 + bool "MII_AN (100Phy)"
2491 + depends on RAETH_GMAC2
2493 +config GE2_RVMII_FORCE_100
2494 + bool "RvMII_FORCE_100 (CPU)"
2495 + depends on RAETH_GMAC2
2497 +config GE2_RGMII_FORCE_1000
2498 + bool "RGMII_FORCE_1000 (GigaSW, CPU)"
2499 + depends on RAETH_GMAC2
2502 +config GE2_RGMII_AN
2503 + bool "RGMII_AN (GigaPhy)"
2504 + depends on RAETH_GMAC2
2506 +config GE2_INTERNAL_GPHY
2507 + bool "Internal GigaPHY"
2508 + depends on RAETH_GMAC2
2509 + select LAN_WAN_SUPPORT
2513 +config GE_RGMII_INTERNAL_P0_AN
2515 + depends on GE2_INTERNAL_GPHY
2516 + default y if WAN_AT_P0
2518 +config GE_RGMII_INTERNAL_P4_AN
2520 + depends on GE2_INTERNAL_GPHY
2521 + default y if WAN_AT_P4
2523 +config MAC_TO_GIGAPHY_MODE_ADDR2
2525 + default 0 if GE_RGMII_INTERNAL_P0_AN
2526 + default 4 if GE_RGMII_INTERNAL_P4_AN
2527 + depends on GE_RGMII_INTERNAL_P0_AN || GE_RGMII_INTERNAL_P4_AN
2529 +config MAC_TO_GIGAPHY_MODE_ADDR2
2530 + hex "GE2 Phy Address"
2532 + depends on GE2_MII_AN || GE2_RGMII_AN
2535 +config RAETH_ROUTER
2537 +default y if GE1_MII_FORCE_100 || GE2_MII_FORCE_100 || GE1_RVMII_FORCE_100 || GE2_RVMII_FORCE_100
2540 +config MAC_TO_MAC_MODE
2542 +default y if GE1_RGMII_FORCE_1000 || GE2_RGMII_FORCE_1000
2543 +depends on (RALINK_RT2880 || RALINK_RT3883)
2548 +default y if GE1_RGMII_AN || GE2_RGMII_AN
2553 +default y if GE1_MII_AN || GE2_MII_AN
2554 diff --git a/drivers/net/ethernet/raeth/Makefile b/drivers/net/ethernet/raeth/Makefile
2555 new file mode 100644
2556 index 0000000..94c19bd
2558 +++ b/drivers/net/ethernet/raeth/Makefile
2560 +obj-$(CONFIG_RAETH) += raeth.o
2561 +raeth-objs := ra_mac.o mii_mgr.o
2562 +raeth-objs += raether_pdma.o
2563 +EXTRA_CFLAGS += -DWORKQUEUE_BH
2564 +#EXTRA_CFLAGS += -DCONFIG_RAETH_MULTIPLE_RX_RING
2566 +raeth-objs += raether.o
2567 diff --git a/drivers/net/ethernet/raeth/ethtool_readme.txt b/drivers/net/ethernet/raeth/ethtool_readme.txt
2568 new file mode 100644
2569 index 0000000..10e918b
2571 +++ b/drivers/net/ethernet/raeth/ethtool_readme.txt
2574 +Ethtool readme for selecting different PHY address.
2576 +Before doing any ethtool command you should make sure the current PHY
2577 +address is expected. The default PHY address is 1(port 1).
2579 +You can change current PHY address to X(0~4) by doing follow command:
2580 +# echo X > /proc/rt2880/gmac
2582 +Ethtool command also would show the current PHY address as following.
2586 + Supported ports: [ TP MII ]
2587 + Supported link modes: 10baseT/Half 10baseT/Full
2588 + 100baseT/Half 100baseT/Full
2589 + Supports auto-negotiation: Yes
2590 + Advertised link modes: 10baseT/Half 10baseT/Full
2591 + 100baseT/Half 100baseT/Full
2592 + Advertised auto-negotiation: No
2597 + Transceiver: internal
2598 + Auto-negotiation: off
2599 + Current message level: 0x00000000 (0)
2603 +The "PHYAD" field shows the current PHY address.
2609 +# echo 1 > /proc/rt2880/gmac # change phy address to 1
2613 +# echo 0 > /proc/rt2880/gmac # change phy address to 0
2617 diff --git a/drivers/net/ethernet/raeth/mii_mgr.c b/drivers/net/ethernet/raeth/mii_mgr.c
2618 new file mode 100644
2619 index 0000000..3de0a74
2621 +++ b/drivers/net/ethernet/raeth/mii_mgr.c
2623 +#include <linux/module.h>
2624 +#include <linux/version.h>
2625 +#include <linux/netdevice.h>
2627 +#include <linux/kernel.h>
2628 +#include <linux/sched.h>
2629 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
2630 +#include <asm/rt2880/rt_mmap.h>
2633 +#include "ra2882ethreg.h"
2634 +#include "raether.h"
2637 +#define PHY_CONTROL_0 0x0004
2638 +#define MDIO_PHY_CONTROL_0 (RALINK_ETH_SW_BASE + PHY_CONTROL_0)
2639 +#define enable_mdio(x)
2642 +u32 __mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2644 + u32 volatile status = 0;
2646 + unsigned long volatile t_start = jiffies;
2647 + u32 volatile data = 0;
2649 + /* We enable mdio gpio purpose register, and disable it when exit. */
2652 + // make sure previous read operation is complete
2654 + // 0 : Read/write operation complete
2655 + if(!( sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2659 + else if (time_after(jiffies, t_start + 5*HZ)) {
2661 + printk("\n MDIO Read operation is ongoing !!\n");
2666 + data = (0x01 << 16) | (0x02 << 18) | (phy_addr << 20) | (phy_register << 25);
2667 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2669 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2670 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2673 + // make sure read operation is complete
2674 + t_start = jiffies;
2676 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) {
2677 + status = sysRegRead(MDIO_PHY_CONTROL_0);
2678 + *read_data = (u32)(status & 0x0000FFFF);
2683 + else if (time_after(jiffies, t_start+5*HZ)) {
2685 + printk("\n MDIO Read operation is ongoing and Time Out!!\n");
2691 +u32 __mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2693 + unsigned long volatile t_start=jiffies;
2694 + u32 volatile data;
2698 + // make sure previous write operation is complete
2700 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31)))
2704 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2706 + printk("\n MDIO Write operation ongoing\n");
2710 + /*add 1 us delay to make sequencial write more robus*/
2713 + data = (0x01 << 16)| (1<<18) | (phy_addr << 20) | (phy_register << 25) | write_data;
2714 + sysRegWrite(MDIO_PHY_CONTROL_0, data);
2716 + sysRegWrite(MDIO_PHY_CONTROL_0, data); //start operation
2717 + //printk("\n Set Command [0x%08X] to PHY !!\n",MDIO_PHY_CONTROL_0);
2719 + t_start = jiffies;
2721 + // make sure write operation is complete
2723 + if (!(sysRegRead(MDIO_PHY_CONTROL_0) & (0x1 << 31))) //0 : Read/write operation complete
2728 + else if (time_after(jiffies, t_start + 5 * HZ)) {
2730 + printk("\n MDIO Write operation Time Out\n");
2736 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data)
2742 + //phase1: write page address phase
2743 + if(__mii_mgr_write(phy_addr, 0x1f, ((phy_register >> 6) & 0x3FF))) {
2744 + //phase2: write address & read low word phase
2745 + if(__mii_mgr_read(phy_addr, (phy_register >> 2) & 0xF, &low_word)) {
2746 + //phase3: write address & read high word phase
2747 + if(__mii_mgr_read(phy_addr, (0x1 << 4), &high_word)) {
2748 + *read_data = (high_word << 16) | (low_word & 0xFFFF);
2755 + if(__mii_mgr_read(phy_addr, phy_register, read_data)) {
2763 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data)
2765 + if(phy_addr == 31)
2767 + //phase1: write page address phase
2768 + if(__mii_mgr_write(phy_addr, 0x1f, (phy_register >> 6) & 0x3FF)) {
2769 + //phase2: write address & read low word phase
2770 + if(__mii_mgr_write(phy_addr, ((phy_register >> 2) & 0xF), write_data & 0xFFFF)) {
2771 + //phase3: write address & read high word phase
2772 + if(__mii_mgr_write(phy_addr, (0x1 << 4), write_data >> 16)) {
2779 + if(__mii_mgr_write(phy_addr, phy_register, write_data)) {
2787 +EXPORT_SYMBOL(mii_mgr_write);
2788 +EXPORT_SYMBOL(mii_mgr_read);
2789 diff --git a/drivers/net/ethernet/raeth/ra2882ethreg.h b/drivers/net/ethernet/raeth/ra2882ethreg.h
2790 new file mode 100644
2791 index 0000000..05b789e
2793 +++ b/drivers/net/ethernet/raeth/ra2882ethreg.h
2795 +#ifndef RA2882ETHREG_H
2796 +#define RA2882ETHREG_H
2798 +#include <linux/mii.h> // for struct mii_if_info in ra2882ethreg.h
2799 +#include <linux/version.h> /* check linux version for 2.4 and 2.6 compatibility */
2801 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
2802 +#include <asm/rt2880/rt_mmap.h>
2804 +#include "raether.h"
2806 +#ifdef WORKQUEUE_BH
2807 +#include <linux/workqueue.h>
2808 +#endif // WORKQUEUE_BH //
2809 +#ifdef CONFIG_RAETH_LRO
2810 +#include <linux/inet_lro.h>
2813 +#define MAX_PACKET_SIZE 1514
2814 +#define MIN_PACKET_SIZE 60
2816 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
2818 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
2819 +#define BIT(x) ((1 << x))
2821 +#define ETHER_ADDR_LEN 6
2823 +/* Phy Vender ID list */
2825 +#define EV_ICPLUS_PHY_ID0 0x0243
2826 +#define EV_ICPLUS_PHY_ID1 0x0D90
2827 +#define EV_MARVELL_PHY_ID0 0x0141
2828 +#define EV_MARVELL_PHY_ID1 0x0CC2
2829 +#define EV_VTSS_PHY_ID0 0x0007
2830 +#define EV_VTSS_PHY_ID1 0x0421
2835 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2836 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
2838 +#define RX_COHERENT BIT(31)
2839 +#define RX_DLY_INT BIT(30)
2840 +#define TX_COHERENT BIT(29)
2841 +#define TX_DLY_INT BIT(28)
2843 +#define RX_DONE_INT1 BIT(17)
2844 +#define RX_DONE_INT0 BIT(16)
2846 +#define TX_DONE_INT3 BIT(3)
2847 +#define TX_DONE_INT2 BIT(2)
2848 +#define TX_DONE_INT1 BIT(1)
2849 +#define TX_DONE_INT0 BIT(0)
2851 +#if defined (CONFIG_RALINK_MT7621)
2852 +#define RLS_COHERENT BIT(29)
2853 +#define RLS_DLY_INT BIT(28)
2854 +#define RLS_DONE_INT BIT(0)
2858 +//#define CNT_PPE_AF BIT(31)
2859 +//#define CNT_GDM_AF BIT(29)
2860 +#define PSE_P2_FC BIT(26)
2861 +#define GDM_CRC_DROP BIT(25)
2862 +#define PSE_BUF_DROP BIT(24)
2863 +#define GDM_OTHER_DROP BIT(23)
2864 +#define PSE_P1_FC BIT(22)
2865 +#define PSE_P0_FC BIT(21)
2866 +#define PSE_FQ_EMPTY BIT(20)
2867 +#define GE1_STA_CHG BIT(18)
2868 +#define TX_COHERENT BIT(17)
2869 +#define RX_COHERENT BIT(16)
2871 +#define TX_DONE_INT3 BIT(11)
2872 +#define TX_DONE_INT2 BIT(10)
2873 +#define TX_DONE_INT1 BIT(9)
2874 +#define TX_DONE_INT0 BIT(8)
2875 +#define RX_DONE_INT1 RX_DONE_INT0
2876 +#define RX_DONE_INT0 BIT(2)
2877 +#define TX_DLY_INT BIT(1)
2878 +#define RX_DLY_INT BIT(0)
2881 +#define FE_INT_ALL (TX_DONE_INT3 | TX_DONE_INT2 | \
2882 + TX_DONE_INT1 | TX_DONE_INT0 | \
2885 +#if defined (CONFIG_RALINK_MT7621)
2886 +#define QFE_INT_ALL (RLS_DONE_INT | RX_DONE_INT0 | RX_DONE_INT1)
2887 +#define QFE_INT_DLY_INIT (RLS_DLY_INT | RX_DLY_INT)
2889 +#define NUM_QDMA_PAGE 256
2890 +#define QDMA_PAGE_SIZE 2048
2895 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
2896 +#define PORT0_QUEUE_FULL BIT(14) //port0 queue full
2897 +#define PORT1_QUEUE_FULL BIT(15) //port1 queue full
2898 +#define PORT2_QUEUE_FULL BIT(16) //port2 queue full
2899 +#define PORT3_QUEUE_FULL BIT(17) //port3 queue full
2900 +#define PORT4_QUEUE_FULL BIT(18) //port4 queue full
2901 +#define PORT5_QUEUE_FULL BIT(19) //port5 queue full
2902 +#define PORT6_QUEUE_FULL BIT(20) //port6 queue full
2903 +#define SHARED_QUEUE_FULL BIT(23) //shared queue full
2904 +#define QUEUE_EXHAUSTED BIT(24) //global queue is used up and all packets are dropped
2905 +#define BC_STROM BIT(25) //the device is undergoing broadcast storm
2906 +#define PORT_ST_CHG BIT(26) //Port status change
2907 +#define UNSECURED_ALERT BIT(27) //Intruder alert
2908 +#define ABNORMAL_ALERT BIT(28) //Abnormal
2910 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x00)
2911 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x04)
2912 +#define ESW_INT_ALL (PORT_ST_CHG)
2914 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
2915 + defined (CONFIG_RALINK_MT7620)
2916 +#define MIB_INT BIT(25)
2917 +#define ACL_INT BIT(24)
2918 +#define P5_LINK_CH BIT(5)
2919 +#define P4_LINK_CH BIT(4)
2920 +#define P3_LINK_CH BIT(3)
2921 +#define P2_LINK_CH BIT(2)
2922 +#define P1_LINK_CH BIT(1)
2923 +#define P0_LINK_CH BIT(0)
2925 +#define RX_GOCT_CNT BIT(4)
2926 +#define RX_GOOD_CNT BIT(6)
2927 +#define TX_GOCT_CNT BIT(17)
2928 +#define TX_GOOD_CNT BIT(19)
2930 +#define MSK_RX_GOCT_CNT BIT(4)
2931 +#define MSK_RX_GOOD_CNT BIT(6)
2932 +#define MSK_TX_GOCT_CNT BIT(17)
2933 +#define MSK_TX_GOOD_CNT BIT(19)
2934 +#define MSK_CNT_INT_ALL (MSK_RX_GOCT_CNT | MSK_RX_GOOD_CNT | MSK_TX_GOCT_CNT | MSK_TX_GOOD_CNT)
2935 +//#define MSK_CNT_INT_ALL (MSK_RX_GOOD_CNT | MSK_TX_GOOD_CNT)
2938 +#define ESW_IMR (RALINK_ETH_SW_BASE + 0x7000 + 0x8)
2939 +#define ESW_ISR (RALINK_ETH_SW_BASE + 0x7000 + 0xC)
2940 +#define ESW_INT_ALL (P0_LINK_CH | P1_LINK_CH | P2_LINK_CH | P3_LINK_CH | P4_LINK_CH | P5_LINK_CH | ACL_INT | MIB_INT)
2941 +#define ESW_AISR (RALINK_ETH_SW_BASE + 0x8)
2942 +#define ESW_P0_IntSn (RALINK_ETH_SW_BASE + 0x4004)
2943 +#define ESW_P1_IntSn (RALINK_ETH_SW_BASE + 0x4104)
2944 +#define ESW_P2_IntSn (RALINK_ETH_SW_BASE + 0x4204)
2945 +#define ESW_P3_IntSn (RALINK_ETH_SW_BASE + 0x4304)
2946 +#define ESW_P4_IntSn (RALINK_ETH_SW_BASE + 0x4404)
2947 +#define ESW_P5_IntSn (RALINK_ETH_SW_BASE + 0x4504)
2948 +#define ESW_P6_IntSn (RALINK_ETH_SW_BASE + 0x4604)
2949 +#define ESW_P0_IntMn (RALINK_ETH_SW_BASE + 0x4008)
2950 +#define ESW_P1_IntMn (RALINK_ETH_SW_BASE + 0x4108)
2951 +#define ESW_P2_IntMn (RALINK_ETH_SW_BASE + 0x4208)
2952 +#define ESW_P3_IntMn (RALINK_ETH_SW_BASE + 0x4308)
2953 +#define ESW_P4_IntMn (RALINK_ETH_SW_BASE + 0x4408)
2954 +#define ESW_P5_IntMn (RALINK_ETH_SW_BASE + 0x4508)
2955 +#define ESW_P6_IntMn (RALINK_ETH_SW_BASE + 0x4608)
2957 +#if defined (CONFIG_RALINK_MT7620)
2958 +#define ESW_P7_IntSn (RALINK_ETH_SW_BASE + 0x4704)
2959 +#define ESW_P7_IntMn (RALINK_ETH_SW_BASE + 0x4708)
2963 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x7000)
2965 +#elif defined (CONFIG_RALINK_MT7621)
2967 +#define ESW_PHY_POLLING (RALINK_ETH_SW_BASE + 0x0000)
2969 +#define P5_LINK_CH BIT(5)
2970 +#define P4_LINK_CH BIT(4)
2971 +#define P3_LINK_CH BIT(3)
2972 +#define P2_LINK_CH BIT(2)
2973 +#define P1_LINK_CH BIT(1)
2974 +#define P0_LINK_CH BIT(0)
2977 +#endif // CONFIG_RALINK_RT3052 || CONFIG_RALINK_RT3352 || CONFIG_RALINK_RT5350 || defined (CONFIG_RALINK_MT7628)//
2979 +#define RX_BUF_ALLOC_SIZE 2000
2980 +#define FASTPATH_HEADROOM 64
2982 +#define ETHER_BUFFER_ALIGN 32 ///// Align on a cache line
2984 +#define ETHER_ALIGNED_RX_SKB_ADDR(addr) \
2985 + ((((unsigned long)(addr) + ETHER_BUFFER_ALIGN - 1) & \
2986 + ~(ETHER_BUFFER_ALIGN - 1)) - (unsigned long)(addr))
2988 +#ifdef CONFIG_PSEUDO_SUPPORT
2989 +typedef struct _PSEUDO_ADAPTER {
2990 + struct net_device *RaethDev;
2991 + struct net_device *PseudoDev;
2992 + struct net_device_stats stat;
2993 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
2994 + struct mii_if_info mii_info;
2997 +} PSEUDO_ADAPTER, PPSEUDO_ADAPTER;
2999 +#define MAX_PSEUDO_ENTRY 1
3004 +/* Register Categories Definition */
3005 +#define RAFRAMEENGINE_OFFSET 0x0000
3006 +#define RAGDMA_OFFSET 0x0020
3007 +#define RAPSE_OFFSET 0x0040
3008 +#define RAGDMA2_OFFSET 0x0060
3009 +#define RACDMA_OFFSET 0x0080
3010 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3011 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3013 +#define RAPDMA_OFFSET 0x0800
3014 +#define SDM_OFFSET 0x0C00
3016 +#define RAPDMA_OFFSET 0x0100
3018 +#define RAPPE_OFFSET 0x0200
3019 +#define RACMTABLE_OFFSET 0x0400
3020 +#define RAPOLICYTABLE_OFFSET 0x1000
3023 +/* Register Map Detail */
3025 +#define SYSCFG1 (RALINK_SYSCTL_BASE + 0x14)
3027 +#if defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
3030 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x000)
3031 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x004)
3032 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x008)
3033 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00C)
3035 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x010)
3036 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x014)
3037 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x018)
3038 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x01C)
3040 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x020)
3041 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x024)
3042 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x028)
3043 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x02C)
3045 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x030)
3046 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x034)
3047 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x038)
3048 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x03C)
3050 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x100)
3051 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x104)
3052 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x108)
3053 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10C)
3055 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x110)
3056 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x114)
3057 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x118)
3058 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x11C)
3060 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x200)
3061 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x204)
3062 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x208)
3063 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3064 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20C)
3065 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x210)
3066 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x220)
3067 +#define FE_INT_STATUS (INT_STATUS)
3068 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x228)
3069 +#define FE_INT_ENABLE (INT_MASK)
3070 +#define PDMA_WRR (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3071 +#define PDMA_SCH_CFG (PDMA_WRR)
3073 +#define SDM_CON (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x00) //Switch DMA configuration
3074 +#define SDM_RRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x04) //Switch DMA Rx Ring
3075 +#define SDM_TRING (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x08) //Switch DMA Tx Ring
3076 +#define SDM_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x0C) //Switch MAC address LSB
3077 +#define SDM_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10) //Switch MAC Address MSB
3078 +#define SDM_TPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x100) //Switch DMA Tx packet count
3079 +#define SDM_TBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x104) //Switch DMA Tx byte count
3080 +#define SDM_RPCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x108) //Switch DMA rx packet count
3081 +#define SDM_RBCNT (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x10C) //Switch DMA rx byte count
3082 +#define SDM_CS_ERR (RALINK_FRAME_ENGINE_BASE+SDM_OFFSET+0x110) //Switch DMA rx checksum error count
3084 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
3085 + defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
3087 +/* Old FE with New PDMA */
3088 +#define PDMA_RELATED 0x0800
3090 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x000)
3091 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x004)
3092 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x008)
3093 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x00C)
3095 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x010)
3096 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x014)
3097 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x018)
3098 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x01C)
3100 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x020)
3101 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x024)
3102 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x028)
3103 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x02C)
3105 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x030)
3106 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x034)
3107 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x038)
3108 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x03C)
3110 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x100)
3111 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x104)
3112 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x108)
3113 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x10C)
3115 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x110)
3116 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x114)
3117 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x118)
3118 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x11C)
3120 +#define PDMA_INFO (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x200)
3121 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x204)
3122 +#define PDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x208)
3123 +#define PDMA_RST_CFG (PDMA_RST_IDX)
3124 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x20C)
3125 +#define FREEQ_THRES (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x210)
3126 +#define INT_STATUS (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x220)
3127 +#define FE_INT_STATUS (INT_STATUS)
3128 +#define INT_MASK (RALINK_FRAME_ENGINE_BASE + PDMA_RELATED+0x228)
3129 +#define FE_INT_ENABLE (INT_MASK)
3130 +#define SCH_Q01_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x280)
3131 +#define SCH_Q23_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x284)
3133 +#define FE_GLO_CFG RALINK_FRAME_ENGINE_BASE + 0x00
3134 +#define FE_RST_GL RALINK_FRAME_ENGINE_BASE + 0x04
3135 +#define FE_INT_STATUS2 RALINK_FRAME_ENGINE_BASE + 0x08
3136 +#define FE_INT_ENABLE2 RALINK_FRAME_ENGINE_BASE + 0x0c
3137 +//#define FC_DROP_STA RALINK_FRAME_ENGINE_BASE + 0x18
3138 +#define FOE_TS_T RALINK_FRAME_ENGINE_BASE + 0x10
3140 +#if defined (CONFIG_RALINK_MT7620)
3141 +#define GDMA1_RELATED 0x0600
3142 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3143 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3144 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3145 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3146 +#elif defined (CONFIG_RALINK_MT7621)
3147 +#define GDMA1_RELATED 0x0500
3148 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3149 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3150 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3151 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3153 +#define GDMA2_RELATED 0x1500
3154 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3155 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3156 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3157 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3159 +#define GDMA1_RELATED 0x0020
3160 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x00)
3161 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x04)
3162 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x08)
3163 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x0C)
3164 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA1_RELATED + 0x10)
3166 +#define GDMA2_RELATED 0x0060
3167 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x00)
3168 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x04)
3169 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x08)
3170 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x0C)
3171 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE + GDMA2_RELATED + 0x10)
3174 +#if defined (CONFIG_RALINK_MT7620)
3175 +#define PSE_RELATED 0x0500
3176 +#define PSE_FQFC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3177 +#define PSE_IQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3178 +#define PSE_QUE_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3180 +#define PSE_RELATED 0x0040
3181 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x00)
3182 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x04)
3183 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x08)
3184 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x0C)
3185 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x10)
3186 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x14)
3187 +#define GDMA2_OQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x18)
3188 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE + PSE_RELATED + 0x1C)
3192 +#if defined (CONFIG_RALINK_MT7620)
3193 +#define CDMA_RELATED 0x0400
3194 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3195 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x3FE4)
3196 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x3FE8)
3197 +#define CKGCR (RALINK_ETH_SW_BASE + 0x3FF0)
3198 +#elif defined (CONFIG_RALINK_MT7621)
3199 +#define CDMA_RELATED 0x0400
3200 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00) //fake definition
3201 +#define CDMP_IG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3202 +#define CDMP_EG_CTRL (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3204 +#define CDMA_RELATED 0x0080
3205 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x00)
3206 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE + CDMA_RELATED + 0x04)
3207 +#define SMACCR0 (RALINK_ETH_SW_BASE + 0x30E4)
3208 +#define SMACCR1 (RALINK_ETH_SW_BASE + 0x30E8)
3209 +#define CKGCR (RALINK_ETH_SW_BASE + 0x30F0)
3212 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x100)
3215 +#if defined (CONFIG_RALINK_MT7621)
3216 +/*kurtis: add QDMA define*/
3218 +#define CLK_CFG_0 (RALINK_SYSCTL_BASE + 0x2C)
3219 +#define PAD_RGMII2_MDIO_CFG (RALINK_SYSCTL_BASE + 0x58)
3221 +#define QDMA_RELATED 0x1800
3222 +#define QTX_CFG_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x000)
3223 +#define QTX_SCH_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x004)
3224 +#define QTX_HEAD_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x008)
3225 +#define QTX_TAIL_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x00C)
3226 +#define QTX_CFG_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x010)
3227 +#define QTX_SCH_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x014)
3228 +#define QTX_HEAD_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x018)
3229 +#define QTX_TAIL_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x01C)
3230 +#define QTX_CFG_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x020)
3231 +#define QTX_SCH_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x024)
3232 +#define QTX_HEAD_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x028)
3233 +#define QTX_TAIL_2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x02C)
3234 +#define QTX_CFG_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x030)
3235 +#define QTX_SCH_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x034)
3236 +#define QTX_HEAD_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x038)
3237 +#define QTX_TAIL_3 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x03C)
3238 +#define QTX_CFG_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x040)
3239 +#define QTX_SCH_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x044)
3240 +#define QTX_HEAD_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x048)
3241 +#define QTX_TAIL_4 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x04C)
3242 +#define QTX_CFG_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x050)
3243 +#define QTX_SCH_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x054)
3244 +#define QTX_HEAD_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x058)
3245 +#define QTX_TAIL_5 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x05C)
3246 +#define QTX_CFG_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x060)
3247 +#define QTX_SCH_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x064)
3248 +#define QTX_HEAD_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x068)
3249 +#define QTX_TAIL_6 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x06C)
3250 +#define QTX_CFG_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x070)
3251 +#define QTX_SCH_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x074)
3252 +#define QTX_HEAD_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x078)
3253 +#define QTX_TAIL_7 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x07C)
3254 +#define QTX_CFG_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x080)
3255 +#define QTX_SCH_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x084)
3256 +#define QTX_HEAD_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x088)
3257 +#define QTX_TAIL_8 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x08C)
3258 +#define QTX_CFG_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x090)
3259 +#define QTX_SCH_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x094)
3260 +#define QTX_HEAD_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x098)
3261 +#define QTX_TAIL_9 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x09C)
3262 +#define QTX_CFG_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A0)
3263 +#define QTX_SCH_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A4)
3264 +#define QTX_HEAD_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0A8)
3265 +#define QTX_TAIL_10 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0AC)
3266 +#define QTX_CFG_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B0)
3267 +#define QTX_SCH_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B4)
3268 +#define QTX_HEAD_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0B8)
3269 +#define QTX_TAIL_11 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0BC)
3270 +#define QTX_CFG_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C0)
3271 +#define QTX_SCH_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C4)
3272 +#define QTX_HEAD_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0C8)
3273 +#define QTX_TAIL_12 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0CC)
3274 +#define QTX_CFG_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D0)
3275 +#define QTX_SCH_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D4)
3276 +#define QTX_HEAD_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0D8)
3277 +#define QTX_TAIL_13 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0DC)
3278 +#define QTX_CFG_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E0)
3279 +#define QTX_SCH_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E4)
3280 +#define QTX_HEAD_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0E8)
3281 +#define QTX_TAIL_14 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0EC)
3282 +#define QTX_CFG_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F0)
3283 +#define QTX_SCH_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F4)
3284 +#define QTX_HEAD_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0F8)
3285 +#define QTX_TAIL_15 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x0FC)
3286 +#define QRX_BASE_PTR_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x100)
3287 +#define QRX_MAX_CNT_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x104)
3288 +#define QRX_CRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x108)
3289 +#define QRX_DRX_IDX_0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x10C)
3290 +#define QRX_BASE_PTR_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x110)
3291 +#define QRX_MAX_CNT_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x114)
3292 +#define QRX_CRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x118)
3293 +#define QRX_DRX_IDX_1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x11C)
3294 +#define QDMA_INFO (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x200)
3295 +#define QDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x204)
3296 +#define QDMA_RST_IDX (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x208)
3297 +#define QDMA_RST_CFG (QDMA_RST_IDX)
3298 +#define QDMA_DELAY_INT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x20C)
3299 +#define QDMA_FC_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x210)
3300 +#define QDMA_TX_SCH (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x214)
3301 +#define QDMA_INT_STS (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x218)
3302 +#define QFE_INT_STATUS (QDMA_INT_STS)
3303 +#define QDMA_INT_MASK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x21C)
3304 +#define QFE_INT_ENABLE (QDMA_INT_MASK)
3305 +#define QDMA_TRTCM (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x220)
3306 +#define QDMA_DATA0 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x224)
3307 +#define QDMA_DATA1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x228)
3308 +#define QDMA_RED_THRES (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x22C)
3309 +#define QDMA_TEST (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x230)
3310 +#define QDMA_DMA (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x234)
3311 +#define QDMA_BMU (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x238)
3312 +#define QDMA_HRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x240)
3313 +#define QDMA_HRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x244)
3314 +#define QDMA_SRED1 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x248)
3315 +#define QDMA_SRED2 (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x24C)
3316 +#define QTX_CTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x300)
3317 +#define QTX_DTX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x304)
3318 +#define QTX_FWD_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x308)
3319 +#define QTX_CRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x310)
3320 +#define QTX_DRX_PTR (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x314)
3321 +#define QTX_RLS_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x318)
3322 +#define QDMA_FQ_HEAD (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x320)
3323 +#define QDMA_FQ_TAIL (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x324)
3324 +#define QDMA_FQ_CNT (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x328)
3325 +#define QDMA_FQ_BLEN (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x32C)
3326 +#define QTX_Q0MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x350)
3327 +#define QTX_Q1MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x354)
3328 +#define QTX_Q2MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x358)
3329 +#define QTX_Q3MIN_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x35C)
3330 +#define QTX_Q0MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x360)
3331 +#define QTX_Q1MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x364)
3332 +#define QTX_Q2MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x368)
3333 +#define QTX_Q3MAX_BK (RALINK_FRAME_ENGINE_BASE + QDMA_RELATED + 0x36C)
3336 +#endif/*MT7621 QDMA*/
3340 +/* 1. Frame Engine Global Registers */
3341 +#define MDIO_ACCESS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x00)
3342 +#define MDIO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x04)
3343 +#define FE_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x08)
3344 +#define FE_RST_GL (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x0C)
3345 +#define FE_INT_STATUS (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x10)
3346 +#define FE_INT_ENABLE (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x14)
3347 +#define MDIO_CFG2 (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x18) //Original:FC_DROP_STA
3348 +#define FOC_TS_T (RALINK_FRAME_ENGINE_BASE+RAFRAMEENGINE_OFFSET+0x1C)
3351 +/* 2. GDMA Registers */
3352 +#define GDMA1_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x00)
3353 +#define GDMA1_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x04)
3354 +#define GDMA1_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x08)
3355 +#define GDMA1_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x0C)
3356 +#define GDMA1_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA_OFFSET+0x10)
3358 +#define GDMA2_FWD_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x00)
3359 +#define GDMA2_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x04)
3360 +#define GDMA2_SHPR_CFG (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x08)
3361 +#define GDMA2_MAC_ADRL (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x0C)
3362 +#define GDMA2_MAC_ADRH (RALINK_FRAME_ENGINE_BASE+RAGDMA2_OFFSET+0x10)
3365 +#define PSE_FQ_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x00)
3366 +#define CDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x04)
3367 +#define GDMA1_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x08)
3368 +#define GDMA2_FC_CFG (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x0C)
3369 +#define PDMA_FC_CFG (RALINK_FRAME_ENGINE_BASE+0x1f0)
3372 +#define CDMA_CSG_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x00)
3373 +#define CDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RACDMA_OFFSET+0x04)
3374 +/* skip ppoe sid and vlan id definition */
3378 +#define PDMA_GLO_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x00)
3379 +#define PDMA_RST_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x04)
3380 +#define PDMA_SCH_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x08)
3382 +#define DLY_INT_CFG (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x0C)
3384 +#define TX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x10)
3385 +#define TX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x14)
3386 +#define TX_CTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x18)
3387 +#define TX_DTX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x1C)
3389 +#define TX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x20)
3390 +#define TX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x24)
3391 +#define TX_CTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x28)
3392 +#define TX_DTX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x2C)
3394 +#define TX_BASE_PTR2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
3395 +#define TX_MAX_CNT2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
3396 +#define TX_CTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
3397 +#define TX_DTX_IDX2 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
3399 +#define TX_BASE_PTR3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x50)
3400 +#define TX_MAX_CNT3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x54)
3401 +#define TX_CTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x58)
3402 +#define TX_DTX_IDX3 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x5C)
3404 +#define RX_BASE_PTR0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x30)
3405 +#define RX_MAX_CNT0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x34)
3406 +#define RX_CALC_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x38)
3407 +#define RX_DRX_IDX0 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x3C)
3409 +#define RX_BASE_PTR1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x40)
3410 +#define RX_MAX_CNT1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x44)
3411 +#define RX_CALC_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x48)
3412 +#define RX_DRX_IDX1 (RALINK_FRAME_ENGINE_BASE+RAPDMA_OFFSET+0x4C)
3416 +#define DELAY_INT_INIT 0x84048404
3417 +#define FE_INT_DLY_INIT (TX_DLY_INT | RX_DLY_INT)
3420 +#if !defined (CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
3422 +/* 6. Counter and Meter Table */
3423 +#define PPE_AC_BCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x000) /* PPE Accounting Group 0 Byte Cnt */
3424 +#define PPE_AC_PCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x004) /* PPE Accounting Group 0 Packet Cnt */
3427 +#define PPE_MTR_CNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x200) /* 0 ~ 63 */
3429 +#define PPE_MTR_CNT63 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x2FC)
3431 +#define GDMA_TX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x300) /* Transmit good byte cnt for GEport */
3432 +#define GDMA_TX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x304) /* Transmit good pkt cnt for GEport */
3433 +#define GDMA_TX_SKIPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x308) /* Transmit skip cnt for GEport */
3434 +#define GDMA_TX_COLCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x30C) /* Transmit collision cnt for GEport */
3436 +/* update these address mapping to fit data sheet v0.26, by bobtseng, 2007.6.14 */
3437 +#define GDMA_RX_GBCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x320)
3438 +#define GDMA_RX_GPCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x324)
3439 +#define GDMA_RX_OERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x328)
3440 +#define GDMA_RX_FERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x32C)
3441 +#define GDMA_RX_SERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x330)
3442 +#define GDMA_RX_LERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x334)
3443 +#define GDMA_RX_CERCNT0 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x338)
3444 +#define GDMA_RX_FCCNT1 (RALINK_FRAME_ENGINE_BASE+RACMTABLE_OFFSET+0x33C)
3449 +/* Per Port Packet Counts in RT3052, added by bobtseng 2009.4.17. */
3450 +#define PORT0_PKCOUNT (0xb01100e8)
3451 +#define PORT1_PKCOUNT (0xb01100ec)
3452 +#define PORT2_PKCOUNT (0xb01100f0)
3453 +#define PORT3_PKCOUNT (0xb01100f4)
3454 +#define PORT4_PKCOUNT (0xb01100f8)
3455 +#define PORT5_PKCOUNT (0xb01100fc)
3459 +#define PHYS_TO_K1(physaddr) KSEG1ADDR(physaddr)
3462 +#define sysRegRead(phys) \
3463 + (*(volatile unsigned int *)PHYS_TO_K1(phys))
3465 +#define sysRegWrite(phys, val) \
3466 + ((*(volatile unsigned int *)PHYS_TO_K1(phys)) = (val))
3468 +#define u_long unsigned long
3469 +#define u32 unsigned int
3470 +#define u16 unsigned short
3473 +/* ====================================== */
3474 +#define GDM1_DISPAD BIT(18)
3475 +#define GDM1_DISCRC BIT(17)
3477 +//GDMA1 uni-cast frames destination port
3478 +#define GDM1_ICS_EN (0x1 << 22)
3479 +#define GDM1_TCS_EN (0x1 << 21)
3480 +#define GDM1_UCS_EN (0x1 << 20)
3481 +#define GDM1_JMB_EN (0x1 << 19)
3482 +#define GDM1_STRPCRC (0x1 << 16)
3483 +#define GDM1_UFRC_P_CPU (0 << 12)
3484 +#if defined (CONFIG_RALINK_MT7621)
3485 +#define GDM1_UFRC_P_PPE (4 << 12)
3487 +#define GDM1_UFRC_P_PPE (6 << 12)
3490 +//GDMA1 broad-cast MAC address frames
3491 +#define GDM1_BFRC_P_CPU (0 << 8)
3492 +#if defined (CONFIG_RALINK_MT7621)
3493 +#define GDM1_BFRC_P_PPE (4 << 8)
3495 +#define GDM1_BFRC_P_PPE (6 << 8)
3498 +//GDMA1 multi-cast MAC address frames
3499 +#define GDM1_MFRC_P_CPU (0 << 4)
3500 +#if defined (CONFIG_RALINK_MT7621)
3501 +#define GDM1_MFRC_P_PPE (4 << 4)
3503 +#define GDM1_MFRC_P_PPE (6 << 4)
3506 +//GDMA1 other MAC address frames destination port
3507 +#define GDM1_OFRC_P_CPU (0 << 0)
3508 +#if defined (CONFIG_RALINK_MT7621)
3509 +#define GDM1_OFRC_P_PPE (4 << 0)
3511 +#define GDM1_OFRC_P_PPE (6 << 0)
3514 +#if defined (CONFIG_RALINK_RT6856) || defined (CONFIG_RALINK_MT7620) || defined (CONFIG_RALINK_MT7621)
3515 +/* checksum generator registers are removed */
3516 +#define ICS_GEN_EN (0 << 2)
3517 +#define UCS_GEN_EN (0 << 1)
3518 +#define TCS_GEN_EN (0 << 0)
3520 +#define ICS_GEN_EN (1 << 2)
3521 +#define UCS_GEN_EN (1 << 1)
3522 +#define TCS_GEN_EN (1 << 0)
3526 +#define MDIO_CFG_GP1_FC_TX (1 << 11)
3527 +#define MDIO_CFG_GP1_FC_RX (1 << 10)
3529 +/* ====================================== */
3530 +/* ====================================== */
3531 +#define GP1_LNK_DWN BIT(9)
3532 +#define GP1_AN_FAIL BIT(8)
3533 +/* ====================================== */
3534 +/* ====================================== */
3535 +#define PSE_RESET BIT(0)
3536 +/* ====================================== */
3537 +#define PST_DRX_IDX1 BIT(17)
3538 +#define PST_DRX_IDX0 BIT(16)
3539 +#define PST_DTX_IDX3 BIT(3)
3540 +#define PST_DTX_IDX2 BIT(2)
3541 +#define PST_DTX_IDX1 BIT(1)
3542 +#define PST_DTX_IDX0 BIT(0)
3544 +#define RX_2B_OFFSET BIT(31)
3545 +#define DESC_32B_EN BIT(8)
3546 +#define TX_WB_DDONE BIT(6)
3547 +#define RX_DMA_BUSY BIT(3)
3548 +#define TX_DMA_BUSY BIT(1)
3549 +#define RX_DMA_EN BIT(2)
3550 +#define TX_DMA_EN BIT(0)
3552 +#define PDMA_BT_SIZE_4DWORDS (0<<4)
3553 +#define PDMA_BT_SIZE_8DWORDS (1<<4)
3554 +#define PDMA_BT_SIZE_16DWORDS (2<<4)
3555 +#define PDMA_BT_SIZE_32DWORDS (3<<4)
3560 +#define MACCFG_RXEN (1<<2)
3561 +#define MACCFG_TXEN (1<<3)
3562 +#define MACCFG_PROMISC (1<<18)
3563 +#define MACCFG_RXMCAST (1<<19)
3564 +#define MACCFG_FDUPLEX (1<<20)
3565 +#define MACCFG_PORTSEL (1<<27)
3566 +#define MACCFG_HBEATDIS (1<<28)
3569 +#define DMACTL_SR (1<<1) /* Start/Stop Receive */
3570 +#define DMACTL_ST (1<<13) /* Start/Stop Transmission Command */
3572 +#define DMACFG_SWR (1<<0) /* Software Reset */
3573 +#define DMACFG_BURST32 (32<<8)
3575 +#define DMASTAT_TS 0x00700000 /* Transmit Process State */
3576 +#define DMASTAT_RS 0x000e0000 /* Receive Process State */
3578 +#define MACCFG_INIT 0 //(MACCFG_FDUPLEX) // | MACCFG_PORTSEL)
3582 +/* Descriptor bits.
3584 +#define R_OWN 0x80000000 /* Own Bit */
3585 +#define RD_RER 0x02000000 /* Receive End Of Ring */
3586 +#define RD_LS 0x00000100 /* Last Descriptor */
3587 +#define RD_ES 0x00008000 /* Error Summary */
3588 +#define RD_CHAIN 0x01000000 /* Chained */
3591 +#define T_OWN 0x80000000 /* Own Bit */
3592 +#define TD_ES 0x00008000 /* Error Summary */
3595 +#define TD_LS 0x40000000 /* Last Segment */
3596 +#define TD_FS 0x20000000 /* First Segment */
3597 +#define TD_TER 0x08000000 /* Transmit End Of Ring */
3598 +#define TD_CHAIN 0x01000000 /* Chained */
3601 +#define TD_SET 0x08000000 /* Setup Packet */
3604 +#define POLL_DEMAND 1
3606 +#define RSTCTL (0x34)
3607 +#define RSTCTL_RSTENET1 (1<<19)
3608 +#define RSTCTL_RSTENET2 (1<<20)
3610 +#define INIT_VALUE_OF_RT2883_PSE_FQ_CFG 0xff908000
3611 +#define INIT_VALUE_OF_PSE_FQFC_CFG 0x80504000
3612 +#define INIT_VALUE_OF_FORCE_100_FD 0x1001BC01
3613 +#define INIT_VALUE_OF_FORCE_1000_FD 0x1F01DC01
3615 +// Define Whole FE Reset Register
3616 +#define RSTCTRL (RALINK_SYSCTL_BASE + 0x34)
3618 +/*=========================================
3619 + PDMA RX Descriptor Format define
3620 +=========================================*/
3622 +//-------------------------------------------------
3623 +typedef struct _PDMA_RXD_INFO1_ PDMA_RXD_INFO1_T;
3625 +struct _PDMA_RXD_INFO1_
3627 + unsigned int PDP0;
3629 +//-------------------------------------------------
3630 +typedef struct _PDMA_RXD_INFO2_ PDMA_RXD_INFO2_T;
3632 +struct _PDMA_RXD_INFO2_
3634 + unsigned int PLEN1 : 14;
3635 + unsigned int LS1 : 1;
3636 + unsigned int TAG : 1;
3637 + unsigned int PLEN0 : 14;
3638 + unsigned int LS0 : 1;
3639 + unsigned int DDONE_bit : 1;
3641 +//-------------------------------------------------
3642 +typedef struct _PDMA_RXD_INFO3_ PDMA_RXD_INFO3_T;
3644 +struct _PDMA_RXD_INFO3_
3646 + unsigned int VID:16;
3647 + unsigned int TPID:16;
3649 +//-------------------------------------------------
3650 +typedef struct _PDMA_RXD_INFO4_ PDMA_RXD_INFO4_T;
3652 +struct _PDMA_RXD_INFO4_
3654 +#if defined (CONFIG_RALINK_MT7620)
3655 + unsigned int FOE_Entry : 14;
3656 + unsigned int CRSN : 5;
3657 + unsigned int SPORT : 3;
3658 + unsigned int L4F : 1;
3659 + unsigned int L4VLD : 1;
3660 + unsigned int TACK : 1;
3661 + unsigned int IP4F : 1;
3662 + unsigned int IP4 : 1;
3663 + unsigned int IP6 : 1;
3664 + unsigned int UN_USE1 : 4;
3665 +#elif defined (CONFIG_RALINK_MT7621)
3666 + unsigned int FOE_Entry : 14;
3667 + unsigned int CRSN : 5;
3668 + unsigned int SP : 4;
3669 + unsigned int L4F : 1;
3670 + unsigned int L4VLD : 1;
3671 + unsigned int TACK : 1;
3672 + unsigned int IP4F : 1;
3673 + unsigned int IP4 : 1;
3674 + unsigned int IP6 : 1;
3675 + unsigned int UN_USE1 : 3;
3677 + unsigned int FOE_Entry : 14;
3678 + unsigned int FVLD : 1;
3679 + unsigned int UN_USE1 : 1;
3680 + unsigned int AI : 8;
3681 + unsigned int SP : 3;
3682 + unsigned int AIS : 1;
3683 + unsigned int L4F : 1;
3684 + unsigned int IPF : 1;
3685 + unsigned int L4FVLD_bit : 1;
3686 + unsigned int IPFVLD_bit : 1;
3691 +struct PDMA_rxdesc {
3692 + PDMA_RXD_INFO1_T rxd_info1;
3693 + PDMA_RXD_INFO2_T rxd_info2;
3694 + PDMA_RXD_INFO3_T rxd_info3;
3695 + PDMA_RXD_INFO4_T rxd_info4;
3696 +#ifdef CONFIG_32B_DESC
3697 + unsigned int rxd_info5;
3698 + unsigned int rxd_info6;
3699 + unsigned int rxd_info7;
3700 + unsigned int rxd_info8;
3704 +/*=========================================
3705 + PDMA TX Descriptor Format define
3706 +=========================================*/
3707 +//-------------------------------------------------
3708 +typedef struct _PDMA_TXD_INFO1_ PDMA_TXD_INFO1_T;
3710 +struct _PDMA_TXD_INFO1_
3712 + unsigned int SDP0;
3714 +//-------------------------------------------------
3715 +typedef struct _PDMA_TXD_INFO2_ PDMA_TXD_INFO2_T;
3717 +struct _PDMA_TXD_INFO2_
3719 + unsigned int SDL1 : 14;
3720 + unsigned int LS1_bit : 1;
3721 + unsigned int BURST_bit : 1;
3722 + unsigned int SDL0 : 14;
3723 + unsigned int LS0_bit : 1;
3724 + unsigned int DDONE_bit : 1;
3726 +//-------------------------------------------------
3727 +typedef struct _PDMA_TXD_INFO3_ PDMA_TXD_INFO3_T;
3729 +struct _PDMA_TXD_INFO3_
3731 + unsigned int SDP1;
3733 +//-------------------------------------------------
3734 +typedef struct _PDMA_TXD_INFO4_ PDMA_TXD_INFO4_T;
3736 +struct _PDMA_TXD_INFO4_
3738 +#if defined (CONFIG_RALINK_MT7620)
3739 + unsigned int VPRI_VIDX : 8;
3740 + unsigned int SIDX : 4;
3741 + unsigned int INSP : 1;
3742 + unsigned int RESV : 2;
3743 + unsigned int UDF : 5;
3744 + unsigned int FP_BMAP : 8;
3745 + unsigned int TSO : 1;
3746 + unsigned int TUI_CO : 3;
3747 +#elif defined (CONFIG_RALINK_MT7621)
3748 + unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
3749 + unsigned int RESV : 2;
3750 + unsigned int UDF : 6;
3751 + unsigned int FPORT : 3;
3752 + unsigned int TSO : 1;
3753 + unsigned int TUI_CO : 3;
3755 + unsigned int VPRI_VIDX : 8;
3756 + unsigned int SIDX : 4;
3757 + unsigned int INSP : 1;
3758 + unsigned int RESV : 1;
3759 + unsigned int UN_USE3 : 2;
3760 + unsigned int QN : 3;
3761 + unsigned int UN_USE2 : 1;
3762 + unsigned int UDF : 4;
3763 + unsigned int PN : 3;
3764 + unsigned int UN_USE1 : 1;
3765 + unsigned int TSO : 1;
3766 + unsigned int TUI_CO : 3;
3771 +struct PDMA_txdesc {
3772 + PDMA_TXD_INFO1_T txd_info1;
3773 + PDMA_TXD_INFO2_T txd_info2;
3774 + PDMA_TXD_INFO3_T txd_info3;
3775 + PDMA_TXD_INFO4_T txd_info4;
3776 +#ifdef CONFIG_32B_DESC
3777 + unsigned int txd_info5;
3778 + unsigned int txd_info6;
3779 + unsigned int txd_info7;
3780 + unsigned int txd_info8;
3785 +#if defined (CONFIG_RALINK_MT7621)
3786 +/*=========================================
3787 + QDMA TX Descriptor Format define
3788 +=========================================*/
3789 +//-------------------------------------------------
3790 +typedef struct _QDMA_TXD_INFO1_ QDMA_TXD_INFO1_T;
3792 +struct _QDMA_TXD_INFO1_
3796 +//-------------------------------------------------
3797 +typedef struct _QDMA_TXD_INFO2_ QDMA_TXD_INFO2_T;
3799 +struct _QDMA_TXD_INFO2_
3803 +//-------------------------------------------------
3804 +typedef struct _QDMA_TXD_INFO3_ QDMA_TXD_INFO3_T;
3806 +struct _QDMA_TXD_INFO3_
3808 + unsigned int QID : 4;
3809 + unsigned int RESV : 10;
3810 + unsigned int SWC_bit : 1;
3811 + unsigned int BURST_bit : 1;
3812 + unsigned int SDL : 14;
3813 + unsigned int LS_bit : 1;
3814 + unsigned int OWN_bit : 1;
3816 +//-------------------------------------------------
3817 +typedef struct _QDMA_TXD_INFO4_ QDMA_TXD_INFO4_T;
3819 +struct _QDMA_TXD_INFO4_
3821 + unsigned int VLAN_TAG :17; // INSV(1)+VPRI(3)+CFI(1)+VID(12)
3822 + unsigned int RESV : 2;
3823 + unsigned int UDF : 6;
3824 + unsigned int FPORT : 3;
3825 + unsigned int TSO : 1;
3826 + unsigned int TUI_CO : 3;
3830 +struct QDMA_txdesc {
3831 + QDMA_TXD_INFO1_T txd_info1;
3832 + QDMA_TXD_INFO2_T txd_info2;
3833 + QDMA_TXD_INFO3_T txd_info3;
3834 + QDMA_TXD_INFO4_T txd_info4;
3835 +#ifdef CONFIG_32B_DESC
3836 + unsigned int txd_info5;
3837 + unsigned int txd_info6;
3838 + unsigned int txd_info7;
3839 + unsigned int txd_info8;
3844 +#define phys_to_bus(a) (a & 0x1FFFFFFF)
3846 +#define PHY_Enable_Auto_Nego 0x1000
3847 +#define PHY_Restart_Auto_Nego 0x0200
3849 +/* PHY_STAT_REG = 1; */
3850 +#define PHY_Auto_Neco_Comp 0x0020
3851 +#define PHY_Link_Status 0x0004
3853 +/* PHY_AUTO_NEGO_REG = 4; */
3854 +#define PHY_Cap_10_Half 0x0020
3855 +#define PHY_Cap_10_Full 0x0040
3856 +#define PHY_Cap_100_Half 0x0080
3857 +#define PHY_Cap_100_Full 0x0100
3859 +/* proc definition */
3861 +#if !defined (CONFIG_RALINK_RT6855) && !defined(CONFIG_RALINK_RT6855A) && \
3862 + !defined (CONFIG_RALINK_MT7620) && !defined (CONFIG_RALINK_MT7621)
3863 +#define CDMA_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x4c)
3864 +#define GDMA1_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x50)
3865 +#define PPE_OQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x54)
3866 +#define PSE_IQ_STA (RALINK_FRAME_ENGINE_BASE+RAPSE_OFFSET+0x58)
3869 +#define PROCREG_CONTROL_FILE "/var/run/procreg_control"
3870 +#if defined (CONFIG_RALINK_RT2880)
3871 +#define PROCREG_DIR "rt2880"
3872 +#elif defined (CONFIG_RALINK_RT3052)
3873 +#define PROCREG_DIR "rt3052"
3874 +#elif defined (CONFIG_RALINK_RT3352)
3875 +#define PROCREG_DIR "rt3352"
3876 +#elif defined (CONFIG_RALINK_RT5350)
3877 +#define PROCREG_DIR "rt5350"
3878 +#elif defined (CONFIG_RALINK_RT2883)
3879 +#define PROCREG_DIR "rt2883"
3880 +#elif defined (CONFIG_RALINK_RT3883)
3881 +#define PROCREG_DIR "rt3883"
3882 +#elif defined (CONFIG_RALINK_RT6855)
3883 +#define PROCREG_DIR "rt6855"
3884 +#elif defined (CONFIG_RALINK_MT7620)
3885 +#define PROCREG_DIR "mt7620"
3886 +#elif defined (CONFIG_RALINK_MT7621)
3887 +#define PROCREG_DIR "mt7621"
3888 +#elif defined (CONFIG_RALINK_MT7628)
3889 +#define PROCREG_DIR "mt7628"
3890 +#elif defined (CONFIG_RALINK_RT6855A)
3891 +#define PROCREG_DIR "rt6855a"
3893 +#define PROCREG_DIR "rt2880"
3895 +#define PROCREG_SKBFREE "skb_free"
3896 +#define PROCREG_TXRING "tx_ring"
3897 +#define PROCREG_RXRING "rx_ring"
3898 +#define PROCREG_NUM_OF_TXD "num_of_txd"
3899 +#define PROCREG_TSO_LEN "tso_len"
3900 +#define PROCREG_LRO_STATS "lro_stats"
3901 +#define PROCREG_GMAC "gmac"
3902 +#define PROCREG_GMAC2 "gmac2"
3903 +#define PROCREG_CP0 "cp0"
3904 +#define PROCREG_RAQOS "qos"
3905 +#define PROCREG_READ_VAL "regread_value"
3906 +#define PROCREG_WRITE_VAL "regwrite_value"
3907 +#define PROCREG_ADDR "reg_addr"
3908 +#define PROCREG_CTL "procreg_control"
3909 +#define PROCREG_RXDONE_INTR "rxdone_intr_count"
3910 +#define PROCREG_ESW_INTR "esw_intr_count"
3911 +#define PROCREG_ESW_CNT "esw_cnt"
3912 +#define PROCREG_SNMP "snmp"
3913 +#if defined (TASKLET_WORKQUEUE_SW)
3914 +#define PROCREG_SCHE "schedule"
3916 +#define PROCREG_QDMA "qdma"
3918 +struct rt2880_reg_op_data {
3920 + unsigned int reg_addr;
3922 + unsigned int reg_value;
3925 +#ifdef CONFIG_RAETH_LRO
3926 +struct lro_counters {
3927 + u32 lro_aggregated;
3932 +struct lro_para_struct {
3933 + unsigned int lan_ip1;
3936 +#endif // CONFIG_RAETH_LRO //
3941 +typedef struct end_device
3944 + unsigned int tx_cpu_owner_idx0;
3945 + unsigned int rx_cpu_owner_idx0;
3946 + unsigned int fe_int_status;
3947 + unsigned int tx_full;
3949 +#if !defined (CONFIG_RAETH_QDMA)
3950 + unsigned int phy_tx_ring0;
3953 + struct sk_buff *free_skb[NUM_TX_DESC];
3954 + unsigned int tx_dma_ptr;
3955 + unsigned int tx_cpu_ptr;
3956 + unsigned int free_txd_num;
3957 + unsigned int free_txd_head;
3958 + unsigned int free_txd_tail;
3959 + struct QDMA_txdesc *txd_pool;
3960 + dma_addr_t phy_txd_pool;
3961 +// unsigned int phy_txd_pool;
3962 + unsigned int txd_pool_info[NUM_TX_DESC];
3965 + unsigned int phy_rx_ring0, phy_rx_ring1;
3967 +#if defined (CONFIG_RALINK_RT3052) || defined (CONFIG_RALINK_RT3352) || \
3968 + defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_RT6855) || \
3969 + defined(CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7620) || \
3970 + defined(CONFIG_RALINK_MT7621) || defined (CONFIG_RALINK_MT7628)
3971 + //send signal to user application to notify link status changed
3972 + struct work_struct kill_sig_wq;
3975 + struct work_struct reset_task;
3976 +#ifdef WORKQUEUE_BH
3977 + struct work_struct rx_wq;
3979 +#if defined (TASKLET_WORKQUEUE_SW)
3980 + struct work_struct rx_wq;
3982 +#endif // WORKQUEUE_BH //
3984 +#if defined(CONFIG_RAETH_QOS)
3985 + struct sk_buff * skb_free[NUM_TX_RINGS][NUM_TX_DESC];
3986 + unsigned int free_idx[NUM_TX_RINGS];
3988 + struct sk_buff* skb_free[NUM_TX_DESC];
3989 + unsigned int free_idx;
3992 + struct net_device_stats stat; /* The new statistics table. */
3993 + spinlock_t page_lock; /* Page register locks */
3994 + struct PDMA_txdesc *tx_ring0;
3995 +#if defined(CONFIG_RAETH_QOS)
3996 + struct PDMA_txdesc *tx_ring1;
3997 + struct PDMA_txdesc *tx_ring2;
3998 + struct PDMA_txdesc *tx_ring3;
4000 + struct PDMA_rxdesc *rx_ring0;
4001 + struct sk_buff *netrx0_skbuf[NUM_RX_DESC];
4002 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
4003 + struct PDMA_rxdesc *rx_ring1;
4004 + struct sk_buff *netrx1_skbuf[NUM_RX_DESC];
4006 +#ifdef CONFIG_RAETH_NAPI
4008 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
4009 + struct napi_struct napi;
4012 +#ifdef CONFIG_PSEUDO_SUPPORT
4013 + struct net_device *PseudoDev;
4014 + unsigned int isPseudo;
4016 +#if defined (CONFIG_ETHTOOL) /*&& defined (CONFIG_RAETH_ROUTER)*/
4017 + struct mii_if_info mii_info;
4019 +#ifdef CONFIG_RAETH_LRO
4020 + struct lro_counters lro_counters;
4021 + struct net_lro_mgr lro_mgr;
4022 + struct net_lro_desc lro_arr[8];
4024 +#ifdef CONFIG_RAETH_HW_VLAN_RX
4025 + struct vlan_group *vlgrp;
4027 +} END_DEVICE, *pEND_DEVICE;
4030 +#define RAETH_VERSION "v3.0"
4034 +#ifdef CONFIG_RAETH_QDMA
4035 +#define DMA_GLO_CFG QDMA_GLO_CFG
4036 +#define GDMA1_FWD_PORT 0x5555
4037 +#define GDMA2_FWD_PORT 0x5555
4038 +#define RAETH_RX_CALC_IDX0 QRX_CRX_IDX_0
4039 +#define RAETH_RX_CALC_IDX1 QRX_CRX_IDX_1
4040 +#define RAETH_FE_INT_STATUS QFE_INT_STATUS
4041 +#define RAETH_FE_INT_ALL QFE_INT_ALL
4042 +#define RAETH_FE_INT_ENABLE QFE_INT_ENABLE
4043 +#define RAETH_FE_INT_DLY_INIT QFE_INT_DLY_INIT
4044 +#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | RLS_DONE_INT
4045 +#define RAETH_TX_DLY_INT RLS_DLY_INT
4046 +#define RAETH_TX_DONE_INT0 RLS_DONE_INT
4047 +#define RAETH_DLY_INT_CFG QDMA_DELAY_INT
4049 +#define DMA_GLO_CFG PDMA_GLO_CFG
4050 +#define GDMA1_FWD_PORT 0x0000
4051 +#define GDMA2_FWD_PORT 0x0000
4052 +#define RAETH_RX_CALC_IDX0 RX_CALC_IDX0
4053 +#define RAETH_RX_CALC_IDX1 RX_CALC_IDX1
4054 +#define RAETH_FE_INT_STATUS FE_INT_STATUS
4055 +#define RAETH_FE_INT_ALL FE_INT_ALL
4056 +#define RAETH_FE_INT_ENABLE FE_INT_ENABLE
4057 +#define RAETH_FE_INT_DLY_INIT FE_INT_DLY_INIT
4058 +#define RAETH_FE_INT_SETTING RX_DONE_INT0 | RX_DONE_INT1 | TX_DONE_INT0 | TX_DONE_INT1 | TX_DONE_INT2 | TX_DONE_INT3
4059 +#define RAETH_TX_DLY_INT TX_DLY_INT
4060 +#define RAETH_TX_DONE_INT0 TX_DONE_INT0
4061 +#define RAETH_DLY_INT_CFG DLY_INT_CFG
4063 diff --git a/drivers/net/ethernet/raeth/ra_ioctl.h b/drivers/net/ethernet/raeth/ra_ioctl.h
4064 new file mode 100644
4065 index 0000000..eac0964
4067 +++ b/drivers/net/ethernet/raeth/ra_ioctl.h
4069 +#ifndef _RAETH_IOCTL_H
4070 +#define _RAETH_IOCTL_H
4072 +/* ioctl commands */
4073 +#define RAETH_ESW_REG_READ 0x89F1
4074 +#define RAETH_ESW_REG_WRITE 0x89F2
4075 +#define RAETH_MII_READ 0x89F3
4076 +#define RAETH_MII_WRITE 0x89F4
4077 +#define RAETH_ESW_INGRESS_RATE 0x89F5
4078 +#define RAETH_ESW_EGRESS_RATE 0x89F6
4079 +#define RAETH_ESW_PHY_DUMP 0x89F7
4080 +#define RAETH_QDMA_REG_READ 0x89F8
4081 +#define RAETH_QDMA_REG_WRITE 0x89F9
4082 +#define RAETH_QDMA_QUEUE_MAPPING 0x89FA
4083 +#define RAETH_QDMA_READ_CPU_CLK 0x89FB
4085 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
4086 + defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
4088 +#define REG_ESW_WT_MAC_MFC 0x10
4089 +#define REG_ESW_WT_MAC_ATA1 0x74
4090 +#define REG_ESW_WT_MAC_ATA2 0x78
4091 +#define REG_ESW_WT_MAC_ATWD 0x7C
4092 +#define REG_ESW_WT_MAC_ATC 0x80
4094 +#define REG_ESW_TABLE_TSRA1 0x84
4095 +#define REG_ESW_TABLE_TSRA2 0x88
4096 +#define REG_ESW_TABLE_ATRD 0x8C
4099 +#define REG_ESW_VLAN_VTCR 0x90
4100 +#define REG_ESW_VLAN_VAWD1 0x94
4101 +#define REG_ESW_VLAN_VAWD2 0x98
4104 +#define REG_ESW_VLAN_ID_BASE 0x100
4106 +//#define REG_ESW_VLAN_ID_BASE 0x50
4107 +#define REG_ESW_VLAN_MEMB_BASE 0x70
4108 +#define REG_ESW_TABLE_SEARCH 0x24
4109 +#define REG_ESW_TABLE_STATUS0 0x28
4110 +#define REG_ESW_TABLE_STATUS1 0x2C
4111 +#define REG_ESW_TABLE_STATUS2 0x30
4112 +#define REG_ESW_WT_MAC_AD0 0x34
4113 +#define REG_ESW_WT_MAC_AD1 0x38
4114 +#define REG_ESW_WT_MAC_AD2 0x3C
4117 +/* rt3052 embedded ethernet switch registers */
4118 +#define REG_ESW_VLAN_ID_BASE 0x50
4119 +#define REG_ESW_VLAN_MEMB_BASE 0x70
4120 +#define REG_ESW_TABLE_SEARCH 0x24
4121 +#define REG_ESW_TABLE_STATUS0 0x28
4122 +#define REG_ESW_TABLE_STATUS1 0x2C
4123 +#define REG_ESW_TABLE_STATUS2 0x30
4124 +#define REG_ESW_WT_MAC_AD0 0x34
4125 +#define REG_ESW_WT_MAC_AD1 0x38
4126 +#define REG_ESW_WT_MAC_AD2 0x3C
4130 +#if defined(CONFIG_RALINK_RT3352) || defined (CONFIG_RALINK_RT5350) || defined (CONFIG_RALINK_MT7628)
4131 +#define REG_ESW_MAX 0x16C
4132 +#elif defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
4133 + defined (CONFIG_RALINK_MT7620)
4134 +#define REG_ESW_MAX 0x7FFFF
4135 +#else //RT305x, RT3350
4136 +#define REG_ESW_MAX 0xFC
4138 +#define REG_HQOS_MAX 0x3FFF
4141 +typedef struct rt3052_esw_reg {
4146 +typedef struct ralink_mii_ioctl_data {
4151 +} ra_mii_ioctl_data;
4153 +typedef struct rt335x_esw_reg {
4154 + unsigned int on_off;
4155 + unsigned int port;
4156 + unsigned int bw;/*Mbps*/
4161 diff --git a/drivers/net/ethernet/raeth/ra_mac.c b/drivers/net/ethernet/raeth/ra_mac.c
4162 new file mode 100644
4163 index 0000000..8e07a06
4165 +++ b/drivers/net/ethernet/raeth/ra_mac.c
4167 +#include <linux/module.h>
4168 +#include <linux/version.h>
4169 +#include <linux/kernel.h>
4170 +#include <linux/sched.h>
4171 +#include <linux/types.h>
4172 +#include <linux/fcntl.h>
4173 +#include <linux/interrupt.h>
4174 +#include <linux/ptrace.h>
4175 +#include <linux/ioport.h>
4176 +#include <linux/in.h>
4177 +#include <linux/slab.h>
4178 +#include <linux/string.h>
4179 +#include <linux/signal.h>
4180 +#include <linux/irq.h>
4181 +#include <linux/ctype.h>
4183 +#include <asm/io.h>
4184 +#include <asm/bitops.h>
4185 +#include <asm/io.h>
4186 +#include <asm/dma.h>
4188 +#include <asm/rt2880/surfboardint.h> /* for cp0 reg access, added by bobtseng */
4190 +#include <linux/errno.h>
4191 +#include <linux/init.h>
4192 +//#include <linux/mca.h>
4194 +#include <linux/netdevice.h>
4195 +#include <linux/etherdevice.h>
4196 +#include <linux/skbuff.h>
4198 +#include <linux/init.h>
4199 +#include <linux/module.h>
4200 +#include <linux/proc_fs.h>
4201 +#include <asm/uaccess.h>
4203 +#if defined(CONFIG_USER_SNMPD)
4204 +#include <linux/seq_file.h>
4209 +#include "ra2882ethreg.h"
4210 +#include "raether.h"
4211 +#include "ra_mac.h"
4213 +extern struct net_device *dev_raether;
4216 +void ra2880stop(END_DEVICE *ei_local)
4218 + unsigned int regValue;
4219 + printk("ra2880stop()...");
4221 + regValue = sysRegRead(PDMA_GLO_CFG);
4222 + regValue &= ~(TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN);
4223 + sysRegWrite(PDMA_GLO_CFG, regValue);
4224 + printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regValue);
4228 +void ei_irq_clear(void)
4230 + sysRegWrite(FE_INT_STATUS, 0xFFFFFFFF);
4231 + printk("-> %s 0x%08x 0x%08x\n", "FE_INT_STATUS", FE_INT_STATUS, 0xFFFFFFFF);
4234 +void rt2880_gmac_hard_reset(void)
4236 + sysRegWrite(RSTCTRL, RALINK_FE_RST);
4237 + printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, RALINK_FE_RST);
4238 + sysRegWrite(RSTCTRL, 0);
4239 + printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, 0);
4242 +void ra2880EnableInterrupt()
4244 + unsigned int regValue = sysRegRead(FE_INT_ENABLE);
4245 + sysRegWrite(FE_INT_ENABLE, regValue);
4246 + printk("-> %s 0x%08x 0x%08x\n", "FE_INT_ENABLE", FE_INT_ENABLE, regValue);
4249 +void ra2880MacAddressSet(unsigned char p[6])
4251 + unsigned long regValue;
4253 + regValue = (p[0] << 8) | (p[1]);
4254 + sysRegWrite(GDMA1_MAC_ADRH, regValue);
4255 + printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRH", GDMA1_MAC_ADRH, regValue);
4257 + regValue = (p[2] << 24) | (p[3] <<16) | (p[4] << 8) | p[5];
4258 + printk("-> %s 0x%08x 0x%08x\n", "GDMA1_MAC_ADRL", GDMA1_MAC_ADRL, regValue);
4259 + sysRegWrite(GDMA1_MAC_ADRL, regValue);
4265 diff --git a/drivers/net/ethernet/raeth/ra_mac.h b/drivers/net/ethernet/raeth/ra_mac.h
4266 new file mode 100644
4267 index 0000000..4f4e6ae
4269 +++ b/drivers/net/ethernet/raeth/ra_mac.h
4274 +void ra2880stop(END_DEVICE *ei_local);
4275 +void ra2880MacAddressSet(unsigned char p[6]);
4276 +void ra2880Mac2AddressSet(unsigned char p[6]);
4277 +void ethtool_init(struct net_device *dev);
4279 +void ra2880EnableInterrupt(void);
4281 +void dump_qos(void);
4282 +void dump_reg(void);
4283 +void dump_cp0(void);
4285 +int debug_proc_init(void);
4286 +void debug_proc_exit(void);
4288 +#if defined (CONFIG_RALINK_RT6855) || defined(CONFIG_RALINK_RT6855A) || \
4289 + defined (CONFIG_RALINK_MT7620) || defined(CONFIG_RALINK_MT7621)
4290 +void enable_auto_negotiate(int unused);
4292 +void enable_auto_negotiate(int ge);
4295 +void rt2880_gmac_hard_reset(void);
4297 +int TsoLenUpdate(int tso_len);
4298 +int NumOfTxdUpdate(int num_of_txd);
4300 +#ifdef CONFIG_RAETH_LRO
4301 +int LroStatsUpdate(struct net_lro_mgr *lro_mgr, bool all_flushed);
4303 +int getnext(const char *src, int separator, char *dest);
4304 +int str_to_ip(unsigned int *ip, const char *str);
4306 diff --git a/drivers/net/ethernet/raeth/raether.c b/drivers/net/ethernet/raeth/raether.c
4307 new file mode 100644
4308 index 0000000..b6cbc40
4310 +++ b/drivers/net/ethernet/raeth/raether.c
4312 +#include <linux/module.h>
4313 +#include <linux/version.h>
4314 +#include <linux/kernel.h>
4315 +#include <linux/types.h>
4316 +#include <linux/pci.h>
4317 +#include <linux/interrupt.h>
4318 +#include <linux/init.h>
4319 +#include <linux/skbuff.h>
4320 +#include <linux/if_vlan.h>
4321 +#include <linux/if_ether.h>
4322 +#include <linux/fs.h>
4323 +#include <asm/uaccess.h>
4324 +#include <linux/delay.h>
4325 +#include <linux/sched.h>
4327 +#include <asm/rt2880/rt_mmap.h>
4328 +#include "ra2882ethreg.h"
4329 +#include "raether.h"
4330 +#include "ra_mac.h"
4331 +#include "ra_ioctl.h"
4333 +static int rt2880_eth_recv(struct net_device* dev);
4336 +void setup_internal_gsw(void);
4338 +#define MAX_RX_LENGTH 1536
4340 +struct net_device *dev_raether;
4342 +static int rx_dma_owner_idx;
4343 +static int rx_dma_owner_idx0;
4344 +static int pending_recv;
4345 +static struct PDMA_rxdesc *rx_ring;
4346 +static unsigned long tx_ring_full=0;
4348 +#define KSEG1 0xa0000000
4349 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
4350 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
4352 +extern int fe_dma_init(struct net_device *dev);
4353 +extern int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no);
4354 +extern void ei_xmit_housekeeping(unsigned long unused);
4355 +extern inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no);
4357 +static int ei_set_mac_addr(struct net_device *dev, void *p)
4359 + struct sockaddr *addr = p;
4361 + memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
4363 + if(netif_running(dev))
4366 + ra2880MacAddressSet(addr->sa_data);
4371 +void set_fe_dma_glo_cfg(void)
4373 + int dma_glo_cfg=0;
4375 + dma_glo_cfg = (TX_WB_DDONE | RX_DMA_EN | TX_DMA_EN | PDMA_BT_SIZE_16DWORDS);
4377 + dma_glo_cfg |= (RX_2B_OFFSET);
4379 + sysRegWrite(DMA_GLO_CFG, dma_glo_cfg);
4380 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "DMA_GLO_CFG", DMA_GLO_CFG, dma_glo_cfg);
4383 +int forward_config(struct net_device *dev)
4385 + unsigned int regVal, regCsg;
4387 + regVal = sysRegRead(GDMA1_FWD_CFG);
4388 + regCsg = sysRegRead(CDMA_CSG_CFG);
4390 + //set unicast/multicast/broadcast frame to cpu
4391 + regVal &= ~0xFFFF;
4392 + regVal |= GDMA1_FWD_PORT;
4395 + //disable ipv4 header checksum check
4396 + regVal &= ~GDM1_ICS_EN;
4397 + regCsg &= ~ICS_GEN_EN;
4399 + //disable tcp checksum check
4400 + regVal &= ~GDM1_TCS_EN;
4401 + regCsg &= ~TCS_GEN_EN;
4403 + //disable udp checksum check
4404 + regVal &= ~GDM1_UCS_EN;
4405 + regCsg &= ~UCS_GEN_EN;
4408 + dev->features &= ~NETIF_F_IP_CSUM; /* disable checksum TCP/UDP over IPv4 */
4411 + sysRegWrite(GDMA1_FWD_CFG, regVal);
4412 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "GDMA1_FWD_CFG", GDMA1_FWD_CFG, regVal);
4413 + sysRegWrite(CDMA_CSG_CFG, regCsg);
4414 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "CDMA_CSG_CFG", CDMA_CSG_CFG, regCsg);
4417 + sysRegWrite(FE_RST_GL, regVal);
4418 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, regVal);
4419 + sysRegWrite(FE_RST_GL, 0); // update for RSTCTL issue
4420 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "FE_RST_GL", FE_RST_GL, 1);
4422 + regCsg = sysRegRead(CDMA_CSG_CFG);
4423 + printk("CDMA_CSG_CFG = %0X\n",regCsg);
4424 + regVal = sysRegRead(GDMA1_FWD_CFG);
4425 + printk("GDMA1_FWD_CFG = %0X\n",regVal);
4431 +static int rt2880_eth_recv(struct net_device* dev)
4433 + struct sk_buff *skb, *rx_skb;
4434 + unsigned int length = 0;
4435 + unsigned long RxProcessed;
4438 + int bReschedule = 0;
4439 + END_DEVICE* ei_local = netdev_priv(dev);
4445 + rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
4449 + if (RxProcessed++ > NUM_RX_MAX_PROCESS)
4451 + // need to reschedule rx handle
4458 + if (ei_local->rx_ring0[rx_dma_owner_idx0].rxd_info2.DDONE_bit == 1) {
4459 + rx_ring = ei_local->rx_ring0;
4460 + rx_dma_owner_idx = rx_dma_owner_idx0;
4465 + /* skb processing */
4466 + length = rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0;
4467 + rx_skb = ei_local->netrx0_skbuf[rx_dma_owner_idx];
4468 + rx_skb->data = ei_local->netrx0_skbuf[rx_dma_owner_idx]->data;
4469 + rx_skb->len = length;
4471 + rx_skb->data += NET_IP_ALIGN;
4473 + rx_skb->tail = rx_skb->data + length;
4475 + rx_skb->dev = dev;
4476 + rx_skb->protocol = eth_type_trans(rx_skb,dev);
4478 + rx_skb->ip_summed = CHECKSUM_NONE;
4481 + /* We have to check the free memory size is big enough
4482 + * before pass the packet to cpu*/
4483 + skb = __dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN, GFP_ATOMIC);
4485 + if (unlikely(skb == NULL))
4487 + printk(KERN_ERR "skb not available...\n");
4488 + ei_local->stat.rx_dropped++;
4498 + ei_local->stat.rx_packets++;
4499 + ei_local->stat.rx_bytes += length;
4503 + rx_ring[rx_dma_owner_idx].rxd_info2.PLEN0 = MAX_RX_LENGTH;
4504 + rx_ring[rx_dma_owner_idx].rxd_info2.LS0 = 0;
4505 + rx_ring[rx_dma_owner_idx].rxd_info2.DDONE_bit = 0;
4506 + rx_ring[rx_dma_owner_idx].rxd_info1.PDP0 = dma_map_single(NULL, skb->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
4508 + /* Move point to next RXD which wants to alloc*/
4509 + sysRegWrite(RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
4510 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_RX_CALC_IDX0", RAETH_RX_CALC_IDX0, rx_dma_owner_idx);
4511 + ei_local->netrx0_skbuf[rx_dma_owner_idx] = skb;
4513 + /* Update to Next packet point that was received.
4515 + rx_dma_owner_idx0 = (sysRegRead(RAETH_RX_CALC_IDX0) + 1) % NUM_RX_DESC;
4518 + return bReschedule;
4521 +void ei_receive_workq(struct work_struct *work)
4523 + struct net_device *dev = dev_raether;
4524 + END_DEVICE *ei_local = netdev_priv(dev);
4525 + unsigned long reg_int_mask=0;
4526 + int bReschedule=0;
4529 + if(tx_ring_full==0){
4530 + bReschedule = rt2880_eth_recv(dev);
4533 + schedule_work(&ei_local->rx_wq);
4535 + reg_int_mask=sysRegRead(RAETH_FE_INT_ENABLE);
4536 + sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
4537 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask| RX_DLY_INT);
4540 + schedule_work(&ei_local->rx_wq);
4545 +static irqreturn_t ei_interrupt(int irq, void *dev_id)
4547 + unsigned long reg_int_val;
4548 + unsigned long reg_int_mask=0;
4549 + unsigned int recv = 0;
4550 + unsigned int transmit __maybe_unused = 0;
4551 + unsigned long flags;
4553 + struct net_device *dev = (struct net_device *) dev_id;
4554 + END_DEVICE *ei_local = netdev_priv(dev);
4558 + printk (KERN_ERR "net_interrupt(): irq %x for unknown device.\n", IRQ_ENET0);
4563 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4564 + reg_int_val = sysRegRead(RAETH_FE_INT_STATUS);
4566 + if((reg_int_val & RX_DLY_INT))
4569 + if (reg_int_val & RAETH_TX_DLY_INT)
4572 + sysRegWrite(RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
4573 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_STATUS", RAETH_FE_INT_STATUS, RAETH_FE_INT_DLY_INIT);
4575 + ei_xmit_housekeeping(0);
4577 + if (((recv == 1) || (pending_recv ==1)) && (tx_ring_full==0))
4579 + reg_int_mask = sysRegRead(RAETH_FE_INT_ENABLE);
4580 + sysRegWrite(RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
4581 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, reg_int_mask & ~(RX_DLY_INT));
4583 + schedule_work(&ei_local->rx_wq);
4585 + else if (recv == 1 && tx_ring_full==1)
4589 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4591 + return IRQ_HANDLED;
4594 +static void esw_link_status_changed(int port_no, void *dev_id)
4596 + unsigned int reg_val;
4597 + mii_mgr_read(31, (0x3008 + (port_no*0x100)), ®_val);
4598 + if(reg_val & 0x1) {
4599 + printk("ESW: Link Status Changed - Port%d Link UP\n", port_no);
4601 + printk("ESW: Link Status Changed - Port%d Link Down\n", port_no);
4606 +static irqreturn_t esw_interrupt(int irq, void *dev_id)
4608 + unsigned long flags;
4609 + unsigned int reg_int_val;
4610 + struct net_device *dev = (struct net_device *) dev_id;
4611 + END_DEVICE *ei_local = netdev_priv(dev);
4613 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4614 + mii_mgr_read(31, 0x700c, ®_int_val);
4616 + if (reg_int_val & P4_LINK_CH) {
4617 + esw_link_status_changed(4, dev_id);
4620 + if (reg_int_val & P3_LINK_CH) {
4621 + esw_link_status_changed(3, dev_id);
4623 + if (reg_int_val & P2_LINK_CH) {
4624 + esw_link_status_changed(2, dev_id);
4626 + if (reg_int_val & P1_LINK_CH) {
4627 + esw_link_status_changed(1, dev_id);
4629 + if (reg_int_val & P0_LINK_CH) {
4630 + esw_link_status_changed(0, dev_id);
4633 + mii_mgr_write(31, 0x700c, 0x1f); //ack switch link change
4634 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4635 + return IRQ_HANDLED;
4640 +static int ei_start_xmit_fake(struct sk_buff* skb, struct net_device *dev)
4642 + return ei_start_xmit(skb, dev, 1);
4645 +static int ei_change_mtu(struct net_device *dev, int new_mtu)
4647 + unsigned long flags;
4648 + END_DEVICE *ei_local = netdev_priv(dev); // get priv ei_local pointer from net_dev structure
4650 + if ( ei_local == NULL ) {
4651 + printk(KERN_EMERG "%s: ei_change_mtu passed a non-existent private pointer from net_dev!\n", dev->name);
4655 + spin_lock_irqsave(&ei_local->page_lock, flags);
4657 + if ( (new_mtu > 4096) || (new_mtu < 64)) {
4658 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
4662 + if ( new_mtu > 1500 ) {
4663 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
4667 + dev->mtu = new_mtu;
4669 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
4674 +static const struct net_device_ops ei_netdev_ops = {
4675 + .ndo_init = rather_probe,
4676 + .ndo_open = ei_open,
4677 + .ndo_stop = ei_close,
4678 + .ndo_start_xmit = ei_start_xmit_fake,
4679 + .ndo_set_mac_address = eth_mac_addr,
4680 + .ndo_change_mtu = ei_change_mtu,
4681 + .ndo_validate_addr = eth_validate_addr,
4684 +void ra2880_setup_dev_fptable(struct net_device *dev)
4686 + RAETH_PRINT(__FUNCTION__ "is called!\n");
4688 + dev->netdev_ops = &ei_netdev_ops;
4689 +#define TX_TIMEOUT (5*HZ)
4690 + dev->watchdog_timeo = TX_TIMEOUT;
4694 +void fe_reset(void)
4697 + val = sysRegRead(RSTCTRL);
4699 + val = val | RALINK_FE_RST;
4700 + sysRegWrite(RSTCTRL, val);
4701 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
4702 + val = val & ~(RALINK_FE_RST);
4703 + sysRegWrite(RSTCTRL, val);
4704 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RSTCTRL", RSTCTRL, val);
4707 +void ei_reset_task(struct work_struct *work)
4709 + struct net_device *dev = dev_raether;
4717 +void ei_tx_timeout(struct net_device *dev)
4719 + END_DEVICE *ei_local = netdev_priv(dev);
4721 + schedule_work(&ei_local->reset_task);
4724 +int __init rather_probe(struct net_device *dev)
4726 + END_DEVICE *ei_local = netdev_priv(dev);
4727 + struct sockaddr addr;
4728 + unsigned char mac_addr01234[5] = {0x00, 0x0C, 0x43, 0x28, 0x80};
4731 + net_srandom(jiffies);
4732 + memcpy(addr.sa_data, mac_addr01234, 5);
4733 + addr.sa_data[5] = net_random()&0xFF;
4734 + ei_set_mac_addr(dev, &addr);
4735 + spin_lock_init(&ei_local->page_lock);
4742 +int ei_open(struct net_device *dev)
4745 + unsigned long flags;
4746 + END_DEVICE *ei_local;
4749 + if (!try_module_get(THIS_MODULE))
4751 + printk("%s: Cannot reserve module\n", __FUNCTION__);
4754 + printk("Raeth %s (",RAETH_VERSION);
4755 + printk("Workqueue");
4758 + ei_local = netdev_priv(dev); // get device pointer from System
4759 + // unsigned int flags;
4761 + if (ei_local == NULL)
4763 + printk(KERN_EMERG "%s: ei_open passed a non-existent device!\n", dev->name);
4767 + /* receiving packet buffer allocation - NUM_RX_DESC x MAX_RX_LENGTH */
4768 + for ( i = 0; i < NUM_RX_DESC; i++)
4770 + ei_local->netrx0_skbuf[i] = dev_alloc_skb(MAX_RX_LENGTH + NET_IP_ALIGN);
4771 + if (ei_local->netrx0_skbuf[i] == NULL ) {
4772 + printk("rx skbuff buffer allocation failed!");
4777 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4779 + fe_sw_init(); //initialize fe and switch register
4780 + err = request_irq( dev->irq, ei_interrupt, 0, dev->name, dev); // try to fix irq in open
4784 + if ( dev->dev_addr != NULL) {
4785 + ra2880MacAddressSet((void *)(dev->dev_addr));
4787 + printk("dev->dev_addr is empty !\n");
4789 + mii_mgr_write(31, 0x7008, 0x1f); //enable switch link change intr
4790 + err = request_irq(31, esw_interrupt, IRQF_DISABLED, "Ralink_ESW", dev);
4794 + sysRegWrite(RAETH_DLY_INT_CFG, DELAY_INT_INIT);
4795 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RAETH_DLY_INT_CFG", RAETH_DLY_INT_CFG, DELAY_INT_INIT);
4796 + sysRegWrite(RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
4797 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "RAETH_FE_INT_ENABLE", RAETH_FE_INT_ENABLE, RAETH_FE_INT_DLY_INIT);
4799 + INIT_WORK(&ei_local->reset_task, ei_reset_task);
4801 + INIT_WORK(&ei_local->rx_wq, ei_receive_workq);
4803 + netif_start_queue(dev);
4806 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4809 + forward_config(dev);
4813 +int ei_close(struct net_device *dev)
4816 + END_DEVICE *ei_local = netdev_priv(dev); // device pointer
4817 + unsigned long flags;
4818 + spin_lock_irqsave(&(ei_local->page_lock), flags);
4820 + cancel_work_sync(&ei_local->reset_task);
4821 + netif_stop_queue(dev);
4822 + ra2880stop(ei_local);
4825 + cancel_work_sync(&ei_local->rx_wq);
4826 + free_irq(dev->irq, dev);
4827 + free_irq(31, dev);
4828 + for ( i = 0; i < NUM_RX_DESC; i++)
4830 + if (ei_local->netrx0_skbuf[i] != NULL) {
4831 + dev_kfree_skb(ei_local->netrx0_skbuf[i]);
4832 + ei_local->netrx0_skbuf[i] = NULL;
4835 + if (ei_local->tx_ring0 != NULL) {
4836 + pci_free_consistent(NULL, NUM_TX_DESC*sizeof(struct PDMA_txdesc), ei_local->tx_ring0, ei_local->phy_tx_ring0);
4838 + pci_free_consistent(NULL, NUM_RX_DESC*sizeof(struct PDMA_rxdesc), ei_local->rx_ring0, ei_local->phy_rx_ring0);
4840 + printk("Free TX/RX Ring Memory!\n");
4843 + spin_unlock_irqrestore(&(ei_local->page_lock), flags);
4845 + module_put(THIS_MODULE);
4850 +void setup_internal_gsw(void)
4855 + /* reduce RGMII2 PAD driving strength */
4856 + *(volatile u_long *)(PAD_RGMII2_MDIO_CFG) &= ~(0x3 << 4);
4858 + //RGMII1=Normal mode
4859 + *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) &= ~(0x1 << 14);
4861 + //GMAC1= RGMII mode
4862 + *(volatile u_long *)(SYSCFG1) &= ~(0x3 << 12);
4864 + //enable MDIO to control MT7530
4865 + regValue = le32_to_cpu(*(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60));
4866 + regValue &= ~(0x3 << 12);
4867 + *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x60) = regValue;
4872 + mii_mgr_read(i, 0x0 ,®Value);
4873 + regValue |= (0x1<<11);
4874 + mii_mgr_write(i, 0x0, regValue);
4876 + mii_mgr_write(31, 0x7000, 0x3); //reset switch
4879 + if(sysRegRead(0xbe00000c)==0x00030101) {
4880 + sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e30b);//(GE1, Force 1000M/FD, FC ON)
4881 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e30b);
4882 + mii_mgr_write(31, 0x3600, 0x5e30b);
4884 + sysRegWrite(RALINK_ETH_SW_BASE+0x100, 0x2005e33b);//(GE1, Force 1000M/FD, FC ON)
4885 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x100", RALINK_ETH_SW_BASE+0x100, 0x2005e33b);
4886 + mii_mgr_write(31, 0x3600, 0x5e33b);
4889 + sysRegWrite(RALINK_ETH_SW_BASE+0x200, 0x00008000);//(GE2, Link down)
4890 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RALINK_ETH_SW_BASE+0x200", RALINK_ETH_SW_BASE+0x200, 0x00008000);
4892 + //regValue = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable*/
4893 + mii_mgr_read(31, 0x7804 ,®Value);
4894 + regValue &= ~(1<<8); //Enable Port 6
4895 + regValue |= (1<<6); //Disable Port 5
4896 + regValue |= (1<<13); //Port 5 as GMAC, no Internal PHY
4898 + regValue |= (1<<16);//change HW-TRAP
4899 + printk("change HW-TRAP to 0x%x!!!!!!!!!!!!",regValue);
4900 + mii_mgr_write(31, 0x7804 ,regValue);
4901 + regValue = *(volatile u_long *)(RALINK_SYSCTL_BASE + 0x10);
4902 + regValue = (regValue >> 6) & 0x7;
4903 + if(regValue >= 6) { //25Mhz Xtal
4905 + } else if(regValue >=3) { //40Mhz
4907 + mii_mgr_write(0, 13, 0x1f); // disable MT7530 core clock
4908 + mii_mgr_write(0, 14, 0x410);
4909 + mii_mgr_write(0, 13, 0x401f);
4910 + mii_mgr_write(0, 14, 0x0);
4912 + mii_mgr_write(0, 13, 0x1f); // disable MT7530 PLL
4913 + mii_mgr_write(0, 14, 0x40d);
4914 + mii_mgr_write(0, 13, 0x401f);
4915 + mii_mgr_write(0, 14, 0x2020);
4917 + mii_mgr_write(0, 13, 0x1f); // for MT7530 core clock = 500Mhz
4918 + mii_mgr_write(0, 14, 0x40e);
4919 + mii_mgr_write(0, 13, 0x401f);
4920 + mii_mgr_write(0, 14, 0x119);
4922 + mii_mgr_write(0, 13, 0x1f); // enable MT7530 PLL
4923 + mii_mgr_write(0, 14, 0x40d);
4924 + mii_mgr_write(0, 13, 0x401f);
4925 + mii_mgr_write(0, 14, 0x2820);
4927 + udelay(20); //suggest by CD
4929 + mii_mgr_write(0, 13, 0x1f); // enable MT7530 core clock
4930 + mii_mgr_write(0, 14, 0x410);
4931 + mii_mgr_write(0, 13, 0x401f);
4932 + }else { //20Mhz Xtal
4937 + mii_mgr_write(0, 14, 0x1); /*RGMII*/
4940 + mii_mgr_write(31, 0x7b00, 0x102); //delay setting for 10/1000M
4941 + mii_mgr_write(31, 0x7b04, 0x14); //delay setting for 10/1000M
4943 + mii_mgr_write(31, 0x7b00, 8); // delay setting for 100M
4944 + mii_mgr_write(31, 0x7b04, 0x14); // for 100M
4947 + mii_mgr_write(31, 0x7a54, 0x44); //lower driving
4948 + mii_mgr_write(31, 0x7a5c, 0x44); //lower driving
4949 + mii_mgr_write(31, 0x7a64, 0x44); //lower driving
4950 + mii_mgr_write(31, 0x7a6c, 0x44); //lower driving
4951 + mii_mgr_write(31, 0x7a74, 0x44); //lower driving
4952 + mii_mgr_write(31, 0x7a7c, 0x44); //lower driving
4957 + mii_mgr_read(i, 0x0 ,®Value);
4958 + regValue &= ~(0x1<<11);
4959 + mii_mgr_write(i, 0x0, regValue);
4962 + mii_mgr_read(31, 0x7808 ,®Value);
4963 + regValue |= (3<<16); //Enable INTR
4964 + mii_mgr_write(31, 0x7808 ,regValue);
4967 +int __init ra2882eth_init(void)
4970 + struct net_device *dev = alloc_etherdev(sizeof(END_DEVICE));
4974 + strcpy(dev->name, DEV_NAME);
4975 + dev->irq = IRQ_ENET0;
4976 + dev->addr_len = 6;
4977 + dev->base_addr = RALINK_FRAME_ENGINE_BASE;
4979 + rather_probe(dev);
4980 + ra2880_setup_dev_fptable(dev);
4982 + if ( register_netdev(dev) != 0) {
4983 + printk(KERN_WARNING " " __FILE__ ": No ethernet port found.\n");
4988 + dev_raether = dev;
4992 +void fe_sw_init(void)
4994 + setup_internal_gsw();
4998 +void ra2882eth_cleanup_module(void)
5001 +EXPORT_SYMBOL(set_fe_dma_glo_cfg);
5002 +module_init(ra2882eth_init);
5003 +module_exit(ra2882eth_cleanup_module);
5004 +MODULE_LICENSE("GPL");
5005 diff --git a/drivers/net/ethernet/raeth/raether.h b/drivers/net/ethernet/raeth/raether.h
5006 new file mode 100644
5007 index 0000000..49326d1
5009 +++ b/drivers/net/ethernet/raeth/raether.h
5011 +#ifndef RA2882ETHEND_H
5012 +#define RA2882ETHEND_H
5014 +#ifdef DSP_VIA_NONCACHEABLE
5015 +#define ESRAM_BASE 0xa0800000 /* 0x0080-0000 ~ 0x00807FFF */
5017 +#define ESRAM_BASE 0x80800000 /* 0x0080-0000 ~ 0x00807FFF */
5020 +#define RX_RING_BASE ((int)(ESRAM_BASE + 0x7000))
5021 +#define TX_RING_BASE ((int)(ESRAM_BASE + 0x7800))
5023 +#if defined(CONFIG_RALINK_RT2880)
5024 +#define NUM_TX_RINGS 1
5026 +#define NUM_TX_RINGS 4
5028 +#ifdef MEMORY_OPTIMIZATION
5029 +#ifdef CONFIG_RAETH_ROUTER
5030 +#define NUM_RX_DESC 128
5031 +#define NUM_TX_DESC 128
5032 +#elif CONFIG_RT_3052_ESW
5033 +#define NUM_RX_DESC 64
5034 +#define NUM_TX_DESC 64
5036 +#define NUM_RX_DESC 128
5037 +#define NUM_TX_DESC 128
5039 +//#define NUM_RX_MAX_PROCESS 32
5040 +#define NUM_RX_MAX_PROCESS 64
5042 +#if defined (CONFIG_RAETH_ROUTER)
5043 +#define NUM_RX_DESC 256
5044 +#define NUM_TX_DESC 256
5045 +#elif defined (CONFIG_RT_3052_ESW)
5046 +#define NUM_RX_DESC 256
5047 +#define NUM_TX_DESC 256
5049 +#define NUM_RX_DESC 256
5050 +#define NUM_TX_DESC 256
5052 +#if defined(CONFIG_RALINK_RT3883) || defined(CONFIG_RALINK_MT7620)
5053 +#define NUM_RX_MAX_PROCESS 2
5055 +#define NUM_RX_MAX_PROCESS 16
5059 +#define DEV_NAME "eth0"
5060 +#define DEV2_NAME "eth3"
5062 +#if defined (CONFIG_RALINK_RT6855A) || defined (CONFIG_RALINK_MT7621)
5063 +#define GMAC0_OFFSET 0xE000
5064 +#define GMAC2_OFFSET 0xE006
5066 +#define GMAC0_OFFSET 0x28
5067 +#define GMAC2_OFFSET 0x22
5070 +#if defined(CONFIG_RALINK_RT6855A)
5071 +#define IRQ_ENET0 22
5073 +#define IRQ_ENET0 11 /* hardware interrupt #3, defined in RT2880 Soc Design Spec Rev 0.03, pp43 */
5076 +#define FE_INT_STATUS_REG (*(volatile unsigned long *)(FE_INT_STATUS))
5077 +#define FE_INT_STATUS_CLEAN(reg) (*(volatile unsigned long *)(FE_INT_STATUS)) = reg
5079 +//#define RAETH_DEBUG
5081 +#define RAETH_PRINT(fmt, args...) printk(KERN_INFO fmt, ## args)
5083 +#define RAETH_PRINT(fmt, args...) { }
5086 +struct net_device_stats *ra_get_stats(struct net_device *dev);
5088 +void ei_tx_timeout(struct net_device *dev);
5089 +int rather_probe(struct net_device *dev);
5090 +int ei_open(struct net_device *dev);
5091 +int ei_close(struct net_device *dev);
5093 +int ra2882eth_init(void);
5094 +void ra2882eth_cleanup_module(void);
5096 +void ei_xmit_housekeeping(unsigned long data);
5098 +u32 mii_mgr_read(u32 phy_addr, u32 phy_register, u32 *read_data);
5099 +u32 mii_mgr_write(u32 phy_addr, u32 phy_register, u32 write_data);
5100 +void fe_sw_init(void);
5103 diff --git a/drivers/net/ethernet/raeth/raether_pdma.c b/drivers/net/ethernet/raeth/raether_pdma.c
5104 new file mode 100644
5105 index 0000000..4f1b154
5107 +++ b/drivers/net/ethernet/raeth/raether_pdma.c
5109 +#include <linux/module.h>
5110 +#include <linux/version.h>
5111 +#include <linux/kernel.h>
5112 +#include <linux/types.h>
5113 +#include <linux/pci.h>
5114 +#include <linux/init.h>
5115 +#include <linux/skbuff.h>
5116 +#include <linux/if_vlan.h>
5117 +#include <linux/if_ether.h>
5118 +#include <linux/fs.h>
5119 +#include <asm/uaccess.h>
5120 +#include <linux/delay.h>
5121 +#include <linux/sched.h>
5122 +#include <asm/rt2880/rt_mmap.h>
5123 +#include "ra2882ethreg.h"
5124 +#include "raether.h"
5125 +#include "ra_mac.h"
5127 +#define MAX_RX_LENGTH 1536
5129 +extern int reg_dbg;
5130 +extern struct net_device *dev_raether;
5131 +static unsigned long tx_ring_full=0;
5133 +#define KSEG1 0xa0000000
5134 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
5135 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
5137 +extern void set_fe_dma_glo_cfg(void);
5139 +int fe_dma_init(struct net_device *dev)
5143 + unsigned int regVal;
5144 + END_DEVICE* ei_local = netdev_priv(dev);
5148 + regVal = sysRegRead(PDMA_GLO_CFG);
5149 + if((regVal & RX_DMA_BUSY))
5151 + printk("\n RX_DMA_BUSY !!! ");
5154 + if((regVal & TX_DMA_BUSY))
5156 + printk("\n TX_DMA_BUSY !!! ");
5162 + for (i=0;i<NUM_TX_DESC;i++){
5163 + ei_local->skb_free[i]=0;
5165 + ei_local->free_idx =0;
5166 + ei_local->tx_ring0 = pci_alloc_consistent(NULL, NUM_TX_DESC * sizeof(struct PDMA_txdesc), &ei_local->phy_tx_ring0);
5167 + printk("\nphy_tx_ring = 0x%08x, tx_ring = 0x%p\n", ei_local->phy_tx_ring0, ei_local->tx_ring0);
5169 + for (i=0; i < NUM_TX_DESC; i++) {
5170 + memset(&ei_local->tx_ring0[i],0,sizeof(struct PDMA_txdesc));
5171 + ei_local->tx_ring0[i].txd_info2.LS0_bit = 1;
5172 + ei_local->tx_ring0[i].txd_info2.DDONE_bit = 1;
5176 + /* Initial RX Ring 0*/
5177 + ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
5178 + for (i = 0; i < NUM_RX_DESC; i++) {
5179 + memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
5180 + ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
5181 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
5182 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
5183 + ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
5185 + printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
5188 + regVal = sysRegRead(PDMA_GLO_CFG);
5189 + regVal &= 0x000000FF;
5190 + sysRegWrite(PDMA_GLO_CFG, regVal);
5191 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "PDMA_GLO_CFG", PDMA_GLO_CFG, regVal);
5193 + regVal=sysRegRead(PDMA_GLO_CFG);
5195 + /* Tell the adapter where the TX/RX rings are located. */
5196 + sysRegWrite(TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
5197 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_BASE_PTR0", TX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_tx_ring0));
5198 + sysRegWrite(TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
5199 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_MAX_CNT0", TX_MAX_CNT0, cpu_to_le32((u32) NUM_TX_DESC));
5200 + sysRegWrite(TX_CTX_IDX0, 0);
5201 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "TX_CTX_IDX0", TX_CTX_IDX0, 0);
5202 + sysRegWrite(PDMA_RST_CFG, PST_DTX_IDX0);
5203 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DTX_IDX0);
5205 + sysRegWrite(RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
5206 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_BASE_PTR0", RX_BASE_PTR0, phys_to_bus((u32) ei_local->phy_rx_ring0));
5207 + sysRegWrite(RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
5208 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_MAX_CNT0", RX_MAX_CNT0, cpu_to_le32((u32) NUM_RX_DESC));
5209 + sysRegWrite(RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5210 + if (reg_dbg) printk("-> %s 0x%08x 0x%08x\n", "RX_CALC_IDX0", RX_CALC_IDX0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5211 + sysRegWrite(PDMA_RST_CFG, PST_DRX_IDX0);
5212 + if (reg_dbg) printk("-> %s 0x%08x 0x%08lx\n", "PDMA_RST_CFG", PDMA_RST_CFG, PST_DRX_IDX0);
5214 + set_fe_dma_glo_cfg();
5219 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
5221 + unsigned int length=skb->len;
5222 + END_DEVICE* ei_local = netdev_priv(dev);
5223 + unsigned long tx_cpu_owner_idx0 = sysRegRead(TX_CTX_IDX0);
5225 + while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
5227 + ei_local->stat.tx_errors++;
5230 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info1.SDP0 = virt_to_phys(skb->data);
5231 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.SDL0 = length;
5232 + if (gmac_no == 1) {
5233 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 1;
5235 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info4.FPORT = 2;
5237 + ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit = 0;
5238 + tx_cpu_owner_idx0 = (tx_cpu_owner_idx0+1) % NUM_TX_DESC;
5239 + while(ei_local->tx_ring0[tx_cpu_owner_idx0].txd_info2.DDONE_bit == 0)
5241 + ei_local->stat.tx_errors++;
5243 + sysRegWrite(TX_CTX_IDX0, cpu_to_le32((u32)tx_cpu_owner_idx0));
5246 + ei_local->stat.tx_packets++;
5247 + ei_local->stat.tx_bytes += length;
5253 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
5255 + END_DEVICE *ei_local = netdev_priv(dev);
5256 + unsigned long flags;
5257 + unsigned long tx_cpu_owner_idx;
5258 + unsigned int tx_cpu_owner_idx_next;
5259 + unsigned int num_of_txd;
5260 + unsigned int tx_cpu_owner_idx_next2;
5262 + dev->trans_start = jiffies; /* save the timestamp */
5263 + spin_lock_irqsave(&ei_local->page_lock, flags);
5264 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5266 + tx_cpu_owner_idx = sysRegRead(TX_CTX_IDX0);
5268 + tx_cpu_owner_idx_next = (tx_cpu_owner_idx + num_of_txd) % NUM_TX_DESC;
5270 + if(((ei_local->skb_free[tx_cpu_owner_idx]) ==0) && (ei_local->skb_free[tx_cpu_owner_idx_next]==0)){
5271 + rt2880_eth_send(dev, skb, gmac_no);
5273 + tx_cpu_owner_idx_next2 = (tx_cpu_owner_idx_next + 1) % NUM_TX_DESC;
5275 + if(ei_local->skb_free[tx_cpu_owner_idx_next2]!=0){
5278 + ei_local->stat.tx_dropped++;
5280 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5284 + ei_local->skb_free[tx_cpu_owner_idx] = skb;
5285 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
5289 +void ei_xmit_housekeeping(unsigned long unused)
5291 + struct net_device *dev = dev_raether;
5292 + END_DEVICE *ei_local = netdev_priv(dev);
5293 + struct PDMA_txdesc *tx_desc;
5294 + unsigned long skb_free_idx;
5295 + unsigned long tx_dtx_idx __maybe_unused;
5296 + unsigned long reg_int_mask=0;
5298 + tx_dtx_idx = sysRegRead(TX_DTX_IDX0);
5299 + tx_desc = ei_local->tx_ring0;
5300 + skb_free_idx = ei_local->free_idx;
5301 + if ((ei_local->skb_free[skb_free_idx]) != 0 && tx_desc[skb_free_idx].txd_info2.DDONE_bit==1) {
5302 + while(tx_desc[skb_free_idx].txd_info2.DDONE_bit==1 && (ei_local->skb_free[skb_free_idx])!=0 ){
5303 + dev_kfree_skb_any(ei_local->skb_free[skb_free_idx]);
5304 + ei_local->skb_free[skb_free_idx]=0;
5305 + skb_free_idx = (skb_free_idx +1) % NUM_TX_DESC;
5308 + netif_wake_queue(dev);
5310 + ei_local->free_idx = skb_free_idx;
5313 + reg_int_mask=sysRegRead(FE_INT_ENABLE);
5314 + sysRegWrite(FE_INT_ENABLE, reg_int_mask| TX_DLY_INT);
5317 +EXPORT_SYMBOL(ei_start_xmit);
5318 +EXPORT_SYMBOL(ei_xmit_housekeeping);
5319 +EXPORT_SYMBOL(fe_dma_init);
5320 +EXPORT_SYMBOL(rt2880_eth_send);
5321 diff --git a/drivers/net/ethernet/raeth/raether_qdma.c b/drivers/net/ethernet/raeth/raether_qdma.c
5322 new file mode 100644
5323 index 0000000..4ad2f42
5325 +++ b/drivers/net/ethernet/raeth/raether_qdma.c
5327 +#include <linux/module.h>
5328 +#include <linux/version.h>
5329 +#include <linux/kernel.h>
5330 +#include <linux/types.h>
5331 +#include <linux/pci.h>
5332 +#include <linux/init.h>
5333 +#include <linux/skbuff.h>
5334 +#include <linux/if_vlan.h>
5335 +#include <linux/if_ether.h>
5336 +#include <linux/fs.h>
5337 +#include <asm/uaccess.h>
5338 +#include <asm/rt2880/surfboardint.h>
5339 +#if defined (CONFIG_RAETH_TSO)
5340 +#include <linux/tcp.h>
5341 +#include <net/ipv6.h>
5342 +#include <linux/ip.h>
5343 +#include <net/ip.h>
5344 +#include <net/tcp.h>
5345 +#include <linux/in.h>
5346 +#include <linux/ppp_defs.h>
5347 +#include <linux/if_pppox.h>
5349 +#include <linux/delay.h>
5350 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,35)
5351 +#include <linux/sched.h>
5354 +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0)
5355 +#include <asm/rt2880/rt_mmap.h>
5357 +#include <linux/libata-compat.h>
5360 +#include "ra2882ethreg.h"
5361 +#include "raether.h"
5362 +#include "ra_mac.h"
5363 +#include "ra_ioctl.h"
5364 +#include "ra_rfrw.h"
5365 +#ifdef CONFIG_RAETH_NETLINK
5366 +#include "ra_netlink.h"
5368 +#if defined (CONFIG_RAETH_QOS)
5369 +#include "ra_qos.h"
5372 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
5373 +#include "../../../net/nat/hw_nat/ra_nat.h"
5376 +#if defined (TASKLET_WORKQUEUE_SW)
5378 +int working_schedule;
5382 +#if !defined(CONFIG_RA_NAT_NONE)
5385 +extern int (*ra_sw_nat_hook_rx)(struct sk_buff *skb);
5386 +extern int (*ra_sw_nat_hook_tx)(struct sk_buff *skb, int gmac_no);
5389 +#if defined(CONFIG_RA_CLASSIFIER)||defined(CONFIG_RA_CLASSIFIER_MODULE)
5392 +#include <asm/mipsregs.h>
5393 +extern int (*ra_classifier_hook_tx)(struct sk_buff *skb, unsigned long cur_cycle);
5394 +extern int (*ra_classifier_hook_rx)(struct sk_buff *skb, unsigned long cur_cycle);
5395 +#endif /* CONFIG_RA_CLASSIFIER */
5397 +#if defined (CONFIG_RALINK_RT3052_MP2)
5398 +int32_t mcast_rx(struct sk_buff * skb);
5399 +int32_t mcast_tx(struct sk_buff * skb);
5402 +#ifdef RA_MTD_RW_BY_NUM
5403 +int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
5405 +int ra_mtd_read_nm(char *name, loff_t from, size_t len, u_char *buf);
5408 +/* gmac driver feature set config */
5409 +#if defined (CONFIG_RAETH_NAPI) || defined (CONFIG_RAETH_QOS)
5412 +#define DELAY_INT 1
5415 +//#define CONFIG_UNH_TEST
5416 +/* end of config */
5418 +#if defined (CONFIG_RAETH_JUMBOFRAME)
5419 +#define MAX_RX_LENGTH 4096
5421 +#define MAX_RX_LENGTH 1536
5424 +extern struct net_device *dev_raether;
5426 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5427 +static int rx_dma_owner_idx1;
5428 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5429 +static int rx_calc_idx1;
5432 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5433 +static int rx_calc_idx0;
5434 +static unsigned long tx_cpu_owner_idx0=0;
5436 +static unsigned long tx_ring_full=0;
5438 +#if defined (CONFIG_ETHTOOL) && defined (CONFIG_RAETH_ROUTER)
5439 +#include "ra_ethtool.h"
5440 +extern struct ethtool_ops ra_ethtool_ops;
5441 +#ifdef CONFIG_PSEUDO_SUPPORT
5442 +extern struct ethtool_ops ra_virt_ethtool_ops;
5443 +#endif // CONFIG_PSEUDO_SUPPORT //
5444 +#endif // (CONFIG_ETHTOOL //
5446 +#ifdef CONFIG_RALINK_VISTA_BASIC
5447 +int is_switch_175c = 1;
5450 +//skb->mark to queue mapping table
5451 +extern unsigned int M2Q_table[64];
5454 +#define KSEG1 0xa0000000
5455 +#define PHYS_TO_VIRT(x) ((void *)((x) | KSEG1))
5456 +#define VIRT_TO_PHYS(x) ((unsigned long)(x) & ~KSEG1)
5458 +extern void set_fe_dma_glo_cfg(void);
5463 + * @brief: get the TXD index from its address
5467 + * @return: TXD index
5470 +static unsigned int GET_TXD_OFFSET(struct QDMA_txdesc **cpu_ptr)
5472 + struct net_device *dev = dev_raether;
5473 + END_DEVICE *ei_local = netdev_priv(dev);
5475 + ctx_offset = (((((u32)*cpu_ptr) <<8)>>8) - ((((u32)ei_local->txd_pool)<<8)>>8))/ sizeof(struct QDMA_txdesc);
5476 + ctx_offset = (*cpu_ptr - ei_local->txd_pool);
5478 + return ctx_offset;
5484 + * @brief get free TXD from TXD queue
5490 +static int get_free_txd(struct QDMA_txdesc **free_txd)
5492 + struct net_device *dev = dev_raether;
5493 + END_DEVICE *ei_local = netdev_priv(dev);
5494 + unsigned int tmp_idx;
5496 + if(ei_local->free_txd_num > 0){
5497 + tmp_idx = ei_local->free_txd_head;
5498 + ei_local->free_txd_head = ei_local->txd_pool_info[tmp_idx];
5499 + ei_local->free_txd_num -= 1;
5500 + *free_txd = &ei_local->txd_pool[tmp_idx];
5503 + return NUM_TX_DESC;
5508 + * @brief add free TXD into TXD queue
5514 +int put_free_txd(int free_txd_idx)
5516 + struct net_device *dev = dev_raether;
5517 + END_DEVICE *ei_local = netdev_priv(dev);
5518 + ei_local->txd_pool_info[ei_local->free_txd_tail] = free_txd_idx;
5519 + ei_local->free_txd_tail = free_txd_idx;
5520 + ei_local->txd_pool_info[free_txd_idx] = NUM_TX_DESC;
5521 + ei_local->free_txd_num += 1;
5525 +/*define qdma initial alloc*/
5534 +bool qdma_tx_desc_alloc(void)
5536 + struct net_device *dev = dev_raether;
5537 + END_DEVICE *ei_local = netdev_priv(dev);
5538 + struct QDMA_txdesc *free_txd = NULL;
5539 + unsigned int txd_idx;
5543 + ei_local->txd_pool = pci_alloc_consistent(NULL, sizeof(struct QDMA_txdesc) * NUM_TX_DESC, &ei_local->phy_txd_pool);
5544 + printk("txd_pool=%p phy_txd_pool=%08X\n", ei_local->txd_pool , ei_local->phy_txd_pool);
5546 + if (ei_local->txd_pool == NULL) {
5547 + printk("adapter->txd_pool allocation failed!\n");
5550 + printk("ei_local->skb_free start address is 0x%p.\n", ei_local->skb_free);
5551 + //set all txd_pool_info to 0.
5552 + for ( i = 0; i < NUM_TX_DESC; i++)
5554 + ei_local->skb_free[i]= 0;
5555 + ei_local->txd_pool_info[i] = i + 1;
5556 + ei_local->txd_pool[i].txd_info3.LS_bit = 1;
5557 + ei_local->txd_pool[i].txd_info3.OWN_bit = 1;
5560 + ei_local->free_txd_head = 0;
5561 + ei_local->free_txd_tail = NUM_TX_DESC - 1;
5562 + ei_local->free_txd_num = NUM_TX_DESC;
5565 + //get free txd from txd pool
5566 + txd_idx = get_free_txd(&free_txd);
5567 + if( txd_idx == NUM_TX_DESC) {
5568 + printk("get_free_txd fail\n");
5572 + //add null TXD for transmit
5573 + ei_local->tx_dma_ptr = VIRT_TO_PHYS(free_txd);
5574 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5575 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
5576 + sysRegWrite(QTX_DTX_PTR, ei_local->tx_dma_ptr);
5578 + //get free txd from txd pool
5580 + txd_idx = get_free_txd(&free_txd);
5581 + if( txd_idx == NUM_TX_DESC) {
5582 + printk("get_free_txd fail\n");
5585 + // add null TXD for release
5586 + sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(free_txd));
5587 + sysRegWrite(QTX_DRX_PTR, VIRT_TO_PHYS(free_txd));
5589 + printk("free_txd: %p, ei_local->cpu_ptr: %08X\n", free_txd, ei_local->tx_cpu_ptr);
5591 + printk(" POOL HEAD_PTR | DMA_PTR | CPU_PTR \n");
5592 + printk("----------------+---------+--------\n");
5594 + printk(" 0x%p 0x%08X 0x%08X\n",ei_local->txd_pool,
5595 + ei_local->tx_dma_ptr, ei_local->tx_cpu_ptr);
5600 +bool fq_qdma_init(void)
5602 + struct QDMA_txdesc *free_head = NULL;
5603 + unsigned int free_head_phy;
5604 + unsigned int free_tail_phy;
5605 + unsigned int *free_page_head = NULL;
5606 + unsigned int free_page_head_phy;
5609 + free_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * sizeof(struct QDMA_txdesc), &free_head_phy);
5610 + if (unlikely(free_head == NULL)){
5611 + printk(KERN_ERR "QDMA FQ decriptor not available...\n");
5614 + memset(free_head, 0x0, sizeof(struct QDMA_txdesc) * NUM_QDMA_PAGE);
5616 + free_page_head = pci_alloc_consistent(NULL, NUM_QDMA_PAGE * QDMA_PAGE_SIZE, &free_page_head_phy);
5617 + if (unlikely(free_page_head == NULL)){
5618 + printk(KERN_ERR "QDMA FQ pager not available...\n");
5621 + for (i=0; i < NUM_QDMA_PAGE; i++) {
5622 + free_head[i].txd_info1.SDP = (free_page_head_phy + (i * QDMA_PAGE_SIZE));
5623 + if(i < (NUM_QDMA_PAGE-1)){
5624 + free_head[i].txd_info2.NDP = (free_head_phy + ((i+1) * sizeof(struct QDMA_txdesc)));
5628 + printk("free_head_phy[%d] is 0x%x!!!\n",i, VIRT_TO_PHYS(&free_head[i]) );
5629 + printk("free_head[%d] is 0x%x!!!\n",i, &free_head[i] );
5630 + printk("free_head[%d].txd_info1.SDP is 0x%x!!!\n",i, free_head[i].txd_info1.SDP );
5631 + printk("free_head[%d].txd_info2.NDP is 0x%x!!!\n",i, free_head[i].txd_info2.NDP );
5634 + free_head[i].txd_info3.SDL = QDMA_PAGE_SIZE;
5637 + free_tail_phy = (free_head_phy + (u32)((NUM_QDMA_PAGE-1) * sizeof(struct QDMA_txdesc)));
5639 + printk("free_head_phy is 0x%x!!!\n", free_head_phy);
5640 + printk("free_tail_phy is 0x%x!!!\n", free_tail_phy);
5641 + sysRegWrite(QDMA_FQ_HEAD, (u32)free_head_phy);
5642 + sysRegWrite(QDMA_FQ_TAIL, (u32)free_tail_phy);
5643 + sysRegWrite(QDMA_FQ_CNT, ((NUM_TX_DESC << 16) | NUM_QDMA_PAGE));
5644 + sysRegWrite(QDMA_FQ_BLEN, QDMA_PAGE_SIZE << 16);
5648 +int fe_dma_init(struct net_device *dev)
5652 + unsigned int regVal;
5653 + END_DEVICE* ei_local = netdev_priv(dev);
5659 + regVal = sysRegRead(QDMA_GLO_CFG);
5660 + if((regVal & RX_DMA_BUSY))
5662 + printk("\n RX_DMA_BUSY !!! ");
5665 + if((regVal & TX_DMA_BUSY))
5667 + printk("\n TX_DMA_BUSY !!! ");
5672 + /*tx desc alloc, add a NULL TXD to HW*/
5674 + qdma_tx_desc_alloc();
5677 + /* Initial RX Ring 0*/
5678 +#ifdef CONFIG_32B_DESC
5679 + ei_local->rx_ring0 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
5680 + ei_local->phy_rx_ring0 = virt_to_phys(ei_local->rx_ring0);
5682 + ei_local->rx_ring0 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring0);
5684 + for (i = 0; i < NUM_RX_DESC; i++) {
5685 + memset(&ei_local->rx_ring0[i],0,sizeof(struct PDMA_rxdesc));
5686 + ei_local->rx_ring0[i].rxd_info2.DDONE_bit = 0;
5687 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
5688 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
5689 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
5691 + ei_local->rx_ring0[i].rxd_info2.LS0 = 1;
5693 + ei_local->rx_ring0[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx0_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
5695 + printk("\nphy_rx_ring0 = 0x%08x, rx_ring0 = 0x%p\n",ei_local->phy_rx_ring0,ei_local->rx_ring0);
5697 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5698 + /* Initial RX Ring 1*/
5699 +#ifdef CONFIG_32B_DESC
5700 + ei_local->rx_ring1 = kmalloc(NUM_RX_DESC * sizeof(struct PDMA_rxdesc), GFP_KERNEL);
5701 + ei_local->phy_rx_ring1 = virt_to_phys(ei_local->rx_ring1);
5703 + ei_local->rx_ring1 = pci_alloc_consistent(NULL, NUM_RX_DESC * sizeof(struct PDMA_rxdesc), &ei_local->phy_rx_ring1);
5705 + for (i = 0; i < NUM_RX_DESC; i++) {
5706 + memset(&ei_local->rx_ring1[i],0,sizeof(struct PDMA_rxdesc));
5707 + ei_local->rx_ring1[i].rxd_info2.DDONE_bit = 0;
5708 +#if defined (CONFIG_RAETH_SCATTER_GATHER_RX_DMA)
5709 + ei_local->rx_ring0[i].rxd_info2.LS0 = 0;
5710 + ei_local->rx_ring0[i].rxd_info2.PLEN0 = MAX_RX_LENGTH;
5712 + ei_local->rx_ring1[i].rxd_info2.LS0 = 1;
5714 + ei_local->rx_ring1[i].rxd_info1.PDP0 = dma_map_single(NULL, ei_local->netrx1_skbuf[i]->data, MAX_RX_LENGTH, PCI_DMA_FROMDEVICE);
5716 + printk("\nphy_rx_ring1 = 0x%08x, rx_ring1 = 0x%p\n",ei_local->phy_rx_ring1,ei_local->rx_ring1);
5719 + regVal = sysRegRead(QDMA_GLO_CFG);
5720 + regVal &= 0x000000FF;
5721 + sysRegWrite(QDMA_GLO_CFG, regVal);
5722 + regVal=sysRegRead(QDMA_GLO_CFG);
5724 + /* Tell the adapter where the TX/RX rings are located. */
5726 + sysRegWrite(QRX_BASE_PTR_0, phys_to_bus((u32) ei_local->phy_rx_ring0));
5727 + sysRegWrite(QRX_MAX_CNT_0, cpu_to_le32((u32) NUM_RX_DESC));
5728 + sysRegWrite(QRX_CRX_IDX_0, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5729 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5730 + rx_calc_idx0 = rx_dma_owner_idx0 = sysRegRead(QRX_CRX_IDX_0);
5732 + sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX0);
5733 +#if defined (CONFIG_RAETH_MULTIPLE_RX_RING)
5734 + sysRegWrite(QRX_BASE_PTR_1, phys_to_bus((u32) ei_local->phy_rx_ring1));
5735 + sysRegWrite(QRX_MAX_CNT_1, cpu_to_le32((u32) NUM_RX_DESC));
5736 + sysRegWrite(QRX_CRX_IDX_1, cpu_to_le32((u32) (NUM_RX_DESC - 1)));
5737 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5738 + rx_calc_idx1 = rx_dma_owner_idx1 = sysRegRead(QRX_CRX_IDX_1);
5740 + sysRegWrite(QDMA_RST_CFG, PST_DRX_IDX1);
5743 + set_fe_dma_glo_cfg();
5748 +inline int rt2880_eth_send(struct net_device* dev, struct sk_buff *skb, int gmac_no)
5750 + unsigned int length=skb->len;
5751 + END_DEVICE* ei_local = netdev_priv(dev);
5753 + struct QDMA_txdesc *cpu_ptr;
5755 + struct QDMA_txdesc *dma_ptr __maybe_unused;
5756 + struct QDMA_txdesc *free_txd;
5758 +#if defined (CONFIG_RAETH_TSO)
5759 + struct iphdr *iph = NULL;
5760 + struct QDMA_txdesc *init_cpu_ptr;
5761 + struct tcphdr *th = NULL;
5762 + struct skb_frag_struct *frag;
5763 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
5766 +#endif // CONFIG_RAETH_TSO //
5768 +#if defined (CONFIG_RAETH_TSOV6)
5769 + struct ipv6hdr *ip6h = NULL;
5772 +#ifdef CONFIG_PSEUDO_SUPPORT
5773 + PSEUDO_ADAPTER *pAd;
5775 + cpu_ptr = PHYS_TO_VIRT(ei_local->tx_cpu_ptr);
5776 + dma_ptr = PHYS_TO_VIRT(ei_local->tx_dma_ptr);
5777 + ctx_offset = GET_TXD_OFFSET(&cpu_ptr);
5778 + ei_local->skb_free[ctx_offset] = skb;
5779 +#if defined (CONFIG_RAETH_TSO)
5780 + init_cpu_ptr = cpu_ptr;
5781 + init_txd_idx = ctx_offset;
5784 +#if !defined (CONFIG_RAETH_TSO)
5787 + cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
5788 + cpu_ptr->txd_info3.SDL = skb->len;
5790 + if (gmac_no == 1) {
5791 + cpu_ptr->txd_info4.FPORT = 1;
5793 + cpu_ptr->txd_info4.FPORT = 2;
5797 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
5799 + iph = (struct iphdr *)skb_network_header(skb);
5800 + if (iph->tos == 0xe0)
5801 + cpu_ptr->txd_info3.QID = 3;
5802 + else if (iph->tos == 0xa0)
5803 + cpu_ptr->txd_info3.QID = 2;
5804 + else if (iph->tos == 0x20)
5805 + cpu_ptr->txd_info3.QID = 1;
5807 + cpu_ptr->txd_info3.QID = 0;
5810 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
5811 + if (skb->ip_summed == CHECKSUM_PARTIAL){
5812 + cpu_ptr->txd_info4.TUI_CO = 7;
5814 + cpu_ptr->txd_info4.TUI_CO = 0;
5818 +#ifdef CONFIG_RAETH_HW_VLAN_TX
5819 + if(vlan_tx_tag_present(skb)) {
5820 + cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
5822 + cpu_ptr->txd_info4.VLAN_TAG = 0;
5826 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
5827 + if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
5828 + if(ra_sw_nat_hook_rx!= NULL){
5829 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
5830 + FOE_MAGIC_TAG(skb) = 0;
5835 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
5836 + cpu_ptr->txd_info4.UDF = 0x2F;
5839 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5840 + cpu_ptr->txd_info3.SWC_bit = 1;
5842 + //3. get NULL TXD and decrease free_tx_num by 1.
5843 + ctx_offset = get_free_txd(&free_txd);
5844 + if(ctx_offset == NUM_TX_DESC) {
5845 + printk("get_free_txd fail\n"); // this should not happen. free_txd_num is 2 at least.
5849 + //4. hook new TXD in the end of queue
5850 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
5853 + //5. move CPU_PTR to new TXD
5854 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5855 + cpu_ptr->txd_info3.OWN_bit = 0;
5856 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
5859 + printk("----------------------------------------------\n");
5860 + printk("txd_info1:%08X \n",*(int *)&cpu_ptr->txd_info1);
5861 + printk("txd_info2:%08X \n",*(int *)&cpu_ptr->txd_info2);
5862 + printk("txd_info3:%08X \n",*(int *)&cpu_ptr->txd_info3);
5863 + printk("txd_info4:%08X \n",*(int *)&cpu_ptr->txd_info4);
5866 +#else //#if !defined (CONFIG_RAETH_TSO)
5867 + cpu_ptr->txd_info1.SDP = VIRT_TO_PHYS(skb->data);
5868 + cpu_ptr->txd_info3.SDL = (length - skb->data_len);
5869 + cpu_ptr->txd_info3.LS_bit = nr_frags ? 0:1;
5870 + if (gmac_no == 1) {
5871 + cpu_ptr->txd_info4.FPORT = 1;
5873 + cpu_ptr->txd_info4.FPORT = 2;
5876 + cpu_ptr->txd_info4.TSO = 0;
5877 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
5878 +#if defined (CONFIG_RAETH_CHECKSUM_OFFLOAD) && ! defined(CONFIG_RALINK_RT5350) && !defined (CONFIG_RALINK_MT7628)
5879 + if (skb->ip_summed == CHECKSUM_PARTIAL){
5880 + cpu_ptr->txd_info4.TUI_CO = 7;
5882 + cpu_ptr->txd_info4.TUI_CO = 0;
5886 +#ifdef CONFIG_RAETH_HW_VLAN_TX
5887 + if(vlan_tx_tag_present(skb)) {
5888 + cpu_ptr->txd_info4.VLAN_TAG = 0x10000 | vlan_tx_tag_get(skb);
5890 + cpu_ptr->txd_info4.VLAN_TAG = 0;
5894 +#if defined (CONFIG_RA_HW_NAT) || defined (CONFIG_RA_HW_NAT_MODULE)
5895 + if(FOE_MAGIC_TAG(skb) == FOE_MAGIC_PPE) {
5896 + if(ra_sw_nat_hook_rx!= NULL){
5897 + cpu_ptr->txd_info4.FPORT = 4; /* PPE */
5898 + FOE_MAGIC_TAG(skb) = 0;
5903 + cpu_ptr->txd_info3.SWC_bit = 1;
5905 + ctx_offset = get_free_txd(&free_txd);
5906 + if(ctx_offset == NUM_TX_DESC) {
5907 + printk("get_free_txd fail\n");
5910 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
5911 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5913 + if(nr_frags > 0) {
5914 + for(i=0;i<nr_frags;i++) {
5915 + frag = &skb_shinfo(skb)->frags[i];
5916 + cpu_ptr = free_txd;
5917 + cpu_ptr->txd_info3.QID = M2Q_table[skb->mark];
5918 + cpu_ptr->txd_info1.SDP = pci_map_page(NULL, frag->page, frag->page_offset, frag->size, PCI_DMA_TODEVICE);
5919 + cpu_ptr->txd_info3.SDL = frag->size;
5920 + cpu_ptr->txd_info3.LS_bit = (i==nr_frags-1)?1:0;
5921 + cpu_ptr->txd_info3.OWN_bit = 0;
5922 + cpu_ptr->txd_info3.SWC_bit = 1;
5923 + ei_local->skb_free[ctx_offset] = (i==nr_frags-1)?skb:(struct sk_buff *)0xFFFFFFFF; //MAGIC ID
5925 + ctx_offset = get_free_txd(&free_txd);
5926 + cpu_ptr->txd_info2.NDP = VIRT_TO_PHYS(free_txd);
5927 + ei_local->tx_cpu_ptr = VIRT_TO_PHYS(free_txd);
5929 + ei_local->skb_free[init_txd_idx]= (struct sk_buff *)0xFFFFFFFF; //MAGIC ID
5932 + if(skb_shinfo(skb)->gso_segs > 1) {
5934 +// TsoLenUpdate(skb->len);
5936 + /* TCP over IPv4 */
5937 + iph = (struct iphdr *)skb_network_header(skb);
5938 +#if defined (CONFIG_RAETH_TSOV6)
5939 + /* TCP over IPv6 */
5940 + ip6h = (struct ipv6hdr *)skb_network_header(skb);
5942 + if((iph->version == 4) && (iph->protocol == IPPROTO_TCP)) {
5943 + th = (struct tcphdr *)skb_transport_header(skb);
5945 + init_cpu_ptr->txd_info4.TSO = 1;
5947 + th->check = htons(skb_shinfo(skb)->gso_size);
5948 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
5951 +#if defined (CONFIG_RAETH_TSOV6)
5952 + /* TCP over IPv6 */
5953 + //ip6h = (struct ipv6hdr *)skb_network_header(skb);
5954 + else if ((ip6h->version == 6) && (ip6h->nexthdr == NEXTHDR_TCP)) {
5955 + th = (struct tcphdr *)skb_transport_header(skb);
5956 +#ifdef CONFIG_RAETH_RW_PDMAPTR_FROM_VAR
5957 + init_cpu_ptr->txd_info4.TSO = 1;
5959 + init_cpu_ptr->txd_info4.TSO = 1;
5961 + th->check = htons(skb_shinfo(skb)->gso_size);
5962 + dma_cache_sync(NULL, th, sizeof(struct tcphdr), DMA_TO_DEVICE);
5968 +// dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
5970 + init_cpu_ptr->txd_info3.OWN_bit = 0;
5971 +#endif // CONFIG_RAETH_TSO //
5973 + sysRegWrite(QTX_CTX_PTR, ei_local->tx_cpu_ptr);
5975 +#ifdef CONFIG_PSEUDO_SUPPORT
5976 + if (gmac_no == 2) {
5977 + if (ei_local->PseudoDev != NULL) {
5978 + pAd = netdev_priv(ei_local->PseudoDev);
5979 + pAd->stat.tx_packets++;
5980 + pAd->stat.tx_bytes += length;
5986 + ei_local->stat.tx_packets++;
5987 + ei_local->stat.tx_bytes += skb->len;
5992 +int ei_start_xmit(struct sk_buff* skb, struct net_device *dev, int gmac_no)
5994 + END_DEVICE *ei_local = netdev_priv(dev);
5995 + unsigned long flags;
5996 + unsigned int num_of_txd;
5997 +#if defined (CONFIG_RAETH_TSO)
5998 + unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6000 +#ifdef CONFIG_PSEUDO_SUPPORT
6001 + PSEUDO_ADAPTER *pAd;
6004 +#if !defined(CONFIG_RA_NAT_NONE)
6005 + if(ra_sw_nat_hook_tx!= NULL)
6007 + spin_lock_irqsave(&ei_local->page_lock, flags);
6008 + if(ra_sw_nat_hook_tx(skb, gmac_no)==1){
6009 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
6012 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
6020 + dev->trans_start = jiffies; /* save the timestamp */
6021 + spin_lock_irqsave(&ei_local->page_lock, flags);
6022 + dma_cache_sync(NULL, skb->data, skb->len, DMA_TO_DEVICE);
6025 +//check free_txd_num before calling rt288_eth_send()
6027 +#if defined (CONFIG_RAETH_TSO)
6028 + num_of_txd = (nr_frags==0) ? 1 : (nr_frags + 1);
6033 +#if defined(CONFIG_RALINK_MT7621)
6034 + if(sysRegRead(0xbe00000c)==0x00030101) {
6035 + ei_xmit_housekeeping(0);
6040 + if ((ei_local->free_txd_num > num_of_txd + 1) && (ei_local->free_txd_num != NUM_TX_DESC))
6042 + rt2880_eth_send(dev, skb, gmac_no); // need to modify rt2880_eth_send() for QDMA
6043 + if (ei_local->free_txd_num < 3)
6045 +#if defined (CONFIG_RAETH_STOP_RX_WHEN_TX_FULL)
6046 + netif_stop_queue(dev);
6047 +#ifdef CONFIG_PSEUDO_SUPPORT
6048 + netif_stop_queue(ei_local->PseudoDev);
6054 +#ifdef CONFIG_PSEUDO_SUPPORT
6057 + if (ei_local->PseudoDev != NULL)
6059 + pAd = netdev_priv(ei_local->PseudoDev);
6060 + pAd->stat.tx_dropped++;
6064 + ei_local->stat.tx_dropped++;
6066 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
6069 + spin_unlock_irqrestore(&ei_local->page_lock, flags);
6073 +void ei_xmit_housekeeping(unsigned long unused)
6075 + struct net_device *dev = dev_raether;
6076 + END_DEVICE *ei_local = netdev_priv(dev);
6077 +#ifndef CONFIG_RAETH_NAPI
6078 + unsigned long reg_int_mask=0;
6080 + struct QDMA_txdesc *dma_ptr = NULL;
6081 + struct QDMA_txdesc *cpu_ptr = NULL;
6082 + struct QDMA_txdesc *tmp_ptr = NULL;
6083 + unsigned int htx_offset = 0;
6085 + dma_ptr = PHYS_TO_VIRT(sysRegRead(QTX_DRX_PTR));
6086 + cpu_ptr = PHYS_TO_VIRT(sysRegRead(QTX_CRX_PTR));
6087 + if(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
6088 + while(cpu_ptr != dma_ptr && (cpu_ptr->txd_info3.OWN_bit == 1)) {
6090 + //1. keep cpu next TXD
6091 + tmp_ptr = PHYS_TO_VIRT(cpu_ptr->txd_info2.NDP);
6092 + htx_offset = GET_TXD_OFFSET(&tmp_ptr);
6093 + //2. free skb meomry
6094 +#if defined (CONFIG_RAETH_TSO)
6095 + if(ei_local->skb_free[htx_offset]!=(struct sk_buff *)0xFFFFFFFF) {
6096 + dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
6099 + dev_kfree_skb_any(ei_local->skb_free[htx_offset]);
6103 + htx_offset = GET_TXD_OFFSET(&cpu_ptr);
6104 + put_free_txd(htx_offset);
6106 + netif_wake_queue(dev);
6107 +#ifdef CONFIG_PSEUDO_SUPPORT
6108 + netif_wake_queue(ei_local->PseudoDev);
6112 + //4. update cpu_ptr to next ptr
6113 + cpu_ptr = tmp_ptr;
6116 + sysRegWrite(QTX_CRX_PTR, VIRT_TO_PHYS(cpu_ptr));
6117 +#ifndef CONFIG_RAETH_NAPI
6118 + reg_int_mask=sysRegRead(QFE_INT_ENABLE);
6119 +#if defined (DELAY_INT)
6120 + sysRegWrite(FE_INT_ENABLE, reg_int_mask| RLS_DLY_INT);
6123 + sysRegWrite(FE_INT_ENABLE, reg_int_mask | RLS_DONE_INT);
6125 +#endif //CONFIG_RAETH_NAPI//
6128 +EXPORT_SYMBOL(ei_start_xmit);
6129 +EXPORT_SYMBOL(ei_xmit_housekeeping);
6130 +EXPORT_SYMBOL(fe_dma_init);
6131 +EXPORT_SYMBOL(rt2880_eth_send);
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