target/linux/ramips/patches-3.14/0035-NET-MIPS-add-ralink-SoC-ethernet-driver.patch

   1 From c55d6cf3e2c593bf7d228c6532ec9bd8da82e09d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 22 Apr 2013 23:20:03 +0200
   4 Subject: [PATCH 35/57] NET: MIPS: add ralink SoC ethernet driver
   5
   6 Add support for Ralink FE and ESW.
   7
   8 Signed-off-by: John Crispin <blogic@openwrt.org>
   9 ---
  10  .../include/asm/mach-ralink/rt305x_esw_platform.h  |   27 +
  11  arch/mips/ralink/rt305x.c                          |    1 +
  12  drivers/net/ethernet/Kconfig                       |    1 +
  13  drivers/net/ethernet/Makefile                      |    1 +
  14  drivers/net/ethernet/ralink/Kconfig                |   32 +
  15  drivers/net/ethernet/ralink/Makefile               |   18 +
  16  drivers/net/ethernet/ralink/esw_rt3052.c           | 1463 ++++++++++++++++++++
  17  drivers/net/ethernet/ralink/esw_rt3052.h           |   32 +
  18  drivers/net/ethernet/ralink/gsw_mt7620a.c          |  566 ++++++++
  19  drivers/net/ethernet/ralink/gsw_mt7620a.h          |   30 +
  20  drivers/net/ethernet/ralink/mdio.c                 |  244 ++++
  21  drivers/net/ethernet/ralink/mdio.h                 |   29 +
  22  drivers/net/ethernet/ralink/mdio_rt2880.c          |  232 ++++
  23  drivers/net/ethernet/ralink/mdio_rt2880.h          |   26 +
  24  drivers/net/ethernet/ralink/mt7530.c               |  579 ++++++++
  25  drivers/net/ethernet/ralink/mt7530.h               |   20 +
  26  drivers/net/ethernet/ralink/ralink_soc_eth.c       |  844 +++++++++++
  27  drivers/net/ethernet/ralink/ralink_soc_eth.h       |  384 +++++
  28  drivers/net/ethernet/ralink/soc_mt7620.c           |  172 +++
  29  drivers/net/ethernet/ralink/soc_rt2880.c           |   52 +
  30  drivers/net/ethernet/ralink/soc_rt305x.c           |  113 ++
  31  drivers/net/ethernet/ralink/soc_rt3883.c           |   60 +
  32  22 files changed, 4926 insertions(+)
  33  create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  34  create mode 100644 drivers/net/ethernet/ralink/Kconfig
  35  create mode 100644 drivers/net/ethernet/ralink/Makefile
  36  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
  37  create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
  38  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
  39  create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
  40  create mode 100644 drivers/net/ethernet/ralink/mdio.c
  41  create mode 100644 drivers/net/ethernet/ralink/mdio.h
  42  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
  43  create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
  44  create mode 100644 drivers/net/ethernet/ralink/mt7530.c
  45  create mode 100644 drivers/net/ethernet/ralink/mt7530.h
  46  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
  47  create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
  48  create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
  49  create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
  50  create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
  51  create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
  52
  53 Index: linux-3.14.18/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
  54 ===================================================================
  55 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  56 +++ linux-3.14.18/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h       2014-10-29 20:25:55.429357372 +0100
  57 @@ -0,0 +1,27 @@
  58 +/*
  59 + *  Ralink RT305x SoC platform device registration
  60 + *
  61 + *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
  62 + *
  63 + *  This program is free software; you can redistribute it and/or modify it
  64 + *  under the terms of the GNU General Public License version 2 as published
  65 + *  by the Free Software Foundation.
  66 + */
  67 +
  68 +#ifndef _RT305X_ESW_PLATFORM_H
  69 +#define _RT305X_ESW_PLATFORM_H
  70 +
  71 +enum {
  72 +       RT305X_ESW_VLAN_CONFIG_NONE = 0,
  73 +       RT305X_ESW_VLAN_CONFIG_LLLLW,
  74 +       RT305X_ESW_VLAN_CONFIG_WLLLL,
  75 +};
  76 +
  77 +struct rt305x_esw_platform_data
  78 +{
  79 +       u8 vlan_config;
  80 +       u32 reg_initval_fct2;
  81 +       u32 reg_initval_fpa2;
  82 +};
  83 +
  84 +#endif /* _RT305X_ESW_PLATFORM_H */
  85 Index: linux-3.14.18/arch/mips/ralink/rt305x.c
  86 ===================================================================
  87 --- linux-3.14.18.orig/arch/mips/ralink/rt305x.c        2014-10-29 20:25:55.377355456 +0100
  88 +++ linux-3.14.18/arch/mips/ralink/rt305x.c     2014-10-29 20:25:55.433357519 +0100
  89 @@ -199,6 +199,7 @@
  90         }
  91
  92         ralink_clk_add("cpu", cpu_rate);
  93 +       ralink_clk_add("sys", sys_rate);
  94         ralink_clk_add("10000b00.spi", sys_rate);
  95         ralink_clk_add("10000100.timer", wdt_rate);
  96         ralink_clk_add("10000120.watchdog", wdt_rate);
  97 Index: linux-3.14.18/drivers/net/ethernet/Kconfig
  98 ===================================================================
  99 --- linux-3.14.18.orig/drivers/net/ethernet/Kconfig     2014-09-06 01:34:59.000000000 +0200
 100 +++ linux-3.14.18/drivers/net/ethernet/Kconfig  2014-10-30 09:43:22.196245753 +0100
 101 @@ -134,6 +134,7 @@
 102  source "drivers/net/ethernet/packetengines/Kconfig"
 103  source "drivers/net/ethernet/pasemi/Kconfig"
 104  source "drivers/net/ethernet/qlogic/Kconfig"
 105 +source "drivers/net/ethernet/ralink/Kconfig"
 106  source "drivers/net/ethernet/realtek/Kconfig"
 107  source "drivers/net/ethernet/renesas/Kconfig"
 108  source "drivers/net/ethernet/rdc/Kconfig"
 109 Index: linux-3.14.18/drivers/net/ethernet/Makefile
 110 ===================================================================
 111 --- linux-3.14.18.orig/drivers/net/ethernet/Makefile    2014-09-06 01:34:59.000000000 +0200
 112 +++ linux-3.14.18/drivers/net/ethernet/Makefile 2014-10-30 09:43:22.196245753 +0100
 113 @@ -56,6 +56,7 @@
 114  obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
 115  obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
 116  obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
 117 +obj-$(CONFIG_NET_RALINK) += ralink/
 118  obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
 119  obj-$(CONFIG_SH_ETH) += renesas/
 120  obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
 121 Index: linux-3.14.18/drivers/net/ethernet/ralink/Kconfig
 122 ===================================================================
 123 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 124 +++ linux-3.14.18/drivers/net/ethernet/ralink/Kconfig   2014-10-29 20:25:55.433357519 +0100
 125 @@ -0,0 +1,31 @@
 126 +config NET_RALINK
 127 +       tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
 128 +       depends on RALINK
 129 +       help
 130 +         This driver supports the ethernet mac inside the ralink wisocs
 131 +
 132 +if NET_RALINK
 133 +
 134 +config NET_RALINK_MDIO
 135 +       def_bool NET_RALINK
 136 +       depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
 137 +       select PHYLIB
 138 +
 139 +config NET_RALINK_MDIO_RT2880
 140 +       def_bool NET_RALINK
 141 +       depends on (SOC_RT288X || SOC_RT3883)
 142 +       select NET_RALINK_MDIO
 143 +
 144 +config NET_RALINK_ESW_RT3052
 145 +       def_bool NET_RALINK
 146 +       depends on SOC_RT305X
 147 +       select PHYLIB
 148 +       select SWCONFIG
 149 +
 150 +config NET_RALINK_GSW_MT7620
 151 +       def_bool NET_RALINK
 152 +       depends on SOC_MT7620
 153 +       select NET_RALINK_MDIO
 154 +       select PHYLIB
 155 +       select SWCONFIG
 156 +endif
 157 Index: linux-3.14.18/drivers/net/ethernet/ralink/Makefile
 158 ===================================================================
 159 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 160 +++ linux-3.14.18/drivers/net/ethernet/ralink/Makefile  2014-10-29 20:25:55.433357519 +0100
 161 @@ -0,0 +1,18 @@
 162 +#
 163 +# Makefile for the Ralink SoCs built-in ethernet macs
 164 +#
 165 +
 166 +ralink-eth-y                                   += ralink_soc_eth.o ralink_ethtool.o
 167 +
 168 +ralink-eth-$(CONFIG_NET_RALINK_MDIO)           += mdio.o
 169 +ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880)    += mdio_rt2880.o
 170 +
 171 +ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052)     += esw_rt3052.o
 172 +ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620)     += gsw_mt7620a.o mt7530.o
 173 +
 174 +ralink-eth-$(CONFIG_SOC_RT288X)                        += soc_rt2880.o
 175 +ralink-eth-$(CONFIG_SOC_RT305X)                        += soc_rt305x.o
 176 +ralink-eth-$(CONFIG_SOC_RT3883)                        += soc_rt3883.o
 177 +ralink-eth-$(CONFIG_SOC_MT7620)                        += soc_mt7620.o
 178 +
 179 +obj-$(CONFIG_NET_RALINK)                       += ralink-eth.o
 180 Index: linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.c
 181 ===================================================================
 182 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
 183 +++ linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.c      2014-10-29 20:25:55.433357519 +0100
 184 @@ -0,0 +1,1463 @@
 185 +/*
 186 + *   This program is free software; you can redistribute it and/or modify
 187 + *   it under the terms of the GNU General Public License as published by
 188 + *   the Free Software Foundation; version 2 of the License
 189 + *
 190 + *   This program is distributed in the hope that it will be useful,
 191 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 192 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 193 + *   GNU General Public License for more details.
 194 + *
 195 + *   You should have received a copy of the GNU General Public License
 196 + *   along with this program; if not, write to the Free Software
 197 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
 198 + *
 199 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
 200 + */
 201 +
 202 +#include <linux/module.h>
 203 +#include <linux/kernel.h>
 204 +#include <linux/types.h>
 205 +#include <linux/dma-mapping.h>
 206 +#include <linux/init.h>
 207 +#include <linux/skbuff.h>
 208 +#include <linux/etherdevice.h>
 209 +#include <linux/ethtool.h>
 210 +#include <linux/platform_device.h>
 211 +#include <linux/of_device.h>
 212 +#include <linux/clk.h>
 213 +#include <linux/of_net.h>
 214 +#include <linux/of_mdio.h>
 215 +
 216 +#include <asm/mach-ralink/ralink_regs.h>
 217 +
 218 +#include "ralink_soc_eth.h"
 219 +
 220 +#include <linux/ioport.h>
 221 +#include <linux/switch.h>
 222 +#include <linux/mii.h>
 223 +
 224 +#include <ralink_regs.h>
 225 +#include <asm/mach-ralink/rt305x.h>
 226 +#include <asm/mach-ralink/rt305x_esw_platform.h>
 227 +
 228 +/*
 229 + * HW limitations for this switch:
 230 + * - No large frame support (PKT_MAX_LEN at most 1536)
 231 + * - Can't have untagged vlan and tagged vlan on one port at the same time,
 232 + *   though this might be possible using the undocumented PPE.
 233 + */
 234 +
 235 +#define RT305X_ESW_REG_ISR             0x00
 236 +#define RT305X_ESW_REG_IMR             0x04
 237 +#define RT305X_ESW_REG_FCT0            0x08
 238 +#define RT305X_ESW_REG_PFC1            0x14
 239 +#define RT305X_ESW_REG_ATS             0x24
 240 +#define RT305X_ESW_REG_ATS0            0x28
 241 +#define RT305X_ESW_REG_ATS1            0x2c
 242 +#define RT305X_ESW_REG_ATS2            0x30
 243 +#define RT305X_ESW_REG_PVIDC(_n)       (0x40 + 4 * (_n))
 244 +#define RT305X_ESW_REG_VLANI(_n)       (0x50 + 4 * (_n))
 245 +#define RT305X_ESW_REG_VMSC(_n)                (0x70 + 4 * (_n))
 246 +#define RT305X_ESW_REG_POA             0x80
 247 +#define RT305X_ESW_REG_FPA             0x84
 248 +#define RT305X_ESW_REG_SOCPC           0x8c
 249 +#define RT305X_ESW_REG_POC0            0x90
 250 +#define RT305X_ESW_REG_POC1            0x94
 251 +#define RT305X_ESW_REG_POC2            0x98
 252 +#define RT305X_ESW_REG_SGC             0x9c
 253 +#define RT305X_ESW_REG_STRT            0xa0
 254 +#define RT305X_ESW_REG_PCR0            0xc0
 255 +#define RT305X_ESW_REG_PCR1            0xc4
 256 +#define RT305X_ESW_REG_FPA2            0xc8
 257 +#define RT305X_ESW_REG_FCT2            0xcc
 258 +#define RT305X_ESW_REG_SGC2            0xe4
 259 +#define RT305X_ESW_REG_P0LED           0xa4
 260 +#define RT305X_ESW_REG_P1LED           0xa8
 261 +#define RT305X_ESW_REG_P2LED           0xac
 262 +#define RT305X_ESW_REG_P3LED           0xb0
 263 +#define RT305X_ESW_REG_P4LED           0xb4
 264 +#define RT305X_ESW_REG_PXPC(_x)                (0xe8 + (4 * _x))
 265 +#define RT305X_ESW_REG_P1PC            0xec
 266 +#define RT305X_ESW_REG_P2PC            0xf0
 267 +#define RT305X_ESW_REG_P3PC            0xf4
 268 +#define RT305X_ESW_REG_P4PC            0xf8
 269 +#define RT305X_ESW_REG_P5PC            0xfc
 270 +
 271 +#define RT305X_ESW_LED_LINK            0
 272 +#define RT305X_ESW_LED_100M            1
 273 +#define RT305X_ESW_LED_DUPLEX          2
 274 +#define RT305X_ESW_LED_ACTIVITY                3
 275 +#define RT305X_ESW_LED_COLLISION       4
 276 +#define RT305X_ESW_LED_LINKACT         5
 277 +#define RT305X_ESW_LED_DUPLCOLL                6
 278 +#define RT305X_ESW_LED_10MACT          7
 279 +#define RT305X_ESW_LED_100MACT         8
 280 +/* Additional led states not in datasheet: */
 281 +#define RT305X_ESW_LED_BLINK           10
 282 +#define RT305X_ESW_LED_ON              12
 283 +
 284 +#define RT305X_ESW_LINK_S              25
 285 +#define RT305X_ESW_DUPLEX_S            9
 286 +#define RT305X_ESW_SPD_S               0
 287 +
 288 +#define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
 289 +#define RT305X_ESW_PCR0_WT_PHY_CMD     BIT(13)
 290 +#define RT305X_ESW_PCR0_CPU_PHY_REG_S  8
 291 +
 292 +#define RT305X_ESW_PCR1_WT_DONE                BIT(0)
 293 +
 294 +#define RT305X_ESW_ATS_TIMEOUT         (5 * HZ)
 295 +#define RT305X_ESW_PHY_TIMEOUT         (5 * HZ)
 296 +
 297 +#define RT305X_ESW_PVIDC_PVID_M                0xfff
 298 +#define RT305X_ESW_PVIDC_PVID_S                12
 299 +
 300 +#define RT305X_ESW_VLANI_VID_M         0xfff
 301 +#define RT305X_ESW_VLANI_VID_S         12
 302 +
 303 +#define RT305X_ESW_VMSC_MSC_M          0xff
 304 +#define RT305X_ESW_VMSC_MSC_S          8
 305 +
 306 +#define RT305X_ESW_SOCPC_DISUN2CPU_S   0
 307 +#define RT305X_ESW_SOCPC_DISMC2CPU_S   8
 308 +#define RT305X_ESW_SOCPC_DISBC2CPU_S   16
 309 +#define RT305X_ESW_SOCPC_CRC_PADDING   BIT(25)
 310 +
 311 +#define RT305X_ESW_POC0_EN_BP_S                0
 312 +#define RT305X_ESW_POC0_EN_FC_S                8
 313 +#define RT305X_ESW_POC0_DIS_RMC2CPU_S  16
 314 +#define RT305X_ESW_POC0_DIS_PORT_M     0x7f
 315 +#define RT305X_ESW_POC0_DIS_PORT_S     23
 316 +
 317 +#define RT305X_ESW_POC2_UNTAG_EN_M     0xff
 318 +#define RT305X_ESW_POC2_UNTAG_EN_S     0
 319 +#define RT305X_ESW_POC2_ENAGING_S      8
 320 +#define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
 321 +
 322 +#define RT305X_ESW_SGC2_DOUBLE_TAG_M   0x7f
 323 +#define RT305X_ESW_SGC2_DOUBLE_TAG_S   0
 324 +#define RT305X_ESW_SGC2_LAN_PMAP_M     0x3f
 325 +#define RT305X_ESW_SGC2_LAN_PMAP_S     24
 326 +
 327 +#define RT305X_ESW_PFC1_EN_VLAN_M      0xff
 328 +#define RT305X_ESW_PFC1_EN_VLAN_S      16
 329 +#define RT305X_ESW_PFC1_EN_TOS_S       24
 330 +
 331 +#define RT305X_ESW_VLAN_NONE           0xfff
 332 +
 333 +#define RT305X_ESW_GSC_BC_STROM_MASK   0x3
 334 +#define RT305X_ESW_GSC_BC_STROM_SHIFT  4
 335 +
 336 +#define RT305X_ESW_GSC_LED_FREQ_MASK   0x3
 337 +#define RT305X_ESW_GSC_LED_FREQ_SHIFT  23
 338 +
 339 +#define RT305X_ESW_POA_LINK_MASK       0x1f
 340 +#define RT305X_ESW_POA_LINK_SHIFT      25
 341 +
 342 +#define RT305X_ESW_PORT_ST_CHG         BIT(26)
 343 +#define RT305X_ESW_PORT0               0
 344 +#define RT305X_ESW_PORT1               1
 345 +#define RT305X_ESW_PORT2               2
 346 +#define RT305X_ESW_PORT3               3
 347 +#define RT305X_ESW_PORT4               4
 348 +#define RT305X_ESW_PORT5               5
 349 +#define RT305X_ESW_PORT6               6
 350 +
 351 +#define RT305X_ESW_PORTS_NONE          0
 352 +
 353 +#define RT305X_ESW_PMAP_LLLLLL         0x3f
 354 +#define RT305X_ESW_PMAP_LLLLWL         0x2f
 355 +#define RT305X_ESW_PMAP_WLLLLL         0x3e
 356 +
 357 +#define RT305X_ESW_PORTS_INTERNAL                                      \
 358 +               (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |        \
 359 +                BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |        \
 360 +                BIT(RT305X_ESW_PORT4))
 361 +
 362 +#define RT305X_ESW_PORTS_NOCPU                                         \
 363 +               (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
 364 +
 365 +#define RT305X_ESW_PORTS_CPU   BIT(RT305X_ESW_PORT6)
 366 +
 367 +#define RT305X_ESW_PORTS_ALL                                           \
 368 +               (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
 369 +
 370 +#define RT305X_ESW_NUM_VLANS           16
 371 +#define RT305X_ESW_NUM_VIDS            4096
 372 +#define RT305X_ESW_NUM_PORTS           7
 373 +#define RT305X_ESW_NUM_LANWAN          6
 374 +#define RT305X_ESW_NUM_LEDS            5
 375 +
 376 +#define RT5350_ESW_REG_PXTPC(_x)       (0x150 + (4 * _x))
 377 +#define RT5350_EWS_REG_LED_POLARITY    0x168
 378 +#define RT5350_RESET_EPHY              BIT(24)
 379 +#define SYSC_REG_RESET_CTRL            0x34
 380 +
 381 +enum {
 382 +       /* Global attributes. */
 383 +       RT305X_ESW_ATTR_ENABLE_VLAN,
 384 +       RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
 385 +       RT305X_ESW_ATTR_BC_STATUS,
 386 +       RT305X_ESW_ATTR_LED_FREQ,
 387 +       /* Port attributes. */
 388 +       RT305X_ESW_ATTR_PORT_DISABLE,
 389 +       RT305X_ESW_ATTR_PORT_DOUBLETAG,
 390 +       RT305X_ESW_ATTR_PORT_UNTAG,
 391 +       RT305X_ESW_ATTR_PORT_LED,
 392 +       RT305X_ESW_ATTR_PORT_LAN,
 393 +       RT305X_ESW_ATTR_PORT_RECV_BAD,
 394 +       RT305X_ESW_ATTR_PORT_RECV_GOOD,
 395 +       RT5350_ESW_ATTR_PORT_TR_BAD,
 396 +       RT5350_ESW_ATTR_PORT_TR_GOOD,
 397 +};
 398 +
 399 +struct esw_port {
 400 +       bool    disable;
 401 +       bool    doubletag;
 402 +       bool    untag;
 403 +       u8      led;
 404 +       u16     pvid;
 405 +};
 406 +
 407 +struct esw_vlan {
 408 +       u8      ports;
 409 +       u16     vid;
 410 +};
 411 +
 412 +struct rt305x_esw {
 413 +       struct device           *dev;
 414 +       void __iomem            *base;
 415 +       int                     irq;
 416 +       const struct rt305x_esw_platform_data *pdata;
 417 +       /* Protects against concurrent register rmw operations. */
 418 +       spinlock_t              reg_rw_lock;
 419 +
 420 +       unsigned char           port_map;
 421 +       unsigned int            reg_initval_fct2;
 422 +       unsigned int            reg_initval_fpa2;
 423 +       unsigned int            reg_led_polarity;
 424 +
 425 +
 426 +       struct switch_dev       swdev;
 427 +       bool                    global_vlan_enable;
 428 +       bool                    alt_vlan_disable;
 429 +       int                     bc_storm_protect;
 430 +       int                     led_frequency;
 431 +       struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
 432 +       struct esw_port ports[RT305X_ESW_NUM_PORTS];
 433 +
 434 +};
 435 +
 436 +static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
 437 +{
 438 +       __raw_writel(val, esw->base + reg);
 439 +}
 440 +
 441 +static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
 442 +{
 443 +       return __raw_readl(esw->base + reg);
 444 +}
 445 +
 446 +static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 447 +                  unsigned long val)
 448 +{
 449 +       unsigned long t;
 450 +
 451 +       t = __raw_readl(esw->base + reg) & ~mask;
 452 +       __raw_writel(t | val, esw->base + reg);
 453 +}
 454 +
 455 +static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
 456 +              unsigned long val)
 457 +{
 458 +       unsigned long flags;
 459 +
 460 +       spin_lock_irqsave(&esw->reg_rw_lock, flags);
 461 +       esw_rmw_raw(esw, reg, mask, val);
 462 +       spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
 463 +}
 464 +
 465 +static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
 466 +                u32 write_data)
 467 +{
 468 +       unsigned long t_start = jiffies;
 469 +       int ret = 0;
 470 +
 471 +       while (1) {
 472 +               if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
 473 +                     RT305X_ESW_PCR1_WT_DONE))
 474 +                       break;
 475 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 476 +                       ret = 1;
 477 +                       goto out;
 478 +               }
 479 +       }
 480 +
 481 +       write_data &= 0xffff;
 482 +       esw_w32(esw,
 483 +                     (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
 484 +                     (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
 485 +                     (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
 486 +                     RT305X_ESW_REG_PCR0);
 487 +
 488 +       t_start = jiffies;
 489 +       while (1) {
 490 +               if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
 491 +                   RT305X_ESW_PCR1_WT_DONE)
 492 +                       break;
 493 +
 494 +               if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
 495 +                       ret = 1;
 496 +                       break;
 497 +               }
 498 +       }
 499 +out:
 500 +       if (ret)
 501 +               printk(KERN_ERR "ramips_eth: MDIO timeout\n");
 502 +       return ret;
 503 +}
 504 +
 505 +static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
 506 +{
 507 +       unsigned s;
 508 +       unsigned val;
 509 +
 510 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 511 +       val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
 512 +       val = (val >> s) & RT305X_ESW_VLANI_VID_M;
 513 +
 514 +       return val;
 515 +}
 516 +
 517 +static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
 518 +{
 519 +       unsigned s;
 520 +
 521 +       s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
 522 +       esw_rmw(esw,
 523 +                      RT305X_ESW_REG_VLANI(vlan / 2),
 524 +                      RT305X_ESW_VLANI_VID_M << s,
 525 +                      (vid & RT305X_ESW_VLANI_VID_M) << s);
 526 +}
 527 +
 528 +static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
 529 +{
 530 +       unsigned s, val;
 531 +
 532 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 533 +       val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
 534 +       return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
 535 +}
 536 +
 537 +static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
 538 +{
 539 +       unsigned s;
 540 +
 541 +       s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
 542 +       esw_rmw(esw,
 543 +                      RT305X_ESW_REG_PVIDC(port / 2),
 544 +                      RT305X_ESW_PVIDC_PVID_M << s,
 545 +                      (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
 546 +}
 547 +
 548 +static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
 549 +{
 550 +       unsigned s, val;
 551 +
 552 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 553 +       val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
 554 +       val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
 555 +
 556 +       return val;
 557 +}
 558 +
 559 +static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
 560 +{
 561 +       unsigned s;
 562 +
 563 +       s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
 564 +       esw_rmw(esw,
 565 +                      RT305X_ESW_REG_VMSC(vlan / 4),
 566 +                      RT305X_ESW_VMSC_MSC_M << s,
 567 +                      (msc & RT305X_ESW_VMSC_MSC_M) << s);
 568 +}
 569 +
 570 +static unsigned esw_get_port_disable(struct rt305x_esw *esw)
 571 +{
 572 +       unsigned reg;
 573 +       reg = esw_r32(esw, RT305X_ESW_REG_POC0);
 574 +       return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
 575 +              RT305X_ESW_POC0_DIS_PORT_M;
 576 +}
 577 +
 578 +static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
 579 +{
 580 +       unsigned old_mask;
 581 +       unsigned enable_mask;
 582 +       unsigned changed;
 583 +       int i;
 584 +
 585 +       old_mask = esw_get_port_disable(esw);
 586 +       changed = old_mask ^ disable_mask;
 587 +       enable_mask = old_mask & disable_mask;
 588 +
 589 +       /* enable before writing to MII */
 590 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 591 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 592 +                       RT305X_ESW_POC0_DIS_PORT_S),
 593 +                      enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 594 +
 595 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
 596 +               if (!(changed & (1 << i)))
 597 +                       continue;
 598 +               if (disable_mask & (1 << i)) {
 599 +                       /* disable */
 600 +                       rt305x_mii_write(esw, i, MII_BMCR,
 601 +                                        BMCR_PDOWN);
 602 +               } else {
 603 +                       /* enable */
 604 +                       rt305x_mii_write(esw, i, MII_BMCR,
 605 +                                        BMCR_FULLDPLX |
 606 +                                        BMCR_ANENABLE |
 607 +                                        BMCR_ANRESTART |
 608 +                                        BMCR_SPEED100);
 609 +               }
 610 +       }
 611 +
 612 +       /* disable after writing to MII */
 613 +       esw_rmw(esw, RT305X_ESW_REG_POC0,
 614 +                      (RT305X_ESW_POC0_DIS_PORT_M <<
 615 +                       RT305X_ESW_POC0_DIS_PORT_S),
 616 +                      disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
 617 +}
 618 +
 619 +static void esw_set_gsc(struct rt305x_esw *esw)
 620 +{
 621 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 622 +               RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
 623 +               esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
 624 +       esw_rmw(esw, RT305X_ESW_REG_SGC,
 625 +               RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
 626 +               esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
 627 +}
 628 +
 629 +static int esw_apply_config(struct switch_dev *dev);
 630 +
 631 +static void esw_hw_init(struct rt305x_esw *esw)
 632 +{
 633 +       int i;
 634 +       u8 port_disable = 0;
 635 +       u8 port_map = RT305X_ESW_PMAP_LLLLLL;
 636 +
 637 +       /* vodoo from original driver */
 638 +       esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
 639 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
 640 +       /* Port priority 1 for all ports, vlan enabled. */
 641 +       esw_w32(esw, 0x00005555 |
 642 +                     (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
 643 +                     RT305X_ESW_REG_PFC1);
 644 +
 645 +       /* Enable Back Pressure, and Flow Control */
 646 +       esw_w32(esw,
 647 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
 648 +                      (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
 649 +                     RT305X_ESW_REG_POC0);
 650 +
 651 +       /* Enable Aging, and VLAN TAG removal */
 652 +       esw_w32(esw,
 653 +                     ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
 654 +                      (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
 655 +                     RT305X_ESW_REG_POC2);
 656 +
 657 +       if (esw->reg_initval_fct2)
 658 +               esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 659 +       else
 660 +               esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
 661 +
 662 +       /*
 663 +        * 300s aging timer, max packet len 1536, broadcast storm prevention
 664 +        * disabled, disable collision abort, mac xor48 hash, 10 packet back
 665 +        * pressure jam, GMII disable was_transmit, back pressure disabled,
 666 +        * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
 667 +        * ports.
 668 +        */
 669 +       esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
 670 +
 671 +       /* Setup SoC Port control register */
 672 +       esw_w32(esw,
 673 +                     (RT305X_ESW_SOCPC_CRC_PADDING |
 674 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
 675 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
 676 +                      (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
 677 +                     RT305X_ESW_REG_SOCPC);
 678 +
 679 +       if (esw->reg_initval_fpa2)
 680 +               esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 681 +       else
 682 +               esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
 683 +       esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
 684 +
 685 +       /* Force Link/Activity on ports */
 686 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
 687 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
 688 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
 689 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
 690 +       esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
 691 +
 692 +       /* Copy disabled port configuration from bootloader setup */
 693 +       port_disable = esw_get_port_disable(esw);
 694 +       for (i = 0; i < 6; i++)
 695 +               esw->ports[i].disable = (port_disable & (1 << i)) != 0;
 696 +
 697 +       if (soc_is_rt3352()) {
 698 +               /* reset EPHY */
 699 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 700 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 701 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 702 +
 703 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 704 +               for (i = 0; i < 5; i++) {
 705 +                       if (esw->ports[i].disable) {
 706 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 707 +                       } else {
 708 +                               rt305x_mii_write(esw, i, MII_BMCR,
 709 +                                        BMCR_FULLDPLX |
 710 +                                        BMCR_ANENABLE |
 711 +                                        BMCR_SPEED100);
 712 +                       }
 713 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 714 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 715 +                       /* TX100/TX10 AD/DA current bias */
 716 +                       rt305x_mii_write(esw, i, 29, 0x7016);
 717 +                       /* TX100 slew rate control */
 718 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 719 +               }
 720 +
 721 +               /* select global register */
 722 +               rt305x_mii_write(esw, 0, 31, 0x0);
 723 +               /* enlarge agcsel threshold 3 and threshold 2 */
 724 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 725 +               /* enlarge agcsel threshold 5 and threshold 4 */
 726 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 727 +               /* enlarge agcsel threshold  */
 728 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 729 +               rt305x_mii_write(esw, 0,12, 0x7eaa);
 730 +               /* longer TP_IDL tail length */
 731 +               rt305x_mii_write(esw, 0, 14, 0x65);
 732 +               /* increased squelch pulse count threshold. */
 733 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 734 +               /* set TX10 signal amplitude threshold to minimum */
 735 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 736 +               /* set squelch amplitude to higher threshold */
 737 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 738 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 739 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 740 +               /* set PLL/Receive bias current are calibrated */
 741 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 742 +               /* change PLL/Receive bias current to internal(RT3350) */
 743 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 744 +               /* change PLL bias current to internal(RT3052_MP3) */
 745 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 746 +               /* select local register */
 747 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 748 +       } else if (soc_is_rt5350()) {
 749 +               /* reset EPHY */
 750 +               u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
 751 +               rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
 752 +               rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
 753 +
 754 +               /* set the led polarity */
 755 +               esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
 756 +
 757 +               /* local registers */
 758 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 759 +               for (i = 0; i < 5; i++) {
 760 +                       if (esw->ports[i].disable) {
 761 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 762 +                       } else {
 763 +                               rt305x_mii_write(esw, i, MII_BMCR,
 764 +                                        BMCR_FULLDPLX |
 765 +                                        BMCR_ANENABLE |
 766 +                                        BMCR_SPEED100);
 767 +                       }
 768 +                       /* TX10 waveform coefficient LSB=0 disable PHY */
 769 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 770 +                       /* TX100/TX10 AD/DA current bias */
 771 +                       rt305x_mii_write(esw, i, 29, 0x7015);
 772 +                       /* TX100 slew rate control */
 773 +                       rt305x_mii_write(esw, i, 30, 0x0038);
 774 +               }
 775 +
 776 +               /* global registers */
 777 +               rt305x_mii_write(esw, 0, 31, 0x0);
 778 +               /* enlarge agcsel threshold 3 and threshold 2 */
 779 +               rt305x_mii_write(esw, 0, 1, 0x4a40);
 780 +               /* enlarge agcsel threshold 5 and threshold 4 */
 781 +               rt305x_mii_write(esw, 0, 2, 0x6254);
 782 +               /* enlarge agcsel threshold 6 */
 783 +               rt305x_mii_write(esw, 0, 3, 0xa17f);
 784 +               rt305x_mii_write(esw, 0, 12, 0x7eaa);
 785 +               /* longer TP_IDL tail length */
 786 +               rt305x_mii_write(esw, 0, 14, 0x65);
 787 +               /* increased squelch pulse count threshold. */
 788 +               rt305x_mii_write(esw, 0, 16, 0x0684);
 789 +               /* set TX10 signal amplitude threshold to minimum */
 790 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 791 +               /* set squelch amplitude to higher threshold */
 792 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 793 +               /* tune TP_IDL tail and head waveform, enable power down slew rate control */
 794 +               rt305x_mii_write(esw, 0, 22, 0x253f);
 795 +               /* set PLL/Receive bias current are calibrated */
 796 +               rt305x_mii_write(esw, 0, 27, 0x2fda);
 797 +               /* change PLL/Receive bias current to internal(RT3350) */
 798 +               rt305x_mii_write(esw, 0, 28, 0xc410);
 799 +               /* change PLL bias current to internal(RT3052_MP3) */
 800 +               rt305x_mii_write(esw, 0, 29, 0x598b);
 801 +               /* select local register */
 802 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 803 +       } else {
 804 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 805 +               for (i = 0; i < 5; i++) {
 806 +                       if (esw->ports[i].disable) {
 807 +                               rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
 808 +                       } else {
 809 +                               rt305x_mii_write(esw, i, MII_BMCR,
 810 +                                        BMCR_FULLDPLX |
 811 +                                        BMCR_ANENABLE |
 812 +                                        BMCR_SPEED100);
 813 +                       }
 814 +                       /* TX10 waveform coefficient */
 815 +                       rt305x_mii_write(esw, i, 26, 0x1601);
 816 +                       /* TX100/TX10 AD/DA current bias */
 817 +                       rt305x_mii_write(esw, i, 29, 0x7058);
 818 +                       /* TX100 slew rate control */
 819 +                       rt305x_mii_write(esw, i, 30, 0x0018);
 820 +               }
 821 +
 822 +               /* PHY IOT */
 823 +               /* select global register */
 824 +               rt305x_mii_write(esw, 0, 31, 0x0);
 825 +               /* tune TP_IDL tail and head waveform */
 826 +               rt305x_mii_write(esw, 0, 22, 0x052f);
 827 +               /* set TX10 signal amplitude threshold to minimum */
 828 +               rt305x_mii_write(esw, 0, 17, 0x0fe0);
 829 +               /* set squelch amplitude to higher threshold */
 830 +               rt305x_mii_write(esw, 0, 18, 0x40ba);
 831 +               /* longer TP_IDL tail length */
 832 +               rt305x_mii_write(esw, 0, 14, 0x65);
 833 +               /* select local register */
 834 +               rt305x_mii_write(esw, 0, 31, 0x8000);
 835 +       }
 836 +
 837 +       if (esw->port_map)
 838 +               port_map = esw->port_map;
 839 +       else
 840 +               port_map = RT305X_ESW_PMAP_LLLLLL;
 841 +
 842 +       /*
 843 +        * Unused HW feature, but still nice to be consistent here...
 844 +        * This is also exported to userspace ('lan' attribute) so it's
 845 +        * conveniently usable to decide which ports go into the wan vlan by
 846 +        * default.
 847 +        */
 848 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 849 +                      RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
 850 +                      port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
 851 +
 852 +       /* make the switch leds blink */
 853 +       for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
 854 +               esw->ports[i].led = 0x05;
 855 +
 856 +       /* Apply the empty config. */
 857 +       esw_apply_config(&esw->swdev);
 858 +
 859 +       /* Only unmask the port change interrupt */
 860 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
 861 +}
 862 +
 863 +static irqreturn_t esw_interrupt(int irq, void *_esw)
 864 +{
 865 +       struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
 866 +       u32 status;
 867 +
 868 +       status = esw_r32(esw, RT305X_ESW_REG_ISR);
 869 +       if (status & RT305X_ESW_PORT_ST_CHG) {
 870 +               u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
 871 +               link >>= RT305X_ESW_POA_LINK_SHIFT;
 872 +               link &= RT305X_ESW_POA_LINK_MASK;
 873 +               dev_info(esw->dev, "link changed 0x%02X\n", link);
 874 +       }
 875 +       esw_w32(esw, status, RT305X_ESW_REG_ISR);
 876 +
 877 +       return IRQ_HANDLED;
 878 +}
 879 +
 880 +static int esw_apply_config(struct switch_dev *dev)
 881 +{
 882 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 883 +       int i;
 884 +       u8 disable = 0;
 885 +       u8 doubletag = 0;
 886 +       u8 en_vlan = 0;
 887 +       u8 untag = 0;
 888 +
 889 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
 890 +               u32 vid, vmsc;
 891 +               if (esw->global_vlan_enable) {
 892 +                       vid = esw->vlans[i].vid;
 893 +                       vmsc = esw->vlans[i].ports;
 894 +               } else {
 895 +                       vid = RT305X_ESW_VLAN_NONE;
 896 +                       vmsc = RT305X_ESW_PORTS_NONE;
 897 +               }
 898 +               esw_set_vlan_id(esw, i, vid);
 899 +               esw_set_vmsc(esw, i, vmsc);
 900 +       }
 901 +
 902 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
 903 +               u32 pvid;
 904 +               disable |= esw->ports[i].disable << i;
 905 +               if (esw->global_vlan_enable) {
 906 +                       doubletag |= esw->ports[i].doubletag << i;
 907 +                       en_vlan   |= 1                       << i;
 908 +                       untag     |= esw->ports[i].untag     << i;
 909 +                       pvid       = esw->ports[i].pvid;
 910 +               } else {
 911 +                       int x = esw->alt_vlan_disable ? 0 : 1;
 912 +                       doubletag |= x << i;
 913 +                       en_vlan   |= x << i;
 914 +                       untag     |= x << i;
 915 +                       pvid       = 0;
 916 +               }
 917 +               esw_set_pvid(esw, i, pvid);
 918 +               if (i < RT305X_ESW_NUM_LEDS)
 919 +                       esw_w32(esw, esw->ports[i].led,
 920 +                                     RT305X_ESW_REG_P0LED + 4*i);
 921 +       }
 922 +
 923 +       esw_set_gsc(esw);
 924 +       esw_set_port_disable(esw, disable);
 925 +       esw_rmw(esw, RT305X_ESW_REG_SGC2,
 926 +                      (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
 927 +                       RT305X_ESW_SGC2_DOUBLE_TAG_S),
 928 +                      doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
 929 +       esw_rmw(esw, RT305X_ESW_REG_PFC1,
 930 +                      RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
 931 +                      en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
 932 +       esw_rmw(esw, RT305X_ESW_REG_POC2,
 933 +                      RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
 934 +                      untag << RT305X_ESW_POC2_UNTAG_EN_S);
 935 +
 936 +       if (!esw->global_vlan_enable) {
 937 +               /*
 938 +                * Still need to put all ports into vlan 0 or they'll be
 939 +                * isolated.
 940 +                * NOTE: vlan 0 is special, no vlan tag is prepended
 941 +                */
 942 +               esw_set_vlan_id(esw, 0, 0);
 943 +               esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
 944 +       }
 945 +
 946 +       return 0;
 947 +}
 948 +
 949 +static int esw_reset_switch(struct switch_dev *dev)
 950 +{
 951 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 952 +
 953 +       esw->global_vlan_enable = 0;
 954 +       memset(esw->ports, 0, sizeof(esw->ports));
 955 +       memset(esw->vlans, 0, sizeof(esw->vlans));
 956 +       esw_hw_init(esw);
 957 +
 958 +       return 0;
 959 +}
 960 +
 961 +static int esw_get_vlan_enable(struct switch_dev *dev,
 962 +                          const struct switch_attr *attr,
 963 +                          struct switch_val *val)
 964 +{
 965 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 966 +
 967 +       val->value.i = esw->global_vlan_enable;
 968 +
 969 +       return 0;
 970 +}
 971 +
 972 +static int esw_set_vlan_enable(struct switch_dev *dev,
 973 +                          const struct switch_attr *attr,
 974 +                          struct switch_val *val)
 975 +{
 976 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 977 +
 978 +       esw->global_vlan_enable = val->value.i != 0;
 979 +
 980 +       return 0;
 981 +}
 982 +
 983 +static int esw_get_alt_vlan_disable(struct switch_dev *dev,
 984 +                               const struct switch_attr *attr,
 985 +                               struct switch_val *val)
 986 +{
 987 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 988 +
 989 +       val->value.i = esw->alt_vlan_disable;
 990 +
 991 +       return 0;
 992 +}
 993 +
 994 +static int esw_set_alt_vlan_disable(struct switch_dev *dev,
 995 +                               const struct switch_attr *attr,
 996 +                               struct switch_val *val)
 997 +{
 998 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
 999 +
1000 +       esw->alt_vlan_disable = val->value.i != 0;
1001 +
1002 +       return 0;
1003 +}
1004 +
1005 +static int
1006 +rt305x_esw_set_bc_status(struct switch_dev *dev,
1007 +                       const struct switch_attr *attr,
1008 +                       struct switch_val *val)
1009 +{
1010 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1011 +
1012 +       esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
1013 +
1014 +       return 0;
1015 +}
1016 +
1017 +static int
1018 +rt305x_esw_get_bc_status(struct switch_dev *dev,
1019 +                       const struct switch_attr *attr,
1020 +                       struct switch_val *val)
1021 +{
1022 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1023 +
1024 +       val->value.i = esw->bc_storm_protect;
1025 +
1026 +       return 0;
1027 +}
1028 +
1029 +static int
1030 +rt305x_esw_set_led_freq(struct switch_dev *dev,
1031 +                       const struct switch_attr *attr,
1032 +                       struct switch_val *val)
1033 +{
1034 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1035 +
1036 +       esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
1037 +
1038 +       return 0;
1039 +}
1040 +
1041 +static int
1042 +rt305x_esw_get_led_freq(struct switch_dev *dev,
1043 +                       const struct switch_attr *attr,
1044 +                       struct switch_val *val)
1045 +{
1046 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1047 +
1048 +       val->value.i = esw->led_frequency;
1049 +
1050 +       return 0;
1051 +}
1052 +
1053 +static int esw_get_port_link(struct switch_dev *dev,
1054 +                        int port,
1055 +                        struct switch_port_link *link)
1056 +{
1057 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1058 +       u32 speed, poa;
1059 +
1060 +       if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
1061 +               return -EINVAL;
1062 +
1063 +       poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
1064 +
1065 +       link->link = (poa >> RT305X_ESW_LINK_S) & 1;
1066 +       link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
1067 +       if (port < RT305X_ESW_NUM_LEDS) {
1068 +               speed = (poa >> RT305X_ESW_SPD_S) & 1;
1069 +       } else {
1070 +               if (port == RT305X_ESW_NUM_PORTS - 1)
1071 +                       poa >>= 1;
1072 +               speed = (poa >> RT305X_ESW_SPD_S) & 3;
1073 +       }
1074 +       switch (speed) {
1075 +       case 0:
1076 +               link->speed = SWITCH_PORT_SPEED_10;
1077 +               break;
1078 +       case 1:
1079 +               link->speed = SWITCH_PORT_SPEED_100;
1080 +               break;
1081 +       case 2:
1082 +       case 3: /* forced gige speed can be 2 or 3 */
1083 +               link->speed = SWITCH_PORT_SPEED_1000;
1084 +               break;
1085 +       default:
1086 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
1087 +               break;
1088 +       }
1089 +
1090 +       return 0;
1091 +}
1092 +
1093 +static int esw_get_port_bool(struct switch_dev *dev,
1094 +                        const struct switch_attr *attr,
1095 +                        struct switch_val *val)
1096 +{
1097 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1098 +       int idx = val->port_vlan;
1099 +       u32 x, reg, shift;
1100 +
1101 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1102 +               return -EINVAL;
1103 +
1104 +       switch (attr->id) {
1105 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1106 +               reg = RT305X_ESW_REG_POC0;
1107 +               shift = RT305X_ESW_POC0_DIS_PORT_S;
1108 +               break;
1109 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1110 +               reg = RT305X_ESW_REG_SGC2;
1111 +               shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1112 +               break;
1113 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1114 +               reg = RT305X_ESW_REG_POC2;
1115 +               shift = RT305X_ESW_POC2_UNTAG_EN_S;
1116 +               break;
1117 +       case RT305X_ESW_ATTR_PORT_LAN:
1118 +               reg = RT305X_ESW_REG_SGC2;
1119 +               shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1120 +               if (idx >= RT305X_ESW_NUM_LANWAN)
1121 +                       return -EINVAL;
1122 +               break;
1123 +       default:
1124 +               return -EINVAL;
1125 +       }
1126 +
1127 +       x = esw_r32(esw, reg);
1128 +       val->value.i = (x >> (idx + shift)) & 1;
1129 +
1130 +       return 0;
1131 +}
1132 +
1133 +static int esw_set_port_bool(struct switch_dev *dev,
1134 +                        const struct switch_attr *attr,
1135 +                        struct switch_val *val)
1136 +{
1137 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1138 +       int idx = val->port_vlan;
1139 +
1140 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1141 +           val->value.i < 0 || val->value.i > 1)
1142 +               return -EINVAL;
1143 +
1144 +       switch (attr->id) {
1145 +       case RT305X_ESW_ATTR_PORT_DISABLE:
1146 +               esw->ports[idx].disable = val->value.i;
1147 +               break;
1148 +       case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1149 +               esw->ports[idx].doubletag = val->value.i;
1150 +               break;
1151 +       case RT305X_ESW_ATTR_PORT_UNTAG:
1152 +               esw->ports[idx].untag = val->value.i;
1153 +               break;
1154 +       default:
1155 +               return -EINVAL;
1156 +       }
1157 +
1158 +       return 0;
1159 +}
1160 +
1161 +static int esw_get_port_recv_badgood(struct switch_dev *dev,
1162 +                                const struct switch_attr *attr,
1163 +                                struct switch_val *val)
1164 +{
1165 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1166 +       int idx = val->port_vlan;
1167 +       int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1168 +       u32 reg;
1169 +
1170 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1171 +               return -EINVAL;
1172 +       reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1173 +       val->value.i = (reg >> shift) & 0xffff;
1174 +
1175 +       return 0;
1176 +}
1177 +
1178 +static int
1179 +esw_get_port_tr_badgood(struct switch_dev *dev,
1180 +                                const struct switch_attr *attr,
1181 +                                struct switch_val *val)
1182 +{
1183 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1184 +
1185 +       int idx = val->port_vlan;
1186 +       int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1187 +       u32 reg;
1188 +
1189 +       if (!soc_is_rt5350())
1190 +               return -EINVAL;
1191 +
1192 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1193 +               return -EINVAL;
1194 +
1195 +       reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1196 +       val->value.i = (reg >> shift) & 0xffff;
1197 +
1198 +       return 0;
1199 +}
1200 +
1201 +static int esw_get_port_led(struct switch_dev *dev,
1202 +                       const struct switch_attr *attr,
1203 +                       struct switch_val *val)
1204 +{
1205 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1206 +       int idx = val->port_vlan;
1207 +
1208 +       if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1209 +           idx >= RT305X_ESW_NUM_LEDS)
1210 +               return -EINVAL;
1211 +
1212 +       val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1213 +
1214 +       return 0;
1215 +}
1216 +
1217 +static int esw_set_port_led(struct switch_dev *dev,
1218 +                       const struct switch_attr *attr,
1219 +                       struct switch_val *val)
1220 +{
1221 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1222 +       int idx = val->port_vlan;
1223 +
1224 +       if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1225 +               return -EINVAL;
1226 +
1227 +       esw->ports[idx].led = val->value.i;
1228 +
1229 +       return 0;
1230 +}
1231 +
1232 +static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1233 +{
1234 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1235 +
1236 +       if (port >= RT305X_ESW_NUM_PORTS)
1237 +               return -EINVAL;
1238 +
1239 +       *val = esw_get_pvid(esw, port);
1240 +
1241 +       return 0;
1242 +}
1243 +
1244 +static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1245 +{
1246 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1247 +
1248 +       if (port >= RT305X_ESW_NUM_PORTS)
1249 +               return -EINVAL;
1250 +
1251 +       esw->ports[port].pvid = val;
1252 +
1253 +       return 0;
1254 +}
1255 +
1256 +static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1257 +{
1258 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1259 +       u32 vmsc, poc2;
1260 +       int vlan_idx = -1;
1261 +       int i;
1262 +
1263 +       val->len = 0;
1264 +
1265 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1266 +               return -EINVAL;
1267 +
1268 +       /* valid vlan? */
1269 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1270 +               if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1271 +                   esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1272 +                       vlan_idx = i;
1273 +                       break;
1274 +               }
1275 +       }
1276 +
1277 +       if (vlan_idx == -1)
1278 +               return -EINVAL;
1279 +
1280 +       vmsc = esw_get_vmsc(esw, vlan_idx);
1281 +       poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1282 +
1283 +       for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1284 +               struct switch_port *p;
1285 +               int port_mask = 1 << i;
1286 +
1287 +               if (!(vmsc & port_mask))
1288 +                       continue;
1289 +
1290 +               p = &val->value.ports[val->len++];
1291 +               p->id = i;
1292 +               if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1293 +                       p->flags = 0;
1294 +               else
1295 +                       p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1296 +       }
1297 +
1298 +       return 0;
1299 +}
1300 +
1301 +static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1302 +{
1303 +       struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1304 +       int ports;
1305 +       int vlan_idx = -1;
1306 +       int i;
1307 +
1308 +       if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1309 +           val->len > RT305X_ESW_NUM_PORTS)
1310 +               return -EINVAL;
1311 +
1312 +       /* one of the already defined vlans? */
1313 +       for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1314 +               if (esw->vlans[i].vid == val->port_vlan &&
1315 +                   esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1316 +                       vlan_idx = i;
1317 +                       break;
1318 +               }
1319 +       }
1320 +
1321 +       /* select a free slot */
1322 +       for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1323 +               if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1324 +                       vlan_idx = i;
1325 +       }
1326 +
1327 +       /* bail if all slots are in use */
1328 +       if (vlan_idx == -1)
1329 +               return -EINVAL;
1330 +
1331 +       ports = RT305X_ESW_PORTS_NONE;
1332 +       for (i = 0; i < val->len; i++) {
1333 +               struct switch_port *p = &val->value.ports[i];
1334 +               int port_mask = 1 << p->id;
1335 +               bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1336 +
1337 +               if (p->id >= RT305X_ESW_NUM_PORTS)
1338 +                       return -EINVAL;
1339 +
1340 +               ports |= port_mask;
1341 +               esw->ports[p->id].untag = untagged;
1342 +       }
1343 +       esw->vlans[vlan_idx].ports = ports;
1344 +       if (ports == RT305X_ESW_PORTS_NONE)
1345 +               esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1346 +       else
1347 +               esw->vlans[vlan_idx].vid = val->port_vlan;
1348 +
1349 +       return 0;
1350 +}
1351 +
1352 +static const struct switch_attr esw_global[] = {
1353 +       {
1354 +               .type = SWITCH_TYPE_INT,
1355 +               .name = "enable_vlan",
1356 +               .description = "VLAN mode (1:enabled)",
1357 +               .max = 1,
1358 +               .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1359 +               .get = esw_get_vlan_enable,
1360 +               .set = esw_set_vlan_enable,
1361 +       },
1362 +       {
1363 +               .type = SWITCH_TYPE_INT,
1364 +               .name = "alternate_vlan_disable",
1365 +               .description = "Use en_vlan instead of doubletag to disable"
1366 +                               " VLAN mode",
1367 +               .max = 1,
1368 +               .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1369 +               .get = esw_get_alt_vlan_disable,
1370 +               .set = esw_set_alt_vlan_disable,
1371 +       },
1372 +       {
1373 +               .type = SWITCH_TYPE_INT,
1374 +               .name = "bc_storm_protect",
1375 +               .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1376 +               .max = 3,
1377 +               .id = RT305X_ESW_ATTR_BC_STATUS,
1378 +               .get = rt305x_esw_get_bc_status,
1379 +               .set = rt305x_esw_set_bc_status,
1380 +       },
1381 +       {
1382 +               .type = SWITCH_TYPE_INT,
1383 +               .name = "led_frequency",
1384 +               .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1385 +               .max = 3,
1386 +               .id = RT305X_ESW_ATTR_LED_FREQ,
1387 +               .get = rt305x_esw_get_led_freq,
1388 +               .set = rt305x_esw_set_led_freq,
1389 +       }
1390 +};
1391 +
1392 +static const struct switch_attr esw_port[] = {
1393 +       {
1394 +               .type = SWITCH_TYPE_INT,
1395 +               .name = "disable",
1396 +               .description = "Port state (1:disabled)",
1397 +               .max = 1,
1398 +               .id = RT305X_ESW_ATTR_PORT_DISABLE,
1399 +               .get = esw_get_port_bool,
1400 +               .set = esw_set_port_bool,
1401 +       },
1402 +       {
1403 +               .type = SWITCH_TYPE_INT,
1404 +               .name = "doubletag",
1405 +               .description = "Double tagging for incoming vlan packets "
1406 +                               "(1:enabled)",
1407 +               .max = 1,
1408 +               .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1409 +               .get = esw_get_port_bool,
1410 +               .set = esw_set_port_bool,
1411 +       },
1412 +       {
1413 +               .type = SWITCH_TYPE_INT,
1414 +               .name = "untag",
1415 +               .description = "Untag (1:strip outgoing vlan tag)",
1416 +               .max = 1,
1417 +               .id = RT305X_ESW_ATTR_PORT_UNTAG,
1418 +               .get = esw_get_port_bool,
1419 +               .set = esw_set_port_bool,
1420 +       },
1421 +       {
1422 +               .type = SWITCH_TYPE_INT,
1423 +               .name = "led",
1424 +               .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1425 +                               " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1426 +                               " 8:100mact, 10:blink, 11:off, 12:on)",
1427 +               .max = 15,
1428 +               .id = RT305X_ESW_ATTR_PORT_LED,
1429 +               .get = esw_get_port_led,
1430 +               .set = esw_set_port_led,
1431 +       },
1432 +       {
1433 +               .type = SWITCH_TYPE_INT,
1434 +               .name = "lan",
1435 +               .description = "HW port group (0:wan, 1:lan)",
1436 +               .max = 1,
1437 +               .id = RT305X_ESW_ATTR_PORT_LAN,
1438 +               .get = esw_get_port_bool,
1439 +       },
1440 +       {
1441 +               .type = SWITCH_TYPE_INT,
1442 +               .name = "recv_bad",
1443 +               .description = "Receive bad packet counter",
1444 +               .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1445 +               .get = esw_get_port_recv_badgood,
1446 +       },
1447 +       {
1448 +               .type = SWITCH_TYPE_INT,
1449 +               .name = "recv_good",
1450 +               .description = "Receive good packet counter",
1451 +               .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1452 +               .get = esw_get_port_recv_badgood,
1453 +       },
1454 +       {
1455 +               .type = SWITCH_TYPE_INT,
1456 +               .name = "tr_bad",
1457 +
1458 +               .description = "Transmit bad packet counter. rt5350 only",
1459 +               .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1460 +               .get = esw_get_port_tr_badgood,
1461 +       },
1462 +       {
1463 +               .type = SWITCH_TYPE_INT,
1464 +               .name = "tr_good",
1465 +
1466 +               .description = "Transmit good packet counter. rt5350 only",
1467 +               .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1468 +               .get = esw_get_port_tr_badgood,
1469 +       },
1470 +};
1471 +
1472 +static const struct switch_attr esw_vlan[] = {
1473 +};
1474 +
1475 +static const struct switch_dev_ops esw_ops = {
1476 +       .attr_global = {
1477 +               .attr = esw_global,
1478 +               .n_attr = ARRAY_SIZE(esw_global),
1479 +       },
1480 +       .attr_port = {
1481 +               .attr = esw_port,
1482 +               .n_attr = ARRAY_SIZE(esw_port),
1483 +       },
1484 +       .attr_vlan = {
1485 +               .attr = esw_vlan,
1486 +               .n_attr = ARRAY_SIZE(esw_vlan),
1487 +       },
1488 +       .get_vlan_ports = esw_get_vlan_ports,
1489 +       .set_vlan_ports = esw_set_vlan_ports,
1490 +       .get_port_pvid = esw_get_port_pvid,
1491 +       .set_port_pvid = esw_set_port_pvid,
1492 +       .get_port_link = esw_get_port_link,
1493 +       .apply_config = esw_apply_config,
1494 +       .reset_switch = esw_reset_switch,
1495 +};
1496 +
1497 +static struct rt305x_esw_platform_data rt3050_esw_data = {
1498 +       /* All ports are LAN ports. */
1499 +       .vlan_config            = RT305X_ESW_VLAN_CONFIG_NONE,
1500 +       .reg_initval_fct2       = 0x00d6500c,
1501 +       /*
1502 +        * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
1503 +        * turbo mii off, rgmi 3.3v off
1504 +        * port5: disabled
1505 +        * port6: enabled, gige, full-duplex, rx/tx-flow-control
1506 +        */
1507 +       .reg_initval_fpa2       = 0x3f502b28,
1508 +};
1509 +
1510 +static const struct of_device_id ralink_esw_match[] = {
1511 +       { .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
1512 +       {},
1513 +};
1514 +MODULE_DEVICE_TABLE(of, ralink_esw_match);
1515 +
1516 +static int esw_probe(struct platform_device *pdev)
1517 +{
1518 +       struct device_node *np = pdev->dev.of_node;
1519 +       const struct rt305x_esw_platform_data *pdata;
1520 +       const __be32 *port_map, *reg_init;
1521 +       struct rt305x_esw *esw;
1522 +       struct switch_dev *swdev;
1523 +       struct resource *res, *irq;
1524 +       int err;
1525 +
1526 +       pdata = pdev->dev.platform_data;
1527 +       if (!pdata) {
1528 +               const struct of_device_id *match;
1529 +               match = of_match_device(ralink_esw_match, &pdev->dev);
1530 +               if (match)
1531 +                       pdata = (struct rt305x_esw_platform_data *) match->data;
1532 +       }
1533 +       if (!pdata)
1534 +               return -EINVAL;
1535 +
1536 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1537 +       if (!res) {
1538 +               dev_err(&pdev->dev, "no memory resource found\n");
1539 +               return -ENOMEM;
1540 +       }
1541 +
1542 +       irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1543 +       if (!irq) {
1544 +               dev_err(&pdev->dev, "no irq resource found\n");
1545 +               return -ENOMEM;
1546 +       }
1547 +
1548 +       esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
1549 +       if (!esw) {
1550 +               dev_err(&pdev->dev, "no memory for private data\n");
1551 +               return -ENOMEM;
1552 +       }
1553 +
1554 +       esw->dev = &pdev->dev;
1555 +       esw->irq = irq->start;
1556 +       esw->base = ioremap(res->start, resource_size(res));
1557 +       if (!esw->base) {
1558 +               dev_err(&pdev->dev, "ioremap failed\n");
1559 +               err = -ENOMEM;
1560 +               goto free_esw;
1561 +       }
1562 +
1563 +       port_map = of_get_property(np, "ralink,portmap", NULL);
1564 +        if (port_map)
1565 +               esw->port_map = be32_to_cpu(*port_map);
1566 +
1567 +       reg_init = of_get_property(np, "ralink,fct2", NULL);
1568 +        if (reg_init)
1569 +               esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1570 +
1571 +       reg_init = of_get_property(np, "ralink,fpa2", NULL);
1572 +        if (reg_init)
1573 +               esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1574 +
1575 +       reg_init = of_get_property(np, "ralink,led_polarity", NULL);
1576 +        if (reg_init)
1577 +               esw->reg_led_polarity = be32_to_cpu(*reg_init);
1578 +
1579 +       swdev = &esw->swdev;
1580 +       swdev->of_node = pdev->dev.of_node;
1581 +       swdev->name = "rt305x-esw";
1582 +       swdev->alias = "rt305x";
1583 +       swdev->cpu_port = RT305X_ESW_PORT6;
1584 +       swdev->ports = RT305X_ESW_NUM_PORTS;
1585 +       swdev->vlans = RT305X_ESW_NUM_VIDS;
1586 +       swdev->ops = &esw_ops;
1587 +
1588 +       err = register_switch(swdev, NULL);
1589 +       if (err < 0) {
1590 +               dev_err(&pdev->dev, "register_switch failed\n");
1591 +               goto unmap_base;
1592 +       }
1593 +
1594 +       platform_set_drvdata(pdev, esw);
1595 +
1596 +       esw->pdata = pdata;
1597 +       spin_lock_init(&esw->reg_rw_lock);
1598 +
1599 +       esw_hw_init(esw);
1600 +
1601 +       esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1602 +       esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1603 +       request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
1604 +
1605 +       return 0;
1606 +
1607 +unmap_base:
1608 +       iounmap(esw->base);
1609 +free_esw:
1610 +       kfree(esw);
1611 +       return err;
1612 +}
1613 +
1614 +static int esw_remove(struct platform_device *pdev)
1615 +{
1616 +       struct rt305x_esw *esw;
1617 +
1618 +       esw = platform_get_drvdata(pdev);
1619 +       if (esw) {
1620 +               unregister_switch(&esw->swdev);
1621 +               platform_set_drvdata(pdev, NULL);
1622 +               iounmap(esw->base);
1623 +               kfree(esw);
1624 +       }
1625 +
1626 +       return 0;
1627 +}
1628 +
1629 +static struct platform_driver esw_driver = {
1630 +       .probe = esw_probe,
1631 +       .remove = esw_remove,
1632 +       .driver = {
1633 +               .name = "rt305x-esw",
1634 +               .owner = THIS_MODULE,
1635 +               .of_match_table = ralink_esw_match,
1636 +       },
1637 +};
1638 +
1639 +int __init rtesw_init(void)
1640 +{
1641 +       return platform_driver_register(&esw_driver);
1642 +}
1643 +
1644 +void rtesw_exit(void)
1645 +{
1646 +       platform_driver_unregister(&esw_driver);
1647 +}
1648 Index: linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.h
1649 ===================================================================
1650 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1651 +++ linux-3.14.18/drivers/net/ethernet/ralink/esw_rt3052.h      2014-10-29 20:25:55.433357519 +0100
1652 @@ -0,0 +1,32 @@
1653 +/*
1654 + *   This program is free software; you can redistribute it and/or modify
1655 + *   it under the terms of the GNU General Public License as published by
1656 + *   the Free Software Foundation; version 2 of the License
1657 + *
1658 + *   This program is distributed in the hope that it will be useful,
1659 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1660 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1661 + *   GNU General Public License for more details.
1662 + *
1663 + *   You should have received a copy of the GNU General Public License
1664 + *   along with this program; if not, write to the Free Software
1665 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1666 + *
1667 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1668 + */
1669 +
1670 +#ifndef _RALINK_ESW_RT3052_H__
1671 +#define _RALINK_ESW_RT3052_H__
1672 +
1673 +#ifdef CONFIG_NET_RALINK_ESW_RT3052
1674 +
1675 +int __init rtesw_init(void);
1676 +void rtesw_exit(void);
1677 +
1678 +#else
1679 +
1680 +static inline int __init rtesw_init(void) { return 0; }
1681 +static inline void rtesw_exit(void) { }
1682 +
1683 +#endif
1684 +#endif
1685 Index: linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.c
1686 ===================================================================
1687 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
1688 +++ linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.c     2014-10-30 09:02:08.735269671 +0100
1689 @@ -0,0 +1,569 @@
1690 +/*
1691 + *   This program is free software; you can redistribute it and/or modify
1692 + *   it under the terms of the GNU General Public License as published by
1693 + *   the Free Software Foundation; version 2 of the License
1694 + *
1695 + *   This program is distributed in the hope that it will be useful,
1696 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
1697 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1698 + *   GNU General Public License for more details.
1699 + *
1700 + *   You should have received a copy of the GNU General Public License
1701 + *   along with this program; if not, write to the Free Software
1702 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
1703 + *
1704 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
1705 + */
1706 +
1707 +#include <linux/module.h>
1708 +#include <linux/kernel.h>
1709 +#include <linux/types.h>
1710 +#include <linux/dma-mapping.h>
1711 +#include <linux/init.h>
1712 +#include <linux/skbuff.h>
1713 +#include <linux/etherdevice.h>
1714 +#include <linux/ethtool.h>
1715 +#include <linux/platform_device.h>
1716 +#include <linux/of_device.h>
1717 +#include <linux/clk.h>
1718 +#include <linux/of_net.h>
1719 +#include <linux/of_mdio.h>
1720 +#include <linux/of_irq.h>
1721 +#include <linux/of_address.h>
1722 +#include <linux/switch.h>
1723 +
1724 +#include <asm/mach-ralink/ralink_regs.h>
1725 +
1726 +#include "ralink_soc_eth.h"
1727 +
1728 +#include <linux/ioport.h>
1729 +#include <linux/switch.h>
1730 +#include <linux/mii.h>
1731 +
1732 +#include <ralink_regs.h>
1733 +#include <asm/mach-ralink/mt7620.h>
1734 +
1735 +#include "ralink_soc_eth.h"
1736 +#include "gsw_mt7620a.h"
1737 +#include "mt7530.h"
1738 +#include "mdio.h"
1739 +
1740 +#define GSW_REG_PHY_TIMEOUT    (5 * HZ)
1741 +
1742 +#define MT7620A_GSW_REG_PIAC   0x7004
1743 +
1744 +#define GSW_NUM_VLANS          16
1745 +#define GSW_NUM_VIDS           4096
1746 +#define GSW_NUM_PORTS          7
1747 +#define GSW_PORT6              6
1748 +
1749 +#define GSW_MDIO_ACCESS                BIT(31)
1750 +#define GSW_MDIO_READ          BIT(19)
1751 +#define GSW_MDIO_WRITE         BIT(18)
1752 +#define GSW_MDIO_START         BIT(16)
1753 +#define GSW_MDIO_ADDR_SHIFT    20
1754 +#define GSW_MDIO_REG_SHIFT     25
1755 +
1756 +#define GSW_REG_PORT_PMCR(x)   (0x3000 + (x * 0x100))
1757 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
1758 +#define GSW_REG_SMACCR0                0x3fE4
1759 +#define GSW_REG_SMACCR1                0x3fE8
1760 +#define GSW_REG_CKGCR          0x3ff0
1761 +
1762 +#define GSW_REG_IMR            0x7008
1763 +#define GSW_REG_ISR            0x700c
1764 +
1765 +#define SYSC_REG_CFG1          0x14
1766 +
1767 +#define PORT_IRQ_ST_CHG                0x7f
1768 +
1769 +#define SYSCFG1                        0x14
1770 +
1771 +#define ESW_PHY_POLLING                0x7000
1772 +
1773 +#define        PMCR_IPG                BIT(18)
1774 +#define        PMCR_MAC_MODE           BIT(16)
1775 +#define        PMCR_FORCE              BIT(15)
1776 +#define        PMCR_TX_EN              BIT(14)
1777 +#define        PMCR_RX_EN              BIT(13)
1778 +#define        PMCR_BACKOFF            BIT(9)
1779 +#define        PMCR_BACKPRES           BIT(8)
1780 +#define        PMCR_RX_FC              BIT(5)
1781 +#define        PMCR_TX_FC              BIT(4)
1782 +#define        PMCR_SPEED(_x)          (_x << 2)
1783 +#define        PMCR_DUPLEX             BIT(1)
1784 +#define        PMCR_LINK               BIT(0)
1785 +
1786 +#define PHY_AN_EN              BIT(31)
1787 +#define PHY_PRE_EN             BIT(30)
1788 +#define PMY_MDC_CONF(_x)       ((_x & 0x3f) << 24)
1789 +
1790 +enum {
1791 +       /* Global attributes. */
1792 +       GSW_ATTR_ENABLE_VLAN,
1793 +       /* Port attributes. */
1794 +       GSW_ATTR_PORT_UNTAG,
1795 +};
1796 +
1797 +enum {
1798 +       PORT4_EPHY = 0,
1799 +       PORT4_EXT,
1800 +};
1801 +
1802 +struct mt7620_gsw {
1803 +       struct device           *dev;
1804 +       void __iomem            *base;
1805 +       int                     irq;
1806 +       int                     port4;
1807 +       long unsigned int       autopoll;
1808 +};
1809 +
1810 +static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
1811 +{
1812 +       iowrite32(val, gsw->base + reg);
1813 +}
1814 +
1815 +static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
1816 +{
1817 +       return ioread32(gsw->base + reg);
1818 +}
1819 +
1820 +static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
1821 +{
1822 +       unsigned long t_start = jiffies;
1823 +
1824 +       while (1) {
1825 +               if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
1826 +                       return 0;
1827 +               if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
1828 +                       break;
1829 +               }
1830 +       }
1831 +
1832 +       printk(KERN_ERR "mdio: MDIO timeout\n");
1833 +       return -1;
1834 +}
1835 +
1836 +static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
1837 +                               u32 write_data)
1838 +{
1839 +       if (mt7620_mii_busy_wait(gsw))
1840 +               return -1;
1841 +
1842 +       write_data &= 0xffff;
1843 +
1844 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
1845 +               (phy_register << GSW_MDIO_REG_SHIFT) |
1846 +               (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
1847 +               MT7620A_GSW_REG_PIAC);
1848 +
1849 +       if (mt7620_mii_busy_wait(gsw))
1850 +               return -1;
1851 +
1852 +       return 0;
1853 +}
1854 +
1855 +static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
1856 +{
1857 +       u32 d;
1858 +
1859 +       if (mt7620_mii_busy_wait(gsw))
1860 +               return 0xffff;
1861 +
1862 +       gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
1863 +               (phy_reg << GSW_MDIO_REG_SHIFT) |
1864 +               (phy_addr << GSW_MDIO_ADDR_SHIFT),
1865 +               MT7620A_GSW_REG_PIAC);
1866 +
1867 +       if (mt7620_mii_busy_wait(gsw))
1868 +               return 0xffff;
1869 +
1870 +       d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
1871 +
1872 +       return d;
1873 +}
1874 +
1875 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
1876 +{
1877 +       struct fe_priv *priv = bus->priv;
1878 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1879 +
1880 +       return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
1881 +}
1882 +
1883 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
1884 +{
1885 +       struct fe_priv *priv = bus->priv;
1886 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1887 +
1888 +       return _mt7620_mii_read(gsw, phy_addr, phy_reg);
1889 +}
1890 +
1891 +static unsigned char *fe_speed_str(int speed)
1892 +{
1893 +       switch (speed) {
1894 +       case 2:
1895 +       case SPEED_1000:
1896 +               return "1000";
1897 +       case 1:
1898 +       case SPEED_100:
1899 +               return "100";
1900 +       case 0:
1901 +       case SPEED_10:
1902 +               return "10";
1903 +       }
1904 +
1905 +       return "? ";
1906 +}
1907 +
1908 +int mt7620a_has_carrier(struct fe_priv *priv)
1909 +{
1910 +        struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1911 +       int i;
1912 +
1913 +       for (i = 0; i < GSW_PORT6; i++)
1914 +               if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
1915 +                       return 1;
1916 +       return 0;
1917 +}
1918 +
1919 +static void mt7620a_handle_carrier(struct fe_priv *priv)
1920 +{
1921 +       if (!priv->phy)
1922 +               return;
1923 +
1924 +       if (mt7620a_has_carrier(priv))
1925 +               netif_carrier_on(priv->netdev);
1926 +       else
1927 +               netif_carrier_off(priv->netdev);
1928 +}
1929 +
1930 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
1931 +{
1932 +       if (priv->link[port])
1933 +               netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1934 +                       port, fe_speed_str(priv->phy->speed[port]),
1935 +                       (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
1936 +       else
1937 +               netdev_info(priv->netdev, "port %d link down\n", port);
1938 +       mt7620a_handle_carrier(priv);
1939 +}
1940 +
1941 +static irqreturn_t gsw_interrupt(int irq, void *_priv)
1942 +{
1943 +       struct fe_priv *priv = (struct fe_priv *) _priv;
1944 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1945 +       u32 status;
1946 +       int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
1947 +
1948 +       status = gsw_r32(gsw, GSW_REG_ISR);
1949 +       if (status & PORT_IRQ_ST_CHG)
1950 +               for (i = 0; i <= max; i++) {
1951 +                       u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
1952 +                       int link = status & 0x1;
1953 +
1954 +                       if (link != priv->link[i]) {
1955 +                               if (link)
1956 +                                       netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
1957 +                                                       i, fe_speed_str((status >> 2) & 3),
1958 +                                                       (status & 0x2) ? "Full" : "Half");
1959 +                               else
1960 +                                       netdev_info(priv->netdev, "port %d link down\n", i);
1961 +                       }
1962 +
1963 +                       priv->link[i] = link;
1964 +               }
1965 +       mt7620a_handle_carrier(priv);
1966 +
1967 +       gsw_w32(gsw, status, GSW_REG_ISR);
1968 +
1969 +       return IRQ_HANDLED;
1970 +}
1971 +
1972 +static int mt7620_is_bga(void)
1973 +{
1974 +       u32 bga = rt_sysc_r32(0x0c);
1975 +
1976 +       return (bga >> 16) & 1;
1977 +}
1978 +
1979 +static void gsw_auto_poll(struct mt7620_gsw *gsw)
1980 +{
1981 +       int phy;
1982 +       int lsb = -1, msb = 0;
1983 +
1984 +       for_each_set_bit(phy, &gsw->autopoll, 32) {
1985 +               if (lsb < 0)
1986 +                       lsb = phy;
1987 +               msb = phy;
1988 +       }
1989 +
1990 +       gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
1991 +}
1992 +
1993 +void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
1994 +{
1995 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
1996 +       const __be32 *_id = of_get_property(np, "reg", NULL);
1997 +       int phy_mode, size, id;
1998 +       int shift = 12;
1999 +       u32 val, mask = 0;
2000 +       int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
2001 +
2002 +       if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
2003 +               if (_id)
2004 +                       pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
2005 +               else
2006 +                       pr_err("%s: invalid port id\n", np->name);
2007 +               return;
2008 +       }
2009 +
2010 +       id = be32_to_cpu(*_id);
2011 +
2012 +       if (id == 4)
2013 +               shift = 14;
2014 +
2015 +       priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
2016 +       if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
2017 +               pr_err("%s: invalid fixed link property\n", np->name);
2018 +               priv->phy->phy_fixed[id] = NULL;
2019 +               return;
2020 +       }
2021 +
2022 +       phy_mode = of_get_phy_mode(np);
2023 +       switch (phy_mode) {
2024 +       case PHY_INTERFACE_MODE_RGMII:
2025 +               mask = 0;
2026 +               break;
2027 +       case PHY_INTERFACE_MODE_MII:
2028 +               mask = 1;
2029 +               break;
2030 +       case PHY_INTERFACE_MODE_RMII:
2031 +               mask = 2;
2032 +               break;
2033 +       default:
2034 +               dev_err(priv->device, "port %d - invalid phy mode\n", id);
2035 +               return;
2036 +       }
2037 +
2038 +       priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
2039 +       if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
2040 +               return;
2041 +
2042 +       val = rt_sysc_r32(SYSCFG1);
2043 +       val &= ~(3 << shift);
2044 +       val |= mask << shift;
2045 +       rt_sysc_w32(val, SYSCFG1);
2046 +
2047 +       if (priv->phy->phy_fixed[id]) {
2048 +               const __be32 *link = priv->phy->phy_fixed[id];
2049 +               int tx_fc, rx_fc;
2050 +               u32 val = 0;
2051 +
2052 +               priv->phy->speed[id] = be32_to_cpup(link++);
2053 +               tx_fc = be32_to_cpup(link++);
2054 +               rx_fc = be32_to_cpup(link++);
2055 +               priv->phy->duplex[id] = be32_to_cpup(link++);
2056 +               priv->link[id] = 1;
2057 +
2058 +               switch (priv->phy->speed[id]) {
2059 +               case SPEED_10:
2060 +                       val = 0;
2061 +                       break;
2062 +               case SPEED_100:
2063 +                       val = 1;
2064 +                       break;
2065 +               case SPEED_1000:
2066 +                       val = 2;
2067 +                       break;
2068 +               default:
2069 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
2070 +                       priv->phy->phy_fixed[id] = 0;
2071 +                       return;
2072 +               }
2073 +               val = PMCR_SPEED(val);
2074 +               val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2075 +                       PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
2076 +               if (tx_fc)
2077 +                       val |= PMCR_TX_FC;
2078 +               if (rx_fc)
2079 +                       val |= PMCR_RX_FC;
2080 +               if (priv->phy->duplex[id])
2081 +                       val |= PMCR_DUPLEX;
2082 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2083 +               dev_info(priv->device, "using fixed link parameters\n");
2084 +               return;
2085 +       }
2086 +
2087 +       if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
2088 +               u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
2089 +                       PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
2090 +
2091 +               gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
2092 +               fe_connect_phy_node(priv, priv->phy->phy_node[id]);
2093 +               gsw->autopoll |= BIT(id);
2094 +               gsw_auto_poll(gsw);
2095 +               return;
2096 +       }
2097 +}
2098 +
2099 +static void gsw_hw_init(struct mt7620_gsw *gsw)
2100 +{
2101 +       u32 is_BGA = mt7620_is_bga();
2102 +
2103 +       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
2104 +       gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
2105 +
2106 +       /*correct  PHY  setting L3.0 BGA*/
2107 +       _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
2108 +
2109 +       _mt7620_mii_write(gsw, 1, 17, 0x7444);
2110 +       if (is_BGA)
2111 +               _mt7620_mii_write(gsw, 1, 19, 0x0114);
2112 +       else
2113 +               _mt7620_mii_write(gsw, 1, 19, 0x0117);
2114 +
2115 +       _mt7620_mii_write(gsw, 1, 22, 0x10cf);
2116 +       _mt7620_mii_write(gsw, 1, 25, 0x6212);
2117 +       _mt7620_mii_write(gsw, 1, 26, 0x0777);
2118 +       _mt7620_mii_write(gsw, 1, 29, 0x4000);
2119 +       _mt7620_mii_write(gsw, 1, 28, 0xc077);
2120 +       _mt7620_mii_write(gsw, 1, 24, 0x0000);
2121 +
2122 +       _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
2123 +       _mt7620_mii_write(gsw, 1, 17, 0x4838);
2124 +
2125 +       _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
2126 +       if (is_BGA) {
2127 +               _mt7620_mii_write(gsw, 1, 21, 0x0515);
2128 +               _mt7620_mii_write(gsw, 1, 22, 0x0053);
2129 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2130 +               _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
2131 +               _mt7620_mii_write(gsw, 1, 25, 0x0fad);
2132 +               _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
2133 +       } else {
2134 +               _mt7620_mii_write(gsw, 1, 21, 0x0517);
2135 +               _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
2136 +               _mt7620_mii_write(gsw, 1, 23, 0x00bf);
2137 +               _mt7620_mii_write(gsw, 1, 24, 0x0aab);
2138 +               _mt7620_mii_write(gsw, 1, 25, 0x00ae);
2139 +               _mt7620_mii_write(gsw, 1, 26, 0x0fff);
2140 +       }
2141 +       _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
2142 +       _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
2143 +
2144 +       _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
2145 +       _mt7620_mii_write(gsw, 0, 30, 0xa000);
2146 +       _mt7620_mii_write(gsw, 1, 30, 0xa000);
2147 +       _mt7620_mii_write(gsw, 2, 30, 0xa000);
2148 +       _mt7620_mii_write(gsw, 3, 30, 0xa000);
2149 +
2150 +       _mt7620_mii_write(gsw, 0, 4, 0x05e1);
2151 +       _mt7620_mii_write(gsw, 1, 4, 0x05e1);
2152 +       _mt7620_mii_write(gsw, 2, 4, 0x05e1);
2153 +       _mt7620_mii_write(gsw, 3, 4, 0x05e1);
2154 +
2155 +       _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
2156 +       _mt7620_mii_write(gsw, 0, 16, 0x1111);
2157 +       _mt7620_mii_write(gsw, 1, 16, 0x1010);
2158 +       _mt7620_mii_write(gsw, 2, 16, 0x1515);
2159 +       _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
2160 +
2161 +       /* CPU Port6 Force Link 1G, FC ON */
2162 +       gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
2163 +       /* Set Port6 CPU Port */
2164 +       gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
2165 +
2166 +       /* setup port 4 */
2167 +       if (gsw->port4 == PORT4_EPHY) {
2168 +               u32 val = rt_sysc_r32(SYSCFG1);
2169 +               val |= 3 << 14;
2170 +               rt_sysc_w32(val, SYSCFG1);
2171 +               _mt7620_mii_write(gsw, 4, 30, 0xa000);
2172 +               _mt7620_mii_write(gsw, 4, 4, 0x05e1);
2173 +               _mt7620_mii_write(gsw, 4, 16, 0x1313);
2174 +               pr_info("gsw: setting port4 to ephy mode\n");
2175 +       }
2176 +}
2177 +
2178 +void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
2179 +{
2180 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2181 +       unsigned long flags;
2182 +
2183 +       spin_lock_irqsave(&priv->page_lock, flags);
2184 +       gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
2185 +       gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
2186 +               GSW_REG_SMACCR0);
2187 +       spin_unlock_irqrestore(&priv->page_lock, flags);
2188 +}
2189 +
2190 +static struct of_device_id gsw_match[] = {
2191 +       { .compatible = "ralink,mt7620a-gsw" },
2192 +       {}
2193 +};
2194 +
2195 +int mt7620_gsw_config(struct fe_priv *priv)
2196 +{
2197 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
2198 +
2199 +       /* is the mt7530 internal or external */
2200 +       if (priv->mii_bus->phy_map[0x1f]) {
2201 +               mt7530_probe(priv->device, gsw->base, NULL, 0);
2202 +               mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
2203 +       } else {
2204 +               mt7530_probe(priv->device, gsw->base, NULL, 1);
2205 +       }
2206 +
2207 +       return 0;
2208 +}
2209 +
2210 +int mt7620_gsw_probe(struct fe_priv *priv)
2211 +{
2212 +       struct mt7620_gsw *gsw;
2213 +       struct device_node *np;
2214 +       const char *port4 = NULL;
2215 +
2216 +       np = of_find_matching_node(NULL, gsw_match);
2217 +       if (!np) {
2218 +               dev_err(priv->device, "no gsw node found\n");
2219 +               return -EINVAL;
2220 +       }
2221 +       np = of_node_get(np);
2222 +
2223 +       gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
2224 +       if (!gsw) {
2225 +               dev_err(priv->device, "no gsw memory for private data\n");
2226 +               return -ENOMEM;
2227 +       }
2228 +
2229 +       gsw->irq = irq_of_parse_and_map(np, 0);
2230 +       if (!gsw->irq) {
2231 +               dev_err(priv->device, "no gsw irq resource found\n");
2232 +               return -ENOMEM;
2233 +       }
2234 +
2235 +       gsw->base = of_iomap(np, 0);
2236 +       if (!gsw->base) {
2237 +               dev_err(priv->device, "gsw ioremap failed\n");
2238 +               return -ENOMEM;
2239 +       }
2240 +
2241 +       gsw->dev = priv->device;
2242 +       priv->soc->swpriv = gsw;
2243 +
2244 +       of_property_read_string(np, "ralink,port4", &port4);
2245 +       if (port4 && !strcmp(port4, "ephy"))
2246 +               gsw->port4 = PORT4_EPHY;
2247 +       else if (port4 && !strcmp(port4, "gmac"))
2248 +               gsw->port4 = PORT4_EXT;
2249 +       else
2250 +               WARN_ON(port4);
2251 +
2252 +       gsw_hw_init(gsw);
2253 +
2254 +       gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
2255 +       request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
2256 +
2257 +       return 0;
2258 +}
2259 Index: linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.h
2260 ===================================================================
2261 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2262 +++ linux-3.14.18/drivers/net/ethernet/ralink/gsw_mt7620a.h     2014-10-29 20:25:55.433357519 +0100
2263 @@ -0,0 +1,30 @@
2264 +/*
2265 + *   This program is free software; you can redistribute it and/or modify
2266 + *   it under the terms of the GNU General Public License as published by
2267 + *   the Free Software Foundation; version 2 of the License
2268 + *
2269 + *   This program is distributed in the hope that it will be useful,
2270 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2271 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2272 + *   GNU General Public License for more details.
2273 + *
2274 + *   You should have received a copy of the GNU General Public License
2275 + *   along with this program; if not, write to the Free Software
2276 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2277 + *
2278 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2279 + */
2280 +
2281 +#ifndef _RALINK_GSW_MT7620_H__
2282 +#define _RALINK_GSW_MT7620_H__
2283 +
2284 +extern int mt7620_gsw_config(struct fe_priv *priv);
2285 +extern int mt7620_gsw_probe(struct fe_priv *priv);
2286 +extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
2287 +extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2288 +extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2289 +extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
2290 +extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
2291 +extern int mt7620a_has_carrier(struct fe_priv *priv);
2292 +
2293 +#endif
2294 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio.c
2295 ===================================================================
2296 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2297 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio.c    2014-10-29 20:25:55.433357519 +0100
2298 @@ -0,0 +1,275 @@
2299 +/*
2300 + *   This program is free software; you can redistribute it and/or modify
2301 + *   it under the terms of the GNU General Public License as published by
2302 + *   the Free Software Foundation; version 2 of the License
2303 + *
2304 + *   This program is distributed in the hope that it will be useful,
2305 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2306 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2307 + *   GNU General Public License for more details.
2308 + *
2309 + *   You should have received a copy of the GNU General Public License
2310 + *   along with this program; if not, write to the Free Software
2311 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2312 + *
2313 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2314 + */
2315 +
2316 +#include <linux/module.h>
2317 +#include <linux/kernel.h>
2318 +#include <linux/types.h>
2319 +#include <linux/dma-mapping.h>
2320 +#include <linux/init.h>
2321 +#include <linux/skbuff.h>
2322 +#include <linux/etherdevice.h>
2323 +#include <linux/ethtool.h>
2324 +#include <linux/platform_device.h>
2325 +#include <linux/phy.h>
2326 +#include <linux/of_device.h>
2327 +#include <linux/clk.h>
2328 +#include <linux/of_net.h>
2329 +#include <linux/of_mdio.h>
2330 +
2331 +#include "ralink_soc_eth.h"
2332 +#include "mdio.h"
2333 +
2334 +static int fe_mdio_reset(struct mii_bus *bus)
2335 +{
2336 +       /* TODO */
2337 +       return 0;
2338 +}
2339 +
2340 +static void fe_phy_link_adjust(struct net_device *dev)
2341 +{
2342 +       struct fe_priv *priv = netdev_priv(dev);
2343 +       unsigned long flags;
2344 +       int i;
2345 +
2346 +       spin_lock_irqsave(&priv->phy->lock, flags);
2347 +       for (i = 0; i < 8; i++) {
2348 +               if (priv->phy->phy_node[i]) {
2349 +                       struct phy_device *phydev = priv->phy->phy[i];
2350 +                       int status_change = 0;
2351 +
2352 +                       if (phydev->link)
2353 +                               if (priv->phy->duplex[i] != phydev->duplex ||
2354 +                                               priv->phy->speed[i] != phydev->speed)
2355 +                                       status_change = 1;
2356 +
2357 +                       if (phydev->link != priv->link[i])
2358 +                               status_change = 1;
2359 +
2360 +                       switch (phydev->speed) {
2361 +                       case SPEED_1000:
2362 +                       case SPEED_100:
2363 +                       case SPEED_10:
2364 +                               priv->link[i] = phydev->link;
2365 +                               priv->phy->duplex[i] = phydev->duplex;
2366 +                               priv->phy->speed[i] = phydev->speed;
2367 +
2368 +                               if (status_change && priv->soc->mdio_adjust_link)
2369 +                                       priv->soc->mdio_adjust_link(priv, i);
2370 +                               break;
2371 +                       }
2372 +               }
2373 +       }
2374 +}
2375 +
2376 +int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
2377 +{
2378 +       const __be32 *_port = NULL;
2379 +       struct phy_device *phydev;
2380 +       int phy_mode, port;
2381 +
2382 +       _port = of_get_property(phy_node, "reg", NULL);
2383 +
2384 +       if (!_port || (be32_to_cpu(*_port) >= 0x20)) {
2385 +               pr_err("%s: invalid port id\n", phy_node->name);
2386 +               return -EINVAL;
2387 +       }
2388 +       port = be32_to_cpu(*_port);
2389 +       phy_mode = of_get_phy_mode(phy_node);
2390 +       if (phy_mode < 0) {
2391 +               dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
2392 +               priv->phy->phy_node[port] = NULL;
2393 +               return -EINVAL;
2394 +       }
2395 +
2396 +       phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
2397 +                               0, phy_mode);
2398 +       if (IS_ERR(phydev)) {
2399 +               dev_err(priv->device, "could not connect to PHY\n");
2400 +               priv->phy->phy_node[port] = NULL;
2401 +               return PTR_ERR(phydev);
2402 +       }
2403 +
2404 +       phydev->supported &= PHY_GBIT_FEATURES;
2405 +       phydev->advertising = phydev->supported;
2406 +       phydev->no_auto_carrier_off = 1;
2407 +
2408 +       dev_info(priv->device,
2409 +                "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
2410 +                port, dev_name(&phydev->dev), phydev->phy_id,
2411 +                phydev->drv->name);
2412 +
2413 +       priv->phy->phy[port] = phydev;
2414 +       priv->link[port] = 0;
2415 +
2416 +       return 0;
2417 +}
2418 +
2419 +static void phy_init(struct fe_priv *priv, struct phy_device *phy)
2420 +{
2421 +       phy_attach(priv->netdev, dev_name(&phy->dev), PHY_INTERFACE_MODE_MII);
2422 +
2423 +       phy->autoneg = AUTONEG_ENABLE;
2424 +       phy->speed = 0;
2425 +       phy->duplex = 0;
2426 +       phy->supported &= PHY_BASIC_FEATURES;
2427 +       phy->advertising = phy->supported | ADVERTISED_Autoneg;
2428 +
2429 +       phy_start_aneg(phy);
2430 +}
2431 +
2432 +static int fe_phy_connect(struct fe_priv *priv)
2433 +{
2434 +       int i;
2435 +
2436 +       for (i = 0; i < 8; i++) {
2437 +               if (priv->phy->phy_node[i]) {
2438 +                       if (!priv->phy_dev) {
2439 +                               priv->phy_dev = priv->phy->phy[i];
2440 +                               priv->phy_flags = FE_PHY_FLAG_PORT;
2441 +                       }
2442 +               } else if (priv->mii_bus && priv->mii_bus->phy_map[i]) {
2443 +                       phy_init(priv, priv->mii_bus->phy_map[i]);
2444 +                       if (!priv->phy_dev) {
2445 +                               priv->phy_dev = priv->mii_bus->phy_map[i];
2446 +                               priv->phy_flags = FE_PHY_FLAG_ATTACH;
2447 +                       }
2448 +               }
2449 +       }
2450 +
2451 +       return 0;
2452 +}
2453 +
2454 +static void fe_phy_disconnect(struct fe_priv *priv)
2455 +{
2456 +       unsigned long flags;
2457 +       int i;
2458 +
2459 +       for (i = 0; i < 8; i++)
2460 +               if (priv->phy->phy_fixed[i]) {
2461 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2462 +                       priv->link[i] = 0;
2463 +                       if (priv->soc->mdio_adjust_link)
2464 +                               priv->soc->mdio_adjust_link(priv, i);
2465 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2466 +               } else if (priv->phy->phy[i]) {
2467 +                       phy_disconnect(priv->phy->phy[i]);
2468 +               } else if (priv->mii_bus && priv->mii_bus->phy_map[i]) {
2469 +                       phy_detach(priv->mii_bus->phy_map[i]);
2470 +               }
2471 +}
2472 +
2473 +static void fe_phy_start(struct fe_priv *priv)
2474 +{
2475 +       unsigned long flags;
2476 +       int i;
2477 +
2478 +       for (i = 0; i < 8; i++) {
2479 +               if (priv->phy->phy_fixed[i]) {
2480 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2481 +                       priv->link[i] = 1;
2482 +                       if (priv->soc->mdio_adjust_link)
2483 +                               priv->soc->mdio_adjust_link(priv, i);
2484 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2485 +               } else if (priv->phy->phy[i]) {
2486 +                       phy_start(priv->phy->phy[i]);
2487 +               }
2488 +       }
2489 +}
2490 +
2491 +static void fe_phy_stop(struct fe_priv *priv)
2492 +{
2493 +       unsigned long flags;
2494 +       int i;
2495 +
2496 +       for (i = 0; i < 8; i++)
2497 +               if (priv->phy->phy_fixed[i]) {
2498 +                       spin_lock_irqsave(&priv->phy->lock, flags);
2499 +                       priv->link[i] = 0;
2500 +                       if (priv->soc->mdio_adjust_link)
2501 +                               priv->soc->mdio_adjust_link(priv, i);
2502 +                       spin_unlock_irqrestore(&priv->phy->lock, flags);
2503 +               } else if (priv->phy->phy[i]) {
2504 +                       phy_stop(priv->phy->phy[i]);
2505 +               }
2506 +}
2507 +
2508 +static struct fe_phy phy_ralink = {
2509 +       .connect = fe_phy_connect,
2510 +       .disconnect = fe_phy_disconnect,
2511 +       .start = fe_phy_start,
2512 +       .stop = fe_phy_stop,
2513 +};
2514 +
2515 +int fe_mdio_init(struct fe_priv *priv)
2516 +{
2517 +       struct device_node *mii_np;
2518 +       int err;
2519 +
2520 +       if (!priv->soc->mdio_read || !priv->soc->mdio_write)
2521 +               return 0;
2522 +
2523 +       spin_lock_init(&phy_ralink.lock);
2524 +       priv->phy = &phy_ralink;
2525 +
2526 +       mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
2527 +       if (!mii_np) {
2528 +               dev_err(priv->device, "no %s child node found", "mdio-bus");
2529 +               return -ENODEV;
2530 +       }
2531 +
2532 +       if (!of_device_is_available(mii_np)) {
2533 +               err = 0;
2534 +               goto err_put_node;
2535 +       }
2536 +
2537 +       priv->mii_bus = mdiobus_alloc();
2538 +       if (priv->mii_bus == NULL) {
2539 +               err = -ENOMEM;
2540 +               goto err_put_node;
2541 +       }
2542 +
2543 +       priv->mii_bus->name = "mdio";
2544 +       priv->mii_bus->read = priv->soc->mdio_read;
2545 +       priv->mii_bus->write = priv->soc->mdio_write;
2546 +       priv->mii_bus->reset = fe_mdio_reset;
2547 +       priv->mii_bus->priv = priv;
2548 +       priv->mii_bus->parent = priv->device;
2549 +
2550 +       snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
2551 +       err = of_mdiobus_register(priv->mii_bus, mii_np);
2552 +       if (err)
2553 +               goto err_free_bus;
2554 +
2555 +       return 0;
2556 +
2557 +err_free_bus:
2558 +       kfree(priv->mii_bus);
2559 +err_put_node:
2560 +       of_node_put(mii_np);
2561 +       priv->mii_bus = NULL;
2562 +       return err;
2563 +}
2564 +
2565 +void fe_mdio_cleanup(struct fe_priv *priv)
2566 +{
2567 +       if (!priv->mii_bus)
2568 +               return;
2569 +
2570 +       mdiobus_unregister(priv->mii_bus);
2571 +       of_node_put(priv->mii_bus->dev.of_node);
2572 +       kfree(priv->mii_bus);
2573 +}
2574 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio.h
2575 ===================================================================
2576 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2577 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio.h    2014-10-29 20:25:55.433357519 +0100
2578 @@ -0,0 +1,29 @@
2579 +/*
2580 + *   This program is free software; you can redistribute it and/or modify
2581 + *   it under the terms of the GNU General Public License as published by
2582 + *   the Free Software Foundation; version 2 of the License
2583 + *
2584 + *   This program is distributed in the hope that it will be useful,
2585 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2586 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2587 + *   GNU General Public License for more details.
2588 + *
2589 + *   You should have received a copy of the GNU General Public License
2590 + *   along with this program; if not, write to the Free Software
2591 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2592 + *
2593 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2594 + */
2595 +
2596 +#ifndef _RALINK_MDIO_H__
2597 +#define _RALINK_MDIO_H__
2598 +
2599 +#ifdef CONFIG_NET_RALINK_MDIO
2600 +extern int fe_mdio_init(struct fe_priv *priv);
2601 +extern void fe_mdio_cleanup(struct fe_priv *priv);
2602 +extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
2603 +#else
2604 +static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
2605 +static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
2606 +#endif
2607 +#endif
2608 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.c
2609 ===================================================================
2610 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2611 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.c     2014-10-29 20:25:55.433357519 +0100
2612 @@ -0,0 +1,232 @@
2613 +/*
2614 + *   This program is free software; you can redistribute it and/or modify
2615 + *   it under the terms of the GNU General Public License as published by
2616 + *   the Free Software Foundation; version 2 of the License
2617 + *
2618 + *   This program is distributed in the hope that it will be useful,
2619 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2620 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2621 + *   GNU General Public License for more details.
2622 + *
2623 + *   You should have received a copy of the GNU General Public License
2624 + *   along with this program; if not, write to the Free Software
2625 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2626 + *
2627 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2628 + */
2629 +
2630 +#include <linux/module.h>
2631 +#include <linux/kernel.h>
2632 +#include <linux/types.h>
2633 +#include <linux/dma-mapping.h>
2634 +#include <linux/init.h>
2635 +#include <linux/skbuff.h>
2636 +#include <linux/etherdevice.h>
2637 +#include <linux/ethtool.h>
2638 +#include <linux/platform_device.h>
2639 +#include <linux/phy.h>
2640 +#include <linux/of_device.h>
2641 +#include <linux/clk.h>
2642 +#include <linux/of_net.h>
2643 +#include <linux/of_mdio.h>
2644 +
2645 +#include "ralink_soc_eth.h"
2646 +#include "mdio_rt2880.h"
2647 +#include "mdio.h"
2648 +
2649 +#define FE_MDIO_RETRY  1000
2650 +
2651 +static unsigned char *rt2880_speed_str(struct fe_priv *priv)
2652 +{
2653 +       switch (priv->phy->speed[0]) {
2654 +       case SPEED_1000:
2655 +               return "1000";
2656 +       case SPEED_100:
2657 +               return "100";
2658 +       case SPEED_10:
2659 +               return "10";
2660 +       }
2661 +
2662 +       return "?";
2663 +}
2664 +
2665 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
2666 +{
2667 +       u32 mdio_cfg;
2668 +
2669 +       if (!priv->link[0]) {
2670 +               netif_carrier_off(priv->netdev);
2671 +               netdev_info(priv->netdev, "link down\n");
2672 +               return;
2673 +       }
2674 +
2675 +       mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
2676 +                  FE_MDIO_CFG_RX_CLK_SKEW_200 |
2677 +                  FE_MDIO_CFG_GP1_FRC_EN;
2678 +
2679 +       if (priv->phy->duplex[0] == DUPLEX_FULL)
2680 +               mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
2681 +
2682 +       if (priv->phy->tx_fc[0])
2683 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
2684 +
2685 +       if (priv->phy->rx_fc[0])
2686 +               mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
2687 +
2688 +       switch (priv->phy->speed[0]) {
2689 +       case SPEED_10:
2690 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
2691 +               break;
2692 +       case SPEED_100:
2693 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
2694 +               break;
2695 +       case SPEED_1000:
2696 +               mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
2697 +               break;
2698 +       default:
2699 +               BUG();
2700 +       }
2701 +
2702 +       fe_w32(mdio_cfg, FE_MDIO_CFG);
2703 +
2704 +       netif_carrier_on(priv->netdev);
2705 +       netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
2706 +                   rt2880_speed_str(priv),
2707 +                   (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
2708 +}
2709 +
2710 +static int rt2880_mdio_wait_ready(struct fe_priv *priv)
2711 +{
2712 +       int retries;
2713 +
2714 +       retries = FE_MDIO_RETRY;
2715 +       while (1) {
2716 +               u32 t;
2717 +
2718 +               t = fe_r32(FE_MDIO_ACCESS);
2719 +               if ((t & (0x1 << 31)) == 0)
2720 +                       return 0;
2721 +
2722 +               if (retries-- == 0)
2723 +                       break;
2724 +
2725 +               udelay(1);
2726 +       }
2727 +
2728 +       dev_err(priv->device, "MDIO operation timed out\n");
2729 +       return -ETIMEDOUT;
2730 +}
2731 +
2732 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
2733 +{
2734 +       struct fe_priv *priv = bus->priv;
2735 +       int err;
2736 +       u32 t;
2737 +
2738 +       err = rt2880_mdio_wait_ready(priv);
2739 +       if (err)
2740 +               return 0xffff;
2741 +
2742 +       t = (phy_addr << 24) | (phy_reg << 16);
2743 +       fe_w32(t, FE_MDIO_ACCESS);
2744 +       t |= (1 << 31);
2745 +       fe_w32(t, FE_MDIO_ACCESS);
2746 +
2747 +       err = rt2880_mdio_wait_ready(priv);
2748 +       if (err)
2749 +               return 0xffff;
2750 +
2751 +       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2752 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2753 +
2754 +       return fe_r32(FE_MDIO_ACCESS) & 0xffff;
2755 +}
2756 +
2757 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
2758 +{
2759 +       struct fe_priv *priv = bus->priv;
2760 +       int err;
2761 +       u32 t;
2762 +
2763 +       pr_debug("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
2764 +               phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
2765 +
2766 +       err = rt2880_mdio_wait_ready(priv);
2767 +       if (err)
2768 +               return err;
2769 +
2770 +       t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
2771 +       fe_w32(t, FE_MDIO_ACCESS);
2772 +       t |= (1 << 31);
2773 +       fe_w32(t, FE_MDIO_ACCESS);
2774 +
2775 +       return rt2880_mdio_wait_ready(priv);
2776 +}
2777 +
2778 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
2779 +{
2780 +       const __be32 *id = of_get_property(np, "reg", NULL);
2781 +       const __be32 *link;
2782 +       int size;
2783 +       int phy_mode;
2784 +
2785 +       if (!id || (be32_to_cpu(*id) != 0)) {
2786 +               pr_err("%s: invalid port id\n", np->name);
2787 +               return;
2788 +       }
2789 +
2790 +       priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
2791 +       if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
2792 +               pr_err("%s: invalid fixed link property\n", np->name);
2793 +               priv->phy->phy_fixed[0] = NULL;
2794 +               return;
2795 +       }
2796 +
2797 +       phy_mode = of_get_phy_mode(np);
2798 +       switch (phy_mode) {
2799 +       case PHY_INTERFACE_MODE_RGMII:
2800 +               break;
2801 +       case PHY_INTERFACE_MODE_MII:
2802 +               break;
2803 +       case PHY_INTERFACE_MODE_RMII:
2804 +               break;
2805 +       default:
2806 +               if (!priv->phy->phy_fixed[0])
2807 +                       dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
2808 +               break;
2809 +       }
2810 +
2811 +       priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
2812 +       if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
2813 +               return;
2814 +
2815 +       if (priv->phy->phy_fixed[0]) {
2816 +               link = priv->phy->phy_fixed[0];
2817 +               priv->phy->speed[0] = be32_to_cpup(link++);
2818 +               priv->phy->duplex[0] = be32_to_cpup(link++);
2819 +               priv->phy->tx_fc[0] = be32_to_cpup(link++);
2820 +               priv->phy->rx_fc[0] = be32_to_cpup(link++);
2821 +
2822 +               priv->link[0] = 1;
2823 +               switch (priv->phy->speed[0]) {
2824 +               case SPEED_10:
2825 +                       break;
2826 +               case SPEED_100:
2827 +                       break;
2828 +               case SPEED_1000:
2829 +                       break;
2830 +               default:
2831 +                       dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
2832 +                       priv->phy->phy_fixed[0] = 0;
2833 +                       return;
2834 +               }
2835 +               dev_info(priv->device, "using fixed link parameters\n");
2836 +               rt2880_mdio_link_adjust(priv, 0);
2837 +               return;
2838 +       }
2839 +       if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
2840 +               fe_connect_phy_node(priv, priv->phy->phy_node[0]);
2841 +       }
2842 +
2843 +       return;
2844 +}
2845 Index: linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.h
2846 ===================================================================
2847 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2848 +++ linux-3.14.18/drivers/net/ethernet/ralink/mdio_rt2880.h     2014-10-29 20:25:55.433357519 +0100
2849 @@ -0,0 +1,26 @@
2850 +/*
2851 + *   This program is free software; you can redistribute it and/or modify
2852 + *   it under the terms of the GNU General Public License as published by
2853 + *   the Free Software Foundation; version 2 of the License
2854 + *
2855 + *   This program is distributed in the hope that it will be useful,
2856 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
2857 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2858 + *   GNU General Public License for more details.
2859 + *
2860 + *   You should have received a copy of the GNU General Public License
2861 + *   along with this program; if not, write to the Free Software
2862 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2863 + *
2864 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
2865 + */
2866 +
2867 +#ifndef _RALINK_MDIO_RT2880_H__
2868 +#define _RALINK_MDIO_RT2880_H__
2869 +
2870 +void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
2871 +int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
2872 +int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
2873 +void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
2874 +
2875 +#endif
2876 Index: linux-3.14.18/drivers/net/ethernet/ralink/mt7530.c
2877 ===================================================================
2878 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
2879 +++ linux-3.14.18/drivers/net/ethernet/ralink/mt7530.c  2014-10-30 09:37:26.847089658 +0100
2880 @@ -0,0 +1,588 @@
2881 +/*
2882 + * This program is free software; you can redistribute it and/or
2883 + * modify it under the terms of the GNU General Public License
2884 + * as published by the Free Software Foundation; either version 2
2885 + * of the License, or (at your option) any later version.
2886 + *
2887 + * This program is distributed in the hope that it will be useful,
2888 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2889 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
2890 + * GNU General Public License for more details.
2891 + *
2892 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
2893 + */
2894 +
2895 +#include <linux/if.h>
2896 +#include <linux/module.h>
2897 +#include <linux/init.h>
2898 +#include <linux/list.h>
2899 +#include <linux/if_ether.h>
2900 +#include <linux/skbuff.h>
2901 +#include <linux/netdevice.h>
2902 +#include <linux/netlink.h>
2903 +#include <linux/bitops.h>
2904 +#include <net/genetlink.h>
2905 +#include <linux/switch.h>
2906 +#include <linux/delay.h>
2907 +#include <linux/phy.h>
2908 +#include <linux/netdevice.h>
2909 +#include <linux/etherdevice.h>
2910 +#include <linux/lockdep.h>
2911 +#include <linux/workqueue.h>
2912 +#include <linux/of_device.h>
2913 +
2914 +#include "mt7530.h"
2915 +
2916 +#define MT7530_CPU_PORT                6
2917 +#define MT7530_NUM_PORTS       8
2918 +#define MT7530_NUM_VLANS       16
2919 +#define MT7530_MAX_VID         4095
2920 +#define MT7530_MIN_VID         0
2921 +
2922 +/* registers */
2923 +#define REG_ESW_VLAN_VTCR              0x90
2924 +#define REG_ESW_VLAN_VAWD1             0x94
2925 +#define REG_ESW_VLAN_VAWD2             0x98
2926 +#define REG_ESW_VLAN_VTIM(x)   (0x100 + 4 * ((x) / 2))
2927 +
2928 +#define REG_ESW_VLAN_VAWD1_IVL_MAC     BIT(30)
2929 +#define REG_ESW_VLAN_VAWD1_VTAG_EN     BIT(28)
2930 +#define REG_ESW_VLAN_VAWD1_VALID       BIT(0)
2931 +
2932 +/* vlan egress mode */
2933 +enum {
2934 +       ETAG_CTRL_UNTAG = 0,
2935 +       ETAG_CTRL_TAG   = 2,
2936 +       ETAG_CTRL_SWAP  = 1,
2937 +       ETAG_CTRL_STACK = 3,
2938 +};
2939 +
2940 +#define REG_ESW_PORT_PCR(x)    (0x2004 | ((x) << 8))
2941 +#define REG_ESW_PORT_PVC(x)    (0x2010 | ((x) << 8))
2942 +#define REG_ESW_PORT_PPBV1(x)  (0x2014 | ((x) << 8))
2943 +
2944 +#define REG_HWTRAP             0x7804
2945 +
2946 +enum {
2947 +       /* Global attributes. */
2948 +       MT7530_ATTR_ENABLE_VLAN,
2949 +};
2950 +
2951 +struct mt7530_port_entry {
2952 +       u16     pvid;
2953 +};
2954 +
2955 +struct mt7530_vlan_entry {
2956 +       u16     vid;
2957 +       u8      member;
2958 +       u8      etags;
2959 +};
2960 +
2961 +struct mt7530_priv {
2962 +       void __iomem            *base;
2963 +       struct mii_bus          *bus;
2964 +       struct switch_dev       swdev;
2965 +
2966 +       bool                    global_vlan_enable;
2967 +       struct mt7530_vlan_entry        vlan_entries[MT7530_NUM_VLANS];
2968 +       struct mt7530_port_entry        port_entries[MT7530_NUM_PORTS];
2969 +};
2970 +
2971 +struct mt7530_mapping {
2972 +       char    *name;
2973 +       u16     pvids[MT7530_NUM_PORTS];
2974 +       u8      members[MT7530_NUM_VLANS];
2975 +       u8      etags[MT7530_NUM_VLANS];
2976 +       u16     vids[MT7530_NUM_VLANS];
2977 +} mt7530_defaults[] = {
2978 +       {
2979 +               .name = "llllw",
2980 +               .pvids = { 1, 1, 1, 1, 2, 1, 1 },
2981 +               .members = { 0, 0x6f, 0x50 },
2982 +               .etags = { 0, 0x40, 0x40 },
2983 +               .vids = { 0, 1, 2 },
2984 +       }, {
2985 +               .name = "wllll",
2986 +               .pvids = { 2, 1, 1, 1, 1, 1, 1 },
2987 +               .members = { 0, 0x7e, 0x41 },
2988 +               .etags = { 0, 0x40, 0x40 },
2989 +               .vids = { 0, 1, 2 },
2990 +       },
2991 +};
2992 +
2993 +struct mt7530_mapping*
2994 +mt7530_find_mapping(struct device_node *np)
2995 +{
2996 +       const char *map;
2997 +       int i;
2998 +
2999 +       if (of_property_read_string(np, "ralink,port-map", &map))
3000 +               return NULL;
3001 +
3002 +       for (i = 0; i < ARRAY_SIZE(mt7530_defaults); i++)
3003 +               if (!strcmp(map, mt7530_defaults[i].name))
3004 +                       return &mt7530_defaults[i];
3005 +
3006 +       return NULL;
3007 +}
3008 +
3009 +static void
3010 +mt7530_apply_mapping(struct mt7530_priv *mt7530, struct mt7530_mapping *map)
3011 +{
3012 +       int i = 0;
3013 +
3014 +       for (i = 0; i < MT7530_NUM_PORTS; i++)
3015 +               mt7530->port_entries[i].pvid = map->pvids[i];
3016 +
3017 +       for (i = 0; i < MT7530_NUM_VLANS; i++) {
3018 +               mt7530->vlan_entries[i].member = map->members[i];
3019 +               mt7530->vlan_entries[i].etags = map->etags[i];
3020 +               mt7530->vlan_entries[i].vid = map->vids[i];
3021 +       }
3022 +}
3023 +
3024 +static int
3025 +mt7530_reset_switch(struct switch_dev *dev)
3026 +{
3027 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3028 +       int i;
3029 +
3030 +       memset(priv->port_entries, 0, sizeof(priv->port_entries));
3031 +       memset(priv->vlan_entries, 0, sizeof(priv->vlan_entries));
3032 +
3033 +       /* set default vid of each vlan to the same number of vlan, so the vid
3034 +        * won't need be set explicitly.
3035 +        */
3036 +       for (i = 0; i < MT7530_NUM_VLANS; i++) {
3037 +               priv->vlan_entries[i].vid = i;
3038 +       }
3039 +
3040 +       return 0;
3041 +}
3042 +
3043 +static int
3044 +mt7530_get_vlan_enable(struct switch_dev *dev,
3045 +                          const struct switch_attr *attr,
3046 +                          struct switch_val *val)
3047 +{
3048 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3049 +
3050 +       val->value.i = priv->global_vlan_enable;
3051 +
3052 +       return 0;
3053 +}
3054 +
3055 +static int
3056 +mt7530_set_vlan_enable(struct switch_dev *dev,
3057 +                          const struct switch_attr *attr,
3058 +                          struct switch_val *val)
3059 +{
3060 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3061 +
3062 +       priv->global_vlan_enable = val->value.i != 0;
3063 +
3064 +       return 0;
3065 +}
3066 +
3067 +static u32
3068 +mt7530_r32(struct mt7530_priv *priv, u32 reg)
3069 +{
3070 +       u32 val;
3071 +       if (priv->bus) {
3072 +               u16 high, low;
3073 +
3074 +               mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3075 +               low = mdiobus_read(priv->bus, 0x1f, (reg >> 2) & 0xf);
3076 +               high = mdiobus_read(priv->bus, 0x1f, 0x10);
3077 +
3078 +               return (high << 16) | (low & 0xffff);
3079 +       }
3080 +
3081 +       val = ioread32(priv->base + reg);
3082 +       pr_debug("MT7530 MDIO Read [%04x]=%08x\n", reg, val);
3083 +
3084 +       return val;
3085 +}
3086 +
3087 +static void
3088 +mt7530_w32(struct mt7530_priv *priv, u32 reg, u32 val)
3089 +{
3090 +       if (priv->bus) {
3091 +               mdiobus_write(priv->bus, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
3092 +               mdiobus_write(priv->bus, 0x1f, (reg >> 2) & 0xf,  val & 0xffff);
3093 +               mdiobus_write(priv->bus, 0x1f, 0x10, val >> 16);
3094 +               return;
3095 +       }
3096 +
3097 +       pr_debug("MT7530 MDIO Write[%04x]=%08x\n", reg, val);
3098 +       iowrite32(val, priv->base + reg);
3099 +}
3100 +
3101 +static void
3102 +mt7530_vtcr(struct mt7530_priv *priv, u32 cmd, u32 val)
3103 +{
3104 +       int i;
3105 +
3106 +       mt7530_w32(priv, REG_ESW_VLAN_VTCR, BIT(31) | (cmd << 12) | val);
3107 +
3108 +       for (i = 0; i < 20; i++) {
3109 +               u32 val = mt7530_r32(priv, REG_ESW_VLAN_VTCR);
3110 +
3111 +               if ((val & BIT(31)) == 0)
3112 +                       break;
3113 +
3114 +               udelay(1000);
3115 +       }
3116 +       if (i == 20)
3117 +               printk("mt7530: vtcr timeout\n");
3118 +}
3119 +
3120 +static int
3121 +mt7530_get_port_pvid(struct switch_dev *dev, int port, int *val)
3122 +{
3123 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3124 +
3125 +       if (port >= MT7530_NUM_PORTS)
3126 +               return -EINVAL;
3127 +
3128 +       *val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(port));
3129 +       *val &= 0xfff;
3130 +
3131 +       return 0;
3132 +}
3133 +
3134 +static int
3135 +mt7530_set_port_pvid(struct switch_dev *dev, int port, int pvid)
3136 +{
3137 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3138 +
3139 +       if (port >= MT7530_NUM_PORTS)
3140 +               return -EINVAL;
3141 +
3142 +       if (pvid < MT7530_MIN_VID || pvid > MT7530_MAX_VID)
3143 +               return -EINVAL;
3144 +
3145 +       priv->port_entries[port].pvid = pvid;
3146 +
3147 +       return 0;
3148 +}
3149 +
3150 +static int
3151 +mt7530_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3152 +{
3153 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3154 +       u32 member;
3155 +       u32 etags;
3156 +       int i;
3157 +
3158 +       val->len = 0;
3159 +
3160 +       if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS)
3161 +               return -EINVAL;
3162 +
3163 +       mt7530_vtcr(priv, 0, val->port_vlan);
3164 +
3165 +       member = mt7530_r32(priv, REG_ESW_VLAN_VAWD1);
3166 +       member >>= 16;
3167 +       member &= 0xff;
3168 +
3169 +       etags = mt7530_r32(priv, REG_ESW_VLAN_VAWD2);
3170 +
3171 +       for (i = 0; i < MT7530_NUM_PORTS; i++) {
3172 +               struct switch_port *p;
3173 +               int etag;
3174 +
3175 +               if (!(member & BIT(i)))
3176 +                       continue;
3177 +
3178 +               p = &val->value.ports[val->len++];
3179 +               p->id = i;
3180 +
3181 +               etag = (etags >> (i * 2)) & 0x3;
3182 +
3183 +               if (etag == ETAG_CTRL_TAG)
3184 +                       p->flags |= BIT(SWITCH_PORT_FLAG_TAGGED);
3185 +               else if (etag != ETAG_CTRL_UNTAG)
3186 +                       printk("vlan egress tag control neither untag nor tag.\n");
3187 +       }
3188 +
3189 +       return 0;
3190 +}
3191 +
3192 +static int
3193 +mt7530_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
3194 +{
3195 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3196 +       u8 member = 0;
3197 +       u8 etags = 0;
3198 +       int i;
3199 +
3200 +       if (val->port_vlan < 0 || val->port_vlan >= MT7530_NUM_VLANS ||
3201 +                       val->len > MT7530_NUM_PORTS)
3202 +               return -EINVAL;
3203 +
3204 +       for (i = 0; i < val->len; i++) {
3205 +               struct switch_port *p = &val->value.ports[i];
3206 +
3207 +               if (p->id >= MT7530_NUM_PORTS)
3208 +                       return -EINVAL;
3209 +
3210 +               member |= BIT(p->id);
3211 +
3212 +               if (p->flags & BIT(SWITCH_PORT_FLAG_TAGGED))
3213 +                       etags |= BIT(p->id);
3214 +       }
3215 +       priv->vlan_entries[val->port_vlan].member = member;
3216 +       priv->vlan_entries[val->port_vlan].etags = etags;
3217 +
3218 +       return 0;
3219 +}
3220 +
3221 +static int
3222 +mt7530_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
3223 +               struct switch_val *val)
3224 +{
3225 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3226 +       int vlan;
3227 +       u16 vid;
3228 +
3229 +       vlan = val->port_vlan;
3230 +       vid = (u16)val->value.i;
3231 +
3232 +       if (vlan < 0 || vlan >= MT7530_NUM_VLANS)
3233 +               return -EINVAL;
3234 +
3235 +       if (vid < MT7530_MIN_VID || vid > MT7530_MAX_VID)
3236 +               return -EINVAL;
3237 +
3238 +       priv->vlan_entries[vlan].vid = vid;
3239 +       return 0;
3240 +}
3241 +
3242 +static int
3243 +mt7530_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
3244 +               struct switch_val *val)
3245 +{
3246 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3247 +       u32 vid;
3248 +       int vlan;
3249 +
3250 +       vlan = val->port_vlan;
3251 +
3252 +       vid = mt7530_r32(priv, REG_ESW_VLAN_VTIM(vlan));
3253 +       if (vlan & 1)
3254 +               vid = vid >> 12;
3255 +       vid &= 0xfff;
3256 +
3257 +       val->value.i = vid;
3258 +       return 0;
3259 +}
3260 +
3261 +static int
3262 +mt7530_apply_config(struct switch_dev *dev)
3263 +{
3264 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3265 +       int i, j;
3266 +
3267 +       if (!priv->global_vlan_enable) {
3268 +               for (i = 0; i < MT7530_NUM_PORTS; i++)
3269 +                       mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0000);
3270 +
3271 +               for (i = 0; i < MT7530_NUM_PORTS; i++)
3272 +                       mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x810000c0);
3273 +
3274 +               return 0;
3275 +       }
3276 +
3277 +       /* set all ports as security mode */
3278 +       for (i = 0; i < MT7530_NUM_PORTS; i++)
3279 +               mt7530_w32(priv, REG_ESW_PORT_PCR(i), 0x00ff0003);
3280 +
3281 +       /* set all ports as user port */
3282 +       for (i = 0; i < MT7530_NUM_PORTS; i++)
3283 +               mt7530_w32(priv, REG_ESW_PORT_PVC(i), 0x81000000);
3284 +
3285 +       for (i = 0; i < MT7530_NUM_VLANS; i++) {
3286 +               u16 vid = priv->vlan_entries[i].vid;
3287 +               u8 member = priv->vlan_entries[i].member;
3288 +               u8 etags = priv->vlan_entries[i].etags;
3289 +               u32 val;
3290 +
3291 +               /* vid of vlan */
3292 +               val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
3293 +               if (i % 2 == 0) {
3294 +                       val &= 0xfff000;
3295 +                       val |= vid;
3296 +               } else {
3297 +                       val &= 0xfff;
3298 +                       val |= (vid << 12);
3299 +               }
3300 +               mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
3301 +
3302 +               /* vlan port membership */
3303 +               if (member)
3304 +                       mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
3305 +                               REG_ESW_VLAN_VAWD1_VTAG_EN | (member << 16) |
3306 +                               REG_ESW_VLAN_VAWD1_VALID);
3307 +               else
3308 +                       mt7530_w32(priv, REG_ESW_VLAN_VAWD1, 0);
3309 +
3310 +               /* egress mode */
3311 +               val = 0;
3312 +               for (j = 0; j < MT7530_NUM_PORTS; j++) {
3313 +                       if (etags & BIT(j))
3314 +                               val |= ETAG_CTRL_TAG << (j * 2);
3315 +                       else
3316 +                               val |= ETAG_CTRL_UNTAG << (j * 2);
3317 +               }
3318 +               mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
3319 +
3320 +               /* write to vlan table */
3321 +               mt7530_vtcr(priv, 1, i);
3322 +       }
3323 +
3324 +       /* Port Default PVID */
3325 +       for (i = 0; i < MT7530_NUM_PORTS; i++) {
3326 +               u32 val;
3327 +               val = mt7530_r32(priv, REG_ESW_PORT_PPBV1(i));
3328 +               val &= ~0xfff;
3329 +               val |= priv->port_entries[i].pvid;
3330 +               mt7530_w32(priv, REG_ESW_PORT_PPBV1(i), val);
3331 +       }
3332 +
3333 +       return 0;
3334 +}
3335 +
3336 +static int
3337 +mt7530_get_port_link(struct switch_dev *dev,  int port,
3338 +                       struct switch_port_link *link)
3339 +{
3340 +       struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
3341 +       u32 speed, pmsr;
3342 +
3343 +       if (port < 0 || port >= MT7530_NUM_PORTS)
3344 +               return -EINVAL;
3345 +
3346 +       pmsr = mt7530_r32(priv, 0x3008 + (0x100 * port));
3347 +
3348 +       link->link = pmsr & 1;
3349 +       link->duplex = (pmsr >> 1) & 1;
3350 +       speed = (pmsr >> 2) & 3;
3351 +
3352 +       switch (speed) {
3353 +       case 0:
3354 +               link->speed = SWITCH_PORT_SPEED_10;
3355 +               break;
3356 +       case 1:
3357 +               link->speed = SWITCH_PORT_SPEED_100;
3358 +               break;
3359 +       case 2:
3360 +       case 3: /* forced gige speed can be 2 or 3 */
3361 +               link->speed = SWITCH_PORT_SPEED_1000;
3362 +               break;
3363 +       default:
3364 +               link->speed = SWITCH_PORT_SPEED_UNKNOWN;
3365 +               break;
3366 +       }
3367 +
3368 +       return 0;
3369 +}
3370 +
3371 +static const struct switch_attr mt7530_global[] = {
3372 +       {
3373 +               .type = SWITCH_TYPE_INT,
3374 +               .name = "enable_vlan",
3375 +               .description = "VLAN mode (1:enabled)",
3376 +               .max = 1,
3377 +               .id = MT7530_ATTR_ENABLE_VLAN,
3378 +               .get = mt7530_get_vlan_enable,
3379 +               .set = mt7530_set_vlan_enable,
3380 +       },
3381 +};
3382 +
3383 +static const struct switch_attr mt7530_port[] = {
3384 +};
3385 +
3386 +static const struct switch_attr mt7530_vlan[] = {
3387 +       {
3388 +               .type = SWITCH_TYPE_INT,
3389 +               .name = "vid",
3390 +               .description = "VLAN ID (0-4094)",
3391 +               .set = mt7530_set_vid,
3392 +               .get = mt7530_get_vid,
3393 +               .max = 4094,
3394 +       },
3395 +};
3396 +
3397 +static const struct switch_dev_ops mt7530_ops = {
3398 +       .attr_global = {
3399 +               .attr = mt7530_global,
3400 +               .n_attr = ARRAY_SIZE(mt7530_global),
3401 +       },
3402 +       .attr_port = {
3403 +               .attr = mt7530_port,
3404 +               .n_attr = ARRAY_SIZE(mt7530_port),
3405 +       },
3406 +       .attr_vlan = {
3407 +               .attr = mt7530_vlan,
3408 +               .n_attr = ARRAY_SIZE(mt7530_vlan),
3409 +       },
3410 +       .get_vlan_ports = mt7530_get_vlan_ports,
3411 +       .set_vlan_ports = mt7530_set_vlan_ports,
3412 +       .get_port_pvid = mt7530_get_port_pvid,
3413 +       .set_port_pvid = mt7530_set_port_pvid,
3414 +       .get_port_link = mt7530_get_port_link,
3415 +       .apply_config = mt7530_apply_config,
3416 +       .reset_switch = mt7530_reset_switch,
3417 +};
3418 +
3419 +int
3420 +mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan)
3421 +{
3422 +       struct switch_dev *swdev;
3423 +       struct mt7530_priv *mt7530;
3424 +       struct mt7530_mapping *map;
3425 +       int ret;
3426 +
3427 +       mt7530 = devm_kzalloc(dev, sizeof(struct mt7530_priv), GFP_KERNEL);
3428 +       if (!mt7530)
3429 +               return -ENOMEM;
3430 +
3431 +       mt7530->base = base;
3432 +       mt7530->bus = bus;
3433 +       mt7530->global_vlan_enable = vlan;
3434 +
3435 +       swdev = &mt7530->swdev;
3436 +       if (bus) {
3437 +               swdev->alias = "mt7530";
3438 +               swdev->name = "mt7530";
3439 +       } else {
3440 +               swdev->alias = "mt7620";
3441 +               swdev->name = "mt7620";
3442 +       }
3443 +       swdev->cpu_port = MT7530_CPU_PORT;
3444 +       swdev->ports = MT7530_NUM_PORTS;
3445 +       swdev->vlans = MT7530_NUM_VLANS;
3446 +       swdev->ops = &mt7530_ops;
3447 +
3448 +       ret = register_switch(swdev, NULL);
3449 +       if (ret) {
3450 +               dev_err(dev, "failed to register mt7530\n");
3451 +               return ret;
3452 +       }
3453 +
3454 +
3455 +       map = mt7530_find_mapping(dev->of_node);
3456 +       if (map)
3457 +               mt7530_apply_mapping(mt7530, map);
3458 +       mt7530_apply_config(swdev);
3459 +
3460 +       /* magic vodoo */
3461 +       if (bus && mt7530_r32(mt7530, REG_HWTRAP) !=  0x1117edf) {
3462 +               dev_info(dev, "fixing up MHWTRAP register - bootloader probably played with it\n");
3463 +               mt7530_w32(mt7530, REG_HWTRAP, 0x1117edf);
3464 +       }
3465 +       dev_info(dev, "loaded %s driver\n", swdev->name);
3466 +
3467 +       return 0;
3468 +}
3469 Index: linux-3.14.18/drivers/net/ethernet/ralink/mt7530.h
3470 ===================================================================
3471 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
3472 +++ linux-3.14.18/drivers/net/ethernet/ralink/mt7530.h  2014-10-29 20:30:49.296185172 +0100
3473 @@ -0,0 +1,20 @@
3474 +/*
3475 + * This program is free software; you can redistribute it and/or
3476 + * modify it under the terms of the GNU General Public License
3477 + * as published by the Free Software Foundation; either version 2
3478 + * of the License, or (at your option) any later version.
3479 + *
3480 + * This program is distributed in the hope that it will be useful,
3481 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3482 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3483 + * GNU General Public License for more details.
3484 + *
3485 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
3486 + */
3487 +
3488 +#ifndef _MT7530_H__
3489 +#define _MT7530_H__
3490 +
3491 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
3492 +
3493 +#endif
3494 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.c
3495 ===================================================================
3496 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
3497 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.c  2014-10-30 07:59:41.679492638 +0100
3498 @@ -0,0 +1,1331 @@
3499 +/*
3500 + *   This program is free software; you can redistribute it and/or modify
3501 + *   it under the terms of the GNU General Public License as published by
3502 + *   the Free Software Foundation; version 2 of the License
3503 + *
3504 + *   This program is distributed in the hope that it will be useful,
3505 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
3506 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
3507 + *   GNU General Public License for more details.
3508 + *
3509 + *   You should have received a copy of the GNU General Public License
3510 + *   along with this program; if not, write to the Free Software
3511 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
3512 + *
3513 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
3514 + */
3515 +
3516 +#include <linux/module.h>
3517 +#include <linux/kernel.h>
3518 +#include <linux/types.h>
3519 +#include <linux/dma-mapping.h>
3520 +#include <linux/init.h>
3521 +#include <linux/skbuff.h>
3522 +#include <linux/etherdevice.h>
3523 +#include <linux/ethtool.h>
3524 +#include <linux/platform_device.h>
3525 +#include <linux/of_device.h>
3526 +#include <linux/clk.h>
3527 +#include <linux/of_net.h>
3528 +#include <linux/of_mdio.h>
3529 +#include <linux/if_vlan.h>
3530 +#include <linux/reset.h>
3531 +#include <linux/tcp.h>
3532 +#include <linux/io.h>
3533 +
3534 +#include <asm/mach-ralink/ralink_regs.h>
3535 +
3536 +#include "ralink_soc_eth.h"
3537 +#include "esw_rt3052.h"
3538 +#include "mdio.h"
3539 +#include "ralink_ethtool.h"
3540 +
3541 +#define TX_TIMEOUT             (2 * HZ)
3542 +#define        MAX_RX_LENGTH           1536
3543 +#define FE_RX_OFFSET           (NET_SKB_PAD + NET_IP_ALIGN)
3544 +#define FE_RX_HLEN             (FE_RX_OFFSET + VLAN_ETH_HLEN + VLAN_HLEN + \
3545 +               ETH_FCS_LEN)
3546 +#define DMA_DUMMY_DESC         0xffffffff
3547 +#define FE_DEFAULT_MSG_ENABLE    \
3548 +        (NETIF_MSG_DRV      | \
3549 +         NETIF_MSG_PROBE    | \
3550 +         NETIF_MSG_LINK     | \
3551 +         NETIF_MSG_TIMER    | \
3552 +         NETIF_MSG_IFDOWN   | \
3553 +         NETIF_MSG_IFUP     | \
3554 +         NETIF_MSG_RX_ERR   | \
3555 +         NETIF_MSG_TX_ERR)
3556 +
3557 +#define TX_DMA_DESP2_DEF       (TX_DMA_LS0 | TX_DMA_DONE)
3558 +#define TX_DMA_DESP4_DEF       (TX_DMA_QN(3) | TX_DMA_PN(1))
3559 +#define NEXT_TX_DESP_IDX(X)    (((X) + 1) & (NUM_DMA_DESC - 1))
3560 +#define NEXT_RX_DESP_IDX(X)    (((X) + 1) & (NUM_DMA_DESC - 1))
3561 +
3562 +static int fe_msg_level = -1;
3563 +module_param_named(msg_level, fe_msg_level, int, 0);
3564 +MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
3565 +
3566 +static const u32 fe_reg_table_default[FE_REG_COUNT] = {
3567 +       [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
3568 +       [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
3569 +       [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
3570 +       [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
3571 +       [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
3572 +       [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
3573 +       [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
3574 +       [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
3575 +       [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
3576 +       [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
3577 +       [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
3578 +       [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
3579 +       [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
3580 +};
3581 +
3582 +static const u32 *fe_reg_table = fe_reg_table_default;
3583 +
3584 +static void __iomem *fe_base = 0;
3585 +
3586 +void fe_w32(u32 val, unsigned reg)
3587 +{
3588 +       __raw_writel(val, fe_base + reg);
3589 +}
3590 +
3591 +u32 fe_r32(unsigned reg)
3592 +{
3593 +       return __raw_readl(fe_base + reg);
3594 +}
3595 +
3596 +void fe_reg_w32(u32 val, enum fe_reg reg)
3597 +{
3598 +       fe_w32(val, fe_reg_table[reg]);
3599 +}
3600 +
3601 +u32 fe_reg_r32(enum fe_reg reg)
3602 +{
3603 +       return fe_r32(fe_reg_table[reg]);
3604 +}
3605 +
3606 +static inline void fe_int_disable(u32 mask)
3607 +{
3608 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
3609 +                    FE_REG_FE_INT_ENABLE);
3610 +       /* flush write */
3611 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3612 +}
3613 +
3614 +static inline void fe_int_enable(u32 mask)
3615 +{
3616 +       fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
3617 +                    FE_REG_FE_INT_ENABLE);
3618 +       /* flush write */
3619 +       fe_reg_r32(FE_REG_FE_INT_ENABLE);
3620 +}
3621 +
3622 +static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
3623 +{
3624 +       unsigned long flags;
3625 +
3626 +       spin_lock_irqsave(&priv->page_lock, flags);
3627 +       fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
3628 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
3629 +                    FE_GDMA1_MAC_ADRL);
3630 +       spin_unlock_irqrestore(&priv->page_lock, flags);
3631 +}
3632 +
3633 +static int fe_set_mac_address(struct net_device *dev, void *p)
3634 +{
3635 +       int ret = eth_mac_addr(dev, p);
3636 +
3637 +       if (!ret) {
3638 +               struct fe_priv *priv = netdev_priv(dev);
3639 +
3640 +               if (priv->soc->set_mac)
3641 +                       priv->soc->set_mac(priv, dev->dev_addr);
3642 +               else
3643 +                       fe_hw_set_macaddr(priv, p);
3644 +       }
3645 +
3646 +       return ret;
3647 +}
3648 +
3649 +static inline int fe_max_frag_size(int mtu)
3650 +{
3651 +       return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
3652 +               SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3653 +}
3654 +
3655 +static inline int fe_max_buf_size(int frag_size)
3656 +{
3657 +       return frag_size - FE_RX_HLEN -
3658 +               SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
3659 +}
3660 +
3661 +static void fe_clean_rx(struct fe_priv *priv)
3662 +{
3663 +       int i;
3664 +
3665 +       if (priv->rx_data) {
3666 +               for (i = 0; i < NUM_DMA_DESC; i++)
3667 +                       if (priv->rx_data[i]) {
3668 +                               if (priv->rx_dma && priv->rx_dma[i].rxd1)
3669 +                                       dma_unmap_single(&priv->netdev->dev,
3670 +                                                       priv->rx_dma[i].rxd1,
3671 +                                                       priv->rx_buf_size,
3672 +                                                       DMA_FROM_DEVICE);
3673 +                               put_page(virt_to_head_page(priv->rx_data[i]));
3674 +                       }
3675 +
3676 +               kfree(priv->rx_data);
3677 +               priv->rx_data = NULL;
3678 +       }
3679 +
3680 +       if (priv->rx_dma) {
3681 +               dma_free_coherent(&priv->netdev->dev,
3682 +                               NUM_DMA_DESC * sizeof(*priv->rx_dma),
3683 +                               priv->rx_dma,
3684 +                               priv->rx_phys);
3685 +               priv->rx_dma = NULL;
3686 +       }
3687 +}
3688 +
3689 +static int fe_alloc_rx(struct fe_priv *priv)
3690 +{
3691 +       struct net_device *netdev = priv->netdev;
3692 +       int i;
3693 +
3694 +       priv->rx_data = kcalloc(NUM_DMA_DESC, sizeof(*priv->rx_data),
3695 +                       GFP_KERNEL);
3696 +       if (!priv->rx_data)
3697 +               goto no_rx_mem;
3698 +
3699 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3700 +               priv->rx_data[i] = netdev_alloc_frag(priv->frag_size);
3701 +               if (!priv->rx_data[i])
3702 +                       goto no_rx_mem;
3703 +       }
3704 +
3705 +       priv->rx_dma = dma_alloc_coherent(&netdev->dev,
3706 +                       NUM_DMA_DESC * sizeof(*priv->rx_dma),
3707 +                       &priv->rx_phys,
3708 +                       GFP_ATOMIC | __GFP_ZERO);
3709 +       if (!priv->rx_dma)
3710 +               goto no_rx_mem;
3711 +
3712 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3713 +               dma_addr_t dma_addr = dma_map_single(&netdev->dev,
3714 +                               priv->rx_data[i] + FE_RX_OFFSET,
3715 +                               priv->rx_buf_size,
3716 +                               DMA_FROM_DEVICE);
3717 +               if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
3718 +                       goto no_rx_mem;
3719 +               priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
3720 +
3721 +               if (priv->soc->rx_dma)
3722 +                       priv->soc->rx_dma(priv, i, priv->rx_buf_size);
3723 +               else
3724 +                       priv->rx_dma[i].rxd2 = RX_DMA_LSO;
3725 +       }
3726 +       wmb();
3727 +
3728 +       fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
3729 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
3730 +       fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
3731 +       fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
3732 +
3733 +       return 0;
3734 +
3735 +no_rx_mem:
3736 +       return -ENOMEM;
3737 +}
3738 +
3739 +static void fe_clean_tx(struct fe_priv *priv)
3740 +{
3741 +       int i;
3742 +
3743 +       if (priv->tx_skb) {
3744 +               for (i = 0; i < NUM_DMA_DESC; i++) {
3745 +                       if (priv->tx_skb[i])
3746 +                               dev_kfree_skb_any(priv->tx_skb[i]);
3747 +               }
3748 +               kfree(priv->tx_skb);
3749 +               priv->tx_skb = NULL;
3750 +       }
3751 +
3752 +       if (priv->tx_dma) {
3753 +               dma_free_coherent(&priv->netdev->dev,
3754 +                               NUM_DMA_DESC * sizeof(*priv->tx_dma),
3755 +                               priv->tx_dma,
3756 +                               priv->tx_phys);
3757 +               priv->tx_dma = NULL;
3758 +       }
3759 +}
3760 +
3761 +static int fe_alloc_tx(struct fe_priv *priv)
3762 +{
3763 +       int i;
3764 +
3765 +       priv->tx_free_idx = 0;
3766 +
3767 +       priv->tx_skb = kcalloc(NUM_DMA_DESC, sizeof(*priv->tx_skb),
3768 +                       GFP_KERNEL);
3769 +       if (!priv->tx_skb)
3770 +               goto no_tx_mem;
3771 +
3772 +       priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
3773 +                       NUM_DMA_DESC * sizeof(*priv->tx_dma),
3774 +                       &priv->tx_phys,
3775 +                       GFP_ATOMIC | __GFP_ZERO);
3776 +       if (!priv->tx_dma)
3777 +               goto no_tx_mem;
3778 +
3779 +       for (i = 0; i < NUM_DMA_DESC; i++) {
3780 +               if (priv->soc->tx_dma) {
3781 +                       priv->soc->tx_dma(priv, i, NULL);
3782 +                       continue;
3783 +               }
3784 +               priv->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
3785 +       }
3786 +       wmb();
3787 +
3788 +       fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
3789 +       fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
3790 +       fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
3791 +       fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
3792 +
3793 +       return 0;
3794 +
3795 +no_tx_mem:
3796 +       return -ENOMEM;
3797 +}
3798 +
3799 +static int fe_init_dma(struct fe_priv *priv)
3800 +{
3801 +       int err;
3802 +
3803 +       err = fe_alloc_tx(priv);
3804 +       if (err)
3805 +               return err;
3806 +
3807 +       err = fe_alloc_rx(priv);
3808 +       if (err)
3809 +               return err;
3810 +
3811 +       return 0;
3812 +}
3813 +
3814 +static void fe_free_dma(struct fe_priv *priv)
3815 +{
3816 +       fe_clean_tx(priv);
3817 +       fe_clean_rx(priv);
3818 +
3819 +       netdev_reset_queue(priv->netdev);
3820 +}
3821 +
3822 +static inline void txd_unmap_single(struct device *dev, struct fe_tx_dma *txd)
3823 +{
3824 +       if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
3825 +               dma_unmap_single(dev, txd->txd1,
3826 +                               TX_DMA_GET_PLEN0(txd->txd2),
3827 +                               DMA_TO_DEVICE);
3828 +}
3829 +
3830 +static inline void txd_unmap_page0(struct device *dev, struct fe_tx_dma *txd)
3831 +{
3832 +       if (txd->txd1 && TX_DMA_GET_PLEN0(txd->txd2))
3833 +               dma_unmap_page(dev, txd->txd1,
3834 +                               TX_DMA_GET_PLEN0(txd->txd2),
3835 +                               DMA_TO_DEVICE);
3836 +}
3837 +
3838 +static inline void txd_unmap_page1(struct device *dev, struct fe_tx_dma *txd)
3839 +{
3840 +       if (txd->txd3 && TX_DMA_GET_PLEN1(txd->txd2))
3841 +               dma_unmap_page(dev, txd->txd3,
3842 +                               TX_DMA_GET_PLEN1(txd->txd2),
3843 +                               DMA_TO_DEVICE);
3844 +}
3845 +
3846 +void fe_stats_update(struct fe_priv *priv)
3847 +{
3848 +       struct fe_hw_stats *hwstats = priv->hw_stats;
3849 +       unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
3850 +
3851 +       u64_stats_update_begin(&hwstats->syncp);
3852 +
3853 +       hwstats->tx_bytes                       += fe_r32(base);
3854 +       hwstats->tx_packets                     += fe_r32(base + 0x04);
3855 +       hwstats->tx_skip                        += fe_r32(base + 0x08);
3856 +       hwstats->tx_collisions                  += fe_r32(base + 0x0c);
3857 +       hwstats->rx_bytes                       += fe_r32(base + 0x20);
3858 +       hwstats->rx_packets                     += fe_r32(base + 0x24);
3859 +       hwstats->rx_overflow                    += fe_r32(base + 0x28);
3860 +       hwstats->rx_fcs_errors                  += fe_r32(base + 0x2c);
3861 +       hwstats->rx_short_errors                += fe_r32(base + 0x30);
3862 +       hwstats->rx_long_errors                 += fe_r32(base + 0x34);
3863 +       hwstats->rx_checksum_errors             += fe_r32(base + 0x38);
3864 +       hwstats->rx_flow_control_packets        += fe_r32(base + 0x3c);
3865 +
3866 +       u64_stats_update_end(&hwstats->syncp);
3867 +}
3868 +
3869 +static struct rtnl_link_stats64 *fe_get_stats64(struct net_device *dev,
3870 +               struct rtnl_link_stats64 *storage)
3871 +{
3872 +       struct fe_priv *priv = netdev_priv(dev);
3873 +       struct fe_hw_stats *hwstats = priv->hw_stats;
3874 +       unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
3875 +       unsigned int start;
3876 +
3877 +       if (!base) {
3878 +               netdev_stats_to_stats64(storage, &dev->stats);
3879 +               return storage;
3880 +       }
3881 +
3882 +       if (netif_running(dev) && netif_device_present(dev)) {
3883 +               if (spin_trylock(&hwstats->stats_lock)) {
3884 +                       fe_stats_update(priv);
3885 +                       spin_unlock(&hwstats->stats_lock);
3886 +               }
3887 +       }
3888 +
3889 +       do {
3890 +               start = u64_stats_fetch_begin_bh(&hwstats->syncp);
3891 +               storage->rx_packets = hwstats->rx_packets;
3892 +               storage->tx_packets = hwstats->tx_packets;
3893 +               storage->rx_bytes = hwstats->rx_bytes;
3894 +               storage->tx_bytes = hwstats->tx_bytes;
3895 +               storage->collisions = hwstats->tx_collisions;
3896 +               storage->rx_length_errors = hwstats->rx_short_errors +
3897 +                       hwstats->rx_long_errors;
3898 +               storage->rx_over_errors = hwstats->rx_overflow;
3899 +               storage->rx_crc_errors = hwstats->rx_fcs_errors;
3900 +               storage->rx_errors = hwstats->rx_checksum_errors;
3901 +               storage->tx_aborted_errors = hwstats->tx_skip;
3902 +       } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
3903 +
3904 +       storage->tx_errors = priv->netdev->stats.tx_errors;
3905 +       storage->rx_dropped = priv->netdev->stats.rx_dropped;
3906 +       storage->tx_dropped = priv->netdev->stats.tx_dropped;
3907 +
3908 +       return storage;
3909 +}
3910 +
3911 +static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
3912 +               int idx)
3913 +{
3914 +       struct fe_priv *priv = netdev_priv(dev);
3915 +       struct skb_frag_struct *frag;
3916 +       struct fe_tx_dma *txd;
3917 +       dma_addr_t mapped_addr;
3918 +       unsigned int nr_frags;
3919 +       u32 def_txd4, txd2;
3920 +       int i, j, unmap_idx, tx_num;
3921 +
3922 +       txd = &priv->tx_dma[idx];
3923 +       nr_frags = skb_shinfo(skb)->nr_frags;
3924 +       tx_num = 1 + (nr_frags >> 1);
3925 +
3926 +       /* init tx descriptor */
3927 +       if (priv->soc->tx_dma)
3928 +               priv->soc->tx_dma(priv, idx, skb);
3929 +       else
3930 +               txd->txd4 = TX_DMA_DESP4_DEF;
3931 +       def_txd4 = txd->txd4;
3932 +
3933 +       /* use dma_unmap_single to free it */
3934 +       txd->txd4 |= priv->soc->tx_udf_bit;
3935 +
3936 +       /* TX Checksum offload */
3937 +       if (skb->ip_summed == CHECKSUM_PARTIAL)
3938 +               txd->txd4 |= TX_DMA_CHKSUM;
3939 +
3940 +       /* VLAN header offload */
3941 +       if (vlan_tx_tag_present(skb)) {
3942 +               txd->txd4 |= TX_DMA_INS_VLAN |
3943 +                       ((vlan_tx_tag_get(skb) >> VLAN_PRIO_SHIFT) << 4) |
3944 +                       (vlan_tx_tag_get(skb) & 0xF);
3945 +       }
3946 +
3947 +       /* TSO: fill MSS info in tcp checksum field */
3948 +       if (skb_is_gso(skb)) {
3949 +               if (skb_cow_head(skb, 0)) {
3950 +                       netif_warn(priv, tx_err, dev,
3951 +                                       "GSO expand head fail.\n");
3952 +                       goto err_out;
3953 +               }
3954 +               if (skb_shinfo(skb)->gso_type &
3955 +                               (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
3956 +                       txd->txd4 |= TX_DMA_TSO;
3957 +                       tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
3958 +               }
3959 +       }
3960 +
3961 +       mapped_addr = dma_map_single(&dev->dev, skb->data,
3962 +                       skb_headlen(skb), DMA_TO_DEVICE);
3963 +       if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
3964 +               goto err_out;
3965 +       txd->txd1 = mapped_addr;
3966 +       txd2 = TX_DMA_PLEN0(skb_headlen(skb));
3967 +
3968 +       /* TX SG offload */
3969 +       j = idx;
3970 +       for (i = 0; i < nr_frags; i++) {
3971 +
3972 +               frag = &skb_shinfo(skb)->frags[i];
3973 +               mapped_addr = skb_frag_dma_map(&dev->dev, frag, 0,
3974 +                               skb_frag_size(frag), DMA_TO_DEVICE);
3975 +               if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
3976 +                       goto err_dma;
3977 +
3978 +               if (i & 0x1) {
3979 +                       j = NEXT_TX_DESP_IDX(j);
3980 +                       txd = &priv->tx_dma[j];
3981 +                       txd->txd1 = mapped_addr;
3982 +                       txd2 = TX_DMA_PLEN0(frag->size);
3983 +                       txd->txd4 = def_txd4;
3984 +               } else {
3985 +                       txd->txd3 = mapped_addr;
3986 +                       txd2 |= TX_DMA_PLEN1(frag->size);
3987 +                       if (i != (nr_frags -1))
3988 +                               txd->txd2 = txd2;
3989 +                       priv->tx_skb[j] = (struct sk_buff *) DMA_DUMMY_DESC;
3990 +               }
3991 +       }
3992 +
3993 +       /* set last segment */
3994 +       if (nr_frags & 0x1)
3995 +               txd->txd2 = (txd2 | TX_DMA_LS1);
3996 +       else
3997 +               txd->txd2 = (txd2 | TX_DMA_LS0);
3998 +
3999 +       /* store skb to cleanup */
4000 +       priv->tx_skb[j] = skb;
4001 +
4002 +       wmb();
4003 +       j = NEXT_TX_DESP_IDX(j);
4004 +       fe_reg_w32(j, FE_REG_TX_CTX_IDX0);
4005 +
4006 +       return 0;
4007 +
4008 +err_dma:
4009 +       /* unmap dma */
4010 +       txd = &priv->tx_dma[idx];
4011 +       txd_unmap_single(&dev->dev, txd);
4012 +
4013 +       j = idx;
4014 +       unmap_idx = i;
4015 +       for (i = 0; i < unmap_idx; i++) {
4016 +               if (i & 0x1) {
4017 +                       j = NEXT_TX_DESP_IDX(j);
4018 +                       txd = &priv->tx_dma[j];
4019 +                       txd_unmap_page0(&dev->dev, txd);
4020 +               } else {
4021 +                       txd_unmap_page1(&dev->dev, txd);
4022 +               }
4023 +       }
4024 +
4025 +err_out:
4026 +       /* reinit descriptors and skb */
4027 +       j = idx;
4028 +       for (i = 0; i < tx_num; i++) {
4029 +               priv->tx_dma[j].txd2 = TX_DMA_DESP2_DEF;
4030 +               priv->tx_skb[j] = NULL;
4031 +               j = NEXT_TX_DESP_IDX(j);
4032 +       }
4033 +       wmb();
4034 +
4035 +       return -1;
4036 +}
4037 +
4038 +static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv) {
4039 +       unsigned int len;
4040 +       int ret;
4041 +
4042 +       ret = 0;
4043 +       if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
4044 +               if ((priv->flags & FE_FLAG_PADDING_64B) &&
4045 +                               !(priv->flags & FE_FLAG_PADDING_BUG))
4046 +                       return ret;
4047 +
4048 +               if (vlan_tx_tag_present(skb))
4049 +                       len = ETH_ZLEN;
4050 +               else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
4051 +                       len = VLAN_ETH_ZLEN;
4052 +               else if(!(priv->flags & FE_FLAG_PADDING_64B))
4053 +                       len = ETH_ZLEN;
4054 +               else
4055 +                       return ret;
4056 +
4057 +               if (skb->len < len) {
4058 +                       if ((ret = skb_pad(skb, len - skb->len)) < 0)
4059 +                               return ret;
4060 +                       skb->len = len;
4061 +                       skb_set_tail_pointer(skb, len);
4062 +               }
4063 +       }
4064 +
4065 +       return ret;
4066 +}
4067 +
4068 +static inline u32 fe_empty_txd(struct fe_priv *priv, u32 tx_fill_idx)
4069 +{
4070 +       return (u32)(NUM_DMA_DESC - ((tx_fill_idx - priv->tx_free_idx) &
4071 +                               (NUM_DMA_DESC - 1)));
4072 +}
4073 +
4074 +static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
4075 +{
4076 +       struct fe_priv *priv = netdev_priv(dev);
4077 +       struct net_device_stats *stats = &dev->stats;
4078 +       u32 tx;
4079 +       int tx_num;
4080 +
4081 +       if (fe_skb_padto(skb, priv)) {
4082 +               netif_warn(priv, tx_err, dev, "tx padding failed!\n");
4083 +               return NETDEV_TX_OK;
4084 +       }
4085 +
4086 +       spin_lock(&priv->page_lock);
4087 +       tx_num = 1 + (skb_shinfo(skb)->nr_frags >> 1);
4088 +       tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
4089 +       if (unlikely(fe_empty_txd(priv, tx) <= tx_num))
4090 +       {
4091 +               netif_stop_queue(dev);
4092 +               spin_unlock(&priv->page_lock);
4093 +               netif_err(priv, tx_queued,dev,
4094 +                               "Tx Ring full when queue awake!\n");
4095 +               return NETDEV_TX_BUSY;
4096 +       }
4097 +
4098 +       if (fe_tx_map_dma(skb, dev, tx) < 0) {
4099 +               kfree_skb(skb);
4100 +
4101 +               stats->tx_dropped++;
4102 +       } else {
4103 +               netdev_sent_queue(dev, skb->len);
4104 +               skb_tx_timestamp(skb);
4105 +
4106 +               stats->tx_packets++;
4107 +               stats->tx_bytes += skb->len;
4108 +       }
4109 +
4110 +       spin_unlock(&priv->page_lock);
4111 +
4112 +       return NETDEV_TX_OK;
4113 +}
4114 +
4115 +static inline void fe_rx_vlan(struct sk_buff *skb)
4116 +{
4117 +       struct ethhdr *ehdr;
4118 +       u16 vlanid;
4119 +
4120 +       if (!__vlan_get_tag(skb, &vlanid)) {
4121 +               /* pop the vlan tag */
4122 +               ehdr = (struct ethhdr *)skb->data;
4123 +               memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2);
4124 +               skb_pull(skb, VLAN_HLEN);
4125 +               __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid);
4126 +       }
4127 +}
4128 +
4129 +static int fe_poll_rx(struct napi_struct *napi, int budget,
4130 +               struct fe_priv *priv)
4131 +{
4132 +       struct net_device *netdev = priv->netdev;
4133 +       struct net_device_stats *stats = &netdev->stats;
4134 +       struct fe_soc_data *soc = priv->soc;
4135 +       u32 checksum_bit;
4136 +       int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
4137 +       struct sk_buff *skb;
4138 +       u8 *data, *new_data;
4139 +       struct fe_rx_dma *rxd;
4140 +       int done = 0;
4141 +       bool rx_vlan = netdev->features & NETIF_F_HW_VLAN_CTAG_RX;
4142 +
4143 +       if (netdev->features & NETIF_F_RXCSUM)
4144 +               checksum_bit = soc->checksum_bit;
4145 +       else
4146 +               checksum_bit = 0;
4147 +
4148 +       while (done < budget) {
4149 +               unsigned int pktlen;
4150 +               dma_addr_t dma_addr;
4151 +               idx = NEXT_RX_DESP_IDX(idx);
4152 +               rxd = &priv->rx_dma[idx];
4153 +               data = priv->rx_data[idx];
4154 +
4155 +               if (!(rxd->rxd2 & RX_DMA_DONE))
4156 +                       break;
4157 +
4158 +               /* alloc new buffer */
4159 +               new_data = netdev_alloc_frag(priv->frag_size);
4160 +               if (unlikely(!new_data)) {
4161 +                       stats->rx_dropped++;
4162 +                       goto release_desc;
4163 +               }
4164 +               dma_addr = dma_map_single(&netdev->dev,
4165 +                               new_data + FE_RX_OFFSET,
4166 +                               priv->rx_buf_size,
4167 +                               DMA_FROM_DEVICE);
4168 +               if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
4169 +                       put_page(virt_to_head_page(new_data));
4170 +                       goto release_desc;
4171 +               }
4172 +
4173 +               /* receive data */
4174 +               skb = build_skb(data, priv->frag_size);
4175 +               if (unlikely(!skb)) {
4176 +                       put_page(virt_to_head_page(new_data));
4177 +                       goto release_desc;
4178 +               }
4179 +               skb_reserve(skb, FE_RX_OFFSET);
4180 +
4181 +               dma_unmap_single(&netdev->dev, rxd->rxd1,
4182 +                               priv->rx_buf_size, DMA_FROM_DEVICE);
4183 +               pktlen = RX_DMA_PLEN0(rxd->rxd2);
4184 +               skb_put(skb, pktlen);
4185 +               skb->dev = netdev;
4186 +               if (rxd->rxd4 & checksum_bit) {
4187 +                       skb->ip_summed = CHECKSUM_UNNECESSARY;
4188 +               } else {
4189 +                       skb_checksum_none_assert(skb);
4190 +               }
4191 +               if (rx_vlan)
4192 +                       fe_rx_vlan(skb);
4193 +               skb->protocol = eth_type_trans(skb, netdev);
4194 +
4195 +               stats->rx_packets++;
4196 +               stats->rx_bytes += pktlen;
4197 +
4198 +               napi_gro_receive(napi, skb);
4199 +
4200 +               priv->rx_data[idx] = new_data;
4201 +               rxd->rxd1 = (unsigned int) dma_addr;
4202 +
4203 +release_desc:
4204 +               if (soc->rx_dma)
4205 +                       soc->rx_dma(priv, idx, priv->rx_buf_size);
4206 +               else
4207 +                       rxd->rxd2 = RX_DMA_LSO;
4208 +
4209 +               wmb();
4210 +               fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
4211 +               done++;
4212 +       }
4213 +
4214 +       return done;
4215 +}
4216 +
4217 +static int fe_poll_tx(struct fe_priv *priv, int budget)
4218 +{
4219 +       struct net_device *netdev = priv->netdev;
4220 +       struct device *dev = &netdev->dev;
4221 +       unsigned int bytes_compl = 0;
4222 +       struct sk_buff *skb;
4223 +       struct fe_tx_dma *txd;
4224 +       int done = 0, idx;
4225 +       u32 udf_bit = priv->soc->tx_udf_bit;
4226 +
4227 +       idx = priv->tx_free_idx;
4228 +       while (done < budget) {
4229 +               txd = &priv->tx_dma[idx];
4230 +               skb = priv->tx_skb[idx];
4231 +
4232 +               if (!(txd->txd2 & TX_DMA_DONE) || !skb)
4233 +                       break;
4234 +
4235 +               txd_unmap_page1(dev, txd);
4236 +
4237 +               if (txd->txd4 & udf_bit)
4238 +                       txd_unmap_single(dev, txd);
4239 +               else
4240 +                       txd_unmap_page0(dev, txd);
4241 +
4242 +               if (skb != (struct sk_buff *) DMA_DUMMY_DESC) {
4243 +                       bytes_compl += skb->len;
4244 +                       dev_kfree_skb_any(skb);
4245 +                       done++;
4246 +               }
4247 +               priv->tx_skb[idx] = NULL;
4248 +               idx = NEXT_TX_DESP_IDX(idx);
4249 +       }
4250 +       priv->tx_free_idx = idx;
4251 +
4252 +       if (!done)
4253 +               return 0;
4254 +
4255 +       netdev_completed_queue(netdev, done, bytes_compl);
4256 +       if (unlikely(netif_queue_stopped(netdev) &&
4257 +                               netif_carrier_ok(netdev))) {
4258 +               netif_wake_queue(netdev);
4259 +       }
4260 +
4261 +       return done;
4262 +}
4263 +
4264 +static int fe_poll(struct napi_struct *napi, int budget)
4265 +{
4266 +       struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
4267 +       struct fe_hw_stats *hwstat = priv->hw_stats;
4268 +       int tx_done, rx_done;
4269 +       u32 status, mask;
4270 +       u32 tx_intr, rx_intr;
4271 +
4272 +       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
4273 +       tx_intr = priv->soc->tx_dly_int;
4274 +       rx_intr = priv->soc->rx_dly_int;
4275 +       tx_done = rx_done = 0;
4276 +
4277 +poll_again:
4278 +       if (status & tx_intr) {
4279 +               tx_done += fe_poll_tx(priv, budget - tx_done);
4280 +               if (tx_done < budget) {
4281 +                       fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
4282 +               }
4283 +               status = fe_reg_r32(FE_REG_FE_INT_STATUS);
4284 +       }
4285 +
4286 +       if (status & rx_intr) {
4287 +               rx_done += fe_poll_rx(napi, budget - rx_done, priv);
4288 +               if (rx_done < budget) {
4289 +                       fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
4290 +               }
4291 +       }
4292 +
4293 +       if (unlikely(hwstat && (status & FE_CNT_GDM_AF))) {
4294 +               if (spin_trylock(&hwstat->stats_lock)) {
4295 +                       fe_stats_update(priv);
4296 +                       spin_unlock(&hwstat->stats_lock);
4297 +               }
4298 +               fe_reg_w32(FE_CNT_GDM_AF, FE_REG_FE_INT_STATUS);
4299 +       }
4300 +
4301 +       if (unlikely(netif_msg_intr(priv))) {
4302 +               mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
4303 +               netdev_info(priv->netdev,
4304 +                               "done tx %d, rx %d, intr 0x%x/0x%x\n",
4305 +                               tx_done, rx_done, status, mask);
4306 +       }
4307 +
4308 +       if ((tx_done < budget) && (rx_done < budget)) {
4309 +               status = fe_reg_r32(FE_REG_FE_INT_STATUS);
4310 +               if (status & (tx_intr | rx_intr )) {
4311 +                       goto poll_again;
4312 +               }
4313 +               napi_complete(napi);
4314 +               fe_int_enable(tx_intr | rx_intr);
4315 +       }
4316 +
4317 +       return rx_done;
4318 +}
4319 +
4320 +static void fe_tx_timeout(struct net_device *dev)
4321 +{
4322 +       struct fe_priv *priv = netdev_priv(dev);
4323 +
4324 +       priv->netdev->stats.tx_errors++;
4325 +       netif_err(priv, tx_err, dev,
4326 +                       "transmit timed out, waking up the queue\n");
4327 +       netif_info(priv, drv, dev, ": dma_cfg:%08x, free_idx:%d, " \
4328 +                       "dma_ctx_idx=%u, dma_crx_idx=%u\n",
4329 +                       fe_reg_r32(FE_REG_PDMA_GLO_CFG), priv->tx_free_idx,
4330 +                       fe_reg_r32(FE_REG_TX_CTX_IDX0),
4331 +                       fe_reg_r32(FE_REG_RX_CALC_IDX0));
4332 +       netif_wake_queue(dev);
4333 +}
4334 +
4335 +static irqreturn_t fe_handle_irq(int irq, void *dev)
4336 +{
4337 +       struct fe_priv *priv = netdev_priv(dev);
4338 +       u32 status, dly_int;
4339 +
4340 +       status = fe_reg_r32(FE_REG_FE_INT_STATUS);
4341 +
4342 +       if (unlikely(!status))
4343 +               return IRQ_NONE;
4344 +
4345 +       dly_int = (priv->soc->rx_dly_int | priv->soc->tx_dly_int);
4346 +       if (likely(status & dly_int)) {
4347 +               fe_int_disable(dly_int);
4348 +               napi_schedule(&priv->rx_napi);
4349 +       } else {
4350 +               fe_reg_w32(status, FE_REG_FE_INT_STATUS);
4351 +       }
4352 +
4353 +       return IRQ_HANDLED;
4354 +}
4355 +
4356 +int fe_set_clock_cycle(struct fe_priv *priv)
4357 +{
4358 +       unsigned long sysclk = priv->sysclk;
4359 +
4360 +       if (!sysclk) {
4361 +               return -EINVAL;
4362 +       }
4363 +
4364 +       sysclk /= FE_US_CYC_CNT_DIVISOR;
4365 +       sysclk <<= FE_US_CYC_CNT_SHIFT;
4366 +
4367 +       fe_w32((fe_r32(FE_FE_GLO_CFG) &
4368 +                               ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
4369 +                       sysclk,
4370 +                       FE_FE_GLO_CFG);
4371 +       return 0;
4372 +}
4373 +
4374 +void fe_fwd_config(struct fe_priv *priv)
4375 +{
4376 +       u32 fwd_cfg;
4377 +
4378 +       fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
4379 +
4380 +       /* disable jumbo frame */
4381 +       if (priv->flags & FE_FLAG_JUMBO_FRAME)
4382 +               fwd_cfg &= ~FE_GDM1_JMB_EN;
4383 +
4384 +       /* set unicast/multicast/broadcast frame to cpu */
4385 +       fwd_cfg &= ~0xffff;
4386 +
4387 +       fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
4388 +}
4389 +
4390 +static void fe_rxcsum_config(bool enable)
4391 +{
4392 +       if (enable)
4393 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
4394 +                                       FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
4395 +                               FE_GDMA1_FWD_CFG);
4396 +       else
4397 +               fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
4398 +                                       FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
4399 +                               FE_GDMA1_FWD_CFG);
4400 +}
4401 +
4402 +static void fe_txcsum_config(bool enable)
4403 +{
4404 +       if (enable)
4405 +               fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
4406 +                                       FE_TCS_GEN_EN | FE_UCS_GEN_EN),
4407 +                               FE_CDMA_CSG_CFG);
4408 +       else
4409 +               fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
4410 +                                       FE_TCS_GEN_EN | FE_UCS_GEN_EN),
4411 +                               FE_CDMA_CSG_CFG);
4412 +}
4413 +
4414 +void fe_csum_config(struct fe_priv *priv)
4415 +{
4416 +       struct net_device *dev = priv_netdev(priv);
4417 +
4418 +       fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
4419 +       fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
4420 +}
4421 +
4422 +static int fe_hw_init(struct net_device *dev)
4423 +{
4424 +       struct fe_priv *priv = netdev_priv(dev);
4425 +       int i, err;
4426 +
4427 +       err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
4428 +                               dev_name(priv->device), dev);
4429 +       if (err)
4430 +               return err;
4431 +
4432 +       if (priv->soc->set_mac)
4433 +               priv->soc->set_mac(priv, dev->dev_addr);
4434 +       else
4435 +               fe_hw_set_macaddr(priv, dev->dev_addr);
4436 +
4437 +       fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
4438 +
4439 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4440 +
4441 +        /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc. */
4442 +       if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
4443 +               for (i = 0; i < 16; i += 2)
4444 +                       fe_w32(((i + 1) << 16) + i,
4445 +                                       fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
4446 +                                       (i * 2));
4447 +
4448 +       BUG_ON(!priv->soc->fwd_config);
4449 +       if (priv->soc->fwd_config(priv))
4450 +               netdev_err(dev, "unable to get clock\n");
4451 +
4452 +       fe_w32(1, FE_FE_RST_GL);
4453 +       fe_w32(0, FE_FE_RST_GL);
4454 +
4455 +       return 0;
4456 +}
4457 +
4458 +static int fe_open(struct net_device *dev)
4459 +{
4460 +       struct fe_priv *priv = netdev_priv(dev);
4461 +       unsigned long flags;
4462 +       u32 val;
4463 +       int err;
4464 +
4465 +       err = fe_init_dma(priv);
4466 +       if (err)
4467 +               goto err_out;
4468 +
4469 +       spin_lock_irqsave(&priv->page_lock, flags);
4470 +       napi_enable(&priv->rx_napi);
4471 +
4472 +       val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
4473 +       val |= priv->soc->pdma_glo_cfg;
4474 +       fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
4475 +
4476 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4477 +
4478 +       if (priv->phy)
4479 +               priv->phy->start(priv);
4480 +
4481 +       if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
4482 +               netif_carrier_on(dev);
4483 +
4484 +       netif_start_queue(dev);
4485 +       fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4486 +
4487 +       return 0;
4488 +
4489 +err_out:
4490 +       fe_free_dma(priv);
4491 +       return err;
4492 +}
4493 +
4494 +static int fe_stop(struct net_device *dev)
4495 +{
4496 +       struct fe_priv *priv = netdev_priv(dev);
4497 +       unsigned long flags;
4498 +       int i;
4499 +
4500 +       fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
4501 +
4502 +       netif_tx_disable(dev);
4503 +
4504 +       if (priv->phy)
4505 +               priv->phy->stop(priv);
4506 +
4507 +       spin_lock_irqsave(&priv->page_lock, flags);
4508 +       napi_disable(&priv->rx_napi);
4509 +
4510 +       fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
4511 +                    ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
4512 +                    FE_REG_PDMA_GLO_CFG);
4513 +       spin_unlock_irqrestore(&priv->page_lock, flags);
4514 +
4515 +       /* wait dma stop */
4516 +       for (i = 0; i < 10; i++) {
4517 +               if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
4518 +                               (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
4519 +                       msleep(10);
4520 +                       continue;
4521 +               }
4522 +               break;
4523 +       }
4524 +
4525 +       fe_free_dma(priv);
4526 +
4527 +       return 0;
4528 +}
4529 +
4530 +static int __init fe_init(struct net_device *dev)
4531 +{
4532 +       struct fe_priv *priv = netdev_priv(dev);
4533 +       struct device_node *port;
4534 +       int err;
4535 +
4536 +       BUG_ON(!priv->soc->reset_fe);
4537 +       priv->soc->reset_fe();
4538 +
4539 +       if (priv->soc->switch_init)
4540 +               priv->soc->switch_init(priv);
4541 +
4542 +       memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
4543 +       of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
4544 +
4545 +       err = fe_mdio_init(priv);
4546 +       if (err)
4547 +               return err;
4548 +
4549 +       if (priv->soc->port_init)
4550 +               for_each_child_of_node(priv->device->of_node, port)
4551 +                       if (of_device_is_compatible(port, "ralink,eth-port") && of_device_is_available(port))
4552 +                               priv->soc->port_init(priv, port);
4553 +
4554 +       if (priv->phy) {
4555 +               err = priv->phy->connect(priv);
4556 +               if (err)
4557 +                       goto err_phy_disconnect;
4558 +       }
4559 +
4560 +       err = fe_hw_init(dev);
4561 +       if (err)
4562 +               goto err_phy_disconnect;
4563 +
4564 +       if (priv->soc->switch_config)
4565 +               priv->soc->switch_config(priv);
4566 +
4567 +       return 0;
4568 +
4569 +err_phy_disconnect:
4570 +       if (priv->phy)
4571 +               priv->phy->disconnect(priv);
4572 +       fe_mdio_cleanup(priv);
4573 +
4574 +       return err;
4575 +}
4576 +
4577 +static void fe_uninit(struct net_device *dev)
4578 +{
4579 +       struct fe_priv *priv = netdev_priv(dev);
4580 +
4581 +       if (priv->phy)
4582 +               priv->phy->disconnect(priv);
4583 +       fe_mdio_cleanup(priv);
4584 +
4585 +       fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
4586 +       free_irq(dev->irq, dev);
4587 +}
4588 +
4589 +static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4590 +{
4591 +       struct fe_priv *priv = netdev_priv(dev);
4592 +
4593 +       if (!priv->phy_dev)
4594 +               return -ENODEV;
4595 +
4596 +       switch (cmd) {
4597 +       case SIOCETHTOOL:
4598 +               return phy_ethtool_ioctl(priv->phy_dev,
4599 +                               (void *) ifr->ifr_data);
4600 +       case SIOCGMIIPHY:
4601 +       case SIOCGMIIREG:
4602 +       case SIOCSMIIREG:
4603 +               return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
4604 +       default:
4605 +               break;
4606 +       }
4607 +
4608 +       return -EOPNOTSUPP;
4609 +}
4610 +
4611 +static int fe_change_mtu(struct net_device *dev, int new_mtu)
4612 +{
4613 +       struct fe_priv *priv = netdev_priv(dev);
4614 +       int frag_size, old_mtu;
4615 +       u32 fwd_cfg;
4616 +
4617 +       if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
4618 +               return eth_change_mtu(dev, new_mtu);
4619 +
4620 +       frag_size = fe_max_frag_size(new_mtu);
4621 +       if (new_mtu < 68 || frag_size > PAGE_SIZE)
4622 +               return -EINVAL;
4623 +
4624 +       old_mtu = dev->mtu;
4625 +       dev->mtu = new_mtu;
4626 +
4627 +       /* return early if the buffer sizes will not change */
4628 +       if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
4629 +               return 0;
4630 +       if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
4631 +               return 0;
4632 +
4633 +       if (new_mtu <= ETH_DATA_LEN) {
4634 +               priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
4635 +               priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
4636 +       } else {
4637 +               priv->frag_size = PAGE_SIZE;
4638 +               priv->rx_buf_size = fe_max_buf_size(PAGE_SIZE);
4639 +       }
4640 +
4641 +       if (!netif_running(dev))
4642 +               return 0;
4643 +
4644 +       fe_stop(dev);
4645 +       fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
4646 +       if (new_mtu <= ETH_DATA_LEN)
4647 +               fwd_cfg &= ~FE_GDM1_JMB_EN;
4648 +       else {
4649 +               fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
4650 +               fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
4651 +                               FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
4652 +       }
4653 +       fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
4654 +
4655 +       return fe_open(dev);
4656 +}
4657 +
4658 +static const struct net_device_ops fe_netdev_ops = {
4659 +       .ndo_init               = fe_init,
4660 +       .ndo_uninit             = fe_uninit,
4661 +       .ndo_open               = fe_open,
4662 +       .ndo_stop               = fe_stop,
4663 +       .ndo_start_xmit         = fe_start_xmit,
4664 +       .ndo_set_mac_address    = fe_set_mac_address,
4665 +       .ndo_validate_addr      = eth_validate_addr,
4666 +       .ndo_do_ioctl           = fe_do_ioctl,
4667 +       .ndo_change_mtu         = fe_change_mtu,
4668 +       .ndo_tx_timeout         = fe_tx_timeout,
4669 +       .ndo_get_stats64        = fe_get_stats64,
4670 +};
4671 +
4672 +static int fe_probe(struct platform_device *pdev)
4673 +{
4674 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4675 +       const struct of_device_id *match;
4676 +       struct fe_soc_data *soc;
4677 +       struct net_device *netdev;
4678 +       struct fe_priv *priv;
4679 +       struct clk *sysclk;
4680 +       int err;
4681 +
4682 +       device_reset(&pdev->dev);
4683 +
4684 +       match = of_match_device(of_fe_match, &pdev->dev);
4685 +       soc = (struct fe_soc_data *) match->data;
4686 +
4687 +       if (soc->reg_table)
4688 +               fe_reg_table = soc->reg_table;
4689 +       else
4690 +               soc->reg_table = fe_reg_table;
4691 +
4692 +       fe_base = devm_request_and_ioremap(&pdev->dev, res);
4693 +       if (!fe_base) {
4694 +               err = -EADDRNOTAVAIL;
4695 +               goto err_out;
4696 +       }
4697 +
4698 +       netdev = alloc_etherdev(sizeof(*priv));
4699 +       if (!netdev) {
4700 +               dev_err(&pdev->dev, "alloc_etherdev failed\n");
4701 +               err = -ENOMEM;
4702 +               goto err_iounmap;
4703 +       }
4704 +
4705 +       SET_NETDEV_DEV(netdev, &pdev->dev);
4706 +       netdev->netdev_ops = &fe_netdev_ops;
4707 +       netdev->base_addr = (unsigned long) fe_base;
4708 +       netdev->watchdog_timeo = TX_TIMEOUT;
4709 +
4710 +       netdev->irq = platform_get_irq(pdev, 0);
4711 +       if (netdev->irq < 0) {
4712 +               dev_err(&pdev->dev, "no IRQ resource found\n");
4713 +               err = -ENXIO;
4714 +               goto err_free_dev;
4715 +       }
4716 +
4717 +       if (soc->init_data)
4718 +               soc->init_data(soc, netdev);
4719 +       /* fake NETIF_F_HW_VLAN_CTAG_RX for good GRO performance */
4720 +       netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4721 +       netdev->vlan_features = netdev->hw_features &
4722 +               ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
4723 +       netdev->features |= netdev->hw_features;
4724 +
4725 +       priv = netdev_priv(netdev);
4726 +       spin_lock_init(&priv->page_lock);
4727 +       if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
4728 +               priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
4729 +               if (!priv->hw_stats) {
4730 +                       err = -ENOMEM;
4731 +                       goto err_free_dev;
4732 +               }
4733 +               spin_lock_init(&priv->hw_stats->stats_lock);
4734 +       }
4735 +
4736 +       sysclk = devm_clk_get(&pdev->dev, NULL);
4737 +       if (!IS_ERR(sysclk))
4738 +               priv->sysclk = clk_get_rate(sysclk);
4739 +
4740 +       priv->netdev = netdev;
4741 +       priv->device = &pdev->dev;
4742 +       priv->soc = soc;
4743 +       priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
4744 +       priv->frag_size = fe_max_frag_size(ETH_DATA_LEN);
4745 +       priv->rx_buf_size = fe_max_buf_size(ETH_DATA_LEN);
4746 +       if (priv->frag_size > PAGE_SIZE) {
4747 +               dev_err(&pdev->dev, "error frag size.\n");
4748 +               err = -EINVAL;
4749 +               goto err_free_dev;
4750 +       }
4751 +
4752 +       netif_napi_add(netdev, &priv->rx_napi, fe_poll, 32);
4753 +       fe_set_ethtool_ops(netdev);
4754 +
4755 +       err = register_netdev(netdev);
4756 +       if (err) {
4757 +               dev_err(&pdev->dev, "error bringing up device\n");
4758 +               goto err_free_dev;
4759 +       }
4760 +
4761 +       platform_set_drvdata(pdev, netdev);
4762 +
4763 +       netif_info(priv, probe, netdev, "ralink at 0x%08lx, irq %d\n",
4764 +                       netdev->base_addr, netdev->irq);
4765 +
4766 +       return 0;
4767 +
4768 +err_free_dev:
4769 +       free_netdev(netdev);
4770 +err_iounmap:
4771 +       devm_iounmap(&pdev->dev, fe_base);
4772 +err_out:
4773 +       return err;
4774 +}
4775 +
4776 +static int fe_remove(struct platform_device *pdev)
4777 +{
4778 +        struct net_device *dev = platform_get_drvdata(pdev);
4779 +       struct fe_priv *priv = netdev_priv(dev);
4780 +
4781 +       netif_napi_del(&priv->rx_napi);
4782 +       if (priv->hw_stats)
4783 +               kfree(priv->hw_stats);
4784 +
4785 +       unregister_netdev(dev);
4786 +       free_netdev(dev);
4787 +       platform_set_drvdata(pdev, NULL);
4788 +
4789 +       return 0;
4790 +}
4791 +
4792 +static struct platform_driver fe_driver = {
4793 +       .probe = fe_probe,
4794 +       .remove = fe_remove,
4795 +       .driver = {
4796 +               .name = "ralink_soc_eth",
4797 +               .owner = THIS_MODULE,
4798 +               .of_match_table = of_fe_match,
4799 +       },
4800 +};
4801 +
4802 +static int __init init_rtfe(void)
4803 +{
4804 +       int ret;
4805 +
4806 +       ret = rtesw_init();
4807 +       if (ret)
4808 +               return ret;
4809 +
4810 +       ret = platform_driver_register(&fe_driver);
4811 +       if (ret)
4812 +               rtesw_exit();
4813 +
4814 +       return ret;
4815 +}
4816 +
4817 +static void __exit exit_rtfe(void)
4818 +{
4819 +       platform_driver_unregister(&fe_driver);
4820 +       rtesw_exit();
4821 +}
4822 +
4823 +module_init(init_rtfe);
4824 +module_exit(exit_rtfe);
4825 +
4826 +MODULE_LICENSE("GPL");
4827 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
4828 +MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
4829 +MODULE_VERSION(FE_DRV_VERSION);
4830 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.h
4831 ===================================================================
4832 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
4833 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_soc_eth.h  2014-10-29 20:25:55.433357519 +0100
4834 @@ -0,0 +1,448 @@
4835 +/*
4836 + *   This program is free software; you can redistribute it and/or modify
4837 + *   it under the terms of the GNU General Public License as published by
4838 + *   the Free Software Foundation; version 2 of the License
4839 + *
4840 + *   This program is distributed in the hope that it will be useful,
4841 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
4842 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
4843 + *   GNU General Public License for more details.
4844 + *
4845 + *   You should have received a copy of the GNU General Public License
4846 + *   along with this program; if not, write to the Free Software
4847 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
4848 + *
4849 + *   based on Ralink SDK3.3
4850 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
4851 + */
4852 +
4853 +#ifndef FE_ETH_H
4854 +#define FE_ETH_H
4855 +
4856 +#include <linux/mii.h>
4857 +#include <linux/interrupt.h>
4858 +#include <linux/netdevice.h>
4859 +#include <linux/dma-mapping.h>
4860 +#include <linux/phy.h>
4861 +#include <linux/ethtool.h>
4862 +
4863 +enum fe_reg {
4864 +       FE_REG_PDMA_GLO_CFG = 0,
4865 +       FE_REG_PDMA_RST_CFG,
4866 +       FE_REG_DLY_INT_CFG,
4867 +       FE_REG_TX_BASE_PTR0,
4868 +       FE_REG_TX_MAX_CNT0,
4869 +       FE_REG_TX_CTX_IDX0,
4870 +       FE_REG_RX_BASE_PTR0,
4871 +       FE_REG_RX_MAX_CNT0,
4872 +       FE_REG_RX_CALC_IDX0,
4873 +       FE_REG_FE_INT_ENABLE,
4874 +       FE_REG_FE_INT_STATUS,
4875 +       FE_REG_FE_DMA_VID_BASE,
4876 +       FE_REG_FE_COUNTER_BASE,
4877 +       FE_REG_COUNT
4878 +};
4879 +
4880 +#define FE_DRV_VERSION         "0.1.0"
4881 +
4882 +/* power of 2 to let NEXT_TX_DESP_IDX work */
4883 +#define NUM_DMA_DESC           (1 << 7)
4884 +#define MAX_DMA_DESC           0xfff
4885 +
4886 +#define FE_DELAY_EN_INT                0x80
4887 +#define FE_DELAY_MAX_INT       0x04
4888 +#define FE_DELAY_MAX_TOUT      0x04
4889 +#define FE_DELAY_TIME          20
4890 +#define FE_DELAY_CHAN          (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
4891 +#define FE_DELAY_INIT          ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
4892 +#define FE_PSE_FQFC_CFG_INIT   0x80504000
4893 +#define FE_PSE_FQFC_CFG_256Q   0xff908000
4894 +
4895 +/* interrupt bits */
4896 +#define FE_CNT_PPE_AF          BIT(31)
4897 +#define FE_CNT_GDM_AF          BIT(29)
4898 +#define FE_PSE_P2_FC           BIT(26)
4899 +#define FE_PSE_BUF_DROP                BIT(24)
4900 +#define FE_GDM_OTHER_DROP      BIT(23)
4901 +#define FE_PSE_P1_FC           BIT(22)
4902 +#define FE_PSE_P0_FC           BIT(21)
4903 +#define FE_PSE_FQ_EMPTY                BIT(20)
4904 +#define FE_GE1_STA_CHG         BIT(18)
4905 +#define FE_TX_COHERENT         BIT(17)
4906 +#define FE_RX_COHERENT         BIT(16)
4907 +#define FE_TX_DONE_INT3                BIT(11)
4908 +#define FE_TX_DONE_INT2                BIT(10)
4909 +#define FE_TX_DONE_INT1                BIT(9)
4910 +#define FE_TX_DONE_INT0                BIT(8)
4911 +#define FE_RX_DONE_INT0                BIT(2)
4912 +#define FE_TX_DLY_INT          BIT(1)
4913 +#define FE_RX_DLY_INT          BIT(0)
4914 +
4915 +#define RT5350_RX_DLY_INT      BIT(30)
4916 +#define RT5350_TX_DLY_INT      BIT(28)
4917 +
4918 +/* registers */
4919 +#define FE_FE_OFFSET           0x0000
4920 +#define FE_GDMA_OFFSET         0x0020
4921 +#define FE_PSE_OFFSET          0x0040
4922 +#define FE_GDMA2_OFFSET                0x0060
4923 +#define FE_CDMA_OFFSET         0x0080
4924 +#define FE_DMA_VID0            0x00a8
4925 +#define FE_PDMA_OFFSET         0x0100
4926 +#define FE_PPE_OFFSET          0x0200
4927 +#define FE_CMTABLE_OFFSET      0x0400
4928 +#define FE_POLICYTABLE_OFFSET  0x1000
4929 +
4930 +#define RT5350_PDMA_OFFSET     0x0800
4931 +#define RT5350_SDM_OFFSET      0x0c00
4932 +
4933 +#define FE_MDIO_ACCESS         (FE_FE_OFFSET + 0x00)
4934 +#define FE_MDIO_CFG            (FE_FE_OFFSET + 0x04)
4935 +#define FE_FE_GLO_CFG          (FE_FE_OFFSET + 0x08)
4936 +#define FE_FE_RST_GL           (FE_FE_OFFSET + 0x0C)
4937 +#define FE_FE_INT_STATUS       (FE_FE_OFFSET + 0x10)
4938 +#define FE_FE_INT_ENABLE       (FE_FE_OFFSET + 0x14)
4939 +#define FE_MDIO_CFG2           (FE_FE_OFFSET + 0x18)
4940 +#define FE_FOC_TS_T            (FE_FE_OFFSET + 0x1C)
4941 +
4942 +#define        FE_GDMA1_FWD_CFG        (FE_GDMA_OFFSET + 0x00)
4943 +#define FE_GDMA1_SCH_CFG       (FE_GDMA_OFFSET + 0x04)
4944 +#define FE_GDMA1_SHPR_CFG      (FE_GDMA_OFFSET + 0x08)
4945 +#define FE_GDMA1_MAC_ADRL      (FE_GDMA_OFFSET + 0x0C)
4946 +#define FE_GDMA1_MAC_ADRH      (FE_GDMA_OFFSET + 0x10)
4947 +
4948 +#define        FE_GDMA2_FWD_CFG        (FE_GDMA2_OFFSET + 0x00)
4949 +#define FE_GDMA2_SCH_CFG       (FE_GDMA2_OFFSET + 0x04)
4950 +#define FE_GDMA2_SHPR_CFG      (FE_GDMA2_OFFSET + 0x08)
4951 +#define FE_GDMA2_MAC_ADRL      (FE_GDMA2_OFFSET + 0x0C)
4952 +#define FE_GDMA2_MAC_ADRH      (FE_GDMA2_OFFSET + 0x10)
4953 +
4954 +#define FE_PSE_FQ_CFG          (FE_PSE_OFFSET + 0x00)
4955 +#define FE_CDMA_FC_CFG         (FE_PSE_OFFSET + 0x04)
4956 +#define FE_GDMA1_FC_CFG                (FE_PSE_OFFSET + 0x08)
4957 +#define FE_GDMA2_FC_CFG                (FE_PSE_OFFSET + 0x0C)
4958 +
4959 +#define FE_CDMA_CSG_CFG                (FE_CDMA_OFFSET + 0x00)
4960 +#define FE_CDMA_SCH_CFG                (FE_CDMA_OFFSET + 0x04)
4961 +
4962 +#define MT7620A_GDMA_OFFSET            0x0600
4963 +#define        MT7620A_GDMA1_FWD_CFG           (MT7620A_GDMA_OFFSET + 0x00)
4964 +#define MT7620A_FE_GDMA1_SCH_CFG       (MT7620A_GDMA_OFFSET + 0x04)
4965 +#define MT7620A_FE_GDMA1_SHPR_CFG      (MT7620A_GDMA_OFFSET + 0x08)
4966 +#define MT7620A_FE_GDMA1_MAC_ADRL      (MT7620A_GDMA_OFFSET + 0x0C)
4967 +#define MT7620A_FE_GDMA1_MAC_ADRH      (MT7620A_GDMA_OFFSET + 0x10)
4968 +
4969 +#define RT5350_TX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x00)
4970 +#define RT5350_TX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x04)
4971 +#define RT5350_TX_CTX_IDX0     (RT5350_PDMA_OFFSET + 0x08)
4972 +#define RT5350_TX_DTX_IDX0     (RT5350_PDMA_OFFSET + 0x0C)
4973 +#define RT5350_TX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x10)
4974 +#define RT5350_TX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x14)
4975 +#define RT5350_TX_CTX_IDX1     (RT5350_PDMA_OFFSET + 0x18)
4976 +#define RT5350_TX_DTX_IDX1     (RT5350_PDMA_OFFSET + 0x1C)
4977 +#define RT5350_TX_BASE_PTR2    (RT5350_PDMA_OFFSET + 0x20)
4978 +#define RT5350_TX_MAX_CNT2     (RT5350_PDMA_OFFSET + 0x24)
4979 +#define RT5350_TX_CTX_IDX2     (RT5350_PDMA_OFFSET + 0x28)
4980 +#define RT5350_TX_DTX_IDX2     (RT5350_PDMA_OFFSET + 0x2C)
4981 +#define RT5350_TX_BASE_PTR3    (RT5350_PDMA_OFFSET + 0x30)
4982 +#define RT5350_TX_MAX_CNT3     (RT5350_PDMA_OFFSET + 0x34)
4983 +#define RT5350_TX_CTX_IDX3     (RT5350_PDMA_OFFSET + 0x38)
4984 +#define RT5350_TX_DTX_IDX3     (RT5350_PDMA_OFFSET + 0x3C)
4985 +#define RT5350_RX_BASE_PTR0    (RT5350_PDMA_OFFSET + 0x100)
4986 +#define RT5350_RX_MAX_CNT0     (RT5350_PDMA_OFFSET + 0x104)
4987 +#define RT5350_RX_CALC_IDX0    (RT5350_PDMA_OFFSET + 0x108)
4988 +#define RT5350_RX_DRX_IDX0     (RT5350_PDMA_OFFSET + 0x10C)
4989 +#define RT5350_RX_BASE_PTR1    (RT5350_PDMA_OFFSET + 0x110)
4990 +#define RT5350_RX_MAX_CNT1     (RT5350_PDMA_OFFSET + 0x114)
4991 +#define RT5350_RX_CALC_IDX1    (RT5350_PDMA_OFFSET + 0x118)
4992 +#define RT5350_RX_DRX_IDX1     (RT5350_PDMA_OFFSET + 0x11C)
4993 +#define RT5350_PDMA_GLO_CFG    (RT5350_PDMA_OFFSET + 0x204)
4994 +#define RT5350_PDMA_RST_CFG    (RT5350_PDMA_OFFSET + 0x208)
4995 +#define RT5350_DLY_INT_CFG     (RT5350_PDMA_OFFSET + 0x20c)
4996 +#define RT5350_FE_INT_STATUS   (RT5350_PDMA_OFFSET + 0x220)
4997 +#define RT5350_FE_INT_ENABLE   (RT5350_PDMA_OFFSET + 0x228)
4998 +#define RT5350_PDMA_SCH_CFG    (RT5350_PDMA_OFFSET + 0x280)
4999 +
5000 +#define FE_PDMA_GLO_CFG                (FE_PDMA_OFFSET + 0x00)
5001 +#define FE_PDMA_RST_CFG                (FE_PDMA_OFFSET + 0x04)
5002 +#define FE_PDMA_SCH_CFG                (FE_PDMA_OFFSET + 0x08)
5003 +#define FE_DLY_INT_CFG         (FE_PDMA_OFFSET + 0x0C)
5004 +#define FE_TX_BASE_PTR0                (FE_PDMA_OFFSET + 0x10)
5005 +#define FE_TX_MAX_CNT0         (FE_PDMA_OFFSET + 0x14)
5006 +#define FE_TX_CTX_IDX0         (FE_PDMA_OFFSET + 0x18)
5007 +#define FE_TX_DTX_IDX0         (FE_PDMA_OFFSET + 0x1C)
5008 +#define FE_TX_BASE_PTR1                (FE_PDMA_OFFSET + 0x20)
5009 +#define FE_TX_MAX_CNT1         (FE_PDMA_OFFSET + 0x24)
5010 +#define FE_TX_CTX_IDX1         (FE_PDMA_OFFSET + 0x28)
5011 +#define FE_TX_DTX_IDX1         (FE_PDMA_OFFSET + 0x2C)
5012 +#define FE_RX_BASE_PTR0                (FE_PDMA_OFFSET + 0x30)
5013 +#define FE_RX_MAX_CNT0         (FE_PDMA_OFFSET + 0x34)
5014 +#define FE_RX_CALC_IDX0                (FE_PDMA_OFFSET + 0x38)
5015 +#define FE_RX_DRX_IDX0         (FE_PDMA_OFFSET + 0x3C)
5016 +#define FE_TX_BASE_PTR2                (FE_PDMA_OFFSET + 0x40)
5017 +#define FE_TX_MAX_CNT2         (FE_PDMA_OFFSET + 0x44)
5018 +#define FE_TX_CTX_IDX2         (FE_PDMA_OFFSET + 0x48)
5019 +#define FE_TX_DTX_IDX2         (FE_PDMA_OFFSET + 0x4C)
5020 +#define FE_TX_BASE_PTR3                (FE_PDMA_OFFSET + 0x50)
5021 +#define FE_TX_MAX_CNT3         (FE_PDMA_OFFSET + 0x54)
5022 +#define FE_TX_CTX_IDX3         (FE_PDMA_OFFSET + 0x58)
5023 +#define FE_TX_DTX_IDX3         (FE_PDMA_OFFSET + 0x5C)
5024 +#define FE_RX_BASE_PTR1                (FE_PDMA_OFFSET + 0x60)
5025 +#define FE_RX_MAX_CNT1         (FE_PDMA_OFFSET + 0x64)
5026 +#define FE_RX_CALC_IDX1                (FE_PDMA_OFFSET + 0x68)
5027 +#define FE_RX_DRX_IDX1         (FE_PDMA_OFFSET + 0x6C)
5028 +
5029 +#define RT5350_SDM_CFG         (RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
5030 +#define RT5350_SDM_RRING       (RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
5031 +#define RT5350_SDM_TRING       (RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
5032 +#define RT5350_SDM_MAC_ADRL    (RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
5033 +#define RT5350_SDM_MAC_ADRH    (RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
5034 +#define RT5350_SDM_TPCNT       (RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
5035 +#define RT5350_SDM_TBCNT       (RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
5036 +#define RT5350_SDM_RPCNT       (RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
5037 +#define RT5350_SDM_RBCNT       (RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
5038 +#define RT5350_SDM_CS_ERR      (RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
5039 +
5040 +#define RT5350_SDM_ICS_EN      BIT(16)
5041 +#define RT5350_SDM_TCS_EN      BIT(17)
5042 +#define RT5350_SDM_UCS_EN      BIT(18)
5043 +
5044 +
5045 +/* MDIO_CFG register bits */
5046 +#define FE_MDIO_CFG_AUTO_POLL_EN       BIT(29)
5047 +#define FE_MDIO_CFG_GP1_BP_EN          BIT(16)
5048 +#define FE_MDIO_CFG_GP1_FRC_EN         BIT(15)
5049 +#define FE_MDIO_CFG_GP1_SPEED_10       (0 << 13)
5050 +#define FE_MDIO_CFG_GP1_SPEED_100      (1 << 13)
5051 +#define FE_MDIO_CFG_GP1_SPEED_1000     (2 << 13)
5052 +#define FE_MDIO_CFG_GP1_DUPLEX         BIT(12)
5053 +#define FE_MDIO_CFG_GP1_FC_TX          BIT(11)
5054 +#define FE_MDIO_CFG_GP1_FC_RX          BIT(10)
5055 +#define FE_MDIO_CFG_GP1_LNK_DWN                BIT(9)
5056 +#define FE_MDIO_CFG_GP1_AN_FAIL                BIT(8)
5057 +#define FE_MDIO_CFG_MDC_CLK_DIV_1      (0 << 6)
5058 +#define FE_MDIO_CFG_MDC_CLK_DIV_2      (1 << 6)
5059 +#define FE_MDIO_CFG_MDC_CLK_DIV_4      (2 << 6)
5060 +#define FE_MDIO_CFG_MDC_CLK_DIV_8      (3 << 6)
5061 +#define FE_MDIO_CFG_TURBO_MII_FREQ     BIT(5)
5062 +#define FE_MDIO_CFG_TURBO_MII_MODE     BIT(4)
5063 +#define FE_MDIO_CFG_RX_CLK_SKEW_0      (0 << 2)
5064 +#define FE_MDIO_CFG_RX_CLK_SKEW_200    (1 << 2)
5065 +#define FE_MDIO_CFG_RX_CLK_SKEW_400    (2 << 2)
5066 +#define FE_MDIO_CFG_RX_CLK_SKEW_INV    (3 << 2)
5067 +#define FE_MDIO_CFG_TX_CLK_SKEW_0      0
5068 +#define FE_MDIO_CFG_TX_CLK_SKEW_200    1
5069 +#define FE_MDIO_CFG_TX_CLK_SKEW_400    2
5070 +#define FE_MDIO_CFG_TX_CLK_SKEW_INV    3
5071 +
5072 +/* uni-cast port */
5073 +#define FE_GDM1_JMB_LEN_MASK   0xf
5074 +#define FE_GDM1_JMB_LEN_SHIFT  28
5075 +#define FE_GDM1_ICS_EN         BIT(22)
5076 +#define FE_GDM1_TCS_EN         BIT(21)
5077 +#define FE_GDM1_UCS_EN         BIT(20)
5078 +#define FE_GDM1_JMB_EN         BIT(19)
5079 +#define FE_GDM1_STRPCRC                BIT(16)
5080 +#define FE_GDM1_UFRC_P_CPU     (0 << 12)
5081 +#define FE_GDM1_UFRC_P_GDMA1   (1 << 12)
5082 +#define FE_GDM1_UFRC_P_PPE     (6 << 12)
5083 +
5084 +/* checksums */
5085 +#define FE_ICS_GEN_EN          BIT(2)
5086 +#define FE_UCS_GEN_EN          BIT(1)
5087 +#define FE_TCS_GEN_EN          BIT(0)
5088 +
5089 +/* dma ring */
5090 +#define FE_PST_DRX_IDX0                BIT(16)
5091 +#define FE_PST_DTX_IDX3                BIT(3)
5092 +#define FE_PST_DTX_IDX2                BIT(2)
5093 +#define FE_PST_DTX_IDX1                BIT(1)
5094 +#define FE_PST_DTX_IDX0                BIT(0)
5095 +
5096 +#define FE_TX_WB_DDONE         BIT(6)
5097 +#define FE_RX_DMA_BUSY         BIT(3)
5098 +#define FE_TX_DMA_BUSY         BIT(1)
5099 +#define FE_RX_DMA_EN           BIT(2)
5100 +#define FE_TX_DMA_EN           BIT(0)
5101 +
5102 +#define FE_PDMA_SIZE_4DWORDS   (0 << 4)
5103 +#define FE_PDMA_SIZE_8DWORDS   (1 << 4)
5104 +#define FE_PDMA_SIZE_16DWORDS  (2 << 4)
5105 +
5106 +#define FE_US_CYC_CNT_MASK     0xff
5107 +#define FE_US_CYC_CNT_SHIFT    0x8
5108 +#define FE_US_CYC_CNT_DIVISOR  1000000
5109 +
5110 +#define RX_DMA_PLEN0(_x)       (((_x) >> 16) & 0x3fff)
5111 +#define RX_DMA_LSO             BIT(30)
5112 +#define RX_DMA_DONE            BIT(31)
5113 +#define RX_DMA_L4VALID         BIT(30)
5114 +
5115 +struct fe_rx_dma {
5116 +       unsigned int rxd1;
5117 +       unsigned int rxd2;
5118 +       unsigned int rxd3;
5119 +       unsigned int rxd4;
5120 +} __packed __aligned(4);
5121 +
5122 +#define TX_DMA_PLEN0_MASK      ((0x3fff) << 16)
5123 +#define TX_DMA_PLEN0(_x)       (((_x) & 0x3fff) << 16)
5124 +#define TX_DMA_PLEN1(_x)       ((_x) & 0x3fff)
5125 +#define TX_DMA_GET_PLEN0(_x)    (((_x) >> 16 ) & 0x3fff)
5126 +#define TX_DMA_GET_PLEN1(_x)    ((_x) & 0x3fff)
5127 +#define TX_DMA_LS1             BIT(14)
5128 +#define TX_DMA_LS0             BIT(30)
5129 +#define TX_DMA_DONE            BIT(31)
5130 +
5131 +#define TX_DMA_INS_VLAN                BIT(7)
5132 +#define TX_DMA_INS_PPPOE       BIT(12)
5133 +#define TX_DMA_QN(_x)          ((_x) << 16)
5134 +#define TX_DMA_PN(_x)          ((_x) << 24)
5135 +#define TX_DMA_QN_MASK         TX_DMA_QN(0x7)
5136 +#define TX_DMA_PN_MASK         TX_DMA_PN(0x7)
5137 +#define TX_DMA_UDF             BIT(20)
5138 +#define TX_DMA_CHKSUM          (0x7 << 29)
5139 +#define TX_DMA_TSO             BIT(28)
5140 +
5141 +/* frame engine counters */
5142 +#define FE_PPE_AC_BCNT0                (FE_CMTABLE_OFFSET + 0x00)
5143 +#define FE_GDMA1_TX_GBCNT      (FE_CMTABLE_OFFSET + 0x300)
5144 +#define FE_GDMA2_TX_GBCNT      (FE_GDMA1_TX_GBCNT + 0x40)
5145 +
5146 +/* phy device flags */
5147 +#define FE_PHY_FLAG_PORT       BIT(0)
5148 +#define FE_PHY_FLAG_ATTACH     BIT(1)
5149 +
5150 +struct fe_tx_dma {
5151 +       unsigned int txd1;
5152 +       unsigned int txd2;
5153 +       unsigned int txd3;
5154 +       unsigned int txd4;
5155 +} __packed __aligned(4);
5156 +
5157 +struct fe_priv;
5158 +
5159 +struct fe_phy {
5160 +       struct phy_device       *phy[8];
5161 +       struct device_node      *phy_node[8];
5162 +       const __be32            *phy_fixed[8];
5163 +       int                     duplex[8];
5164 +       int                     speed[8];
5165 +       int                     tx_fc[8];
5166 +       int                     rx_fc[8];
5167 +       spinlock_t              lock;
5168 +
5169 +       int (*connect)(struct fe_priv *priv);
5170 +       void (*disconnect)(struct fe_priv *priv);
5171 +       void (*start)(struct fe_priv *priv);
5172 +       void (*stop)(struct fe_priv *priv);
5173 +};
5174 +
5175 +struct fe_soc_data
5176 +{
5177 +       unsigned char mac[6];
5178 +       const u32 *reg_table;
5179 +
5180 +       void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
5181 +       void (*reset_fe)(void);
5182 +       void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
5183 +       int (*fwd_config)(struct fe_priv *priv);
5184 +       void (*tx_dma)(struct fe_priv *priv, int idx, struct sk_buff *skb);
5185 +       void (*rx_dma)(struct fe_priv *priv, int idx, int len);
5186 +       int (*switch_init)(struct fe_priv *priv);
5187 +       int (*switch_config)(struct fe_priv *priv);
5188 +       void (*port_init)(struct fe_priv *priv, struct device_node *port);
5189 +       int (*has_carrier)(struct fe_priv *priv);
5190 +       int (*mdio_init)(struct fe_priv *priv);
5191 +       void (*mdio_cleanup)(struct fe_priv *priv);
5192 +       int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
5193 +       int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
5194 +       void (*mdio_adjust_link)(struct fe_priv *priv, int port);
5195 +
5196 +       void *swpriv;
5197 +       u32 pdma_glo_cfg;
5198 +       u32 rx_dly_int;
5199 +       u32 tx_dly_int;
5200 +       u32 checksum_bit;
5201 +       u32 tx_udf_bit;
5202 +};
5203 +
5204 +#define FE_FLAG_PADDING_64B            BIT(0)
5205 +#define FE_FLAG_PADDING_BUG            BIT(1)
5206 +#define FE_FLAG_JUMBO_FRAME            BIT(2)
5207 +
5208 +#define FE_STAT_REG_DECLARE            \
5209 +       _FE(tx_bytes)                   \
5210 +       _FE(tx_packets)                 \
5211 +       _FE(tx_skip)                    \
5212 +       _FE(tx_collisions)              \
5213 +       _FE(rx_bytes)                   \
5214 +       _FE(rx_packets)                 \
5215 +       _FE(rx_overflow)                \
5216 +       _FE(rx_fcs_errors)              \
5217 +       _FE(rx_short_errors)            \
5218 +       _FE(rx_long_errors)             \
5219 +       _FE(rx_checksum_errors)         \
5220 +       _FE(rx_flow_control_packets)
5221 +
5222 +struct fe_hw_stats
5223 +{
5224 +       spinlock_t stats_lock;
5225 +       struct u64_stats_sync syncp;
5226 +#define _FE(x) u64 x;
5227 +FE_STAT_REG_DECLARE
5228 +#undef _FE
5229 +};
5230 +
5231 +struct fe_priv
5232 +{
5233 +       spinlock_t                      page_lock;
5234 +
5235 +       struct fe_soc_data              *soc;
5236 +       struct net_device               *netdev;
5237 +       u32                             msg_enable;
5238 +       u32                             flags;
5239 +
5240 +       struct device                   *device;
5241 +       unsigned long                   sysclk;
5242 +
5243 +       u16                             frag_size;
5244 +       u16                             rx_buf_size;
5245 +       struct fe_rx_dma                *rx_dma;
5246 +       u8                              **rx_data;
5247 +       dma_addr_t                      rx_phys;
5248 +       struct napi_struct              rx_napi;
5249 +
5250 +       struct fe_tx_dma                *tx_dma;
5251 +       struct sk_buff                  **tx_skb;
5252 +       dma_addr_t                      tx_phys;
5253 +       unsigned int                    tx_free_idx;
5254 +
5255 +       struct fe_phy                   *phy;
5256 +       struct mii_bus                  *mii_bus;
5257 +       struct phy_device               *phy_dev;
5258 +       u32                             phy_flags;
5259 +
5260 +       int                             link[8];
5261 +
5262 +       struct fe_hw_stats              *hw_stats;
5263 +};
5264 +
5265 +extern const struct of_device_id of_fe_match[];
5266 +
5267 +void fe_w32(u32 val, unsigned reg);
5268 +u32 fe_r32(unsigned reg);
5269 +
5270 +int fe_set_clock_cycle(struct fe_priv *priv);
5271 +void fe_csum_config(struct fe_priv *priv);
5272 +void fe_stats_update(struct fe_priv *priv);
5273 +void fe_fwd_config(struct fe_priv *priv);
5274 +void fe_reg_w32(u32 val, enum fe_reg reg);
5275 +u32 fe_reg_r32(enum fe_reg reg);
5276 +
5277 +static inline void *priv_netdev(struct fe_priv *priv)
5278 +{
5279 +       return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
5280 +}
5281 +
5282 +#endif /* FE_ETH_H */
5283 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_mt7620.c
5284 ===================================================================
5285 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5286 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_mt7620.c      2014-10-29 20:25:55.433357519 +0100
5287 @@ -0,0 +1,164 @@
5288 +/*
5289 + *   This program is free software; you can redistribute it and/or modify
5290 + *   it under the terms of the GNU General Public License as published by
5291 + *   the Free Software Foundation; version 2 of the License
5292 + *
5293 + *   This program is distributed in the hope that it will be useful,
5294 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
5295 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5296 + *   GNU General Public License for more details.
5297 + *
5298 + *   You should have received a copy of the GNU General Public License
5299 + *   along with this program; if not, write to the Free Software
5300 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5301 + *
5302 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5303 + */
5304 +
5305 +#include <linux/module.h>
5306 +#include <linux/platform_device.h>
5307 +#include <linux/if_vlan.h>
5308 +
5309 +#include <asm/mach-ralink/ralink_regs.h>
5310 +
5311 +#include <mt7620.h>
5312 +#include "ralink_soc_eth.h"
5313 +#include "gsw_mt7620a.h"
5314 +
5315 +#define MT7620A_CDMA_CSG_CFG   0x400
5316 +#define MT7620_DMA_VID         (MT7620A_CDMA_CSG_CFG | 0x30)
5317 +#define MT7620A_DMA_2B_OFFSET  BIT(31)
5318 +#define MT7620A_RESET_FE       BIT(21)
5319 +#define MT7620A_RESET_ESW      BIT(23)
5320 +#define MT7620_L4_VALID                BIT(23)
5321 +
5322 +#define MT7620_TX_DMA_UDF      BIT(15)
5323 +#define TX_DMA_FP_BMAP         ((0xff) << 19)
5324 +
5325 +#define SYSC_REG_RESET_CTRL     0x34
5326 +
5327 +#define CDMA_ICS_EN            BIT(2)
5328 +#define CDMA_UCS_EN            BIT(1)
5329 +#define CDMA_TCS_EN            BIT(0)
5330 +
5331 +#define GDMA_ICS_EN            BIT(22)
5332 +#define GDMA_TCS_EN            BIT(21)
5333 +#define GDMA_UCS_EN            BIT(20)
5334 +
5335 +/* frame engine counters */
5336 +#define MT7620_REG_MIB_OFFSET  0x1000
5337 +#define MT7620_PPE_AC_BCNT0    (MT7620_REG_MIB_OFFSET + 0x00)
5338 +#define MT7620_GDM1_TX_GBCNT   (MT7620_REG_MIB_OFFSET + 0x300)
5339 +#define MT7620_GDM2_TX_GBCNT   (MT7620_GDM1_TX_GBCNT + 0x40)
5340 +
5341 +static const u32 mt7620_reg_table[FE_REG_COUNT] = {
5342 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
5343 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
5344 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
5345 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
5346 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
5347 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
5348 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
5349 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
5350 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
5351 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
5352 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
5353 +       [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
5354 +       [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
5355 +};
5356 +
5357 +static void mt7620_fe_reset(void)
5358 +{
5359 +       rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
5360 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
5361 +}
5362 +
5363 +static void mt7620_rxcsum_config(bool enable)
5364 +{
5365 +       if (enable)
5366 +               fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
5367 +                                       GDMA_TCS_EN | GDMA_UCS_EN),
5368 +                               MT7620A_GDMA1_FWD_CFG);
5369 +       else
5370 +               fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
5371 +                                       GDMA_TCS_EN | GDMA_UCS_EN),
5372 +                               MT7620A_GDMA1_FWD_CFG);
5373 +}
5374 +
5375 +static void mt7620_txcsum_config(bool enable)
5376 +{
5377 +       if (enable)
5378 +               fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
5379 +                                       CDMA_UCS_EN | CDMA_TCS_EN),
5380 +                               MT7620A_CDMA_CSG_CFG);
5381 +       else
5382 +               fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
5383 +                                       CDMA_UCS_EN | CDMA_TCS_EN),
5384 +                               MT7620A_CDMA_CSG_CFG);
5385 +}
5386 +
5387 +static int mt7620_fwd_config(struct fe_priv *priv)
5388 +{
5389 +       struct net_device *dev = priv_netdev(priv);
5390 +
5391 +       fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
5392 +
5393 +       mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
5394 +       mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
5395 +
5396 +       return 0;
5397 +}
5398 +
5399 +static void mt7620_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
5400 +{
5401 +       priv->tx_dma[idx].txd4 = 0;
5402 +}
5403 +
5404 +static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
5405 +{
5406 +       priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
5407 +}
5408 +
5409 +static void mt7620_init_data(struct fe_soc_data *data,
5410 +               struct net_device *netdev)
5411 +{
5412 +       struct fe_priv *priv = netdev_priv(netdev);
5413 +
5414 +       priv->flags = FE_FLAG_PADDING_64B;
5415 +       netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
5416 +               NETIF_F_HW_VLAN_CTAG_TX;
5417 +
5418 +       if (mt7620_get_eco() >= 5)
5419 +               netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
5420 +                       NETIF_F_IPV6_CSUM;
5421 +}
5422 +
5423 +static struct fe_soc_data mt7620_data = {
5424 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5425 +       .init_data = mt7620_init_data,
5426 +       .reset_fe = mt7620_fe_reset,
5427 +       .set_mac = mt7620_set_mac,
5428 +       .fwd_config = mt7620_fwd_config,
5429 +       .tx_dma = mt7620_tx_dma,
5430 +       .rx_dma = mt7620_rx_dma,
5431 +       .switch_init = mt7620_gsw_probe,
5432 +       .switch_config = mt7620_gsw_config,
5433 +       .port_init = mt7620_port_init,
5434 +       .reg_table = mt7620_reg_table,
5435 +       .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
5436 +       .rx_dly_int = RT5350_RX_DLY_INT,
5437 +       .tx_dly_int = RT5350_TX_DLY_INT,
5438 +       .checksum_bit = MT7620_L4_VALID,
5439 +       .tx_udf_bit = MT7620_TX_DMA_UDF,
5440 +       .has_carrier = mt7620a_has_carrier,
5441 +       .mdio_read = mt7620_mdio_read,
5442 +       .mdio_write = mt7620_mdio_write,
5443 +       .mdio_adjust_link = mt7620_mdio_link_adjust,
5444 +};
5445 +
5446 +const struct of_device_id of_fe_match[] = {
5447 +       { .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
5448 +       {},
5449 +};
5450 +
5451 +MODULE_DEVICE_TABLE(of, of_fe_match);
5452 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_rt2880.c
5453 ===================================================================
5454 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5455 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_rt2880.c      2014-10-29 20:25:55.433357519 +0100
5456 @@ -0,0 +1,81 @@
5457 +/*
5458 + *   This program is free software; you can redistribute it and/or modify
5459 + *   it under the terms of the GNU General Public License as published by
5460 + *   the Free Software Foundation; version 2 of the License
5461 + *
5462 + *   This program is distributed in the hope that it will be useful,
5463 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
5464 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5465 + *   GNU General Public License for more details.
5466 + *
5467 + *   You should have received a copy of the GNU General Public License
5468 + *   along with this program; if not, write to the Free Software
5469 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5470 + *
5471 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5472 + */
5473 +
5474 +#include <linux/module.h>
5475 +
5476 +#include <asm/mach-ralink/ralink_regs.h>
5477 +
5478 +#include "ralink_soc_eth.h"
5479 +#include "mdio_rt2880.h"
5480 +
5481 +#define SYSC_REG_RESET_CTRL            0x034
5482 +#define RT2880_RESET_FE                        BIT(18)
5483 +
5484 +static void rt2880_init_data(struct fe_soc_data *data,
5485 +               struct net_device *netdev)
5486 +{
5487 +       struct fe_priv *priv = netdev_priv(netdev);
5488 +
5489 +       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
5490 +               FE_FLAG_JUMBO_FRAME;
5491 +       netdev->hw_features = NETIF_F_SG | NETIF_F_HW_VLAN_CTAG_TX;
5492 +       /* maybe have hardware bug. */
5493 +       //netdev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
5494 +}
5495 +
5496 +void rt2880_fe_reset(void)
5497 +{
5498 +       rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
5499 +}
5500 +
5501 +static int rt2880_fwd_config(struct fe_priv *priv)
5502 +{
5503 +       int ret;
5504 +
5505 +       ret = fe_set_clock_cycle(priv);
5506 +       if (ret)
5507 +               return ret;
5508 +
5509 +       fe_fwd_config(priv);
5510 +       fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
5511 +       fe_csum_config(priv);
5512 +
5513 +       return ret;
5514 +}
5515 +
5516 +struct fe_soc_data rt2880_data = {
5517 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5518 +       .init_data = rt2880_init_data,
5519 +       .reset_fe = rt2880_fe_reset,
5520 +       .fwd_config = rt2880_fwd_config,
5521 +       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
5522 +       .checksum_bit = RX_DMA_L4VALID,
5523 +       .tx_udf_bit = TX_DMA_UDF,
5524 +       .rx_dly_int = FE_RX_DLY_INT,
5525 +       .tx_dly_int = FE_TX_DLY_INT,
5526 +       .mdio_read = rt2880_mdio_read,
5527 +       .mdio_write = rt2880_mdio_write,
5528 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
5529 +       .port_init = rt2880_port_init,
5530 +};
5531 +
5532 +const struct of_device_id of_fe_match[] = {
5533 +       { .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
5534 +       {},
5535 +};
5536 +
5537 +MODULE_DEVICE_TABLE(of, of_fe_match);
5538 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_rt305x.c
5539 ===================================================================
5540 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5541 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_rt305x.c      2014-10-29 20:25:55.433357519 +0100
5542 @@ -0,0 +1,161 @@
5543 +/*
5544 + *   This program is free software; you can redistribute it and/or modify
5545 + *   it under the terms of the GNU General Public License as published by
5546 + *   the Free Software Foundation; version 2 of the License
5547 + *
5548 + *   This program is distributed in the hope that it will be useful,
5549 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
5550 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5551 + *   GNU General Public License for more details.
5552 + *
5553 + *   You should have received a copy of the GNU General Public License
5554 + *   along with this program; if not, write to the Free Software
5555 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5556 + *
5557 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5558 + */
5559 +
5560 +#include <linux/module.h>
5561 +
5562 +#include <asm/mach-ralink/ralink_regs.h>
5563 +#include <asm/mach-ralink/rt305x.h>
5564 +
5565 +#include "ralink_soc_eth.h"
5566 +#include "mdio_rt2880.h"
5567 +
5568 +#define RT305X_RESET_FE         BIT(21)
5569 +#define RT305X_RESET_ESW        BIT(23)
5570 +#define SYSC_REG_RESET_CTRL     0x034
5571 +
5572 +static const u32 rt5350_reg_table[FE_REG_COUNT] = {
5573 +       [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
5574 +       [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
5575 +       [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
5576 +       [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
5577 +       [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
5578 +       [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
5579 +       [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
5580 +       [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
5581 +       [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
5582 +       [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
5583 +       [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
5584 +       [FE_REG_FE_DMA_VID_BASE] = 0,
5585 +};
5586 +
5587 +static void rt305x_init_data(struct fe_soc_data *data,
5588 +               struct net_device *netdev)
5589 +{
5590 +       struct fe_priv *priv = netdev_priv(netdev);
5591 +
5592 +       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG;
5593 +       netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
5594 +               NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
5595 +}
5596 +
5597 +static int rt3050_fwd_config(struct fe_priv *priv)
5598 +{
5599 +       int ret;
5600 +
5601 +       if (soc_is_rt3052()) {
5602 +               ret = fe_set_clock_cycle(priv);
5603 +               if (ret)
5604 +                       return ret;
5605 +       }
5606 +
5607 +       fe_fwd_config(priv);
5608 +       if (!soc_is_rt3352())
5609 +               fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
5610 +       fe_csum_config(priv);
5611 +
5612 +       return 0;
5613 +}
5614 +
5615 +static void rt305x_fe_reset(void)
5616 +{
5617 +       rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
5618 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
5619 +}
5620 +
5621 +static void rt5350_init_data(struct fe_soc_data *data,
5622 +               struct net_device *netdev)
5623 +{
5624 +       netdev->hw_features = NETIF_F_SG | NETIF_F_RXCSUM;
5625 +}
5626 +
5627 +static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
5628 +{
5629 +       unsigned long flags;
5630 +
5631 +       spin_lock_irqsave(&priv->page_lock, flags);
5632 +       fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
5633 +       fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
5634 +               RT5350_SDM_MAC_ADRL);
5635 +       spin_unlock_irqrestore(&priv->page_lock, flags);
5636 +}
5637 +
5638 +static void rt5350_rxcsum_config(bool enable)
5639 +{
5640 +       if (enable)
5641 +               fe_w32(fe_r32(RT5350_SDM_CFG) | (RT5350_SDM_ICS_EN |
5642 +                               RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
5643 +                               RT5350_SDM_CFG);
5644 +       else
5645 +               fe_w32(fe_r32(RT5350_SDM_CFG) & ~(RT5350_SDM_ICS_EN |
5646 +                               RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN),
5647 +                               RT5350_SDM_CFG);
5648 +}
5649 +
5650 +static int rt5350_fwd_config(struct fe_priv *priv)
5651 +{
5652 +       struct net_device *dev = priv_netdev(priv);
5653 +
5654 +       rt5350_rxcsum_config((dev->features & NETIF_F_RXCSUM));
5655 +
5656 +       return 0;
5657 +}
5658 +
5659 +static void rt5350_tx_dma(struct fe_priv *priv, int idx, struct sk_buff *skb)
5660 +{
5661 +       priv->tx_dma[idx].txd4 = 0;
5662 +}
5663 +
5664 +static void rt5350_fe_reset(void)
5665 +{
5666 +       rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
5667 +       rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
5668 +}
5669 +
5670 +static struct fe_soc_data rt3050_data = {
5671 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5672 +       .init_data = rt305x_init_data,
5673 +       .reset_fe = rt305x_fe_reset,
5674 +       .fwd_config = rt3050_fwd_config,
5675 +       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
5676 +       .checksum_bit = RX_DMA_L4VALID,
5677 +       .tx_udf_bit = TX_DMA_UDF,
5678 +       .rx_dly_int = FE_RX_DLY_INT,
5679 +       .tx_dly_int = FE_TX_DLY_INT,
5680 +};
5681 +
5682 +static struct fe_soc_data rt5350_data = {
5683 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5684 +       .init_data = rt5350_init_data,
5685 +       .reg_table = rt5350_reg_table,
5686 +       .reset_fe = rt5350_fe_reset,
5687 +       .set_mac = rt5350_set_mac,
5688 +       .fwd_config = rt5350_fwd_config,
5689 +       .tx_dma = rt5350_tx_dma,
5690 +       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
5691 +       .checksum_bit = RX_DMA_L4VALID,
5692 +       .tx_udf_bit = TX_DMA_UDF,
5693 +       .rx_dly_int = RT5350_RX_DLY_INT,
5694 +       .tx_dly_int = RT5350_TX_DLY_INT,
5695 +};
5696 +
5697 +const struct of_device_id of_fe_match[] = {
5698 +       { .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
5699 +       { .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
5700 +       {},
5701 +};
5702 +
5703 +MODULE_DEVICE_TABLE(of, of_fe_match);
5704 Index: linux-3.14.18/drivers/net/ethernet/ralink/soc_rt3883.c
5705 ===================================================================
5706 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5707 +++ linux-3.14.18/drivers/net/ethernet/ralink/soc_rt3883.c      2014-10-29 20:25:55.433357519 +0100
5708 @@ -0,0 +1,88 @@
5709 +/*
5710 + *   This program is free software; you can redistribute it and/or modify
5711 + *   it under the terms of the GNU General Public License as published by
5712 + *   the Free Software Foundation; version 2 of the License
5713 + *
5714 + *   This program is distributed in the hope that it will be useful,
5715 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
5716 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5717 + *   GNU General Public License for more details.
5718 + *
5719 + *   You should have received a copy of the GNU General Public License
5720 + *   along with this program; if not, write to the Free Software
5721 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5722 + *
5723 + *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
5724 + */
5725 +
5726 +#include <linux/module.h>
5727 +
5728 +#include <asm/mach-ralink/ralink_regs.h>
5729 +
5730 +#include "ralink_soc_eth.h"
5731 +#include "mdio_rt2880.h"
5732 +
5733 +#define RT3883_SYSC_REG_RSTCTRL                0x34
5734 +#define RT3883_RSTCTRL_FE              BIT(21)
5735 +
5736 +static void rt3883_fe_reset(void)
5737 +{
5738 +       u32 t;
5739 +
5740 +       t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
5741 +       t |= RT3883_RSTCTRL_FE;
5742 +       rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
5743 +
5744 +       t &= ~RT3883_RSTCTRL_FE;
5745 +       rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
5746 +}
5747 +
5748 +static int rt3883_fwd_config(struct fe_priv *priv)
5749 +{
5750 +       int ret;
5751 +
5752 +       ret = fe_set_clock_cycle(priv);
5753 +       if (ret)
5754 +               return ret;
5755 +
5756 +       fe_fwd_config(priv);
5757 +       fe_w32(FE_PSE_FQFC_CFG_256Q, FE_PSE_FQ_CFG);
5758 +       fe_csum_config(priv);
5759 +
5760 +       return ret;
5761 +}
5762 +
5763 +static void rt3883_init_data(struct fe_soc_data *data,
5764 +               struct net_device *netdev)
5765 +{
5766 +       struct fe_priv *priv = netdev_priv(netdev);
5767 +
5768 +       priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_PADDING_BUG |
5769 +               FE_FLAG_JUMBO_FRAME;
5770 +       netdev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
5771 +               NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX;
5772 +}
5773 +
5774 +static struct fe_soc_data rt3883_data = {
5775 +       .mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
5776 +       .init_data = rt3883_init_data,
5777 +       .reset_fe = rt3883_fe_reset,
5778 +       .fwd_config = rt3883_fwd_config,
5779 +       .pdma_glo_cfg = FE_PDMA_SIZE_8DWORDS,
5780 +       .rx_dly_int = FE_RX_DLY_INT,
5781 +       .tx_dly_int = FE_TX_DLY_INT,
5782 +       .checksum_bit = RX_DMA_L4VALID,
5783 +       .tx_udf_bit = TX_DMA_UDF,
5784 +       .mdio_read = rt2880_mdio_read,
5785 +       .mdio_write = rt2880_mdio_write,
5786 +       .mdio_adjust_link = rt2880_mdio_link_adjust,
5787 +       .port_init = rt2880_port_init,
5788 +};
5789 +
5790 +const struct of_device_id of_fe_match[] = {
5791 +       { .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
5792 +       {},
5793 +};
5794 +
5795 +MODULE_DEVICE_TABLE(of, of_fe_match);
5796 +
5797 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_ethtool.c
5798 ===================================================================
5799 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
5800 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_ethtool.c  2014-10-29 20:25:55.433357519 +0100
5801 @@ -0,0 +1,262 @@
5802 +/*
5803 + *   This program is free software; you can redistribute it and/or modify
5804 + *   it under the terms of the GNU General Public License as published by
5805 + *   the Free Software Foundation; version 2 of the License
5806 + *
5807 + *   This program is distributed in the hope that it will be useful,
5808 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
5809 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5810 + *   GNU General Public License for more details.
5811 + *
5812 + *   You should have received a copy of the GNU General Public License
5813 + *   along with this program; if not, write to the Free Software
5814 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
5815 + *
5816 + *   Copyright (C) 2009-2013 Michael Lee <igvtee@gmail.com>
5817 + */
5818 +
5819 +#include "ralink_soc_eth.h"
5820 +
5821 +static const char fe_gdma_str[][ETH_GSTRING_LEN] = {
5822 +#define _FE(x...)      # x,
5823 +FE_STAT_REG_DECLARE
5824 +#undef _FE
5825 +};
5826 +
5827 +static int fe_get_settings(struct net_device *dev,
5828 +               struct ethtool_cmd *cmd)
5829 +{
5830 +       struct fe_priv *priv = netdev_priv(dev);
5831 +       int err;
5832 +
5833 +       if (!priv->phy_dev)
5834 +               goto out_gset;
5835 +
5836 +       if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
5837 +               err = phy_read_status(priv->phy_dev);
5838 +               if (err)
5839 +                       goto out_gset;
5840 +       }
5841 +
5842 +       return phy_ethtool_gset(priv->phy_dev, cmd);
5843 +
5844 +out_gset:
5845 +       return -ENODEV;
5846 +}
5847 +
5848 +static int fe_set_settings(struct net_device *dev,
5849 +               struct ethtool_cmd *cmd)
5850 +{
5851 +       struct fe_priv *priv = netdev_priv(dev);
5852 +
5853 +       if (!priv->phy_dev)
5854 +               goto out_sset;
5855 +
5856 +       if (cmd->phy_address != priv->phy_dev->addr) {
5857 +               if (priv->phy->phy_node[cmd->phy_address]) {
5858 +                       priv->phy_dev = priv->phy->phy[cmd->phy_address];
5859 +                       priv->phy_flags = FE_PHY_FLAG_PORT;
5860 +               } else if (priv->mii_bus &&
5861 +                               priv->mii_bus->phy_map[cmd->phy_address]) {
5862 +                       priv->phy_dev = priv->mii_bus->phy_map[cmd->phy_address];
5863 +                       priv->phy_flags = FE_PHY_FLAG_ATTACH;
5864 +               } else
5865 +                       goto out_sset;
5866 +       }
5867 +
5868 +       return phy_ethtool_sset(priv->phy_dev, cmd);
5869 +
5870 +out_sset:
5871 +       return -ENODEV;
5872 +}
5873 +
5874 +static void fe_get_drvinfo (struct net_device *dev,
5875 +               struct ethtool_drvinfo *info)
5876 +{
5877 +       struct fe_priv *priv = netdev_priv(dev);
5878 +       struct fe_soc_data *soc = priv->soc;
5879 +
5880 +       strlcpy(info->driver, priv->device->driver->name, sizeof(info->driver));
5881 +       strlcpy(info->version, FE_DRV_VERSION, sizeof(info->version));
5882 +       strlcpy(info->bus_info, dev_name(priv->device), sizeof(info->bus_info));
5883 +
5884 +       if (soc->reg_table[FE_REG_FE_COUNTER_BASE])
5885 +               info->n_stats = ARRAY_SIZE(fe_gdma_str);
5886 +}
5887 +
5888 +static u32 fe_get_msglevel(struct net_device *dev)
5889 +{
5890 +       struct fe_priv *priv = netdev_priv(dev);
5891 +
5892 +       return priv->msg_enable;
5893 +}
5894 +
5895 +static void fe_set_msglevel(struct net_device *dev, u32 value)
5896 +{
5897 +       struct fe_priv *priv = netdev_priv(dev);
5898 +
5899 +       priv->msg_enable = value;
5900 +}
5901 +
5902 +static int fe_nway_reset(struct net_device *dev)
5903 +{
5904 +       struct fe_priv *priv = netdev_priv(dev);
5905 +
5906 +       if (!priv->phy_dev)
5907 +               goto out_nway_reset;
5908 +
5909 +       return genphy_restart_aneg(priv->phy_dev);
5910 +
5911 +out_nway_reset:
5912 +       return -EOPNOTSUPP;
5913 +}
5914 +
5915 +static u32 fe_get_link(struct net_device *dev)
5916 +{
5917 +       struct fe_priv *priv = netdev_priv(dev);
5918 +       int err;
5919 +
5920 +       if (!priv->phy_dev)
5921 +               goto out_get_link;
5922 +
5923 +       if (priv->phy_flags == FE_PHY_FLAG_ATTACH) {
5924 +               err = genphy_update_link(priv->phy_dev);
5925 +               if (err)
5926 +                       goto out_get_link;
5927 +       }
5928 +
5929 +       return priv->phy_dev->link;
5930 +
5931 +out_get_link:
5932 +       return ethtool_op_get_link(dev);
5933 +}
5934 +
5935 +static void fe_get_ringparam(struct net_device *dev,
5936 +               struct ethtool_ringparam *ring)
5937 +{
5938 +       ring->rx_max_pending = MAX_DMA_DESC;
5939 +       ring->tx_max_pending = MAX_DMA_DESC;
5940 +       ring->rx_pending = NUM_DMA_DESC;
5941 +       ring->tx_pending = NUM_DMA_DESC;
5942 +}
5943 +
5944 +static int fe_get_coalesce(struct net_device *dev,
5945 +               struct ethtool_coalesce *coal)
5946 +{
5947 +        u32 delay_cfg = fe_reg_r32(FE_REG_DLY_INT_CFG);
5948 +
5949 +        coal->rx_coalesce_usecs = (delay_cfg & 0xff) * FE_DELAY_TIME;
5950 +        coal->rx_max_coalesced_frames = ((delay_cfg >> 8) & 0x7f);
5951 +        coal->use_adaptive_rx_coalesce = (delay_cfg >> 15) & 0x1;
5952 +
5953 +        coal->tx_coalesce_usecs = ((delay_cfg >> 16 )& 0xff) * FE_DELAY_TIME;
5954 +        coal->tx_max_coalesced_frames = ((delay_cfg >> 24) & 0x7f);
5955 +        coal->use_adaptive_tx_coalesce = (delay_cfg >> 31) & 0x1;
5956 +
5957 +        return 0;
5958 +}
5959 +
5960 +static int fe_set_coalesce(struct net_device *dev,
5961 +               struct ethtool_coalesce *coal)
5962 +{
5963 +       u32 delay_cfg;
5964 +       u32 rx_usecs, tx_usecs;
5965 +       u32 rx_frames, tx_frames;
5966 +
5967 +       if (!coal->use_adaptive_rx_coalesce || !coal->use_adaptive_tx_coalesce)
5968 +               return -EINVAL;
5969 +
5970 +       rx_usecs = DIV_ROUND_UP(coal->rx_coalesce_usecs, FE_DELAY_TIME);
5971 +       rx_frames = coal->rx_max_coalesced_frames;
5972 +       tx_usecs = DIV_ROUND_UP(coal->tx_coalesce_usecs, FE_DELAY_TIME);
5973 +       tx_frames = coal->tx_max_coalesced_frames;
5974 +
5975 +       if (((tx_usecs == 0) && (tx_frames ==0)) ||
5976 +                       ((rx_usecs == 0) && (rx_frames ==0)))
5977 +               return -EINVAL;
5978 +
5979 +       if (rx_usecs > 0xff) rx_usecs = 0xff;
5980 +       if (rx_frames > 0x7f) rx_frames = 0x7f;
5981 +       if (tx_usecs > 0xff) tx_usecs = 0xff;
5982 +       if (tx_frames > 0x7f) tx_frames = 0x7f;
5983 +
5984 +       delay_cfg = ((((FE_DELAY_EN_INT | tx_frames) << 8) | tx_usecs) << 16) |
5985 +               (((FE_DELAY_EN_INT | rx_frames) << 8) | rx_usecs);
5986 +
5987 +       fe_reg_w32(delay_cfg, FE_REG_DLY_INT_CFG);
5988 +
5989 +       return 0;
5990 +}
5991 +
5992 +static void fe_get_strings(struct net_device *dev, u32 stringset, u8 *data)
5993 +{
5994 +       switch (stringset) {
5995 +       case ETH_SS_STATS:
5996 +               memcpy(data, *fe_gdma_str, sizeof(fe_gdma_str));
5997 +               break;
5998 +       }
5999 +}
6000 +
6001 +static int fe_get_sset_count(struct net_device *dev, int sset)
6002 +{
6003 +       switch (sset) {
6004 +       case ETH_SS_STATS:
6005 +               return ARRAY_SIZE(fe_gdma_str);
6006 +       default:
6007 +               return -EOPNOTSUPP;
6008 +       }
6009 +}
6010 +
6011 +static void fe_get_ethtool_stats(struct net_device *dev,
6012 +               struct ethtool_stats *stats, u64 *data)
6013 +{
6014 +       struct fe_priv *priv = netdev_priv(dev);
6015 +       struct fe_hw_stats *hwstats = priv->hw_stats;
6016 +       u64 *data_src, *data_dst;
6017 +       unsigned int start;
6018 +       int i;
6019 +
6020 +       if (netif_running(dev) && netif_device_present(dev)) {
6021 +               if (spin_trylock(&hwstats->stats_lock)) {
6022 +                       fe_stats_update(priv);
6023 +                       spin_unlock(&hwstats->stats_lock);
6024 +               }
6025 +       }
6026 +
6027 +       do {
6028 +               data_src = &hwstats->tx_bytes;
6029 +               data_dst = data;
6030 +               start = u64_stats_fetch_begin_bh(&hwstats->syncp);
6031 +
6032 +               for (i = 0; i < ARRAY_SIZE(fe_gdma_str); i++)
6033 +                       *data_dst++ = *data_src++;
6034 +
6035 +       } while (u64_stats_fetch_retry_bh(&hwstats->syncp, start));
6036 +}
6037 +
6038 +static struct ethtool_ops fe_ethtool_ops = {
6039 +       .get_settings           = fe_get_settings,
6040 +       .set_settings           = fe_set_settings,
6041 +       .get_drvinfo            = fe_get_drvinfo,
6042 +       .get_msglevel           = fe_get_msglevel,
6043 +       .set_msglevel           = fe_set_msglevel,
6044 +       .nway_reset             = fe_nway_reset,
6045 +       .get_link               = fe_get_link,
6046 +       .get_ringparam          = fe_get_ringparam,
6047 +       .get_coalesce           = fe_get_coalesce,
6048 +       .set_coalesce           = fe_set_coalesce,
6049 +};
6050 +
6051 +void fe_set_ethtool_ops(struct net_device *netdev)
6052 +{
6053 +       struct fe_priv *priv = netdev_priv(netdev);
6054 +       struct fe_soc_data *soc = priv->soc;
6055 +
6056 +       if (soc->reg_table[FE_REG_FE_COUNTER_BASE]) {
6057 +               fe_ethtool_ops.get_strings = fe_get_strings;
6058 +               fe_ethtool_ops.get_sset_count = fe_get_sset_count;
6059 +               fe_ethtool_ops.get_ethtool_stats = fe_get_ethtool_stats;
6060 +       }
6061 +
6062 +       SET_ETHTOOL_OPS(netdev, &fe_ethtool_ops);
6063 +}
6064 Index: linux-3.14.18/drivers/net/ethernet/ralink/ralink_ethtool.h
6065 ===================================================================
6066 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
6067 +++ linux-3.14.18/drivers/net/ethernet/ralink/ralink_ethtool.h  2014-10-29 20:25:55.433357519 +0100
6068 @@ -0,0 +1,25 @@
6069 +/*
6070 + *   This program is free software; you can redistribute it and/or modify
6071 + *   it under the terms of the GNU General Public License as published by
6072 + *   the Free Software Foundation; version 2 of the License
6073 + *
6074 + *   This program is distributed in the hope that it will be useful,
6075 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
6076 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6077 + *   GNU General Public License for more details.
6078 + *
6079 + *   You should have received a copy of the GNU General Public License
6080 + *   along with this program; if not, write to the Free Software
6081 + *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
6082 + *
6083 + *   Copyright (C) 2009-2013 Michael Lee <igvtee@gmail.com>
6084 + */
6085 +
6086 +#ifndef FE_ETHTOOL_H
6087 +#define FE_ETHTOOL_H
6088 +
6089 +#include <linux/ethtool.h>
6090 +
6091 +void fe_set_ethtool_ops(struct net_device *netdev);
6092 +
6093 +#endif /* FE_ETHTOOL_H */