1 --- a/arch/mips/include/asm/mach-ralink/mt7620.h
2 +++ b/arch/mips/include/asm/mach-ralink/mt7620.h
4 #define SYSC_REG_CPLL_CONFIG0 0x54
5 #define SYSC_REG_CPLL_CONFIG1 0x58
7 -#define MT7620N_CHIP_NAME0 0x33365452
8 -#define MT7620N_CHIP_NAME1 0x20203235
10 -#define MT7620A_CHIP_NAME0 0x3637544d
11 -#define MT7620A_CHIP_NAME1 0x20203032
12 +#define MT7620_CHIP_NAME0 0x3637544d
13 +#define MT7620_CHIP_NAME1 0x20203032
15 #define CHIP_REV_PKG_MASK 0x1
16 #define CHIP_REV_PKG_SHIFT 16
17 --- a/arch/mips/ralink/mt7620.c
18 +++ b/arch/mips/ralink/mt7620.c
19 @@ -167,22 +167,27 @@ void prom_soc_init(struct ralink_soc_inf
25 n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
26 n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
27 + rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
28 + bga = (rev >> CHIP_REV_PKG_SHIFT) & CHIP_REV_PKG_MASK;
30 - if (n0 == MT7620N_CHIP_NAME0 && n1 == MT7620N_CHIP_NAME1) {
32 - soc_info->compatible = "ralink,mt7620n-soc";
33 - } else if (n0 == MT7620A_CHIP_NAME0 && n1 == MT7620A_CHIP_NAME1) {
34 + if (n0 != MT7620_CHIP_NAME0 || n1 != MT7620_CHIP_NAME1)
35 + panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
39 soc_info->compatible = "ralink,mt7620a-soc";
41 - panic("mt7620: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
43 + soc_info->compatible = "ralink,mt7620n-soc";
45 + panic("mt7620n is only supported for non pci kernels");
49 - rev = __raw_readl(sysc + SYSC_REG_CHIP_REV);
51 snprintf(soc_info->sys_type, RAMIPS_SYS_TYPE_LEN,
52 "Ralink %s ver:%u eco:%u",