1 --- a/drivers/spi/spi-rt2880.c
2 +++ b/drivers/spi/spi-rt2880.c
5 #include <linux/reset.h>
6 #include <linux/spi/spi.h>
7 +#include <linux/of_device.h>
8 #include <linux/platform_device.h>
10 +#include <ralink_regs.h>
12 #define DRIVER_NAME "spi-rt2880"
13 /* only one slave is supported*/
14 #define RALINK_NUM_CHIPSELECTS 1
16 /* SPIFIFOSTAT register bit field */
17 #define SPIFIFOSTAT_TXFULL BIT(17)
19 +#define MT7621_SPI_TRANS 0x00
20 +#define SPITRANS_BUSY BIT(16)
21 +#define MT7621_SPI_OPCODE 0x04
22 +#define MT7621_SPI_DATA0 0x08
23 +#define SPI_CTL_TX_RX_CNT_MASK 0xff
24 +#define SPI_CTL_START BIT(8)
25 +#define MT7621_SPI_POLAR 0x38
26 +#define MT7621_SPI_MASTER 0x28
27 +#define MT7621_SPI_SPACE 0x3c
31 +struct rt2880_spi_ops {
32 + void (*init_hw)(struct rt2880_spi *rs);
33 + void (*set_cs)(struct rt2880_spi *rs, int enable);
34 + int (*baudrate_set)(struct spi_device *spi, unsigned int speed);
35 + unsigned int (*write_read)(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer);
39 struct spi_master *master;
41 @@ -70,6 +92,8 @@ struct rt2880_spi {
46 + struct rt2880_spi_ops *ops;
49 static inline struct rt2880_spi *spidev_to_rt2880_spi(struct spi_device *spi)
50 @@ -149,6 +173,17 @@ static int rt2880_spi_baudrate_set(struc
54 +static int mt7621_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
56 +/* u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
58 + // set default clock to hclk/5
59 + master &= ~(0xfff << 16);
60 + master |= 0x3 << 16;
66 * called only when no transfer is active on the bus
68 @@ -164,7 +199,7 @@ rt2880_spi_setup_transfer(struct spi_dev
70 if (rs->speed != speed) {
71 dev_dbg(&spi->dev, "speed_hz:%u\n", speed);
72 - rc = rt2880_spi_baudrate_set(spi, speed);
73 + rc = rs->ops->baudrate_set(spi, speed);
77 @@ -180,6 +215,17 @@ static void rt2880_spi_set_cs(struct rt2
78 rt2880_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
81 +static void mt7621_spi_set_cs(struct rt2880_spi *rs, int enable)
83 + u32 polar = rt2880_spi_read(rs, MT7621_SPI_POLAR);
89 + rt2880_spi_write(rs, MT7621_SPI_POLAR, polar);
92 static inline int rt2880_spi_wait_till_ready(struct rt2880_spi *rs)
95 @@ -198,8 +244,26 @@ static inline int rt2880_spi_wait_till_r
99 +static inline int mt7621_spi_wait_till_ready(struct rt2880_spi *rs)
103 + for (i = 0; i < RALINK_SPI_WAIT_MAX_LOOP; i++) {
106 + status = rt2880_spi_read(rs, MT7621_SPI_TRANS);
107 + if ((status & SPITRANS_BUSY) == 0) {
118 -rt2880_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
119 +rt2880_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
121 struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
123 @@ -239,6 +303,100 @@ out:
128 +mt7621_spi_write_read(struct spi_device *spi, struct list_head *list, struct spi_transfer *xfer)
130 + struct rt2880_spi *rs = spidev_to_rt2880_spi(spi);
131 + struct spi_transfer *next = NULL;
132 + const u8 *tx = xfer->tx_buf;
135 + int len = xfer->len;
140 + if (!list_is_last(&xfer->transfer_list, list)) {
141 + next = list_entry(xfer->transfer_list.next, struct spi_transfer, transfer_list);
145 + trans = rt2880_spi_read(rs, MT7621_SPI_TRANS);
146 + trans &= ~SPI_CTL_TX_RX_CNT_MASK;
149 + u32 data0 = 0, opcode = 0;
151 + switch (xfer->len) {
153 + data0 |= tx[7] << 24;
155 + data0 |= tx[6] << 16;
157 + data0 |= tx[5] << 8;
161 + opcode |= tx[3] << 8;
163 + opcode |= tx[2] << 16;
165 + opcode |= tx[1] << 24;
171 + dev_err(&spi->dev, "trying to write too many bytes: %d\n", next->len);
175 + rt2880_spi_write(rs, MT7621_SPI_DATA0, data0);
176 + rt2880_spi_write(rs, MT7621_SPI_OPCODE, opcode);
177 + trans |= xfer->len;
181 + trans |= (next->len << 4);
182 + rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
183 + trans |= SPI_CTL_START;
184 + rt2880_spi_write(rs, MT7621_SPI_TRANS, trans);
186 + mt7621_spi_wait_till_ready(rs);
189 + u32 data0 = rt2880_spi_read(rs, MT7621_SPI_DATA0);
190 + u32 opcode = rt2880_spi_read(rs, MT7621_SPI_OPCODE);
192 + switch (next->len) {
194 + rx[7] = (opcode >> 24) & 0xff;
196 + rx[6] = (opcode >> 16) & 0xff;
198 + rx[5] = (opcode >> 8) & 0xff;
200 + rx[4] = opcode & 0xff;
202 + rx[3] = (data0 >> 24) & 0xff;
204 + rx[2] = (data0 >> 16) & 0xff;
206 + rx[1] = (data0 >> 8) & 0xff;
208 + rx[0] = data0 & 0xff;
212 + dev_err(&spi->dev, "trying to read too many bytes: %d\n", next->len);
221 static int rt2880_spi_transfer_one_message(struct spi_master *master,
222 struct spi_message *m)
224 @@ -280,25 +438,25 @@ static int rt2880_spi_transfer_one_messa
228 - rt2880_spi_set_cs(rs, 1);
229 + rs->ops->set_cs(rs, 1);
234 - m->actual_length += rt2880_spi_write_read(spi, t);
235 + m->actual_length += rs->ops->write_read(spi, &m->transfers, t);
238 udelay(t->delay_usecs);
241 - rt2880_spi_set_cs(rs, 0);
242 + rs->ops->set_cs(rs, 0);
249 - rt2880_spi_set_cs(rs, 0);
250 + rs->ops->set_cs(rs, 0);
253 spi_finalize_current_message(master);
254 @@ -334,8 +492,41 @@ static void rt2880_spi_reset(struct rt28
255 rt2880_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
258 +static void mt7621_spi_reset(struct rt2880_spi *rs)
260 + u32 master = rt2880_spi_read(rs, MT7621_SPI_MASTER);
262 + master &= ~(0xfff << 16);
266 + rt2880_spi_write(rs, MT7621_SPI_MASTER, master);
269 +static struct rt2880_spi_ops spi_ops[] = {
271 + .init_hw = rt2880_spi_reset,
272 + .set_cs = rt2880_spi_set_cs,
273 + .baudrate_set = rt2880_spi_baudrate_set,
274 + .write_read = rt2880_spi_write_read,
276 + .init_hw = mt7621_spi_reset,
277 + .set_cs = mt7621_spi_set_cs,
278 + .baudrate_set = mt7621_spi_baudrate_set,
279 + .write_read = mt7621_spi_write_read,
283 +static const struct of_device_id rt2880_spi_match[] = {
284 + { .compatible = "ralink,rt2880-spi", .data = &spi_ops[0]},
285 + { .compatible = "ralink,mt7621-spi", .data = &spi_ops[1] },
288 +MODULE_DEVICE_TABLE(of, rt2880_spi_match);
290 static int rt2880_spi_probe(struct platform_device *pdev)
292 + const struct of_device_id *match;
293 struct spi_master *master;
294 struct rt2880_spi *rs;
296 @@ -344,6 +535,10 @@ static int rt2880_spi_probe(struct platf
300 + match = of_match_device(rt2880_spi_match, &pdev->dev);
304 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
305 base = devm_ioremap_resource(&pdev->dev, r);
307 @@ -382,12 +577,13 @@ static int rt2880_spi_probe(struct platf
310 rs->sys_freq = clk_get_rate(rs->clk);
311 + rs->ops = (struct rt2880_spi_ops *) match->data;
312 dev_dbg(&pdev->dev, "sys_freq: %u\n", rs->sys_freq);
313 spin_lock_irqsave(&rs->lock, flags);
315 device_reset(&pdev->dev);
317 - rt2880_spi_reset(rs);
318 + rs->ops->init_hw(rs);
320 return spi_register_master(master);
322 @@ -408,12 +604,6 @@ static int rt2880_spi_remove(struct plat
324 MODULE_ALIAS("platform:" DRIVER_NAME);
326 -static const struct of_device_id rt2880_spi_match[] = {
327 - { .compatible = "ralink,rt2880-spi" },
330 -MODULE_DEVICE_TABLE(of, rt2880_spi_match);
332 static struct platform_driver rt2880_spi_driver = {