1 /**************************************************************************
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 **************************************************************************
30 * May 2007 Bruce Chang
33 * May 2009 Bruce Chang
34 * support RT2880/RT3883 PCIe
36 * May 2011 Bruce Chang
37 * support RT6855/MT7620 PCIe
39 **************************************************************************
42 #include <linux/types.h>
43 #include <linux/pci.h>
44 #include <linux/kernel.h>
45 #include <linux/slab.h>
46 #include <linux/version.h>
49 #include <asm/mips-cm.h>
50 #include <linux/init.h>
51 #include <linux/module.h>
52 #include <linux/delay.h>
54 #include <linux/of_pci.h>
55 #include <linux/of_irq.h>
56 #include <linux/platform_device.h>
58 #include <ralink_regs.h>
60 extern void pcie_phy_init(void);
61 extern void chk_phy_pll(void);
64 * These functions and structures provide the BIOS scan and mapping of the PCI
68 #define CONFIG_PCIE_PORT0
69 #define CONFIG_PCIE_PORT1
70 #define CONFIG_PCIE_PORT2
71 #define RALINK_PCIE0_CLK_EN (1<<24)
72 #define RALINK_PCIE1_CLK_EN (1<<25)
73 #define RALINK_PCIE2_CLK_EN (1<<26)
75 #define RALINK_PCI_CONFIG_ADDR 0x20
76 #define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
77 #define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
78 #define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
79 #define RALINK_PCIE0_RST (1<<24)
80 #define RALINK_PCIE1_RST (1<<25)
81 #define RALINK_PCIE2_RST (1<<26)
82 #define RALINK_SYSCTL_BASE 0xBE000000
84 #define RALINK_PCI_PCICFG_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x0000)
85 #define RALINK_PCI_PCIMSK_ADDR *(volatile u32 *)(RALINK_PCI_BASE + 0x000C)
86 #define RALINK_PCI_BASE 0xBE140000
88 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
89 #define RT6855_PCIE0_OFFSET 0x2000
90 #define RT6855_PCIE1_OFFSET 0x3000
91 #define RT6855_PCIE2_OFFSET 0x4000
93 #define RALINK_PCI0_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0010)
94 #define RALINK_PCI0_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0018)
95 #define RALINK_PCI0_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0030)
96 #define RALINK_PCI0_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0034)
97 #define RALINK_PCI0_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0038)
98 #define RALINK_PCI0_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0050)
99 #define RALINK_PCI0_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0060)
100 #define RALINK_PCI0_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE0_OFFSET + 0x0064)
102 #define RALINK_PCI1_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0010)
103 #define RALINK_PCI1_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0018)
104 #define RALINK_PCI1_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0030)
105 #define RALINK_PCI1_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0034)
106 #define RALINK_PCI1_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0038)
107 #define RALINK_PCI1_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0050)
108 #define RALINK_PCI1_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0060)
109 #define RALINK_PCI1_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE1_OFFSET + 0x0064)
111 #define RALINK_PCI2_BAR0SETUP_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0010)
112 #define RALINK_PCI2_IMBASEBAR0_ADDR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0018)
113 #define RALINK_PCI2_ID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0030)
114 #define RALINK_PCI2_CLASS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0034)
115 #define RALINK_PCI2_SUBID *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0038)
116 #define RALINK_PCI2_STATUS *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0050)
117 #define RALINK_PCI2_DERR *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0060)
118 #define RALINK_PCI2_ECRC *(volatile u32 *)(RALINK_PCI_BASE + RT6855_PCIE2_OFFSET + 0x0064)
120 #define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
121 #define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
124 #define MV_WRITE(ofs, data) \
125 *(volatile u32 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le32(data)
126 #define MV_READ(ofs, data) \
127 *(data) = le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
128 #define MV_READ_DATA(ofs) \
129 le32_to_cpu(*(volatile u32 *)(RALINK_PCI_BASE+(ofs)))
131 #define MV_WRITE_16(ofs, data) \
132 *(volatile u16 *)(RALINK_PCI_BASE+(ofs)) = cpu_to_le16(data)
133 #define MV_READ_16(ofs, data) \
134 *(data) = le16_to_cpu(*(volatile u16 *)(RALINK_PCI_BASE+(ofs)))
136 #define MV_WRITE_8(ofs, data) \
137 *(volatile u8 *)(RALINK_PCI_BASE+(ofs)) = data
138 #define MV_READ_8(ofs, data) \
139 *(data) = *(volatile u8 *)(RALINK_PCI_BASE+(ofs))
143 #define RALINK_PCI_MM_MAP_BASE 0x60000000
144 #define RALINK_PCI_IO_MAP_BASE 0x1e160000
146 #define RALINK_SYSTEM_CONTROL_BASE 0xbe000000
148 #define ASSERT_SYSRST_PCIE(val) do { \
149 if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
150 RALINK_RSTCTRL |= val; \
152 RALINK_RSTCTRL &= ~val; \
154 #define DEASSERT_SYSRST_PCIE(val) do { \
155 if (*(unsigned int *)(0xbe00000c) == 0x00030101) \
156 RALINK_RSTCTRL &= ~val; \
158 RALINK_RSTCTRL |= val; \
160 #define RALINK_SYSCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x14)
161 #define RALINK_CLKCFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x30)
162 #define RALINK_RSTCTRL *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x34)
163 #define RALINK_GPIOMODE *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x60)
164 #define RALINK_PCIE_CLK_GEN *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x7c)
165 #define RALINK_PCIE_CLK_GEN1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x80)
166 #define PPLL_CFG1 *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0x9c)
167 #define PPLL_DRV *(unsigned int *)(RALINK_SYSTEM_CONTROL_BASE + 0xa0)
169 #define RALINK_PCI_HOST_MODE_EN (1<<7)
170 #define RALINK_PCIE_RC_MODE_EN (1<<8)
172 #define RALINK_PCIE_RST (1<<23)
173 #define RALINK_PCI_RST (1<<24)
175 #define RALINK_PCI_CLK_EN (1<<19)
176 #define RALINK_PCIE_CLK_EN (1<<21)
177 //RALINK_GPIOMODE bit
178 #define PCI_SLOTx2 (1<<11)
179 #define PCI_SLOTx1 (2<<11)
181 #define PDRV_SW_SET (1<<31)
182 #define LC_CKDRVPD_ (1<<19)
184 #define MEMORY_BASE 0x0
185 static int pcie_link_status = 0;
187 #define PCI_ACCESS_READ_1 0
188 #define PCI_ACCESS_READ_2 1
189 #define PCI_ACCESS_READ_4 2
190 #define PCI_ACCESS_WRITE_1 3
191 #define PCI_ACCESS_WRITE_2 4
192 #define PCI_ACCESS_WRITE_4 5
194 static int pcie_irq[3];
196 static int config_access(unsigned char access_type, struct pci_bus *bus,
197 unsigned int devfn, unsigned int where, u32 * data)
199 unsigned int slot = PCI_SLOT(devfn);
200 u8 func = PCI_FUNC(devfn);
201 uint32_t address_reg, data_reg;
202 unsigned int address;
204 address_reg = RALINK_PCI_CONFIG_ADDR;
205 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
207 address = (((where&0xF00)>>8)<<24) |(bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
208 MV_WRITE(address_reg, address);
210 switch(access_type) {
211 case PCI_ACCESS_WRITE_1:
212 MV_WRITE_8(data_reg+(where&0x3), *data);
214 case PCI_ACCESS_WRITE_2:
215 MV_WRITE_16(data_reg+(where&0x3), *data);
217 case PCI_ACCESS_WRITE_4:
218 MV_WRITE(data_reg, *data);
220 case PCI_ACCESS_READ_1:
221 MV_READ_8( data_reg+(where&0x3), data);
223 case PCI_ACCESS_READ_2:
224 MV_READ_16(data_reg+(where&0x3), data);
226 case PCI_ACCESS_READ_4:
227 MV_READ(data_reg, data);
230 printk("no specify access type\n");
237 read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val)
239 return config_access(PCI_ACCESS_READ_1, bus, devfn, (unsigned int)where, (u32 *)val);
243 read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val)
245 return config_access(PCI_ACCESS_READ_2, bus, devfn, (unsigned int)where, (u32 *)val);
249 read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val)
251 return config_access(PCI_ACCESS_READ_4, bus, devfn, (unsigned int)where, (u32 *)val);
255 write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val)
257 if (config_access(PCI_ACCESS_WRITE_1, bus, devfn, (unsigned int)where, (u32 *)&val))
260 return PCIBIOS_SUCCESSFUL;
264 write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val)
266 if (config_access(PCI_ACCESS_WRITE_2, bus, devfn, where, (u32 *)&val))
269 return PCIBIOS_SUCCESSFUL;
273 write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val)
275 if (config_access(PCI_ACCESS_WRITE_4, bus, devfn, where, &val))
278 return PCIBIOS_SUCCESSFUL;
283 pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
287 return read_config_byte(bus, devfn, where, (u8 *) val);
289 return read_config_word(bus, devfn, where, (u16 *) val);
291 return read_config_dword(bus, devfn, where, val);
296 pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
300 return write_config_byte(bus, devfn, where, (u8) val);
302 return write_config_word(bus, devfn, where, (u16) val);
304 return write_config_dword(bus, devfn, where, val);
308 struct pci_ops mt7621_pci_ops= {
309 .read = pci_config_read,
310 .write = pci_config_write,
313 static struct resource mt7621_res_pci_mem1 = {
315 .start = RALINK_PCI_MM_MAP_BASE,
316 .end = (u32)((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
317 .flags = IORESOURCE_MEM,
319 static struct resource mt7621_res_pci_io1 = {
321 .start = RALINK_PCI_IO_MAP_BASE,
322 .end = (u32)((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
323 .flags = IORESOURCE_IO,
326 static struct pci_controller mt7621_controller = {
327 .pci_ops = &mt7621_pci_ops,
328 .mem_resource = &mt7621_res_pci_mem1,
329 .io_resource = &mt7621_res_pci_io1,
330 .mem_offset = 0x00000000UL,
331 .io_offset = 0x00000000UL,
332 .io_map_base = 0xa0000000,
336 read_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long *val)
338 unsigned int address_reg, data_reg, address;
340 address_reg = RALINK_PCI_CONFIG_ADDR;
341 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
342 address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
343 MV_WRITE(address_reg, address);
344 MV_READ(data_reg, val);
349 write_config(unsigned long bus, unsigned long dev, unsigned long func, unsigned long reg, unsigned long val)
351 unsigned int address_reg, data_reg, address;
353 address_reg = RALINK_PCI_CONFIG_ADDR;
354 data_reg = RALINK_PCI_CONFIG_DATA_VIRTUAL_REG;
355 address = (((reg & 0xF00)>>8)<<24) | (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000 ;
356 MV_WRITE(address_reg, address);
357 MV_WRITE(data_reg, val);
363 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
369 if (dev->bus->number == 0) {
370 write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
371 read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
372 printk("BAR0 at slot %d = %x\n", slot, val);
375 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
376 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
377 pci_read_config_word(dev, PCI_COMMAND, &cmd);
378 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
379 pci_write_config_word(dev, PCI_COMMAND, cmd);
381 irq = of_irq_parse_and_map_pci(dev, slot, pin);
383 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
388 set_pcie_phy(u32 *addr, int start_b, int bits, int val)
390 // printk("0x%p:", addr);
391 // printk(" %x", *addr);
392 *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
393 *(unsigned int *)(addr) |= val << start_b;
394 // printk(" -> %x\n", *addr);
398 bypass_pipe_rst(void)
400 #if defined (CONFIG_PCIE_PORT0)
402 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
403 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
405 #if defined (CONFIG_PCIE_PORT1)
407 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
408 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
410 #if defined (CONFIG_PCIE_PORT2)
412 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
413 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
418 set_phy_for_ssc(void)
420 unsigned long reg = (*(volatile u32 *)(RALINK_SYSCTL_BASE + 0x10));
422 reg = (reg >> 6) & 0x7;
423 #if defined (CONFIG_PCIE_PORT0) || defined (CONFIG_PCIE_PORT1)
424 /* Set PCIe Port0 & Port1 PHY to disable SSC */
425 /* Debug Xtal Type */
426 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
427 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
428 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
429 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
430 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
431 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
432 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
433 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
434 printk("***** Xtal 40MHz *****\n");
435 } else { // 25MHz | 20MHz Xtal
436 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
438 printk("***** Xtal 25MHz *****\n");
439 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
440 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
441 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
442 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
443 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
445 printk("***** Xtal 20MHz *****\n");
448 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
449 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
450 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
451 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
452 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
453 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
454 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
455 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
456 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
457 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
459 /* Enable PHY and disable force mode */
460 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
461 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
462 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
463 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
465 #if defined (CONFIG_PCIE_PORT2)
466 /* Set PCIe Port2 PHY to disable SSC */
467 /* Debug Xtal Type */
468 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
469 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
470 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
471 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
472 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
473 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
474 } else { // 25MHz | 20MHz Xtal
475 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
476 if (reg >= 6) { // 25MHz Xtal
477 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
478 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0,31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
479 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0,16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
480 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
481 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16,12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
484 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
485 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
486 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
487 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
488 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
489 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
490 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
491 if(reg <= 5 && reg >= 3) { // 40MHz Xtal
492 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
493 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
495 /* Enable PHY and disable force mode */
496 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
497 set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
501 void setup_cm_memory_region(struct resource *mem_resource)
503 resource_size_t mask;
504 if (mips_cps_numiocu(0)) {
505 /* FIXME: hardware doesn't accept mask values with 1s after
506 0s (e.g. 0xffef), so it would be great to warn if that's
508 mask = ~(mem_resource->end - mem_resource->start);
510 write_gcr_reg1_base(mem_resource->start);
511 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
512 printk("PCI coherence region base: 0x%08lx, mask/settings: 0x%08lx\n",
513 read_gcr_reg1_base(),
514 read_gcr_reg1_mask());
518 static int mt7621_pci_probe(struct platform_device *pdev)
520 unsigned long val = 0;
523 for (i = 0; i < 3; i++)
524 pcie_irq[i] = irq_of_parse_and_map(pdev->dev.of_node, i);
526 iomem_resource.start = 0;
527 iomem_resource.end= ~0;
528 ioport_resource.start= 0;
529 ioport_resource.end = ~0;
531 #if defined (CONFIG_PCIE_PORT0)
532 val = RALINK_PCIE0_RST;
534 #if defined (CONFIG_PCIE_PORT1)
535 val |= RALINK_PCIE1_RST;
537 #if defined (CONFIG_PCIE_PORT2)
538 val |= RALINK_PCIE2_RST;
540 ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
541 printk("pull PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
542 #if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
543 *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
544 *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
546 *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
548 *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
552 *(unsigned int *)(0xbe000060) &= ~0x00000c00;
554 #if defined (CONFIG_PCIE_PORT0)
555 val = RALINK_PCIE0_RST;
557 #if defined (CONFIG_PCIE_PORT1)
558 val |= RALINK_PCIE1_RST;
560 #if defined (CONFIG_PCIE_PORT2)
561 val |= RALINK_PCIE2_RST;
563 DEASSERT_SYSRST_PCIE(val);
564 printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
566 if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
569 printk("release PCIe RST: RALINK_RSTCTRL = %x\n", RALINK_RSTCTRL);
571 #if defined (CONFIG_PCIE_PORT0)
572 read_config(0, 0, 0, 0x70c, &val);
573 printk("Port 0 N_FTS = %x\n", (unsigned int)val);
575 #if defined (CONFIG_PCIE_PORT1)
576 read_config(0, 1, 0, 0x70c, &val);
577 printk("Port 1 N_FTS = %x\n", (unsigned int)val);
579 #if defined (CONFIG_PCIE_PORT2)
580 read_config(0, 2, 0, 0x70c, &val);
581 printk("Port 2 N_FTS = %x\n", (unsigned int)val);
584 RALINK_RSTCTRL = (RALINK_RSTCTRL | RALINK_PCIE_RST);
585 RALINK_SYSCFG1 &= ~(0x30);
586 RALINK_SYSCFG1 |= (2<<4);
587 RALINK_PCIE_CLK_GEN &= 0x7fffffff;
588 RALINK_PCIE_CLK_GEN1 &= 0x80ffffff;
589 RALINK_PCIE_CLK_GEN1 |= 0xa << 24;
590 RALINK_PCIE_CLK_GEN |= 0x80000000;
592 RALINK_RSTCTRL = (RALINK_RSTCTRL & ~RALINK_PCIE_RST);
595 #if defined GPIO_PERST /* add GPIO control instead of PERST_N */ /*chhung*/
596 *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
599 RALINK_PCI_PCICFG_ADDR &= ~(1<<1); //de-assert PERST
605 #if defined (CONFIG_PCIE_PORT0)
606 if(( RALINK_PCI0_STATUS & 0x1) == 0)
608 printk("PCIE0 no card, disable it(RST&CLK)\n");
609 ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
610 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE0_CLK_EN);
611 pcie_link_status &= ~(1<<0);
613 pcie_link_status |= 1<<0;
614 RALINK_PCI_PCIMSK_ADDR |= (1<<20); // enable pcie1 interrupt
617 #if defined (CONFIG_PCIE_PORT1)
618 if(( RALINK_PCI1_STATUS & 0x1) == 0)
620 printk("PCIE1 no card, disable it(RST&CLK)\n");
621 ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
622 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE1_CLK_EN);
623 pcie_link_status &= ~(1<<1);
625 pcie_link_status |= 1<<1;
626 RALINK_PCI_PCIMSK_ADDR |= (1<<21); // enable pcie1 interrupt
629 #if defined (CONFIG_PCIE_PORT2)
630 if (( RALINK_PCI2_STATUS & 0x1) == 0) {
631 printk("PCIE2 no card, disable it(RST&CLK)\n");
632 ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
633 RALINK_CLKCFG1 = (RALINK_CLKCFG1 & ~RALINK_PCIE2_CLK_EN);
634 pcie_link_status &= ~(1<<2);
636 pcie_link_status |= 1<<2;
637 RALINK_PCI_PCIMSK_ADDR |= (1<<22); // enable pcie2 interrupt
640 if (pcie_link_status == 0)
644 pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
654 switch(pcie_link_status) {
656 RALINK_PCI_PCICFG_ADDR &= ~0x00ff0000;
657 RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
658 RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
661 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
662 RALINK_PCI_PCICFG_ADDR |= 0x1 << 16; //port0
663 RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
664 RALINK_PCI_PCICFG_ADDR |= 0x0 << 24; //port2
667 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
668 RALINK_PCI_PCICFG_ADDR |= 0x0 << 16; //port0
669 RALINK_PCI_PCICFG_ADDR |= 0x2 << 20; //port1
670 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
673 RALINK_PCI_PCICFG_ADDR &= ~0x0fff0000;
674 RALINK_PCI_PCICFG_ADDR |= 0x2 << 16; //port0
675 RALINK_PCI_PCICFG_ADDR |= 0x0 << 20; //port1
676 RALINK_PCI_PCICFG_ADDR |= 0x1 << 24; //port2
679 printk(" -> %x\n", RALINK_PCI_PCICFG_ADDR);
680 //printk(" RALINK_PCI_ARBCTL = %x\n", RALINK_PCI_ARBCTL);
683 ioport_resource.start = mt7621_res_pci_io1.start;
684 ioport_resource.end = mt7621_res_pci_io1.end;
687 RALINK_PCI_MEMBASE = 0xffffffff; //RALINK_PCI_MM_MAP_BASE;
688 RALINK_PCI_IOBASE = RALINK_PCI_IO_MAP_BASE;
690 #if defined (CONFIG_PCIE_PORT0)
692 if((pcie_link_status & 0x1) != 0) {
693 RALINK_PCI0_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
694 RALINK_PCI0_IMBASEBAR0_ADDR = MEMORY_BASE;
695 RALINK_PCI0_CLASS = 0x06040001;
696 printk("PCIE0 enabled\n");
699 #if defined (CONFIG_PCIE_PORT1)
701 if ((pcie_link_status & 0x2) != 0) {
702 RALINK_PCI1_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
703 RALINK_PCI1_IMBASEBAR0_ADDR = MEMORY_BASE;
704 RALINK_PCI1_CLASS = 0x06040001;
705 printk("PCIE1 enabled\n");
708 #if defined (CONFIG_PCIE_PORT2)
710 if ((pcie_link_status & 0x4) != 0) {
711 RALINK_PCI2_BAR0SETUP_ADDR = 0x7FFF0001; //open 7FFF:2G; ENABLE
712 RALINK_PCI2_IMBASEBAR0_ADDR = MEMORY_BASE;
713 RALINK_PCI2_CLASS = 0x06040001;
714 printk("PCIE2 enabled\n");
719 switch(pcie_link_status) {
721 read_config(0, 2, 0, 0x4, &val);
722 write_config(0, 2, 0, 0x4, val|0x4);
723 // write_config(0, 1, 0, 0x4, val|0x7);
724 read_config(0, 2, 0, 0x70c, &val);
727 write_config(0, 2, 0, 0x70c, val);
731 read_config(0, 1, 0, 0x4, &val);
732 write_config(0, 1, 0, 0x4, val|0x4);
733 // write_config(0, 1, 0, 0x4, val|0x7);
734 read_config(0, 1, 0, 0x70c, &val);
737 write_config(0, 1, 0, 0x70c, val);
739 read_config(0, 0, 0, 0x4, &val);
740 write_config(0, 0, 0, 0x4, val|0x4); //bus master enable
741 // write_config(0, 0, 0, 0x4, val|0x7); //bus master enable
742 read_config(0, 0, 0, 0x70c, &val);
745 write_config(0, 0, 0, 0x70c, val);
748 pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
749 setup_cm_memory_region(mt7621_controller.mem_resource);
750 register_pci_controller(&mt7621_controller);
755 int pcibios_plat_dev_init(struct pci_dev *dev)
760 static const struct of_device_id mt7621_pci_ids[] = {
761 { .compatible = "mediatek,mt7621-pci" },
764 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
766 static struct platform_driver mt7621_pci_driver = {
767 .probe = mt7621_pci_probe,
769 .name = "mt7621-pci",
770 .of_match_table = of_match_ptr(mt7621_pci_ids),
774 static int __init mt7621_pci_init(void)
776 return platform_driver_register(&mt7621_pci_driver);
779 arch_initcall(mt7621_pci_init);