2 #include <linux/kernel.h>
3 #include <linux/slab.h>
6 #ifdef CONFIG_PROJECT_7621
7 #include "mtk-phy-7621.h"
9 #ifdef CONFIG_PROJECT_PHY
10 static struct u3phy_operator project_operators = {
12 .change_pipe_phase = phy_change_pipe_phase,
13 .eyescan_init = eyescan_init,
14 .eyescan = phy_eyescan,
15 .u2_slew_rate_calibration = u2_slew_rate_calibration,
20 PHY_INT32 u3phy_init(){
21 #ifndef CONFIG_PROJECT_PHY
22 PHY_INT32 u3phy_version;
29 u3phy = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
30 #if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
31 u3phy_p1 = kmalloc(sizeof(struct u3phy_info), GFP_NOIO);
33 #ifdef CONFIG_U3_PHY_GPIO_SUPPORT
34 u3phy->phyd_version_addr = 0x2000e4;
35 #if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
36 u3phy_p1->phyd_version_addr = 0x2000e4;
39 u3phy->phyd_version_addr = U3_PHYD_B2_BASE + 0xe4;
40 #if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
41 u3phy_p1->phyd_version_addr = U3_PHYD_B2_BASE_P1 + 0xe4;
45 #ifdef CONFIG_PROJECT_PHY
47 u3phy->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE;
48 u3phy->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE;
49 u3phy->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE;
50 u3phy->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE;
51 u3phy->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE;
52 u3phy->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
53 u3phy->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
54 u3phy_ops = &project_operators;
56 #if defined (CONFIG_USB_MT7621_XHCI_PLATFORM)
57 u3phy_p1->u2phy_regs = (struct u2phy_reg *)U2_PHY_BASE_P1;
58 u3phy_p1->u3phyd_regs = (struct u3phyd_reg *)U3_PHYD_BASE_P1;
59 u3phy_p1->u3phyd_bank2_regs = (struct u3phyd_bank2_reg *)U3_PHYD_B2_BASE_P1;
60 u3phy_p1->u3phya_regs = (struct u3phya_reg *)U3_PHYA_BASE_P1;
61 u3phy_p1->u3phya_da_regs = (struct u3phya_da_reg *)U3_PHYA_DA_BASE_P1;
62 u3phy_p1->sifslv_chip_regs = (struct sifslv_chip_reg *)SIFSLV_CHIP_BASE;
63 u3phy_p1->sifslv_fm_regs = (struct sifslv_fm_feg *)SIFSLV_FM_FEG_BASE;
70 PHY_INT32 U3PhyWriteField8(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
74 cur_value = U3PhyReadReg8(addr);
75 new_value = (cur_value & (~mask)) | (value << offset);
77 U3PhyWriteReg8(addr, new_value);
81 PHY_INT32 U3PhyWriteField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask, PHY_INT32 value){
85 cur_value = U3PhyReadReg32(addr);
86 new_value = (cur_value & (~mask)) | ((value << offset) & mask);
87 U3PhyWriteReg32(addr, new_value);
93 PHY_INT32 U3PhyReadField8(PHY_INT32 addr,PHY_INT32 offset,PHY_INT32 mask){
95 return ((U3PhyReadReg8(addr) & mask) >> offset);
98 PHY_INT32 U3PhyReadField32(PHY_INT32 addr, PHY_INT32 offset, PHY_INT32 mask){
100 return ((U3PhyReadReg32(addr) & mask) >> offset);