1 #include <linux/ioport.h>
3 #include <rt305x_regs.h>
4 #include <rt305x_esw_platform.h>
6 #define RT305X_ESW_REG_FCT0 0x08
7 #define RT305X_ESW_REG_PFC1 0x14
8 #define RT305X_ESW_REG_PVIDC(_n) (0x48 + 4 * (_n))
9 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
10 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
11 #define RT305X_ESW_REG_FPA 0x84
12 #define RT305X_ESW_REG_SOCPC 0x8c
13 #define RT305X_ESW_REG_POC1 0x90
14 #define RT305X_ESW_REG_POC2 0x94
15 #define RT305X_ESW_REG_POC3 0x98
16 #define RT305X_ESW_REG_SGC 0x9c
17 #define RT305X_ESW_REG_PCR0 0xc0
18 #define RT305X_ESW_REG_PCR1 0xc4
19 #define RT305X_ESW_REG_FPA2 0xc8
20 #define RT305X_ESW_REG_FCT2 0xcc
21 #define RT305X_ESW_REG_SGC2 0xe4
23 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
24 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
25 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
27 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
29 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
33 struct rt305x_esw_platform_data *pdata;
34 spinlock_t reg_rw_lock;
38 rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
40 __raw_writel(val, esw->base + reg);
44 rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
46 return __raw_readl(esw->base + reg);
50 rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
55 t = __raw_readl(esw->base + reg) & ~mask;
56 __raw_writel(t | val, esw->base + reg);
60 rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
65 spin_lock_irqsave(&esw->reg_rw_lock, flags);
66 rt305x_esw_rmw_raw(esw, reg, mask, val);
67 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
71 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
74 unsigned long t_start = jiffies;
78 if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
79 RT305X_ESW_PCR1_WT_DONE))
81 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
89 (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
90 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
91 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
96 if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
97 RT305X_ESW_PCR1_WT_DONE)
100 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
107 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
112 rt305x_esw_hw_init(struct rt305x_esw *esw)
116 /* vodoo from original driver */
117 rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
118 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
119 rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
120 rt305x_esw_wr(esw, 0x00002001, RT305X_ESW_REG_VLANI(0));
121 rt305x_esw_wr(esw, 0x00007f7f, RT305X_ESW_REG_POC1);
122 rt305x_esw_wr(esw, 0x00007f3f, RT305X_ESW_REG_POC3);
123 rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
124 rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
125 rt305x_esw_wr(esw, 0x02404040, RT305X_ESW_REG_SOCPC);
126 rt305x_esw_wr(esw, 0x00001002, RT305X_ESW_REG_PVIDC(2));
127 rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
128 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
130 rt305x_mii_write(esw, 0, 31, 0x8000);
131 for (i = 0; i < 5; i++) {
132 /* TX10 waveform coefficient */
133 rt305x_mii_write(esw, i, 0, 0x3100);
134 /* TX10 waveform coefficient */
135 rt305x_mii_write(esw, i, 26, 0x1601);
136 /* TX100/TX10 AD/DA current bias */
137 rt305x_mii_write(esw, i, 29, 0x7058);
138 /* TX100 slew rate control */
139 rt305x_mii_write(esw, i, 30, 0x0018);
143 /* select global register */
144 rt305x_mii_write(esw, 0, 31, 0x0);
145 /* tune TP_IDL tail and head waveform */
146 rt305x_mii_write(esw, 0, 22, 0x052f);
147 /* set TX10 signal amplitude threshold to minimum */
148 rt305x_mii_write(esw, 0, 17, 0x0fe0);
149 /* set squelch amplitude to higher threshold */
150 rt305x_mii_write(esw, 0, 18, 0x40ba);
151 /* longer TP_IDL tail length */
152 rt305x_mii_write(esw, 0, 14, 0x65);
153 /* select local register */
154 rt305x_mii_write(esw, 0, 31, 0x8000);
156 /* set default vlan */
157 rt305x_esw_wr(esw, 0x2001, RT305X_ESW_REG_VLANI(0));
158 rt305x_esw_wr(esw, 0x504f, RT305X_ESW_REG_VMSC(0));
162 rt305x_esw_probe(struct platform_device *pdev)
164 struct rt305x_esw_platform_data *pdata;
165 struct rt305x_esw *esw;
166 struct resource *res;
169 pdata = pdev->dev.platform_data;
173 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
175 dev_err(&pdev->dev, "no memory resource found\n");
179 esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
181 dev_err(&pdev->dev, "no memory for private data\n");
185 esw->base = ioremap(res->start, resource_size(res));
187 dev_err(&pdev->dev, "ioremap failed\n");
192 platform_set_drvdata(pdev, esw);
195 spin_lock_init(&esw->reg_rw_lock);
196 rt305x_esw_hw_init(esw);
206 rt305x_esw_remove(struct platform_device *pdev)
208 struct rt305x_esw *esw;
210 esw = platform_get_drvdata(pdev);
212 platform_set_drvdata(pdev, NULL);
220 static struct platform_driver rt305x_esw_driver = {
221 .probe = rt305x_esw_probe,
222 .remove = rt305x_esw_remove,
224 .name = "rt305x-esw",
225 .owner = THIS_MODULE,
230 rt305x_esw_init(void)
232 return platform_driver_register(&rt305x_esw_driver);
236 rt305x_esw_exit(void)
238 platform_driver_unregister(&rt305x_esw_driver);