1 #include <linux/ioport.h>
3 #include <rt305x_regs.h>
4 #include <rt305x_esw_platform.h>
6 #define RT305X_ESW_REG_FCT0 0x08
7 #define RT305X_ESW_REG_PFC1 0x14
8 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
9 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
10 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
11 #define RT305X_ESW_REG_FPA 0x84
12 #define RT305X_ESW_REG_SOCPC 0x8c
13 #define RT305X_ESW_REG_POC1 0x90
14 #define RT305X_ESW_REG_POC2 0x94
15 #define RT305X_ESW_REG_POC3 0x98
16 #define RT305X_ESW_REG_SGC 0x9c
17 #define RT305X_ESW_REG_PCR0 0xc0
18 #define RT305X_ESW_REG_PCR1 0xc4
19 #define RT305X_ESW_REG_FPA2 0xc8
20 #define RT305X_ESW_REG_FCT2 0xcc
21 #define RT305X_ESW_REG_SGC2 0xe4
22 #define RT305X_ESW_REG_P0LED 0xa4
23 #define RT305X_ESW_REG_P1LED 0xa8
24 #define RT305X_ESW_REG_P2LED 0xac
25 #define RT305X_ESW_REG_P3LED 0xb0
26 #define RT305X_ESW_REG_P4LED 0xb4
28 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
29 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
30 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
32 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
34 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
36 #define RT305X_ESW_PVIDC_PVID_M 0xfff
37 #define RT305X_ESW_PVIDC_PVID_S 12
39 #define RT305X_ESW_VLANI_VID_M 0xfff
40 #define RT305X_ESW_VLANI_VID_S 12
42 #define RT305X_ESW_VMSC_MSC_M 0xff
43 #define RT305X_ESW_VMSC_MSC_S 8
45 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
46 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
47 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
48 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
50 #define RT305X_ESW_POC1_EN_BP_S 0
51 #define RT305X_ESW_POC1_EN_FC_S 8
52 #define RT305X_ESW_POC1_DIS_RMC2CPU_S 16
53 #define RT305X_ESW_POC1_DIS_PORT_S 23
55 #define RT305X_ESW_POC3_UNTAG_EN_S 0
56 #define RT305X_ESW_POC3_ENAGING_S 8
57 #define RT305X_ESW_POC3_DIS_UC_PAUSE_S 16
59 #define RT305X_ESW_PORT0 0
60 #define RT305X_ESW_PORT1 1
61 #define RT305X_ESW_PORT2 2
62 #define RT305X_ESW_PORT3 3
63 #define RT305X_ESW_PORT4 4
64 #define RT305X_ESW_PORT5 5
65 #define RT305X_ESW_PORT6 6
67 #define RT305X_ESW_PORTS_INTERNAL \
68 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
69 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
70 BIT(RT305X_ESW_PORT4))
72 #define RT305X_ESW_PORTS_NOCPU \
73 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
75 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
77 #define RT305X_ESW_PORTS_ALL \
78 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
80 #define RT305X_ESW_NUM_VLANS 16
81 #define RT305X_ESW_NUM_PORTS 7
85 struct rt305x_esw_platform_data *pdata;
86 spinlock_t reg_rw_lock;
90 rt305x_esw_wr(struct rt305x_esw *esw, u32 val, unsigned reg)
92 __raw_writel(val, esw->base + reg);
96 rt305x_esw_rr(struct rt305x_esw *esw, unsigned reg)
98 return __raw_readl(esw->base + reg);
102 rt305x_esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
107 t = __raw_readl(esw->base + reg) & ~mask;
108 __raw_writel(t | val, esw->base + reg);
112 rt305x_esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
117 spin_lock_irqsave(&esw->reg_rw_lock, flags);
118 rt305x_esw_rmw_raw(esw, reg, mask, val);
119 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
123 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
126 unsigned long t_start = jiffies;
130 if (!(rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
131 RT305X_ESW_PCR1_WT_DONE))
133 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
139 write_data &= 0xffff;
141 (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
142 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
143 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
144 RT305X_ESW_REG_PCR0);
148 if (rt305x_esw_rr(esw, RT305X_ESW_REG_PCR1) &
149 RT305X_ESW_PCR1_WT_DONE)
152 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
159 printk(KERN_ERR "ramips_eth: MDIO timeout\n");
164 rt305x_esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
168 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
170 RT305X_ESW_REG_VLANI(vlan / 2),
171 RT305X_ESW_VLANI_VID_M << s,
172 (vid & RT305X_ESW_VLANI_VID_M) << s);
176 rt305x_esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
180 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
182 RT305X_ESW_REG_PVIDC(port / 2),
183 RT305X_ESW_PVIDC_PVID_M << s,
184 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
188 rt305x_esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
192 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
194 RT305X_ESW_REG_VMSC(vlan / 4),
195 RT305X_ESW_VMSC_MSC_M << s,
196 (msc & RT305X_ESW_VMSC_MSC_M) << s);
200 rt305x_esw_hw_init(struct rt305x_esw *esw)
204 /* vodoo from original driver */
205 rt305x_esw_wr(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
206 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_SGC2);
207 rt305x_esw_wr(esw, 0x00405555, RT305X_ESW_REG_PFC1);
209 /* Enable Back Pressure, and Flow Control */
211 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_BP_S) |
212 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC1_EN_FC_S)),
213 RT305X_ESW_REG_POC1);
215 /* Enable Aging, and VLAN TAG removal */
217 ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC3_ENAGING_S) |
218 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC3_UNTAG_EN_S)),
219 RT305X_ESW_REG_POC3);
221 rt305x_esw_wr(esw, 0x00d6500c, RT305X_ESW_REG_FCT2);
222 rt305x_esw_wr(esw, 0x0008a301, RT305X_ESW_REG_SGC);
224 /* Setup SoC Port control register */
226 (RT305X_ESW_SOCPC_CRC_PADDING |
227 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
228 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
229 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
230 RT305X_ESW_REG_SOCPC);
232 rt305x_esw_wr(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
233 rt305x_esw_wr(esw, 0x00000000, RT305X_ESW_REG_FPA);
235 /* Force Link/Activity on ports */
236 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P0LED);
237 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P1LED);
238 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P2LED);
239 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P3LED);
240 rt305x_esw_wr(esw, 0x00000005, RT305X_ESW_REG_P4LED);
242 rt305x_mii_write(esw, 0, 31, 0x8000);
243 for (i = 0; i < 5; i++) {
244 /* TX10 waveform coefficient */
245 rt305x_mii_write(esw, i, 0, 0x3100);
246 /* TX10 waveform coefficient */
247 rt305x_mii_write(esw, i, 26, 0x1601);
248 /* TX100/TX10 AD/DA current bias */
249 rt305x_mii_write(esw, i, 29, 0x7058);
250 /* TX100 slew rate control */
251 rt305x_mii_write(esw, i, 30, 0x0018);
255 /* select global register */
256 rt305x_mii_write(esw, 0, 31, 0x0);
257 /* tune TP_IDL tail and head waveform */
258 rt305x_mii_write(esw, 0, 22, 0x052f);
259 /* set TX10 signal amplitude threshold to minimum */
260 rt305x_mii_write(esw, 0, 17, 0x0fe0);
261 /* set squelch amplitude to higher threshold */
262 rt305x_mii_write(esw, 0, 18, 0x40ba);
263 /* longer TP_IDL tail length */
264 rt305x_mii_write(esw, 0, 14, 0x65);
265 /* select local register */
266 rt305x_mii_write(esw, 0, 31, 0x8000);
268 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
269 rt305x_esw_set_vlan_id(esw, i, 0);
270 rt305x_esw_set_vmsc(esw, i, 0);
273 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++)
274 rt305x_esw_set_pvid(esw, i, 1);
276 switch (esw->pdata->vlan_config) {
277 case RT305X_ESW_VLAN_CONFIG_NONE:
280 case RT305X_ESW_VLAN_CONFIG_LLLLW:
281 rt305x_esw_set_vlan_id(esw, 0, 1);
282 rt305x_esw_set_vlan_id(esw, 1, 2);
283 rt305x_esw_set_pvid(esw, RT305X_ESW_PORT4, 2);
285 rt305x_esw_set_vmsc(esw, 0,
286 BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |
287 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |
288 BIT(RT305X_ESW_PORT6));
289 rt305x_esw_set_vmsc(esw, 1,
290 BIT(RT305X_ESW_PORT4) | BIT(RT305X_ESW_PORT6));
293 case RT305X_ESW_VLAN_CONFIG_WLLLL:
294 rt305x_esw_set_vlan_id(esw, 0, 1);
295 rt305x_esw_set_vlan_id(esw, 1, 2);
296 rt305x_esw_set_pvid(esw, RT305X_ESW_PORT0, 2);
298 rt305x_esw_set_vmsc(esw, 0,
299 BIT(RT305X_ESW_PORT1) | BIT(RT305X_ESW_PORT2) |
300 BIT(RT305X_ESW_PORT3) | BIT(RT305X_ESW_PORT4) |
301 BIT(RT305X_ESW_PORT6));
302 rt305x_esw_set_vmsc(esw, 1,
303 BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT6));
312 rt305x_esw_probe(struct platform_device *pdev)
314 struct rt305x_esw_platform_data *pdata;
315 struct rt305x_esw *esw;
316 struct resource *res;
319 pdata = pdev->dev.platform_data;
323 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
325 dev_err(&pdev->dev, "no memory resource found\n");
329 esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
331 dev_err(&pdev->dev, "no memory for private data\n");
335 esw->base = ioremap(res->start, resource_size(res));
337 dev_err(&pdev->dev, "ioremap failed\n");
342 platform_set_drvdata(pdev, esw);
345 spin_lock_init(&esw->reg_rw_lock);
346 rt305x_esw_hw_init(esw);
356 rt305x_esw_remove(struct platform_device *pdev)
358 struct rt305x_esw *esw;
360 esw = platform_get_drvdata(pdev);
362 platform_set_drvdata(pdev, NULL);
370 static struct platform_driver rt305x_esw_driver = {
371 .probe = rt305x_esw_probe,
372 .remove = rt305x_esw_remove,
374 .name = "rt305x-esw",
375 .owner = THIS_MODULE,
380 rt305x_esw_init(void)
382 return platform_driver_register(&rt305x_esw_driver);
386 rt305x_esw_exit(void)
388 platform_driver_unregister(&rt305x_esw_driver);