2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_address.h>
33 #include <linux/switch.h>
35 #include <asm/mach-ralink/ralink_regs.h>
37 #include "ralink_soc_eth.h"
39 #include <linux/ioport.h>
40 #include <linux/switch.h>
41 #include <linux/mii.h>
43 #include <ralink_regs.h>
44 #include <asm/mach-ralink/mt7620.h>
46 #include "ralink_soc_eth.h"
47 #include "gsw_mt7620a.h"
51 #define GSW_REG_PHY_TIMEOUT (5 * HZ)
53 #ifdef CONFIG_SOC_MT7621
54 #define MT7620A_GSW_REG_PIAC 0x0004
56 #define MT7620A_GSW_REG_PIAC 0x7004
59 #define GSW_NUM_VLANS 16
60 #define GSW_NUM_VIDS 4096
61 #define GSW_NUM_PORTS 7
64 #define GSW_MDIO_ACCESS BIT(31)
65 #define GSW_MDIO_READ BIT(19)
66 #define GSW_MDIO_WRITE BIT(18)
67 #define GSW_MDIO_START BIT(16)
68 #define GSW_MDIO_ADDR_SHIFT 20
69 #define GSW_MDIO_REG_SHIFT 25
71 #define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
72 #define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
73 #define GSW_REG_SMACCR0 0x3fE4
74 #define GSW_REG_SMACCR1 0x3fE8
75 #define GSW_REG_CKGCR 0x3ff0
77 #define GSW_REG_IMR 0x7008
78 #define GSW_REG_ISR 0x700c
79 #define GSW_REG_GPC1 0x7014
81 #define SYSC_REG_CHIP_REV_ID 0x0c
82 #define SYSC_REG_CFG1 0x14
83 #define SYSC_REG_RESET_CTRL 0x34
84 #define RST_CTRL_MCM BIT(2)
85 #define SYSC_PAD_RGMII2_MDIO 0x58
86 #define SYSC_GPIO_MODE 0x60
88 #define PORT_IRQ_ST_CHG 0x7f
91 #ifdef CONFIG_SOC_MT7621
92 #define ESW_PHY_POLLING 0x0000
94 #define ESW_PHY_POLLING 0x7000
97 #define PMCR_IPG BIT(18)
98 #define PMCR_MAC_MODE BIT(16)
99 #define PMCR_FORCE BIT(15)
100 #define PMCR_TX_EN BIT(14)
101 #define PMCR_RX_EN BIT(13)
102 #define PMCR_BACKOFF BIT(9)
103 #define PMCR_BACKPRES BIT(8)
104 #define PMCR_RX_FC BIT(5)
105 #define PMCR_TX_FC BIT(4)
106 #define PMCR_SPEED(_x) (_x << 2)
107 #define PMCR_DUPLEX BIT(1)
108 #define PMCR_LINK BIT(0)
110 #define PHY_AN_EN BIT(31)
111 #define PHY_PRE_EN BIT(30)
112 #define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
115 /* Global attributes. */
116 GSW_ATTR_ENABLE_VLAN,
117 /* Port attributes. */
131 long unsigned int autopoll;
134 static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
136 iowrite32(val, gsw->base + reg);
139 static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
141 return ioread32(gsw->base + reg);
144 static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
146 unsigned long t_start = jiffies;
149 if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
151 if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
156 printk(KERN_ERR "mdio: MDIO timeout\n");
160 static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
163 if (mt7620_mii_busy_wait(gsw))
166 write_data &= 0xffff;
168 gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
169 (phy_register << GSW_MDIO_REG_SHIFT) |
170 (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
171 MT7620A_GSW_REG_PIAC);
173 if (mt7620_mii_busy_wait(gsw))
179 static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
183 if (mt7620_mii_busy_wait(gsw))
186 gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
187 (phy_reg << GSW_MDIO_REG_SHIFT) |
188 (phy_addr << GSW_MDIO_ADDR_SHIFT),
189 MT7620A_GSW_REG_PIAC);
191 if (mt7620_mii_busy_wait(gsw))
194 d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
199 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
201 struct fe_priv *priv = bus->priv;
202 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
204 return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
207 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
209 struct fe_priv *priv = bus->priv;
210 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
212 return _mt7620_mii_read(gsw, phy_addr, phy_reg);
216 mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val)
218 _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
219 _mt7620_mii_write(gsw, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
220 _mt7620_mii_write(gsw, 0x1f, 0x10, val >> 16);
224 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg)
228 _mt7620_mii_write(gsw, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
229 low = _mt7620_mii_read(gsw, 0x1f, (reg >> 2) & 0xf);
230 high = _mt7620_mii_read(gsw, 0x1f, 0x10);
232 return (high << 16) | (low & 0xffff);
235 static unsigned char *fe_speed_str(int speed)
252 int mt7620a_has_carrier(struct fe_priv *priv)
254 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
257 for (i = 0; i < GSW_PORT6; i++)
258 if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
263 static void mt7620a_handle_carrier(struct fe_priv *priv)
268 if (mt7620a_has_carrier(priv))
269 netif_carrier_on(priv->netdev);
271 netif_carrier_off(priv->netdev);
274 void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
276 if (priv->link[port])
277 netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
278 port, fe_speed_str(priv->phy->speed[port]),
279 (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
281 netdev_info(priv->netdev, "port %d link down\n", port);
282 mt7620a_handle_carrier(priv);
285 static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
287 struct fe_priv *priv = (struct fe_priv *) _priv;
288 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
290 int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
292 status = gsw_r32(gsw, GSW_REG_ISR);
293 if (status & PORT_IRQ_ST_CHG)
294 for (i = 0; i <= max; i++) {
295 u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
296 int link = status & 0x1;
298 if (link != priv->link[i]) {
300 netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
301 i, fe_speed_str((status >> 2) & 3),
302 (status & 0x2) ? "Full" : "Half");
304 netdev_info(priv->netdev, "port %d link down\n", i);
307 priv->link[i] = link;
309 mt7620a_handle_carrier(priv);
311 gsw_w32(gsw, status, GSW_REG_ISR);
316 static irqreturn_t gsw_interrupt_mt7621(int irq, void *_priv)
318 struct fe_priv *priv = (struct fe_priv *) _priv;
319 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
322 reg = mt7530_mdio_r32(gsw, 0x700c);
324 for (i = 0; i < 5; i++)
326 unsigned int link = mt7530_mdio_r32(gsw, 0x3008 + (i * 0x100)) & 0x1;
328 if (link != priv->link[i]) {
329 priv->link[i] = link;
331 netdev_info(priv->netdev, "port %d link up\n", i);
333 netdev_info(priv->netdev, "port %d link down\n", i);
337 mt7620a_handle_carrier(priv);
338 mt7530_mdio_w32(gsw, 0x700c, 0x1f);
343 static int mt7620_is_bga(void)
345 u32 bga = rt_sysc_r32(0x0c);
347 return (bga >> 16) & 1;
350 static void gsw_auto_poll(struct mt7620_gsw *gsw)
353 int lsb = -1, msb = 0;
355 for_each_set_bit(phy, &gsw->autopoll, 32) {
364 gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
367 void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
369 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
370 const __be32 *_id = of_get_property(np, "reg", NULL);
371 int phy_mode, size, id;
374 int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
376 if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
378 pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
380 pr_err("%s: invalid port id\n", np->name);
384 id = be32_to_cpu(*_id);
389 priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
390 if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
391 pr_err("%s: invalid fixed link property\n", np->name);
392 priv->phy->phy_fixed[id] = NULL;
396 phy_mode = of_get_phy_mode(np);
398 case PHY_INTERFACE_MODE_RGMII:
401 case PHY_INTERFACE_MODE_MII:
404 case PHY_INTERFACE_MODE_RMII:
408 dev_err(priv->device, "port %d - invalid phy mode\n", id);
412 priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
413 if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
416 val = rt_sysc_r32(SYSC_REG_CFG1);
417 val &= ~(3 << shift);
418 val |= mask << shift;
419 rt_sysc_w32(val, SYSC_REG_CFG1);
421 if (priv->phy->phy_fixed[id]) {
422 const __be32 *link = priv->phy->phy_fixed[id];
426 priv->phy->speed[id] = be32_to_cpup(link++);
427 tx_fc = be32_to_cpup(link++);
428 rx_fc = be32_to_cpup(link++);
429 priv->phy->duplex[id] = be32_to_cpup(link++);
432 switch (priv->phy->speed[id]) {
443 dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
444 priv->phy->phy_fixed[id] = 0;
447 val = PMCR_SPEED(val);
448 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
449 PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
454 if (priv->phy->duplex[id])
456 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
457 dev_info(priv->device, "using fixed link parameters\n");
461 if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
462 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
463 PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
465 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
466 fe_connect_phy_node(priv, priv->phy->phy_node[id]);
467 gsw->autopoll |= BIT(id);
473 static void gsw_hw_init_mt7620(struct mt7620_gsw *gsw, struct device_node *np)
475 u32 is_BGA = mt7620_is_bga();
477 rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
478 gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
480 if (of_property_read_bool(np, "mediatek,mt7530")) {
483 /* turn off ephy and set phy base addr to 12 */
484 gsw_w32(gsw, gsw_r32(gsw, GSW_REG_GPC1) | (0x1f << 24) | (0xc << 16), GSW_REG_GPC1);
486 /* set MT7530 central align */
487 val = mt7530_mdio_r32(gsw, 0x7830);
490 mt7530_mdio_w32(gsw, 0x7830, val);
492 val = mt7530_mdio_r32(gsw, 0x7a40);
494 mt7530_mdio_w32(gsw, 0x7a40, val);
496 mt7530_mdio_w32(gsw, 0x7a78, 0x855);
498 /* EPHY1 fixup - only run if the ephy is enabled */
500 /*correct PHY setting L3.0 BGA*/
501 _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
503 _mt7620_mii_write(gsw, 1, 17, 0x7444);
505 _mt7620_mii_write(gsw, 1, 19, 0x0114);
507 _mt7620_mii_write(gsw, 1, 19, 0x0117);
509 _mt7620_mii_write(gsw, 1, 22, 0x10cf);
510 _mt7620_mii_write(gsw, 1, 25, 0x6212);
511 _mt7620_mii_write(gsw, 1, 26, 0x0777);
512 _mt7620_mii_write(gsw, 1, 29, 0x4000);
513 _mt7620_mii_write(gsw, 1, 28, 0xc077);
514 _mt7620_mii_write(gsw, 1, 24, 0x0000);
516 _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
517 _mt7620_mii_write(gsw, 1, 17, 0x4838);
519 _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
521 _mt7620_mii_write(gsw, 1, 21, 0x0515);
522 _mt7620_mii_write(gsw, 1, 22, 0x0053);
523 _mt7620_mii_write(gsw, 1, 23, 0x00bf);
524 _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
525 _mt7620_mii_write(gsw, 1, 25, 0x0fad);
526 _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
528 _mt7620_mii_write(gsw, 1, 21, 0x0517);
529 _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
530 _mt7620_mii_write(gsw, 1, 23, 0x00bf);
531 _mt7620_mii_write(gsw, 1, 24, 0x0aab);
532 _mt7620_mii_write(gsw, 1, 25, 0x00ae);
533 _mt7620_mii_write(gsw, 1, 26, 0x0fff);
535 _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
536 _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
539 _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
540 _mt7620_mii_write(gsw, 0, 30, 0xa000);
541 _mt7620_mii_write(gsw, 1, 30, 0xa000);
542 _mt7620_mii_write(gsw, 2, 30, 0xa000);
543 _mt7620_mii_write(gsw, 3, 30, 0xa000);
545 _mt7620_mii_write(gsw, 0, 4, 0x05e1);
546 _mt7620_mii_write(gsw, 1, 4, 0x05e1);
547 _mt7620_mii_write(gsw, 2, 4, 0x05e1);
548 _mt7620_mii_write(gsw, 3, 4, 0x05e1);
550 _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
551 _mt7620_mii_write(gsw, 0, 16, 0x1111);
552 _mt7620_mii_write(gsw, 1, 16, 0x1010);
553 _mt7620_mii_write(gsw, 2, 16, 0x1515);
554 _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
556 /* CPU Port6 Force Link 1G, FC ON */
557 gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
558 /* Set Port6 CPU Port */
559 gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
562 if (gsw->port4 == PORT4_EPHY) {
563 u32 val = rt_sysc_r32(SYSC_REG_CFG1);
565 rt_sysc_w32(val, SYSC_REG_CFG1);
566 _mt7620_mii_write(gsw, 4, 30, 0xa000);
567 _mt7620_mii_write(gsw, 4, 4, 0x05e1);
568 _mt7620_mii_write(gsw, 4, 16, 0x1313);
569 pr_info("gsw: setting port4 to ephy mode\n");
573 static void gsw_hw_init_mt7621(struct mt7620_gsw *gsw, struct device_node *np)
578 /* Hardware reset Switch */
579 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
580 rt_sysc_w32(val | RST_CTRL_MCM, SYSC_REG_RESET_CTRL);
582 rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
585 /* reduce RGMII2 PAD driving strength */
586 rt_sysc_m32(3 << 4, 0, SYSC_PAD_RGMII2_MDIO);
588 /* gpio mux - RGMII1=Normal mode */
589 rt_sysc_m32(BIT(14), 0, SYSC_GPIO_MODE);
592 rt_sysc_m32(3 << 12, 0, SYSC_REG_CFG1);
594 /* enable MDIO to control MT7530 */
595 rt_sysc_m32(3 << 12, 0, SYSC_GPIO_MODE);
597 /* turn off all PHYs */
598 for (i = 0; i <= 4; i++) {
599 val = _mt7620_mii_read(gsw, i, 0x0);
601 _mt7620_mii_write(gsw, i, 0x0, val);
604 /* reset the switch */
605 mt7530_mdio_w32(gsw, 0x7000, 0x3);
608 if ((rt_sysc_r32(SYSC_REG_CHIP_REV_ID) & 0xFFFF) == 0x0101) {
609 /* (GE1, Force 1000M/FD, FC ON) */
610 gsw_w32(gsw, 0x2005e30b, 0x100);
611 mt7530_mdio_w32(gsw, 0x3600, 0x5e30b);
613 /* (GE1, Force 1000M/FD, FC ON) */
614 gsw_w32(gsw, 0x2005e33b, 0x100);
615 mt7530_mdio_w32(gsw, 0x3600, 0x5e33b);
618 /* (GE2, Link down) */
619 gsw_w32(gsw, 0x8000, 0x200);
621 //val = 0x117ccf; //Enable Port 6, P5 as GMAC5, P5 disable
622 val = mt7530_mdio_r32(gsw, 0x7804);
623 val &= ~(1<<8); //Enable Port 6
624 val |= (1<<6); //Disable Port 5
625 val |= (1<<13); //Port 5 as GMAC, no Internal PHY
627 val |= (1<<16);//change HW-TRAP
628 printk("change HW-TRAP to 0x%x\n", val);
629 mt7530_mdio_w32(gsw, 0x7804, val);
631 val = rt_sysc_r32(0x10);
632 val = (val >> 6) & 0x7;
634 /* 25Mhz Xtal - do nothing */
638 /* disable MT7530 core clock */
639 _mt7620_mii_write(gsw, 0, 13, 0x1f);
640 _mt7620_mii_write(gsw, 0, 14, 0x410);
641 _mt7620_mii_write(gsw, 0, 13, 0x401f);
642 _mt7620_mii_write(gsw, 0, 14, 0x0);
644 /* disable MT7530 PLL */
645 _mt7620_mii_write(gsw, 0, 13, 0x1f);
646 _mt7620_mii_write(gsw, 0, 14, 0x40d);
647 _mt7620_mii_write(gsw, 0, 13, 0x401f);
648 _mt7620_mii_write(gsw, 0, 14, 0x2020);
650 /* for MT7530 core clock = 500Mhz */
651 _mt7620_mii_write(gsw, 0, 13, 0x1f);
652 _mt7620_mii_write(gsw, 0, 14, 0x40e);
653 _mt7620_mii_write(gsw, 0, 13, 0x401f);
654 _mt7620_mii_write(gsw, 0, 14, 0x119);
656 /* enable MT7530 PLL */
657 _mt7620_mii_write(gsw, 0, 13, 0x1f);
658 _mt7620_mii_write(gsw, 0, 14, 0x40d);
659 _mt7620_mii_write(gsw, 0, 13, 0x401f);
660 _mt7620_mii_write(gsw, 0, 14, 0x2820);
664 /* enable MT7530 core clock */
665 _mt7620_mii_write(gsw, 0, 13, 0x1f);
666 _mt7620_mii_write(gsw, 0, 14, 0x410);
667 _mt7620_mii_write(gsw, 0, 13, 0x401f);
669 /* 20Mhz Xtal - TODO */
673 _mt7620_mii_write(gsw, 0, 14, 0x1);
675 /* set MT7530 central align */
676 val = mt7530_mdio_r32(gsw, 0x7830);
679 mt7530_mdio_w32(gsw, 0x7830, val);
681 val = mt7530_mdio_r32(gsw, 0x7a40);
683 mt7530_mdio_w32(gsw, 0x7a40, val);
685 mt7530_mdio_w32(gsw, 0x7a78, 0x855);
686 mt7530_mdio_w32(gsw, 0x7b00, 0x102); //delay setting for 10/1000M
687 mt7530_mdio_w32(gsw, 0x7b04, 0x14); //delay setting for 10/1000M
690 mt7530_mdio_w32(gsw, 0x7a54, 0x44); //lower driving
691 mt7530_mdio_w32(gsw, 0x7a5c, 0x44); //lower driving
692 mt7530_mdio_w32(gsw, 0x7a64, 0x44); //lower driving
693 mt7530_mdio_w32(gsw, 0x7a6c, 0x44); //lower driving
694 mt7530_mdio_w32(gsw, 0x7a74, 0x44); //lower driving
695 mt7530_mdio_w32(gsw, 0x7a7c, 0x44); //lower driving
699 /* turn on all PHYs */
700 for (i = 0; i <= 4; i++) {
701 val = _mt7620_mii_read(gsw, i, 0);
703 _mt7620_mii_write(gsw, i, 0, val);
707 val = mt7530_mdio_r32(gsw, 0x7808);
709 mt7530_mdio_w32(gsw, 0x7808, val);
712 void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
714 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
717 spin_lock_irqsave(&priv->page_lock, flags);
718 gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
719 gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
721 spin_unlock_irqrestore(&priv->page_lock, flags);
724 static struct of_device_id gsw_match[] = {
725 { .compatible = "ralink,mt7620a-gsw" },
729 int mt7620_gsw_config(struct fe_priv *priv)
731 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
733 /* is the mt7530 internal or external */
734 if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
735 mt7530_probe(priv->device, gsw->base, NULL, 0);
736 mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
738 mt7530_probe(priv->device, gsw->base, NULL, 1);
744 int mt7621_gsw_config(struct fe_priv *priv)
746 if (priv->mii_bus && priv->mii_bus->phy_map[0x1f])
747 mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
752 int mt7620_gsw_probe(struct fe_priv *priv)
754 struct mt7620_gsw *gsw;
755 struct device_node *np;
756 const char *port4 = NULL;
758 np = of_find_matching_node(NULL, gsw_match);
760 dev_err(priv->device, "no gsw node found\n");
763 np = of_node_get(np);
765 gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
767 dev_err(priv->device, "no gsw memory for private data\n");
771 gsw->base = of_iomap(np, 0);
773 dev_err(priv->device, "gsw ioremap failed\n");
777 gsw->dev = priv->device;
778 priv->soc->swpriv = gsw;
780 of_property_read_string(np, "ralink,port4", &port4);
781 if (port4 && !strcmp(port4, "ephy"))
782 gsw->port4 = PORT4_EPHY;
783 else if (port4 && !strcmp(port4, "gmac"))
784 gsw->port4 = PORT4_EXT;
786 gsw->port4 = PORT4_EPHY;
788 if (IS_ENABLED(CONFIG_SOC_MT7620))
789 gsw_hw_init_mt7620(gsw, np);
791 gsw_hw_init_mt7621(gsw, np);
793 gsw->irq = irq_of_parse_and_map(np, 0);
795 if (IS_ENABLED(CONFIG_SOC_MT7620)) {
796 request_irq(gsw->irq, gsw_interrupt_mt7620, 0, "gsw", priv);
797 gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
799 request_irq(gsw->irq, gsw_interrupt_mt7621, 0, "gsw", priv);
800 mt7530_mdio_w32(gsw, 0x7008, 0x1f);