2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; version 2 of the License
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/init.h>
23 #include <linux/skbuff.h>
24 #include <linux/etherdevice.h>
25 #include <linux/ethtool.h>
26 #include <linux/platform_device.h>
27 #include <linux/of_device.h>
28 #include <linux/clk.h>
29 #include <linux/of_net.h>
30 #include <linux/of_mdio.h>
31 #include <linux/of_irq.h>
32 #include <linux/of_address.h>
33 #include <linux/switch.h>
35 #include <asm/mach-ralink/ralink_regs.h>
37 #include "ralink_soc_eth.h"
39 #include <linux/ioport.h>
40 #include <linux/switch.h>
41 #include <linux/mii.h>
43 #include <ralink_regs.h>
44 #include <asm/mach-ralink/mt7620.h>
46 #include "ralink_soc_eth.h"
47 #include "gsw_mt7620a.h"
51 #define GSW_REG_PHY_TIMEOUT (5 * HZ)
53 #define MT7620A_GSW_REG_PIAC 0x7004
55 #define GSW_NUM_VLANS 16
56 #define GSW_NUM_VIDS 4096
57 #define GSW_NUM_PORTS 7
60 #define GSW_MDIO_ACCESS BIT(31)
61 #define GSW_MDIO_READ BIT(19)
62 #define GSW_MDIO_WRITE BIT(18)
63 #define GSW_MDIO_START BIT(16)
64 #define GSW_MDIO_ADDR_SHIFT 20
65 #define GSW_MDIO_REG_SHIFT 25
67 #define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100))
68 #define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
69 #define GSW_REG_SMACCR0 0x3fE4
70 #define GSW_REG_SMACCR1 0x3fE8
71 #define GSW_REG_CKGCR 0x3ff0
73 #define GSW_REG_IMR 0x7008
74 #define GSW_REG_ISR 0x700c
75 #define GSW_REG_GPC1 0x7014
77 #define SYSC_REG_CFG1 0x14
79 #define PORT_IRQ_ST_CHG 0x7f
83 #define ESW_PHY_POLLING 0x7000
85 #define PMCR_IPG BIT(18)
86 #define PMCR_MAC_MODE BIT(16)
87 #define PMCR_FORCE BIT(15)
88 #define PMCR_TX_EN BIT(14)
89 #define PMCR_RX_EN BIT(13)
90 #define PMCR_BACKOFF BIT(9)
91 #define PMCR_BACKPRES BIT(8)
92 #define PMCR_RX_FC BIT(5)
93 #define PMCR_TX_FC BIT(4)
94 #define PMCR_SPEED(_x) (_x << 2)
95 #define PMCR_DUPLEX BIT(1)
96 #define PMCR_LINK BIT(0)
98 #define PHY_AN_EN BIT(31)
99 #define PHY_PRE_EN BIT(30)
100 #define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24)
103 /* Global attributes. */
104 GSW_ATTR_ENABLE_VLAN,
105 /* Port attributes. */
119 long unsigned int autopoll;
122 static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
124 iowrite32(val, gsw->base + reg);
127 static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
129 return ioread32(gsw->base + reg);
132 static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
134 unsigned long t_start = jiffies;
137 if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
139 if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
144 printk(KERN_ERR "mdio: MDIO timeout\n");
148 static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
151 if (mt7620_mii_busy_wait(gsw))
154 write_data &= 0xffff;
156 gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
157 (phy_register << GSW_MDIO_REG_SHIFT) |
158 (phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
159 MT7620A_GSW_REG_PIAC);
161 if (mt7620_mii_busy_wait(gsw))
167 static u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg)
171 if (mt7620_mii_busy_wait(gsw))
174 gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
175 (phy_reg << GSW_MDIO_REG_SHIFT) |
176 (phy_addr << GSW_MDIO_ADDR_SHIFT),
177 MT7620A_GSW_REG_PIAC);
179 if (mt7620_mii_busy_wait(gsw))
182 d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
187 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
189 struct fe_priv *priv = bus->priv;
190 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
192 return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
195 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
197 struct fe_priv *priv = bus->priv;
198 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
200 return _mt7620_mii_read(gsw, phy_addr, phy_reg);
203 static unsigned char *fe_speed_str(int speed)
220 int mt7620a_has_carrier(struct fe_priv *priv)
222 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
225 for (i = 0; i < GSW_PORT6; i++)
226 if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
231 static void mt7620a_handle_carrier(struct fe_priv *priv)
236 if (mt7620a_has_carrier(priv))
237 netif_carrier_on(priv->netdev);
239 netif_carrier_off(priv->netdev);
242 void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
244 if (priv->link[port])
245 netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
246 port, fe_speed_str(priv->phy->speed[port]),
247 (DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
249 netdev_info(priv->netdev, "port %d link down\n", port);
250 mt7620a_handle_carrier(priv);
253 static irqreturn_t gsw_interrupt(int irq, void *_priv)
255 struct fe_priv *priv = (struct fe_priv *) _priv;
256 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
258 int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
260 status = gsw_r32(gsw, GSW_REG_ISR);
261 if (status & PORT_IRQ_ST_CHG)
262 for (i = 0; i <= max; i++) {
263 u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
264 int link = status & 0x1;
266 if (link != priv->link[i]) {
268 netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
269 i, fe_speed_str((status >> 2) & 3),
270 (status & 0x2) ? "Full" : "Half");
272 netdev_info(priv->netdev, "port %d link down\n", i);
275 priv->link[i] = link;
277 mt7620a_handle_carrier(priv);
279 gsw_w32(gsw, status, GSW_REG_ISR);
284 static int mt7620_is_bga(void)
286 u32 bga = rt_sysc_r32(0x0c);
288 return (bga >> 16) & 1;
291 static void gsw_auto_poll(struct mt7620_gsw *gsw)
294 int lsb = -1, msb = 0;
296 for_each_set_bit(phy, &gsw->autopoll, 32) {
305 gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
308 void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
310 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
311 const __be32 *_id = of_get_property(np, "reg", NULL);
312 int phy_mode, size, id;
315 int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
317 if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
319 pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
321 pr_err("%s: invalid port id\n", np->name);
325 id = be32_to_cpu(*_id);
330 priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
331 if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
332 pr_err("%s: invalid fixed link property\n", np->name);
333 priv->phy->phy_fixed[id] = NULL;
337 phy_mode = of_get_phy_mode(np);
339 case PHY_INTERFACE_MODE_RGMII:
342 case PHY_INTERFACE_MODE_MII:
345 case PHY_INTERFACE_MODE_RMII:
349 dev_err(priv->device, "port %d - invalid phy mode\n", id);
353 priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
354 if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
357 val = rt_sysc_r32(SYSCFG1);
358 val &= ~(3 << shift);
359 val |= mask << shift;
360 rt_sysc_w32(val, SYSCFG1);
362 if (priv->phy->phy_fixed[id]) {
363 const __be32 *link = priv->phy->phy_fixed[id];
367 priv->phy->speed[id] = be32_to_cpup(link++);
368 tx_fc = be32_to_cpup(link++);
369 rx_fc = be32_to_cpup(link++);
370 priv->phy->duplex[id] = be32_to_cpup(link++);
373 switch (priv->phy->speed[id]) {
384 dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
385 priv->phy->phy_fixed[id] = 0;
388 val = PMCR_SPEED(val);
389 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
390 PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
395 if (priv->phy->duplex[id])
397 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
398 dev_info(priv->device, "using fixed link parameters\n");
402 if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
403 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
404 PMCR_TX_EN | PMCR_MAC_MODE | PMCR_IPG;
406 gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
407 fe_connect_phy_node(priv, priv->phy->phy_node[id]);
408 gsw->autopoll |= BIT(id);
414 static void gsw_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
416 u32 is_BGA = mt7620_is_bga();
418 rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
419 gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
421 if (of_property_read_bool(np, "mediatek,mt7530")) {
422 gsw_w32(gsw, gsw_r32(gsw, GSW_REG_GPC1) | (0x1f << 24), GSW_REG_GPC1);
423 pr_info("gsw: truning EPHY off\n");
425 /* EPHY1 fixup - only run if the ephy is enabled */
427 /*correct PHY setting L3.0 BGA*/
428 _mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
430 _mt7620_mii_write(gsw, 1, 17, 0x7444);
432 _mt7620_mii_write(gsw, 1, 19, 0x0114);
434 _mt7620_mii_write(gsw, 1, 19, 0x0117);
436 _mt7620_mii_write(gsw, 1, 22, 0x10cf);
437 _mt7620_mii_write(gsw, 1, 25, 0x6212);
438 _mt7620_mii_write(gsw, 1, 26, 0x0777);
439 _mt7620_mii_write(gsw, 1, 29, 0x4000);
440 _mt7620_mii_write(gsw, 1, 28, 0xc077);
441 _mt7620_mii_write(gsw, 1, 24, 0x0000);
443 _mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
444 _mt7620_mii_write(gsw, 1, 17, 0x4838);
446 _mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
448 _mt7620_mii_write(gsw, 1, 21, 0x0515);
449 _mt7620_mii_write(gsw, 1, 22, 0x0053);
450 _mt7620_mii_write(gsw, 1, 23, 0x00bf);
451 _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
452 _mt7620_mii_write(gsw, 1, 25, 0x0fad);
453 _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
455 _mt7620_mii_write(gsw, 1, 21, 0x0517);
456 _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
457 _mt7620_mii_write(gsw, 1, 23, 0x00bf);
458 _mt7620_mii_write(gsw, 1, 24, 0x0aab);
459 _mt7620_mii_write(gsw, 1, 25, 0x00ae);
460 _mt7620_mii_write(gsw, 1, 26, 0x0fff);
462 _mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
463 _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
466 _mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
467 _mt7620_mii_write(gsw, 0, 30, 0xa000);
468 _mt7620_mii_write(gsw, 1, 30, 0xa000);
469 _mt7620_mii_write(gsw, 2, 30, 0xa000);
470 _mt7620_mii_write(gsw, 3, 30, 0xa000);
472 _mt7620_mii_write(gsw, 0, 4, 0x05e1);
473 _mt7620_mii_write(gsw, 1, 4, 0x05e1);
474 _mt7620_mii_write(gsw, 2, 4, 0x05e1);
475 _mt7620_mii_write(gsw, 3, 4, 0x05e1);
477 _mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
478 _mt7620_mii_write(gsw, 0, 16, 0x1111);
479 _mt7620_mii_write(gsw, 1, 16, 0x1010);
480 _mt7620_mii_write(gsw, 2, 16, 0x1515);
481 _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
483 /* CPU Port6 Force Link 1G, FC ON */
484 gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
485 /* Set Port6 CPU Port */
486 gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
489 if (gsw->port4 == PORT4_EPHY) {
490 u32 val = rt_sysc_r32(SYSCFG1);
492 rt_sysc_w32(val, SYSCFG1);
493 _mt7620_mii_write(gsw, 4, 30, 0xa000);
494 _mt7620_mii_write(gsw, 4, 4, 0x05e1);
495 _mt7620_mii_write(gsw, 4, 16, 0x1313);
496 pr_info("gsw: setting port4 to ephy mode\n");
500 void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
502 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
505 spin_lock_irqsave(&priv->page_lock, flags);
506 gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
507 gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
509 spin_unlock_irqrestore(&priv->page_lock, flags);
512 static struct of_device_id gsw_match[] = {
513 { .compatible = "ralink,mt7620a-gsw" },
517 int mt7620_gsw_config(struct fe_priv *priv)
519 struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
521 /* is the mt7530 internal or external */
522 if (priv->mii_bus && priv->mii_bus->phy_map[0x1f]) {
523 mt7530_probe(priv->device, gsw->base, NULL, 0);
524 mt7530_probe(priv->device, NULL, priv->mii_bus, 1);
526 mt7530_probe(priv->device, gsw->base, NULL, 1);
532 int mt7620_gsw_probe(struct fe_priv *priv)
534 struct mt7620_gsw *gsw;
535 struct device_node *np;
536 const char *port4 = NULL;
538 np = of_find_matching_node(NULL, gsw_match);
540 dev_err(priv->device, "no gsw node found\n");
543 np = of_node_get(np);
545 gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
547 dev_err(priv->device, "no gsw memory for private data\n");
551 gsw->irq = irq_of_parse_and_map(np, 0);
553 dev_err(priv->device, "no gsw irq resource found\n");
557 gsw->base = of_iomap(np, 0);
559 dev_err(priv->device, "gsw ioremap failed\n");
563 gsw->dev = priv->device;
564 priv->soc->swpriv = gsw;
566 of_property_read_string(np, "ralink,port4", &port4);
567 if (port4 && !strcmp(port4, "ephy"))
568 gsw->port4 = PORT4_EPHY;
569 else if (port4 && !strcmp(port4, "gmac"))
570 gsw->port4 = PORT4_EXT;
574 gsw_hw_init(gsw, np);
576 gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
577 request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);