target/linux/ramips/dts/rt3052_sitecom_wl-351.dts

   1 /dts-v1/;
   2
   3 #include "rt3050.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         compatible = "sitecom,wl-351", "ralink,rt3052-soc";
  10         model = "Sitecom WL-351 v1 002";
  11
  12         aliases {
  13                 led-boot = &led_power;
  14                 led-failsafe = &led_power;
  15                 led-running = &led_power;
  16                 led-upgrade = &led_power;
  17         };
  18
  19         cfi@1f000000 {
  20                 compatible = "cfi-flash";
  21                 reg = <0x1f000000 0x800000>;
  22                 bank-width = <2>;
  23                 device-width = <2>;
  24
  25                 partitions {
  26                         compatible = "fixed-partitions";
  27                         #address-cells = <1>;
  28                         #size-cells = <1>;
  29
  30                         partition@0 {
  31                                 label = "u-boot";
  32                                 reg = <0x0 0x30000>;
  33                                 read-only;
  34                         };
  35
  36                         partition@30000 {
  37                                 label = "u-boot-env";
  38                                 reg = <0x30000 0x10000>;
  39                                 read-only;
  40                         };
  41
  42                         factory: partition@40000 {
  43                                 label = "factory";
  44                                 reg = <0x40000 0x10000>;
  45                                 read-only;
  46                         };
  47
  48                         partition@50000 {
  49                                 compatible = "denx,uimage";
  50                                 label = "firmware";
  51                                 reg = <0x50000 0x3b0000>;
  52                         };
  53                 };
  54         };
  55
  56         leds {
  57                 compatible = "gpio-leds";
  58
  59                 led_power: power {
  60                         label = "wl-351:amber:power";
  61                         gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
  62                 };
  63
  64                 unpopulated {
  65                         label = "wl-351:amber:unpopulated";
  66                         gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  67                 };
  68
  69                 unpopulated2 {
  70                         label = "wl-351:blue:unpopulated";
  71                         gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  72                 };
  73         };
  74
  75         keys {
  76                 compatible = "gpio-keys-polled";
  77                 poll-interval = <20>;
  78
  79                 reset {
  80                         label = "reset";
  81                         gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  82                         linux,code = <KEY_RESTART>;
  83                 };
  84
  85                 wps {
  86                         label = "wps";
  87                         gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
  88                         linux,code = <KEY_WPS_BUTTON>;
  89                 };
  90         };
  91
  92         rtl8366rb {
  93                 compatible = "realtek,rtl8366rb";
  94                 gpio-sda = <&gpio0 1 GPIO_ACTIVE_HIGH>;
  95                 gpio-sck = <&gpio0 2 GPIO_ACTIVE_HIGH>;
  96         };
  97 };
  98
  99 &pinctrl {
 100         state_default: pinctrl0 {
 101                 gpio {
 102                         ralink,group = "spi", "i2c", "jtag", "mdio", "uartf";
 103                         ralink,function = "gpio";
 104                 };
 105         };
 106 };
 107
 108 &ethernet {
 109         mtd-mac-address = <&factory 0x4>;
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&rgmii_pins>;
 112 };
 113
 114 &esw {
 115         ralink,rgmii = <1>;
 116         mediatek,portmap = <0x3f>;
 117         ralink,fct2 = <0x0002500c>;
 118         /*
 119          * ext phy base addr 31, rx/tx clock skew 0,
 120          * turbo mii off, rgmi 3.3v off, port 5 polling off
 121          * port5: enabled, gige, full-duplex, rx/tx-flow-control
 122          * port6: enabled, gige, full-duplex, rx/tx-flow-control
 123         */
 124         ralink,fpa2 = <0x1f003fff>;
 125 };
 126
 127 &wmac {
 128         ralink,mtd-eeprom = <&factory 0>;
 129 };
 130
 131 &otg {
 132         status = "okay";
 133 };