1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/clock/mt7621-clk.h>
3 #include <dt-bindings/gpio/gpio.h>
8 compatible = "mediatek,mt7621-soc";
16 compatible = "mips,mips1004Kc";
22 compatible = "mips,mips1004Kc";
29 #interrupt-cells = <1>;
31 compatible = "mti,cpu-interrupt-controller";
39 compatible = "mediatek,mt7621-pll", "syscon";
42 clock-output-names = "cpu", "bus";
47 compatible = "fixed-clock";
49 /* FIXME: there should be way to detect this */
50 clock-frequency = <50000000>;
53 palmbus: palmbus@1E000000 {
54 compatible = "palmbus";
55 reg = <0x1E000000 0x100000>;
56 ranges = <0x0 0x1E000000 0x0FFFFF>;
62 compatible = "mtk,mt7621-sysc";
67 compatible = "mediatek,mt7621-wdt";
73 #interrupt-cells = <2>;
74 compatible = "mediatek,mt7621-gpio";
78 interrupt-parent = <&gic>;
79 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
83 compatible = "mediatek,mt7621-i2c";
88 resets = <&rstctrl 16>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&i2c_pins>;
101 compatible = "mediatek,mt7621-i2s";
104 clocks = <&sysclock>;
106 resets = <&rstctrl 17>;
109 interrupt-parent = <&gic>;
110 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
117 dma-names = "tx", "rx";
122 systick: systick@500 {
123 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
126 resets = <&rstctrl 28>;
127 reset-names = "intc";
129 interrupt-parent = <&gic>;
130 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
134 compatible = "mtk,mt7621-memc";
135 reg = <0x5000 0x1000>;
139 compatible = "mtk,mt7621-cpc";
140 reg = <0x1fbf0000 0x8000>;
144 compatible = "mtk,mt7621-mc";
145 reg = <0x1fbf8000 0x8000>;
148 uartlite: uartlite@c00 {
149 compatible = "ns16550a";
152 clock-frequency = <50000000>;
154 interrupt-parent = <&gic>;
155 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
162 uartlite2: uartlite2@d00 {
163 compatible = "ns16550a";
166 clock-frequency = <50000000>;
168 interrupt-parent = <&gic>;
169 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
174 pinctrl-names = "default";
175 pinctrl-0 = <&uart2_pins>;
180 uartlite3: uartlite3@e00 {
181 compatible = "ns16550a";
184 clock-frequency = <50000000>;
186 interrupt-parent = <&gic>;
187 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&uart3_pins>;
201 compatible = "ralink,mt7621-spi";
204 clocks = <&pll MT7621_CLK_BUS>;
206 resets = <&rstctrl 18>;
209 #address-cells = <1>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&spi_pins>;
217 compatible = "ralink,rt3883-gdma";
218 reg = <0x2800 0x800>;
220 resets = <&rstctrl 14>;
223 interrupt-parent = <&gic>;
224 interrupts = <0 13 4>;
227 #dma-channels = <16>;
228 #dma-requests = <16>;
234 compatible = "mediatek,mt7621-hsdma";
235 reg = <0x7000 0x1000>;
237 resets = <&rstctrl 5>;
238 reset-names = "hsdma";
240 interrupt-parent = <&gic>;
241 interrupts = <0 11 4>;
252 compatible = "ralink,rt2880-pinmux";
253 pinctrl-names = "default";
254 pinctrl-0 = <&state_default>;
256 state_default: pinctrl0 {
294 rgmii1_pins: rgmii1 {
301 rgmii2_pins: rgmii2 {
343 compatible = "ralink,rt2880-reset";
348 compatible = "ralink,rt2880-clock";
352 sdhci: sdhci@1E130000 {
355 compatible = "ralink,mt7620-sdhci";
356 reg = <0x1E130000 0x4000>;
358 interrupt-parent = <&gic>;
359 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&sdhci_pins>;
365 xhci: xhci@1E1C0000 {
366 #address-cells = <1>;
370 compatible = "mediatek,mt8173-xhci";
371 reg = <0x1e1c0000 0x1000
373 reg-names = "mac", "ippc";
375 clocks = <&sysclock>;
376 clock-names = "sys_ck";
378 interrupt-parent = <&gic>;
379 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
382 * Port 1 of both hubs is one usb slot and referenced here.
383 * The binding doesn't allow to address individual hubs.
384 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
386 xhci_ehci_port1: port@1 {
388 #trigger-source-cells = <0>;
392 * Only the second usb hub has a second port. That port serves
397 #trigger-source-cells = <0>;
401 gic: interrupt-controller@1fbc0000 {
402 compatible = "mti,gic";
403 reg = <0x1fbc0000 0x2000>;
405 interrupt-controller;
406 #interrupt-cells = <3>;
408 mti,reserved-cpu-vectors = <7>;
411 compatible = "mti,gic-timer";
412 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
413 clocks = <&pll MT7621_CLK_CPU>;
419 compatible = "fixed-clock";
421 clock-frequency = <125000000>;
424 nand: nand@1e003000 {
427 compatible = "mediatek,mt7621-nfc";
428 reg = <0x1e003000 0x800
430 reg-names = "nfi", "ecc";
432 clocks = <&nficlock>;
433 clock-names = "nfi_clk";
436 ethsys: syscon@1e000000 {
437 compatible = "mediatek,mt7621-ethsys",
439 reg = <0x1e000000 0x1000>;
443 ethernet: ethernet@1e100000 {
444 compatible = "mediatek,mt7621-eth";
445 reg = <0x1e100000 0x10000>;
447 clocks = <&sysclock>;
448 clock-names = "ethif";
450 #address-cells = <1>;
453 resets = <&rstctrl 6 &rstctrl 23>;
454 reset-names = "fe", "eth";
456 interrupt-parent = <&gic>;
457 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
459 mediatek,ethsys = <ðsys>;
462 compatible = "mediatek,eth-mac";
474 compatible = "mediatek,eth-mac";
477 phy-mode = "rgmii-rxid";
481 #address-cells = <1>;
485 compatible = "mediatek,mt7621";
486 #address-cells = <1>;
490 resets = <&rstctrl 2>;
494 #address-cells = <1>;
545 compatible = "mediatek,mt7621-gsw";
546 reg = <0x1e110000 0x8000>;
547 interrupt-parent = <&gic>;
548 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
551 pcie: pcie@1e140000 {
552 compatible = "mediatek,mt7621-pci";
553 reg = <0x1e140000 0x100 /* host-pci bridge registers */
554 0x1e142000 0x100 /* pcie port 0 RC control registers */
555 0x1e143000 0x100 /* pcie port 1 RC control registers */
556 0x1e144000 0x100>; /* pcie port 2 RC control registers */
557 #address-cells = <3>;
560 pinctrl-names = "default";
561 pinctrl-0 = <&pcie_pins>;
567 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
568 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
571 interrupt-parent = <&gic>;
572 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
573 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
574 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
578 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
579 reset-names = "pcie0", "pcie1", "pcie2";
580 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
581 clock-names = "pcie0", "pcie1", "pcie2";
582 phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
583 phy-names = "pcie-phy0", "pcie-phy2";
585 reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
588 reg = <0x0000 0 0 0 0>;
589 #address-cells = <3>;
592 bus-range = <0x00 0xff>;
596 reg = <0x0800 0 0 0 0>;
597 #address-cells = <3>;
600 bus-range = <0x00 0xff>;
604 reg = <0x1000 0 0 0 0>;
605 #address-cells = <3>;
608 bus-range = <0x00 0xff>;
612 pcie0_phy: pcie-phy@1e149000 {
613 compatible = "mediatek,mt7621-pci-phy";
614 reg = <0x1e149000 0x0700>;
618 pcie2_phy: pcie-phy@1e14a000 {
619 compatible = "mediatek,mt7621-pci-phy";
620 reg = <0x1e14a000 0x0700>;