4 compatible = "mediatek,mtk7621-soc";
8 compatible = "mips,mips1004Kc";
12 compatible = "mips,mips1004Kc";
18 #interrupt-cells = <1>;
20 compatible = "mti,cpu-interrupt-controller";
24 compatible = "palmbus";
25 reg = <0x1E000000 0x100000>;
26 ranges = <0x0 0x1E000000 0x0FFFFF>;
32 compatible = "mtk,mt7621-sysc";
37 compatible = "mtk,mt7621-wdt";
45 compatible = "mtk,mt7621-gpio";
50 compatible = "mtk,mt7621-gpio-bank";
57 compatible = "mtk,mt7621-gpio-bank";
64 compatible = "mtk,mt7621-gpio-bank";
71 compatible = "mtk,mt7621-memc";
76 compatible = "ns16550a";
79 interrupt-parent = <&gic>;
90 compatible = "ralink,mt7621-spi";
93 resets = <&rstctrl 18>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&spi_pins>;
103 #address-cells = <1>;
106 spi-max-frequency = <10000000>;
107 m25p,chunked-io = <32>;
113 compatible = "ralink,rt2880-pinmux";
114 pinctrl-names = "default";
115 pinctrl-0 = <&state_default>;
117 state_default: pinctrl0 {
122 ralink,group = "spi";
123 ralink,function = "spi";
129 ralink,group = "i2c";
130 ralink,function = "i2c";
136 ralink,group = "uart1";
137 ralink,function = "uart";
143 ralink,group = "uart2";
144 ralink,function = "uart";
150 ralink,group = "uart3";
151 ralink,function = "uart";
155 rgmii1_pins: rgmii1 {
157 ralink,group = "rgmii1";
158 ralink,function = "rgmii";
162 rgmii2_pins: rgmii2 {
164 ralink,group = "rgmii2";
165 ralink,function = "rgmii";
171 ralink,group = "mdio";
172 ralink,function = "mdio";
178 ralink,group = "pcie";
179 ralink,function = "pcie rst";
185 ralink,group = "spi";
186 ralink,function = "nand";
190 ralink,group = "sdhci";
191 ralink,function = "nand";
197 ralink,group = "sdhci";
198 ralink,function = "sdhci";
204 compatible = "ralink,rt2880-reset";
209 compatible = "ralink,mt7620-sdhci";
210 reg = <0x1E130000 4000>;
212 interrupt-parent = <&gic>;
219 compatible = "xhci-platform";
220 reg = <0x1E1C0000 4000>;
222 interrupt-parent = <&gic>;
227 #address-cells = <0>;
228 #interrupt-cells = <1>;
229 interrupt-controller;
230 compatible = "ralink,mt7621-gic";
231 reg = < 0x1fbc0000 0x80 /* gic */
232 0x1fbf0000 0x8000 /* cpc */
233 0x1fbf8000 0x8000 /* gpmc */
238 compatible = "mtk,mt7621-nand";
240 reg = <0x1e003000 0x800
242 #address-cells = <1>;
247 reg = <0x00000 0x80000>; /* 64 KB */
252 reg = <0x80000 0x80000>; /* 64 KB */
257 reg = <0x100000 0x40000>;
262 reg = <0x140000 0xec0000>;
267 compatible = "ralink,mt7621-eth";
268 reg = <0x1e100000 10000>;
270 #address-cells = <1>;
273 resets = <&rstctrl 6 &rstctrl 23>;
274 reset-names = "fe", "eth";
276 interrupt-parent = <&gic>;
280 #address-cells = <1>;
283 phy1f: ethernet-phy@1f {
291 compatible = "ralink,mt7620a-gsw";
292 reg = <0x1e110000 8000>;
293 interrupt-parent = <&gic>;
298 compatible = "mediatek,mt7621-pci";
299 reg = <0x1e140000 0x100
302 #address-cells = <3>;
305 pinctrl-names = "default";
306 pinctrl-0 = <&pcie_pins>;
312 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
313 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
319 reg = <0x0000 0 0 0 0>;
321 #address-cells = <3>;
328 reg = <0x0800 0 0 0 0>;
330 #address-cells = <3>;
337 reg = <0x1000 0 0 0 0>;
339 #address-cells = <3>;