1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mtk7621-soc";
10 compatible = "mips,mips1004Kc";
14 compatible = "mips,mips1004Kc";
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
29 cpuclock: cpuclock@0 {
31 compatible = "fixed-clock";
33 /* FIXME: there should be way to detect this */
34 clock-frequency = <880000000>;
37 sysclock: sysclock@0 {
39 compatible = "fixed-clock";
41 /* FIXME: there should be way to detect this */
42 clock-frequency = <50000000>;
45 palmbus: palmbus@1E000000 {
46 compatible = "palmbus";
47 reg = <0x1E000000 0x100000>;
48 ranges = <0x0 0x1E000000 0x0FFFFF>;
54 compatible = "mtk,mt7621-sysc";
59 compatible = "mtk,mt7621-wdt";
67 compatible = "mtk,mt7621-gpio";
72 compatible = "mtk,mt7621-gpio-bank";
79 compatible = "mtk,mt7621-gpio-bank";
86 compatible = "mtk,mt7621-gpio-bank";
93 compatible = "mediatek,mt7621-i2c";
98 resets = <&rstctrl 16>;
101 #address-cells = <1>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&i2c_pins>;
111 compatible = "mediatek,mt7621-i2s";
114 clocks = <&sysclock>;
116 resets = <&rstctrl 17>;
119 interrupt-parent = <&gic>;
120 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
127 dma-names = "tx", "rx";
133 compatible = "mtk,mt7621-memc";
138 compatible = "mtk,mt7621-cpc";
139 reg = <0x1fbf0000 0x8000>;
143 compatible = "mtk,mt7621-mc";
144 reg = <0x1fbf8000 0x8000>;
147 uartlite: uartlite@c00 {
148 compatible = "ns16550a";
151 clocks = <&sysclock>;
152 clock-frequency = <50000000>;
154 interrupt-parent = <&gic>;
155 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
165 compatible = "ralink,mt7621-spi";
168 clocks = <&sysclock>;
170 resets = <&rstctrl 18>;
173 #address-cells = <1>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&spi_pins>;
180 #address-cells = <1>;
183 spi-max-frequency = <10000000>;
184 m25p,chunked-io = <32>;
189 compatible = "ralink,rt3883-gdma";
190 reg = <0x2800 0x800>;
192 resets = <&rstctrl 14>;
195 interrupt-parent = <&gic>;
196 interrupts = <0 13 4>;
199 #dma-channels = <16>;
200 #dma-requests = <16>;
206 compatible = "mediatek,mt7621-hsdma";
207 reg = <0x7000 0x1000>;
209 resets = <&rstctrl 5>;
210 reset-names = "hsdma";
212 interrupt-parent = <&gic>;
213 interrupts = <0 11 4>;
224 compatible = "ralink,rt2880-pinmux";
225 pinctrl-names = "default";
226 pinctrl-0 = <&state_default>;
228 state_default: pinctrl0 {
233 ralink,group = "i2c";
234 ralink,function = "i2c";
240 ralink,group = "spi";
241 ralink,function = "spi";
247 ralink,group = "uart1";
248 ralink,function = "uart1";
254 ralink,group = "uart2";
255 ralink,function = "uart2";
261 ralink,group = "uart3";
262 ralink,function = "uart3";
266 rgmii1_pins: rgmii1 {
268 ralink,group = "rgmii1";
269 ralink,function = "rgmii1";
273 rgmii2_pins: rgmii2 {
275 ralink,group = "rgmii2";
276 ralink,function = "rgmii2";
282 ralink,group = "mdio";
283 ralink,function = "mdio";
289 ralink,group = "pcie";
290 ralink,function = "pcie rst";
296 ralink,group = "spi";
297 ralink,function = "nand1";
301 ralink,group = "sdhci";
302 ralink,function = "nand2";
308 ralink,group = "sdhci";
309 ralink,function = "sdhci";
315 compatible = "ralink,rt2880-reset";
320 compatible = "ralink,rt2880-clock";
324 sdhci: sdhci@1E130000 {
325 compatible = "ralink,mt7620-sdhci";
326 reg = <0x1E130000 0x4000>;
328 interrupt-parent = <&gic>;
329 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
332 xhci: xhci@1E1C0000 {
335 compatible = "mediatek,mt8173-xhci";
336 reg = <0x1e1c0000 0x1000
339 clocks = <&sysclock>;
340 clock-names = "sys_ck";
342 interrupt-parent = <&gic>;
343 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
346 gic: interrupt-controller@1fbc0000 {
347 compatible = "mti,gic";
348 reg = <0x1fbc0000 0x2000>;
350 interrupt-controller;
351 #interrupt-cells = <3>;
353 mti,reserved-cpu-vectors = <7>;
356 compatible = "mti,gic-timer";
357 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
358 clocks = <&cpuclock>;
362 nand: nand@1e003000 {
365 compatible = "mtk,mt7621-nand";
367 reg = <0x1e003000 0x800
369 #address-cells = <1>;
373 ethernet: ethernet@1e100000 {
374 compatible = "mediatek,mt7621-eth";
375 reg = <0x1e100000 0x10000>;
377 #address-cells = <1>;
380 resets = <&rstctrl 6 &rstctrl 23>;
381 reset-names = "fe", "eth";
383 interrupt-parent = <&gic>;
384 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
386 mediatek,switch = <&gsw>;
389 #address-cells = <1>;
392 phy1f: ethernet-phy@1f {
400 compatible = "mediatek,mt7621-gsw";
401 reg = <0x1e110000 0x8000>;
402 interrupt-parent = <&gic>;
403 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
406 pcie: pcie@1e140000 {
407 compatible = "mediatek,mt7621-pci";
408 reg = <0x1e140000 0x100
411 #address-cells = <3>;
414 pinctrl-names = "default";
415 pinctrl-0 = <&pcie_pins>;
421 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
422 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
425 interrupt-parent = <&gic>;
426 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
427 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
428 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
432 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
433 reset-names = "pcie0", "pcie1", "pcie2";
434 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
435 clock-names = "pcie0", "pcie1", "pcie2";
438 reg = <0x0000 0 0 0 0>;
440 #address-cells = <3>;
447 reg = <0x0800 0 0 0 0>;
449 #address-cells = <3>;
456 reg = <0x1000 0 0 0 0>;
458 #address-cells = <3>;