1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mtk7621-soc";
10 compatible = "mips,mips1004Kc";
14 compatible = "mips,mips1004Kc";
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
25 cpuclock: cpuclock@0 {
27 compatible = "fixed-clock";
29 /* FIXME: there should be way to detect this */
30 clock-frequency = <880000000>;
33 sysclock: sysclock@0 {
35 compatible = "fixed-clock";
37 /* FIXME: there should be way to detect this */
38 clock-frequency = <50000000>;
42 compatible = "palmbus";
43 reg = <0x1E000000 0x100000>;
44 ranges = <0x0 0x1E000000 0x0FFFFF>;
50 compatible = "mtk,mt7621-sysc";
55 compatible = "mtk,mt7621-wdt";
63 compatible = "mtk,mt7621-gpio";
68 compatible = "mtk,mt7621-gpio-bank";
75 compatible = "mtk,mt7621-gpio-bank";
82 compatible = "mtk,mt7621-gpio-bank";
89 compatible = "mtk,mt7621-memc";
94 compatible = "mtk,mt7621-cpc";
95 reg = <0x1fbf0000 0x8000>;
99 compatible = "mtk,mt7621-mc";
100 reg = <0x1fbf8000 0x8000>;
104 compatible = "ns16550a";
107 clocks = <&sysclock>;
109 interrupt-parent = <&gic>;
110 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
120 compatible = "ralink,mt7621-spi";
123 clocks = <&sysclock>;
125 resets = <&rstctrl 18>;
128 #address-cells = <1>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&spi_pins>;
135 #address-cells = <1>;
138 spi-max-frequency = <10000000>;
139 m25p,chunked-io = <32>;
145 compatible = "ralink,rt2880-pinmux";
146 pinctrl-names = "default";
147 pinctrl-0 = <&state_default>;
149 state_default: pinctrl0 {
154 ralink,group = "spi";
155 ralink,function = "spi";
161 ralink,group = "i2c";
162 ralink,function = "i2c";
168 ralink,group = "uart1";
169 ralink,function = "uart1";
175 ralink,group = "uart2";
176 ralink,function = "uart2";
182 ralink,group = "uart3";
183 ralink,function = "uart3";
187 rgmii1_pins: rgmii1 {
189 ralink,group = "rgmii1";
190 ralink,function = "rgmii1";
194 rgmii2_pins: rgmii2 {
196 ralink,group = "rgmii2";
197 ralink,function = "rgmii2";
203 ralink,group = "mdio";
204 ralink,function = "mdio";
210 ralink,group = "pcie";
211 ralink,function = "pcie rst";
217 ralink,group = "spi";
218 ralink,function = "nand1";
222 ralink,group = "sdhci";
223 ralink,function = "nand2";
229 ralink,group = "sdhci";
230 ralink,function = "sdhci";
236 compatible = "ralink,rt2880-reset";
241 compatible = "ralink,mt7620-sdhci";
242 reg = <0x1E130000 4000>;
244 interrupt-parent = <&gic>;
245 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
251 compatible = "xhci-platform";
252 reg = <0x1E1C0000 4000>;
254 interrupt-parent = <&gic>;
255 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
258 gic: interrupt-controller@1fbc0000 {
259 compatible = "mti,gic";
260 reg = <0x1fbc0000 0x2000>;
262 interrupt-controller;
263 #interrupt-cells = <3>;
265 mti,reserved-cpu-vectors = <7>;
268 compatible = "mti,gic-timer";
269 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
270 clocks = <&cpuclock>;
275 compatible = "mtk,mt7621-nand";
277 reg = <0x1e003000 0x800
279 #address-cells = <1>;
284 reg = <0x00000 0x80000>; /* 64 KB */
289 reg = <0x80000 0x80000>; /* 64 KB */
294 reg = <0x100000 0x40000>;
299 reg = <0x140000 0xec0000>;
304 compatible = "ralink,mt7621-eth";
305 reg = <0x1e100000 10000>;
307 #address-cells = <1>;
310 resets = <&rstctrl 6 &rstctrl 23>;
311 reset-names = "fe", "eth";
313 interrupt-parent = <&gic>;
314 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
317 #address-cells = <1>;
320 phy1f: ethernet-phy@1f {
328 compatible = "ralink,mt7620a-gsw";
329 reg = <0x1e110000 8000>;
330 interrupt-parent = <&gic>;
331 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
335 compatible = "mediatek,mt7621-pci";
336 reg = <0x1e140000 0x100
339 #address-cells = <3>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&pcie_pins>;
349 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
350 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
353 interrupt-parent = <&gic>;
354 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
355 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
356 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
361 reg = <0x0000 0 0 0 0>;
363 #address-cells = <3>;
370 reg = <0x0800 0 0 0 0>;
372 #address-cells = <3>;
379 reg = <0x1000 0 0 0 0>;
381 #address-cells = <3>;