1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/clock/mt7621-clk.h>
7 compatible = "mediatek,mt7621-soc";
15 compatible = "mips,mips1004Kc";
21 compatible = "mips,mips1004Kc";
28 #interrupt-cells = <1>;
30 compatible = "mti,cpu-interrupt-controller";
38 compatible = "mediatek,mt7621-pll", "syscon";
41 clock-output-names = "cpu", "bus";
46 compatible = "fixed-clock";
48 /* FIXME: there should be way to detect this */
49 clock-frequency = <50000000>;
52 palmbus: palmbus@1E000000 {
53 compatible = "palmbus";
54 reg = <0x1E000000 0x100000>;
55 ranges = <0x0 0x1E000000 0x0FFFFF>;
61 compatible = "mtk,mt7621-sysc";
66 compatible = "mediatek,mt7621-wdt";
74 compatible = "mtk,mt7621-gpio";
77 interrupt-parent = <&gic>;
78 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
82 compatible = "mtk,mt7621-gpio-bank";
89 compatible = "mtk,mt7621-gpio-bank";
96 compatible = "mtk,mt7621-gpio-bank";
103 compatible = "mediatek,mt7621-i2c";
106 clocks = <&sysclock>;
108 resets = <&rstctrl 16>;
111 #address-cells = <1>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&i2c_pins>;
121 compatible = "mediatek,mt7621-i2s";
124 clocks = <&sysclock>;
126 resets = <&rstctrl 17>;
129 interrupt-parent = <&gic>;
130 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
137 dma-names = "tx", "rx";
142 systick: systick@500 {
143 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
146 resets = <&rstctrl 28>;
147 reset-names = "intc";
149 interrupt-parent = <&gic>;
150 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
154 compatible = "mtk,mt7621-memc";
155 reg = <0x5000 0x1000>;
159 compatible = "mtk,mt7621-cpc";
160 reg = <0x1fbf0000 0x8000>;
164 compatible = "mtk,mt7621-mc";
165 reg = <0x1fbf8000 0x8000>;
168 uartlite: uartlite@c00 {
169 compatible = "ns16550a";
172 clock-frequency = <50000000>;
174 interrupt-parent = <&gic>;
175 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
182 uartlite2: uartlite2@d00 {
183 compatible = "ns16550a";
186 clock-frequency = <50000000>;
188 interrupt-parent = <&gic>;
189 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&uart2_pins>;
200 uartlite3: uartlite3@e00 {
201 compatible = "ns16550a";
204 clock-frequency = <50000000>;
206 interrupt-parent = <&gic>;
207 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&uart3_pins>;
221 compatible = "ralink,mt7621-spi";
224 clocks = <&pll MT7621_CLK_BUS>;
226 resets = <&rstctrl 18>;
229 #address-cells = <1>;
232 pinctrl-names = "default";
233 pinctrl-0 = <&spi_pins>;
237 compatible = "ralink,rt3883-gdma";
238 reg = <0x2800 0x800>;
240 resets = <&rstctrl 14>;
243 interrupt-parent = <&gic>;
244 interrupts = <0 13 4>;
247 #dma-channels = <16>;
248 #dma-requests = <16>;
254 compatible = "mediatek,mt7621-hsdma";
255 reg = <0x7000 0x1000>;
257 resets = <&rstctrl 5>;
258 reset-names = "hsdma";
260 interrupt-parent = <&gic>;
261 interrupts = <0 11 4>;
272 compatible = "ralink,rt2880-pinmux";
273 pinctrl-names = "default";
274 pinctrl-0 = <&state_default>;
276 state_default: pinctrl0 {
281 ralink,group = "i2c";
282 ralink,function = "i2c";
288 ralink,group = "spi";
289 ralink,function = "spi";
295 ralink,group = "uart1";
296 ralink,function = "uart1";
302 ralink,group = "uart2";
303 ralink,function = "uart2";
309 ralink,group = "uart3";
310 ralink,function = "uart3";
314 rgmii1_pins: rgmii1 {
316 ralink,group = "rgmii1";
317 ralink,function = "rgmii1";
321 rgmii2_pins: rgmii2 {
323 ralink,group = "rgmii2";
324 ralink,function = "rgmii2";
330 ralink,group = "mdio";
331 ralink,function = "mdio";
337 ralink,group = "pcie";
338 ralink,function = "pcie rst";
344 ralink,group = "spi";
345 ralink,function = "nand1";
349 ralink,group = "sdhci";
350 ralink,function = "nand2";
356 ralink,group = "sdhci";
357 ralink,function = "sdhci";
363 compatible = "ralink,rt2880-reset";
368 compatible = "ralink,rt2880-clock";
372 sdhci: sdhci@1E130000 {
375 compatible = "ralink,mt7620-sdhci";
376 reg = <0x1E130000 0x4000>;
378 interrupt-parent = <&gic>;
379 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&sdhci_pins>;
385 xhci: xhci@1E1C0000 {
386 #address-cells = <1>;
390 compatible = "mediatek,mt8173-xhci";
391 reg = <0x1e1c0000 0x1000
393 reg-names = "mac", "ippc";
395 clocks = <&sysclock>;
396 clock-names = "sys_ck";
398 interrupt-parent = <&gic>;
399 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
402 * Port 1 of both hubs is one usb slot and referenced here.
403 * The binding doesn't allow to address individual hubs.
404 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
406 xhci_ehci_port1: port@1 {
408 #trigger-source-cells = <0>;
412 * Only the second usb hub has a second port. That port serves
417 #trigger-source-cells = <0>;
421 gic: interrupt-controller@1fbc0000 {
422 compatible = "mti,gic";
423 reg = <0x1fbc0000 0x2000>;
425 interrupt-controller;
426 #interrupt-cells = <3>;
428 mti,reserved-cpu-vectors = <7>;
431 compatible = "mti,gic-timer";
432 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
433 clocks = <&pll MT7621_CLK_CPU>;
437 nand: nand@1e003000 {
440 compatible = "mtk,mt7621-nand";
442 reg = <0x1e003000 0x800
446 ethernet: ethernet@1e100000 {
447 compatible = "mediatek,mt7621-eth";
448 reg = <0x1e100000 0x10000>;
450 #address-cells = <1>;
453 resets = <&rstctrl 6 &rstctrl 23>;
454 reset-names = "fe", "eth";
456 interrupt-parent = <&gic>;
457 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
459 mediatek,switch = <&gsw>;
462 #address-cells = <1>;
465 phy1f: ethernet-phy@1f {
472 compatible = "mediatek,mt7623-hnat";
477 resets = <&rstctrl 0>;
478 reset-names = "mtketh";
483 compatible = "mediatek,mt7621-gsw";
484 reg = <0x1e110000 0x8000>;
485 interrupt-parent = <&gic>;
486 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
489 pcie: pcie@1e140000 {
490 compatible = "mediatek,mt7621-pci";
491 reg = <0x1e140000 0x100
494 #address-cells = <3>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pcie_pins>;
504 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
505 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
508 interrupt-parent = <&gic>;
509 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
510 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
511 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
515 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
516 reset-names = "pcie0", "pcie1", "pcie2";
517 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
518 clock-names = "pcie0", "pcie1", "pcie2";
521 reg = <0x0000 0 0 0 0>;
523 #address-cells = <3>;
530 reg = <0x0800 0 0 0 0>;
532 #address-cells = <3>;
539 reg = <0x1000 0 0 0 0>;
541 #address-cells = <3>;