target/linux/ramips/dts/mt7621.dtsi

   1 #include <dt-bindings/interrupt-controller/mips-gic.h>
   2
   3 / {
   4         #address-cells = <1>;
   5         #size-cells = <1>;
   6         compatible = "mediatek,mtk7621-soc";
   7
   8         cpus {
   9                 cpu@0 {
  10                         compatible = "mips,mips1004Kc";
  11                 };
  12
  13                 cpu@1 {
  14                         compatible = "mips,mips1004Kc";
  15                 };
  16         };
  17
  18         cpuintc: cpuintc@0 {
  19                 #address-cells = <0>;
  20                 #interrupt-cells = <1>;
  21                 interrupt-controller;
  22                 compatible = "mti,cpu-interrupt-controller";
  23         };
  24
  25         aliases {
  26                 serial0 = &uartlite;
  27         };
  28
  29         cpuclock: cpuclock@0 {
  30                 #clock-cells = <0>;
  31                 compatible = "fixed-clock";
  32
  33                 /* FIXME: there should be way to detect this */
  34                 clock-frequency = <880000000>;
  35         };
  36
  37         sysclock: sysclock@0 {
  38                 #clock-cells = <0>;
  39                 compatible = "fixed-clock";
  40
  41                 /* FIXME: there should be way to detect this */
  42                 clock-frequency = <50000000>;
  43         };
  44
  45         palmbus: palmbus@1E000000 {
  46                 compatible = "palmbus";
  47                 reg = <0x1E000000 0x100000>;
  48                 ranges = <0x0 0x1E000000 0x0FFFFF>;
  49
  50                 #address-cells = <1>;
  51                 #size-cells = <1>;
  52
  53                 sysc: sysc@0 {
  54                         compatible = "mtk,mt7621-sysc";
  55                         reg = <0x0 0x100>;
  56                 };
  57
  58                 wdt: wdt@100 {
  59                         compatible = "mtk,mt7621-wdt";
  60                         reg = <0x100 0x100>;
  61                 };
  62
  63                 gpio@600 {
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66
  67                         compatible = "mtk,mt7621-gpio";
  68                         reg = <0x600 0x100>;
  69
  70                         gpio0: bank@0 {
  71                                 reg = <0>;
  72                                 compatible = "mtk,mt7621-gpio-bank";
  73                                 gpio-controller;
  74                                 #gpio-cells = <2>;
  75                         };
  76
  77                         gpio1: bank@1 {
  78                                 reg = <1>;
  79                                 compatible = "mtk,mt7621-gpio-bank";
  80                                 gpio-controller;
  81                                 #gpio-cells = <2>;
  82                         };
  83
  84                         gpio2: bank@2 {
  85                                 reg = <2>;
  86                                 compatible = "mtk,mt7621-gpio-bank";
  87                                 gpio-controller;
  88                                 #gpio-cells = <2>;
  89                         };
  90                 };
  91
  92                 memc: memc@5000 {
  93                         compatible = "mtk,mt7621-memc";
  94                         reg = <0x300 0x100>;
  95                 };
  96
  97                 cpc: cpc@1fbf0000 {
  98                              compatible = "mtk,mt7621-cpc";
  99                              reg = <0x1fbf0000 0x8000>;
 100                 };
 101
 102                 mc: mc@1fbf8000 {
 103                             compatible = "mtk,mt7621-mc";
 104                             reg = <0x1fbf8000 0x8000>;
 105                 };
 106
 107                 uartlite: uartlite@c00 {
 108                         compatible = "ns16550a";
 109                         reg = <0xc00 0x100>;
 110
 111                         clocks = <&sysclock>;
 112                         clock-frequency = <50000000>;
 113
 114                         interrupt-parent = <&gic>;
 115                         interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
 116
 117                         reg-shift = <2>;
 118                         reg-io-width = <4>;
 119                         no-loopback-test;
 120                 };
 121
 122                 spi0: spi@b00 {
 123                         status = "okay";
 124
 125                         compatible = "ralink,mt7621-spi";
 126                         reg = <0xb00 0x100>;
 127
 128                         clocks = <&sysclock>;
 129
 130                         resets = <&rstctrl 18>;
 131                         reset-names = "spi";
 132
 133                         #address-cells = <1>;
 134                         #size-cells = <0>;
 135
 136                         pinctrl-names = "default";
 137                         pinctrl-0 = <&spi_pins>;
 138
 139                         m25p80@0 {
 140                                 #address-cells = <1>;
 141                                 #size-cells = <1>;
 142                                 reg = <0>;
 143                                 spi-max-frequency = <10000000>;
 144                                 m25p,chunked-io = <32>;
 145                         };
 146                 };
 147
 148                 gdma: gdma@2800 {
 149                         compatible = "ralink,rt3883-gdma";
 150                         reg = <0x2800 0x800>;
 151
 152                         resets = <&rstctrl 14>;
 153                         reset-names = "dma";
 154
 155                         interrupt-parent = <&gic>;
 156                         interrupts = <0 13 4>;
 157
 158                         #dma-cells = <1>;
 159                         #dma-channels = <16>;
 160                         #dma-requests = <16>;
 161
 162                         status = "disabled";
 163                 };
 164
 165                 hsdma: hsdma@7000 {
 166                         compatible = "mediatek,mt7621-hsdma";
 167                         reg = <0x7000 0x1000>;
 168
 169                         resets = <&rstctrl 5>;
 170                         reset-names = "hsdma";
 171
 172                         interrupt-parent = <&gic>;
 173                         interrupts = <0 11 4>;
 174
 175                         #dma-cells = <1>;
 176                         #dma-channels = <1>;
 177                         #dma-requests = <1>;
 178
 179                         status = "disabled";
 180                 };
 181         };
 182
 183         pinctrl: pinctrl {
 184                 compatible = "ralink,rt2880-pinmux";
 185                 pinctrl-names = "default";
 186                 pinctrl-0 = <&state_default>;
 187
 188                 state_default: pinctrl0 {
 189                 };
 190
 191                 spi_pins: spi {
 192                         spi {
 193                                 ralink,group = "spi";
 194                                 ralink,function = "spi";
 195                         };
 196                 };
 197
 198                 i2c_pins: i2c {
 199                         i2c {
 200                                 ralink,group = "i2c";
 201                                 ralink,function = "i2c";
 202                         };
 203                 };
 204
 205                 uart1_pins: uart1 {
 206                         uart1 {
 207                                 ralink,group = "uart1";
 208                                 ralink,function = "uart1";
 209                         };
 210                 };
 211
 212                 uart2_pins: uart2 {
 213                         uart2 {
 214                                 ralink,group = "uart2";
 215                                 ralink,function = "uart2";
 216                         };
 217                 };
 218
 219                 uart3_pins: uart3 {
 220                         uart3 {
 221                                 ralink,group = "uart3";
 222                                 ralink,function = "uart3";
 223                         };
 224                 };
 225
 226                 rgmii1_pins: rgmii1 {
 227                         rgmii1 {
 228                                 ralink,group = "rgmii1";
 229                                 ralink,function = "rgmii1";
 230                         };
 231                 };
 232
 233                 rgmii2_pins: rgmii2 {
 234                         rgmii2 {
 235                                 ralink,group = "rgmii2";
 236                                 ralink,function = "rgmii2";
 237                         };
 238                 };
 239
 240                 mdio_pins: mdio {
 241                         mdio {
 242                                 ralink,group = "mdio";
 243                                 ralink,function = "mdio";
 244                         };
 245                 };
 246
 247                 pcie_pins: pcie {
 248                         pcie {
 249                                 ralink,group = "pcie";
 250                                 ralink,function = "pcie rst";
 251                         };
 252                 };
 253
 254                 nand_pins: nand {
 255                         spi-nand {
 256                                 ralink,group = "spi";
 257                                 ralink,function = "nand1";
 258                         };
 259
 260                         sdhci-nand {
 261                                 ralink,group = "sdhci";
 262                                 ralink,function = "nand2";
 263                         };
 264                 };
 265
 266                 sdhci_pins: sdhci {
 267                         sdhci {
 268                                 ralink,group = "sdhci";
 269                                 ralink,function = "sdhci";
 270                         };
 271                 };
 272         };
 273
 274         rstctrl: rstctrl {
 275                 compatible = "ralink,rt2880-reset";
 276                 #reset-cells = <1>;
 277         };
 278
 279         clkctrl: clkctrl {
 280                 compatible = "ralink,rt2880-clock";
 281                 #clock-cells = <1>;
 282         };
 283
 284         sdhci: sdhci@1E130000 {
 285                 compatible = "ralink,mt7620-sdhci";
 286                 reg = <0x1E130000 0x4000>;
 287
 288                 interrupt-parent = <&gic>;
 289                 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
 290         };
 291
 292         xhci: xhci@1E1C0000 {
 293                 status = "okay";
 294
 295                 compatible = "mediatek,mt8173-xhci";
 296                 reg = <0x1e1c0000 0x1000
 297                        0x1e1d0700 0x0100>;
 298
 299                 clocks = <&sysclock>;
 300                 clock-names = "sys_ck";
 301
 302                 interrupt-parent = <&gic>;
 303                 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
 304         };
 305
 306         gic: interrupt-controller@1fbc0000 {
 307                 compatible = "mti,gic";
 308                 reg = <0x1fbc0000 0x2000>;
 309
 310                 interrupt-controller;
 311                 #interrupt-cells = <3>;
 312
 313                 mti,reserved-cpu-vectors = <7>;
 314
 315                 timer {
 316                         compatible = "mti,gic-timer";
 317                         interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
 318                         clocks = <&cpuclock>;
 319                 };
 320         };
 321
 322         nand: nand@1e003000 {
 323                 status = "disabled";
 324
 325                 compatible = "mtk,mt7621-nand";
 326                 bank-width = <2>;
 327                 reg = <0x1e003000 0x800
 328                         0x1e003800 0x800>;
 329                 #address-cells = <1>;
 330                 #size-cells = <1>;
 331         };
 332
 333         ethernet: ethernet@1e100000 {
 334                 compatible = "mediatek,mt7621-eth";
 335                 reg = <0x1e100000 0x10000>;
 336
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339
 340                 resets = <&rstctrl 6 &rstctrl 23>;
 341                 reset-names = "fe", "eth";
 342
 343                 interrupt-parent = <&gic>;
 344                 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
 345
 346                 mediatek,switch = <&gsw>;
 347
 348                 mdio-bus {
 349                         #address-cells = <1>;
 350                         #size-cells = <0>;
 351
 352                         phy1f: ethernet-phy@1f {
 353                                 reg = <0x1f>;
 354                                 phy-mode = "rgmii";
 355                         };
 356                 };
 357         };
 358
 359         gsw: gsw@1e110000 {
 360                 compatible = "mediatek,mt7621-gsw";
 361                 reg = <0x1e110000 0x8000>;
 362                 interrupt-parent = <&gic>;
 363                 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
 364         };
 365
 366         pcie: pcie@1e140000 {
 367                 compatible = "mediatek,mt7621-pci";
 368                 reg = <0x1e140000 0x100
 369                         0x1e142000 0x100>;
 370
 371                 #address-cells = <3>;
 372                 #size-cells = <2>;
 373
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&pcie_pins>;
 376
 377                 device_type = "pci";
 378
 379                 bus-range = <0 255>;
 380                 ranges = <
 381                         0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
 382                         0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
 383                 >;
 384
 385                 interrupt-parent = <&gic>;
 386                 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
 387                                 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
 388                                 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
 389
 390                 status = "okay";
 391
 392                 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
 393                 reset-names = "pcie0", "pcie1", "pcie2";
 394                 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
 395                 clock-names = "pcie0", "pcie1", "pcie2";
 396
 397                 pcie0 {
 398                         reg = <0x0000 0 0 0 0>;
 399
 400                         #address-cells = <3>;
 401                         #size-cells = <2>;
 402
 403                         device_type = "pci";
 404                 };
 405
 406                 pcie1 {
 407                         reg = <0x0800 0 0 0 0>;
 408
 409                         #address-cells = <3>;
 410                         #size-cells = <2>;
 411
 412                         device_type = "pci";
 413                 };
 414
 415                 pcie2 {
 416                         reg = <0x1000 0 0 0 0>;
 417
 418                         #address-cells = <3>;
 419                         #size-cells = <2>;
 420
 421                         device_type = "pci";
 422                 };
 423         };
 424 };