1 #include <dt-bindings/interrupt-controller/mips-gic.h>
2 #include <dt-bindings/clock/mt7621-clk.h>
7 compatible = "mediatek,mt7621-soc";
15 compatible = "mips,mips1004Kc";
21 compatible = "mips,mips1004Kc";
28 #interrupt-cells = <1>;
30 compatible = "mti,cpu-interrupt-controller";
38 compatible = "mediatek,mt7621-pll", "syscon";
41 clock-output-names = "cpu", "bus";
46 compatible = "fixed-clock";
48 /* FIXME: there should be way to detect this */
49 clock-frequency = <50000000>;
54 palmbus: palmbus@1E000000 {
55 compatible = "palmbus";
56 reg = <0x1E000000 0x100000>;
57 ranges = <0x0 0x1E000000 0x0FFFFF>;
63 compatible = "mtk,mt7621-sysc";
68 compatible = "mediatek,mt7621-wdt";
76 compatible = "mtk,mt7621-gpio";
81 compatible = "mtk,mt7621-gpio-bank";
88 compatible = "mtk,mt7621-gpio-bank";
95 compatible = "mtk,mt7621-gpio-bank";
102 compatible = "mediatek,mt7621-i2c";
105 clocks = <&sysclock>;
107 resets = <&rstctrl 16>;
110 #address-cells = <1>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2c_pins>;
120 compatible = "mediatek,mt7621-i2s";
123 clocks = <&sysclock>;
125 resets = <&rstctrl 17>;
128 interrupt-parent = <&gic>;
129 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
136 dma-names = "tx", "rx";
141 systick: systick@500 {
142 compatible = "ralink,mt7621-systick", "ralink,cevt-systick";
145 resets = <&rstctrl 28>;
146 reset-names = "intc";
148 interrupt-parent = <&gic>;
149 interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
153 compatible = "mtk,mt7621-memc";
154 reg = <0x5000 0x1000>;
158 compatible = "mtk,mt7621-cpc";
159 reg = <0x1fbf0000 0x8000>;
163 compatible = "mtk,mt7621-mc";
164 reg = <0x1fbf8000 0x8000>;
167 uartlite: uartlite@c00 {
168 compatible = "ns16550a";
171 clock-frequency = <50000000>;
173 interrupt-parent = <&gic>;
174 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
181 uartlite2: uartlite2@d00 {
182 compatible = "ns16550a";
185 clock-frequency = <50000000>;
187 interrupt-parent = <&gic>;
188 interrupts = <GIC_SHARED 27 IRQ_TYPE_LEVEL_HIGH>;
193 pinctrl-names = "default";
194 pinctrl-0 = <&uart2_pins>;
199 uartlite3: uartlite3@e00 {
200 compatible = "ns16550a";
203 clock-frequency = <50000000>;
205 interrupt-parent = <&gic>;
206 interrupts = <GIC_SHARED 28 IRQ_TYPE_LEVEL_HIGH>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&uart3_pins>;
220 compatible = "ralink,mt7621-spi";
223 clocks = <&pll MT7621_CLK_BUS>;
225 resets = <&rstctrl 18>;
228 #address-cells = <1>;
231 pinctrl-names = "default";
232 pinctrl-0 = <&spi_pins>;
236 compatible = "ralink,rt3883-gdma";
237 reg = <0x2800 0x800>;
239 resets = <&rstctrl 14>;
242 interrupt-parent = <&gic>;
243 interrupts = <0 13 4>;
246 #dma-channels = <16>;
247 #dma-requests = <16>;
253 compatible = "mediatek,mt7621-hsdma";
254 reg = <0x7000 0x1000>;
256 resets = <&rstctrl 5>;
257 reset-names = "hsdma";
259 interrupt-parent = <&gic>;
260 interrupts = <0 11 4>;
271 compatible = "ralink,rt2880-pinmux";
272 pinctrl-names = "default";
273 pinctrl-0 = <&state_default>;
275 state_default: pinctrl0 {
280 ralink,group = "i2c";
281 ralink,function = "i2c";
287 ralink,group = "spi";
288 ralink,function = "spi";
294 ralink,group = "uart1";
295 ralink,function = "uart1";
301 ralink,group = "uart2";
302 ralink,function = "uart2";
308 ralink,group = "uart3";
309 ralink,function = "uart3";
313 rgmii1_pins: rgmii1 {
315 ralink,group = "rgmii1";
316 ralink,function = "rgmii1";
320 rgmii2_pins: rgmii2 {
322 ralink,group = "rgmii2";
323 ralink,function = "rgmii2";
329 ralink,group = "mdio";
330 ralink,function = "mdio";
336 ralink,group = "pcie";
337 ralink,function = "pcie rst";
343 ralink,group = "spi";
344 ralink,function = "nand1";
348 ralink,group = "sdhci";
349 ralink,function = "nand2";
355 ralink,group = "sdhci";
356 ralink,function = "sdhci";
362 compatible = "ralink,rt2880-reset";
367 compatible = "ralink,rt2880-clock";
371 sdhci: sdhci@1E130000 {
374 compatible = "ralink,mt7620-sdhci";
375 reg = <0x1E130000 0x4000>;
377 interrupt-parent = <&gic>;
378 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&sdhci_pins>;
384 xhci: xhci@1E1C0000 {
385 #address-cells = <1>;
389 compatible = "mediatek,mt8173-xhci";
390 reg = <0x1e1c0000 0x1000
392 reg-names = "mac", "ippc";
394 clocks = <&sysclock>;
395 clock-names = "sys_ck";
397 interrupt-parent = <&gic>;
398 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
401 * Port 1 of both hubs is one usb slot and referenced here.
402 * The binding doesn't allow to address individual hubs.
403 * hub 1 - port 1 is ehci and ohci, hub 2 - port 1 is xhci.
405 xhci_ehci_port1: port@1 {
407 #trigger-source-cells = <0>;
411 * Only the second usb hub has a second port. That port serves
416 #trigger-source-cells = <0>;
420 gic: interrupt-controller@1fbc0000 {
421 compatible = "mti,gic";
422 reg = <0x1fbc0000 0x2000>;
424 interrupt-controller;
425 #interrupt-cells = <3>;
427 mti,reserved-cpu-vectors = <7>;
430 compatible = "mti,gic-timer";
431 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
432 clocks = <&pll MT7621_CLK_CPU>;
436 nand: nand@1e003000 {
439 compatible = "mtk,mt7621-nand";
441 reg = <0x1e003000 0x800
445 ethernet: ethernet@1e100000 {
446 compatible = "mediatek,mt7621-eth";
447 reg = <0x1e100000 0x10000>;
449 #address-cells = <1>;
452 resets = <&rstctrl 6 &rstctrl 23>;
453 reset-names = "fe", "eth";
455 interrupt-parent = <&gic>;
456 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
458 mediatek,switch = <&gsw>;
461 #address-cells = <1>;
464 phy1f: ethernet-phy@1f {
471 compatible = "mediatek,mt7623-hnat";
476 resets = <&rstctrl 0>;
477 reset-names = "mtketh";
482 compatible = "mediatek,mt7621-gsw";
483 reg = <0x1e110000 0x8000>;
484 interrupt-parent = <&gic>;
485 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
488 pcie: pcie@1e140000 {
489 compatible = "mediatek,mt7621-pci";
490 reg = <0x1e140000 0x100
493 #address-cells = <3>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pcie_pins>;
503 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
504 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
507 interrupt-parent = <&gic>;
508 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
509 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
510 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
514 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
515 reset-names = "pcie0", "pcie1", "pcie2";
516 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
517 clock-names = "pcie0", "pcie1", "pcie2";
520 reg = <0x0000 0 0 0 0>;
522 #address-cells = <3>;
529 reg = <0x0800 0 0 0 0>;
531 #address-cells = <3>;
538 reg = <0x1000 0 0 0 0>;
540 #address-cells = <3>;