1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mtk7621-soc";
10 compatible = "mips,mips1004Kc";
14 compatible = "mips,mips1004Kc";
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
29 cpuclock: cpuclock@0 {
31 compatible = "fixed-clock";
33 /* FIXME: there should be way to detect this */
34 clock-frequency = <880000000>;
37 sysclock: sysclock@0 {
39 compatible = "fixed-clock";
41 /* FIXME: there should be way to detect this */
42 clock-frequency = <50000000>;
46 compatible = "palmbus";
47 reg = <0x1E000000 0x100000>;
48 ranges = <0x0 0x1E000000 0x0FFFFF>;
54 compatible = "mtk,mt7621-sysc";
59 compatible = "mtk,mt7621-wdt";
67 compatible = "mtk,mt7621-gpio";
72 compatible = "mtk,mt7621-gpio-bank";
79 compatible = "mtk,mt7621-gpio-bank";
86 compatible = "mtk,mt7621-gpio-bank";
93 compatible = "mtk,mt7621-memc";
98 compatible = "mtk,mt7621-cpc";
99 reg = <0x1fbf0000 0x8000>;
103 compatible = "mtk,mt7621-mc";
104 reg = <0x1fbf8000 0x8000>;
107 uartlite: uartlite@c00 {
108 compatible = "ns16550a";
111 clocks = <&sysclock>;
113 interrupt-parent = <&gic>;
114 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
124 compatible = "ralink,mt7621-spi";
127 clocks = <&sysclock>;
129 resets = <&rstctrl 18>;
132 #address-cells = <1>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&spi_pins>;
139 #address-cells = <1>;
142 spi-max-frequency = <10000000>;
143 m25p,chunked-io = <32>;
149 compatible = "ralink,rt2880-pinmux";
150 pinctrl-names = "default";
151 pinctrl-0 = <&state_default>;
153 state_default: pinctrl0 {
158 ralink,group = "spi";
159 ralink,function = "spi";
165 ralink,group = "i2c";
166 ralink,function = "i2c";
172 ralink,group = "uart1";
173 ralink,function = "uart1";
179 ralink,group = "uart2";
180 ralink,function = "uart2";
186 ralink,group = "uart3";
187 ralink,function = "uart3";
191 rgmii1_pins: rgmii1 {
193 ralink,group = "rgmii1";
194 ralink,function = "rgmii1";
198 rgmii2_pins: rgmii2 {
200 ralink,group = "rgmii2";
201 ralink,function = "rgmii2";
207 ralink,group = "mdio";
208 ralink,function = "mdio";
214 ralink,group = "pcie";
215 ralink,function = "pcie rst";
221 ralink,group = "spi";
222 ralink,function = "nand1";
226 ralink,group = "sdhci";
227 ralink,function = "nand2";
233 ralink,group = "sdhci";
234 ralink,function = "sdhci";
240 compatible = "ralink,rt2880-reset";
245 compatible = "ralink,mt7620-sdhci";
246 reg = <0x1E130000 0x4000>;
248 interrupt-parent = <&gic>;
249 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
255 compatible = "mediatek,mt8173-xhci";
256 reg = <0x1e1c0000 0x1000
259 clocks = <&sysclock>;
260 clock-names = "sys_ck";
262 interrupt-parent = <&gic>;
263 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
266 gic: interrupt-controller@1fbc0000 {
267 compatible = "mti,gic";
268 reg = <0x1fbc0000 0x2000>;
270 interrupt-controller;
271 #interrupt-cells = <3>;
273 mti,reserved-cpu-vectors = <7>;
276 compatible = "mti,gic-timer";
277 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
278 clocks = <&cpuclock>;
285 compatible = "mtk,mt7621-nand";
287 reg = <0x1e003000 0x800
289 #address-cells = <1>;
294 compatible = "mediatek,mt7621-eth";
295 reg = <0x1e100000 0x10000>;
297 #address-cells = <1>;
300 resets = <&rstctrl 6 &rstctrl 23>;
301 reset-names = "fe", "eth";
303 interrupt-parent = <&gic>;
304 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
306 mediatek,switch = <&gsw>;
309 #address-cells = <1>;
312 phy1f: ethernet-phy@1f {
320 compatible = "mediatek,mt7621-gsw";
321 reg = <0x1e110000 0x8000>;
322 interrupt-parent = <&gic>;
323 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
327 compatible = "mediatek,mt7621-pci";
328 reg = <0x1e140000 0x100
331 #address-cells = <3>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&pcie_pins>;
341 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
342 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
345 interrupt-parent = <&gic>;
346 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
347 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
348 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
353 reg = <0x0000 0 0 0 0>;
355 #address-cells = <3>;
362 reg = <0x0800 0 0 0 0>;
364 #address-cells = <3>;
371 reg = <0x1000 0 0 0 0>;
373 #address-cells = <3>;