1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mt7621-soc";
10 compatible = "mips,mips1004Kc";
14 compatible = "mips,mips1004Kc";
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
29 cpuclock: cpuclock@0 {
31 compatible = "fixed-clock";
33 /* FIXME: there should be way to detect this */
34 clock-frequency = <880000000>;
37 sysclock: sysclock@0 {
39 compatible = "fixed-clock";
41 /* FIXME: there should be way to detect this */
42 clock-frequency = <50000000>;
45 palmbus: palmbus@1E000000 {
46 compatible = "palmbus";
47 reg = <0x1E000000 0x100000>;
48 ranges = <0x0 0x1E000000 0x0FFFFF>;
54 compatible = "mtk,mt7621-sysc";
59 compatible = "mtk,mt7621-wdt";
67 compatible = "mtk,mt7621-gpio";
72 compatible = "mtk,mt7621-gpio-bank";
79 compatible = "mtk,mt7621-gpio-bank";
86 compatible = "mtk,mt7621-gpio-bank";
93 compatible = "mediatek,mt7621-i2c";
98 resets = <&rstctrl 16>;
101 #address-cells = <1>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&i2c_pins>;
111 compatible = "mediatek,mt7621-i2s";
114 clocks = <&sysclock>;
116 resets = <&rstctrl 17>;
119 interrupt-parent = <&gic>;
120 interrupts = <GIC_SHARED 16 IRQ_TYPE_LEVEL_HIGH>;
127 dma-names = "tx", "rx";
133 compatible = "mtk,mt7621-memc";
138 compatible = "mtk,mt7621-cpc";
139 reg = <0x1fbf0000 0x8000>;
143 compatible = "mtk,mt7621-mc";
144 reg = <0x1fbf8000 0x8000>;
147 uartlite: uartlite@c00 {
148 compatible = "ns16550a";
151 clocks = <&sysclock>;
152 clock-frequency = <50000000>;
154 interrupt-parent = <&gic>;
155 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
165 compatible = "ralink,mt7621-spi";
168 clocks = <&sysclock>;
170 resets = <&rstctrl 18>;
173 #address-cells = <1>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&spi_pins>;
181 compatible = "ralink,rt3883-gdma";
182 reg = <0x2800 0x800>;
184 resets = <&rstctrl 14>;
187 interrupt-parent = <&gic>;
188 interrupts = <0 13 4>;
191 #dma-channels = <16>;
192 #dma-requests = <16>;
198 compatible = "mediatek,mt7621-hsdma";
199 reg = <0x7000 0x1000>;
201 resets = <&rstctrl 5>;
202 reset-names = "hsdma";
204 interrupt-parent = <&gic>;
205 interrupts = <0 11 4>;
216 compatible = "ralink,rt2880-pinmux";
217 pinctrl-names = "default";
218 pinctrl-0 = <&state_default>;
220 state_default: pinctrl0 {
225 ralink,group = "i2c";
226 ralink,function = "i2c";
232 ralink,group = "spi";
233 ralink,function = "spi";
239 ralink,group = "uart1";
240 ralink,function = "uart1";
246 ralink,group = "uart2";
247 ralink,function = "uart2";
253 ralink,group = "uart3";
254 ralink,function = "uart3";
258 rgmii1_pins: rgmii1 {
260 ralink,group = "rgmii1";
261 ralink,function = "rgmii1";
265 rgmii2_pins: rgmii2 {
267 ralink,group = "rgmii2";
268 ralink,function = "rgmii2";
274 ralink,group = "mdio";
275 ralink,function = "mdio";
281 ralink,group = "pcie";
282 ralink,function = "pcie rst";
288 ralink,group = "spi";
289 ralink,function = "nand1";
293 ralink,group = "sdhci";
294 ralink,function = "nand2";
300 ralink,group = "sdhci";
301 ralink,function = "sdhci";
307 compatible = "ralink,rt2880-reset";
312 compatible = "ralink,rt2880-clock";
316 sdhci: sdhci@1E130000 {
319 compatible = "ralink,mt7620-sdhci";
320 reg = <0x1E130000 0x4000>;
322 interrupt-parent = <&gic>;
323 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
326 xhci: xhci@1E1C0000 {
329 compatible = "mediatek,mt8173-xhci";
330 reg = <0x1e1c0000 0x1000
333 clocks = <&sysclock>;
334 clock-names = "sys_ck";
336 interrupt-parent = <&gic>;
337 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
340 gic: interrupt-controller@1fbc0000 {
341 compatible = "mti,gic";
342 reg = <0x1fbc0000 0x2000>;
344 interrupt-controller;
345 #interrupt-cells = <3>;
347 mti,reserved-cpu-vectors = <7>;
350 compatible = "mti,gic-timer";
351 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
352 clocks = <&cpuclock>;
356 nand: nand@1e003000 {
359 compatible = "mtk,mt7621-nand";
361 reg = <0x1e003000 0x800
363 #address-cells = <1>;
367 ethernet: ethernet@1e100000 {
368 compatible = "mediatek,mt7621-eth";
369 reg = <0x1e100000 0x10000>;
371 #address-cells = <1>;
374 resets = <&rstctrl 6 &rstctrl 23>;
375 reset-names = "fe", "eth";
377 interrupt-parent = <&gic>;
378 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
380 mediatek,switch = <&gsw>;
383 #address-cells = <1>;
386 phy1f: ethernet-phy@1f {
394 compatible = "mediatek,mt7621-gsw";
395 reg = <0x1e110000 0x8000>;
396 interrupt-parent = <&gic>;
397 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
400 pcie: pcie@1e140000 {
401 compatible = "mediatek,mt7621-pci";
402 reg = <0x1e140000 0x100
405 #address-cells = <3>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pcie_pins>;
415 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
416 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
419 interrupt-parent = <&gic>;
420 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
421 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
422 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
426 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
427 reset-names = "pcie0", "pcie1", "pcie2";
428 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
429 clock-names = "pcie0", "pcie1", "pcie2";
432 reg = <0x0000 0 0 0 0>;
434 #address-cells = <3>;
441 reg = <0x0800 0 0 0 0>;
443 #address-cells = <3>;
450 reg = <0x1000 0 0 0 0>;
452 #address-cells = <3>;