1 #include <dt-bindings/interrupt-controller/mips-gic.h>
6 compatible = "mediatek,mtk7621-soc";
10 compatible = "mips,mips1004Kc";
14 compatible = "mips,mips1004Kc";
20 #interrupt-cells = <1>;
22 compatible = "mti,cpu-interrupt-controller";
29 cpuclock: cpuclock@0 {
31 compatible = "fixed-clock";
33 /* FIXME: there should be way to detect this */
34 clock-frequency = <880000000>;
37 sysclock: sysclock@0 {
39 compatible = "fixed-clock";
41 /* FIXME: there should be way to detect this */
42 clock-frequency = <50000000>;
45 palmbus: palmbus@1E000000 {
46 compatible = "palmbus";
47 reg = <0x1E000000 0x100000>;
48 ranges = <0x0 0x1E000000 0x0FFFFF>;
54 compatible = "mtk,mt7621-sysc";
59 compatible = "mtk,mt7621-wdt";
67 compatible = "mtk,mt7621-gpio";
72 compatible = "mtk,mt7621-gpio-bank";
79 compatible = "mtk,mt7621-gpio-bank";
86 compatible = "mtk,mt7621-gpio-bank";
93 compatible = "mtk,mt7621-memc";
98 compatible = "mtk,mt7621-cpc";
99 reg = <0x1fbf0000 0x8000>;
103 compatible = "mtk,mt7621-mc";
104 reg = <0x1fbf8000 0x8000>;
107 uartlite: uartlite@c00 {
108 compatible = "ns16550a";
111 clocks = <&sysclock>;
112 clock-frequency = <50000000>;
114 interrupt-parent = <&gic>;
115 interrupts = <GIC_SHARED 26 IRQ_TYPE_LEVEL_HIGH>;
125 compatible = "ralink,mt7621-spi";
128 clocks = <&sysclock>;
130 resets = <&rstctrl 18>;
133 #address-cells = <1>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&spi_pins>;
140 #address-cells = <1>;
143 spi-max-frequency = <10000000>;
144 m25p,chunked-io = <32>;
150 compatible = "ralink,rt2880-pinmux";
151 pinctrl-names = "default";
152 pinctrl-0 = <&state_default>;
154 state_default: pinctrl0 {
159 ralink,group = "spi";
160 ralink,function = "spi";
166 ralink,group = "i2c";
167 ralink,function = "i2c";
173 ralink,group = "uart1";
174 ralink,function = "uart1";
180 ralink,group = "uart2";
181 ralink,function = "uart2";
187 ralink,group = "uart3";
188 ralink,function = "uart3";
192 rgmii1_pins: rgmii1 {
194 ralink,group = "rgmii1";
195 ralink,function = "rgmii1";
199 rgmii2_pins: rgmii2 {
201 ralink,group = "rgmii2";
202 ralink,function = "rgmii2";
208 ralink,group = "mdio";
209 ralink,function = "mdio";
215 ralink,group = "pcie";
216 ralink,function = "pcie rst";
222 ralink,group = "spi";
223 ralink,function = "nand1";
227 ralink,group = "sdhci";
228 ralink,function = "nand2";
234 ralink,group = "sdhci";
235 ralink,function = "sdhci";
241 compatible = "ralink,rt2880-reset";
246 compatible = "ralink,rt2880-clock";
250 sdhci: sdhci@1E130000 {
251 compatible = "ralink,mt7620-sdhci";
252 reg = <0x1E130000 0x4000>;
254 interrupt-parent = <&gic>;
255 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>;
258 xhci: xhci@1E1C0000 {
261 compatible = "mediatek,mt8173-xhci";
262 reg = <0x1e1c0000 0x1000
265 clocks = <&sysclock>;
266 clock-names = "sys_ck";
268 interrupt-parent = <&gic>;
269 interrupts = <GIC_SHARED 22 IRQ_TYPE_LEVEL_HIGH>;
272 gic: interrupt-controller@1fbc0000 {
273 compatible = "mti,gic";
274 reg = <0x1fbc0000 0x2000>;
276 interrupt-controller;
277 #interrupt-cells = <3>;
279 mti,reserved-cpu-vectors = <7>;
282 compatible = "mti,gic-timer";
283 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
284 clocks = <&cpuclock>;
288 nand: nand@1e003000 {
291 compatible = "mtk,mt7621-nand";
293 reg = <0x1e003000 0x800
295 #address-cells = <1>;
299 ethernet: ethernet@1e100000 {
300 compatible = "mediatek,mt7621-eth";
301 reg = <0x1e100000 0x10000>;
303 #address-cells = <1>;
306 resets = <&rstctrl 6 &rstctrl 23>;
307 reset-names = "fe", "eth";
309 interrupt-parent = <&gic>;
310 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
312 mediatek,switch = <&gsw>;
315 #address-cells = <1>;
318 phy1f: ethernet-phy@1f {
326 compatible = "mediatek,mt7621-gsw";
327 reg = <0x1e110000 0x8000>;
328 interrupt-parent = <&gic>;
329 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
332 pcie: pcie@1e140000 {
333 compatible = "mediatek,mt7621-pci";
334 reg = <0x1e140000 0x100
337 #address-cells = <3>;
340 pinctrl-names = "default";
341 pinctrl-0 = <&pcie_pins>;
347 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
348 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
351 interrupt-parent = <&gic>;
352 interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
353 GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
354 GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
358 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
359 reset-names = "pcie0", "pcie1", "pcie2";
360 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
361 clock-names = "pcie0", "pcie1", "pcie2";
364 reg = <0x0000 0 0 0 0>;
366 #address-cells = <3>;
373 reg = <0x0800 0 0 0 0>;
375 #address-cells = <3>;
382 reg = <0x1000 0 0 0 0>;
384 #address-cells = <3>;