1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 #include "mt7620a.dtsi"
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
11 compatible = "ralink,mt7620a-soc";
14 led-boot = &led_power;
15 led-failsafe = &led_power;
16 led-running = &led_power;
17 led-upgrade = &led_power;
21 bootargs = "console=ttyS0,57600";
25 compatible = "gpio-keys";
29 gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
30 linux,code = <KEY_RESTART>;
34 label = "switch high";
35 gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
37 linux,input-type = <EV_SW>;
42 gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
44 linux,input-type = <EV_SW>;
61 compatible = "jedec,spi-nor";
63 spi-max-frequency = <10000000>;
66 compatible = "fixed-partitions";
78 reg = <0x30000 0x10000>;
82 factory: partition@40000 {
84 reg = <0x40000 0x10000>;
90 reg = <0x50000 0x20000>;
95 compatible = "edimax,uimage";
97 reg = <0x00070000 0x00790000>;
104 state_default: pinctrl0 {
106 ralink,group = "i2c", "uartf", "nd_sd", "rgmii2";
107 ralink,function = "gpio";
111 phy_reset_pins: phy-reset {
113 ralink,group = "spi refclk";
114 ralink,function = "gpio";
122 mtd-mac-address = <&factory 0x4>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&rgmii1_pins &mdio_pins &phy_reset_pins>;
127 mediatek,portmap = "l";
128 mediatek,mdio-mode = <1>;
130 phy-reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
131 phy-reset-duration = <30>;
135 mediatek,fixed-link = <1000 1 1 1>;
142 phy0: ethernet-phy@0 {
148 phy1: ethernet-phy@1 {
154 phy2: ethernet-phy@2 {
160 phy3: ethernet-phy@3 {
166 phy4: ethernet-phy@4 {
175 mediatek,port5 = "gmac";
179 ralink,mtd-eeprom = <&factory 0>;
188 reg = <0x0000 0 0 0 0>;
189 mediatek,mtd-eeprom = <&factory 0x8000>;