target/linux/ramips/dts/BR-6478AC-V2.dts

   1 /*
   2  * Device Tree file for the Edimax BR-6478AC V2
   3  * based on Linksys E1700
   4  *
   5  * Copyright (C) 2016 Rohan Murch <rohan.murch@gmail.com>
   6  * Copyright (C) 2016 Hans Ulli Kroll <ulli.kroll@googlemail.com>
   7  * Copyright (C) 2017 James McKenzie <openwrt@madingley.org>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2.  This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 /dts-v1/;
  15
  16 #include "mt7620a.dtsi"
  17
  18 #include <dt-bindings/gpio/gpio.h>
  19 #include <dt-bindings/input/input.h>
  20
  21 / {
  22         compatible = "edimax,br-6478ac-v2", "ralink,mt7620a-soc";
  23         model = "Edimax BR-6478AC v2";
  24
  25         aliases {
  26                 led-status = &led_power;
  27         };
  28
  29         chosen {
  30                 bootargs = "console=ttyS0,57600";
  31         };
  32
  33         gpio-keys-polled {
  34                 compatible = "gpio-keys-polled";
  35                 #address-cells = <1>;
  36                 #size-cells = <0>;
  37                 poll-interval = <20>;
  38
  39                 reset_wps {
  40                         label = "reset_wps";
  41                         gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
  42                         linux,code = <KEY_RESTART>;
  43                 };
  44         };
  45
  46         gpio-leds {
  47                 compatible = "gpio-leds";
  48
  49                 led_power: power {
  50                         label = "br-6478ac-v2:white:power";
  51                         gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
  52                 };
  53                 wan {
  54                         label = "br-6478ac-v2:blue:wan";
  55                         gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
  56                 };
  57                 wlan {
  58                         label = "br-6478ac-v2:blue:wlan";
  59                         gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  60                 };
  61                 usb {
  62                         label = "br-6478ac-v2:blue:usb";
  63                         gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
  64                 };
  65         };
  66
  67
  68         gpio_export {
  69                 compatible = "gpio-export";
  70                 #size-cells = <0>;
  71                 usb-power {
  72                         gpio-export,name="usb-power";
  73                         gpio-export,output=<1>;
  74                         gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;  /* pin45 */
  75                 };
  76         };
  77 };
  78
  79
  80 &gpio2 {
  81         status = "okay";
  82 };
  83
  84
  85 &spi0 {
  86         status = "okay";
  87
  88         m25p80@0 {
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 compatible = "jedec,spi-nor";
  92                 reg = <0 0>;
  93                 linux,modalias = "m25p80", "mx25l6405d";
  94                 spi-max-frequency = <10000000>;
  95
  96                 partition@0 {
  97                         label = "u-boot";
  98                         reg = <0x0 0x30000>;
  99                         read-only;
 100                 };
 101
 102                 partition@30000 {
 103                         label = "u-boot-env";
 104                         reg = <0x30000 0x10000>;
 105                         read-only;
 106                 };
 107
 108                 factory: partition@40000 {
 109                         label = "factory";
 110                         reg = <0x40000 0x10000>;
 111                         read-only;
 112                 };
 113
 114                 partition@50000 {
 115                         label = "cimage";
 116                         reg = <0x50000 0x20000>;
 117                         read-only;
 118                 };
 119
 120                 partition@70000 {
 121                         label = "firmware";
 122                         reg = <0x00070000 0x00790000>;
 123                 };
 124         };
 125 };
 126
 127 &pinctrl {
 128         state_default: pinctrl0 {
 129                 gpio {
 130                         ralink,group = "i2c", "uartf", "wdt", "pa",
 131                                         "ephy", "nd_sd", "wled";
 132                         ralink,function = "gpio";
 133                 };
 134         };
 135 };
 136
 137 &ethernet {
 138         status = "okay";
 139         mtd-mac-address = <&factory 0x4>;
 140         pinctrl-names = "default";
 141         pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
 142         mediatek,portmap = "wllll";
 143
 144         port@5 {
 145                 status = "okay";
 146                 mediatek,fixed-link = <1000 1 1 1>;
 147                 phy-mode = "rgmii";
 148         };
 149
 150         mdio-bus {
 151                 status = "okay";
 152
 153                 phy0: ethernet-phy@0 {
 154                         reg = <0>;
 155                         phy-mode = "rgmii";
 156                 };
 157
 158                 phy1: ethernet-phy@1 {
 159                         reg = <1>;
 160                         phy-mode = "rgmii";
 161                 };
 162
 163                 phy2: ethernet-phy@2 {
 164                         reg = <2>;
 165                         phy-mode = "rgmii";
 166                 };
 167
 168                 phy3: ethernet-phy@3 {
 169                         reg = <3>;
 170                         phy-mode = "rgmii";
 171                 };
 172
 173                 phy4: ethernet-phy@4 {
 174                         reg = <4>;
 175                         phy-mode = "rgmii";
 176                 };
 177
 178                 phy1f: ethernet-phy@1f {
 179                         reg = <0x1f>;
 180                         phy-mode = "rgmii";
 181                 };
 182         };
 183 };
 184
 185 &gsw {
 186         mediatek,port4 = "gmac";
 187 };
 188
 189
 190 &wmac {
 191         ralink,mtd-eeprom = <&factory 0>;
 192 };
 193
 194 &pcie {
 195         status = "okay";
 196
 197         pcie-bridge {
 198                 mt76@0,0 {
 199                         reg = <0x0000 0 0 0 0>;
 200                         device_type = "pci";
 201                         mediatek,mtd-eeprom = <&factory 0x8000>;
 202                         mediatek,2ghz = <0>;
 203                 };
 204         };
 205
 206 };
 207
 208 &ehci {
 209         status = "okay";
 210 };
 211
 212 &ohci {
 213         status = "okay";
 214 };