1 --- a/arch/powerpc/boot/Makefile
2 +++ b/arch/powerpc/boot/Makefile
4 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
5 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
6 cuboot-acadia.c cuboot-amigaone.c cuboot-magicboxv1.c \
8 + cuboot-magicboxv2.c cuboot-openrb-light.c
9 src-boot := $(src-wlib) $(src-plat) empty.c
11 src-boot := $(addprefix $(obj)/, $(src-boot))
13 image-$(CONFIG_ACADIA) += cuImage.acadia
14 image-$(CONFIG_MAGICBOXV1) += cuImage.magicboxv1
15 image-$(CONFIG_MAGICBOXV2) += cuImage.magicboxv2
16 +image-$(CONFIG_OPENRB_LIGHT) += cuImage.openrb-light
18 # Board ports in arch/powerpc/platform/44x/Kconfig
19 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
20 --- a/arch/powerpc/platforms/40x/Kconfig
21 +++ b/arch/powerpc/platforms/40x/Kconfig
24 This option enables support for the AMCC PPC405EX board.
30 + select PPC40x_SIMPLE
34 + This option enables support for the OpenRB Light board.
39 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
40 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
48 static int __init ppc40x_probe(void)
50 +++ b/arch/powerpc/boot/cuboot-openrb-light.c
53 + * Old U-boot compatibility for OpenRB Light board
55 + * Author: Gabor Juhos <juhosg@openwrt.org>
57 + * This program is free software; you can redistribute it and/or modify it
58 + * under the terms of the GNU General Public License version 2 as published
59 + * by the Free Software Foundation.
76 +static void openrb_light_fixups(void)
78 + ibm405ep_fixup_clocks(33333000);
79 + ibm4xx_sdram_fixup_memsize();
80 + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
83 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
84 + unsigned long r6, unsigned long r7)
87 + platform_ops.fixups = openrb_light_fixups;
88 + platform_ops.exit = ibm40x_dbcr_reset;
89 + fdt_init(_dtb_start);
90 + serial_console_init();
94 +++ b/arch/powerpc/boot/dts/openrb-light.dts
97 + * Device Tree Source for OpenRB Light board
99 + * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
101 + * Based on magicboxv2.dts
103 + * This file is licensed under the terms of the GNU General Public
104 + * License version 2. This program is licensed "as is" without
105 + * any warranty of any kind, whether express or implied.
111 + #address-cells = <1>;
113 + model = "openrb,light";
114 + compatible = "openrb,light";
115 + dcr-parent = <&{/cpus/cpu@0}>;
118 + ethernet0 = &EMAC0;
124 + #address-cells = <1>;
128 + device_type = "cpu";
129 + model = "PowerPC,405EP";
130 + reg = <0x00000000>;
131 + clock-frequency = <0xbebc200>; /* Filled in by zImage */
132 + timebase-frequency = <0>; /* Filled in by zImage */
133 + i-cache-line-size = <20>;
134 + d-cache-line-size = <20>;
135 + i-cache-size = <4000>;
136 + d-cache-size = <4000>;
138 + dcr-access-method = "native";
143 + device_type = "memory";
144 + reg = <0x00000000 0x00000000>; /* Filled in by zImage */
147 + UIC0: interrupt-controller {
148 + compatible = "ibm,uic";
149 + interrupt-controller;
151 + dcr-reg = <0x0c0 0x009>;
152 + #address-cells = <0>;
154 + #interrupt-cells = <2>;
158 + compatible = "ibm,plb3";
159 + #address-cells = <1>;
162 + clock-frequency = <0>; /* Filled in by zImage */
164 + SDRAM0: memory-controller {
165 + compatible = "ibm,sdram-405ep";
166 + dcr-reg = <0x010 0x002>;
170 + compatible = "ibm,mcmal-405ep", "ibm,mcmal";
171 + dcr-reg = <0x180 0x062>;
172 + num-tx-chans = <4>;
173 + num-rx-chans = <2>;
174 + interrupt-parent = <&UIC0>;
176 + 0xb 0x4 /* TXEOB */
177 + 0xc 0x4 /* RXEOB */
180 + 0xe 0x4 /* RXDE */>;
184 + compatible = "ibm,opb-405ep", "ibm,opb";
185 + #address-cells = <1>;
187 + ranges = <0xef600000 0xef600000 0x00a00000>;
188 + dcr-reg = <0x0a0 0x005>;
189 + clock-frequency = <0>; /* Filled in by zImage */
191 + UART0: serial@ef600300 {
192 + device_type = "serial";
193 + compatible = "ns16550";
194 + reg = <0xef600300 0x00000008>;
195 + virtual-reg = <0xef600300>;
196 + clock-frequency = <0>; /* Filled in by zImage */
197 + current-speed = <115200>;
198 + interrupt-parent = <&UIC0>;
199 + interrupts = <0x0 0x4>;
202 + UART1: serial@ef600400 {
203 + device_type = "serial";
204 + compatible = "ns16550";
205 + reg = <0xef600400 0x00000008>;
206 + virtual-reg = <0xef600400>;
207 + clock-frequency = <0>; /* Filled in by zImage */
208 + current-speed = <115200>;
209 + interrupt-parent = <&UIC0>;
210 + interrupts = <0x1 0x4>;
213 + IIC: i2c@ef600500 {
214 + #address-cells = <1>;
216 + compatible = "ibm,iic-405ep", "ibm,iic";
217 + reg = <0xef600500 0x00000011>;
218 + interrupt-parent = <&UIC0>;
219 + interrupts = <0x2 0x4>;
222 + compatible = "at24,24c16";
227 + GPIO0: gpio-controller@ef600700 {
228 + compatible = "ibm,ppc4xx-gpio";
229 + reg = <0xef600700 0x00000020>;
234 + EMAC0: ethernet@ef600800 {
235 + linux,network-index = <0x0>;
236 + device_type = "network";
237 + compatible = "ibm,emac-405ep", "ibm,emac";
238 + interrupt-parent = <&UIC0>;
240 + 0xf 0x4 /* Ethernet */
241 + 0x9 0x4 /* Ethernet Wake Up */>;
242 + local-mac-address = [000000000000]; /* Filled in by zImage */
243 + reg = <0xef600800 0x00000070>;
244 + mal-device = <&MAL>;
245 + mal-tx-channel = <0>;
246 + mal-rx-channel = <0>;
248 + max-frame-size = <0x5dc>;
249 + rx-fifo-size = <0x1000>;
250 + tx-fifo-size = <0x800>;
252 + phy-map = <0x00000000>;
256 + compatible = "gpio-leds";
258 + label = "openrb:green:user";
259 + gpios = <&GPIO0 2 1>;
265 + compatible = "ibm,ebc-405ep", "ibm,ebc";
266 + dcr-reg = <0x012 0x002>;
267 + #address-cells = <2>;
269 + /* The ranges property is supplied by the bootwrapper
270 + * and is based on the firmware's configuration of the
273 + clock-frequency = <0>; /* Filled in by zImage */
275 + nor_flash@ff800000 {
276 + compatible = "cfi-flash";
278 + reg = <0x00000000 0xff800000 0x00800000>;
279 + #address-cells = <1>;
283 + reg = <0x0 0x120000>;
287 + reg = <0x120000 0x6a0000>;
291 + reg = <0x7c0000 0x30000>;
297 + PCI0: pci@ec000000 {
298 + device_type = "pci";
299 + #interrupt-cells = <1>;
301 + #address-cells = <3>;
302 + compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
304 + reg = <0xeec00000 0x00000008 /* Config space access */
305 + 0xeed80000 0x00000004 /* IACK */
306 + 0xeed80000 0x00000004 /* Special cycle */
307 + 0xef480000 0x00000040>; /* Internal registers */
309 + /* Outbound ranges, one memory and one IO,
310 + * later cannot be changed. Chip supports a second
311 + * IO range but we don't use it for now
313 + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
314 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
316 + /* Inbound 2GB range starting at 0 */
317 + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
319 + interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
322 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
325 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
328 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
331 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
337 + linux,stdout-path = "/plb/opb/serial@ef600300";