2 +++ b/arch/powerpc/boot/cuboot-openrb.c
5 + * Old U-boot compatibility for OpenRB boards
7 + * Author: Gabor Juhos <juhosg@openwrt.org>
8 + * Imre Kaloz <kaloz@openwrt.org>
10 + * This program is free software; you can redistribute it and/or modify it
11 + * under the terms of the GNU General Public License version 2 as published
12 + * by the Free Software Foundation.
29 +static void fixup_perwe(void)
31 +#define DCRN_CPC0_PCI_BASE 0xf9
33 + /* Turn on PerWE instead of PCIINT */
34 + mtdcr(DCRN_CPC0_PCI_BASE,
35 + mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
37 +#undef DCRN_CPC0_PCI_BASE
40 +static void fixup_cf_card(void)
42 +#define CF_CS0_BASE 0xff100000
43 +#define CF_CS1_BASE 0xff200000
45 + /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
46 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B1CR);
47 + mtdcr(DCRN_EBC0_CFGDATA, CF_CS0_BASE | EBC_BXCR_BS_1M |
48 + EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
49 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B1AP);
50 + mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
52 + /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
53 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B2CR);
54 + mtdcr(DCRN_EBC0_CFGDATA, CF_CS1_BASE | EBC_BXCR_BS_1M |
55 + EBC_BXCR_BU_RW | EBC_BXCR_BW_16);
56 + mtdcr(DCRN_EBC0_CFGADDR, EBC_B2AP);
57 + mtdcr(DCRN_EBC0_CFGDATA, 0x080bd800);
63 +static void openrb_fixups(void)
65 + ibm405ep_fixup_clocks(bd.bi_procfreq / 8);
66 + ibm4xx_sdram_fixup_memsize();
71 + dt_fixup_mac_addresses(&bd.bi_enetaddr, &bd.bi_enet1addr);
74 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
75 + unsigned long r6, unsigned long r7)
78 + platform_ops.fixups = openrb_fixups;
79 + platform_ops.exit = ibm40x_dbcr_reset;
80 + fdt_init(_dtb_start);
81 + serial_console_init();
84 +++ b/arch/powerpc/boot/dts/openrb.dts
87 + * Device Tree Source for OpenRB boards
89 + * Copyright 2009 Gabor Juhos <juhosg@openwrt.org>
90 + * Copyright 2009 Imre Kaloz <kaloz@openwrt.org>
92 + * Based on walnut.dts
94 + * This file is licensed under the terms of the GNU General Public
95 + * License version 2. This program is licensed "as is" without
96 + * any warranty of any kind, whether express or implied.
102 + #address-cells = <1>;
105 + compatible = "openrb";
106 + dcr-parent = <&{/cpus/cpu@0}>;
109 + ethernet0 = &EMAC0;
110 + ethernet1 = &EMAC1;
116 + #address-cells = <1>;
120 + device_type = "cpu";
121 + model = "PowerPC,405EP";
122 + reg = <0x00000000>;
123 + clock-frequency = <0>; /* Filled in by zImage */
124 + timebase-frequency = <0>; /* Filled in by zImage */
125 + i-cache-line-size = <0x20>;
126 + d-cache-line-size = <0x20>;
127 + i-cache-size = <0x4000>;
128 + d-cache-size = <0x4000>;
130 + dcr-access-method = "native";
135 + device_type = "memory";
136 + reg = <0x00000000 0x00000000>; /* Filled in by zImage */
139 + UIC0: interrupt-controller {
140 + compatible = "ibm,uic";
141 + interrupt-controller;
143 + dcr-reg = <0x0c0 0x009>;
144 + #address-cells = <0>;
146 + #interrupt-cells = <2>;
150 + compatible = "ibm,plb3";
151 + #address-cells = <1>;
154 + clock-frequency = <0>; /* Filled in by zImage */
156 + SDRAM0: memory-controller {
157 + compatible = "ibm,sdram-405ep";
158 + dcr-reg = <0x010 0x002>;
162 + compatible = "ibm,mcmal-405ep", "ibm,mcmal";
163 + dcr-reg = <0x180 0x062>;
164 + num-tx-chans = <4>;
165 + num-rx-chans = <2>;
166 + interrupt-parent = <&UIC0>;
168 + 0xb 0x4 /* TXEOB */
169 + 0xc 0x4 /* RXEOB */
172 + 0xe 0x4 /* RXDE */>;
176 + compatible = "ibm,opb-405ep", "ibm,opb";
177 + #address-cells = <1>;
179 + ranges = <0xef600000 0xef600000 0x00a00000>;
180 + dcr-reg = <0x0a0 0x005>;
181 + clock-frequency = <0>; /* Filled in by zImage */
183 + UART0: serial@ef600300 {
184 + device_type = "serial";
185 + compatible = "ns16550";
186 + reg = <0xef600300 0x00000008>;
187 + virtual-reg = <0xef600300>;
188 + clock-frequency = <0>; /* Filled in by zImage */
189 + current-speed = <115200>;
190 + interrupt-parent = <&UIC0>;
191 + interrupts = <0x0 0x4>;
194 + UART1: serial@ef600400 {
195 + device_type = "serial";
196 + compatible = "ns16550";
197 + reg = <0xef600400 0x00000008>;
198 + virtual-reg = <0xef600400>;
199 + clock-frequency = <0>; /* Filled in by zImage */
200 + current-speed = <115200>;
201 + interrupt-parent = <&UIC0>;
202 + interrupts = <0x1 0x4>;
205 + IIC: i2c@ef600500 {
206 + compatible = "ibm,iic-405ep", "ibm,iic";
207 + #address-cells = <1>;
209 + reg = <0xef600500 0x00000011>;
210 + interrupt-parent = <&UIC0>;
211 + interrupts = <0x2 0x4>;
214 + compatible = "at24,24c16";
219 + GPIO0: gpio-controller@ef600700 {
220 + compatible = "ibm,ppc4xx-gpio";
221 + reg = <0xef600700 0x00000020>;
226 + EMAC0: ethernet@ef600800 {
227 + linux,network-index = <0x0>;
228 + device_type = "network";
229 + compatible = "ibm,emac-405ep", "ibm,emac";
230 + interrupt-parent = <&UIC0>;
232 + 0xf 0x4 /* Ethernet */
233 + 0x9 0x4 /* Ethernet Wake Up */>;
234 + local-mac-address = [000000000000]; /* Filled in by zImage */
235 + reg = <0xef600800 0x00000070>;
236 + mal-device = <&MAL>;
237 + mal-tx-channel = <0>;
238 + mal-rx-channel = <0>;
240 + max-frame-size = <0x5dc>;
241 + rx-fifo-size = <0x1000>;
242 + tx-fifo-size = <0x800>;
244 + phy-map = <0x00000000>;
247 + EMAC1: ethernet@ef600900 {
248 + linux,network-index = <0x1>;
249 + device_type = "network";
250 + compatible = "ibm,emac-405ep", "ibm,emac";
251 + interrupt-parent = <&UIC0>;
253 + 0x11 0x4 /* Ethernet */
254 + 0x09 0x4 /* Ethernet Wake Up */>;
255 + local-mac-address = [000000000000]; /* Filled in by zImage */
256 + reg = <0xef600900 0x00000070>;
257 + mal-device = <&MAL>;
258 + mal-tx-channel = <2>;
259 + mal-rx-channel = <1>;
261 + max-frame-size = <0x5dc>;
262 + rx-fifo-size = <0x1000>;
263 + tx-fifo-size = <0x800>;
264 + mdio-device = <&EMAC0>;
266 + phy-map = <0x00000001>;
270 + compatible = "gpio-leds";
272 + label = "openrb:green:user";
273 + gpios = <&GPIO0 2 1>;
279 + compatible = "ibm,ebc-405ep", "ibm,ebc";
280 + dcr-reg = <0x012 0x002>;
281 + #address-cells = <2>;
283 + /* The ranges property is supplied by the bootwrapper
284 + * and is based on the firmware's configuration of the
287 + clock-frequency = <0>; /* Filled in by zImage */
290 + compatible = "magicbox-cf", "pata-magicbox-cf";
291 + reg = <0x00000000 0xff100000 0x00001000
292 + 0x00000000 0xff200000 0x00001000>;
293 + interrupt-parent = <&UIC0>;
294 + interrupts = <0x19 0x1 /* IRQ_TYPE_EDGE_RISING */ >;
297 + nor_flash@ff800000 {
298 + compatible = "cfi-flash";
300 + reg = <0x00000000 0xff800000 0x00800000>;
301 + #address-cells = <1>;
305 + reg = <0x0 0x140000>;
307 + partition1@120000 {
309 + reg = <0x140000 0x680000>;
311 + partition2@7c0000 {
313 + reg = <0x7c0000 0x30000>;
317 + label = "firmware";
318 + reg = <0x0 0x7c0000>;
323 + PCI0: pci@ec000000 {
324 + device_type = "pci";
325 + #interrupt-cells = <1>;
327 + #address-cells = <3>;
328 + compatible = "ibm,plb405ep-pci", "ibm,plb-pci";
330 + reg = <0xeec00000 0x00000008 /* Config space access */
331 + 0xeed80000 0x00000004 /* IACK */
332 + 0xeed80000 0x00000004 /* Special cycle */
333 + 0xef480000 0x00000040>; /* Internal registers */
335 + /* Outbound ranges, one memory and one IO,
336 + * later cannot be changed. Chip supports a second
337 + * IO range but we don't use it for now
339 + ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x20000000
340 + 0x01000000 0x00000000 0x00000000 0xe8000000 0x00000000 0x00010000>;
342 + /* Inbound 2GB range starting at 0 */
343 + dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
345 + interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
348 + 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
351 + 0x1000 0x0 0x0 0x0 &UIC0 0x1d 0x8
354 + 0x1800 0x0 0x0 0x0 &UIC0 0x1e 0x8
357 + 0x2000 0x0 0x0 0x0 &UIC0 0x1f 0x8
363 + linux,stdout-path = "/plb/opb/serial@ef600300";
366 --- a/arch/powerpc/boot/Makefile
367 +++ b/arch/powerpc/boot/Makefile
368 @@ -44,6 +44,7 @@ $(obj)/cuboot-taishan.o: BOOTCFLAGS += -
369 $(obj)/cuboot-katmai.o: BOOTCFLAGS += -mcpu=440
370 $(obj)/cuboot-acadia.o: BOOTCFLAGS += -mcpu=405
371 $(obj)/cuboot-magicbox.o: BOOTCFLAGS += -mcpu=405
372 +$(obj)/cuboot-openrb.o: BOOTCFLAGS += -mcpu=405
373 $(obj)/treeboot-walnut.o: BOOTCFLAGS += -mcpu=405
374 $(obj)/virtex405-head.o: BOOTAFLAGS += -mcpu=405
376 @@ -78,7 +79,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
377 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
378 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
379 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
381 + cuboot-magicbox.c cuboot-openrb.c
382 src-boot := $(src-wlib) $(src-plat) empty.c
384 src-boot := $(addprefix $(obj)/, $(src-boot))
385 @@ -197,6 +198,7 @@ image-$(CONFIG_HOTFOOT) += cuImage.hot
386 image-$(CONFIG_WALNUT) += treeImage.walnut
387 image-$(CONFIG_ACADIA) += cuImage.acadia
388 image-$(CONFIG_MAGICBOX) += cuImage.magicbox
389 +image-$(CONFIG_OPENRB) += cuImage.openrb
391 # Board ports in arch/powerpc/platform/44x/Kconfig
392 image-$(CONFIG_EBONY) += treeImage.ebony cuImage.ebony
393 --- a/arch/powerpc/platforms/40x/Kconfig
394 +++ b/arch/powerpc/platforms/40x/Kconfig
395 @@ -70,6 +70,16 @@ config MAGICBOX
397 This option enables support for the Magicbox boards.
403 + select PPC40x_SIMPLE
407 + This option enables support for the OpenRB boards.
412 --- a/arch/powerpc/platforms/40x/ppc40x_simple.c
413 +++ b/arch/powerpc/platforms/40x/ppc40x_simple.c
414 @@ -56,7 +56,8 @@ static char *board[] __initdata = {
423 static int __init ppc40x_probe(void)