1 From cd2a6af51553d38072cd31699b58d16ca6176ef5 Mon Sep 17 00:00:00 2001
2 From: Ionela Voinescu <ionela.voinescu@imgtec.com>
3 Date: Thu, 2 Feb 2017 16:46:14 +0000
4 Subject: spi: img-spfi: Implement dual and quad mode
6 For dual and quad modes to work the SPFI controller needs
7 to have information about command/address/dummy bytes in the
8 transaction register. This information is not relevant for
9 single mode, and therefore it can have any value in the
10 allowed range. Therefore, for any read or write transfers of less
11 than 8 bytes (cmd = 1 byte, addr up to 7 bytes), SPFI will be
12 configured, but not enabled (unless it is the last transfer in
13 the queue). The transfer will be enabled by the subsequent tranfer.
14 A pending transfer is determined by the content of the transaction
15 register: if command part is set and tsize is not.
17 This way we ensure that for dual and quad transactions
18 the command request size will apear in the command/address part
19 of the transaction register, while the data size will be in
20 tsize, all data being sent/received in the same transaction (as
21 set up in the transaction register).
23 Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
24 Signed-off-by: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
26 drivers/spi/spi-img-spfi.c | 96 ++++++++++++++++++++++++++++++++++++++++------
27 1 file changed, 85 insertions(+), 11 deletions(-)
29 diff --git a/drivers/spi/spi-img-spfi.c b/drivers/spi/spi-img-spfi.c
30 index 7a37090..c845a50 100644
31 --- a/drivers/spi/spi-img-spfi.c
32 +++ b/drivers/spi/spi-img-spfi.c
34 #define SPFI_CONTROL_SOFT_RESET BIT(11)
35 #define SPFI_CONTROL_SEND_DMA BIT(10)
36 #define SPFI_CONTROL_GET_DMA BIT(9)
37 -#define SPFI_CONTROL_SE BIT(8)
38 +#define SPFI_CONTROL_SE BIT(8)
39 +#define SPFI_CONTROL_TX_RX BIT(1)
40 #define SPFI_CONTROL_TMODE_SHIFT 5
41 #define SPFI_CONTROL_TMODE_MASK 0x7
42 #define SPFI_CONTROL_TMODE_SINGLE 0
44 #define SPFI_TRANSACTION 0x18
45 #define SPFI_TRANSACTION_TSIZE_SHIFT 16
46 #define SPFI_TRANSACTION_TSIZE_MASK 0xffff
47 +#define SPFI_TRANSACTION_CMD_SHIFT 13
48 +#define SPFI_TRANSACTION_CMD_MASK 0x7
49 +#define SPFI_TRANSACTION_ADDR_SHIFT 10
50 +#define SPFI_TRANSACTION_ADDR_MASK 0x7
52 #define SPFI_PORT_STATE 0x1c
53 #define SPFI_PORT_STATE_DEV_SEL_SHIFT 20
56 #define SPFI_32BIT_FIFO_SIZE 64
57 #define SPFI_8BIT_FIFO_SIZE 16
58 +#define SPFI_DATA_REQUEST_MAX_SIZE 8
62 @@ -103,6 +109,8 @@ struct img_spfi {
63 struct dma_chan *tx_ch;
70 struct img_spfi_device_data {
71 @@ -123,9 +131,11 @@ static inline void spfi_start(struct img_spfi *spfi)
75 - val = spfi_readl(spfi, SPFI_CONTROL);
76 - val |= SPFI_CONTROL_SPFI_EN;
77 - spfi_writel(spfi, val, SPFI_CONTROL);
78 + if (spfi->complete) {
79 + val = spfi_readl(spfi, SPFI_CONTROL);
80 + val |= SPFI_CONTROL_SPFI_EN;
81 + spfi_writel(spfi, val, SPFI_CONTROL);
85 static inline void spfi_reset(struct img_spfi *spfi)
86 @@ -138,12 +148,21 @@ static int spfi_wait_all_done(struct img_spfi *spfi)
88 unsigned long timeout = jiffies + msecs_to_jiffies(50);
90 + if (!(spfi->complete))
93 while (time_before(jiffies, timeout)) {
94 u32 status = spfi_readl(spfi, SPFI_INTERRUPT_STATUS);
96 if (status & SPFI_INTERRUPT_ALLDONETRIG) {
97 spfi_writel(spfi, SPFI_INTERRUPT_ALLDONETRIG,
98 SPFI_INTERRUPT_CLEAR);
100 + * Disable SPFI for it not to interfere with
101 + * pending transactions
103 + spfi_writel(spfi, spfi_readl(spfi, SPFI_CONTROL)
104 + & ~SPFI_CONTROL_SPFI_EN, SPFI_CONTROL);
108 @@ -494,9 +513,32 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
109 struct spi_transfer *xfer)
111 struct img_spfi *spfi = spi_master_get_devdata(spi->master);
113 + u32 val, div, transact;
117 + * For read or write transfers of less than 8 bytes (cmd = 1 byte,
118 + * addr up to 7 bytes), SPFI will be configured, but not enabled
119 + * (unless it is the last transfer in the queue).The transfer will
120 + * be enabled by the subsequent transfer.
121 + * A pending transfer is determined by the content of the
122 + * transaction register: if command part is set and tsize
125 + transact = spfi_readl(spfi, SPFI_TRANSACTION);
126 + is_pending = ((transact >> SPFI_TRANSACTION_CMD_SHIFT) &
127 + SPFI_TRANSACTION_CMD_MASK) &&
128 + (!((transact >> SPFI_TRANSACTION_TSIZE_SHIFT) &
129 + SPFI_TRANSACTION_TSIZE_MASK));
131 + /* If there are no pending transactions it's OK to soft reset */
133 + /* Start the transaction from a known (reset) state */
138 + * Before anything else, set up parameters.
139 * output = spfi_clk * (BITCLK / 512), where BITCLK must be a
140 * power of 2 up to 128
142 @@ -509,20 +551,52 @@ static void img_spfi_config(struct spi_master *master, struct spi_device *spi,
143 val |= div << SPFI_DEVICE_PARAMETER_BITCLK_SHIFT;
144 spfi_writel(spfi, val, SPFI_DEVICE_PARAMETER(spi->chip_select));
146 - spfi_writel(spfi, xfer->len << SPFI_TRANSACTION_TSIZE_SHIFT,
148 + if (!list_is_last(&xfer->transfer_list, &master->cur_msg->transfers) &&
150 + * For duplex mode (both the tx and rx buffers are !NULL) the
151 + * CMD, ADDR, and DUMMY byte parts of the transaction register
152 + * should always be 0 and therefore the pending transfer
153 + * technique cannot be used.
155 + (xfer->tx_buf) && (!xfer->rx_buf) &&
156 + (xfer->len <= SPFI_DATA_REQUEST_MAX_SIZE) && !is_pending) {
157 + transact = (1 & SPFI_TRANSACTION_CMD_MASK) <<
158 + SPFI_TRANSACTION_CMD_SHIFT;
159 + transact |= ((xfer->len - 1) & SPFI_TRANSACTION_ADDR_MASK) <<
160 + SPFI_TRANSACTION_ADDR_SHIFT;
161 + spfi->complete = false;
163 + spfi->complete = true;
165 + /* Keep setup from pending transfer */
166 + transact |= ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) <<
167 + SPFI_TRANSACTION_TSIZE_SHIFT);
169 + transact = ((xfer->len & SPFI_TRANSACTION_TSIZE_MASK) <<
170 + SPFI_TRANSACTION_TSIZE_SHIFT);
173 + spfi_writel(spfi, transact, SPFI_TRANSACTION);
175 val = spfi_readl(spfi, SPFI_CONTROL);
176 val &= ~(SPFI_CONTROL_SEND_DMA | SPFI_CONTROL_GET_DMA);
179 + * We set up send DMA for pending transfers also, as
180 + * those are always send transfers
182 + if ((xfer->tx_buf) || is_pending)
183 val |= SPFI_CONTROL_SEND_DMA;
186 + val |= SPFI_CONTROL_TX_RX;
187 + if (xfer->rx_buf) {
188 val |= SPFI_CONTROL_GET_DMA;
189 + val &= ~SPFI_CONTROL_TX_RX;
191 val &= ~(SPFI_CONTROL_TMODE_MASK << SPFI_CONTROL_TMODE_SHIFT);
192 - if (xfer->tx_nbits == SPI_NBITS_DUAL &&
193 + if (xfer->tx_nbits == SPI_NBITS_DUAL ||
194 xfer->rx_nbits == SPI_NBITS_DUAL)
195 val |= SPFI_CONTROL_TMODE_DUAL << SPFI_CONTROL_TMODE_SHIFT;
196 - else if (xfer->tx_nbits == SPI_NBITS_QUAD &&
197 + else if (xfer->tx_nbits == SPI_NBITS_QUAD ||
198 xfer->rx_nbits == SPI_NBITS_QUAD)
199 val |= SPFI_CONTROL_TMODE_QUAD << SPFI_CONTROL_TMODE_SHIFT;
200 val |= SPFI_CONTROL_SE;