1 --- a/drivers/pci/host/Kconfig
2 +++ b/drivers/pci/host/Kconfig
3 @@ -220,4 +220,9 @@ config VMD
4 To compile this driver as a module, choose M here: the
5 module will be called vmd.
8 + bool "PLX Oxnas PCIe controller"
9 + depends on ARCH_OXNAS
13 --- a/drivers/pci/host/Makefile
14 +++ b/drivers/pci/host/Makefile
15 @@ -20,6 +20,7 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera
16 obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
17 obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
18 obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
19 +obj-$(CONFIG_PCIE_OXNAS) += pcie-oxnas.o
20 obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
21 obj-$(CONFIG_VMD) += vmd.o
23 --- a/arch/arm/boot/dts/ox820.dtsi
24 +++ b/arch/arm/boot/dts/ox820.dtsi
26 reg = <0x1000 0x1000>,
30 + pcie0: pcie-controller@c00000 {
31 + compatible = "plxtech,nas782x-pcie";
32 + device_type = "pci";
33 + #address-cells = <3>;
36 + /* flag & space bus address host address size */
37 + ranges = < 0x82000000 0 0x48000000 0x48000000 0 0x2000000
38 + 0xC2000000 0 0x4A000000 0x4A000000 0 0x1E00000
39 + 0x81000000 0 0x4BE00000 0x4BE00000 0 0x0100000
40 + 0x80000000 0 0x4BF00000 0x4BF00000 0 0x0100000>;
42 + bus-range = <0x00 0x7f>;
44 + /* cfg inbound translator phy*/
45 + reg = <0x47C00000 0x1000>, <0x47D00000 0x100>, <0x44A00000 0x10>;
47 + #interrupt-cells = <1>;
48 + /* wild card mask, match all bus address & interrupt specifier */
49 + /* format: bus address mask, interrupt specifier mask */
50 + /* each bit 1 means need match, 0 means ignored when match */
51 + interrupt-map-mask = <0 0 0 0>;
52 + /* format: a list of: bus address, interrupt specifier,
53 + * parent interrupt controller & specifier */
54 + interrupt-map = <0 0 0 0 &gic 0 19 0x304>;
56 + gpios = <&gpio1 12 0>;
57 + clocks = <&stdclk CLK_820_PCIEA>, <&pllb>;
58 + clock-names = "pcie", "busclk";
59 + resets = <&reset RESET_PCIEA>, <&reset RESET_PCIEPHY>;
60 + reset-names = "pcie", "phy";
62 + plxtech,pcie-hcsl-bit = <2>;
63 + plxtech,pcie-ctrl-offset = <0x120>;
64 + plxtech,pcie-outbound-offset = <0x138>;
65 + status = "disabled";
68 + pcie1: pcie-controller@e00000 {
69 + compatible = "plxtech,nas782x-pcie";
70 + device_type = "pci";
71 + #address-cells = <3>;
74 + /* flag & space bus address host address size */
75 + ranges = < 0x82000000 0 0x4C000000 0x4C000000 0 0x2000000
76 + 0xC2000000 0 0x4E000000 0x4E000000 0 0x1E00000
77 + 0x81000000 0 0x4FE00000 0x4FE00000 0 0x0100000
78 + 0x80000000 0 0x4FF00000 0x4FF00000 0 0x0100000>;
80 + bus-range = <0x80 0xff>;
82 + /* cfg inbound translator phy*/
83 + reg = <0x47E00000 0x1000>, <0x47F00000 0x100>, <0x44A00000 0x10>;
85 + #interrupt-cells = <1>;
86 + /* wild card mask, match all bus address & interrupt specifier */
87 + /* format: bus address mask, interrupt specifier mask */
88 + /* each bit 1 means need match, 0 means ignored when match */
89 + interrupt-map-mask = <0 0 0 0>;
90 + /* format: a list of: bus address, interrupt specifier,
91 + * parent interrupt controller & specifier */
92 + interrupt-map = <0 0 0 0 &gic 0 20 0x304>;
94 + /* gpios = <&gpio1 12 0>; */
95 + clocks = <&stdclk CLK_820_PCIEB>, <&pllb>;
96 + clock-names = "pcie", "busclk";
97 + resets = <&reset RESET_PCIEB>, <&reset RESET_PCIEPHY>;
98 + reset-names = "pcie", "phy";
100 + plxtech,pcie-hcsl-bit = <3>;
101 + plxtech,pcie-ctrl-offset = <0x124>;
102 + plxtech,pcie-outbound-offset = <0x174>;
103 + status = "disabled";