target/linux/oxnas/files/drivers/power/reset/oxnas-restart.c

   1 // SPDX-License-Identifier: (GPL-2.0)
   2 /*
   3  * oxnas SoC reset driver
   4  * based on:
   5  * Microsemi MIPS SoC reset driver
   6  * and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
   7  *
   8  * License: GPL
   9  * Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
  10  * Copyright (c) 2017 Microsemi Corporation
  11  * Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
  12  */
  13 #include <linux/delay.h>
  14 #include <linux/io.h>
  15 #include <linux/notifier.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/of_address.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/reboot.h>
  21 #include <linux/regmap.h>
  22 #include <dt-bindings/reset/oxsemi,ox820.h>
  23
  24 /* bit numbers of clock control register */
  25 #define SYS_CTRL_CLK_COPRO              0
  26 #define SYS_CTRL_CLK_DMA                1
  27 #define SYS_CTRL_CLK_CIPHER             2
  28 #define SYS_CTRL_CLK_SD                 3
  29 #define SYS_CTRL_CLK_SATA               4
  30 #define SYS_CTRL_CLK_I2S                5
  31 #define SYS_CTRL_CLK_USBHS              6
  32 #define SYS_CTRL_CLK_MACA               7
  33 #define SYS_CTRL_CLK_MAC                SYS_CTRL_CLK_MACA
  34 #define SYS_CTRL_CLK_PCIEA              8
  35 #define SYS_CTRL_CLK_STATIC             9
  36 #define SYS_CTRL_CLK_MACB               10
  37 #define SYS_CTRL_CLK_PCIEB              11
  38 #define SYS_CTRL_CLK_REF600             12
  39 #define SYS_CTRL_CLK_USBDEV             13
  40 #define SYS_CTRL_CLK_DDR                14
  41 #define SYS_CTRL_CLK_DDRPHY             15
  42 #define SYS_CTRL_CLK_DDRCK              16
  43
  44 /* Regmap offsets */
  45 #define CLK_SET_REGOFFSET               0x2c
  46 #define CLK_CLR_REGOFFSET               0x30
  47 #define RST_SET_REGOFFSET               0x34
  48 #define RST_CLR_REGOFFSET               0x38
  49 #define SECONDARY_SEL_REGOFFSET         0x14
  50 #define TERTIARY_SEL_REGOFFSET          0x8c
  51 #define QUATERNARY_SEL_REGOFFSET        0x94
  52 #define DEBUG_SEL_REGOFFSET             0x9c
  53 #define ALTERNATIVE_SEL_REGOFFSET       0xa4
  54 #define PULLUP_SEL_REGOFFSET            0xac
  55 #define SEC_SECONDARY_SEL_REGOFFSET     0x100014
  56 #define SEC_TERTIARY_SEL_REGOFFSET      0x10008c
  57 #define SEC_QUATERNARY_SEL_REGOFFSET    0x100094
  58 #define SEC_DEBUG_SEL_REGOFFSET         0x10009c
  59 #define SEC_ALTERNATIVE_SEL_REGOFFSET   0x1000a4
  60 #define SEC_PULLUP_SEL_REGOFFSET        0x1000ac
  61
  62
  63 struct oxnas_restart_context {
  64         struct regmap *sys_ctrl;
  65         struct notifier_block restart_handler;
  66 };
  67
  68 static int oxnas_restart_handle(struct notifier_block *this,
  69                                  unsigned long mode, void *cmd)
  70 {
  71         struct oxnas_restart_context *ctx = container_of(this, struct
  72                                                         oxnas_restart_context,
  73                                                         restart_handler);
  74         u32 value;
  75
  76         /* Assert reset to cores as per power on defaults
  77          * Don't touch the DDR interface as things will come to an impromptu stop
  78          * NB Possibly should be asserting reset for PLLB, but there are timing
  79          *    concerns here according to the docs */
  80         value = BIT(RESET_LEON)         |
  81                 BIT(RESET_USBHS)        |
  82                 BIT(RESET_USBPHYA)      |
  83                 BIT(RESET_MAC)          |
  84                 BIT(RESET_PCIEA)        |
  85                 BIT(RESET_SGDMA)        |
  86                 BIT(RESET_CIPHER)       |
  87                 BIT(RESET_SATA)         |
  88                 BIT(RESET_SATA_LINK)    |
  89                 BIT(RESET_SATA_PHY)     |
  90                 BIT(RESET_PCIEPHY)      |
  91                 BIT(RESET_NAND)         |
  92                 BIT(RESET_UART1)        |
  93                 BIT(RESET_UART2)        |
  94                 BIT(RESET_MISC)         |
  95                 BIT(RESET_I2S)          |
  96                 BIT(RESET_SD)           |
  97                 BIT(RESET_MAC_2)        |
  98                 BIT(RESET_PCIEB)        |
  99                 BIT(RESET_VIDEO)        |
 100                 BIT(RESET_USBPHYB)      |
 101                 BIT(RESET_USBDEV);
 102
 103         regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
 104
 105         /* Release reset to cores as per power on defaults */
 106         regmap_write(ctx->sys_ctrl, RST_CLR_REGOFFSET, BIT(RESET_GPIO));
 107
 108         /* Disable clocks to cores as per power-on defaults - must leave DDR
 109          * related clocks enabled otherwise we'll stop rather abruptly. */
 110         value =
 111                 BIT(SYS_CTRL_CLK_COPRO)         |
 112                 BIT(SYS_CTRL_CLK_DMA)           |
 113                 BIT(SYS_CTRL_CLK_CIPHER)        |
 114                 BIT(SYS_CTRL_CLK_SD)            |
 115                 BIT(SYS_CTRL_CLK_SATA)          |
 116                 BIT(SYS_CTRL_CLK_I2S)           |
 117                 BIT(SYS_CTRL_CLK_USBHS)         |
 118                 BIT(SYS_CTRL_CLK_MAC)           |
 119                 BIT(SYS_CTRL_CLK_PCIEA)         |
 120                 BIT(SYS_CTRL_CLK_STATIC)        |
 121                 BIT(SYS_CTRL_CLK_MACB)          |
 122                 BIT(SYS_CTRL_CLK_PCIEB)         |
 123                 BIT(SYS_CTRL_CLK_REF600)        |
 124                 BIT(SYS_CTRL_CLK_USBDEV);
 125
 126         regmap_write(ctx->sys_ctrl, CLK_CLR_REGOFFSET, value);
 127
 128         /* Enable clocks to cores as per power-on defaults */
 129
 130         /* Set sys-control pin mux'ing as per power-on defaults */
 131         regmap_write(ctx->sys_ctrl, SECONDARY_SEL_REGOFFSET, 0);
 132         regmap_write(ctx->sys_ctrl, TERTIARY_SEL_REGOFFSET, 0);
 133         regmap_write(ctx->sys_ctrl, QUATERNARY_SEL_REGOFFSET, 0);
 134         regmap_write(ctx->sys_ctrl, DEBUG_SEL_REGOFFSET, 0);
 135         regmap_write(ctx->sys_ctrl, ALTERNATIVE_SEL_REGOFFSET, 0);
 136         regmap_write(ctx->sys_ctrl, PULLUP_SEL_REGOFFSET, 0);
 137
 138         regmap_write(ctx->sys_ctrl, SEC_SECONDARY_SEL_REGOFFSET, 0);
 139         regmap_write(ctx->sys_ctrl, SEC_TERTIARY_SEL_REGOFFSET, 0);
 140         regmap_write(ctx->sys_ctrl, SEC_QUATERNARY_SEL_REGOFFSET, 0);
 141         regmap_write(ctx->sys_ctrl, SEC_DEBUG_SEL_REGOFFSET, 0);
 142         regmap_write(ctx->sys_ctrl, SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
 143         regmap_write(ctx->sys_ctrl, SEC_PULLUP_SEL_REGOFFSET, 0);
 144
 145         /* No need to save any state, as the ROM loader can determine whether
 146          * reset is due to power cycling or programatic action, just hit the
 147          * (self-clearing) CPU reset bit of the block reset register */
 148         value =
 149                 BIT(RESET_SCU) |
 150                 BIT(RESET_ARM0) |
 151                 BIT(RESET_ARM1);
 152
 153         regmap_write(ctx->sys_ctrl, RST_SET_REGOFFSET, value);
 154
 155         pr_emerg("Unable to restart system\n");
 156         return NOTIFY_DONE;
 157 }
 158
 159 static int oxnas_restart_probe(struct platform_device *pdev)
 160 {
 161         struct oxnas_restart_context *ctx;
 162         struct regmap *sys_ctrl;
 163         struct device *dev = &pdev->dev;
 164         int err = 0;
 165
 166         sys_ctrl = syscon_regmap_lookup_by_compatible("oxsemi,ox820-sys-ctrl");
 167         if (IS_ERR(sys_ctrl))
 168                 return PTR_ERR(sys_ctrl);
 169
 170         ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
 171         if (!ctx)
 172                 return -ENOMEM;
 173
 174         ctx->sys_ctrl = sys_ctrl;
 175         ctx->restart_handler.notifier_call = oxnas_restart_handle;
 176         ctx->restart_handler.priority = 192;
 177         err = register_restart_handler(&ctx->restart_handler);
 178         if (err)
 179                 dev_err(dev, "can't register restart notifier (err=%d)\n", err);
 180
 181         return err;
 182 }
 183
 184 static const struct of_device_id oxnas_restart_of_match[] = {
 185         { .compatible = "oxsemi,ox820-sys-ctrl" },
 186         {}
 187 };
 188
 189 static struct platform_driver oxnas_restart_driver = {
 190         .probe = oxnas_restart_probe,
 191         .driver = {
 192                 .name = "oxnas-chip-reset",
 193                 .of_match_table = oxnas_restart_of_match,
 194         },
 195 };
 196 builtin_platform_driver(oxnas_restart_driver);