2 * PCIe driver for PLX NAS782X SoCs
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/module.h>
13 #include <linux/mbus.h>
14 #include <linux/slab.h>
15 #include <linux/platform_device.h>
16 #include <linux/of_address.h>
17 #include <linux/of_pci.h>
18 #include <linux/of_irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/of_gpio.h>
21 #include <linux/gpio.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <linux/reset.h>
26 #include <linux/sizes.h>
28 #define OXNAS_UART1_BASE 0x44200000
29 #define OXNAS_UART1_SIZE SZ_32
30 #define OXNAS_UART1_BASE_VA 0xF0000000
32 #define OXNAS_UART2_BASE 0x44300000
33 #define OXNAS_UART2_SIZE SZ_32
35 #define OXNAS_PERCPU_BASE 0x47000000
36 #define OXNAS_PERCPU_SIZE SZ_8K
37 #define OXNAS_PERCPU_BASE_VA 0xF0002000
39 #define OXNAS_SYSCRTL_BASE 0x44E00000
40 #define OXNAS_SYSCRTL_SIZE SZ_4K
41 #define OXNAS_SYSCRTL_BASE_VA 0xF0004000
43 #define OXNAS_SECCRTL_BASE 0x44F00000
44 #define OXNAS_SECCRTL_SIZE SZ_4K
45 #define OXNAS_SECCRTL_BASE_VA 0xF0005000
47 #define OXNAS_RPSA_BASE 0x44400000
48 #define OXNAS_RPSA_SIZE SZ_4K
49 #define OXNAS_RPSA_BASE_VA 0xF0006000
51 #define OXNAS_RPSC_BASE 0x44500000
52 #define OXNAS_RPSC_SIZE SZ_4K
53 #define OXNAS_RPSC_BASE_VA 0xF0007000
57 * Location of flags and vectors in SRAM for controlling the booting of the
58 * secondary ARM11 processors.
61 #define OXNAS_SCU_BASE_VA OXNAS_PERCPU_BASE_VA
62 #define OXNAS_GICN_BASE_VA(n) (OXNAS_PERCPU_BASE_VA + 0x200 + n*0x100)
64 #define HOLDINGPEN_CPU IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
65 #define HOLDINGPEN_LOCATION IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
68 * System block reset and clock control
70 #define SYS_CTRL_PCI_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x20)
71 #define SYSCTRL_CLK_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x24)
72 #define SYS_CTRL_CLK_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x2C)
73 #define SYS_CTRL_CLK_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x30)
74 #define SYS_CTRL_RST_SET_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x34)
75 #define SYS_CTRL_RST_CLR_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x38)
77 #define SYS_CTRL_PLLSYS_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x48)
78 #define SYS_CTRL_CLK_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x64)
79 #define SYS_CTRL_PLLSYS_KEY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x6C)
80 #define SYS_CTRL_GMAC_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x78)
81 #define SYS_CTRL_GMAC_DELAY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x100)
83 /* Scratch registers */
84 #define SYS_CTRL_SCRATCHWORD0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc4)
85 #define SYS_CTRL_SCRATCHWORD1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xc8)
86 #define SYS_CTRL_SCRATCHWORD2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xcc)
87 #define SYS_CTRL_SCRATCHWORD3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xd0)
89 #define SYS_CTRL_PLLA_CTRL0 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F0)
90 #define SYS_CTRL_PLLA_CTRL1 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F4)
91 #define SYS_CTRL_PLLA_CTRL2 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1F8)
92 #define SYS_CTRL_PLLA_CTRL3 IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x1FC)
94 #define SYS_CTRL_USBHSMPH_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x40)
95 #define SYS_CTRL_USBHSMPH_STAT IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x44)
96 #define SYS_CTRL_REF300_DIV IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xF8)
97 #define SYS_CTRL_USBHSPHY_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x84)
98 #define SYS_CTRL_USB_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x90)
101 #define SYS_CTRL_HCSL_CTRL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x114)
103 /* System control multi-function pin function selection */
104 #define SYS_CTRL_SECONDARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x14)
105 #define SYS_CTRL_TERTIARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x8c)
106 #define SYS_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x94)
107 #define SYS_CTRL_DEBUG_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0x9c)
108 #define SYS_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xa4)
109 #define SYS_CTRL_PULLUP_SEL IOMEM(OXNAS_SYSCRTL_BASE_VA + 0xac)
111 /* Secure control multi-function pin function selection */
112 #define SEC_CTRL_SECONDARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x14)
113 #define SEC_CTRL_TERTIARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x8c)
114 #define SEC_CTRL_QUATERNARY_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x94)
115 #define SEC_CTRL_DEBUG_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x9c)
116 #define SEC_CTRL_ALTERNATIVE_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xa4)
117 #define SEC_CTRL_PULLUP_SEL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xac)
119 #define SEC_CTRL_COPRO_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x68)
120 #define SEC_CTRL_SECURE_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0x98)
121 #define SEC_CTRL_LEON_DEBUG IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF0)
122 #define SEC_CTRL_PLLB_DIV_CTRL IOMEM(OXNAS_SECCRTL_BASE_VA + 0xF8)
123 #define SEC_CTRL_PLLB_CTRL0 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F0)
124 #define SEC_CTRL_PLLB_CTRL1 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
125 #define SEC_CTRL_PLLB_CTRL8 IOMEM(OXNAS_SECCRTL_BASE_VA + 0x1F4)
127 #define RPSA_IRQ_SOFT IOMEM(OXNAS_RPSA_BASE_VA + 0x10)
128 #define RPSA_FIQ_ENABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x108)
129 #define RPSA_FIQ_DISABLE IOMEM(OXNAS_RPSA_BASE_VA + 0x10C)
130 #define RPSA_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSA_BASE_VA + 0x1FC)
132 #define RPSC_IRQ_SOFT IOMEM(OXNAS_RPSC_BASE_VA + 0x10)
133 #define RPSC_FIQ_ENABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x108)
134 #define RPSC_FIQ_DISABLE IOMEM(OXNAS_RPSC_BASE_VA + 0x10C)
135 #define RPSC_FIQ_IRQ_TO_FIQ IOMEM(OXNAS_RPSC_BASE_VA + 0x1FC)
137 #define RPSA_TIMER2_VAL IOMEM(OXNAS_RPSA_BASE_VA + 0x224)
139 #define REF300_DIV_INT_SHIFT 8
140 #define REF300_DIV_FRAC_SHIFT 0
141 #define REF300_DIV_INT(val) ((val) << REF300_DIV_INT_SHIFT)
142 #define REF300_DIV_FRAC(val) ((val) << REF300_DIV_FRAC_SHIFT)
144 #define USBHSPHY_SUSPENDM_MANUAL_ENABLE 16
145 #define USBHSPHY_SUSPENDM_MANUAL_STATE 15
146 #define USBHSPHY_ATE_ESET 14
147 #define USBHSPHY_TEST_DIN 6
148 #define USBHSPHY_TEST_ADD 2
149 #define USBHSPHY_TEST_DOUT_SEL 1
150 #define USBHSPHY_TEST_CLK 0
152 #define USB_CTRL_USBAPHY_CKSEL_SHIFT 5
153 #define USB_CLK_XTAL0_XTAL1 (0 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
154 #define USB_CLK_XTAL0 (1 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
155 #define USB_CLK_INTERNAL (2 << USB_CTRL_USBAPHY_CKSEL_SHIFT)
157 #define USBAMUX_DEVICE BIT(4)
159 #define USBPHY_REFCLKDIV_SHIFT 2
160 #define USB_PHY_REF_12MHZ (0 << USBPHY_REFCLKDIV_SHIFT)
161 #define USB_PHY_REF_24MHZ (1 << USBPHY_REFCLKDIV_SHIFT)
162 #define USB_PHY_REF_48MHZ (2 << USBPHY_REFCLKDIV_SHIFT)
164 #define USB_CTRL_USB_CKO_SEL_BIT 0
166 #define USB_INT_CLK_XTAL 0
167 #define USB_INT_CLK_REF300 2
168 #define USB_INT_CLK_PLLB 3
170 #define SYS_CTRL_GMAC_CKEN_RX_IN 14
171 #define SYS_CTRL_GMAC_CKEN_RXN_OUT 13
172 #define SYS_CTRL_GMAC_CKEN_RX_OUT 12
173 #define SYS_CTRL_GMAC_CKEN_TX_IN 10
174 #define SYS_CTRL_GMAC_CKEN_TXN_OUT 9
175 #define SYS_CTRL_GMAC_CKEN_TX_OUT 8
176 #define SYS_CTRL_GMAC_RX_SOURCE 7
177 #define SYS_CTRL_GMAC_TX_SOURCE 6
178 #define SYS_CTRL_GMAC_LOW_TX_SOURCE 4
179 #define SYS_CTRL_GMAC_AUTO_TX_SOURCE 3
180 #define SYS_CTRL_GMAC_RGMII 2
181 #define SYS_CTRL_GMAC_SIMPLE_MUX 1
182 #define SYS_CTRL_GMAC_CKEN_GTX 0
183 #define SYS_CTRL_GMAC_TX_VARDELAY_SHIFT 0
184 #define SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT 8
185 #define SYS_CTRL_GMAC_RX_VARDELAY_SHIFT 16
186 #define SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT 24
187 #define SYS_CTRL_GMAC_TX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TX_VARDELAY_SHIFT)
188 #define SYS_CTRL_GMAC_TXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_TXN_VARDELAY_SHIFT)
189 #define SYS_CTRL_GMAC_RX_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RX_VARDELAY_SHIFT)
190 #define SYS_CTRL_GMAC_RXN_VARDELAY(d) ((d)<<SYS_CTRL_GMAC_RXN_VARDELAY_SHIFT)
192 #define PLLB_BYPASS 1
194 #define PLLB_OUTDIV 4
195 #define PLLB_REFDIV 8
196 #define PLLB_DIV_INT_SHIFT 8
197 #define PLLB_DIV_FRAC_SHIFT 0
198 #define PLLB_DIV_INT(val) ((val) << PLLB_DIV_INT_SHIFT)
199 #define PLLB_DIV_FRAC(val) ((val) << PLLB_DIV_FRAC_SHIFT)
201 #define SYS_CTRL_CKCTRL_PCI_DIV_BIT 0
202 #define SYS_CTRL_CKCTRL_SLOW_BIT 8
204 #define SYS_CTRL_UART2_DEQ_EN 0
205 #define SYS_CTRL_UART3_DEQ_EN 1
206 #define SYS_CTRL_UART3_IQ_EN 2
207 #define SYS_CTRL_UART4_IQ_EN 3
208 #define SYS_CTRL_UART4_NOT_PCI_MODE 4
210 #define SYS_CTRL_PCI_CTRL1_PCI_STATIC_RQ_BIT 11
212 #define PLLA_REFDIV_MASK 0x3F
213 #define PLLA_REFDIV_SHIFT 8
214 #define PLLA_OUTDIV_MASK 0x7
215 #define PLLA_OUTDIV_SHIFT 4
217 /* bit numbers of clock control register */
218 #define SYS_CTRL_CLK_COPRO 0
219 #define SYS_CTRL_CLK_DMA 1
220 #define SYS_CTRL_CLK_CIPHER 2
221 #define SYS_CTRL_CLK_SD 3
222 #define SYS_CTRL_CLK_SATA 4
223 #define SYS_CTRL_CLK_I2S 5
224 #define SYS_CTRL_CLK_USBHS 6
225 #define SYS_CTRL_CLK_MACA 7
226 #define SYS_CTRL_CLK_MAC SYS_CTRL_CLK_MACA
227 #define SYS_CTRL_CLK_PCIEA 8
228 #define SYS_CTRL_CLK_STATIC 9
229 #define SYS_CTRL_CLK_MACB 10
230 #define SYS_CTRL_CLK_PCIEB 11
231 #define SYS_CTRL_CLK_REF600 12
232 #define SYS_CTRL_CLK_USBDEV 13
233 #define SYS_CTRL_CLK_DDR 14
234 #define SYS_CTRL_CLK_DDRPHY 15
235 #define SYS_CTRL_CLK_DDRCK 16
238 /* bit numbers of reset control register */
239 #define SYS_CTRL_RST_SCU 0
240 #define SYS_CTRL_RST_COPRO 1
241 #define SYS_CTRL_RST_ARM0 2
242 #define SYS_CTRL_RST_ARM1 3
243 #define SYS_CTRL_RST_USBHS 4
244 #define SYS_CTRL_RST_USBHSPHYA 5
245 #define SYS_CTRL_RST_MACA 6
246 #define SYS_CTRL_RST_MAC SYS_CTRL_RST_MACA
247 #define SYS_CTRL_RST_PCIEA 7
248 #define SYS_CTRL_RST_SGDMA 8
249 #define SYS_CTRL_RST_CIPHER 9
250 #define SYS_CTRL_RST_DDR 10
251 #define SYS_CTRL_RST_SATA 11
252 #define SYS_CTRL_RST_SATA_LINK 12
253 #define SYS_CTRL_RST_SATA_PHY 13
254 #define SYS_CTRL_RST_PCIEPHY 14
255 #define SYS_CTRL_RST_STATIC 15
256 #define SYS_CTRL_RST_GPIO 16
257 #define SYS_CTRL_RST_UART1 17
258 #define SYS_CTRL_RST_UART2 18
259 #define SYS_CTRL_RST_MISC 19
260 #define SYS_CTRL_RST_I2S 20
261 #define SYS_CTRL_RST_SD 21
262 #define SYS_CTRL_RST_MACB 22
263 #define SYS_CTRL_RST_PCIEB 23
264 #define SYS_CTRL_RST_VIDEO 24
265 #define SYS_CTRL_RST_DDR_PHY 25
266 #define SYS_CTRL_RST_USBHSPHYB 26
267 #define SYS_CTRL_RST_USBDEV 27
268 #define SYS_CTRL_RST_ARMDBG 29
269 #define SYS_CTRL_RST_PLLA 30
270 #define SYS_CTRL_RST_PLLB 31
272 static inline void oxnas_register_clear_mask(void __iomem *p, unsigned mask)
274 u32 val = readl_relaxed(p);
277 writel_relaxed(val, p);
280 static inline void oxnas_register_set_mask(void __iomem *p, unsigned mask)
282 u32 val = readl_relaxed(p);
285 writel_relaxed(val, p);
288 static inline void oxnas_register_value_mask(void __iomem *p,
289 unsigned mask, unsigned new_value)
291 /* TODO sanity check mask & new_value = new_value */
292 u32 val = readl_relaxed(p);
296 writel_relaxed(val, p);
299 #define VERSION_ID_MAGIC 0x082510b5
300 #define LINK_UP_TIMEOUT_SECONDS 1
301 #define NUM_CONTROLLERS 1
304 PCIE_DEVICE_TYPE_MASK = 0x0F,
305 PCIE_DEVICE_TYPE_ENDPOINT = 0,
306 PCIE_DEVICE_TYPE_LEGACY_ENDPOINT = 1,
307 PCIE_DEVICE_TYPE_ROOT = 4,
310 PCIE_READY_ENTR_L23 = BIT(9),
311 PCIE_LINK_UP = BIT(11),
312 PCIE_OBTRANS = BIT(12),
316 HCSL_BIAS_ON = BIT(0),
317 HCSL_PCIE_EN = BIT(1),
318 HCSL_PCIEA_EN = BIT(2),
319 HCSL_PCIEB_EN = BIT(3),
323 /* pcie phy reg offset */
326 /* phy data reg bits */
332 /* core config registers */
334 PCI_CONFIG_VERSION_DEVICEID = 0,
335 PCI_CONFIG_COMMAND_STATUS = 4,
338 /* inbound config registers */
340 IB_ADDR_XLATE_ENABLE = 0xFC,
343 ENABLE_IN_ADDR_TRANS = BIT(0),
346 /* outbound config registers, offset relative to PCIE_POM0_MEM_ADDR */
348 PCIE_POM0_MEM_ADDR = 0,
349 PCIE_POM1_MEM_ADDR = 4,
350 PCIE_IN0_MEM_ADDR = 8,
351 PCIE_IN1_MEM_ADDR = 12,
352 PCIE_IN_IO_ADDR = 16,
353 PCIE_IN_CFG0_ADDR = 20,
354 PCIE_IN_CFG1_ADDR = 24,
355 PCIE_IN_MSG_ADDR = 28,
356 PCIE_IN0_MEM_LIMIT = 32,
357 PCIE_IN1_MEM_LIMIT = 36,
358 PCIE_IN_IO_LIMIT = 40,
359 PCIE_IN_CFG0_LIMIT = 44,
360 PCIE_IN_CFG1_LIMIT = 48,
361 PCIE_IN_MSG_LIMIT = 52,
362 PCIE_AHB_SLAVE_CTRL = 56,
364 PCIE_SLAVE_BE_SHIFT = 22,
367 #define ADDR_VAL(val) ((val) & 0xFFFF)
368 #define DATA_VAL(val) ((val) & 0xFFFF)
370 #define PCIE_SLAVE_BE(val) ((val) << PCIE_SLAVE_BE_SHIFT)
371 #define PCIE_SLAVE_BE_MASK PCIE_SLAVE_BE(0xF)
373 struct oxnas_pcie_shared {
374 /* seems all access are serialized, no lock required */
378 /* Structure representing one PCIe interfaces */
380 void __iomem *cfgbase;
382 void __iomem *inbound;
383 void __iomem *outbound;
384 void __iomem *pcie_ctrl;
387 struct platform_device *pdev;
390 struct resource pre_mem; /* prefetchable */
391 struct resource non_mem; /* non-prefetchable */
392 struct resource busn; /* max available bus numbers */
393 int card_reset; /* gpio pin, optional */
394 unsigned hcsl_en; /* hcsl pci enable bit */
396 struct clk *busclk; /* for pcie bus, actually the PLLB */
397 void *private_data[1];
401 static struct oxnas_pcie_shared pcie_shared = {
405 static inline struct oxnas_pcie *sys_to_pcie(struct pci_sys_data *sys)
407 return sys->private_data;
411 static inline void set_out_lanes(struct oxnas_pcie *pcie, unsigned lanes)
413 oxnas_register_value_mask(pcie->outbound + PCIE_AHB_SLAVE_CTRL,
414 PCIE_SLAVE_BE_MASK, PCIE_SLAVE_BE(lanes));
418 static int oxnas_pcie_link_up(struct oxnas_pcie *pcie)
422 /* Poll for PCIE link up */
423 end = jiffies + (LINK_UP_TIMEOUT_SECONDS * HZ);
424 while (!time_after(jiffies, end)) {
425 if (readl(pcie->pcie_ctrl) & PCIE_LINK_UP)
431 static void __init oxnas_pcie_setup_hw(struct oxnas_pcie *pcie)
433 /* We won't have any inbound address translation. This allows PCI
434 * devices to access anywhere in the AHB address map. Might be regarded
435 * as a bit dangerous, but let's get things working before we worry
438 oxnas_register_clear_mask(pcie->inbound + IB_ADDR_XLATE_ENABLE,
439 ENABLE_IN_ADDR_TRANS);
443 * Program outbound translation windows
445 * Outbound window is what is referred to as "PCI client" region in HRM
447 * Could use the larger alternative address space to get >>64M regions
448 * for graphics cards etc., but will not bother at this point.
450 * IP bug means that AMBA window size must be a power of 2
452 * Set mem0 window for first 16MB of outbound window non-prefetchable
453 * Set mem1 window for second 16MB of outbound window prefetchable
454 * Set io window for next 16MB of outbound window
455 * Set cfg0 for final 1MB of outbound window
457 * Ignore mem1, cfg1 and msg windows for now as no obvious use cases for
458 * 820 that would need them
460 * Probably ideally want no offset between mem0 window start as seen by
461 * ARM and as seen on PCI bus and get Linux to assign memory regions to
462 * PCI devices using the same "PCI client" region start address as seen
466 /* Set PCIeA mem0 region to be 1st 16MB of the 64MB PCIeA window */
467 writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_IN0_MEM_ADDR);
468 writel_relaxed(pcie->non_mem.end, pcie->outbound + PCIE_IN0_MEM_LIMIT);
469 writel_relaxed(pcie->non_mem.start, pcie->outbound + PCIE_POM0_MEM_ADDR);
471 /* Set PCIeA mem1 region to be 2nd 16MB of the 64MB PCIeA window */
472 writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_IN1_MEM_ADDR);
473 writel_relaxed(pcie->pre_mem.end, pcie->outbound + PCIE_IN1_MEM_LIMIT);
474 writel_relaxed(pcie->pre_mem.start, pcie->outbound + PCIE_POM1_MEM_ADDR);
476 /* Set PCIeA io to be third 16M region of the 64MB PCIeA window*/
477 writel_relaxed(pcie->io.start, pcie->outbound + PCIE_IN_IO_ADDR);
478 writel_relaxed(pcie->io.end, pcie->outbound + PCIE_IN_IO_LIMIT);
480 /* Set PCIeA cgf0 to be last 16M region of the 64MB PCIeA window*/
481 writel_relaxed(pcie->cfg.start, pcie->outbound + PCIE_IN_CFG0_ADDR);
482 writel_relaxed(pcie->cfg.end, pcie->outbound + PCIE_IN_CFG0_LIMIT);
485 /* Enable outbound address translation */
486 oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_OBTRANS);
490 * Program PCIe command register for core to:
491 * enable memory space
495 writel_relaxed(7, pcie->base + PCI_CONFIG_COMMAND_STATUS);
500 static unsigned oxnas_pcie_cfg_to_offset(
501 struct pci_sys_data *sys,
502 unsigned char bus_number,
506 unsigned int function = PCI_FUNC(devfn);
507 unsigned int slot = PCI_SLOT(devfn);
508 unsigned char bus_number_offset;
510 bus_number_offset = bus_number - sys->busnr;
513 * We'll assume for now that the offset, function, slot, bus encoding
514 * should map onto linear, contiguous addresses in PCIe config space,
515 * albeit that the majority will be unused as only slot 0 is valid for
516 * any PCIe bus and most devices have only function 0
518 * Could be that PCIe in fact works by not encoding the slot number into
519 * the config space address as it's known that only slot 0 is valid.
520 * We'll have to experiment if/when we get a PCIe switch connected to
523 return (bus_number_offset << 20) | (slot << 15) | (function << 12) |
527 /* PCI configuration space write function */
528 static int oxnas_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
529 int where, int size, u32 val)
532 struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
537 /* Only a single device per bus for PCIe point-to-point links */
538 if (PCI_SLOT(devfn) > 0)
539 return PCIBIOS_DEVICE_NOT_FOUND;
542 return PCIBIOS_DEVICE_NOT_FOUND;
544 offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
547 value = val << (8 * (where & 3));
548 lanes = (0xf >> (4-size)) << (where & 3);
549 /* it race with mem and io write, but the possibility is low, normally
550 * all config writes happens at driver initialize stage, wont interleave
552 * and many pcie cards use dword (4bytes) access mem/io access only,
553 * so not bother to copy that ugly work-around now. */
554 spin_lock_irqsave(&pcie->lock, flags);
555 set_out_lanes(pcie, lanes);
556 writel_relaxed(value, pcie->cfgbase + offset);
557 set_out_lanes(pcie, 0xf);
558 spin_unlock_irqrestore(&pcie->lock, flags);
560 return PCIBIOS_SUCCESSFUL;
563 /* PCI configuration space read function */
564 static int oxnas_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
567 struct oxnas_pcie *pcie = sys_to_pcie(bus->sysdata);
570 u32 left_bytes, right_bytes;
572 /* Only a single device per bus for PCIe point-to-point links */
573 if (PCI_SLOT(devfn) > 0) {
575 return PCIBIOS_DEVICE_NOT_FOUND;
578 if (!pcie->haslink) {
580 return PCIBIOS_DEVICE_NOT_FOUND;
583 offset = oxnas_pcie_cfg_to_offset(bus->sysdata, bus->number, devfn,
585 value = readl_relaxed(pcie->cfgbase + offset);
586 left_bytes = where & 3;
587 right_bytes = 4 - left_bytes - size;
588 value <<= right_bytes * 8;
589 value >>= (left_bytes + right_bytes) * 8;
592 return PCIBIOS_SUCCESSFUL;
595 static struct pci_ops oxnas_pcie_ops = {
596 .read = oxnas_pcie_rd_conf,
597 .write = oxnas_pcie_wr_conf,
600 static int __init oxnas_pcie_setup(int nr, struct pci_sys_data *sys)
602 struct oxnas_pcie *pcie = sys_to_pcie(sys);
604 pci_add_resource_offset(&sys->resources, &pcie->non_mem, sys->mem_offset);
605 pci_add_resource_offset(&sys->resources, &pcie->pre_mem, sys->mem_offset);
606 pci_add_resource_offset(&sys->resources, &pcie->io, sys->io_offset);
607 pci_add_resource(&sys->resources, &pcie->busn);
608 if (sys->busnr == 0) { /* default one */
609 sys->busnr = pcie->busn.start;
611 /* do not use devm_ioremap_resource, it does not like cfg resource */
612 pcie->cfgbase = devm_ioremap(&pcie->pdev->dev, pcie->cfg.start,
613 resource_size(&pcie->cfg));
617 oxnas_pcie_setup_hw(pcie);
622 static void __init oxnas_pcie_enable(struct device *dev, struct oxnas_pcie *pcie)
627 memset(&hw, 0, sizeof(hw));
628 for (i = 0; i < NUM_CONTROLLERS; i++)
629 pcie->private_data[i] = pcie;
631 hw.nr_controllers = NUM_CONTROLLERS;
632 /* I think use stack pointer is a bad idea though it is valid in this case */
633 hw.private_data = pcie->private_data;
634 hw.setup = oxnas_pcie_setup;
635 hw.map_irq = of_irq_parse_and_map_pci;
636 hw.ops = &oxnas_pcie_ops;
638 /* pass dev to maintain of tree, interrupt mapping rely on this */
639 pci_common_init_dev(dev, &hw);
642 void oxnas_pcie_init_shared_hw(struct platform_device *pdev,
643 void __iomem *phybase)
645 struct reset_control *rstc;
648 /* generate clocks from HCSL buffers, shared parts */
649 writel(HCSL_BIAS_ON|HCSL_PCIE_EN, SYS_CTRL_HCSL_CTRL);
651 /* Ensure PCIe PHY is properly reset */
652 rstc = reset_control_get(&pdev->dev, "phy");
656 ret = reset_control_reset(rstc);
657 reset_control_put(rstc);
661 dev_err(&pdev->dev, "phy reset failed %d\n", ret);
665 /* Enable PCIe Pre-Emphasis: What these value means? */
667 writel(ADDR_VAL(0x0014), phybase + PHY_ADDR);
668 writel(DATA_VAL(0xce10) | CAP_DATA, phybase + PHY_DATA);
669 writel(DATA_VAL(0xce10) | WRITE_EN, phybase + PHY_DATA);
671 writel(ADDR_VAL(0x2004), phybase + PHY_ADDR);
672 writel(DATA_VAL(0x82c7) | CAP_DATA, phybase + PHY_DATA);
673 writel(DATA_VAL(0x82c7) | WRITE_EN, phybase + PHY_DATA);
676 static int oxnas_pcie_shared_init(struct platform_device *pdev)
678 if (++pcie_shared.refcount == 1) {
679 /* we are the first */
680 struct device_node *np = pdev->dev.of_node;
681 void __iomem *phy = of_iomap(np, 2);
683 --pcie_shared.refcount;
686 oxnas_pcie_init_shared_hw(pdev, phy);
695 /* maybe we will call it when enter low power state */
696 static void oxnas_pcie_shared_deinit(struct platform_device *pdev)
698 if (--pcie_shared.refcount == 0) {
699 /* no cleanup needed */;
705 oxnas_pcie_map_registers(struct platform_device *pdev,
706 struct device_node *np,
707 struct oxnas_pcie *pcie)
709 struct resource regs;
711 u32 outbound_ctrl_offset;
712 u32 pcie_ctrl_offset;
714 /* 2 is reserved for shared phy */
715 ret = of_address_to_resource(np, 0, ®s);
718 pcie->base = devm_ioremap_resource(&pdev->dev, ®s);
722 ret = of_address_to_resource(np, 1, ®s);
725 pcie->inbound = devm_ioremap_resource(&pdev->dev, ®s);
730 if (of_property_read_u32(np, "plxtech,pcie-outbound-offset",
731 &outbound_ctrl_offset))
733 /* SYSCRTL is shared by too many drivers, so is mapped by board file */
734 pcie->outbound = IOMEM(OXNAS_SYSCRTL_BASE_VA + outbound_ctrl_offset);
736 if (of_property_read_u32(np, "plxtech,pcie-ctrl-offset",
739 pcie->pcie_ctrl = IOMEM(OXNAS_SYSCRTL_BASE_VA + pcie_ctrl_offset);
744 static int __init oxnas_pcie_init_res(struct platform_device *pdev,
745 struct oxnas_pcie *pcie,
746 struct device_node *np)
748 struct of_pci_range range;
749 struct of_pci_range_parser parser;
752 if (of_pci_range_parser_init(&parser, np))
755 /* Get the I/O and memory ranges from DT */
756 for_each_of_pci_range(&parser, &range) {
758 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
759 if (restype == IORESOURCE_IO) {
760 of_pci_range_to_resource(&range, np, &pcie->io);
761 pcie->io.name = "I/O";
763 if (restype == IORESOURCE_MEM) {
764 if (range.flags & IORESOURCE_PREFETCH) {
765 of_pci_range_to_resource(&range, np, &pcie->pre_mem);
766 pcie->pre_mem.name = "PRE MEM";
768 of_pci_range_to_resource(&range, np, &pcie->non_mem);
769 pcie->non_mem.name = "NON MEM";
774 of_pci_range_to_resource(&range, np, &pcie->cfg);
777 /* Get the bus range */
778 ret = of_pci_parse_bus_range(np, &pcie->busn);
781 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
786 pcie->card_reset = of_get_gpio(np, 0);
787 if (pcie->card_reset < 0)
788 dev_info(&pdev->dev, "card reset gpio pin not exists\n");
790 if (of_property_read_u32(np, "plxtech,pcie-hcsl-bit", &pcie->hcsl_en))
793 pcie->clk = of_clk_get_by_name(np, "pcie");
794 if (IS_ERR(pcie->clk)) {
795 return PTR_ERR(pcie->clk);
798 pcie->busclk = of_clk_get_by_name(np, "busclk");
799 if (IS_ERR(pcie->busclk)) {
801 return PTR_ERR(pcie->busclk);
807 static void oxnas_pcie_init_hw(struct platform_device *pdev,
808 struct oxnas_pcie *pcie)
813 clk_prepare_enable(pcie->busclk);
815 /* reset PCIe cards use hard-wired gpio pin */
816 if (pcie->card_reset >= 0 &&
817 !gpio_direction_output(pcie->card_reset, 0)) {
820 /* must tri-state the pin to pull it up */
821 gpio_direction_input(pcie->card_reset);
826 oxnas_register_set_mask(SYS_CTRL_HCSL_CTRL, BIT(pcie->hcsl_en));
829 ret = device_reset(&pdev->dev);
831 dev_err(&pdev->dev, "core reset failed %d\n", ret);
835 /* Start PCIe core clocks */
836 clk_prepare_enable(pcie->clk);
838 version_id = readl_relaxed(pcie->base + PCI_CONFIG_VERSION_DEVICEID);
839 dev_info(&pdev->dev, "PCIe version/deviceID 0x%x\n", version_id);
841 if (version_id != VERSION_ID_MAGIC) {
842 dev_info(&pdev->dev, "PCIe controller not found\n");
847 /* allow entry to L23 state */
848 oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_READY_ENTR_L23);
850 /* Set PCIe core into RootCore mode */
851 oxnas_register_value_mask(pcie->pcie_ctrl, PCIE_DEVICE_TYPE_MASK,
852 PCIE_DEVICE_TYPE_ROOT);
855 /* Bring up the PCI core */
856 oxnas_register_set_mask(pcie->pcie_ctrl, PCIE_LTSSM);
860 static int __init oxnas_pcie_probe(struct platform_device *pdev)
862 struct oxnas_pcie *pcie;
863 struct device_node *np = pdev->dev.of_node;
866 pcie = devm_kzalloc(&pdev->dev, sizeof(struct oxnas_pcie),
873 spin_lock_init(&pcie->lock);
875 ret = oxnas_pcie_init_res(pdev, pcie, np);
878 if (pcie->card_reset >= 0) {
879 ret = gpio_request_one(pcie->card_reset, GPIOF_DIR_IN,
880 dev_name(&pdev->dev));
882 dev_err(&pdev->dev, "cannot request gpio pin %d\n",
888 ret = oxnas_pcie_map_registers(pdev, np, pcie);
890 dev_err(&pdev->dev, "cannot map registers\n");
894 ret = oxnas_pcie_shared_init(pdev);
898 /* if hw not found, haslink cleared */
899 oxnas_pcie_init_hw(pdev, pcie);
901 if (pcie->haslink && oxnas_pcie_link_up(pcie)) {
903 dev_info(&pdev->dev, "link up\n");
906 dev_info(&pdev->dev, "link down\n");
908 /* should we register our controller even when pcie->haslink is 0 ? */
909 /* register the controller with framework */
910 oxnas_pcie_enable(&pdev->dev, pcie);
915 if (pcie->card_reset)
916 gpio_free(pcie->card_reset);
921 static const struct of_device_id oxnas_pcie_of_match_table[] = {
922 { .compatible = "plxtech,nas782x-pcie", },
925 MODULE_DEVICE_TABLE(of, oxnas_pcie_of_match_table);
927 static struct platform_driver oxnas_pcie_driver = {
929 .owner = THIS_MODULE,
930 .name = "oxnas-pcie",
932 of_match_ptr(oxnas_pcie_of_match_table),
936 static int __init oxnas_pcie_init(void)
938 return platform_driver_probe(&oxnas_pcie_driver,
942 subsys_initcall(oxnas_pcie_init);
944 MODULE_AUTHOR("Ma Haijun <mahaijuns@gmail.com>");
945 MODULE_DESCRIPTION("NAS782x PCIe driver");
946 MODULE_LICENSE("GPLv2");