2 #include <linux/libata.h>
3 #include <linux/of_platform.h>
4 #include <linux/delay.h>
5 #include <linux/module.h>
6 #include <linux/slab.h>
7 #include <linux/of_address.h>
8 #include <linux/of_irq.h>
10 #include <linux/reset.h>
12 #include <mach/utils.h>
14 /* sgdma request structure */
15 struct sgdma_request {
16 volatile u32 qualifier;
20 } __packed __aligned(4);
23 /* Controller information */
25 SATA_OXNAS_MAX_PRD = 254,
26 SATA_OXNAS_DMA_SIZE = SATA_OXNAS_MAX_PRD *
27 sizeof(struct ata_bmdma_prd) +
28 sizeof(struct sgdma_request),
29 SATA_OXNAS_MAX_PORTS = 1,
30 /** The different Oxsemi SATA core version numbers */
31 SATA_OXNAS_CORE_VERSION = 0x1f3,
32 SATA_OXNAS_IRQ_FLAG = IRQF_SHARED,
33 SATA_OXNAS_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
34 ATA_FLAG_NO_ATAPI /*| ATA_FLAG_NCQ*/),
35 SATA_OXNAS_QUEUE_DEPTH = 32,
37 SATA_OXNAS_DMA_BOUNDARY = 0xFFFFFFFF,
45 /** sata host port register offsets */
64 /** These registers allow access to the link layer registers
65 that reside in a different clock domain to the processor bus */
79 /** sata port register bits */
82 * commands to issue in the master status to tell it to move shadow ,
83 * registers to the actual device ,
85 SATA_OPCODE_MASK = 0x00000007,
86 CMD_WRITE_TO_ORB_REGS_NO_COMMAND = 0x4,
87 CMD_WRITE_TO_ORB_REGS = 0x2,
88 CMD_SYNC_ESCAPE = 0x7,
89 CMD_CORE_BUSY = (1 << 7),
90 CMD_DRIVE_SELECT_SHIFT = 12,
91 CMD_DRIVE_SELECT_MASK = (0xf << CMD_DRIVE_SELECT_SHIFT),
94 INT_END_OF_CMD = 1 << 0,
95 INT_LINK_SERROR = 1 << 1,
97 INT_LINK_IRQ = 1 << 3,
98 INT_REG_ACCESS_ERR = 1 << 7,
99 INT_BIST_FIS = 1 << 11,
100 INT_MASKABLE = INT_END_OF_CMD |
106 INT_WANT = INT_END_OF_CMD |
110 INT_ERRORS = INT_LINK_SERROR |
114 /** raw interrupt bits, unmaskable, but do not generate interrupts */
115 RAW_END_OF_CMD = INT_END_OF_CMD << 16,
116 RAW_LINK_SERROR = INT_LINK_SERROR << 16,
117 RAW_ERROR = INT_ERROR << 16,
118 RAW_LINK_IRQ = INT_LINK_IRQ << 16,
119 RAW_REG_ACCESS_ERR = INT_REG_ACCESS_ERR << 16,
120 RAW_BIST_FIS = INT_BIST_FIS << 16,
121 RAW_WANT = INT_WANT << 16,
122 RAW_ERRORS = INT_ERRORS << 16,
125 * variables to write to the device control register to set the current
126 * device, ie. master or slave.
131 SATA_CTL_ERR_MASK = 0x00000016,
135 /* ATA SGDMA register offsets */
139 SGDMA_REQUESTPTR = 0x8,
141 SGDMA_CORESIZE = 0x10,
145 /* see DMA core docs for the values. Out means from memory (bus A) out
147 SGDMA_REQCTL0OUT = 0x0497c03d,
148 /* burst mode disabled when no micro code used */
149 SGDMA_REQCTL0IN = 0x0493a3c1,
150 SGDMA_REQCTL1OUT = 0x0497c07d,
151 SGDMA_REQCTL1IN = 0x0497a3c5,
152 SGDMA_CONTROL_NOGO = 0x3e,
153 SGDMA_CONTROL_GO = SGDMA_CONTROL_NOGO | 1,
154 SGDMA_ERRORMASK = 0x3f,
157 SGDMA_RESETS_CTRL = 1 << 0,
158 SGDMA_RESETS_ARBT = 1 << 1,
159 SGDMA_RESETS_AHB = 1 << 2,
160 SGDMA_RESETS_ALL = SGDMA_RESETS_CTRL |
165 SGDMA_REQQUAL = 0x00220001,
169 /** SATA core register offsets */
174 DATACOUNT_PORT0 = 0x010,
175 DATACOUNT_PORT1 = 0x014,
176 CORE_INT_STATUS = 0x030,
177 CORE_INT_CLEAR = 0x030,
178 CORE_INT_ENABLE = 0x034,
179 CORE_INT_DISABLE = 0x038,
180 CORE_REBUILD_ENABLE = 0x050,
181 CORE_FAILED_PORT_R = 0x054,
182 DEVICE_CONTROL = 0x068,
184 RAID_SIZE_LOW = 0x070,
185 RAID_SIZE_HIGH = 0x074,
186 PORT_ERROR_MASK = 0x078,
188 RAID_CONTROL = 0x090,
189 DATA_PLANE_CTRL = 0x0AC,
190 CORE_DATAPLANE_STAT = 0x0b8,
195 UCODE_STORE = 0x1000,
196 RAID_WP_BOT_LOW = 0x1FF0,
197 RAID_WP_BOT_HIGH = 0x1FF4,
198 RAID_WP_TOP_LOW = 0x1FF8,
199 RAID_WP_TOP_HIGH = 0x1FFC,
200 DATA_MUX_RAM0 = 0x8000,
201 DATA_MUX_RAM1 = 0xA000,
205 /* Sata core debug1 register bits */
206 CORE_PORT0_DATA_DIR_BIT = 20,
207 CORE_PORT1_DATA_DIR_BIT = 21,
208 CORE_PORT0_DATA_DIR = 1 << CORE_PORT0_DATA_DIR_BIT,
209 CORE_PORT1_DATA_DIR = 1 << CORE_PORT1_DATA_DIR_BIT,
211 /** sata core control register bits */
212 SCTL_CLR_ERR = 0x00003016,
213 RAID_CLR_ERR = 0x0000011e,
215 /* Interrupts direct from the ports */
216 NORMAL_INTS_WANTED = 0x00000303,
218 /* shift these left by port number */
219 COREINT_HOST = 0x00000001,
220 COREINT_END = 0x00000100,
221 CORERAW_HOST = COREINT_HOST << 16,
222 CORERAW_END = COREINT_END << 16,
224 /* Interrupts from the RAID controller only */
225 RAID_INTS_WANTED = 0x00008300,
227 /* The bits in the IDLE_STATUS that, when set indicate an idle core */
228 IDLE_CORES = (1 << 18) | (1 << 19),
230 /* Data plane control error-mask mask and bit, these bit in the data
231 * plane control mask out errors from the ports that prevent the SGDMA
232 * care from sending an interrupt */
233 DPC_ERROR_MASK = 0x00000300,
234 DPC_ERROR_MASK_BIT = 0x00000100,
235 /* enable jbod micro-code */
236 DPC_JBOD_UCODE = 1 << 0,
237 DPC_FIS_SWCH = 1 << 1,
239 /** Device Control register bits */
240 DEVICE_CONTROL_DMABT = 1 << 4,
241 DEVICE_CONTROL_ABORT = 1 << 2,
242 DEVICE_CONTROL_PAD = 1 << 3,
243 DEVICE_CONTROL_PADPAT = 1 << 16,
244 DEVICE_CONTROL_PRTRST = 1 << 8,
245 DEVICE_CONTROL_RAMRST = 1 << 12,
246 DEVICE_CONTROL_ATA_ERR_OVERRIDE = 1 << 28,
248 /** oxsemi HW raid modes */
249 OXNASSATA_NOTRAID = 0,
252 /** OX820 specific HW-RAID register values */
257 /* SATA PHY Registers */
264 STAT_READ_VALID = (1 << 21),
265 STAT_CR_ACK = (1 << 20),
266 STAT_CR_READ = (1 << 19),
267 STAT_CR_WRITE = (1 << 18),
268 STAT_CAP_DATA = (1 << 17),
269 STAT_CAP_ADDR = (1 << 16),
271 STAT_ACK_ANY = STAT_CR_ACK |
277 CR_READ_ENABLE = (1 << 16),
278 CR_WRITE_ENABLE = (1 << 17),
279 CR_CAP_DATA = (1 << 18),
283 /* Link layer registers */
288 OXNAS_SATA_SOFTRESET = 1,
289 OXNAS_SATA_REINIT = 2,
293 OXNAS_SATA_UCODE_RAID0,
294 OXNAS_SATA_UCODE_RAID1,
295 OXNAS_SATA_UCODE_JBOD,
296 OXNAS_SATA_UCODE_NONE,
299 struct sata_oxnas_host_priv {
300 void __iomem *port_base[SATA_OXNAS_MAX_PORTS];
301 void __iomem *sgdma_base[SATA_OXNAS_MAX_PORTS];
302 void __iomem *core_base;
303 void __iomem *phy_base;
305 void __iomem *dma_base_va;
310 struct reset_control *rst_sata;
311 struct reset_control *rst_link;
312 struct reset_control *rst_phy;
316 struct sata_oxnas_port_priv {
317 void __iomem *port_base;
318 void __iomem *sgdma_base;
319 void __iomem *core_base;
320 struct sgdma_request *sgdma_request;
321 dma_addr_t sgdma_request_pa;
324 static u8 sata_oxnas_check_status(struct ata_port *ap);
325 static int sata_oxnas_cleanup(struct ata_host *ah);
326 static void sata_oxnas_tf_load(struct ata_port *ap,
327 const struct ata_taskfile *tf);
328 static void sata_oxnas_irq_on(struct ata_port *ap);
329 static void sata_oxnas_post_reset_init(struct ata_port *ap);
331 /* ??????????????????????????????????? */
332 static void wait_cr_ack(void __iomem *phy_base)
334 while ((ioread32(phy_base + PHY_STAT) >> 16) & 0x1f)
335 ; /* wait for an ack bit to be set */
338 static u16 read_cr(void __iomem *phy_base, u16 address)
340 iowrite32((u32)address, phy_base + PHY_STAT);
341 wait_cr_ack(phy_base);
342 iowrite32(CR_READ_ENABLE, phy_base + PHY_DATA);
343 wait_cr_ack(phy_base);
344 return (u16)ioread32(phy_base + PHY_STAT);
347 static void write_cr(void __iomem *phy_base, u16 data, u16 address)
349 iowrite32((u32)address, phy_base + PHY_STAT);
350 wait_cr_ack(phy_base);
351 iowrite32((data | CR_CAP_DATA), phy_base + PHY_DATA);
352 wait_cr_ack(phy_base);
353 iowrite32(CR_WRITE_ENABLE, phy_base + PHY_DATA);
354 wait_cr_ack(phy_base);
359 #define PH_GAIN_OFFSET 6
360 #define FR_GAIN_OFFSET 8
361 #define PH_GAIN_MASK (0x3 << PH_GAIN_OFFSET)
362 #define FR_GAIN_MASK (0x3 << FR_GAIN_OFFSET)
363 #define USE_INT_SETTING (1<<5)
365 void workaround5458(struct ata_host *ah)
367 struct sata_oxnas_host_priv *hd = ah->private_data;
368 void __iomem *phy_base = hd->phy_base;
372 for (i = 0; i < 2; i++) {
373 rx_control = read_cr(phy_base, 0x201d + (i << 8));
374 rx_control &= ~(PH_GAIN_MASK | FR_GAIN_MASK);
375 rx_control |= PH_GAIN << PH_GAIN_OFFSET;
376 rx_control |= (FR_GAIN << FR_GAIN_OFFSET) | USE_INT_SETTING;
377 write_cr(phy_base, rx_control, 0x201d+(i<<8));
382 * allows access to the link layer registers
383 * @param link_reg the link layer register to access (oxsemi indexing ie
384 * 00 = static config, 04 = phy ctrl)
386 void sata_oxnas_link_write(struct ata_port *ap, unsigned int link_reg, u32 val)
388 struct sata_oxnas_port_priv *port_priv = ap->private_data;
389 void __iomem *port_base = port_priv->port_base;
392 DPRINTK("[0x%02x]->0x%08x\n", link_reg, val);
394 iowrite32(val, port_base + LINK_DATA);
396 /* accessed twice as a work around for a bug in the SATA abp bridge
397 * hardware (bug 6828) */
398 iowrite32(link_reg , port_base + LINK_WR_ADDR);
399 ioread32(port_base + LINK_WR_ADDR);
401 for (patience = 0x100000; patience > 0; --patience) {
402 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
407 static int sata_oxnas_scr_write_port(struct ata_port *ap, unsigned int sc_reg,
410 sata_oxnas_link_write(ap, 0x20 + (sc_reg * 4), val);
414 static int sata_oxnas_scr_write(struct ata_link *link, unsigned int sc_reg,
417 return sata_oxnas_scr_write_port(link->ap, sc_reg, val);
421 u32 sata_oxnas_link_read(struct ata_port *ap, unsigned int link_reg)
423 struct sata_oxnas_port_priv *pd = ap->private_data;
424 void __iomem *port_base = pd->port_base;
428 /* accessed twice as a work around for a bug in the SATA abp bridge
429 * hardware (bug 6828) */
430 iowrite32(link_reg, port_base + LINK_RD_ADDR);
431 ioread32(port_base + LINK_RD_ADDR);
433 for (patience = 0x100000; patience > 0; --patience) {
434 if (ioread32(port_base + LINK_CONTROL) & 0x00000001)
438 DPRINTK("link read timed out\n");
440 result = readl(port_base + LINK_DATA);
445 static int sata_oxnas_scr_read_port(struct ata_port *ap, unsigned int sc_reg,
448 *val = sata_oxnas_link_read(ap, 0x20 + (sc_reg*4));
452 static int sata_oxnas_scr_read(struct ata_link *link,
453 unsigned int sc_reg, u32 *val)
456 return sata_oxnas_scr_read_port(link->ap, sc_reg, val);
460 * sata_oxnas_irq_clear is called during probe just before the interrupt handler is
461 * registered, to be sure hardware is quiet. It clears and masks interrupt bits
464 * @param ap hardware with the registers in
466 static void sata_oxnas_irq_clear(struct ata_port *ap)
468 struct sata_oxnas_port_priv *port_priv = ap->private_data;
470 /* clear pending interrupts */
471 iowrite32(~0, port_priv->port_base + INT_CLEAR);
472 iowrite32(COREINT_END, port_priv->core_base + CORE_INT_CLEAR);
476 * qc_issue is used to make a command active, once the hardware and S/G tables
477 * have been prepared. IDE BMDMA drivers use the helper function
478 * ata_qc_issue_prot() for taskfile protocol-based dispatch. More advanced
479 * drivers roll their own ->qc_issue implementation, using this as the
480 * "issue new ATA command to hardware" hook.
481 * @param qc the queued command to issue
483 static unsigned int sata_oxnas_qc_issue(struct ata_queued_cmd *qc)
485 struct sata_oxnas_port_priv *pd = qc->ap->private_data;
486 void __iomem *port_base = pd->port_base;
487 void __iomem *core_base = pd->core_base;
488 int port_no = qc->ap->port_no;
491 /* check the core is idle */
492 if (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY) {
495 DPRINTK("core busy for a command on port %d\n",
500 DPRINTK("core busy for a command on port %d\n",
502 /* CrazyDumpDebug(); */
503 sata_oxnas_cleanup(qc->ap->host);
505 } while (ioread32(port_base + SATA_COMMAND) & CMD_CORE_BUSY);
508 /* enable passing of error signals to DMA sub-core by clearing the
509 * appropriate bit (all transfers are on dma channel 0) */
510 reg = ioread32(core_base + DATA_PLANE_CTRL);
511 reg &= ~(DPC_ERROR_MASK_BIT << port_no);
512 iowrite32(reg, core_base + DATA_PLANE_CTRL);
514 /* Disable all interrupts for ports and RAID controller */
515 iowrite32(~0, port_base + INT_DISABLE);
517 /* Disable all interrupts for core */
518 iowrite32(~0, core_base + CORE_INT_DISABLE);
521 /* Load the command settings into the orb registers */
522 sata_oxnas_tf_load(qc->ap, &qc->tf);
524 /* both pio and dma commands use dma */
525 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
527 iowrite32(SGDMA_CONTROL_GO, pd->sgdma_base + SGDMA_CONTROL);
531 /* enable End of command interrupt */
532 iowrite32(INT_WANT, port_base + INT_ENABLE);
533 iowrite32(COREINT_END, core_base + CORE_INT_ENABLE);
536 /* Start the command */
537 reg = ioread32(port_base + SATA_COMMAND);
538 reg &= ~SATA_OPCODE_MASK;
539 reg |= CMD_WRITE_TO_ORB_REGS;
540 iowrite32(reg , port_base + SATA_COMMAND);
547 * Will schedule the libATA error handler on the premise that there has
548 * been a hotplug event on the port specified
550 void sata_oxnas_checkforhotplug(struct ata_port *ap)
554 ata_ehi_hotplugged(&ap->link.eh_info);
559 static inline int sata_oxnas_is_host_frozen(struct ata_host *ah)
561 struct sata_oxnas_host_priv *hd = ah->private_data;
564 return hd->port_in_eh;
567 static inline u32 sata_oxnas_hostportbusy(struct ata_port *ap)
569 struct sata_oxnas_port_priv *pd = ap->private_data;
571 return ioread32(pd->port_base + SATA_COMMAND) & CMD_CORE_BUSY;
574 static inline u32 sata_oxnas_hostdmabusy(struct ata_port *ap)
576 struct sata_oxnas_port_priv *pd = ap->private_data;
578 return ioread32(pd->sgdma_base + SGDMA_STATUS) & SGDMA_BUSY;
583 * Turns on the cores clock and resets it
585 static void sata_oxnas_reset_core(struct ata_host *ah)
587 struct sata_oxnas_host_priv *host_priv = ah->private_data;
590 clk_prepare_enable(host_priv->clk);
592 reset_control_assert(host_priv->rst_sata);
593 reset_control_assert(host_priv->rst_link);
594 reset_control_assert(host_priv->rst_phy);
598 /* un-reset the PHY, then Link and Controller */
599 reset_control_deassert(host_priv->rst_phy);
602 reset_control_deassert(host_priv->rst_sata);
603 reset_control_deassert(host_priv->rst_link);
607 /* tune for sata compatability */
608 sata_oxnas_link_write(ah->ports[0], 0x60, 0x2988);
610 /* each port in turn */
611 sata_oxnas_link_write(ah->ports[0], 0x70, 0x55629);
617 * Called after an identify device command has worked out what kind of device
620 * @param port The port to configure
621 * @param pdev The hardware associated with controlling the port
623 static void sata_oxnas_dev_config(struct ata_device *pdev)
625 struct sata_oxnas_port_priv *pd = pdev->link->ap->private_data;
626 void __iomem *port_base = pd->port_base;
630 /* Set the bits to put the port into 28 or 48-bit node */
631 reg = ioread32(port_base + DRIVE_CONTROL);
633 reg |= (pdev->flags & ATA_DFLAG_LBA48) ? DR_CON_48 : DR_CON_28;
634 iowrite32(reg, port_base + DRIVE_CONTROL);
636 /* if this is an ATA-6 disk, put port into ATA-5 auto translate mode */
637 if (pdev->flags & ATA_DFLAG_LBA48) {
638 reg = ioread32(port_base + PORT_CONTROL);
640 iowrite32(reg, port_base + PORT_CONTROL);
644 * called to write a taskfile into the ORB registers
645 * @param ap hardware with the registers in
646 * @param tf taskfile to write to the registers
648 static void sata_oxnas_tf_load(struct ata_port *ap,
649 const struct ata_taskfile *tf)
658 struct sata_oxnas_port_priv *port_priv = ap->private_data;
659 void __iomem *port_base = port_priv->port_base;
660 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
662 /* wait a maximum of 10ms for the core to be idle */
664 Command_Reg = ioread32(port_base + SATA_COMMAND);
665 if (!(Command_Reg & CMD_CORE_BUSY))
669 } while (count < 200);
671 /* check if the ctl register has interrupts disabled or enabled and
672 * modify the interrupt enable registers on the ata core as required */
673 if (tf->ctl & ATA_NIEN) {
674 /* interrupts disabled */
675 u32 mask = (COREINT_END << ap->port_no);
677 iowrite32(mask, port_priv->core_base + CORE_INT_DISABLE);
678 sata_oxnas_irq_clear(ap);
680 sata_oxnas_irq_on(ap);
683 Orb2 |= (tf->command) << 24;
685 /* write 48 or 28 bit tf parameters */
687 /* set LBA bit as it's an address */
688 Orb1 |= (tf->device & ATA_LBA) << 24;
690 if (tf->flags & ATA_TFLAG_LBA48) {
691 Orb1 |= ATA_LBA << 24;
692 Orb2 |= (tf->hob_nsect) << 8;
693 Orb3 |= (tf->hob_lbal) << 24;
694 Orb4 |= (tf->hob_lbam) << 0;
695 Orb4 |= (tf->hob_lbah) << 8;
696 Orb4 |= (tf->hob_feature) << 16;
698 Orb3 |= (tf->device & 0xf) << 24;
701 /* write 28-bit lba */
702 Orb2 |= (tf->nsect) << 0;
703 Orb2 |= (tf->feature) << 16;
704 Orb3 |= (tf->lbal) << 0;
705 Orb3 |= (tf->lbam) << 8;
706 Orb3 |= (tf->lbah) << 16;
707 Orb4 |= (tf->ctl) << 24;
710 if (tf->flags & ATA_TFLAG_DEVICE)
711 Orb1 |= (tf->device) << 24;
713 ap->last_ctl = tf->ctl;
715 /* write values to registers */
716 iowrite32(Orb1, port_base + ORB1);
717 iowrite32(Orb2, port_base + ORB2);
718 iowrite32(Orb3, port_base + ORB3);
719 iowrite32(Orb4, port_base + ORB4);
723 void sata_oxnas_set_mode(struct ata_port *ap, u32 mode, u32 force)
725 struct sata_oxnas_port_priv *port_priv = ap->private_data;
726 void __iomem *core_base = port_priv->core_base;
730 unsigned int progmicrocode = 0;
731 unsigned int changeparameters = 0;
732 static u32 previous_mode = UNKNOWN_MODE;
734 /* these micro-code programs _should_ include the version word */
737 static const unsigned int jbod[] = {
738 0x07B400AC, 0x0228A280, 0x00200001, 0x00204002, 0x00224001,
739 0x00EE0009, 0x00724901, 0x01A24903, 0x00E40009, 0x00224001,
740 0x00621120, 0x0183C908, 0x00E20005, 0x00718908, 0x0198A206,
741 0x00621124, 0x0183C908, 0x00E20046, 0x00621104, 0x0183C908,
742 0x00E20015, 0x00EE009D, 0x01A3E301, 0x00E2001B, 0x0183C900,
743 0x00E2001B, 0x00210001, 0x00EE0020, 0x01A3E302, 0x00E2009D,
744 0x0183C901, 0x00E2009D, 0x00210002, 0x0235D700, 0x0208A204,
745 0x0071C908, 0x000F8207, 0x000FC207, 0x0071C920, 0x000F8507,
746 0x000FC507, 0x0228A240, 0x02269A40, 0x00094004, 0x00621104,
747 0x0180C908, 0x00E40031, 0x00621112, 0x01A3C801, 0x00E2002B,
748 0x00294000, 0x0228A220, 0x01A69ABF, 0x002F8000, 0x002FC000,
749 0x0198A204, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
750 0x0183C903, 0x00E2009D, 0x0228A220, 0x0071890C, 0x0208A206,
751 0x0198A206, 0x0001C022, 0x01B1A220, 0x0001C106, 0x00088007,
752 0x00EE009D, 0x00621104, 0x0183C908, 0x00E2004A, 0x00EE009D,
753 0x01A3C901, 0x00E20050, 0x0021E7FF, 0x0183E007, 0x00E2009D,
754 0x00EE0054, 0x0061600B, 0x0021E7FF, 0x0183C507, 0x00E2009D,
755 0x01A3E301, 0x00E2005A, 0x0183C900, 0x00E2005A, 0x00210001,
756 0x00EE005F, 0x01A3E302, 0x00E20005, 0x0183C901, 0x00E20005,
757 0x00210002, 0x0235D700, 0x0208A204, 0x000F8109, 0x000FC109,
758 0x0071C918, 0x000F8407, 0x000FC407, 0x0001C022, 0x01A1A2BF,
759 0x0001C106, 0x00088007, 0x02269A40, 0x00094004, 0x00621112,
760 0x01A3C801, 0x00E4007F, 0x00621104, 0x0180C908, 0x00E4008D,
761 0x00621128, 0x0183C908, 0x00E2006C, 0x01A3C901, 0x00E2007B,
762 0x0021E7FF, 0x0183E007, 0x00E2007F, 0x00EE006C, 0x0061600B,
763 0x0021E7FF, 0x0183C507, 0x00E4006C, 0x00621111, 0x01A3C801,
764 0x00E2007F, 0x00621110, 0x01A3C801, 0x00E20082, 0x0228A220,
765 0x00621119, 0x01A3C801, 0x00E20086, 0x0001C022, 0x01B1A220,
766 0x0001C106, 0x00088007, 0x0198A204, 0x00294000, 0x01A69ABF,
767 0x002F8000, 0x002FC000, 0x0183C903, 0x00E20005, 0x0228A220,
768 0x0071890C, 0x0208A206, 0x0198A206, 0x0001C022, 0x01B1A220,
769 0x0001C106, 0x00088007, 0x00EE009D, 0x00621128, 0x0183C908,
770 0x00E20005, 0x00621104, 0x0183C908, 0x00E200A6, 0x0062111C,
771 0x0183C908, 0x00E20005, 0x0071890C, 0x0208A206, 0x0198A206,
772 0x00718908, 0x0208A206, 0x00EE0005, ~0
775 /* Bi-Modal RAID-0/1 */
776 static const unsigned int raid[] = {
777 0x00F20145, 0x00EE20FA, 0x00EE20A7, 0x0001C009, 0x00EE0004,
778 0x00220000, 0x0001000B, 0x037003FF, 0x00700018, 0x037003FE,
779 0x037043FD, 0x00704118, 0x037043FC, 0x01A3D240, 0x00E20017,
780 0x00B3C235, 0x00E40018, 0x0093C104, 0x00E80014, 0x0093C004,
781 0x00E80017, 0x01020000, 0x00274020, 0x00EE0083, 0x0080C904,
782 0x0093C104, 0x00EA0020, 0x0093C103, 0x00EC001F, 0x00220002,
783 0x00924104, 0x0005C009, 0x00EE0058, 0x0093CF04, 0x00E80026,
784 0x00900F01, 0x00600001, 0x00910400, 0x00EE0058, 0x00601604,
785 0x01A00003, 0x00E2002C, 0x01018000, 0x00274040, 0x00EE0083,
786 0x0093CF03, 0x00EC0031, 0x00220003, 0x00924F04, 0x0005C009,
787 0x00810104, 0x00B3C235, 0x00E20037, 0x0022C000, 0x00218210,
788 0x00EE0039, 0x0022C001, 0x00218200, 0x00600401, 0x00A04901,
789 0x00604101, 0x01A0C401, 0x00E20040, 0x00216202, 0x00EE0041,
790 0x00216101, 0x02018506, 0x00EE2141, 0x00904901, 0x00E20049,
791 0x00A00401, 0x00600001, 0x02E0C301, 0x00EE2141, 0x00216303,
792 0x037003EE, 0x01A3C001, 0x00E40105, 0x00250080, 0x00204000,
793 0x002042F1, 0x0004C001, 0x00230001, 0x00100006, 0x02C18605,
794 0x00100006, 0x01A3D502, 0x00E20055, 0x00EE0053, 0x00004009,
795 0x00000004, 0x00B3C235, 0x00E40062, 0x0022C001, 0x0020C000,
796 0x00EE2141, 0x0020C001, 0x00EE2141, 0x00EE006B, 0x0022C000,
797 0x0060D207, 0x00EE2141, 0x00B3C242, 0x00E20069, 0x01A3D601,
798 0x00E2006E, 0x02E0C301, 0x00EE2141, 0x00230001, 0x00301303,
799 0x00EE007B, 0x00218210, 0x01A3C301, 0x00E20073, 0x00216202,
800 0x00EE0074, 0x00216101, 0x02018506, 0x00214000, 0x037003EE,
801 0x01A3C001, 0x00E40108, 0x00230001, 0x00100006, 0x00250080,
802 0x00204000, 0x002042F1, 0x0004C001, 0x00EE007F, 0x0024C000,
803 0x01A3D1F0, 0x00E20088, 0x00230001, 0x00300000, 0x01A3D202,
804 0x00E20085, 0x00EE00A5, 0x00B3C800, 0x00E20096, 0x00218000,
805 0x00924709, 0x0005C009, 0x00B20802, 0x00E40093, 0x037103FD,
806 0x00710418, 0x037103FC, 0x00EE0006, 0x00220000, 0x0001000F,
807 0x00EE0006, 0x00800B0C, 0x00B00001, 0x00204000, 0x00208550,
808 0x00208440, 0x002083E0, 0x00208200, 0x00208100, 0x01008000,
809 0x037083EE, 0x02008212, 0x02008216, 0x01A3C201, 0x00E400A5,
810 0x0100C000, 0x00EE20FA, 0x02800000, 0x00208000, 0x00B24C00,
811 0x00E400AD, 0x00224001, 0x00724910, 0x0005C009, 0x00B3CDC4,
812 0x00E200D5, 0x00B3CD29, 0x00E200D5, 0x00B3CD20, 0x00E200D5,
813 0x00B3CD24, 0x00E200D5, 0x00B3CDC5, 0x00E200D2, 0x00B3CD39,
814 0x00E200D2, 0x00B3CD30, 0x00E200D2, 0x00B3CD34, 0x00E200D2,
815 0x00B3CDCA, 0x00E200CF, 0x00B3CD35, 0x00E200CF, 0x00B3CDC8,
816 0x00E200CC, 0x00B3CD25, 0x00E200CC, 0x00B3CD40, 0x00E200CB,
817 0x00B3CD42, 0x00E200CB, 0x01018000, 0x00EE0083, 0x0025C000,
818 0x036083EE, 0x0000800D, 0x00EE00D8, 0x036083EE, 0x00208035,
819 0x00EE00DA, 0x036083EE, 0x00208035, 0x00EE00DA, 0x00208007,
820 0x036083EE, 0x00208025, 0x036083EF, 0x02400000, 0x01A3D208,
821 0x00E200D8, 0x0067120A, 0x0021C000, 0x0021C224, 0x00220000,
822 0x00404B1C, 0x00600105, 0x00800007, 0x0020C00E, 0x00214000,
823 0x01004000, 0x01A0411F, 0x00404E01, 0x01A3C101, 0x00E200F1,
824 0x00B20800, 0x00E400D8, 0x00220001, 0x0080490B, 0x00B04101,
825 0x0040411C, 0x00EE00E1, 0x02269A01, 0x01020000, 0x02275D80,
826 0x01A3D202, 0x00E200F4, 0x01B75D80, 0x01030000, 0x01B69A01,
827 0x00EE00D8, 0x01A3D204, 0x00E40104, 0x00224000, 0x0020C00E,
828 0x0020001E, 0x00214000, 0x01004000, 0x0212490E, 0x00214001,
829 0x01004000, 0x02400000, 0x00B3D702, 0x00E80112, 0x00EE010E,
830 0x00B3D702, 0x00E80112, 0x00B3D702, 0x00E4010E, 0x00230001,
831 0x00EE0140, 0x00200005, 0x036003EE, 0x00204001, 0x00EE0116,
832 0x00230001, 0x00100006, 0x02C18605, 0x00100006, 0x01A3D1F0,
833 0x00E40083, 0x037003EE, 0x01A3C002, 0x00E20121, 0x0020A300,
834 0x0183D102, 0x00E20124, 0x037003EE, 0x01A00005, 0x036003EE,
835 0x01A0910F, 0x00B3C20F, 0x00E2012F, 0x01A3D502, 0x00E20116,
836 0x01A3C002, 0x00E20116, 0x00B3D702, 0x00E4012C, 0x00300000,
837 0x00EE011F, 0x02C18605, 0x00100006, 0x00EE0116, 0x01A3D1F0,
838 0x00E40083, 0x037003EE, 0x01A3C004, 0x00E20088, 0x00200003,
839 0x036003EE, 0x01A3D502, 0x00E20136, 0x00230001, 0x00B3C101,
840 0x00E4012C, 0x00100006, 0x02C18605, 0x00100006, 0x00204000,
841 0x00EE0116, 0x00100006, 0x01A3D1F0, 0x00E40083, 0x01000000,
846 previous_mode = UNKNOWN_MODE;
848 if (mode == previous_mode)
851 /* decide what needs to be done using the STD in my logbook */
852 switch (previous_mode) {
853 case OXNASSATA_RAID1:
855 case OXNASSATA_RAID0:
856 changeparameters = 1;
858 case OXNASSATA_NOTRAID:
859 changeparameters = 1;
864 case OXNASSATA_RAID0:
866 case OXNASSATA_RAID1:
867 changeparameters = 1;
869 case OXNASSATA_NOTRAID:
870 changeparameters = 1;
875 case OXNASSATA_NOTRAID:
877 changeparameters = 1;
882 /* no need to reprogram everything if already in the right mode */
884 /* reset micro-code processor */
885 iowrite32(1, core_base + PROC_RESET);
888 /* select micro-code */
890 case OXNASSATA_RAID1:
891 case OXNASSATA_RAID0:
892 VPRINTK("Loading RAID micro-code\n");
893 src = (unsigned int *)&raid[1];
895 case OXNASSATA_NOTRAID:
896 VPRINTK("Loading JBOD micro-code\n");
897 src = (unsigned int *)&jbod[1];
904 /* load micro code */
905 dst = core_base + UCODE_STORE;
907 iowrite32(*src, dst);
914 if (changeparameters) {
916 /* set other mode dependent flags */
918 case OXNASSATA_RAID1:
919 /* clear JBOD mode */
920 reg = ioread32(core_base + DATA_PLANE_CTRL);
921 reg |= DPC_JBOD_UCODE;
922 reg &= ~DPC_FIS_SWCH;
923 iowrite32(reg, core_base + DATA_PLANE_CTRL);
926 /* set the hardware up for RAID-1 */
927 iowrite32(0, core_base + RAID_WP_BOT_LOW);
928 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
929 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
930 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
931 iowrite32(0, core_base + RAID_SIZE_LOW);
932 iowrite32(0, core_base + RAID_SIZE_HIGH);
935 case OXNASSATA_RAID0:
936 /* clear JBOD mode */
937 reg = ioread32(core_base + DATA_PLANE_CTRL);
938 reg |= DPC_JBOD_UCODE;
939 reg &= ~DPC_FIS_SWCH;
940 iowrite32(reg, core_base + DATA_PLANE_CTRL);
943 /* set the hardware up for RAID-1 */
944 iowrite32(0, core_base + RAID_WP_BOT_LOW);
945 iowrite32(0, core_base + RAID_WP_BOT_HIGH);
946 iowrite32(0xffffffff, core_base + RAID_WP_TOP_LOW);
947 iowrite32(0x7fffffff, core_base + RAID_WP_TOP_HIGH);
948 iowrite32(0xffffffff, core_base + RAID_SIZE_LOW);
949 iowrite32(0x7fffffff, core_base + RAID_SIZE_HIGH);
952 case OXNASSATA_NOTRAID:
953 /* enable jbod mode */
954 reg = ioread32(core_base + DATA_PLANE_CTRL);
955 reg &= ~DPC_JBOD_UCODE;
957 iowrite32(reg, core_base + DATA_PLANE_CTRL);
960 /* start micro-code processor*/
961 iowrite32(1, core_base + PROC_START);
968 previous_mode = mode;
972 * sends a sync-escape if there is a link present
974 static inline void sata_oxnas_send_sync_escape(struct ata_port *ap)
976 struct sata_oxnas_port_priv *pd = ap->private_data;
979 /* read the SSTATUS register and only send a sync escape if there is a
981 if ((sata_oxnas_link_read(ap, 0x20) & 3) == 3) {
982 reg = ioread32(pd->port_base + SATA_COMMAND);
983 reg &= ~SATA_OPCODE_MASK;
984 reg |= CMD_SYNC_ESCAPE;
985 iowrite32(reg, pd->port_base + SATA_COMMAND);
990 static inline void sata_oxnas_clear_CS_error(u32 *base)
994 reg = ioread32(base + SATA_CONTROL);
995 reg &= SATA_CTL_ERR_MASK;
996 iowrite32(reg, base + SATA_CONTROL);
1000 * Clears the error caused by the core's registers being accessed when the
1003 static inline void sata_oxnas_clear_reg_access_error(u32 *base)
1007 reg = ioread32(base + INT_STATUS);
1010 if (reg & INT_REG_ACCESS_ERR) {
1011 printk(KERN_INFO "clearing register access error\n");
1012 iowrite32(INT_REG_ACCESS_ERR, base + INT_STATUS);
1014 if (reg & INT_REG_ACCESS_ERR)
1015 printk(KERN_INFO "register access error didn't clear\n");
1019 * Clean up all the state machines in the sata core.
1020 * @return post cleanup action required
1022 static int sata_oxnas_cleanup(struct ata_host *ah)
1024 int actions_required = 0;
1026 printk(KERN_INFO "ox820sata: reseting SATA core\n");
1028 /* core not recovering, reset it */
1030 sata_oxnas_reset_core(ah);
1032 actions_required |= OXNAS_SATA_REINIT;
1033 /* Perform any SATA core re-initialisation after reset post reset init
1034 * needs to be called for both ports as there's one reset for both
1037 sata_oxnas_post_reset_init(ah->ports[0]);
1039 return actions_required;
1042 void sata_oxnas_freeze_host(struct ata_port *ap)
1044 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1047 hd->port_in_eh |= BIT(ap->port_no);
1051 void sata_oxnas_thaw_host(struct ata_port *ap)
1053 struct sata_oxnas_host_priv *hd = ap->host->private_data;
1056 hd->port_in_eh &= ~BIT(ap->port_no);
1060 static void sata_oxnas_post_internal_cmd(struct ata_queued_cmd *qc)
1063 /* If the core is busy here, make it idle */
1064 if (qc->flags & ATA_QCFLAG_FAILED)
1065 sata_oxnas_cleanup(qc->ap->host);
1070 * turn on the interrupts
1072 * @param ap Hardware with the registers in
1074 static void sata_oxnas_irq_on(struct ata_port *ap)
1076 struct sata_oxnas_port_priv *pd = ap->private_data;
1077 u32 mask = (COREINT_END << ap->port_no);
1079 /* Clear pending interrupts */
1080 iowrite32(~0, pd->port_base + INT_CLEAR);
1081 iowrite32(mask, pd->core_base + CORE_INT_STATUS);
1084 /* enable End of command interrupt */
1085 iowrite32(INT_WANT, pd->port_base + INT_ENABLE);
1086 iowrite32(mask, pd->core_base + CORE_INT_ENABLE);
1090 /** @return true if the port has a cable connected */
1091 int sata_oxnas_check_link(struct ata_port *ap)
1095 sata_oxnas_scr_read_port(ap, SCR_STATUS, ®);
1096 /* Check for the cable present indicated by SCR status bit-0 set */
1101 * ata_std_postreset - standard postreset callback
1102 * @link: the target ata_link
1103 * @classes: classes of attached devices
1105 * This function is invoked after a successful reset. Note that
1106 * the device might have been reset more than once using
1107 * different reset methods before postreset is invoked.
1110 * Kernel thread context (may sleep)
1112 static void sata_oxnas_postreset(struct ata_link *link, unsigned int *classes)
1114 struct ata_port *ap = link->ap;
1119 ata_std_postreset(link, classes);
1121 /* turn on phy error detection by removing the masks */
1122 sata_oxnas_link_write(ap , 0x0c, 0x30003);
1124 /* bail out if no device is present */
1125 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
1126 DPRINTK("EXIT, no device\n");
1130 /* go through all the devices and configure them */
1131 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1132 if (ap->link.device[dev].class == ATA_DEV_ATA)
1133 sata_oxnas_dev_config(&(ap->link.device[dev]));
1140 * Called to read the hardware registers / DMA buffers, to
1141 * obtain the current set of taskfile register values.
1142 * @param ap hardware with the registers in
1143 * @param tf taskfile to read the registers into
1145 static void sata_oxnas_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
1147 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1148 void __iomem *port_base = port_priv->port_base;
1149 /* read the orb registers */
1150 u32 Orb1 = ioread32(port_base + ORB1);
1151 u32 Orb2 = ioread32(port_base + ORB2);
1152 u32 Orb3 = ioread32(port_base + ORB3);
1153 u32 Orb4 = ioread32(port_base + ORB4);
1155 /* read common 28/48 bit tf parameters */
1156 tf->device = (Orb1 >> 24);
1157 tf->nsect = (Orb2 >> 0);
1158 tf->feature = (Orb2 >> 16);
1159 tf->command = sata_oxnas_check_status(ap);
1161 /* read 48 or 28 bit tf parameters */
1162 if (tf->flags & ATA_TFLAG_LBA48) {
1163 tf->hob_nsect = (Orb2 >> 8);
1164 tf->lbal = (Orb3 >> 0);
1165 tf->lbam = (Orb3 >> 8);
1166 tf->lbah = (Orb3 >> 16);
1167 tf->hob_lbal = (Orb3 >> 24);
1168 tf->hob_lbam = (Orb4 >> 0);
1169 tf->hob_lbah = (Orb4 >> 8);
1170 /* feature ext and control are write only */
1172 /* read 28-bit lba */
1173 tf->lbal = (Orb3 >> 0);
1174 tf->lbam = (Orb3 >> 8);
1175 tf->lbah = (Orb3 >> 16);
1180 * Read a result task-file from the sata core registers.
1182 static bool sata_oxnas_qc_fill_rtf(struct ata_queued_cmd *qc)
1184 /* Read the most recently received FIS from the SATA core ORB registers
1185 and convert to an ATA taskfile */
1186 sata_oxnas_tf_read(qc->ap, &qc->result_tf);
1191 * Reads the Status ATA shadow register from hardware.
1193 * @return The status register
1195 static u8 sata_oxnas_check_status(struct ata_port *ap)
1199 struct sata_oxnas_port_priv *port_priv = ap->private_data;
1200 void __iomem *port_base = port_priv->port_base;
1202 /* read byte 3 of Orb2 register */
1203 status = ioread32(port_base + ORB2) >> 24;
1205 /* check for the drive going missing indicated by SCR status bits
1207 sata_oxnas_scr_read_port(ap, SCR_STATUS, &Reg);
1218 * Prepare as much as possible for a command without involving anything that is
1219 * shared between ports.
1221 static void sata_oxnas_qc_prep(struct ata_queued_cmd *qc)
1223 struct sata_oxnas_port_priv *pd;
1224 int port_no = qc->ap->port_no;
1226 /* if the port's not connected, complete now with an error */
1228 if (!sata_oxnas_check_link(qc->ap)) {
1229 printk(KERN_ERR "port %d not connected completing with error\n",
1231 qc->err_mask |= AC_ERR_ATA_BUS;
1232 ata_qc_complete(qc);
1235 /* both pio and dma commands use dma */
1236 if (ata_is_dma(qc->tf.protocol) || ata_is_pio(qc->tf.protocol)) {
1237 /* program the scatterlist into the prd table */
1238 ata_bmdma_qc_prep(qc);
1240 /* point the sgdma controller at the dma request structure */
1241 pd = qc->ap->private_data;
1243 iowrite32(pd->sgdma_request_pa,
1244 pd->sgdma_base + SGDMA_REQUESTPTR);
1246 /* setup the request table */
1248 pd->sgdma_request->control =
1249 (qc->dma_dir == DMA_FROM_DEVICE) ?
1250 SGDMA_REQCTL0IN : SGDMA_REQCTL0OUT;
1252 pd->sgdma_request->control =
1253 (qc->dma_dir == DMA_FROM_DEVICE) ?
1254 SGDMA_REQCTL1IN : SGDMA_REQCTL1OUT;
1256 pd->sgdma_request->qualifier = SGDMA_REQQUAL;
1257 pd->sgdma_request->src_pa = qc->ap->bmdma_prd_dma;
1258 pd->sgdma_request->dst_pa = qc->ap->bmdma_prd_dma;
1261 /* tell it to wait */
1262 iowrite32(SGDMA_CONTROL_NOGO, pd->sgdma_base + SGDMA_CONTROL);
1266 static int sata_oxnas_port_start(struct ata_port *ap)
1268 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1269 struct device *dev = ap->host->dev;
1270 struct sata_oxnas_port_priv *pp;
1276 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
1280 pp->port_base = host_priv->port_base[ap->port_no];
1281 pp->sgdma_base = host_priv->sgdma_base[ap->port_no];
1282 pp->core_base = host_priv->core_base;
1285 if (host_priv->dma_size >= SATA_OXNAS_DMA_SIZE * SATA_OXNAS_MAX_PORTS) {
1286 mem_dma = host_priv->dma_base +
1287 ap->port_no * SATA_OXNAS_DMA_SIZE;
1288 mem = ioremap(mem_dma, SATA_OXNAS_DMA_SIZE);
1291 mem = dma_alloc_coherent(dev, SATA_OXNAS_DMA_SIZE, &mem_dma,
1297 pp->sgdma_request_pa = mem_dma;
1298 pp->sgdma_request = mem;
1299 ap->bmdma_prd_dma = mem_dma + sizeof(struct sgdma_request);
1300 ap->bmdma_prd = mem + sizeof(struct sgdma_request);
1302 ap->private_data = pp;
1304 sata_oxnas_post_reset_init(ap);
1314 static void sata_oxnas_port_stop(struct ata_port *ap)
1316 struct device *dev = ap->host->dev;
1317 struct sata_oxnas_port_priv *pp = ap->private_data;
1318 struct sata_oxnas_host_priv *host_priv = ap->host->private_data;
1321 ap->private_data = NULL;
1322 if (host_priv->dma_size) {
1323 iounmap(pp->sgdma_request);
1325 dma_free_coherent(dev, SATA_OXNAS_DMA_SIZE,
1326 pp->sgdma_request, pp->sgdma_request_pa);
1332 static void sata_oxnas_post_reset_init(struct ata_port *ap)
1334 struct sata_oxnas_port_priv *pd = ap->private_data;
1336 int no_microcode = 0;
1341 sata_oxnas_set_mode(ap, UNKNOWN_MODE, 1);
1342 reg = readl(pd->core_base + DEVICE_CONTROL);
1343 reg |= DEVICE_CONTROL_ATA_ERR_OVERRIDE;
1344 writel(reg, pd->core_base + DEVICE_CONTROL);
1347 sata_oxnas_set_mode(ap, OXNASSATA_NOTRAID, 1);
1348 /* Turn the work around off as it may have been left on by any
1349 * HW-RAID code that we've been working with */
1350 writel(0x0, pd->core_base + PORT_ERROR_MASK);
1352 /* turn on phy error detection by removing the masks */
1353 sata_oxnas_link_write(ap, 0x0C, 0x30003);
1355 /* enable hotplug event detection */
1356 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1357 sata_oxnas_scr_write_port(ap, SERROR_IRQ_MASK, 0x03feffff);
1358 sata_oxnas_scr_write_port(ap, SCR_ACTIVE, ~0 & ~(1 << 26) & ~(1 << 16));
1360 /* enable interrupts for ports */
1361 sata_oxnas_irq_on(ap);
1363 /* go through all the devices and configure them */
1364 for (dev = 0; dev < ATA_MAX_DEVICES; ++dev) {
1365 if (ap->link.device[dev].class == ATA_DEV_ATA) {
1366 sata_std_hardreset(&ap->link, NULL, jiffies + HZ);
1367 sata_oxnas_dev_config(&(ap->link.device[dev]));
1371 /* clean up any remaining errors */
1372 sata_oxnas_scr_write_port(ap, SCR_ERROR, ~0);
1377 * host_stop() is called when the rmmod or hot unplug process begins. The
1378 * hook must stop all hardware interrupts, DMA engines, etc.
1380 * @param ap hardware with the registers in
1382 static void sata_oxnas_host_stop(struct ata_host *host_set)
1388 #define ERROR_HW_ACQUIRE_TIMEOUT_JIFFIES (10 * HZ)
1389 static void sata_oxnas_error_handler(struct ata_port *ap)
1391 DPRINTK("Enter port_no %d\n", ap->port_no);
1392 sata_oxnas_freeze_host(ap);
1394 /* If the core is busy here, make it idle */
1395 sata_oxnas_cleanup(ap->host);
1397 ata_std_error_handler(ap);
1399 sata_oxnas_thaw_host(ap);
1402 static int sata_oxnas_softreset(struct ata_link *link, unsigned int *class,
1403 unsigned long deadline)
1405 struct ata_port *ap = link->ap;
1406 struct sata_oxnas_port_priv *pd = ap->private_data;
1407 void __iomem *port_base = pd->port_base;
1410 struct ata_taskfile tf;
1415 port_base = pd->port_base;
1417 if (ata_link_offline(link)) {
1418 DPRINTK("PHY reports no device\n");
1419 *class = ATA_DEV_NONE;
1423 /* write value to register */
1424 iowrite32((ap->ctl) << 24, port_base + ORB4);
1426 /* command the core to send a control FIS */
1427 Command_Reg = ioread32(port_base + SATA_COMMAND);
1428 Command_Reg &= ~SATA_OPCODE_MASK;
1429 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1430 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1431 udelay(20); /* FIXME: flush */
1433 /* write value to register */
1434 iowrite32((ap->ctl | ATA_SRST) << 24, port_base + ORB4);
1436 /* command the core to send a control FIS */
1437 Command_Reg &= ~SATA_OPCODE_MASK;
1438 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1439 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1440 udelay(20); /* FIXME: flush */
1442 /* write value to register */
1443 iowrite32((ap->ctl) << 24, port_base + ORB4);
1445 /* command the core to send a control FIS */
1446 Command_Reg &= ~SATA_OPCODE_MASK;
1447 Command_Reg |= CMD_WRITE_TO_ORB_REGS_NO_COMMAND;
1448 iowrite32(Command_Reg, port_base + SATA_COMMAND);
1452 rc = ata_sff_wait_ready(link, deadline);
1454 /* if link is occupied, -ENODEV too is an error */
1455 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
1456 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
1460 /* determine by signature whether we have ATA or ATAPI devices */
1461 sata_oxnas_tf_read(ap, &tf);
1462 *class = ata_dev_classify(&tf);
1464 if (*class == ATA_DEV_UNKNOWN)
1465 *class = ATA_DEV_NONE;
1468 DPRINTK("EXIT, class=%u\n", *class);
1473 int sata_oxnas_init_controller(struct ata_host *host)
1481 * This code is a work around for a DMA hardware bug that will repeat the
1482 * penultimate 8-bytes on some reads. This code will check that the amount
1483 * of data transferred is a multiple of 512 bytes, if not the in it will
1484 * fetch the correct data from a buffer in the SATA core and copy it into
1487 * @param port SATA port to check and if necessary, correct.
1489 static int ox820sata_bug_6320_workaround(struct ata_port *ap)
1491 struct sata_oxnas_port_priv *pd = ap->private_data;
1492 void __iomem *core_base = pd->core_base;
1494 int quads_transferred;
1496 int sector_quads_remaining;
1497 int bug_present = 0;
1499 /* Only want to apply fix to reads */
1500 is_read = !(readl(core_base + DM_DBG1) & (ap->port_no ?
1501 BIT(CORE_PORT1_DATA_DIR_BIT) :
1502 BIT(CORE_PORT0_DATA_DIR_BIT)));
1504 /* Check for an incomplete transfer, i.e. not a multiple of 512 bytes
1505 transferred (datacount_port register counts quads transferred) */
1507 readl(core_base + (ap->port_no ?
1508 DATACOUNT_PORT1 : DATACOUNT_PORT0));
1510 remainder = quads_transferred & 0x7f;
1511 sector_quads_remaining = remainder ? (0x80 - remainder) : 0;
1513 if (is_read && (sector_quads_remaining == 2)) {
1515 } else if (sector_quads_remaining) {
1517 printk(KERN_WARNING "SATA read fixup cannot deal with" \
1518 " %d quads remaining\n",
1519 sector_quads_remaining);
1521 printk(KERN_WARNING "SATA write fixup of %d quads" \
1522 " remaining not supported\n",
1523 sector_quads_remaining);
1530 /* This port done an interrupt */
1531 static void sata_oxnas_port_irq(struct ata_port *ap, int force_error)
1533 struct ata_queued_cmd *qc;
1534 struct sata_oxnas_port_priv *pd = ap->private_data;
1535 void __iomem *port_base = pd->port_base;
1538 unsigned long flags = 0;
1540 /* DPRINTK("ENTER irqstatus %x\n", ioread32(port_base + INT_STATUS)); */
1542 if (ap->qc_active & (1 << ATA_TAG_INTERNAL)) {
1543 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1544 DPRINTK("completing non-ncq cmd\n");
1547 ata_qc_complete(qc);
1553 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1556 /* record the port's interrupt */
1557 int_status = ioread32(port_base + INT_STATUS);
1559 /* If there's no command associated with this IRQ, ignore it. We may get
1560 * spurious interrupts when cleaning-up after a failed command, ignore
1563 /* get the status before any error cleanup */
1564 qc->err_mask = ac_err_mask(sata_oxnas_check_status(ap));
1566 /* Pretend there has been a link error */
1567 qc->err_mask |= AC_ERR_ATA_BUS;
1568 DPRINTK(" ####force error####\n");
1570 /* tell libata we're done */
1571 local_irq_save(flags);
1572 sata_oxnas_irq_clear(ap);
1573 local_irq_restore(flags);
1574 ata_qc_complete(qc);
1576 VPRINTK("Ignoring interrupt, can't find the command tag=" \
1577 "%d %08x\n", ap->link.active_tag, ap->qc_active);
1580 /* maybe a hotplug event */
1581 if (unlikely(int_status & INT_LINK_SERROR)) {
1584 sata_oxnas_scr_read_port(ap, SCR_ERROR, &serror);
1585 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
1586 ata_ehi_hotplugged(&ap->link.eh_info);
1587 ata_port_freeze(ap);
1593 * irq_handler is the interrupt handling routine registered with the system,
1596 static irqreturn_t sata_oxnas_interrupt(int irq, void *dev_instance)
1598 struct ata_host *ah = dev_instance;
1599 struct sata_oxnas_host_priv *hd = ah->private_data;
1600 void __iomem *core_base = hd->core_base;
1603 irqreturn_t ret = IRQ_NONE;
1608 /* loop until there are no more interrupts */
1609 while ((int_status = ioread32(core_base + CORE_INT_STATUS)) &
1612 /* clear any interrupt */
1613 iowrite32(int_status, core_base + CORE_INT_CLEAR);
1615 /* Only need this workaround for single disk systems as dual
1616 * disk will use uCode which prevents this read underrun problem
1618 * All single disk systems will use port 0 */
1620 for (port_no = 0; port_no < SATA_OXNAS_MAX_PORTS; ++port_no) {
1621 /* check the raw end of command interrupt to see if the
1623 mask = (CORERAW_HOST << port_no);
1624 if (int_status & mask) {
1625 /* this port had an interrupt, clear it */
1626 iowrite32(mask, core_base + CORE_INT_CLEAR);
1627 bug_present = ox820sata_bug_6320_workaround(
1628 ah->ports[port_no]);
1629 sata_oxnas_port_irq(ah->ports[port_no],
1640 * scsi mid-layer and libata interface structures
1642 static struct scsi_host_template sata_oxnas_sht = {
1643 ATA_NCQ_SHT("sata_oxnas"),
1644 .can_queue = SATA_OXNAS_QUEUE_DEPTH,
1645 .sg_tablesize = SATA_OXNAS_MAX_PRD,
1646 .dma_boundary = ATA_DMA_BOUNDARY,
1647 .unchecked_isa_dma = 0,
1651 static struct ata_port_operations sata_oxnas_ops = {
1652 .inherits = &sata_port_ops,
1653 .qc_prep = sata_oxnas_qc_prep,
1654 .qc_issue = sata_oxnas_qc_issue,
1655 .qc_fill_rtf = sata_oxnas_qc_fill_rtf,
1657 .scr_read = sata_oxnas_scr_read,
1658 .scr_write = sata_oxnas_scr_write,
1660 /* .freeze = sata_oxnas_freeze, */
1661 /* .thaw = sata_oxnas_thaw, */
1662 .softreset = sata_oxnas_softreset,
1663 /* .hardreset = sata_oxnas_hardreset, */
1664 .postreset = sata_oxnas_postreset,
1665 .error_handler = sata_oxnas_error_handler,
1666 .post_internal_cmd = sata_oxnas_post_internal_cmd,
1668 .port_start = sata_oxnas_port_start,
1669 .port_stop = sata_oxnas_port_stop,
1671 .host_stop = sata_oxnas_host_stop,
1672 /* .pmp_attach = sata_oxnas_pmp_attach, */
1673 /* .pmp_detach = sata_oxnas_pmp_detach, */
1674 .sff_check_status = sata_oxnas_check_status,
1677 static const struct ata_port_info sata_oxnas_port_info = {
1678 .flags = SATA_OXNAS_HOST_FLAGS,
1679 .pio_mask = ATA_PIO4,
1680 .udma_mask = ATA_UDMA6,
1681 .port_ops = &sata_oxnas_ops,
1684 static int sata_oxnas_probe(struct platform_device *ofdev)
1686 int retval = -ENXIO;
1687 void __iomem *port_base = NULL;
1688 void __iomem *sgdma_base = NULL;
1689 void __iomem *core_base = NULL;
1690 void __iomem *phy_base = NULL;
1691 struct reset_control *rstc;
1693 struct resource res = {};
1694 struct sata_oxnas_host_priv *host_priv = NULL;
1696 struct ata_host *host = NULL;
1697 struct clk *clk = NULL;
1699 const struct ata_port_info *ppi[] = { &sata_oxnas_port_info, NULL };
1701 port_base = of_iomap(ofdev->dev.of_node, 0);
1703 goto error_exit_with_cleanup;
1705 sgdma_base = of_iomap(ofdev->dev.of_node, 1);
1707 goto error_exit_with_cleanup;
1709 core_base = of_iomap(ofdev->dev.of_node, 2);
1711 goto error_exit_with_cleanup;
1713 phy_base = of_iomap(ofdev->dev.of_node, 3);
1715 goto error_exit_with_cleanup;
1717 host_priv = devm_kzalloc(&ofdev->dev,
1718 sizeof(struct sata_oxnas_host_priv),
1721 goto error_exit_with_cleanup;
1723 host_priv->port_base[0] = port_base;
1724 host_priv->sgdma_base[0] = sgdma_base;
1725 host_priv->core_base = core_base;
1726 host_priv->phy_base = phy_base;
1728 if (!of_address_to_resource(ofdev->dev.of_node, 4, &res)) {
1729 host_priv->dma_base = res.start;
1730 host_priv->dma_size = resource_size(&res);
1733 irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1735 dev_err(&ofdev->dev, "invalid irq from platform\n");
1736 goto error_exit_with_cleanup;
1738 host_priv->irq = irq;
1740 clk = of_clk_get(ofdev->dev.of_node, 0);
1742 retval = PTR_ERR(clk);
1744 goto error_exit_with_cleanup;
1746 host_priv->clk = clk;
1748 rstc = devm_reset_control_get(&ofdev->dev, "sata");
1750 retval = PTR_ERR(rstc);
1751 goto error_exit_with_cleanup;
1753 host_priv->rst_sata = rstc;
1755 rstc = devm_reset_control_get(&ofdev->dev, "link");
1757 retval = PTR_ERR(rstc);
1758 goto error_exit_with_cleanup;
1760 host_priv->rst_link = rstc;
1762 rstc = devm_reset_control_get(&ofdev->dev, "phy");
1764 retval = PTR_ERR(rstc);
1765 goto error_exit_with_cleanup;
1767 host_priv->rst_phy = rstc;
1769 /* allocate host structure */
1770 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_OXNAS_MAX_PORTS);
1773 goto error_exit_with_cleanup;
1775 host->private_data = host_priv;
1776 host->iomap = port_base;
1778 /* initialize host controller */
1779 retval = sata_oxnas_init_controller(host);
1781 goto error_exit_with_cleanup;
1784 * Now, register with libATA core, this will also initiate the
1785 * device discovery process, invoking our port_start() handler &
1786 * error_handler() to execute a dummy softreset EH session
1788 ata_host_activate(host, irq, sata_oxnas_interrupt, SATA_OXNAS_IRQ_FLAG,
1793 error_exit_with_cleanup:
1795 irq_dispose_mapping(host_priv->irq);
1799 ata_host_detach(host);
1803 iounmap(sgdma_base);
1812 static int sata_oxnas_remove(struct platform_device *ofdev)
1814 struct ata_host *host = dev_get_drvdata(&ofdev->dev);
1815 struct sata_oxnas_host_priv *host_priv = host->private_data;
1817 ata_host_detach(host);
1819 irq_dispose_mapping(host_priv->irq);
1820 iounmap(host_priv->port_base);
1821 iounmap(host_priv->sgdma_base);
1822 iounmap(host_priv->core_base);
1824 /* reset Controller, Link and PHY */
1825 reset_control_assert(host_priv->rst_sata);
1826 reset_control_assert(host_priv->rst_link);
1827 reset_control_assert(host_priv->rst_phy);
1829 /* Disable the clock to the SATA block */
1830 clk_disable_unprepare(host_priv->clk);
1831 clk_put(host_priv->clk);
1837 static int sata_oxnas_suspend(struct platform_device *op, pm_message_t state)
1839 struct ata_host *host = dev_get_drvdata(&op->dev);
1841 return ata_host_suspend(host, state);
1844 static int sata_oxnas_resume(struct platform_device *op)
1846 struct ata_host *host = dev_get_drvdata(&op->dev);
1849 ret = sata_oxnas_init_controller(host);
1851 dev_err(&op->dev, "Error initializing hardware\n");
1854 ata_host_resume(host);
1861 static struct of_device_id oxnas_sata_match[] = {
1863 .compatible = "plxtech,nas782x-sata",
1868 MODULE_DEVICE_TABLE(of, oxnas_sata_match);
1870 static struct platform_driver oxnas_sata_driver = {
1872 .name = "oxnas-sata",
1873 .owner = THIS_MODULE,
1874 .of_match_table = oxnas_sata_match,
1876 .probe = sata_oxnas_probe,
1877 .remove = sata_oxnas_remove,
1879 .suspend = sata_oxnas_suspend,
1880 .resume = sata_oxnas_resume,
1884 module_platform_driver(oxnas_sata_driver);
1886 MODULE_LICENSE("GPL");
1887 MODULE_VERSION("1.0");
1888 MODULE_AUTHOR("Oxford Semiconductor Ltd.");
1889 MODULE_DESCRIPTION("934 SATA core controler");