1 /* This header file defines the registers and suspend/resume
2 structures for the Geode GX and LX. The lxfb driver defines
3 _GEODELX_ before including this file, which will unlock the
4 extra registers that are only valid for LX.
12 #define GX_VP_MSR_PAD_SELECT 0xC0002011
13 #define LX_VP_MSR_PAD_SELECT 0x48000011
15 #define GEODE_MSR_GLCP_DOTPLL 0x4c000015
17 #define GLCP_DOTPLL_RESET (1 << 0)
18 #define GLCP_DOTPLL_BYPASS (1 << 15)
19 #define GLCP_DOTPLL_HALFPIX (1 << 24)
20 #define GLCP_DOTPLL_LOCK (1 << 25)
23 #define VP_FP_START 0x400
28 #define GP_REG_SIZE 0x7C
29 #define DC_REG_SIZE 0xF0
30 #define VP_REG_SIZE 0x158
31 #define FP_REG_SIZE 0x70
35 #define GP_REG_SIZE 0x50
36 #define DC_REG_SIZE 0x90
37 #define VP_REG_SIZE 0x138
38 #define FP_REG_SIZE 0x70
42 #define DC_PAL_SIZE 0x105
59 unsigned char b[GP_REG_SIZE];
61 u32 dst_offset; /* 0x00 */
62 u32 src_offset; /* 0x04 */
63 u32 stride; /* 0x08 */
64 u32 wid_height; /* 0x0C */
65 u32 src_color_fg; /* 0x10 */
66 u32 src_color_bg; /* 0x14 */
67 u32 pat_color_0; /* 0x18 */
68 u32 pat_color_1; /* 0x1C */
69 u32 pat_color_2; /* 0x20 */
70 u32 pat_color_3; /* 0x24 */
71 u32 pat_color_4; /* 0x28 */
72 u32 pat_color_5; /* 0x2C */
73 u32 pat_data_0; /* 0x30 */
74 u32 pat_data_1; /* 0x34 */
75 u32 raster_mode; /* 0x38 */
76 u32 vector_mode; /* 0x3C */
77 u32 blt_mode; /* 0x40 */
78 u32 blit_status; /* 0x4C */
79 u32 hst_src; /* 0x48 */
80 u32 base_offset; /* 0x4C */
83 u32 cmd_top; /* 0x50 */
84 u32 cmd_bot; /* 0x54 */
85 u32 cmd_read; /* 0x58 */
86 u32 cmd_write; /* 0x5C */
87 u32 ch3_offset; /* 0x60 */
88 u32 ch3_mode_str; /* 0x64 */
89 u32 ch3_width; /* 0x68 */
90 u32 ch3_hsrc; /* 0x6C */
91 u32 lut_index; /* 0x70 */
92 u32 lut_data; /* 0x74 */
93 u32 int_cntrl; /* 0x78 */
99 unsigned char b[DC_REG_SIZE];
102 u32 unlock; /* 0x00 */
106 u32 fb_st_offset; /* 0x10 */
107 u32 cb_st_offset; /* 0x14 */
108 u32 curs_st_offset; /* 0x18 */
109 u32 icon_st_offset; /* 0x1C */
110 u32 vid_y_st_offset; /* 0x20 */
111 u32 vid_u_st_offset; /* 0x24 */
112 u32 vid_v_st_offset; /* 0x28 */
113 u32 dctop; /* 0x2c */
114 u32 line_size; /* 0x30 */
115 u32 gfx_pitch; /* 0x34 */
116 u32 vid_yuv_pitch; /* 0x38 */
117 u32 rsvd2; /* 0x3C */
118 u32 h_active_timing; /* 0x40 */
119 u32 h_blank_timing; /* 0x44 */
120 u32 h_sync_timing; /* 0x48 */
121 u32 rsvd3; /* 0x4C */
122 u32 v_active_timing; /* 0x50 */
123 u32 v_blank_timing; /* 0x54 */
124 u32 v_sync_timing; /* 0x58 */
125 u32 fbactive; /* 0x5C */
126 u32 dc_cursor_x; /* 0x60 */
127 u32 dc_cursor_y; /* 0x64 */
128 u32 dc_icon_x; /* 0x68 */
129 u32 dc_line_cnt; /* 0x6C */
130 u32 rsvd5; /* 0x70 - palette address */
131 u32 rsvd6; /* 0x74 - palette data */
132 u32 dfifo_diag; /* 0x78 */
133 u32 cfifo_diag; /* 0x7C */
134 u32 dc_vid_ds_delta; /* 0x80 */
135 u32 gliu0_mem_offset; /* 0x84 */
136 u32 dv_ctl; /* 0x88 - added by LX */
137 u32 dv_acc; /* 0x8C */
157 u32 vid_even_y_st_offset; /* 0xD8 */
158 u32 vid_even_u_st_offset; /* 0xDC */
159 u32 vid_even_v_st_offset; /* 0xE0 */
160 u32 v_active_even_timing; /* 0xE4 */
161 u32 v_blank_even_timing; /* 0xE8 */
162 u32 v_sync_even_timing; /* 0xEC */
168 unsigned char b[VP_REG_SIZE];
178 u64 rsvd1; /* 0x38 - Gamma address*/
179 u64 rsvd2; /* 0x40 - Gamma data*/
180 u64 rsvd3; /* 0x48 */
183 u64 rsvd4[3]; /* 0x60-0x70 */
187 u64 crc32; /* 0x90 */
210 u64 a1ye; /* 0x140 */
211 u32 a2ye; /* 0x148 */
212 u32 a3ye; /* 0x150 */
218 unsigned char b[FP_REG_SIZE];
225 u64 blfsr; /* 0x420 */
226 u64 rlfsr; /* 0x428 */
229 u64 rsvd; /* 0x440 */
234 u64 crc32; /* 0x468 */
238 u32 pal[DC_PAL_SIZE];